Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 3 | * copy of this software and associated documentation files (the "Software"), |
| 4 | * to deal in the Software without restriction, including without limitation |
| 5 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 6 | * and/or sell copies of the Software, and to permit persons to whom the |
| 7 | * Software is furnished to do so, subject to the following conditions: |
| 8 | * |
| 9 | * The above copyright notice and this permission notice shall be included in |
| 10 | * all copies or substantial portions of the Software. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 13 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 15 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 16 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 17 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 18 | * OTHER DEALINGS IN THE SOFTWARE. |
| 19 | * |
| 20 | * Authors: Rafał Miłecki <zajec5@gmail.com> |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 21 | * Alex Deucher <alexdeucher@gmail.com> |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 22 | */ |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 23 | #include <drm/drmP.h> |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 24 | #include "radeon.h" |
Dave Airlie | f735261 | 2010-02-18 15:58:36 +1000 | [diff] [blame] | 25 | #include "avivod.h" |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 26 | #include "atom.h" |
Oleg Chernovskiy | 9973670 | 2014-12-08 00:10:45 +0300 | [diff] [blame] | 27 | #include "r600_dpm.h" |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 28 | #include <linux/power_supply.h> |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 29 | #include <linux/hwmon.h> |
| 30 | #include <linux/hwmon-sysfs.h> |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 31 | |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 32 | #define RADEON_IDLE_LOOP_MS 100 |
| 33 | #define RADEON_RECLOCK_DELAY_MS 200 |
Rafał Miłecki | 73a6d3f | 2010-01-08 00:22:47 +0100 | [diff] [blame] | 34 | #define RADEON_WAIT_VBLANK_TIMEOUT 200 |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 35 | |
Rafał Miłecki | f712d0c | 2010-06-07 18:29:44 -0400 | [diff] [blame] | 36 | static const char *radeon_pm_state_type_name[5] = { |
Alex Deucher | eb2c27a | 2012-10-01 18:28:09 -0400 | [diff] [blame] | 37 | "", |
Rafał Miłecki | f712d0c | 2010-06-07 18:29:44 -0400 | [diff] [blame] | 38 | "Powersave", |
| 39 | "Battery", |
| 40 | "Balanced", |
| 41 | "Performance", |
| 42 | }; |
| 43 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 44 | static void radeon_dynpm_idle_work_handler(struct work_struct *work); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 45 | static int radeon_debugfs_pm_init(struct radeon_device *rdev); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 46 | static bool radeon_pm_in_vbl(struct radeon_device *rdev); |
| 47 | static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); |
| 48 | static void radeon_pm_update_profile(struct radeon_device *rdev); |
| 49 | static void radeon_pm_set_clocks(struct radeon_device *rdev); |
| 50 | |
Alex Deucher | a4c9e2e | 2011-11-04 10:09:41 -0400 | [diff] [blame] | 51 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
| 52 | enum radeon_pm_state_type ps_type, |
| 53 | int instance) |
| 54 | { |
| 55 | int i; |
| 56 | int found_instance = -1; |
| 57 | |
| 58 | for (i = 0; i < rdev->pm.num_power_states; i++) { |
| 59 | if (rdev->pm.power_state[i].type == ps_type) { |
| 60 | found_instance++; |
| 61 | if (found_instance == instance) |
| 62 | return i; |
| 63 | } |
| 64 | } |
| 65 | /* return default if no match */ |
| 66 | return rdev->pm.default_power_state_index; |
| 67 | } |
| 68 | |
Alex Deucher | c491707 | 2012-07-31 17:14:35 -0400 | [diff] [blame] | 69 | void radeon_pm_acpi_event_handler(struct radeon_device *rdev) |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 70 | { |
Alex Deucher | 1c71bda | 2013-09-09 19:11:52 -0400 | [diff] [blame] | 71 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { |
| 72 | mutex_lock(&rdev->pm.mutex); |
| 73 | if (power_supply_is_system_supplied() > 0) |
| 74 | rdev->pm.dpm.ac_power = true; |
| 75 | else |
| 76 | rdev->pm.dpm.ac_power = false; |
Alex Deucher | 9668295 | 2014-06-18 14:23:46 -0400 | [diff] [blame] | 77 | if (rdev->family == CHIP_ARUBA) { |
| 78 | if (rdev->asic->dpm.enable_bapm) |
| 79 | radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); |
| 80 | } |
Alex Deucher | 1c71bda | 2013-09-09 19:11:52 -0400 | [diff] [blame] | 81 | mutex_unlock(&rdev->pm.mutex); |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 82 | } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
Alex Deucher | c491707 | 2012-07-31 17:14:35 -0400 | [diff] [blame] | 83 | if (rdev->pm.profile == PM_PROFILE_AUTO) { |
| 84 | mutex_lock(&rdev->pm.mutex); |
| 85 | radeon_pm_update_profile(rdev); |
| 86 | radeon_pm_set_clocks(rdev); |
| 87 | mutex_unlock(&rdev->pm.mutex); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 88 | } |
| 89 | } |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 90 | } |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 91 | |
| 92 | static void radeon_pm_update_profile(struct radeon_device *rdev) |
| 93 | { |
| 94 | switch (rdev->pm.profile) { |
| 95 | case PM_PROFILE_DEFAULT: |
| 96 | rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; |
| 97 | break; |
| 98 | case PM_PROFILE_AUTO: |
| 99 | if (power_supply_is_system_supplied() > 0) { |
| 100 | if (rdev->pm.active_crtc_count > 1) |
| 101 | rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; |
| 102 | else |
| 103 | rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; |
| 104 | } else { |
| 105 | if (rdev->pm.active_crtc_count > 1) |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 106 | rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 107 | else |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 108 | rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 109 | } |
| 110 | break; |
| 111 | case PM_PROFILE_LOW: |
| 112 | if (rdev->pm.active_crtc_count > 1) |
| 113 | rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; |
| 114 | else |
| 115 | rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; |
| 116 | break; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 117 | case PM_PROFILE_MID: |
| 118 | if (rdev->pm.active_crtc_count > 1) |
| 119 | rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; |
| 120 | else |
| 121 | rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; |
| 122 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 123 | case PM_PROFILE_HIGH: |
| 124 | if (rdev->pm.active_crtc_count > 1) |
| 125 | rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; |
| 126 | else |
| 127 | rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; |
| 128 | break; |
| 129 | } |
| 130 | |
| 131 | if (rdev->pm.active_crtc_count == 0) { |
| 132 | rdev->pm.requested_power_state_index = |
| 133 | rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; |
| 134 | rdev->pm.requested_clock_mode_index = |
| 135 | rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; |
| 136 | } else { |
| 137 | rdev->pm.requested_power_state_index = |
| 138 | rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; |
| 139 | rdev->pm.requested_clock_mode_index = |
| 140 | rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; |
| 141 | } |
| 142 | } |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 143 | |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 144 | static void radeon_unmap_vram_bos(struct radeon_device *rdev) |
| 145 | { |
| 146 | struct radeon_bo *bo, *n; |
| 147 | |
| 148 | if (list_empty(&rdev->gem.objects)) |
| 149 | return; |
| 150 | |
| 151 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { |
| 152 | if (bo->tbo.mem.mem_type == TTM_PL_VRAM) |
| 153 | ttm_bo_unmap_virtual(&bo->tbo); |
| 154 | } |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 155 | } |
| 156 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 157 | static void radeon_sync_with_vblank(struct radeon_device *rdev) |
| 158 | { |
| 159 | if (rdev->pm.active_crtcs) { |
| 160 | rdev->pm.vblank_sync = false; |
| 161 | wait_event_timeout( |
| 162 | rdev->irq.vblank_queue, rdev->pm.vblank_sync, |
| 163 | msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); |
| 164 | } |
| 165 | } |
| 166 | |
| 167 | static void radeon_set_power_state(struct radeon_device *rdev) |
| 168 | { |
| 169 | u32 sclk, mclk; |
Alex Deucher | 9264587 | 2010-05-27 17:01:41 -0400 | [diff] [blame] | 170 | bool misc_after = false; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 171 | |
| 172 | if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && |
| 173 | (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) |
| 174 | return; |
| 175 | |
| 176 | if (radeon_gui_idle(rdev)) { |
| 177 | sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
| 178 | clock_info[rdev->pm.requested_clock_mode_index].sclk; |
Alex Deucher | 9ace9f7 | 2011-01-06 21:19:26 -0500 | [diff] [blame] | 179 | if (sclk > rdev->pm.default_sclk) |
| 180 | sclk = rdev->pm.default_sclk; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 181 | |
Alex Deucher | 27810fb | 2012-10-01 19:25:11 -0400 | [diff] [blame] | 182 | /* starting with BTC, there is one state that is used for both |
| 183 | * MH and SH. Difference is that we always use the high clock index for |
Alex Deucher | 7ae764b | 2013-02-11 08:44:48 -0500 | [diff] [blame] | 184 | * mclk and vddci. |
Alex Deucher | 27810fb | 2012-10-01 19:25:11 -0400 | [diff] [blame] | 185 | */ |
| 186 | if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && |
| 187 | (rdev->family >= CHIP_BARTS) && |
| 188 | rdev->pm.active_crtc_count && |
| 189 | ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || |
| 190 | (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) |
| 191 | mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
| 192 | clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; |
| 193 | else |
| 194 | mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
| 195 | clock_info[rdev->pm.requested_clock_mode_index].mclk; |
| 196 | |
Alex Deucher | 9ace9f7 | 2011-01-06 21:19:26 -0500 | [diff] [blame] | 197 | if (mclk > rdev->pm.default_mclk) |
| 198 | mclk = rdev->pm.default_mclk; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 199 | |
Alex Deucher | 9264587 | 2010-05-27 17:01:41 -0400 | [diff] [blame] | 200 | /* upvolt before raising clocks, downvolt after lowering clocks */ |
| 201 | if (sclk < rdev->pm.current_sclk) |
| 202 | misc_after = true; |
| 203 | |
| 204 | radeon_sync_with_vblank(rdev); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 205 | |
| 206 | if (rdev->pm.pm_method == PM_METHOD_DYNPM) { |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 207 | if (!radeon_pm_in_vbl(rdev)) |
| 208 | return; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 209 | } |
| 210 | |
Alex Deucher | 9264587 | 2010-05-27 17:01:41 -0400 | [diff] [blame] | 211 | radeon_pm_prepare(rdev); |
| 212 | |
| 213 | if (!misc_after) |
| 214 | /* voltage, pcie lanes, etc.*/ |
| 215 | radeon_pm_misc(rdev); |
| 216 | |
| 217 | /* set engine clock */ |
| 218 | if (sclk != rdev->pm.current_sclk) { |
| 219 | radeon_pm_debug_check_in_vbl(rdev, false); |
| 220 | radeon_set_engine_clock(rdev, sclk); |
| 221 | radeon_pm_debug_check_in_vbl(rdev, true); |
| 222 | rdev->pm.current_sclk = sclk; |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 223 | DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); |
Alex Deucher | 9264587 | 2010-05-27 17:01:41 -0400 | [diff] [blame] | 224 | } |
| 225 | |
| 226 | /* set memory clock */ |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 227 | if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { |
Alex Deucher | 9264587 | 2010-05-27 17:01:41 -0400 | [diff] [blame] | 228 | radeon_pm_debug_check_in_vbl(rdev, false); |
| 229 | radeon_set_memory_clock(rdev, mclk); |
| 230 | radeon_pm_debug_check_in_vbl(rdev, true); |
| 231 | rdev->pm.current_mclk = mclk; |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 232 | DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); |
Alex Deucher | 9264587 | 2010-05-27 17:01:41 -0400 | [diff] [blame] | 233 | } |
| 234 | |
| 235 | if (misc_after) |
| 236 | /* voltage, pcie lanes, etc.*/ |
| 237 | radeon_pm_misc(rdev); |
| 238 | |
| 239 | radeon_pm_finish(rdev); |
| 240 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 241 | rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; |
| 242 | rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; |
| 243 | } else |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 244 | DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 245 | } |
| 246 | |
| 247 | static void radeon_pm_set_clocks(struct radeon_device *rdev) |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 248 | { |
Gustavo Padovan | a782bca | 2016-06-06 11:41:44 -0300 | [diff] [blame] | 249 | struct drm_crtc *crtc; |
Jerome Glisse | 5f8f635 | 2012-12-17 11:04:32 -0500 | [diff] [blame] | 250 | int i, r; |
Matthew Garrett | 2aba631 | 2010-04-26 15:45:23 -0400 | [diff] [blame] | 251 | |
Alex Deucher | 4e186b2 | 2010-08-13 10:53:35 -0400 | [diff] [blame] | 252 | /* no need to take locks, etc. if nothing's going to change */ |
| 253 | if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && |
| 254 | (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) |
| 255 | return; |
| 256 | |
Christian König | db7fce3 | 2012-05-11 14:57:18 +0200 | [diff] [blame] | 257 | down_write(&rdev->pm.mclk_lock); |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 258 | mutex_lock(&rdev->ring_lock); |
Alex Deucher | 4f3218c | 2010-04-29 16:14:02 -0400 | [diff] [blame] | 259 | |
Alex Deucher | 95f5a3a | 2012-08-10 13:12:08 -0400 | [diff] [blame] | 260 | /* wait for the rings to drain */ |
| 261 | for (i = 0; i < RADEON_NUM_RINGS; i++) { |
| 262 | struct radeon_ring *ring = &rdev->ring[i]; |
Jerome Glisse | 5f8f635 | 2012-12-17 11:04:32 -0500 | [diff] [blame] | 263 | if (!ring->ready) { |
| 264 | continue; |
| 265 | } |
Christian König | 3761552 | 2014-02-18 15:58:31 +0100 | [diff] [blame] | 266 | r = radeon_fence_wait_empty(rdev, i); |
Jerome Glisse | 5f8f635 | 2012-12-17 11:04:32 -0500 | [diff] [blame] | 267 | if (r) { |
| 268 | /* needs a GPU reset dont reset here */ |
| 269 | mutex_unlock(&rdev->ring_lock); |
| 270 | up_write(&rdev->pm.mclk_lock); |
Jerome Glisse | 5f8f635 | 2012-12-17 11:04:32 -0500 | [diff] [blame] | 271 | return; |
| 272 | } |
Alex Deucher | 4f3218c | 2010-04-29 16:14:02 -0400 | [diff] [blame] | 273 | } |
Alex Deucher | 95f5a3a | 2012-08-10 13:12:08 -0400 | [diff] [blame] | 274 | |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 275 | radeon_unmap_vram_bos(rdev); |
| 276 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 277 | if (rdev->irq.installed) { |
Gustavo Padovan | a782bca | 2016-06-06 11:41:44 -0300 | [diff] [blame] | 278 | i = 0; |
| 279 | drm_for_each_crtc(crtc, rdev->ddev) { |
Matthew Garrett | 2aba631 | 2010-04-26 15:45:23 -0400 | [diff] [blame] | 280 | if (rdev->pm.active_crtcs & (1 << i)) { |
Mario Kleiner | e0b34e3 | 2016-02-12 20:30:31 +0100 | [diff] [blame] | 281 | /* This can fail if a modeset is in progress */ |
Gustavo Padovan | a782bca | 2016-06-06 11:41:44 -0300 | [diff] [blame] | 282 | if (drm_crtc_vblank_get(crtc) == 0) |
Mario Kleiner | e0b34e3 | 2016-02-12 20:30:31 +0100 | [diff] [blame] | 283 | rdev->pm.req_vblank |= (1 << i); |
| 284 | else |
| 285 | DRM_DEBUG_DRIVER("crtc %d no vblank, can glitch\n", |
| 286 | i); |
Matthew Garrett | 2aba631 | 2010-04-26 15:45:23 -0400 | [diff] [blame] | 287 | } |
Gustavo Padovan | a782bca | 2016-06-06 11:41:44 -0300 | [diff] [blame] | 288 | i++; |
Matthew Garrett | 2aba631 | 2010-04-26 15:45:23 -0400 | [diff] [blame] | 289 | } |
| 290 | } |
Alex Deucher | 539d241 | 2010-04-29 00:22:43 -0400 | [diff] [blame] | 291 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 292 | radeon_set_power_state(rdev); |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 293 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 294 | if (rdev->irq.installed) { |
Gustavo Padovan | a782bca | 2016-06-06 11:41:44 -0300 | [diff] [blame] | 295 | i = 0; |
| 296 | drm_for_each_crtc(crtc, rdev->ddev) { |
Matthew Garrett | 2aba631 | 2010-04-26 15:45:23 -0400 | [diff] [blame] | 297 | if (rdev->pm.req_vblank & (1 << i)) { |
| 298 | rdev->pm.req_vblank &= ~(1 << i); |
Gustavo Padovan | a782bca | 2016-06-06 11:41:44 -0300 | [diff] [blame] | 299 | drm_crtc_vblank_put(crtc); |
Matthew Garrett | 2aba631 | 2010-04-26 15:45:23 -0400 | [diff] [blame] | 300 | } |
Gustavo Padovan | a782bca | 2016-06-06 11:41:44 -0300 | [diff] [blame] | 301 | i++; |
Matthew Garrett | 2aba631 | 2010-04-26 15:45:23 -0400 | [diff] [blame] | 302 | } |
| 303 | } |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 304 | |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 305 | /* update display watermarks based on new power state */ |
| 306 | radeon_update_bandwidth_info(rdev); |
| 307 | if (rdev->pm.active_crtc_count) |
| 308 | radeon_bandwidth_update(rdev); |
| 309 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 310 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; |
Matthew Garrett | 2aba631 | 2010-04-26 15:45:23 -0400 | [diff] [blame] | 311 | |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 312 | mutex_unlock(&rdev->ring_lock); |
Christian König | db7fce3 | 2012-05-11 14:57:18 +0200 | [diff] [blame] | 313 | up_write(&rdev->pm.mclk_lock); |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 314 | } |
| 315 | |
Rafał Miłecki | f712d0c | 2010-06-07 18:29:44 -0400 | [diff] [blame] | 316 | static void radeon_pm_print_states(struct radeon_device *rdev) |
| 317 | { |
| 318 | int i, j; |
| 319 | struct radeon_power_state *power_state; |
| 320 | struct radeon_pm_clock_info *clock_info; |
| 321 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 322 | DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); |
Rafał Miłecki | f712d0c | 2010-06-07 18:29:44 -0400 | [diff] [blame] | 323 | for (i = 0; i < rdev->pm.num_power_states; i++) { |
| 324 | power_state = &rdev->pm.power_state[i]; |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 325 | DRM_DEBUG_DRIVER("State %d: %s\n", i, |
Rafał Miłecki | f712d0c | 2010-06-07 18:29:44 -0400 | [diff] [blame] | 326 | radeon_pm_state_type_name[power_state->type]); |
| 327 | if (i == rdev->pm.default_power_state_index) |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 328 | DRM_DEBUG_DRIVER("\tDefault"); |
Rafał Miłecki | f712d0c | 2010-06-07 18:29:44 -0400 | [diff] [blame] | 329 | if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 330 | DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); |
Rafał Miłecki | f712d0c | 2010-06-07 18:29:44 -0400 | [diff] [blame] | 331 | if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 332 | DRM_DEBUG_DRIVER("\tSingle display only\n"); |
| 333 | DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); |
Rafał Miłecki | f712d0c | 2010-06-07 18:29:44 -0400 | [diff] [blame] | 334 | for (j = 0; j < power_state->num_clock_modes; j++) { |
| 335 | clock_info = &(power_state->clock_info[j]); |
| 336 | if (rdev->flags & RADEON_IS_IGP) |
Alex Deucher | eb2c27a | 2012-10-01 18:28:09 -0400 | [diff] [blame] | 337 | DRM_DEBUG_DRIVER("\t\t%d e: %d\n", |
| 338 | j, |
| 339 | clock_info->sclk * 10); |
Rafał Miłecki | f712d0c | 2010-06-07 18:29:44 -0400 | [diff] [blame] | 340 | else |
Alex Deucher | eb2c27a | 2012-10-01 18:28:09 -0400 | [diff] [blame] | 341 | DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n", |
| 342 | j, |
| 343 | clock_info->sclk * 10, |
| 344 | clock_info->mclk * 10, |
| 345 | clock_info->voltage.voltage); |
Rafał Miłecki | f712d0c | 2010-06-07 18:29:44 -0400 | [diff] [blame] | 346 | } |
| 347 | } |
| 348 | } |
| 349 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 350 | static ssize_t radeon_get_pm_profile(struct device *dev, |
| 351 | struct device_attribute *attr, |
| 352 | char *buf) |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 353 | { |
Jean Delvare | 3e4e212 | 2013-09-10 10:30:44 +0200 | [diff] [blame] | 354 | struct drm_device *ddev = dev_get_drvdata(dev); |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 355 | struct radeon_device *rdev = ddev->dev_private; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 356 | int cp = rdev->pm.profile; |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 357 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 358 | return snprintf(buf, PAGE_SIZE, "%s\n", |
| 359 | (cp == PM_PROFILE_AUTO) ? "auto" : |
| 360 | (cp == PM_PROFILE_LOW) ? "low" : |
Daniel J Blueman | 12e27be | 2010-07-28 12:25:58 +0100 | [diff] [blame] | 361 | (cp == PM_PROFILE_MID) ? "mid" : |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 362 | (cp == PM_PROFILE_HIGH) ? "high" : "default"); |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 363 | } |
| 364 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 365 | static ssize_t radeon_set_pm_profile(struct device *dev, |
| 366 | struct device_attribute *attr, |
| 367 | const char *buf, |
| 368 | size_t count) |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 369 | { |
Jean Delvare | 3e4e212 | 2013-09-10 10:30:44 +0200 | [diff] [blame] | 370 | struct drm_device *ddev = dev_get_drvdata(dev); |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 371 | struct radeon_device *rdev = ddev->dev_private; |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 372 | |
Alex Deucher | 4f2f203 | 2014-05-19 19:21:29 -0400 | [diff] [blame] | 373 | /* Can't set profile when the card is off */ |
| 374 | if ((rdev->flags & RADEON_IS_PX) && |
| 375 | (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) |
| 376 | return -EINVAL; |
| 377 | |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 378 | mutex_lock(&rdev->pm.mutex); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 379 | if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
| 380 | if (strncmp("default", buf, strlen("default")) == 0) |
| 381 | rdev->pm.profile = PM_PROFILE_DEFAULT; |
| 382 | else if (strncmp("auto", buf, strlen("auto")) == 0) |
| 383 | rdev->pm.profile = PM_PROFILE_AUTO; |
| 384 | else if (strncmp("low", buf, strlen("low")) == 0) |
| 385 | rdev->pm.profile = PM_PROFILE_LOW; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 386 | else if (strncmp("mid", buf, strlen("mid")) == 0) |
| 387 | rdev->pm.profile = PM_PROFILE_MID; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 388 | else if (strncmp("high", buf, strlen("high")) == 0) |
| 389 | rdev->pm.profile = PM_PROFILE_HIGH; |
| 390 | else { |
Thomas Renninger | 1783e4b | 2011-03-23 15:14:09 +0000 | [diff] [blame] | 391 | count = -EINVAL; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 392 | goto fail; |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 393 | } |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 394 | radeon_pm_update_profile(rdev); |
| 395 | radeon_pm_set_clocks(rdev); |
Thomas Renninger | 1783e4b | 2011-03-23 15:14:09 +0000 | [diff] [blame] | 396 | } else |
| 397 | count = -EINVAL; |
| 398 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 399 | fail: |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 400 | mutex_unlock(&rdev->pm.mutex); |
| 401 | |
| 402 | return count; |
| 403 | } |
| 404 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 405 | static ssize_t radeon_get_pm_method(struct device *dev, |
| 406 | struct device_attribute *attr, |
| 407 | char *buf) |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 408 | { |
Jean Delvare | 3e4e212 | 2013-09-10 10:30:44 +0200 | [diff] [blame] | 409 | struct drm_device *ddev = dev_get_drvdata(dev); |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 410 | struct radeon_device *rdev = ddev->dev_private; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 411 | int pm = rdev->pm.pm_method; |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 412 | |
| 413 | return snprintf(buf, PAGE_SIZE, "%s\n", |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 414 | (pm == PM_METHOD_DYNPM) ? "dynpm" : |
| 415 | (pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 416 | } |
| 417 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 418 | static ssize_t radeon_set_pm_method(struct device *dev, |
| 419 | struct device_attribute *attr, |
| 420 | const char *buf, |
| 421 | size_t count) |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 422 | { |
Jean Delvare | 3e4e212 | 2013-09-10 10:30:44 +0200 | [diff] [blame] | 423 | struct drm_device *ddev = dev_get_drvdata(dev); |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 424 | struct radeon_device *rdev = ddev->dev_private; |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 425 | |
Alex Deucher | 4f2f203 | 2014-05-19 19:21:29 -0400 | [diff] [blame] | 426 | /* Can't set method when the card is off */ |
| 427 | if ((rdev->flags & RADEON_IS_PX) && |
| 428 | (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { |
| 429 | count = -EINVAL; |
| 430 | goto fail; |
| 431 | } |
| 432 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 433 | /* we don't support the legacy modes with dpm */ |
| 434 | if (rdev->pm.pm_method == PM_METHOD_DPM) { |
| 435 | count = -EINVAL; |
| 436 | goto fail; |
| 437 | } |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 438 | |
| 439 | if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 440 | mutex_lock(&rdev->pm.mutex); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 441 | rdev->pm.pm_method = PM_METHOD_DYNPM; |
| 442 | rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; |
| 443 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 444 | mutex_unlock(&rdev->pm.mutex); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 445 | } else if (strncmp("profile", buf, strlen("profile")) == 0) { |
| 446 | mutex_lock(&rdev->pm.mutex); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 447 | /* disable dynpm */ |
| 448 | rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; |
| 449 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; |
Rafael J. Wysocki | 3f53eb6 | 2010-06-17 23:02:27 +0000 | [diff] [blame] | 450 | rdev->pm.pm_method = PM_METHOD_PROFILE; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 451 | mutex_unlock(&rdev->pm.mutex); |
Tejun Heo | 32c87fc | 2011-01-03 14:49:32 +0100 | [diff] [blame] | 452 | cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 453 | } else { |
Thomas Renninger | 1783e4b | 2011-03-23 15:14:09 +0000 | [diff] [blame] | 454 | count = -EINVAL; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 455 | goto fail; |
| 456 | } |
| 457 | radeon_pm_compute_clocks(rdev); |
| 458 | fail: |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 459 | return count; |
| 460 | } |
| 461 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 462 | static ssize_t radeon_get_dpm_state(struct device *dev, |
| 463 | struct device_attribute *attr, |
| 464 | char *buf) |
| 465 | { |
Jean Delvare | 3e4e212 | 2013-09-10 10:30:44 +0200 | [diff] [blame] | 466 | struct drm_device *ddev = dev_get_drvdata(dev); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 467 | struct radeon_device *rdev = ddev->dev_private; |
| 468 | enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; |
| 469 | |
| 470 | return snprintf(buf, PAGE_SIZE, "%s\n", |
| 471 | (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : |
| 472 | (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); |
| 473 | } |
| 474 | |
| 475 | static ssize_t radeon_set_dpm_state(struct device *dev, |
| 476 | struct device_attribute *attr, |
| 477 | const char *buf, |
| 478 | size_t count) |
| 479 | { |
Jean Delvare | 3e4e212 | 2013-09-10 10:30:44 +0200 | [diff] [blame] | 480 | struct drm_device *ddev = dev_get_drvdata(dev); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 481 | struct radeon_device *rdev = ddev->dev_private; |
| 482 | |
| 483 | mutex_lock(&rdev->pm.mutex); |
| 484 | if (strncmp("battery", buf, strlen("battery")) == 0) |
| 485 | rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; |
| 486 | else if (strncmp("balanced", buf, strlen("balanced")) == 0) |
| 487 | rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; |
| 488 | else if (strncmp("performance", buf, strlen("performance")) == 0) |
| 489 | rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; |
| 490 | else { |
| 491 | mutex_unlock(&rdev->pm.mutex); |
| 492 | count = -EINVAL; |
| 493 | goto fail; |
| 494 | } |
| 495 | mutex_unlock(&rdev->pm.mutex); |
Pali Rohár | b07a657 | 2014-08-11 19:01:58 +0200 | [diff] [blame] | 496 | |
| 497 | /* Can't set dpm state when the card is off */ |
| 498 | if (!(rdev->flags & RADEON_IS_PX) || |
| 499 | (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) |
| 500 | radeon_pm_compute_clocks(rdev); |
| 501 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 502 | fail: |
| 503 | return count; |
| 504 | } |
| 505 | |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 506 | static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev, |
| 507 | struct device_attribute *attr, |
| 508 | char *buf) |
| 509 | { |
Jean Delvare | 3e4e212 | 2013-09-10 10:30:44 +0200 | [diff] [blame] | 510 | struct drm_device *ddev = dev_get_drvdata(dev); |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 511 | struct radeon_device *rdev = ddev->dev_private; |
| 512 | enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; |
| 513 | |
Alex Deucher | 4f2f203 | 2014-05-19 19:21:29 -0400 | [diff] [blame] | 514 | if ((rdev->flags & RADEON_IS_PX) && |
| 515 | (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) |
| 516 | return snprintf(buf, PAGE_SIZE, "off\n"); |
| 517 | |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 518 | return snprintf(buf, PAGE_SIZE, "%s\n", |
| 519 | (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" : |
| 520 | (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); |
| 521 | } |
| 522 | |
| 523 | static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev, |
| 524 | struct device_attribute *attr, |
| 525 | const char *buf, |
| 526 | size_t count) |
| 527 | { |
Jean Delvare | 3e4e212 | 2013-09-10 10:30:44 +0200 | [diff] [blame] | 528 | struct drm_device *ddev = dev_get_drvdata(dev); |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 529 | struct radeon_device *rdev = ddev->dev_private; |
| 530 | enum radeon_dpm_forced_level level; |
| 531 | int ret = 0; |
| 532 | |
Alex Deucher | 4f2f203 | 2014-05-19 19:21:29 -0400 | [diff] [blame] | 533 | /* Can't force performance level when the card is off */ |
| 534 | if ((rdev->flags & RADEON_IS_PX) && |
| 535 | (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) |
| 536 | return -EINVAL; |
| 537 | |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 538 | mutex_lock(&rdev->pm.mutex); |
| 539 | if (strncmp("low", buf, strlen("low")) == 0) { |
| 540 | level = RADEON_DPM_FORCED_LEVEL_LOW; |
| 541 | } else if (strncmp("high", buf, strlen("high")) == 0) { |
| 542 | level = RADEON_DPM_FORCED_LEVEL_HIGH; |
| 543 | } else if (strncmp("auto", buf, strlen("auto")) == 0) { |
| 544 | level = RADEON_DPM_FORCED_LEVEL_AUTO; |
| 545 | } else { |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 546 | count = -EINVAL; |
| 547 | goto fail; |
| 548 | } |
| 549 | if (rdev->asic->dpm.force_performance_level) { |
Alex Deucher | 0a17af37 | 2013-10-23 17:22:29 -0400 | [diff] [blame] | 550 | if (rdev->pm.dpm.thermal_active) { |
| 551 | count = -EINVAL; |
| 552 | goto fail; |
| 553 | } |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 554 | ret = radeon_dpm_force_performance_level(rdev, level); |
| 555 | if (ret) |
| 556 | count = -EINVAL; |
| 557 | } |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 558 | fail: |
Alex Deucher | 0a17af37 | 2013-10-23 17:22:29 -0400 | [diff] [blame] | 559 | mutex_unlock(&rdev->pm.mutex); |
| 560 | |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 561 | return count; |
| 562 | } |
| 563 | |
Oleg Chernovskiy | 9973670 | 2014-12-08 00:10:45 +0300 | [diff] [blame] | 564 | static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev, |
| 565 | struct device_attribute *attr, |
| 566 | char *buf) |
| 567 | { |
| 568 | struct radeon_device *rdev = dev_get_drvdata(dev); |
| 569 | u32 pwm_mode = 0; |
| 570 | |
| 571 | if (rdev->asic->dpm.fan_ctrl_get_mode) |
| 572 | pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev); |
| 573 | |
| 574 | /* never 0 (full-speed), fuse or smc-controlled always */ |
| 575 | return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2); |
| 576 | } |
| 577 | |
| 578 | static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev, |
| 579 | struct device_attribute *attr, |
| 580 | const char *buf, |
| 581 | size_t count) |
| 582 | { |
| 583 | struct radeon_device *rdev = dev_get_drvdata(dev); |
| 584 | int err; |
| 585 | int value; |
| 586 | |
| 587 | if(!rdev->asic->dpm.fan_ctrl_set_mode) |
| 588 | return -EINVAL; |
| 589 | |
| 590 | err = kstrtoint(buf, 10, &value); |
| 591 | if (err) |
| 592 | return err; |
| 593 | |
Alex Deucher | 082452e | 2015-02-04 17:18:55 -0500 | [diff] [blame] | 594 | switch (value) { |
Oleg Chernovskiy | 9973670 | 2014-12-08 00:10:45 +0300 | [diff] [blame] | 595 | case 1: /* manual, percent-based */ |
| 596 | rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC); |
| 597 | break; |
| 598 | default: /* disable */ |
| 599 | rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0); |
| 600 | break; |
| 601 | } |
| 602 | |
| 603 | return count; |
| 604 | } |
| 605 | |
| 606 | static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev, |
| 607 | struct device_attribute *attr, |
| 608 | char *buf) |
| 609 | { |
| 610 | return sprintf(buf, "%i\n", 0); |
| 611 | } |
| 612 | |
| 613 | static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev, |
| 614 | struct device_attribute *attr, |
| 615 | char *buf) |
| 616 | { |
Alex Deucher | 082452e | 2015-02-04 17:18:55 -0500 | [diff] [blame] | 617 | return sprintf(buf, "%i\n", 255); |
Oleg Chernovskiy | 9973670 | 2014-12-08 00:10:45 +0300 | [diff] [blame] | 618 | } |
| 619 | |
| 620 | static ssize_t radeon_hwmon_set_pwm1(struct device *dev, |
| 621 | struct device_attribute *attr, |
| 622 | const char *buf, size_t count) |
| 623 | { |
| 624 | struct radeon_device *rdev = dev_get_drvdata(dev); |
| 625 | int err; |
| 626 | u32 value; |
| 627 | |
| 628 | err = kstrtou32(buf, 10, &value); |
| 629 | if (err) |
| 630 | return err; |
| 631 | |
Alex Deucher | 082452e | 2015-02-04 17:18:55 -0500 | [diff] [blame] | 632 | value = (value * 100) / 255; |
| 633 | |
Oleg Chernovskiy | 9973670 | 2014-12-08 00:10:45 +0300 | [diff] [blame] | 634 | err = rdev->asic->dpm.set_fan_speed_percent(rdev, value); |
| 635 | if (err) |
| 636 | return err; |
| 637 | |
| 638 | return count; |
| 639 | } |
| 640 | |
| 641 | static ssize_t radeon_hwmon_get_pwm1(struct device *dev, |
| 642 | struct device_attribute *attr, |
| 643 | char *buf) |
| 644 | { |
| 645 | struct radeon_device *rdev = dev_get_drvdata(dev); |
| 646 | int err; |
| 647 | u32 speed; |
| 648 | |
| 649 | err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed); |
| 650 | if (err) |
| 651 | return err; |
| 652 | |
Alex Deucher | 082452e | 2015-02-04 17:18:55 -0500 | [diff] [blame] | 653 | speed = (speed * 255) / 100; |
| 654 | |
Oleg Chernovskiy | 9973670 | 2014-12-08 00:10:45 +0300 | [diff] [blame] | 655 | return sprintf(buf, "%i\n", speed); |
| 656 | } |
| 657 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 658 | static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); |
| 659 | static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 660 | static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state); |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 661 | static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, |
| 662 | radeon_get_dpm_forced_performance_level, |
| 663 | radeon_set_dpm_forced_performance_level); |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 664 | |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 665 | static ssize_t radeon_hwmon_show_temp(struct device *dev, |
| 666 | struct device_attribute *attr, |
| 667 | char *buf) |
| 668 | { |
Guenter Roeck | ec39f64 | 2013-11-22 21:52:00 -0800 | [diff] [blame] | 669 | struct radeon_device *rdev = dev_get_drvdata(dev); |
Alex Deucher | 4f2f203 | 2014-05-19 19:21:29 -0400 | [diff] [blame] | 670 | struct drm_device *ddev = rdev->ddev; |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 671 | int temp; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 672 | |
Alex Deucher | 4f2f203 | 2014-05-19 19:21:29 -0400 | [diff] [blame] | 673 | /* Can't get temperature when the card is off */ |
| 674 | if ((rdev->flags & RADEON_IS_PX) && |
| 675 | (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) |
| 676 | return -EINVAL; |
| 677 | |
Alex Deucher | 6bd1c38 | 2013-06-21 14:38:03 -0400 | [diff] [blame] | 678 | if (rdev->asic->pm.get_temperature) |
| 679 | temp = radeon_get_temperature(rdev); |
| 680 | else |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 681 | temp = 0; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 682 | |
| 683 | return snprintf(buf, PAGE_SIZE, "%d\n", temp); |
| 684 | } |
| 685 | |
Jean Delvare | 6ea4e84 | 2013-09-10 10:32:41 +0200 | [diff] [blame] | 686 | static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev, |
| 687 | struct device_attribute *attr, |
| 688 | char *buf) |
| 689 | { |
Sergey Senozhatsky | e4158f1 | 2013-12-13 02:25:57 +0300 | [diff] [blame] | 690 | struct radeon_device *rdev = dev_get_drvdata(dev); |
Jean Delvare | 6ea4e84 | 2013-09-10 10:32:41 +0200 | [diff] [blame] | 691 | int hyst = to_sensor_dev_attr(attr)->index; |
| 692 | int temp; |
| 693 | |
| 694 | if (hyst) |
| 695 | temp = rdev->pm.dpm.thermal.min_temp; |
| 696 | else |
| 697 | temp = rdev->pm.dpm.thermal.max_temp; |
| 698 | |
| 699 | return snprintf(buf, PAGE_SIZE, "%d\n", temp); |
| 700 | } |
| 701 | |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 702 | static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); |
Jean Delvare | 6ea4e84 | 2013-09-10 10:32:41 +0200 | [diff] [blame] | 703 | static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0); |
| 704 | static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1); |
Oleg Chernovskiy | 9973670 | 2014-12-08 00:10:45 +0300 | [diff] [blame] | 705 | static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0); |
| 706 | static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0); |
| 707 | static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0); |
| 708 | static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0); |
| 709 | |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 710 | |
| 711 | static struct attribute *hwmon_attributes[] = { |
| 712 | &sensor_dev_attr_temp1_input.dev_attr.attr, |
Jean Delvare | 6ea4e84 | 2013-09-10 10:32:41 +0200 | [diff] [blame] | 713 | &sensor_dev_attr_temp1_crit.dev_attr.attr, |
| 714 | &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, |
Oleg Chernovskiy | 9973670 | 2014-12-08 00:10:45 +0300 | [diff] [blame] | 715 | &sensor_dev_attr_pwm1.dev_attr.attr, |
| 716 | &sensor_dev_attr_pwm1_enable.dev_attr.attr, |
| 717 | &sensor_dev_attr_pwm1_min.dev_attr.attr, |
| 718 | &sensor_dev_attr_pwm1_max.dev_attr.attr, |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 719 | NULL |
| 720 | }; |
| 721 | |
Jean Delvare | 6ea4e84 | 2013-09-10 10:32:41 +0200 | [diff] [blame] | 722 | static umode_t hwmon_attributes_visible(struct kobject *kobj, |
| 723 | struct attribute *attr, int index) |
| 724 | { |
Geliang Tang | e3837b0 | 2016-01-13 22:48:43 +0800 | [diff] [blame] | 725 | struct device *dev = kobj_to_dev(kobj); |
Sergey Senozhatsky | e4158f1 | 2013-12-13 02:25:57 +0300 | [diff] [blame] | 726 | struct radeon_device *rdev = dev_get_drvdata(dev); |
Oleg Chernovskiy | 9973670 | 2014-12-08 00:10:45 +0300 | [diff] [blame] | 727 | umode_t effective_mode = attr->mode; |
Jean Delvare | 6ea4e84 | 2013-09-10 10:32:41 +0200 | [diff] [blame] | 728 | |
Alex Deucher | 2a7d44f | 2015-10-19 09:30:42 -0400 | [diff] [blame] | 729 | /* Skip attributes if DPM is not enabled */ |
Jean Delvare | 6ea4e84 | 2013-09-10 10:32:41 +0200 | [diff] [blame] | 730 | if (rdev->pm.pm_method != PM_METHOD_DPM && |
| 731 | (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || |
Alex Deucher | 2a7d44f | 2015-10-19 09:30:42 -0400 | [diff] [blame] | 732 | attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || |
| 733 | attr == &sensor_dev_attr_pwm1.dev_attr.attr || |
| 734 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || |
| 735 | attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || |
| 736 | attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) |
Jean Delvare | 6ea4e84 | 2013-09-10 10:32:41 +0200 | [diff] [blame] | 737 | return 0; |
| 738 | |
Oleg Chernovskiy | 9973670 | 2014-12-08 00:10:45 +0300 | [diff] [blame] | 739 | /* Skip fan attributes if fan is not present */ |
| 740 | if (rdev->pm.no_fan && |
| 741 | (attr == &sensor_dev_attr_pwm1.dev_attr.attr || |
| 742 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || |
| 743 | attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || |
| 744 | attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) |
| 745 | return 0; |
| 746 | |
| 747 | /* mask fan attributes if we have no bindings for this asic to expose */ |
| 748 | if ((!rdev->asic->dpm.get_fan_speed_percent && |
| 749 | attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ |
| 750 | (!rdev->asic->dpm.fan_ctrl_get_mode && |
| 751 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ |
| 752 | effective_mode &= ~S_IRUGO; |
| 753 | |
| 754 | if ((!rdev->asic->dpm.set_fan_speed_percent && |
| 755 | attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ |
| 756 | (!rdev->asic->dpm.fan_ctrl_set_mode && |
| 757 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ |
| 758 | effective_mode &= ~S_IWUSR; |
| 759 | |
| 760 | /* hide max/min values if we can't both query and manage the fan */ |
| 761 | if ((!rdev->asic->dpm.set_fan_speed_percent && |
| 762 | !rdev->asic->dpm.get_fan_speed_percent) && |
| 763 | (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || |
| 764 | attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) |
| 765 | return 0; |
| 766 | |
| 767 | return effective_mode; |
Jean Delvare | 6ea4e84 | 2013-09-10 10:32:41 +0200 | [diff] [blame] | 768 | } |
| 769 | |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 770 | static const struct attribute_group hwmon_attrgroup = { |
| 771 | .attrs = hwmon_attributes, |
Jean Delvare | 6ea4e84 | 2013-09-10 10:32:41 +0200 | [diff] [blame] | 772 | .is_visible = hwmon_attributes_visible, |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 773 | }; |
| 774 | |
Guenter Roeck | ec39f64 | 2013-11-22 21:52:00 -0800 | [diff] [blame] | 775 | static const struct attribute_group *hwmon_groups[] = { |
| 776 | &hwmon_attrgroup, |
| 777 | NULL |
| 778 | }; |
| 779 | |
Dan Carpenter | 0d18abe | 2010-08-09 21:59:42 +0200 | [diff] [blame] | 780 | static int radeon_hwmon_init(struct radeon_device *rdev) |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 781 | { |
Dan Carpenter | 0d18abe | 2010-08-09 21:59:42 +0200 | [diff] [blame] | 782 | int err = 0; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 783 | |
| 784 | switch (rdev->pm.int_thermal_type) { |
| 785 | case THERMAL_TYPE_RV6XX: |
| 786 | case THERMAL_TYPE_RV770: |
| 787 | case THERMAL_TYPE_EVERGREEN: |
Alex Deucher | 457558e | 2011-05-25 17:49:54 -0400 | [diff] [blame] | 788 | case THERMAL_TYPE_NI: |
Alex Deucher | e33df25 | 2010-11-22 17:56:32 -0500 | [diff] [blame] | 789 | case THERMAL_TYPE_SUMO: |
Alex Deucher | 1bd47d2 | 2012-03-20 17:18:10 -0400 | [diff] [blame] | 790 | case THERMAL_TYPE_SI: |
Alex Deucher | 286d9cc | 2013-06-21 15:50:47 -0400 | [diff] [blame] | 791 | case THERMAL_TYPE_CI: |
| 792 | case THERMAL_TYPE_KV: |
Alex Deucher | 6bd1c38 | 2013-06-21 14:38:03 -0400 | [diff] [blame] | 793 | if (rdev->asic->pm.get_temperature == NULL) |
Alex Deucher | 5d7486c | 2012-03-20 17:18:29 -0400 | [diff] [blame] | 794 | return err; |
Alex Deucher | cb3e4e7 | 2014-04-15 12:44:32 -0400 | [diff] [blame] | 795 | rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev, |
| 796 | "radeon", rdev, |
| 797 | hwmon_groups); |
| 798 | if (IS_ERR(rdev->pm.int_hwmon_dev)) { |
| 799 | err = PTR_ERR(rdev->pm.int_hwmon_dev); |
Dan Carpenter | 0d18abe | 2010-08-09 21:59:42 +0200 | [diff] [blame] | 800 | dev_err(rdev->dev, |
| 801 | "Unable to register hwmon device: %d\n", err); |
Dan Carpenter | 0d18abe | 2010-08-09 21:59:42 +0200 | [diff] [blame] | 802 | } |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 803 | break; |
| 804 | default: |
| 805 | break; |
| 806 | } |
Dan Carpenter | 0d18abe | 2010-08-09 21:59:42 +0200 | [diff] [blame] | 807 | |
| 808 | return err; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 809 | } |
| 810 | |
Alex Deucher | cb3e4e7 | 2014-04-15 12:44:32 -0400 | [diff] [blame] | 811 | static void radeon_hwmon_fini(struct radeon_device *rdev) |
| 812 | { |
| 813 | if (rdev->pm.int_hwmon_dev) |
| 814 | hwmon_device_unregister(rdev->pm.int_hwmon_dev); |
| 815 | } |
| 816 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 817 | static void radeon_dpm_thermal_work_handler(struct work_struct *work) |
| 818 | { |
| 819 | struct radeon_device *rdev = |
| 820 | container_of(work, struct radeon_device, |
| 821 | pm.dpm.thermal.work); |
| 822 | /* switch to the thermal state */ |
| 823 | enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL; |
| 824 | |
| 825 | if (!rdev->pm.dpm_enabled) |
| 826 | return; |
| 827 | |
| 828 | if (rdev->asic->pm.get_temperature) { |
| 829 | int temp = radeon_get_temperature(rdev); |
| 830 | |
| 831 | if (temp < rdev->pm.dpm.thermal.min_temp) |
| 832 | /* switch back the user state */ |
| 833 | dpm_state = rdev->pm.dpm.user_state; |
| 834 | } else { |
| 835 | if (rdev->pm.dpm.thermal.high_to_low) |
| 836 | /* switch back the user state */ |
| 837 | dpm_state = rdev->pm.dpm.user_state; |
| 838 | } |
Alex Deucher | 6032034 | 2013-07-24 14:59:48 -0400 | [diff] [blame] | 839 | mutex_lock(&rdev->pm.mutex); |
| 840 | if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL) |
| 841 | rdev->pm.dpm.thermal_active = true; |
| 842 | else |
| 843 | rdev->pm.dpm.thermal_active = false; |
| 844 | rdev->pm.dpm.state = dpm_state; |
| 845 | mutex_unlock(&rdev->pm.mutex); |
| 846 | |
| 847 | radeon_pm_compute_clocks(rdev); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 848 | } |
| 849 | |
Alex Deucher | 3899ca8 | 2015-03-18 17:05:10 -0400 | [diff] [blame] | 850 | static bool radeon_dpm_single_display(struct radeon_device *rdev) |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 851 | { |
Alex Deucher | 4878306 | 2013-07-08 11:35:06 -0400 | [diff] [blame] | 852 | bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? |
| 853 | true : false; |
| 854 | |
| 855 | /* check if the vblank period is too short to adjust the mclk */ |
| 856 | if (single_display && rdev->asic->dpm.vblank_too_short) { |
| 857 | if (radeon_dpm_vblank_too_short(rdev)) |
| 858 | single_display = false; |
| 859 | } |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 860 | |
Alex Deucher | 951caa6 | 2015-02-18 00:59:45 -0500 | [diff] [blame] | 861 | /* 120hz tends to be problematic even if they are under the |
| 862 | * vblank limit. |
| 863 | */ |
| 864 | if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120)) |
| 865 | single_display = false; |
| 866 | |
Alex Deucher | 3899ca8 | 2015-03-18 17:05:10 -0400 | [diff] [blame] | 867 | return single_display; |
| 868 | } |
| 869 | |
| 870 | static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev, |
| 871 | enum radeon_pm_state_type dpm_state) |
| 872 | { |
| 873 | int i; |
| 874 | struct radeon_ps *ps; |
| 875 | u32 ui_class; |
| 876 | bool single_display = radeon_dpm_single_display(rdev); |
| 877 | |
Alex Deucher | edcaa5b | 2013-07-05 11:48:31 -0400 | [diff] [blame] | 878 | /* certain older asics have a separare 3D performance state, |
| 879 | * so try that first if the user selected performance |
| 880 | */ |
| 881 | if (dpm_state == POWER_STATE_TYPE_PERFORMANCE) |
| 882 | dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 883 | /* balanced states don't exist at the moment */ |
| 884 | if (dpm_state == POWER_STATE_TYPE_BALANCED) |
| 885 | dpm_state = POWER_STATE_TYPE_PERFORMANCE; |
| 886 | |
Alex Deucher | edcaa5b | 2013-07-05 11:48:31 -0400 | [diff] [blame] | 887 | restart_search: |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 888 | /* Pick the best power state based on current conditions */ |
| 889 | for (i = 0; i < rdev->pm.dpm.num_ps; i++) { |
| 890 | ps = &rdev->pm.dpm.ps[i]; |
| 891 | ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; |
| 892 | switch (dpm_state) { |
| 893 | /* user states */ |
| 894 | case POWER_STATE_TYPE_BATTERY: |
| 895 | if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { |
| 896 | if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { |
Alex Deucher | 4878306 | 2013-07-08 11:35:06 -0400 | [diff] [blame] | 897 | if (single_display) |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 898 | return ps; |
| 899 | } else |
| 900 | return ps; |
| 901 | } |
| 902 | break; |
| 903 | case POWER_STATE_TYPE_BALANCED: |
| 904 | if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) { |
| 905 | if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { |
Alex Deucher | 4878306 | 2013-07-08 11:35:06 -0400 | [diff] [blame] | 906 | if (single_display) |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 907 | return ps; |
| 908 | } else |
| 909 | return ps; |
| 910 | } |
| 911 | break; |
| 912 | case POWER_STATE_TYPE_PERFORMANCE: |
| 913 | if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { |
| 914 | if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { |
Alex Deucher | 4878306 | 2013-07-08 11:35:06 -0400 | [diff] [blame] | 915 | if (single_display) |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 916 | return ps; |
| 917 | } else |
| 918 | return ps; |
| 919 | } |
| 920 | break; |
| 921 | /* internal states */ |
| 922 | case POWER_STATE_TYPE_INTERNAL_UVD: |
Alex Deucher | d4d3278 | 2013-06-11 17:55:39 -0400 | [diff] [blame] | 923 | if (rdev->pm.dpm.uvd_ps) |
| 924 | return rdev->pm.dpm.uvd_ps; |
| 925 | else |
| 926 | break; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 927 | case POWER_STATE_TYPE_INTERNAL_UVD_SD: |
| 928 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) |
| 929 | return ps; |
| 930 | break; |
| 931 | case POWER_STATE_TYPE_INTERNAL_UVD_HD: |
| 932 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) |
| 933 | return ps; |
| 934 | break; |
| 935 | case POWER_STATE_TYPE_INTERNAL_UVD_HD2: |
| 936 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) |
| 937 | return ps; |
| 938 | break; |
| 939 | case POWER_STATE_TYPE_INTERNAL_UVD_MVC: |
| 940 | if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) |
| 941 | return ps; |
| 942 | break; |
| 943 | case POWER_STATE_TYPE_INTERNAL_BOOT: |
| 944 | return rdev->pm.dpm.boot_ps; |
| 945 | case POWER_STATE_TYPE_INTERNAL_THERMAL: |
| 946 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) |
| 947 | return ps; |
| 948 | break; |
| 949 | case POWER_STATE_TYPE_INTERNAL_ACPI: |
| 950 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) |
| 951 | return ps; |
| 952 | break; |
| 953 | case POWER_STATE_TYPE_INTERNAL_ULV: |
| 954 | if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) |
| 955 | return ps; |
| 956 | break; |
Alex Deucher | edcaa5b | 2013-07-05 11:48:31 -0400 | [diff] [blame] | 957 | case POWER_STATE_TYPE_INTERNAL_3DPERF: |
| 958 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) |
| 959 | return ps; |
| 960 | break; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 961 | default: |
| 962 | break; |
| 963 | } |
| 964 | } |
| 965 | /* use a fallback state if we didn't match */ |
| 966 | switch (dpm_state) { |
| 967 | case POWER_STATE_TYPE_INTERNAL_UVD_SD: |
Alex Deucher | ce3537d | 2013-07-24 12:12:49 -0400 | [diff] [blame] | 968 | dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; |
| 969 | goto restart_search; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 970 | case POWER_STATE_TYPE_INTERNAL_UVD_HD: |
| 971 | case POWER_STATE_TYPE_INTERNAL_UVD_HD2: |
| 972 | case POWER_STATE_TYPE_INTERNAL_UVD_MVC: |
Alex Deucher | d4d3278 | 2013-06-11 17:55:39 -0400 | [diff] [blame] | 973 | if (rdev->pm.dpm.uvd_ps) { |
| 974 | return rdev->pm.dpm.uvd_ps; |
| 975 | } else { |
| 976 | dpm_state = POWER_STATE_TYPE_PERFORMANCE; |
| 977 | goto restart_search; |
| 978 | } |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 979 | case POWER_STATE_TYPE_INTERNAL_THERMAL: |
| 980 | dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI; |
| 981 | goto restart_search; |
| 982 | case POWER_STATE_TYPE_INTERNAL_ACPI: |
| 983 | dpm_state = POWER_STATE_TYPE_BATTERY; |
| 984 | goto restart_search; |
| 985 | case POWER_STATE_TYPE_BATTERY: |
Alex Deucher | edcaa5b | 2013-07-05 11:48:31 -0400 | [diff] [blame] | 986 | case POWER_STATE_TYPE_BALANCED: |
| 987 | case POWER_STATE_TYPE_INTERNAL_3DPERF: |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 988 | dpm_state = POWER_STATE_TYPE_PERFORMANCE; |
| 989 | goto restart_search; |
| 990 | default: |
| 991 | break; |
| 992 | } |
| 993 | |
| 994 | return NULL; |
| 995 | } |
| 996 | |
| 997 | static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev) |
| 998 | { |
| 999 | int i; |
| 1000 | struct radeon_ps *ps; |
| 1001 | enum radeon_pm_state_type dpm_state; |
Alex Deucher | 84dd192 | 2013-01-16 12:52:04 -0500 | [diff] [blame] | 1002 | int ret; |
Alex Deucher | 3899ca8 | 2015-03-18 17:05:10 -0400 | [diff] [blame] | 1003 | bool single_display = radeon_dpm_single_display(rdev); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1004 | |
| 1005 | /* if dpm init failed */ |
| 1006 | if (!rdev->pm.dpm_enabled) |
| 1007 | return; |
| 1008 | |
| 1009 | if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) { |
| 1010 | /* add other state override checks here */ |
Alex Deucher | 8a22755 | 2013-06-21 15:12:57 -0400 | [diff] [blame] | 1011 | if ((!rdev->pm.dpm.thermal_active) && |
| 1012 | (!rdev->pm.dpm.uvd_active)) |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1013 | rdev->pm.dpm.state = rdev->pm.dpm.user_state; |
| 1014 | } |
| 1015 | dpm_state = rdev->pm.dpm.state; |
| 1016 | |
| 1017 | ps = radeon_dpm_pick_power_state(rdev, dpm_state); |
| 1018 | if (ps) |
Alex Deucher | 89c9bc5 | 2013-01-16 14:40:26 -0500 | [diff] [blame] | 1019 | rdev->pm.dpm.requested_ps = ps; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1020 | else |
| 1021 | return; |
| 1022 | |
Alex Deucher | d22b7e4 | 2012-11-29 19:27:56 -0500 | [diff] [blame] | 1023 | /* no need to reprogram if nothing changed unless we are on BTC+ */ |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1024 | if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) { |
Alex Deucher | b62d628 | 2013-08-20 20:29:05 -0400 | [diff] [blame] | 1025 | /* vce just modifies an existing state so force a change */ |
| 1026 | if (ps->vce_active != rdev->pm.dpm.vce_active) |
| 1027 | goto force; |
Alex Deucher | 3899ca8 | 2015-03-18 17:05:10 -0400 | [diff] [blame] | 1028 | /* user has made a display change (such as timing) */ |
| 1029 | if (rdev->pm.dpm.single_display != single_display) |
| 1030 | goto force; |
Alex Deucher | d22b7e4 | 2012-11-29 19:27:56 -0500 | [diff] [blame] | 1031 | if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) { |
| 1032 | /* for pre-BTC and APUs if the num crtcs changed but state is the same, |
| 1033 | * all we need to do is update the display configuration. |
| 1034 | */ |
| 1035 | if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) { |
| 1036 | /* update display watermarks based on new power state */ |
| 1037 | radeon_bandwidth_update(rdev); |
| 1038 | /* update displays */ |
| 1039 | radeon_dpm_display_configuration_changed(rdev); |
| 1040 | rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; |
| 1041 | rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; |
| 1042 | } |
| 1043 | return; |
| 1044 | } else { |
| 1045 | /* for BTC+ if the num crtcs hasn't changed and state is the same, |
| 1046 | * nothing to do, if the num crtcs is > 1 and state is the same, |
| 1047 | * update display configuration. |
| 1048 | */ |
| 1049 | if (rdev->pm.dpm.new_active_crtcs == |
| 1050 | rdev->pm.dpm.current_active_crtcs) { |
| 1051 | return; |
| 1052 | } else { |
| 1053 | if ((rdev->pm.dpm.current_active_crtc_count > 1) && |
| 1054 | (rdev->pm.dpm.new_active_crtc_count > 1)) { |
| 1055 | /* update display watermarks based on new power state */ |
| 1056 | radeon_bandwidth_update(rdev); |
| 1057 | /* update displays */ |
| 1058 | radeon_dpm_display_configuration_changed(rdev); |
| 1059 | rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; |
| 1060 | rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; |
| 1061 | return; |
| 1062 | } |
| 1063 | } |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1064 | } |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1065 | } |
| 1066 | |
Alex Deucher | b62d628 | 2013-08-20 20:29:05 -0400 | [diff] [blame] | 1067 | force: |
Alex Deucher | 033a37d | 2013-10-23 18:35:43 -0400 | [diff] [blame] | 1068 | if (radeon_dpm == 1) { |
| 1069 | printk("switching from power state:\n"); |
| 1070 | radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps); |
| 1071 | printk("switching to power state:\n"); |
| 1072 | radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps); |
| 1073 | } |
Alex Deucher | b62d628 | 2013-08-20 20:29:05 -0400 | [diff] [blame] | 1074 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1075 | down_write(&rdev->pm.mclk_lock); |
| 1076 | mutex_lock(&rdev->ring_lock); |
| 1077 | |
Alex Deucher | b62d628 | 2013-08-20 20:29:05 -0400 | [diff] [blame] | 1078 | /* update whether vce is active */ |
| 1079 | ps->vce_active = rdev->pm.dpm.vce_active; |
| 1080 | |
Alex Deucher | 89c9bc5 | 2013-01-16 14:40:26 -0500 | [diff] [blame] | 1081 | ret = radeon_dpm_pre_set_power_state(rdev); |
| 1082 | if (ret) |
| 1083 | goto done; |
Alex Deucher | 84dd192 | 2013-01-16 12:52:04 -0500 | [diff] [blame] | 1084 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1085 | /* update display watermarks based on new power state */ |
| 1086 | radeon_bandwidth_update(rdev); |
Alex Deucher | d74e766 | 2016-03-08 11:31:00 -0500 | [diff] [blame] | 1087 | /* update displays */ |
| 1088 | radeon_dpm_display_configuration_changed(rdev); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1089 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1090 | /* wait for the rings to drain */ |
| 1091 | for (i = 0; i < RADEON_NUM_RINGS; i++) { |
| 1092 | struct radeon_ring *ring = &rdev->ring[i]; |
| 1093 | if (ring->ready) |
Christian König | 3761552 | 2014-02-18 15:58:31 +0100 | [diff] [blame] | 1094 | radeon_fence_wait_empty(rdev, i); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1095 | } |
| 1096 | |
| 1097 | /* program the new power state */ |
| 1098 | radeon_dpm_set_power_state(rdev); |
| 1099 | |
| 1100 | /* update current power state */ |
| 1101 | rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps; |
| 1102 | |
Alex Deucher | 89c9bc5 | 2013-01-16 14:40:26 -0500 | [diff] [blame] | 1103 | radeon_dpm_post_set_power_state(rdev); |
Alex Deucher | 84dd192 | 2013-01-16 12:52:04 -0500 | [diff] [blame] | 1104 | |
Alex Deucher | 5e031d9 | 2016-02-24 17:38:38 -0500 | [diff] [blame] | 1105 | rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; |
| 1106 | rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; |
| 1107 | rdev->pm.dpm.single_display = single_display; |
| 1108 | |
Alex Deucher | 1cd8b21 | 2013-09-13 14:07:03 -0400 | [diff] [blame] | 1109 | if (rdev->asic->dpm.force_performance_level) { |
Alex Deucher | 14ac88a | 2013-10-23 17:31:42 -0400 | [diff] [blame] | 1110 | if (rdev->pm.dpm.thermal_active) { |
| 1111 | enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; |
Alex Deucher | 1cd8b21 | 2013-09-13 14:07:03 -0400 | [diff] [blame] | 1112 | /* force low perf level for thermal */ |
| 1113 | radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW); |
Alex Deucher | 14ac88a | 2013-10-23 17:31:42 -0400 | [diff] [blame] | 1114 | /* save the user's level */ |
| 1115 | rdev->pm.dpm.forced_level = level; |
| 1116 | } else { |
| 1117 | /* otherwise, user selected level */ |
| 1118 | radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level); |
| 1119 | } |
Alex Deucher | 6032034 | 2013-07-24 14:59:48 -0400 | [diff] [blame] | 1120 | } |
| 1121 | |
Alex Deucher | 84dd192 | 2013-01-16 12:52:04 -0500 | [diff] [blame] | 1122 | done: |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1123 | mutex_unlock(&rdev->ring_lock); |
| 1124 | up_write(&rdev->pm.mclk_lock); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1125 | } |
| 1126 | |
Alex Deucher | ce3537d | 2013-07-24 12:12:49 -0400 | [diff] [blame] | 1127 | void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable) |
| 1128 | { |
| 1129 | enum radeon_pm_state_type dpm_state; |
| 1130 | |
Alex Deucher | 9e9d976 | 2013-07-31 18:13:23 -0400 | [diff] [blame] | 1131 | if (rdev->asic->dpm.powergate_uvd) { |
Alex Deucher | ce3537d | 2013-07-24 12:12:49 -0400 | [diff] [blame] | 1132 | mutex_lock(&rdev->pm.mutex); |
Christian König | 8158eb9 | 2014-01-10 16:05:05 +0100 | [diff] [blame] | 1133 | /* don't powergate anything if we |
| 1134 | have active but pause streams */ |
| 1135 | enable |= rdev->pm.dpm.sd > 0; |
| 1136 | enable |= rdev->pm.dpm.hd > 0; |
Alex Deucher | 9e9d976 | 2013-07-31 18:13:23 -0400 | [diff] [blame] | 1137 | /* enable/disable UVD */ |
| 1138 | radeon_dpm_powergate_uvd(rdev, !enable); |
Alex Deucher | ce3537d | 2013-07-24 12:12:49 -0400 | [diff] [blame] | 1139 | mutex_unlock(&rdev->pm.mutex); |
| 1140 | } else { |
Alex Deucher | 9e9d976 | 2013-07-31 18:13:23 -0400 | [diff] [blame] | 1141 | if (enable) { |
| 1142 | mutex_lock(&rdev->pm.mutex); |
| 1143 | rdev->pm.dpm.uvd_active = true; |
Alex Deucher | 0690a22 | 2014-06-07 11:31:25 -0400 | [diff] [blame] | 1144 | /* disable this for now */ |
| 1145 | #if 0 |
Alex Deucher | 9e9d976 | 2013-07-31 18:13:23 -0400 | [diff] [blame] | 1146 | if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) |
| 1147 | dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD; |
| 1148 | else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) |
| 1149 | dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; |
| 1150 | else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1)) |
| 1151 | dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; |
| 1152 | else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) |
| 1153 | dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2; |
| 1154 | else |
Alex Deucher | 0690a22 | 2014-06-07 11:31:25 -0400 | [diff] [blame] | 1155 | #endif |
Alex Deucher | 9e9d976 | 2013-07-31 18:13:23 -0400 | [diff] [blame] | 1156 | dpm_state = POWER_STATE_TYPE_INTERNAL_UVD; |
| 1157 | rdev->pm.dpm.state = dpm_state; |
| 1158 | mutex_unlock(&rdev->pm.mutex); |
| 1159 | } else { |
| 1160 | mutex_lock(&rdev->pm.mutex); |
| 1161 | rdev->pm.dpm.uvd_active = false; |
| 1162 | mutex_unlock(&rdev->pm.mutex); |
| 1163 | } |
Alex Deucher | ce3537d | 2013-07-24 12:12:49 -0400 | [diff] [blame] | 1164 | |
Alex Deucher | 9e9d976 | 2013-07-31 18:13:23 -0400 | [diff] [blame] | 1165 | radeon_pm_compute_clocks(rdev); |
| 1166 | } |
Alex Deucher | ce3537d | 2013-07-24 12:12:49 -0400 | [diff] [blame] | 1167 | } |
| 1168 | |
Alex Deucher | 03afe6f | 2013-08-23 11:56:26 -0400 | [diff] [blame] | 1169 | void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable) |
| 1170 | { |
| 1171 | if (enable) { |
| 1172 | mutex_lock(&rdev->pm.mutex); |
| 1173 | rdev->pm.dpm.vce_active = true; |
| 1174 | /* XXX select vce level based on ring/task */ |
| 1175 | rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL; |
| 1176 | mutex_unlock(&rdev->pm.mutex); |
| 1177 | } else { |
| 1178 | mutex_lock(&rdev->pm.mutex); |
| 1179 | rdev->pm.dpm.vce_active = false; |
| 1180 | mutex_unlock(&rdev->pm.mutex); |
| 1181 | } |
| 1182 | |
| 1183 | radeon_pm_compute_clocks(rdev); |
| 1184 | } |
| 1185 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1186 | static void radeon_pm_suspend_old(struct radeon_device *rdev) |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1187 | { |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1188 | mutex_lock(&rdev->pm.mutex); |
Rafael J. Wysocki | 3f53eb6 | 2010-06-17 23:02:27 +0000 | [diff] [blame] | 1189 | if (rdev->pm.pm_method == PM_METHOD_DYNPM) { |
Rafael J. Wysocki | 3f53eb6 | 2010-06-17 23:02:27 +0000 | [diff] [blame] | 1190 | if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) |
| 1191 | rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; |
Rafael J. Wysocki | 3f53eb6 | 2010-06-17 23:02:27 +0000 | [diff] [blame] | 1192 | } |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1193 | mutex_unlock(&rdev->pm.mutex); |
Tejun Heo | 32c87fc | 2011-01-03 14:49:32 +0100 | [diff] [blame] | 1194 | |
| 1195 | cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1196 | } |
| 1197 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1198 | static void radeon_pm_suspend_dpm(struct radeon_device *rdev) |
| 1199 | { |
| 1200 | mutex_lock(&rdev->pm.mutex); |
| 1201 | /* disable dpm */ |
| 1202 | radeon_dpm_disable(rdev); |
| 1203 | /* reset the power state */ |
| 1204 | rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; |
| 1205 | rdev->pm.dpm_enabled = false; |
| 1206 | mutex_unlock(&rdev->pm.mutex); |
| 1207 | } |
| 1208 | |
| 1209 | void radeon_pm_suspend(struct radeon_device *rdev) |
| 1210 | { |
| 1211 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
| 1212 | radeon_pm_suspend_dpm(rdev); |
| 1213 | else |
| 1214 | radeon_pm_suspend_old(rdev); |
| 1215 | } |
| 1216 | |
| 1217 | static void radeon_pm_resume_old(struct radeon_device *rdev) |
Rafał Miłecki | d0d6cb8 | 2010-03-02 22:06:52 +0100 | [diff] [blame] | 1218 | { |
Alex Deucher | ed18a36 | 2011-01-06 21:19:32 -0500 | [diff] [blame] | 1219 | /* set up the default clocks if the MC ucode is loaded */ |
Alex Deucher | 2e3b3b1 | 2012-09-14 10:59:26 -0400 | [diff] [blame] | 1220 | if ((rdev->family >= CHIP_BARTS) && |
Alex Deucher | 3609918 | 2013-09-21 14:37:49 -0400 | [diff] [blame] | 1221 | (rdev->family <= CHIP_CAYMAN) && |
Alex Deucher | 2e3b3b1 | 2012-09-14 10:59:26 -0400 | [diff] [blame] | 1222 | rdev->mc_fw) { |
Alex Deucher | ed18a36 | 2011-01-06 21:19:32 -0500 | [diff] [blame] | 1223 | if (rdev->pm.default_vddc) |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 1224 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, |
| 1225 | SET_VOLTAGE_TYPE_ASIC_VDDC); |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 1226 | if (rdev->pm.default_vddci) |
| 1227 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, |
| 1228 | SET_VOLTAGE_TYPE_ASIC_VDDCI); |
Alex Deucher | ed18a36 | 2011-01-06 21:19:32 -0500 | [diff] [blame] | 1229 | if (rdev->pm.default_sclk) |
| 1230 | radeon_set_engine_clock(rdev, rdev->pm.default_sclk); |
| 1231 | if (rdev->pm.default_mclk) |
| 1232 | radeon_set_memory_clock(rdev, rdev->pm.default_mclk); |
| 1233 | } |
Alex Deucher | f8ed8b4 | 2010-06-07 17:49:51 -0400 | [diff] [blame] | 1234 | /* asic init will reset the default power state */ |
| 1235 | mutex_lock(&rdev->pm.mutex); |
| 1236 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
| 1237 | rdev->pm.current_clock_mode_index = 0; |
Alex Deucher | 9ace9f7 | 2011-01-06 21:19:26 -0500 | [diff] [blame] | 1238 | rdev->pm.current_sclk = rdev->pm.default_sclk; |
| 1239 | rdev->pm.current_mclk = rdev->pm.default_mclk; |
Michel Dänzer | 3701695 | 2014-01-08 11:40:20 +0900 | [diff] [blame] | 1240 | if (rdev->pm.power_state) { |
| 1241 | rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; |
| 1242 | rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; |
| 1243 | } |
Rafael J. Wysocki | 3f53eb6 | 2010-06-17 23:02:27 +0000 | [diff] [blame] | 1244 | if (rdev->pm.pm_method == PM_METHOD_DYNPM |
| 1245 | && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { |
| 1246 | rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; |
Tejun Heo | 32c87fc | 2011-01-03 14:49:32 +0100 | [diff] [blame] | 1247 | schedule_delayed_work(&rdev->pm.dynpm_idle_work, |
| 1248 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); |
Rafael J. Wysocki | 3f53eb6 | 2010-06-17 23:02:27 +0000 | [diff] [blame] | 1249 | } |
Alex Deucher | f8ed8b4 | 2010-06-07 17:49:51 -0400 | [diff] [blame] | 1250 | mutex_unlock(&rdev->pm.mutex); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1251 | radeon_pm_compute_clocks(rdev); |
Rafał Miłecki | d0d6cb8 | 2010-03-02 22:06:52 +0100 | [diff] [blame] | 1252 | } |
| 1253 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1254 | static void radeon_pm_resume_dpm(struct radeon_device *rdev) |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1255 | { |
Dave Airlie | 26481fb | 2010-05-18 19:00:14 +1000 | [diff] [blame] | 1256 | int ret; |
Dan Carpenter | 0d18abe | 2010-08-09 21:59:42 +0200 | [diff] [blame] | 1257 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1258 | /* asic init will reset to the boot state */ |
| 1259 | mutex_lock(&rdev->pm.mutex); |
| 1260 | rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; |
| 1261 | radeon_dpm_setup_asic(rdev); |
| 1262 | ret = radeon_dpm_enable(rdev); |
| 1263 | mutex_unlock(&rdev->pm.mutex); |
Alex Deucher | e14cd2b | 2013-12-19 16:17:47 -0500 | [diff] [blame] | 1264 | if (ret) |
| 1265 | goto dpm_resume_fail; |
Alex Deucher | e14cd2b | 2013-12-19 16:17:47 -0500 | [diff] [blame] | 1266 | rdev->pm.dpm_enabled = true; |
Alex Deucher | e14cd2b | 2013-12-19 16:17:47 -0500 | [diff] [blame] | 1267 | return; |
| 1268 | |
| 1269 | dpm_resume_fail: |
| 1270 | DRM_ERROR("radeon: dpm resume failed\n"); |
| 1271 | if ((rdev->family >= CHIP_BARTS) && |
| 1272 | (rdev->family <= CHIP_CAYMAN) && |
| 1273 | rdev->mc_fw) { |
| 1274 | if (rdev->pm.default_vddc) |
| 1275 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, |
| 1276 | SET_VOLTAGE_TYPE_ASIC_VDDC); |
| 1277 | if (rdev->pm.default_vddci) |
| 1278 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, |
| 1279 | SET_VOLTAGE_TYPE_ASIC_VDDCI); |
| 1280 | if (rdev->pm.default_sclk) |
| 1281 | radeon_set_engine_clock(rdev, rdev->pm.default_sclk); |
| 1282 | if (rdev->pm.default_mclk) |
| 1283 | radeon_set_memory_clock(rdev, rdev->pm.default_mclk); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1284 | } |
| 1285 | } |
| 1286 | |
| 1287 | void radeon_pm_resume(struct radeon_device *rdev) |
| 1288 | { |
| 1289 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
| 1290 | radeon_pm_resume_dpm(rdev); |
| 1291 | else |
| 1292 | radeon_pm_resume_old(rdev); |
| 1293 | } |
| 1294 | |
| 1295 | static int radeon_pm_init_old(struct radeon_device *rdev) |
| 1296 | { |
| 1297 | int ret; |
| 1298 | |
Alex Deucher | f8ed8b4 | 2010-06-07 17:49:51 -0400 | [diff] [blame] | 1299 | rdev->pm.profile = PM_PROFILE_DEFAULT; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1300 | rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; |
| 1301 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; |
| 1302 | rdev->pm.dynpm_can_upclock = true; |
| 1303 | rdev->pm.dynpm_can_downclock = true; |
Alex Deucher | 9ace9f7 | 2011-01-06 21:19:26 -0500 | [diff] [blame] | 1304 | rdev->pm.default_sclk = rdev->clock.default_sclk; |
| 1305 | rdev->pm.default_mclk = rdev->clock.default_mclk; |
Alex Deucher | f8ed8b4 | 2010-06-07 17:49:51 -0400 | [diff] [blame] | 1306 | rdev->pm.current_sclk = rdev->clock.default_sclk; |
| 1307 | rdev->pm.current_mclk = rdev->clock.default_mclk; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 1308 | rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1309 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1310 | if (rdev->bios) { |
| 1311 | if (rdev->is_atom_bios) |
| 1312 | radeon_atombios_get_power_modes(rdev); |
| 1313 | else |
| 1314 | radeon_combios_get_power_modes(rdev); |
Rafał Miłecki | f712d0c | 2010-06-07 18:29:44 -0400 | [diff] [blame] | 1315 | radeon_pm_print_states(rdev); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1316 | radeon_pm_init_profile(rdev); |
Alex Deucher | ed18a36 | 2011-01-06 21:19:32 -0500 | [diff] [blame] | 1317 | /* set up the default clocks if the MC ucode is loaded */ |
Alex Deucher | 2e3b3b1 | 2012-09-14 10:59:26 -0400 | [diff] [blame] | 1318 | if ((rdev->family >= CHIP_BARTS) && |
Alex Deucher | 3609918 | 2013-09-21 14:37:49 -0400 | [diff] [blame] | 1319 | (rdev->family <= CHIP_CAYMAN) && |
Alex Deucher | 2e3b3b1 | 2012-09-14 10:59:26 -0400 | [diff] [blame] | 1320 | rdev->mc_fw) { |
Alex Deucher | ed18a36 | 2011-01-06 21:19:32 -0500 | [diff] [blame] | 1321 | if (rdev->pm.default_vddc) |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 1322 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, |
| 1323 | SET_VOLTAGE_TYPE_ASIC_VDDC); |
Alex Deucher | 4639dd2 | 2011-07-25 18:50:08 -0400 | [diff] [blame] | 1324 | if (rdev->pm.default_vddci) |
| 1325 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, |
| 1326 | SET_VOLTAGE_TYPE_ASIC_VDDCI); |
Alex Deucher | ed18a36 | 2011-01-06 21:19:32 -0500 | [diff] [blame] | 1327 | if (rdev->pm.default_sclk) |
| 1328 | radeon_set_engine_clock(rdev, rdev->pm.default_sclk); |
| 1329 | if (rdev->pm.default_mclk) |
| 1330 | radeon_set_memory_clock(rdev, rdev->pm.default_mclk); |
| 1331 | } |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1332 | } |
| 1333 | |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 1334 | /* set up the internal thermal sensor if applicable */ |
Dan Carpenter | 0d18abe | 2010-08-09 21:59:42 +0200 | [diff] [blame] | 1335 | ret = radeon_hwmon_init(rdev); |
| 1336 | if (ret) |
| 1337 | return ret; |
Tejun Heo | 32c87fc | 2011-01-03 14:49:32 +0100 | [diff] [blame] | 1338 | |
| 1339 | INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); |
| 1340 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1341 | if (rdev->pm.num_power_states > 1) { |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1342 | if (radeon_debugfs_pm_init(rdev)) { |
| 1343 | DRM_ERROR("Failed to register debugfs file for PM!\n"); |
| 1344 | } |
| 1345 | |
| 1346 | DRM_INFO("radeon: power management initialized\n"); |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1347 | } |
| 1348 | |
| 1349 | return 0; |
| 1350 | } |
| 1351 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1352 | static void radeon_dpm_print_power_states(struct radeon_device *rdev) |
| 1353 | { |
| 1354 | int i; |
| 1355 | |
| 1356 | for (i = 0; i < rdev->pm.dpm.num_ps; i++) { |
| 1357 | printk("== power state %d ==\n", i); |
| 1358 | radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]); |
| 1359 | } |
| 1360 | } |
| 1361 | |
| 1362 | static int radeon_pm_init_dpm(struct radeon_device *rdev) |
| 1363 | { |
| 1364 | int ret; |
| 1365 | |
Alex Deucher | 1cd8b21 | 2013-09-13 14:07:03 -0400 | [diff] [blame] | 1366 | /* default to balanced state */ |
Alex Deucher | edcaa5b | 2013-07-05 11:48:31 -0400 | [diff] [blame] | 1367 | rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; |
| 1368 | rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; |
Alex Deucher | 1cd8b21 | 2013-09-13 14:07:03 -0400 | [diff] [blame] | 1369 | rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1370 | rdev->pm.default_sclk = rdev->clock.default_sclk; |
| 1371 | rdev->pm.default_mclk = rdev->clock.default_mclk; |
| 1372 | rdev->pm.current_sclk = rdev->clock.default_sclk; |
| 1373 | rdev->pm.current_mclk = rdev->clock.default_mclk; |
| 1374 | rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; |
| 1375 | |
| 1376 | if (rdev->bios && rdev->is_atom_bios) |
| 1377 | radeon_atombios_get_power_modes(rdev); |
| 1378 | else |
| 1379 | return -EINVAL; |
| 1380 | |
| 1381 | /* set up the internal thermal sensor if applicable */ |
| 1382 | ret = radeon_hwmon_init(rdev); |
| 1383 | if (ret) |
| 1384 | return ret; |
| 1385 | |
| 1386 | INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler); |
| 1387 | mutex_lock(&rdev->pm.mutex); |
| 1388 | radeon_dpm_init(rdev); |
| 1389 | rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; |
Alex Deucher | 033a37d | 2013-10-23 18:35:43 -0400 | [diff] [blame] | 1390 | if (radeon_dpm == 1) |
| 1391 | radeon_dpm_print_power_states(rdev); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1392 | radeon_dpm_setup_asic(rdev); |
| 1393 | ret = radeon_dpm_enable(rdev); |
| 1394 | mutex_unlock(&rdev->pm.mutex); |
Alex Deucher | e14cd2b | 2013-12-19 16:17:47 -0500 | [diff] [blame] | 1395 | if (ret) |
| 1396 | goto dpm_failed; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1397 | rdev->pm.dpm_enabled = true; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1398 | |
Alex Deucher | bb5abf9 | 2013-12-18 13:39:58 -0500 | [diff] [blame] | 1399 | if (radeon_debugfs_pm_init(rdev)) { |
| 1400 | DRM_ERROR("Failed to register debugfs file for dpm!\n"); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1401 | } |
| 1402 | |
Alex Deucher | bb5abf9 | 2013-12-18 13:39:58 -0500 | [diff] [blame] | 1403 | DRM_INFO("radeon: dpm initialized\n"); |
| 1404 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1405 | return 0; |
Alex Deucher | e14cd2b | 2013-12-19 16:17:47 -0500 | [diff] [blame] | 1406 | |
| 1407 | dpm_failed: |
| 1408 | rdev->pm.dpm_enabled = false; |
| 1409 | if ((rdev->family >= CHIP_BARTS) && |
| 1410 | (rdev->family <= CHIP_CAYMAN) && |
| 1411 | rdev->mc_fw) { |
| 1412 | if (rdev->pm.default_vddc) |
| 1413 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, |
| 1414 | SET_VOLTAGE_TYPE_ASIC_VDDC); |
| 1415 | if (rdev->pm.default_vddci) |
| 1416 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, |
| 1417 | SET_VOLTAGE_TYPE_ASIC_VDDCI); |
| 1418 | if (rdev->pm.default_sclk) |
| 1419 | radeon_set_engine_clock(rdev, rdev->pm.default_sclk); |
| 1420 | if (rdev->pm.default_mclk) |
| 1421 | radeon_set_memory_clock(rdev, rdev->pm.default_mclk); |
| 1422 | } |
| 1423 | DRM_ERROR("radeon: dpm initialization failed\n"); |
| 1424 | return ret; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1425 | } |
| 1426 | |
Alex Deucher | 4369a69 | 2015-01-08 10:46:33 -0500 | [diff] [blame] | 1427 | struct radeon_dpm_quirk { |
| 1428 | u32 chip_vendor; |
| 1429 | u32 chip_device; |
| 1430 | u32 subsys_vendor; |
| 1431 | u32 subsys_device; |
| 1432 | }; |
| 1433 | |
| 1434 | /* cards with dpm stability problems */ |
| 1435 | static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = { |
| 1436 | /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */ |
| 1437 | { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 }, |
| 1438 | /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */ |
| 1439 | { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 }, |
| 1440 | { 0, 0, 0, 0 }, |
| 1441 | }; |
| 1442 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1443 | int radeon_pm_init(struct radeon_device *rdev) |
| 1444 | { |
Alex Deucher | 4369a69 | 2015-01-08 10:46:33 -0500 | [diff] [blame] | 1445 | struct radeon_dpm_quirk *p = radeon_dpm_quirk_list; |
| 1446 | bool disable_dpm = false; |
| 1447 | |
| 1448 | /* Apply dpm quirks */ |
| 1449 | while (p && p->chip_device != 0) { |
| 1450 | if (rdev->pdev->vendor == p->chip_vendor && |
| 1451 | rdev->pdev->device == p->chip_device && |
| 1452 | rdev->pdev->subsystem_vendor == p->subsys_vendor && |
| 1453 | rdev->pdev->subsystem_device == p->subsys_device) { |
| 1454 | disable_dpm = true; |
| 1455 | break; |
| 1456 | } |
| 1457 | ++p; |
| 1458 | } |
| 1459 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1460 | /* enable dpm on rv6xx+ */ |
| 1461 | switch (rdev->family) { |
Alex Deucher | 4a6369e | 2013-04-12 14:04:10 -0400 | [diff] [blame] | 1462 | case CHIP_RV610: |
| 1463 | case CHIP_RV630: |
| 1464 | case CHIP_RV620: |
| 1465 | case CHIP_RV635: |
| 1466 | case CHIP_RV670: |
Alex Deucher | 9d67006 | 2013-04-12 13:59:22 -0400 | [diff] [blame] | 1467 | case CHIP_RS780: |
| 1468 | case CHIP_RS880: |
Alex Deucher | 76e6dce | 2014-04-18 09:08:11 -0400 | [diff] [blame] | 1469 | case CHIP_RV770: |
Alex Deucher | 8a53fa2 | 2013-08-07 16:09:08 -0400 | [diff] [blame] | 1470 | /* DPM requires the RLC, RV770+ dGPU requires SMC */ |
Alex Deucher | 761bfb9 | 2013-08-06 13:34:00 -0400 | [diff] [blame] | 1471 | if (!rdev->rlc_fw) |
| 1472 | rdev->pm.pm_method = PM_METHOD_PROFILE; |
Alex Deucher | 8a53fa2 | 2013-08-07 16:09:08 -0400 | [diff] [blame] | 1473 | else if ((rdev->family >= CHIP_RV770) && |
| 1474 | (!(rdev->flags & RADEON_IS_IGP)) && |
| 1475 | (!rdev->smc_fw)) |
| 1476 | rdev->pm.pm_method = PM_METHOD_PROFILE; |
Alex Deucher | 761bfb9 | 2013-08-06 13:34:00 -0400 | [diff] [blame] | 1477 | else if (radeon_dpm == 1) |
Alex Deucher | 9d67006 | 2013-04-12 13:59:22 -0400 | [diff] [blame] | 1478 | rdev->pm.pm_method = PM_METHOD_DPM; |
| 1479 | else |
| 1480 | rdev->pm.pm_method = PM_METHOD_PROFILE; |
| 1481 | break; |
Alex Deucher | ab70b1d | 2013-11-01 15:16:02 -0400 | [diff] [blame] | 1482 | case CHIP_RV730: |
| 1483 | case CHIP_RV710: |
| 1484 | case CHIP_RV740: |
Alex Deucher | 59f7a2f | 2013-11-01 15:11:34 -0400 | [diff] [blame] | 1485 | case CHIP_CEDAR: |
| 1486 | case CHIP_REDWOOD: |
| 1487 | case CHIP_JUNIPER: |
| 1488 | case CHIP_CYPRESS: |
| 1489 | case CHIP_HEMLOCK: |
Alex Deucher | 5a16f76 | 2013-10-23 17:11:06 -0400 | [diff] [blame] | 1490 | case CHIP_PALM: |
| 1491 | case CHIP_SUMO: |
| 1492 | case CHIP_SUMO2: |
Alex Deucher | c08abf1 | 2014-07-14 12:01:40 -0400 | [diff] [blame] | 1493 | case CHIP_BARTS: |
| 1494 | case CHIP_TURKS: |
| 1495 | case CHIP_CAICOS: |
Alex Deucher | 8f500af | 2014-07-07 17:13:37 -0400 | [diff] [blame] | 1496 | case CHIP_CAYMAN: |
Alex Deucher | 3a11898 | 2013-11-14 10:21:29 -0500 | [diff] [blame] | 1497 | case CHIP_ARUBA: |
Alex Deucher | 68bc778 | 2013-10-23 17:14:06 -0400 | [diff] [blame] | 1498 | case CHIP_TAHITI: |
| 1499 | case CHIP_PITCAIRN: |
| 1500 | case CHIP_VERDE: |
| 1501 | case CHIP_OLAND: |
| 1502 | case CHIP_HAINAN: |
Alex Deucher | 4f22dde | 2013-12-19 17:37:33 -0500 | [diff] [blame] | 1503 | case CHIP_BONAIRE: |
Alex Deucher | e308b1d | 2013-12-19 17:39:17 -0500 | [diff] [blame] | 1504 | case CHIP_KABINI: |
| 1505 | case CHIP_KAVERI: |
Alex Deucher | 4f22dde | 2013-12-19 17:37:33 -0500 | [diff] [blame] | 1506 | case CHIP_HAWAII: |
Samuel Li | 7d032a4 | 2014-04-30 18:40:51 -0400 | [diff] [blame] | 1507 | case CHIP_MULLINS: |
Alex Deucher | 5a16f76 | 2013-10-23 17:11:06 -0400 | [diff] [blame] | 1508 | /* DPM requires the RLC, RV770+ dGPU requires SMC */ |
| 1509 | if (!rdev->rlc_fw) |
| 1510 | rdev->pm.pm_method = PM_METHOD_PROFILE; |
| 1511 | else if ((rdev->family >= CHIP_RV770) && |
| 1512 | (!(rdev->flags & RADEON_IS_IGP)) && |
| 1513 | (!rdev->smc_fw)) |
| 1514 | rdev->pm.pm_method = PM_METHOD_PROFILE; |
Alex Deucher | 4369a69 | 2015-01-08 10:46:33 -0500 | [diff] [blame] | 1515 | else if (disable_dpm && (radeon_dpm == -1)) |
| 1516 | rdev->pm.pm_method = PM_METHOD_PROFILE; |
Alex Deucher | 5a16f76 | 2013-10-23 17:11:06 -0400 | [diff] [blame] | 1517 | else if (radeon_dpm == 0) |
| 1518 | rdev->pm.pm_method = PM_METHOD_PROFILE; |
| 1519 | else |
| 1520 | rdev->pm.pm_method = PM_METHOD_DPM; |
| 1521 | break; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1522 | default: |
| 1523 | /* default to profile method */ |
| 1524 | rdev->pm.pm_method = PM_METHOD_PROFILE; |
| 1525 | break; |
| 1526 | } |
| 1527 | |
| 1528 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
| 1529 | return radeon_pm_init_dpm(rdev); |
| 1530 | else |
| 1531 | return radeon_pm_init_old(rdev); |
| 1532 | } |
| 1533 | |
Alex Deucher | 914a898 | 2013-12-19 11:37:22 -0500 | [diff] [blame] | 1534 | int radeon_pm_late_init(struct radeon_device *rdev) |
| 1535 | { |
| 1536 | int ret = 0; |
| 1537 | |
| 1538 | if (rdev->pm.pm_method == PM_METHOD_DPM) { |
Alex Deucher | 51a4726 | 2015-09-30 16:45:52 -0400 | [diff] [blame] | 1539 | if (rdev->pm.dpm_enabled) { |
Alex Deucher | 49abb26 | 2015-10-23 10:38:52 -0400 | [diff] [blame] | 1540 | if (!rdev->pm.sysfs_initialized) { |
| 1541 | ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state); |
| 1542 | if (ret) |
| 1543 | DRM_ERROR("failed to create device file for dpm state\n"); |
| 1544 | ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); |
| 1545 | if (ret) |
| 1546 | DRM_ERROR("failed to create device file for dpm state\n"); |
| 1547 | /* XXX: these are noops for dpm but are here for backwards compat */ |
| 1548 | ret = device_create_file(rdev->dev, &dev_attr_power_profile); |
| 1549 | if (ret) |
| 1550 | DRM_ERROR("failed to create device file for power profile\n"); |
| 1551 | ret = device_create_file(rdev->dev, &dev_attr_power_method); |
| 1552 | if (ret) |
| 1553 | DRM_ERROR("failed to create device file for power method\n"); |
Alex Deucher | 24dd2f6 | 2015-11-10 13:01:35 -0500 | [diff] [blame] | 1554 | rdev->pm.sysfs_initialized = true; |
Alex Deucher | 49abb26 | 2015-10-23 10:38:52 -0400 | [diff] [blame] | 1555 | } |
Alex Deucher | 51a4726 | 2015-09-30 16:45:52 -0400 | [diff] [blame] | 1556 | |
| 1557 | mutex_lock(&rdev->pm.mutex); |
| 1558 | ret = radeon_dpm_late_enable(rdev); |
| 1559 | mutex_unlock(&rdev->pm.mutex); |
| 1560 | if (ret) { |
| 1561 | rdev->pm.dpm_enabled = false; |
| 1562 | DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); |
| 1563 | } else { |
| 1564 | /* set the dpm state for PX since there won't be |
| 1565 | * a modeset to call this. |
| 1566 | */ |
| 1567 | radeon_pm_compute_clocks(rdev); |
| 1568 | } |
| 1569 | } |
| 1570 | } else { |
Alex Deucher | 49abb26 | 2015-10-23 10:38:52 -0400 | [diff] [blame] | 1571 | if ((rdev->pm.num_power_states > 1) && |
| 1572 | (!rdev->pm.sysfs_initialized)) { |
Alex Deucher | 51a4726 | 2015-09-30 16:45:52 -0400 | [diff] [blame] | 1573 | /* where's the best place to put these? */ |
| 1574 | ret = device_create_file(rdev->dev, &dev_attr_power_profile); |
| 1575 | if (ret) |
| 1576 | DRM_ERROR("failed to create device file for power profile\n"); |
| 1577 | ret = device_create_file(rdev->dev, &dev_attr_power_method); |
| 1578 | if (ret) |
| 1579 | DRM_ERROR("failed to create device file for power method\n"); |
Alex Deucher | 49abb26 | 2015-10-23 10:38:52 -0400 | [diff] [blame] | 1580 | if (!ret) |
| 1581 | rdev->pm.sysfs_initialized = true; |
Alex Deucher | 51a4726 | 2015-09-30 16:45:52 -0400 | [diff] [blame] | 1582 | } |
Alex Deucher | 914a898 | 2013-12-19 11:37:22 -0500 | [diff] [blame] | 1583 | } |
| 1584 | return ret; |
| 1585 | } |
| 1586 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1587 | static void radeon_pm_fini_old(struct radeon_device *rdev) |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 1588 | { |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1589 | if (rdev->pm.num_power_states > 1) { |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 1590 | mutex_lock(&rdev->pm.mutex); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1591 | if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
| 1592 | rdev->pm.profile = PM_PROFILE_DEFAULT; |
| 1593 | radeon_pm_update_profile(rdev); |
| 1594 | radeon_pm_set_clocks(rdev); |
| 1595 | } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1596 | /* reset default clocks */ |
| 1597 | rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; |
| 1598 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; |
| 1599 | radeon_pm_set_clocks(rdev); |
| 1600 | } |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 1601 | mutex_unlock(&rdev->pm.mutex); |
Tejun Heo | 32c87fc | 2011-01-03 14:49:32 +0100 | [diff] [blame] | 1602 | |
| 1603 | cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); |
Alex Deucher | 58e21df | 2010-03-22 13:31:08 -0400 | [diff] [blame] | 1604 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1605 | device_remove_file(rdev->dev, &dev_attr_power_profile); |
| 1606 | device_remove_file(rdev->dev, &dev_attr_power_method); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1607 | } |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 1608 | |
Alex Deucher | cb3e4e7 | 2014-04-15 12:44:32 -0400 | [diff] [blame] | 1609 | radeon_hwmon_fini(rdev); |
Fabian Frederick | 9c24487 | 2014-07-04 21:37:09 +0200 | [diff] [blame] | 1610 | kfree(rdev->pm.power_state); |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 1611 | } |
| 1612 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1613 | static void radeon_pm_fini_dpm(struct radeon_device *rdev) |
| 1614 | { |
| 1615 | if (rdev->pm.num_power_states > 1) { |
| 1616 | mutex_lock(&rdev->pm.mutex); |
| 1617 | radeon_dpm_disable(rdev); |
| 1618 | mutex_unlock(&rdev->pm.mutex); |
| 1619 | |
| 1620 | device_remove_file(rdev->dev, &dev_attr_power_dpm_state); |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 1621 | device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1622 | /* XXX backwards compat */ |
| 1623 | device_remove_file(rdev->dev, &dev_attr_power_profile); |
| 1624 | device_remove_file(rdev->dev, &dev_attr_power_method); |
| 1625 | } |
| 1626 | radeon_dpm_fini(rdev); |
| 1627 | |
Alex Deucher | cb3e4e7 | 2014-04-15 12:44:32 -0400 | [diff] [blame] | 1628 | radeon_hwmon_fini(rdev); |
Fabian Frederick | 9c24487 | 2014-07-04 21:37:09 +0200 | [diff] [blame] | 1629 | kfree(rdev->pm.power_state); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1630 | } |
| 1631 | |
| 1632 | void radeon_pm_fini(struct radeon_device *rdev) |
| 1633 | { |
| 1634 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
| 1635 | radeon_pm_fini_dpm(rdev); |
| 1636 | else |
| 1637 | radeon_pm_fini_old(rdev); |
| 1638 | } |
| 1639 | |
| 1640 | static void radeon_pm_compute_clocks_old(struct radeon_device *rdev) |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1641 | { |
| 1642 | struct drm_device *ddev = rdev->ddev; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1643 | struct drm_crtc *crtc; |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1644 | struct radeon_crtc *radeon_crtc; |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1645 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1646 | if (rdev->pm.num_power_states < 2) |
| 1647 | return; |
| 1648 | |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1649 | mutex_lock(&rdev->pm.mutex); |
| 1650 | |
| 1651 | rdev->pm.active_crtcs = 0; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1652 | rdev->pm.active_crtc_count = 0; |
Alex Deucher | 3ed9a33 | 2014-04-15 12:44:33 -0400 | [diff] [blame] | 1653 | if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { |
| 1654 | list_for_each_entry(crtc, |
| 1655 | &ddev->mode_config.crtc_list, head) { |
| 1656 | radeon_crtc = to_radeon_crtc(crtc); |
| 1657 | if (radeon_crtc->enabled) { |
| 1658 | rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); |
| 1659 | rdev->pm.active_crtc_count++; |
| 1660 | } |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1661 | } |
| 1662 | } |
| 1663 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1664 | if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
| 1665 | radeon_pm_update_profile(rdev); |
| 1666 | radeon_pm_set_clocks(rdev); |
| 1667 | } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { |
| 1668 | if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { |
| 1669 | if (rdev->pm.active_crtc_count > 1) { |
| 1670 | if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { |
| 1671 | cancel_delayed_work(&rdev->pm.dynpm_idle_work); |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 1672 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1673 | rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; |
| 1674 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; |
| 1675 | radeon_pm_get_dynpm_state(rdev); |
| 1676 | radeon_pm_set_clocks(rdev); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1677 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 1678 | DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1679 | } |
| 1680 | } else if (rdev->pm.active_crtc_count == 1) { |
| 1681 | /* TODO: Increase clocks if needed for current mode */ |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1682 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1683 | if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { |
| 1684 | rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; |
| 1685 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; |
| 1686 | radeon_pm_get_dynpm_state(rdev); |
| 1687 | radeon_pm_set_clocks(rdev); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1688 | |
Tejun Heo | 32c87fc | 2011-01-03 14:49:32 +0100 | [diff] [blame] | 1689 | schedule_delayed_work(&rdev->pm.dynpm_idle_work, |
| 1690 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1691 | } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { |
| 1692 | rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; |
Tejun Heo | 32c87fc | 2011-01-03 14:49:32 +0100 | [diff] [blame] | 1693 | schedule_delayed_work(&rdev->pm.dynpm_idle_work, |
| 1694 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 1695 | DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1696 | } |
| 1697 | } else { /* count == 0 */ |
| 1698 | if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { |
| 1699 | cancel_delayed_work(&rdev->pm.dynpm_idle_work); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1700 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1701 | rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; |
| 1702 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; |
| 1703 | radeon_pm_get_dynpm_state(rdev); |
| 1704 | radeon_pm_set_clocks(rdev); |
| 1705 | } |
| 1706 | } |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1707 | } |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1708 | } |
Rafał Miłecki | 73a6d3f | 2010-01-08 00:22:47 +0100 | [diff] [blame] | 1709 | |
| 1710 | mutex_unlock(&rdev->pm.mutex); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1711 | } |
| 1712 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1713 | static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) |
| 1714 | { |
| 1715 | struct drm_device *ddev = rdev->ddev; |
| 1716 | struct drm_crtc *crtc; |
| 1717 | struct radeon_crtc *radeon_crtc; |
| 1718 | |
Alex Deucher | 6c7bcce | 2013-12-18 14:07:14 -0500 | [diff] [blame] | 1719 | if (!rdev->pm.dpm_enabled) |
| 1720 | return; |
| 1721 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1722 | mutex_lock(&rdev->pm.mutex); |
| 1723 | |
Alex Deucher | 5ca302f | 2012-11-30 10:56:57 -0500 | [diff] [blame] | 1724 | /* update active crtc counts */ |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1725 | rdev->pm.dpm.new_active_crtcs = 0; |
| 1726 | rdev->pm.dpm.new_active_crtc_count = 0; |
Alex Deucher | 3ed9a33 | 2014-04-15 12:44:33 -0400 | [diff] [blame] | 1727 | if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { |
| 1728 | list_for_each_entry(crtc, |
| 1729 | &ddev->mode_config.crtc_list, head) { |
| 1730 | radeon_crtc = to_radeon_crtc(crtc); |
| 1731 | if (crtc->enabled) { |
| 1732 | rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); |
| 1733 | rdev->pm.dpm.new_active_crtc_count++; |
| 1734 | } |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1735 | } |
| 1736 | } |
| 1737 | |
Alex Deucher | 5ca302f | 2012-11-30 10:56:57 -0500 | [diff] [blame] | 1738 | /* update battery/ac status */ |
| 1739 | if (power_supply_is_system_supplied() > 0) |
| 1740 | rdev->pm.dpm.ac_power = true; |
| 1741 | else |
| 1742 | rdev->pm.dpm.ac_power = false; |
| 1743 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1744 | radeon_dpm_change_power_state_locked(rdev); |
| 1745 | |
| 1746 | mutex_unlock(&rdev->pm.mutex); |
Alex Deucher | 8a22755 | 2013-06-21 15:12:57 -0400 | [diff] [blame] | 1747 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1748 | } |
| 1749 | |
| 1750 | void radeon_pm_compute_clocks(struct radeon_device *rdev) |
| 1751 | { |
| 1752 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
| 1753 | radeon_pm_compute_clocks_dpm(rdev); |
| 1754 | else |
| 1755 | radeon_pm_compute_clocks_old(rdev); |
| 1756 | } |
| 1757 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1758 | static bool radeon_pm_in_vbl(struct radeon_device *rdev) |
Dave Airlie | f735261 | 2010-02-18 15:58:36 +1000 | [diff] [blame] | 1759 | { |
Mario Kleiner | 75fa0b0 | 2010-10-05 19:57:37 -0400 | [diff] [blame] | 1760 | int crtc, vpos, hpos, vbl_status; |
Dave Airlie | f735261 | 2010-02-18 15:58:36 +1000 | [diff] [blame] | 1761 | bool in_vbl = true; |
| 1762 | |
Mario Kleiner | 75fa0b0 | 2010-10-05 19:57:37 -0400 | [diff] [blame] | 1763 | /* Iterate over all active crtc's. All crtc's must be in vblank, |
| 1764 | * otherwise return in_vbl == false. |
| 1765 | */ |
| 1766 | for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { |
| 1767 | if (rdev->pm.active_crtcs & (1 << crtc)) { |
Mario Kleiner | 5b5561b | 2015-11-25 20:14:31 +0100 | [diff] [blame] | 1768 | vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, |
| 1769 | crtc, |
| 1770 | USE_REAL_VBLANKSTART, |
Ville Syrjälä | 3bb403b | 2015-09-14 22:43:44 +0300 | [diff] [blame] | 1771 | &vpos, &hpos, NULL, NULL, |
| 1772 | &rdev->mode_info.crtcs[crtc]->base.hwmode); |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1773 | if ((vbl_status & DRM_SCANOUTPOS_VALID) && |
Daniel Vetter | 3d3cbd8 | 2014-09-10 17:36:11 +0200 | [diff] [blame] | 1774 | !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK)) |
Dave Airlie | f735261 | 2010-02-18 15:58:36 +1000 | [diff] [blame] | 1775 | in_vbl = false; |
| 1776 | } |
| 1777 | } |
Matthew Garrett | f81f202 | 2010-04-28 12:13:06 -0400 | [diff] [blame] | 1778 | |
| 1779 | return in_vbl; |
| 1780 | } |
| 1781 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1782 | static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) |
Matthew Garrett | f81f202 | 2010-04-28 12:13:06 -0400 | [diff] [blame] | 1783 | { |
| 1784 | u32 stat_crtc = 0; |
| 1785 | bool in_vbl = radeon_pm_in_vbl(rdev); |
| 1786 | |
Dave Airlie | f735261 | 2010-02-18 15:58:36 +1000 | [diff] [blame] | 1787 | if (in_vbl == false) |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 1788 | DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, |
Alex Deucher | bae6b562 | 2010-04-22 13:38:05 -0400 | [diff] [blame] | 1789 | finish ? "exit" : "entry"); |
Dave Airlie | f735261 | 2010-02-18 15:58:36 +1000 | [diff] [blame] | 1790 | return in_vbl; |
| 1791 | } |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1792 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1793 | static void radeon_dynpm_idle_work_handler(struct work_struct *work) |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1794 | { |
| 1795 | struct radeon_device *rdev; |
Matthew Garrett | d9932a3 | 2010-04-26 16:02:26 -0400 | [diff] [blame] | 1796 | int resched; |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1797 | rdev = container_of(work, struct radeon_device, |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1798 | pm.dynpm_idle_work.work); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1799 | |
Matthew Garrett | d9932a3 | 2010-04-26 16:02:26 -0400 | [diff] [blame] | 1800 | resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1801 | mutex_lock(&rdev->pm.mutex); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1802 | if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1803 | int not_processed = 0; |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 1804 | int i; |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1805 | |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 1806 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
Alex Deucher | 0ec0612 | 2012-06-14 15:54:57 -0400 | [diff] [blame] | 1807 | struct radeon_ring *ring = &rdev->ring[i]; |
| 1808 | |
| 1809 | if (ring->ready) { |
| 1810 | not_processed += radeon_fence_count_emitted(rdev, i); |
| 1811 | if (not_processed >= 3) |
| 1812 | break; |
| 1813 | } |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1814 | } |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1815 | |
| 1816 | if (not_processed >= 3) { /* should upclock */ |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1817 | if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { |
| 1818 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; |
| 1819 | } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && |
| 1820 | rdev->pm.dynpm_can_upclock) { |
| 1821 | rdev->pm.dynpm_planned_action = |
| 1822 | DYNPM_ACTION_UPCLOCK; |
| 1823 | rdev->pm.dynpm_action_timeout = jiffies + |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1824 | msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); |
| 1825 | } |
| 1826 | } else if (not_processed == 0) { /* should downclock */ |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1827 | if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { |
| 1828 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; |
| 1829 | } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && |
| 1830 | rdev->pm.dynpm_can_downclock) { |
| 1831 | rdev->pm.dynpm_planned_action = |
| 1832 | DYNPM_ACTION_DOWNCLOCK; |
| 1833 | rdev->pm.dynpm_action_timeout = jiffies + |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1834 | msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); |
| 1835 | } |
| 1836 | } |
| 1837 | |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 1838 | /* Note, radeon_pm_set_clocks is called with static_switch set |
| 1839 | * to false since we want to wait for vbl to avoid flicker. |
| 1840 | */ |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1841 | if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && |
| 1842 | jiffies > rdev->pm.dynpm_action_timeout) { |
| 1843 | radeon_pm_get_dynpm_state(rdev); |
| 1844 | radeon_pm_set_clocks(rdev); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1845 | } |
Rafael J. Wysocki | 3f53eb6 | 2010-06-17 23:02:27 +0000 | [diff] [blame] | 1846 | |
Tejun Heo | 32c87fc | 2011-01-03 14:49:32 +0100 | [diff] [blame] | 1847 | schedule_delayed_work(&rdev->pm.dynpm_idle_work, |
| 1848 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1849 | } |
| 1850 | mutex_unlock(&rdev->pm.mutex); |
Matthew Garrett | d9932a3 | 2010-04-26 16:02:26 -0400 | [diff] [blame] | 1851 | ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1852 | } |
| 1853 | |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1854 | /* |
| 1855 | * Debugfs info |
| 1856 | */ |
| 1857 | #if defined(CONFIG_DEBUG_FS) |
| 1858 | |
| 1859 | static int radeon_debugfs_pm_info(struct seq_file *m, void *data) |
| 1860 | { |
| 1861 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1862 | struct drm_device *dev = node->minor->dev; |
| 1863 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | 4f2f203 | 2014-05-19 19:21:29 -0400 | [diff] [blame] | 1864 | struct drm_device *ddev = rdev->ddev; |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1865 | |
Alex Deucher | 4f2f203 | 2014-05-19 19:21:29 -0400 | [diff] [blame] | 1866 | if ((rdev->flags & RADEON_IS_PX) && |
| 1867 | (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { |
| 1868 | seq_printf(m, "PX asic powered off\n"); |
| 1869 | } else if (rdev->pm.dpm_enabled) { |
Alex Deucher | 1316b79 | 2013-06-28 09:28:39 -0400 | [diff] [blame] | 1870 | mutex_lock(&rdev->pm.mutex); |
| 1871 | if (rdev->asic->dpm.debugfs_print_current_performance_level) |
| 1872 | radeon_dpm_debugfs_print_current_performance_level(rdev, m); |
| 1873 | else |
Alex Deucher | 7137592 | 2013-07-02 09:11:39 -0400 | [diff] [blame] | 1874 | seq_printf(m, "Debugfs support not implemented for this asic\n"); |
Alex Deucher | 1316b79 | 2013-06-28 09:28:39 -0400 | [diff] [blame] | 1875 | mutex_unlock(&rdev->pm.mutex); |
| 1876 | } else { |
| 1877 | seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); |
| 1878 | /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */ |
| 1879 | if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP)) |
| 1880 | seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); |
| 1881 | else |
| 1882 | seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); |
| 1883 | seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); |
| 1884 | if (rdev->asic->pm.get_memory_clock) |
| 1885 | seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); |
| 1886 | if (rdev->pm.current_vddc) |
| 1887 | seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); |
| 1888 | if (rdev->asic->pm.get_pcie_lanes) |
| 1889 | seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); |
| 1890 | } |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1891 | |
| 1892 | return 0; |
| 1893 | } |
| 1894 | |
| 1895 | static struct drm_info_list radeon_pm_info_list[] = { |
| 1896 | {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL}, |
| 1897 | }; |
| 1898 | #endif |
| 1899 | |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1900 | static int radeon_debugfs_pm_init(struct radeon_device *rdev) |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1901 | { |
| 1902 | #if defined(CONFIG_DEBUG_FS) |
| 1903 | return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); |
| 1904 | #else |
| 1905 | return 0; |
| 1906 | #endif |
| 1907 | } |