blob: 658ac977cb56cd7d22b4711b16518f1d4bf71a43 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/slab.h>
10#include <linux/module.h>
11#include <linux/cpumask.h>
Shaohua Li7d715a62008-02-25 09:46:41 +080012#include <linux/pci-aspm.h>
Bjorn Helgaas284f5f92012-04-30 15:21:02 -060013#include <asm-generic/pci-bridge.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090014#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070015
16#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
17#define CARDBUS_RESERVE_BUSNR 3
Linus Torvalds1da177e2005-04-16 15:20:36 -070018
19/* Ugh. Need to stop exporting this to modules. */
20LIST_HEAD(pci_root_buses);
21EXPORT_SYMBOL(pci_root_buses);
22
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080023static int find_anything(struct device *dev, void *data)
24{
25 return 1;
26}
Linus Torvalds1da177e2005-04-16 15:20:36 -070027
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070028/*
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080031 * is no device to be found on the pci_bus_type.
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070032 */
33int no_pci_devices(void)
34{
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080035 struct device *dev;
36 int no_devices;
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070037
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080038 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
40 put_device(dev);
41 return no_devices;
42}
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070043EXPORT_SYMBOL(no_pci_devices);
44
Linus Torvalds1da177e2005-04-16 15:20:36 -070045/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070046 * PCI Bus Class
47 */
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040048static void release_pcibus_dev(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070049{
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040050 struct pci_bus *pci_bus = to_pci_bus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
52 if (pci_bus->bridge)
53 put_device(pci_bus->bridge);
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -070054 pci_bus_remove_resources(pci_bus);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +100055 pci_release_bus_of_node(pci_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 kfree(pci_bus);
57}
58
59static struct class pcibus_class = {
60 .name = "pci_bus",
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040061 .dev_release = &release_pcibus_dev,
Yinghai Lub9d320f2011-05-12 17:11:39 -070062 .dev_attrs = pcibus_dev_attrs,
Linus Torvalds1da177e2005-04-16 15:20:36 -070063};
64
65static int __init pcibus_class_init(void)
66{
67 return class_register(&pcibus_class);
68}
69postcore_initcall(pcibus_class_init);
70
Matthew Wilcox6ac665c2008-07-28 13:38:59 -040071static u64 pci_size(u64 base, u64 maxbase, u64 mask)
Yinghai Lu07eddf32006-11-29 13:53:10 -080072{
73 u64 size = mask & maxbase; /* Find the significant bits */
74 if (!size)
75 return 0;
76
77 /* Get the lowest of them to find the decode size, and
78 from that the extent. */
79 size = (size & ~(size-1)) - 1;
80
81 /* base == maxbase can be valid only if the BAR has
82 already been programmed with all 1s. */
83 if (base == maxbase && ((base | size) & mask) != mask)
84 return 0;
85
86 return size;
87}
88
Bjorn Helgaas28c68212011-06-14 13:04:35 -060089static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
Yinghai Lu07eddf32006-11-29 13:53:10 -080090{
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -060091 u32 mem_type;
Bjorn Helgaas28c68212011-06-14 13:04:35 -060092 unsigned long flags;
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -060093
Matthew Wilcox6ac665c2008-07-28 13:38:59 -040094 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
Bjorn Helgaas28c68212011-06-14 13:04:35 -060095 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
96 flags |= IORESOURCE_IO;
97 return flags;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -040098 }
99
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600100 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
101 flags |= IORESOURCE_MEM;
102 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
103 flags |= IORESOURCE_PREFETCH;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400104
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600105 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
106 switch (mem_type) {
107 case PCI_BASE_ADDRESS_MEM_TYPE_32:
108 break;
109 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
110 dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n");
111 break;
112 case PCI_BASE_ADDRESS_MEM_TYPE_64:
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600113 flags |= IORESOURCE_MEM_64;
114 break;
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600115 default:
116 dev_warn(&dev->dev,
117 "mem unknown type %x treated as 32-bit BAR\n",
118 mem_type);
119 break;
120 }
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600121 return flags;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400122}
123
Yu Zhao0b400c72008-11-22 02:40:40 +0800124/**
125 * pci_read_base - read a PCI BAR
126 * @dev: the PCI device
127 * @type: type of the BAR
128 * @res: resource buffer to be filled in
129 * @pos: BAR position in the config space
130 *
131 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400132 */
Yu Zhao0b400c72008-11-22 02:40:40 +0800133int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400134 struct resource *res, unsigned int pos)
135{
136 u32 l, sz, mask;
Jacob Pan253d2e52010-07-16 10:19:22 -0700137 u16 orig_cmd;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700138 struct pci_bus_region region;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400139
Michael S. Tsirkin1ed67432009-10-29 17:24:59 +0200140 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400141
Jacob Pan253d2e52010-07-16 10:19:22 -0700142 if (!dev->mmio_always_on) {
143 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
144 pci_write_config_word(dev, PCI_COMMAND,
145 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
146 }
147
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400148 res->name = pci_name(dev);
149
150 pci_read_config_dword(dev, pos, &l);
Michael S. Tsirkin1ed67432009-10-29 17:24:59 +0200151 pci_write_config_dword(dev, pos, l | mask);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400152 pci_read_config_dword(dev, pos, &sz);
153 pci_write_config_dword(dev, pos, l);
154
Jacob Pan253d2e52010-07-16 10:19:22 -0700155 if (!dev->mmio_always_on)
156 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
157
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400158 /*
159 * All bits set in sz means the device isn't working properly.
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600160 * If the BAR isn't implemented, all bits must be 0. If it's a
161 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
162 * 1 must be clear.
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400163 */
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600164 if (!sz || sz == 0xffffffff)
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400165 goto fail;
166
167 /*
168 * I don't know how l can have all bits set. Copied from old code.
169 * Maybe it fixes a bug on some ancient platform.
170 */
171 if (l == 0xffffffff)
172 l = 0;
173
174 if (type == pci_bar_unknown) {
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600175 res->flags = decode_bar(dev, l);
176 res->flags |= IORESOURCE_SIZEALIGN;
177 if (res->flags & IORESOURCE_IO) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400178 l &= PCI_BASE_ADDRESS_IO_MASK;
David S. Miller5aceca92011-05-23 17:12:22 -0700179 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400180 } else {
181 l &= PCI_BASE_ADDRESS_MEM_MASK;
182 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
183 }
184 } else {
185 res->flags |= (l & IORESOURCE_ROM_ENABLE);
186 l &= PCI_ROM_ADDRESS_MASK;
187 mask = (u32)PCI_ROM_ADDRESS_MASK;
188 }
189
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600190 if (res->flags & IORESOURCE_MEM_64) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400191 u64 l64 = l;
192 u64 sz64 = sz;
193 u64 mask64 = mask | (u64)~0 << 32;
194
195 pci_read_config_dword(dev, pos + 4, &l);
196 pci_write_config_dword(dev, pos + 4, ~0);
197 pci_read_config_dword(dev, pos + 4, &sz);
198 pci_write_config_dword(dev, pos + 4, l);
199
200 l64 |= ((u64)l << 32);
201 sz64 |= ((u64)sz << 32);
202
203 sz64 = pci_size(l64, sz64, mask64);
204
205 if (!sz64)
206 goto fail;
207
Matthew Wilcoxcc5499c2008-07-28 13:39:00 -0400208 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
Bjorn Helgaas865df572009-11-04 10:32:57 -0700209 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
210 pos);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400211 goto fail;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600212 }
213
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600214 if ((sizeof(resource_size_t) < 8) && l) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400215 /* Address above 32-bit boundary; disable the BAR */
216 pci_write_config_dword(dev, pos, 0);
217 pci_write_config_dword(dev, pos + 4, 0);
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700218 region.start = 0;
219 region.end = sz64;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -0700220 pcibios_bus_to_resource(dev, res, &region);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400221 } else {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700222 region.start = l64;
223 region.end = l64 + sz64;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -0700224 pcibios_bus_to_resource(dev, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600225 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
Bjorn Helgaasa369c792009-10-06 15:33:44 -0600226 pos, res);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400227 }
228 } else {
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600229 sz = pci_size(l, sz, mask);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400230
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600231 if (!sz)
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400232 goto fail;
233
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700234 region.start = l;
235 region.end = l + sz;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -0700236 pcibios_bus_to_resource(dev, res, &region);
Vincent Legollf393d9b2008-10-12 12:26:12 +0200237
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600238 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400239 }
240
241 out:
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600242 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400243 fail:
244 res->flags = 0;
245 goto out;
Yinghai Lu07eddf32006-11-29 13:53:10 -0800246}
247
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
249{
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400250 unsigned int pos, reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400252 for (pos = 0; pos < howmany; pos++) {
253 struct resource *res = &dev->resource[pos];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400255 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 }
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400257
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258 if (rom) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400259 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700260 dev->rom_base_reg = rom;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400261 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
262 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
263 IORESOURCE_SIZEALIGN;
264 __pci_read_base(dev, pci_bar_mem32, res, rom);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265 }
266}
267
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700268static void __devinit pci_read_bridge_io(struct pci_bus *child)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269{
270 struct pci_dev *dev = child->self;
271 u8 io_base_lo, io_limit_lo;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272 unsigned long base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700273 struct pci_bus_region region;
274 struct resource *res, res2;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276 res = child->resource[0];
277 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
278 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
279 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
280 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
281
282 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
283 u16 io_base_hi, io_limit_hi;
284 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
285 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
286 base |= (io_base_hi << 16);
287 limit |= (io_limit_hi << 16);
288 }
289
Yinghai Lucd81e1e2010-01-22 01:02:22 -0800290 if (base && base <= limit) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
Bjorn Helgaascf48fb62012-03-16 17:47:59 -0600292 res2.flags = res->flags;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700293 region.start = base;
294 region.end = limit + 0xfff;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -0700295 pcibios_bus_to_resource(dev, &res2, &region);
Daniel Yeisley9d265122005-12-05 07:06:43 -0500296 if (!res->start)
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700297 res->start = res2.start;
Daniel Yeisley9d265122005-12-05 07:06:43 -0500298 if (!res->end)
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700299 res->end = res2.end;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600300 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700302}
303
304static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
305{
306 struct pci_dev *dev = child->self;
307 u16 mem_base_lo, mem_limit_lo;
308 unsigned long base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700309 struct pci_bus_region region;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700310 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311
312 res = child->resource[1];
313 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
314 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
315 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
316 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
Yinghai Lucd81e1e2010-01-22 01:02:22 -0800317 if (base && base <= limit) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700319 region.start = base;
320 region.end = limit + 0xfffff;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -0700321 pcibios_bus_to_resource(dev, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600322 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700324}
325
326static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
327{
328 struct pci_dev *dev = child->self;
329 u16 mem_base_lo, mem_limit_lo;
330 unsigned long base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700331 struct pci_bus_region region;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700332 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333
334 res = child->resource[2];
335 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
336 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
337 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
338 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
339
340 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
341 u32 mem_base_hi, mem_limit_hi;
342 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
343 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
344
345 /*
346 * Some bridges set the base > limit by default, and some
347 * (broken) BIOSes do not initialize them. If we find
348 * this, just assume they are not being used.
349 */
350 if (mem_base_hi <= mem_limit_hi) {
351#if BITS_PER_LONG == 64
352 base |= ((long) mem_base_hi) << 32;
353 limit |= ((long) mem_limit_hi) << 32;
354#else
355 if (mem_base_hi || mem_limit_hi) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600356 dev_err(&dev->dev, "can't handle 64-bit "
357 "address space for bridge\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358 return;
359 }
360#endif
361 }
362 }
Yinghai Lucd81e1e2010-01-22 01:02:22 -0800363 if (base && base <= limit) {
Yinghai Lu1f82de12009-04-23 20:48:32 -0700364 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
365 IORESOURCE_MEM | IORESOURCE_PREFETCH;
366 if (res->flags & PCI_PREF_RANGE_TYPE_64)
367 res->flags |= IORESOURCE_MEM_64;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700368 region.start = base;
369 region.end = limit + 0xfffff;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -0700370 pcibios_bus_to_resource(dev, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600371 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372 }
373}
374
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700375void __devinit pci_read_bridge_bases(struct pci_bus *child)
376{
377 struct pci_dev *dev = child->self;
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700378 struct resource *res;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700379 int i;
380
381 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
382 return;
383
384 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
385 child->secondary, child->subordinate,
386 dev->transparent ? " (subtractive decode)" : "");
387
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700388 pci_bus_remove_resources(child);
389 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
390 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
391
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700392 pci_read_bridge_io(child);
393 pci_read_bridge_mmio(child);
394 pci_read_bridge_mmio_pref(child);
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700395
396 if (dev->transparent) {
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700397 pci_bus_for_each_resource(child->parent, res, i) {
398 if (res) {
399 pci_bus_add_resource(child, res,
400 PCI_SUBTRACTIVE_DECODE);
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700401 dev_printk(KERN_DEBUG, &dev->dev,
402 " bridge window %pR (subtractive decode)\n",
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700403 res);
404 }
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700405 }
406 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700407}
408
Sam Ravnborg96bde062007-03-26 21:53:30 -0800409static struct pci_bus * pci_alloc_bus(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410{
411 struct pci_bus *b;
412
Eric Sesterhennf5afe802006-02-28 15:34:49 +0100413 b = kzalloc(sizeof(*b), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414 if (b) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700415 INIT_LIST_HEAD(&b->node);
416 INIT_LIST_HEAD(&b->children);
417 INIT_LIST_HEAD(&b->devices);
Alex Chiangf46753c2008-06-10 15:28:50 -0600418 INIT_LIST_HEAD(&b->slots);
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700419 INIT_LIST_HEAD(&b->resources);
Matthew Wilcox3749c512009-12-13 08:11:32 -0500420 b->max_bus_speed = PCI_SPEED_UNKNOWN;
421 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700422 }
423 return b;
424}
425
Yinghai Lu7b543662012-04-02 18:31:53 -0700426static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
427{
428 struct pci_host_bridge *bridge;
429
430 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
431 if (bridge) {
432 INIT_LIST_HEAD(&bridge->windows);
433 bridge->bus = b;
434 }
435
436 return bridge;
437}
438
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500439static unsigned char pcix_bus_speed[] = {
440 PCI_SPEED_UNKNOWN, /* 0 */
441 PCI_SPEED_66MHz_PCIX, /* 1 */
442 PCI_SPEED_100MHz_PCIX, /* 2 */
443 PCI_SPEED_133MHz_PCIX, /* 3 */
444 PCI_SPEED_UNKNOWN, /* 4 */
445 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
446 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
447 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
448 PCI_SPEED_UNKNOWN, /* 8 */
449 PCI_SPEED_66MHz_PCIX_266, /* 9 */
450 PCI_SPEED_100MHz_PCIX_266, /* A */
451 PCI_SPEED_133MHz_PCIX_266, /* B */
452 PCI_SPEED_UNKNOWN, /* C */
453 PCI_SPEED_66MHz_PCIX_533, /* D */
454 PCI_SPEED_100MHz_PCIX_533, /* E */
455 PCI_SPEED_133MHz_PCIX_533 /* F */
456};
457
Matthew Wilcox3749c512009-12-13 08:11:32 -0500458static unsigned char pcie_link_speed[] = {
459 PCI_SPEED_UNKNOWN, /* 0 */
460 PCIE_SPEED_2_5GT, /* 1 */
461 PCIE_SPEED_5_0GT, /* 2 */
Matthew Wilcox9dfd97f2009-12-13 08:11:35 -0500462 PCIE_SPEED_8_0GT, /* 3 */
Matthew Wilcox3749c512009-12-13 08:11:32 -0500463 PCI_SPEED_UNKNOWN, /* 4 */
464 PCI_SPEED_UNKNOWN, /* 5 */
465 PCI_SPEED_UNKNOWN, /* 6 */
466 PCI_SPEED_UNKNOWN, /* 7 */
467 PCI_SPEED_UNKNOWN, /* 8 */
468 PCI_SPEED_UNKNOWN, /* 9 */
469 PCI_SPEED_UNKNOWN, /* A */
470 PCI_SPEED_UNKNOWN, /* B */
471 PCI_SPEED_UNKNOWN, /* C */
472 PCI_SPEED_UNKNOWN, /* D */
473 PCI_SPEED_UNKNOWN, /* E */
474 PCI_SPEED_UNKNOWN /* F */
475};
476
477void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
478{
479 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
480}
481EXPORT_SYMBOL_GPL(pcie_update_link_speed);
482
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500483static unsigned char agp_speeds[] = {
484 AGP_UNKNOWN,
485 AGP_1X,
486 AGP_2X,
487 AGP_4X,
488 AGP_8X
489};
490
491static enum pci_bus_speed agp_speed(int agp3, int agpstat)
492{
493 int index = 0;
494
495 if (agpstat & 4)
496 index = 3;
497 else if (agpstat & 2)
498 index = 2;
499 else if (agpstat & 1)
500 index = 1;
501 else
502 goto out;
503
504 if (agp3) {
505 index += 2;
506 if (index == 5)
507 index = 0;
508 }
509
510 out:
511 return agp_speeds[index];
512}
513
514
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500515static void pci_set_bus_speed(struct pci_bus *bus)
516{
517 struct pci_dev *bridge = bus->self;
518 int pos;
519
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500520 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
521 if (!pos)
522 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
523 if (pos) {
524 u32 agpstat, agpcmd;
525
526 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
527 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
528
529 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
530 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
531 }
532
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500533 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
534 if (pos) {
535 u16 status;
536 enum pci_bus_speed max;
537 pci_read_config_word(bridge, pos + 2, &status);
538
539 if (status & 0x8000) {
540 max = PCI_SPEED_133MHz_PCIX_533;
541 } else if (status & 0x4000) {
542 max = PCI_SPEED_133MHz_PCIX_266;
543 } else if (status & 0x0002) {
544 if (((status >> 12) & 0x3) == 2) {
545 max = PCI_SPEED_133MHz_PCIX_ECC;
546 } else {
547 max = PCI_SPEED_133MHz_PCIX;
548 }
549 } else {
550 max = PCI_SPEED_66MHz_PCIX;
551 }
552
553 bus->max_bus_speed = max;
554 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
555
556 return;
557 }
558
559 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
560 if (pos) {
561 u32 linkcap;
562 u16 linksta;
563
564 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
565 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
566
567 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
568 pcie_update_link_speed(bus, linksta);
569 }
570}
571
572
Adrian Bunkcbd4e052008-04-18 13:53:55 -0700573static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
574 struct pci_dev *bridge, int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700575{
576 struct pci_bus *child;
577 int i;
578
579 /*
580 * Allocate a new bus, and inherit stuff from the parent..
581 */
582 child = pci_alloc_bus();
583 if (!child)
584 return NULL;
585
Linus Torvalds1da177e2005-04-16 15:20:36 -0700586 child->parent = parent;
587 child->ops = parent->ops;
588 child->sysdata = parent->sysdata;
Michael S. Tsirkin6e325a62006-02-14 18:52:22 +0200589 child->bus_flags = parent->bus_flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700590
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400591 /* initialize some portions of the bus device, but don't register it
592 * now as the parent is not properly set up yet. This device will get
593 * registered later in pci_bus_add_devices()
594 */
595 child->dev.class = &pcibus_class;
Kay Sievers1a927132008-10-30 02:17:49 +0100596 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700597
598 /*
599 * Set up the primary, secondary and subordinate
600 * bus numbers.
601 */
602 child->number = child->secondary = busnr;
603 child->primary = parent->secondary;
604 child->subordinate = 0xff;
605
Yu Zhao3789fa82008-11-22 02:41:07 +0800606 if (!bridge)
607 return child;
608
609 child->self = bridge;
610 child->bridge = get_device(&bridge->dev);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +1000611 pci_set_bus_of_node(child);
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500612 pci_set_bus_speed(child);
613
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614 /* Set up default resource pointers and names.. */
Yu Zhaofde09c62008-11-22 02:39:32 +0800615 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
617 child->resource[i]->name = child->name;
618 }
619 bridge->subordinate = child;
620
621 return child;
622}
623
Sam Ravnborg451124a2008-02-02 22:33:43 +0100624struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700625{
626 struct pci_bus *child;
627
628 child = pci_alloc_child_bus(parent, dev, busnr);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700629 if (child) {
Zhang Yanmind71374d2006-06-02 12:35:43 +0800630 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700631 list_add_tail(&child->node, &parent->children);
Zhang Yanmind71374d2006-06-02 12:35:43 +0800632 up_write(&pci_bus_sem);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700633 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634 return child;
635}
636
Sam Ravnborg96bde062007-03-26 21:53:30 -0800637static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700638{
639 struct pci_bus *parent = child->parent;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700640
641 /* Attempts to fix that up are really dangerous unless
642 we're going to re-assign all bus numbers. */
643 if (!pcibios_assign_all_busses())
644 return;
645
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700646 while (parent->parent && parent->subordinate < max) {
647 parent->subordinate = max;
648 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
649 parent = parent->parent;
650 }
651}
652
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653/*
654 * If it's a bridge, configure it and scan the bus behind it.
655 * For CardBus bridges, we don't scan behind as the devices will
656 * be handled by the bridge driver itself.
657 *
658 * We need to process bridges in two passes -- first we scan those
659 * already configured by the BIOS and after we are done with all of
660 * them, we proceed to assigning numbers to the remaining buses in
661 * order to avoid overlaps between old and new bus numbers.
662 */
Sam Ravnborg0ab2b572008-02-17 10:45:28 +0100663int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664{
665 struct pci_bus *child;
666 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
Dominik Brodowski49887942005-12-08 16:53:12 +0100667 u32 buses, i, j = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668 u16 bctl;
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600669 u8 primary, secondary, subordinate;
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100670 int broken = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671
672 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600673 primary = buses & 0xFF;
674 secondary = (buses >> 8) & 0xFF;
675 subordinate = (buses >> 16) & 0xFF;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700676
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600677 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
678 secondary, subordinate, pass);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679
Yinghai Lu71f6bd42012-01-30 12:25:24 +0100680 if (!primary && (primary != bus->number) && secondary && subordinate) {
681 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
682 primary = bus->number;
683 }
684
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100685 /* Check if setup is sensible at all */
686 if (!pass &&
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600687 (primary != bus->number || secondary <= bus->number)) {
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100688 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
689 broken = 1;
690 }
691
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692 /* Disable MasterAbortMode during probing to avoid reporting
693 of bus errors (in some architectures) */
694 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
695 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
696 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
697
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600698 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
699 !is_cardbus && !broken) {
700 unsigned int cmax;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700701 /*
702 * Bus already configured by firmware, process it in the first
703 * pass and just note the configuration.
704 */
705 if (pass)
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000706 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700707
708 /*
709 * If we already got to this bus through a different bridge,
Alex Chiang74710de2009-03-20 14:56:10 -0600710 * don't re-add it. This can happen with the i450NX chipset.
711 *
712 * However, we continue to descend down the hierarchy and
713 * scan remaining child buses.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700714 */
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600715 child = pci_find_bus(pci_domain_nr(bus), secondary);
Alex Chiang74710de2009-03-20 14:56:10 -0600716 if (!child) {
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600717 child = pci_add_new_bus(bus, dev, secondary);
Alex Chiang74710de2009-03-20 14:56:10 -0600718 if (!child)
719 goto out;
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600720 child->primary = primary;
721 child->subordinate = subordinate;
Alex Chiang74710de2009-03-20 14:56:10 -0600722 child->bridge_ctl = bctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723 }
724
Linus Torvalds1da177e2005-04-16 15:20:36 -0700725 cmax = pci_scan_child_bus(child);
726 if (cmax > max)
727 max = cmax;
728 if (child->subordinate > max)
729 max = child->subordinate;
730 } else {
731 /*
732 * We need to assign a number to this bus which we always
733 * do in the second pass.
734 */
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700735 if (!pass) {
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100736 if (pcibios_assign_all_busses() || broken)
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700737 /* Temporarily disable forwarding of the
738 configuration cycles on all bridges in
739 this bus segment to avoid possible
740 conflicts in the second pass between two
741 bridges programmed with overlapping
742 bus ranges. */
743 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
744 buses & ~0xffffff);
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000745 goto out;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700746 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747
748 /* Clear errors */
749 pci_write_config_word(dev, PCI_STATUS, 0xffff);
750
Rajesh Shahcc574502005-04-28 00:25:47 -0700751 /* Prevent assigning a bus number that already exists.
Tiejun Chenb1a98b62011-06-02 11:02:50 +0800752 * This can happen when a bridge is hot-plugged, so in
753 * this case we only re-scan this bus. */
754 child = pci_find_bus(pci_domain_nr(bus), max+1);
755 if (!child) {
756 child = pci_add_new_bus(bus, dev, ++max);
757 if (!child)
758 goto out;
759 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700760 buses = (buses & 0xff000000)
761 | ((unsigned int)(child->primary) << 0)
762 | ((unsigned int)(child->secondary) << 8)
763 | ((unsigned int)(child->subordinate) << 16);
764
765 /*
766 * yenta.c forces a secondary latency timer of 176.
767 * Copy that behaviour here.
768 */
769 if (is_cardbus) {
770 buses &= ~0xff000000;
771 buses |= CARDBUS_LATENCY_TIMER << 24;
772 }
Jesper Juhl7c867c82011-01-24 21:14:33 +0100773
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774 /*
775 * We need to blast all three values with a single write.
776 */
777 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
778
779 if (!is_cardbus) {
Gary Hade11949252007-10-08 16:24:16 -0700780 child->bridge_ctl = bctl;
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700781 /*
782 * Adjust subordinate busnr in parent buses.
783 * We do this before scanning for children because
784 * some devices may not be detected if the bios
785 * was lazy.
786 */
787 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700788 /* Now we can scan all subordinate buses... */
789 max = pci_scan_child_bus(child);
Kristen Accardie3ac86d2006-01-17 16:57:01 -0800790 /*
791 * now fix it up again since we have found
792 * the real value of max.
793 */
794 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795 } else {
796 /*
797 * For CardBus bridges, we leave 4 bus numbers
798 * as cards with a PCI-to-PCI bridge can be
799 * inserted later.
800 */
Dominik Brodowski49887942005-12-08 16:53:12 +0100801 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
802 struct pci_bus *parent = bus;
Rajesh Shahcc574502005-04-28 00:25:47 -0700803 if (pci_find_bus(pci_domain_nr(bus),
804 max+i+1))
805 break;
Dominik Brodowski49887942005-12-08 16:53:12 +0100806 while (parent->parent) {
807 if ((!pcibios_assign_all_busses()) &&
808 (parent->subordinate > max) &&
809 (parent->subordinate <= max+i)) {
810 j = 1;
811 }
812 parent = parent->parent;
813 }
814 if (j) {
815 /*
816 * Often, there are two cardbus bridges
817 * -- try to leave one valid bus number
818 * for each one.
819 */
820 i /= 2;
821 break;
822 }
823 }
Rajesh Shahcc574502005-04-28 00:25:47 -0700824 max += i;
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700825 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826 }
827 /*
828 * Set the subordinate bus number to its real value.
829 */
830 child->subordinate = max;
831 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
832 }
833
Gary Hadecb3576f2008-02-08 14:00:52 -0800834 sprintf(child->name,
835 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
836 pci_domain_nr(bus), child->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837
Bernhard Kaindld55bef52007-07-30 20:35:13 +0200838 /* Has only triggered on CardBus, fixup is in yenta_socket */
Dominik Brodowski49887942005-12-08 16:53:12 +0100839 while (bus->parent) {
840 if ((child->subordinate > bus->subordinate) ||
841 (child->number > bus->subordinate) ||
842 (child->number < bus->number) ||
843 (child->subordinate < bus->number)) {
Bjorn Helgaas865df572009-11-04 10:32:57 -0700844 dev_info(&child->dev, "[bus %02x-%02x] %s "
845 "hidden behind%s bridge %s [bus %02x-%02x]\n",
Bernhard Kaindld55bef52007-07-30 20:35:13 +0200846 child->number, child->subordinate,
847 (bus->number > child->subordinate &&
848 bus->subordinate < child->number) ?
Joe Perchesa6f29a92007-11-19 17:48:29 -0800849 "wholly" : "partially",
850 bus->self->transparent ? " transparent" : "",
Bjorn Helgaas865df572009-11-04 10:32:57 -0700851 dev_name(&bus->dev),
Bernhard Kaindld55bef52007-07-30 20:35:13 +0200852 bus->number, bus->subordinate);
Dominik Brodowski49887942005-12-08 16:53:12 +0100853 }
854 bus = bus->parent;
855 }
856
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000857out:
858 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
859
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860 return max;
861}
862
863/*
864 * Read interrupt line and base address registers.
865 * The architecture-dependent code can tweak these, of course.
866 */
867static void pci_read_irq(struct pci_dev *dev)
868{
869 unsigned char irq;
870
871 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
Kristen Accardiffeff782005-11-02 16:24:32 -0800872 dev->pin = irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700873 if (irq)
874 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
875 dev->irq = irq;
876}
877
Benjamin Herrenschmidtbb209c82010-01-26 17:10:03 +0000878void set_pcie_port_type(struct pci_dev *pdev)
Yu Zhao480b93b2009-03-20 11:25:14 +0800879{
880 int pos;
881 u16 reg16;
882
883 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
884 if (!pos)
885 return;
886 pdev->is_pcie = 1;
Kenji Kaneshige0efea002009-11-05 12:05:11 +0900887 pdev->pcie_cap = pos;
Yu Zhao480b93b2009-03-20 11:25:14 +0800888 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
889 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
Jon Masonb03e7492011-07-20 15:20:54 -0500890 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
891 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
Yu Zhao480b93b2009-03-20 11:25:14 +0800892}
893
Benjamin Herrenschmidtbb209c82010-01-26 17:10:03 +0000894void set_pcie_hotplug_bridge(struct pci_dev *pdev)
Eric W. Biederman28760482009-09-09 14:09:24 -0700895{
896 int pos;
897 u16 reg16;
898 u32 reg32;
899
Kenji Kaneshige06a1cba2009-11-11 14:30:56 +0900900 pos = pci_pcie_cap(pdev);
Eric W. Biederman28760482009-09-09 14:09:24 -0700901 if (!pos)
902 return;
903 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
904 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
905 return;
906 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
907 if (reg32 & PCI_EXP_SLTCAP_HPC)
908 pdev->is_hotplug_bridge = 1;
909}
910
Bartlomiej Zolnierkiewicz01abc2a2007-04-23 23:19:36 +0200911#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
Randy Dunlap76e6a1d2006-12-29 16:47:29 -0800912
Linus Torvalds1da177e2005-04-16 15:20:36 -0700913/**
914 * pci_setup_device - fill in class and map information of a device
915 * @dev: the device structure to fill
916 *
917 * Initialize the device structure with information about the device's
918 * vendor,class,memory and IO-space addresses,IRQ lines etc.
919 * Called at initialisation of the PCI subsystem and by CardBus services.
Yu Zhao480b93b2009-03-20 11:25:14 +0800920 * Returns 0 on success and negative if unknown type of device (not normal,
921 * bridge or CardBus).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700922 */
Yu Zhao480b93b2009-03-20 11:25:14 +0800923int pci_setup_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924{
925 u32 class;
Yu Zhao480b93b2009-03-20 11:25:14 +0800926 u8 hdr_type;
927 struct pci_slot *slot;
Gabe Blackbc577d22009-10-06 10:45:19 -0500928 int pos = 0;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700929 struct pci_bus_region region;
930 struct resource *res;
Yu Zhao480b93b2009-03-20 11:25:14 +0800931
932 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
933 return -EIO;
934
935 dev->sysdata = dev->bus->sysdata;
936 dev->dev.parent = dev->bus->bridge;
937 dev->dev.bus = &pci_bus_type;
938 dev->hdr_type = hdr_type & 0x7f;
939 dev->multifunction = !!(hdr_type & 0x80);
Yu Zhao480b93b2009-03-20 11:25:14 +0800940 dev->error_state = pci_channel_io_normal;
941 set_pcie_port_type(dev);
942
943 list_for_each_entry(slot, &dev->bus->slots, list)
944 if (PCI_SLOT(dev->devfn) == slot->number)
945 dev->slot = slot;
946
947 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
948 set this higher, assuming the system even supports it. */
949 dev->dma_mask = 0xffffffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700950
Greg Kroah-Hartmaneebfcfb2008-07-02 13:24:49 -0700951 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
952 dev->bus->number, PCI_SLOT(dev->devfn),
953 PCI_FUNC(dev->devfn));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700954
955 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
Auke Kokb8a3a522007-06-08 15:46:30 -0700956 dev->revision = class & 0xff;
Yinghai Lu2dd8ba92012-02-19 14:50:12 -0800957 dev->class = class >> 8; /* upper 3 bytes */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700958
Yinghai Lu2dd8ba92012-02-19 14:50:12 -0800959 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
960 dev->vendor, dev->device, dev->hdr_type, dev->class);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700961
Yu Zhao853346e2009-03-21 22:05:11 +0800962 /* need to have dev->class ready */
963 dev->cfg_size = pci_cfg_space_size(dev);
964
Linus Torvalds1da177e2005-04-16 15:20:36 -0700965 /* "Unknown power state" */
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700966 dev->current_state = PCI_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700967
968 /* Early fixups, before probing the BARs */
969 pci_fixup_device(pci_fixup_early, dev);
Yu Zhaof79b1b12009-05-28 00:25:05 +0800970 /* device class may be changed after fixup */
971 class = dev->class >> 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700972
973 switch (dev->hdr_type) { /* header type */
974 case PCI_HEADER_TYPE_NORMAL: /* standard header */
975 if (class == PCI_CLASS_BRIDGE_PCI)
976 goto bad;
977 pci_read_irq(dev);
978 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
979 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
980 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
Alan Cox368c73d2006-10-04 00:41:26 +0100981
982 /*
983 * Do the ugly legacy mode stuff here rather than broken chip
984 * quirk code. Legacy mode ATA controllers have fixed
985 * addresses. These are not always echoed in BAR0-3, and
986 * BAR0-3 in a few cases contain junk!
987 */
988 if (class == PCI_CLASS_STORAGE_IDE) {
989 u8 progif;
990 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
991 if ((progif & 1) == 0) {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700992 region.start = 0x1F0;
993 region.end = 0x1F7;
994 res = &dev->resource[0];
995 res->flags = LEGACY_IO_RESOURCE;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -0700996 pcibios_bus_to_resource(dev, res, &region);
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700997 region.start = 0x3F6;
998 region.end = 0x3F6;
999 res = &dev->resource[1];
1000 res->flags = LEGACY_IO_RESOURCE;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -07001001 pcibios_bus_to_resource(dev, res, &region);
Alan Cox368c73d2006-10-04 00:41:26 +01001002 }
1003 if ((progif & 4) == 0) {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001004 region.start = 0x170;
1005 region.end = 0x177;
1006 res = &dev->resource[2];
1007 res->flags = LEGACY_IO_RESOURCE;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -07001008 pcibios_bus_to_resource(dev, res, &region);
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001009 region.start = 0x376;
1010 region.end = 0x376;
1011 res = &dev->resource[3];
1012 res->flags = LEGACY_IO_RESOURCE;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -07001013 pcibios_bus_to_resource(dev, res, &region);
Alan Cox368c73d2006-10-04 00:41:26 +01001014 }
1015 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001016 break;
1017
1018 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1019 if (class != PCI_CLASS_BRIDGE_PCI)
1020 goto bad;
1021 /* The PCI-to-PCI bridge spec requires that subtractive
1022 decoding (i.e. transparent) bridge must have programming
1023 interface code of 0x01. */
Kristen Accardi3efd2732005-11-02 16:55:49 -08001024 pci_read_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001025 dev->transparent = ((dev->class & 0xff) == 1);
1026 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
Eric W. Biederman28760482009-09-09 14:09:24 -07001027 set_pcie_hotplug_bridge(dev);
Gabe Blackbc577d22009-10-06 10:45:19 -05001028 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1029 if (pos) {
1030 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1031 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1032 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001033 break;
1034
1035 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1036 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1037 goto bad;
1038 pci_read_irq(dev);
1039 pci_read_bases(dev, 1, 0);
1040 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1041 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1042 break;
1043
1044 default: /* unknown header */
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06001045 dev_err(&dev->dev, "unknown header type %02x, "
1046 "ignoring device\n", dev->hdr_type);
Yu Zhao480b93b2009-03-20 11:25:14 +08001047 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001048
1049 bad:
Yinghai Lu2dd8ba92012-02-19 14:50:12 -08001050 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header "
1051 "type %02x)\n", dev->class, dev->hdr_type);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001052 dev->class = PCI_CLASS_NOT_DEFINED;
1053 }
1054
1055 /* We found a fine healthy device, go go go... */
1056 return 0;
1057}
1058
Zhao, Yu201de562008-10-13 19:49:55 +08001059static void pci_release_capabilities(struct pci_dev *dev)
1060{
1061 pci_vpd_release(dev);
Yu Zhaod1b054d2009-03-20 11:25:11 +08001062 pci_iov_release(dev);
Yinghai Luf7968412012-02-11 00:18:30 -08001063 pci_free_cap_save_buffers(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001064}
1065
Linus Torvalds1da177e2005-04-16 15:20:36 -07001066/**
1067 * pci_release_dev - free a pci device structure when all users of it are finished.
1068 * @dev: device that's been disconnected
1069 *
1070 * Will be called only by the device core when all users of this pci device are
1071 * done.
1072 */
1073static void pci_release_dev(struct device *dev)
1074{
1075 struct pci_dev *pci_dev;
1076
1077 pci_dev = to_pci_dev(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001078 pci_release_capabilities(pci_dev);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001079 pci_release_of_node(pci_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001080 kfree(pci_dev);
1081}
1082
1083/**
1084 * pci_cfg_space_size - get the configuration space size of the PCI device.
Randy Dunlap8f7020d2005-10-23 11:57:38 -07001085 * @dev: PCI device
Linus Torvalds1da177e2005-04-16 15:20:36 -07001086 *
1087 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1088 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1089 * access it. Maybe we don't have a way to generate extended config space
1090 * accesses, or the device is behind a reverse Express bridge. So we try
1091 * reading the dword at 0x100 which must either be 0 or a valid extended
1092 * capability header.
1093 */
Yinghai Lu70b9f7d2008-04-28 16:27:23 -07001094int pci_cfg_space_size_ext(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001095{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001096 u32 status;
Zhao, Yu557848c2008-10-13 19:18:07 +08001097 int pos = PCI_CFG_SPACE_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001098
Zhao, Yu557848c2008-10-13 19:18:07 +08001099 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100 goto fail;
1101 if (status == 0xffffffff)
1102 goto fail;
1103
1104 return PCI_CFG_SPACE_EXP_SIZE;
1105
1106 fail:
1107 return PCI_CFG_SPACE_SIZE;
1108}
1109
Yinghai Lu57741a72008-02-15 01:32:50 -08001110int pci_cfg_space_size(struct pci_dev *dev)
1111{
Yinghai Lu70b9f7d2008-04-28 16:27:23 -07001112 int pos;
1113 u32 status;
Yinghai Ludfadd9ed2009-03-08 21:35:37 -07001114 u16 class;
1115
1116 class = dev->class >> 8;
1117 if (class == PCI_CLASS_BRIDGE_HOST)
1118 return pci_cfg_space_size_ext(dev);
Yinghai Lu70b9f7d2008-04-28 16:27:23 -07001119
Kenji Kaneshige06a1cba2009-11-11 14:30:56 +09001120 pos = pci_pcie_cap(dev);
Yinghai Lu70b9f7d2008-04-28 16:27:23 -07001121 if (!pos) {
1122 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1123 if (!pos)
1124 goto fail;
1125
1126 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1127 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1128 goto fail;
1129 }
1130
1131 return pci_cfg_space_size_ext(dev);
1132
1133 fail:
1134 return PCI_CFG_SPACE_SIZE;
Yinghai Lu57741a72008-02-15 01:32:50 -08001135}
1136
Linus Torvalds1da177e2005-04-16 15:20:36 -07001137static void pci_release_bus_bridge_dev(struct device *dev)
1138{
Yinghai Lu7b543662012-04-02 18:31:53 -07001139 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
1140
Yinghai Lu4fa26492012-04-02 18:31:53 -07001141 if (bridge->release_fn)
1142 bridge->release_fn(bridge);
Yinghai Lu7b543662012-04-02 18:31:53 -07001143
1144 pci_free_resource_list(&bridge->windows);
1145
1146 kfree(bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001147}
1148
Michael Ellerman65891212007-04-05 17:19:08 +10001149struct pci_dev *alloc_pci_dev(void)
1150{
1151 struct pci_dev *dev;
1152
1153 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1154 if (!dev)
1155 return NULL;
1156
Michael Ellerman65891212007-04-05 17:19:08 +10001157 INIT_LIST_HEAD(&dev->bus_list);
1158
1159 return dev;
1160}
1161EXPORT_SYMBOL(alloc_pci_dev);
1162
Yinghai Luefdc87d2012-01-27 10:55:10 -08001163bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1164 int crs_timeout)
1165{
1166 int delay = 1;
1167
1168 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1169 return false;
1170
1171 /* some broken boards return 0 or ~0 if a slot is empty: */
1172 if (*l == 0xffffffff || *l == 0x00000000 ||
1173 *l == 0x0000ffff || *l == 0xffff0000)
1174 return false;
1175
1176 /* Configuration request Retry Status */
1177 while (*l == 0xffff0001) {
1178 if (!crs_timeout)
1179 return false;
1180
1181 msleep(delay);
1182 delay *= 2;
1183 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1184 return false;
1185 /* Card hasn't responded in 60 seconds? Must be stuck. */
1186 if (delay > crs_timeout) {
1187 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1188 "responding\n", pci_domain_nr(bus),
1189 bus->number, PCI_SLOT(devfn),
1190 PCI_FUNC(devfn));
1191 return false;
1192 }
1193 }
1194
1195 return true;
1196}
1197EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1198
Linus Torvalds1da177e2005-04-16 15:20:36 -07001199/*
1200 * Read the config data for a PCI device, sanity-check it
1201 * and fill in the dev structure...
1202 */
Adrian Bunk7f7b5de2008-04-18 13:53:55 -07001203static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001204{
1205 struct pci_dev *dev;
1206 u32 l;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001207
Yinghai Luefdc87d2012-01-27 10:55:10 -08001208 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001209 return NULL;
1210
Michael Ellermanbab41e92007-04-05 17:19:09 +10001211 dev = alloc_pci_dev();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001212 if (!dev)
1213 return NULL;
1214
Linus Torvalds1da177e2005-04-16 15:20:36 -07001215 dev->bus = bus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001216 dev->devfn = devfn;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001217 dev->vendor = l & 0xffff;
1218 dev->device = (l >> 16) & 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001219
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001220 pci_set_of_node(dev);
1221
Yu Zhao480b93b2009-03-20 11:25:14 +08001222 if (pci_setup_device(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001223 kfree(dev);
1224 return NULL;
1225 }
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001226
1227 return dev;
1228}
1229
Zhao, Yu201de562008-10-13 19:49:55 +08001230static void pci_init_capabilities(struct pci_dev *dev)
1231{
1232 /* MSI/MSI-X list */
1233 pci_msi_init_pci_dev(dev);
1234
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01001235 /* Buffers for saving PCIe and PCI-X capabilities */
1236 pci_allocate_cap_save_buffers(dev);
1237
Zhao, Yu201de562008-10-13 19:49:55 +08001238 /* Power Management */
1239 pci_pm_init(dev);
Jesse Barneseb9c39d2008-12-17 12:10:05 -08001240 platform_pci_wakeup_init(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001241
1242 /* Vital Product Data */
1243 pci_vpd_pci22_init(dev);
Yu Zhao58c3a722008-10-14 14:02:53 +08001244
1245 /* Alternative Routing-ID Forwarding */
1246 pci_enable_ari(dev);
Yu Zhaod1b054d2009-03-20 11:25:11 +08001247
1248 /* Single Root I/O Virtualization */
1249 pci_iov_init(dev);
Allen Kayae21ee62009-10-07 10:27:17 -07001250
1251 /* Enable ACS P2P upstream forwarding */
Chris Wright5d990b62009-12-04 12:15:21 -08001252 pci_enable_acs(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001253}
1254
Sam Ravnborg96bde062007-03-26 21:53:30 -08001255void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001256{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001257 device_initialize(&dev->dev);
1258 dev->dev.release = pci_release_dev;
1259 pci_dev_get(dev);
1260
Linus Torvalds1da177e2005-04-16 15:20:36 -07001261 dev->dev.dma_mask = &dev->dma_mask;
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001262 dev->dev.dma_parms = &dev->dma_parms;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001263 dev->dev.coherent_dma_mask = 0xffffffffull;
1264
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001265 pci_set_dma_max_seg_size(dev, 65536);
FUJITA Tomonori59fc67d2008-02-04 22:28:14 -08001266 pci_set_dma_seg_boundary(dev, 0xffffffff);
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001267
Linus Torvalds1da177e2005-04-16 15:20:36 -07001268 /* Fix up broken headers */
1269 pci_fixup_device(pci_fixup_header, dev);
1270
Yinghai Lu2069ecf2012-02-15 21:40:31 -08001271 /* moved out from quirk header fixup code */
1272 pci_reassigndev_resource_alignment(dev);
1273
Rafael J. Wysocki4b77b0a2009-09-09 23:49:59 +02001274 /* Clear the state_saved flag. */
1275 dev->state_saved = false;
1276
Zhao, Yu201de562008-10-13 19:49:55 +08001277 /* Initialize various capabilities */
1278 pci_init_capabilities(dev);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001279
Linus Torvalds1da177e2005-04-16 15:20:36 -07001280 /*
1281 * Add the device to our list of discovered devices
1282 * and the bus list for fixup functions, etc.
1283 */
Zhang Yanmind71374d2006-06-02 12:35:43 +08001284 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001285 list_add_tail(&dev->bus_list, &bus->devices);
Zhang Yanmind71374d2006-06-02 12:35:43 +08001286 up_write(&pci_bus_sem);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001287}
1288
Sam Ravnborg451124a2008-02-02 22:33:43 +01001289struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001290{
1291 struct pci_dev *dev;
1292
Trent Piepho90bdb312009-03-20 14:56:00 -06001293 dev = pci_get_slot(bus, devfn);
1294 if (dev) {
1295 pci_dev_put(dev);
1296 return dev;
1297 }
1298
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001299 dev = pci_scan_device(bus, devfn);
1300 if (!dev)
1301 return NULL;
1302
1303 pci_device_add(dev, bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001304
1305 return dev;
1306}
Adrian Bunkb73e9682007-11-21 15:07:11 -08001307EXPORT_SYMBOL(pci_scan_single_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001308
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001309static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
1310{
1311 u16 cap;
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001312 unsigned pos, next_fn;
1313
1314 if (!dev)
1315 return 0;
1316
1317 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001318 if (!pos)
1319 return 0;
1320 pci_read_config_word(dev, pos + 4, &cap);
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001321 next_fn = cap >> 8;
1322 if (next_fn <= fn)
1323 return 0;
1324 return next_fn;
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001325}
1326
1327static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
1328{
1329 return (fn + 1) % 8;
1330}
1331
1332static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
1333{
1334 return 0;
1335}
1336
1337static int only_one_child(struct pci_bus *bus)
1338{
1339 struct pci_dev *parent = bus->self;
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06001340
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001341 if (!parent || !pci_is_pcie(parent))
1342 return 0;
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06001343 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT)
1344 return 1;
1345 if (parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM &&
1346 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001347 return 1;
1348 return 0;
1349}
1350
Linus Torvalds1da177e2005-04-16 15:20:36 -07001351/**
1352 * pci_scan_slot - scan a PCI slot on a bus for devices.
1353 * @bus: PCI bus to scan
1354 * @devfn: slot number to scan (must have zero function.)
1355 *
1356 * Scan a PCI slot on the specified PCI bus for devices, adding
1357 * discovered devices to the @bus->devices list. New devices
Greg Kroah-Hartman8a1bc902008-02-14 14:56:56 -08001358 * will not have is_added set.
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001359 *
1360 * Returns the number of new devices found.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001361 */
Sam Ravnborg96bde062007-03-26 21:53:30 -08001362int pci_scan_slot(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001363{
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001364 unsigned fn, nr = 0;
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001365 struct pci_dev *dev;
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001366 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
1367
1368 if (only_one_child(bus) && (devfn > 0))
1369 return 0; /* Already scanned the entire slot */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001371 dev = pci_scan_single_device(bus, devfn);
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001372 if (!dev)
1373 return 0;
1374 if (!dev->is_added)
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001375 nr++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001376
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001377 if (pci_ari_enabled(bus))
1378 next_fn = next_ari_fn;
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001379 else if (dev->multifunction)
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001380 next_fn = next_trad_fn;
1381
1382 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
1383 dev = pci_scan_single_device(bus, devfn + fn);
1384 if (dev) {
1385 if (!dev->is_added)
1386 nr++;
1387 dev->multifunction = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001388 }
1389 }
Shaohua Li7d715a62008-02-25 09:46:41 +08001390
Shaohua Li149e1632008-07-23 10:32:31 +08001391 /* only one slot has pcie device */
1392 if (bus->self && nr)
Shaohua Li7d715a62008-02-25 09:46:41 +08001393 pcie_aspm_init_link_state(bus->self);
1394
Linus Torvalds1da177e2005-04-16 15:20:36 -07001395 return nr;
1396}
1397
Jon Masonb03e7492011-07-20 15:20:54 -05001398static int pcie_find_smpss(struct pci_dev *dev, void *data)
1399{
1400 u8 *smpss = data;
1401
1402 if (!pci_is_pcie(dev))
1403 return 0;
1404
1405 /* For PCIE hotplug enabled slots not connected directly to a
1406 * PCI-E root port, there can be problems when hotplugging
1407 * devices. This is due to the possibility of hotplugging a
1408 * device into the fabric with a smaller MPS that the devices
1409 * currently running have configured. Modifying the MPS on the
1410 * running devices could cause a fatal bus error due to an
1411 * incoming frame being larger than the newly configured MPS.
1412 * To work around this, the MPS for the entire fabric must be
1413 * set to the minimum size. Any devices hotplugged into this
1414 * fabric will have the minimum MPS set. If the PCI hotplug
1415 * slot is directly connected to the root port and there are not
1416 * other devices on the fabric (which seems to be the most
1417 * common case), then this is not an issue and MPS discovery
1418 * will occur as normal.
1419 */
1420 if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
Benjamin Herrenschmidt1a4b1a42011-09-13 15:16:33 -03001421 (dev->bus->self &&
1422 dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT)))
Jon Masonb03e7492011-07-20 15:20:54 -05001423 *smpss = 0;
1424
1425 if (*smpss > dev->pcie_mpss)
1426 *smpss = dev->pcie_mpss;
1427
1428 return 0;
1429}
1430
1431static void pcie_write_mps(struct pci_dev *dev, int mps)
1432{
Jon Mason62f392e2011-10-14 14:56:14 -05001433 int rc;
Jon Masonb03e7492011-07-20 15:20:54 -05001434
1435 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
Jon Mason62f392e2011-10-14 14:56:14 -05001436 mps = 128 << dev->pcie_mpss;
Jon Masonb03e7492011-07-20 15:20:54 -05001437
Jon Mason62f392e2011-10-14 14:56:14 -05001438 if (dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && dev->bus->self)
1439 /* For "Performance", the assumption is made that
Jon Masonb03e7492011-07-20 15:20:54 -05001440 * downstream communication will never be larger than
1441 * the MRRS. So, the MPS only needs to be configured
1442 * for the upstream communication. This being the case,
1443 * walk from the top down and set the MPS of the child
1444 * to that of the parent bus.
Jon Mason62f392e2011-10-14 14:56:14 -05001445 *
1446 * Configure the device MPS with the smaller of the
1447 * device MPSS or the bridge MPS (which is assumed to be
1448 * properly configured at this point to the largest
1449 * allowable MPS based on its parent bus).
Jon Masonb03e7492011-07-20 15:20:54 -05001450 */
Jon Mason62f392e2011-10-14 14:56:14 -05001451 mps = min(mps, pcie_get_mps(dev->bus->self));
Jon Masonb03e7492011-07-20 15:20:54 -05001452 }
1453
1454 rc = pcie_set_mps(dev, mps);
1455 if (rc)
1456 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1457}
1458
Jon Mason62f392e2011-10-14 14:56:14 -05001459static void pcie_write_mrrs(struct pci_dev *dev)
Jon Masonb03e7492011-07-20 15:20:54 -05001460{
Jon Mason62f392e2011-10-14 14:56:14 -05001461 int rc, mrrs;
Jon Masonb03e7492011-07-20 15:20:54 -05001462
Jon Masoned2888e2011-09-08 16:41:18 -05001463 /* In the "safe" case, do not configure the MRRS. There appear to be
1464 * issues with setting MRRS to 0 on a number of devices.
1465 */
Jon Masoned2888e2011-09-08 16:41:18 -05001466 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1467 return;
Jon Masonb03e7492011-07-20 15:20:54 -05001468
Jon Masoned2888e2011-09-08 16:41:18 -05001469 /* For Max performance, the MRRS must be set to the largest supported
1470 * value. However, it cannot be configured larger than the MPS the
Jon Mason62f392e2011-10-14 14:56:14 -05001471 * device or the bus can support. This should already be properly
1472 * configured by a prior call to pcie_write_mps.
Jon Masoned2888e2011-09-08 16:41:18 -05001473 */
Jon Mason62f392e2011-10-14 14:56:14 -05001474 mrrs = pcie_get_mps(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05001475
1476 /* MRRS is a R/W register. Invalid values can be written, but a
Jon Masoned2888e2011-09-08 16:41:18 -05001477 * subsequent read will verify if the value is acceptable or not.
Jon Masonb03e7492011-07-20 15:20:54 -05001478 * If the MRRS value provided is not acceptable (e.g., too large),
1479 * shrink the value until it is acceptable to the HW.
1480 */
1481 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1482 rc = pcie_set_readrq(dev, mrrs);
Jon Mason62f392e2011-10-14 14:56:14 -05001483 if (!rc)
1484 break;
Jon Masonb03e7492011-07-20 15:20:54 -05001485
Jon Mason62f392e2011-10-14 14:56:14 -05001486 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
Jon Masonb03e7492011-07-20 15:20:54 -05001487 mrrs /= 2;
1488 }
Jon Mason62f392e2011-10-14 14:56:14 -05001489
1490 if (mrrs < 128)
1491 dev_err(&dev->dev, "MRRS was unable to be configured with a "
1492 "safe value. If problems are experienced, try running "
1493 "with pci=pcie_bus_safe.\n");
Jon Masonb03e7492011-07-20 15:20:54 -05001494}
1495
1496static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1497{
Jon Masona513a992011-10-14 14:56:16 -05001498 int mps, orig_mps;
Jon Masonb03e7492011-07-20 15:20:54 -05001499
1500 if (!pci_is_pcie(dev))
1501 return 0;
1502
Jon Masona513a992011-10-14 14:56:16 -05001503 mps = 128 << *(u8 *)data;
1504 orig_mps = pcie_get_mps(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05001505
1506 pcie_write_mps(dev, mps);
Jon Mason62f392e2011-10-14 14:56:14 -05001507 pcie_write_mrrs(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05001508
Jon Masona513a992011-10-14 14:56:16 -05001509 dev_info(&dev->dev, "PCI-E Max Payload Size set to %4d/%4d (was %4d), "
1510 "Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss,
1511 orig_mps, pcie_get_readrq(dev));
Jon Masonb03e7492011-07-20 15:20:54 -05001512
1513 return 0;
1514}
1515
Jon Masona513a992011-10-14 14:56:16 -05001516/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
Jon Masonb03e7492011-07-20 15:20:54 -05001517 * parents then children fashion. If this changes, then this code will not
1518 * work as designed.
1519 */
1520void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss)
1521{
Jon Mason5f39e672011-10-03 09:50:20 -05001522 u8 smpss;
Jon Masonb03e7492011-07-20 15:20:54 -05001523
Jon Masonb03e7492011-07-20 15:20:54 -05001524 if (!pci_is_pcie(bus->self))
1525 return;
1526
Jon Mason5f39e672011-10-03 09:50:20 -05001527 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
1528 return;
1529
1530 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1531 * to be aware to the MPS of the destination. To work around this,
1532 * simply force the MPS of the entire system to the smallest possible.
1533 */
1534 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1535 smpss = 0;
1536
Jon Masonb03e7492011-07-20 15:20:54 -05001537 if (pcie_bus_config == PCIE_BUS_SAFE) {
Jon Mason5f39e672011-10-03 09:50:20 -05001538 smpss = mpss;
1539
Jon Masonb03e7492011-07-20 15:20:54 -05001540 pcie_find_smpss(bus->self, &smpss);
1541 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1542 }
1543
1544 pcie_bus_configure_set(bus->self, &smpss);
1545 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1546}
Jon Masondebc3b72011-08-02 00:01:18 -05001547EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
Jon Masonb03e7492011-07-20 15:20:54 -05001548
Sam Ravnborg0ab2b572008-02-17 10:45:28 +01001549unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001550{
1551 unsigned int devfn, pass, max = bus->secondary;
1552 struct pci_dev *dev;
1553
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001554 dev_dbg(&bus->dev, "scanning bus\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001555
1556 /* Go find them, Rover! */
1557 for (devfn = 0; devfn < 0x100; devfn += 8)
1558 pci_scan_slot(bus, devfn);
1559
Yu Zhaoa28724b2009-03-20 11:25:13 +08001560 /* Reserve buses for SR-IOV capability. */
1561 max += pci_iov_bus_range(bus);
1562
Linus Torvalds1da177e2005-04-16 15:20:36 -07001563 /*
1564 * After performing arch-dependent fixup of the bus, look behind
1565 * all PCI-to-PCI bridges on this bus.
1566 */
Alex Chiang74710de2009-03-20 14:56:10 -06001567 if (!bus->is_added) {
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001568 dev_dbg(&bus->dev, "fixups for bus\n");
Alex Chiang74710de2009-03-20 14:56:10 -06001569 pcibios_fixup_bus(bus);
1570 if (pci_is_root_bus(bus))
1571 bus->is_added = 1;
1572 }
1573
Linus Torvalds1da177e2005-04-16 15:20:36 -07001574 for (pass=0; pass < 2; pass++)
1575 list_for_each_entry(dev, &bus->devices, bus_list) {
1576 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1577 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1578 max = pci_scan_bridge(bus, dev, max, pass);
1579 }
1580
1581 /*
1582 * We've scanned the bus and so we know all about what's on
1583 * the other side of any bridges that may be on this bus plus
1584 * any devices.
1585 *
1586 * Return how far we've got finding sub-buses.
1587 */
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001588 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001589 return max;
1590}
1591
Bjorn Helgaas166c6372011-10-28 16:25:45 -06001592struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1593 struct pci_ops *ops, void *sysdata, struct list_head *resources)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001594{
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001595 int error;
Bjorn Helgaas5a21d702012-02-23 20:18:59 -07001596 struct pci_host_bridge *bridge;
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001597 struct pci_bus *b, *b2;
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001598 struct pci_host_bridge_window *window, *n;
Bjorn Helgaasa9d9f522011-10-28 16:25:40 -06001599 struct resource *res;
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001600 resource_size_t offset;
1601 char bus_addr[64];
1602 char *fmt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001603
Linus Torvalds1da177e2005-04-16 15:20:36 -07001604
Bjorn Helgaas5a21d702012-02-23 20:18:59 -07001605 b = pci_alloc_bus();
1606 if (!b)
Yinghai Lu7b543662012-04-02 18:31:53 -07001607 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001608
1609 b->sysdata = sysdata;
1610 b->ops = ops;
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001611 b2 = pci_find_bus(pci_domain_nr(b), bus);
1612 if (b2) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001613 /* If we already got to this bus through a different bridge, ignore it */
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001614 dev_dbg(&b2->dev, "bus already known\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001615 goto err_out;
1616 }
Zhang Yanmind71374d2006-06-02 12:35:43 +08001617
Yinghai Lu7b543662012-04-02 18:31:53 -07001618 bridge = pci_alloc_host_bridge(b);
1619 if (!bridge)
1620 goto err_out;
1621
1622 bridge->dev.parent = parent;
1623 bridge->dev.release = pci_release_bus_bridge_dev;
1624 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1625 error = device_register(&bridge->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001626 if (error)
Yinghai Lu7b543662012-04-02 18:31:53 -07001627 goto bridge_dev_reg_err;
1628 b->bridge = get_device(&bridge->dev);
Rafael J. Wysockia1e4d722010-02-08 19:16:33 +01001629 device_enable_async_suspend(b->bridge);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001630 pci_set_bus_of_node(b);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001631
Yinghai Lu0d358f22008-02-19 03:20:41 -08001632 if (!parent)
1633 set_dev_node(b->bridge, pcibus_to_node(b));
1634
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001635 b->dev.class = &pcibus_class;
1636 b->dev.parent = b->bridge;
Kay Sievers1a927132008-10-30 02:17:49 +01001637 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001638 error = device_register(&b->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001639 if (error)
1640 goto class_dev_reg_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001641
1642 /* Create legacy_io and legacy_mem files for this bus */
1643 pci_create_legacy_files(b);
1644
Linus Torvalds1da177e2005-04-16 15:20:36 -07001645 b->number = b->secondary = bus;
Bjorn Helgaas166c6372011-10-28 16:25:45 -06001646
Bjorn Helgaasa9d9f522011-10-28 16:25:40 -06001647 if (parent)
1648 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
1649 else
1650 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
1651
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001652 /* Add initial resources to the bus */
1653 list_for_each_entry_safe(window, n, resources, list) {
1654 list_move_tail(&window->list, &bridge->windows);
1655 res = window->res;
1656 offset = window->offset;
1657 pci_bus_add_resource(b, res, 0);
1658 if (offset) {
1659 if (resource_type(res) == IORESOURCE_IO)
1660 fmt = " (bus address [%#06llx-%#06llx])";
1661 else
1662 fmt = " (bus address [%#010llx-%#010llx])";
1663 snprintf(bus_addr, sizeof(bus_addr), fmt,
1664 (unsigned long long) (res->start - offset),
1665 (unsigned long long) (res->end - offset));
1666 } else
1667 bus_addr[0] = '\0';
1668 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
Bjorn Helgaasa9d9f522011-10-28 16:25:40 -06001669 }
1670
Bjorn Helgaasa5390aa2012-02-23 20:18:59 -07001671 down_write(&pci_bus_sem);
1672 list_add_tail(&b->node, &pci_root_buses);
1673 up_write(&pci_bus_sem);
1674
Linus Torvalds1da177e2005-04-16 15:20:36 -07001675 return b;
1676
Linus Torvalds1da177e2005-04-16 15:20:36 -07001677class_dev_reg_err:
Yinghai Lu7b543662012-04-02 18:31:53 -07001678 put_device(&bridge->dev);
1679 device_unregister(&bridge->dev);
1680bridge_dev_reg_err:
Bjorn Helgaas5a21d702012-02-23 20:18:59 -07001681 kfree(bridge);
Yinghai Lu7b543662012-04-02 18:31:53 -07001682err_out:
1683 kfree(b);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001684 return NULL;
1685}
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001686
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06001687struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
1688 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1689{
1690 struct pci_bus *b;
1691
1692 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
1693 if (!b)
1694 return NULL;
1695
1696 b->subordinate = pci_scan_child_bus(b);
1697 pci_bus_add_devices(b);
1698 return b;
1699}
1700EXPORT_SYMBOL(pci_scan_root_bus);
1701
Bjorn Helgaas7e00fe22011-10-28 16:26:05 -06001702/* Deprecated; use pci_scan_root_bus() instead */
Sam Ravnborg0ab2b572008-02-17 10:45:28 +01001703struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001704 int bus, struct pci_ops *ops, void *sysdata)
1705{
Bjorn Helgaas1e39ae92011-10-28 16:26:00 -06001706 LIST_HEAD(resources);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001707 struct pci_bus *b;
1708
Bjorn Helgaas1e39ae92011-10-28 16:26:00 -06001709 pci_add_resource(&resources, &ioport_resource);
1710 pci_add_resource(&resources, &iomem_resource);
1711 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001712 if (b)
1713 b->subordinate = pci_scan_child_bus(b);
Bjorn Helgaas1e39ae92011-10-28 16:26:00 -06001714 else
1715 pci_free_resource_list(&resources);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001716 return b;
1717}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001718EXPORT_SYMBOL(pci_scan_bus_parented);
1719
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06001720struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
1721 void *sysdata)
1722{
1723 LIST_HEAD(resources);
1724 struct pci_bus *b;
1725
1726 pci_add_resource(&resources, &ioport_resource);
1727 pci_add_resource(&resources, &iomem_resource);
1728 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
1729 if (b) {
1730 b->subordinate = pci_scan_child_bus(b);
1731 pci_bus_add_devices(b);
1732 } else {
1733 pci_free_resource_list(&resources);
1734 }
1735 return b;
1736}
1737EXPORT_SYMBOL(pci_scan_bus);
1738
Linus Torvalds1da177e2005-04-16 15:20:36 -07001739#ifdef CONFIG_HOTPLUG
Alex Chiang3ed4fd92009-03-20 14:56:25 -06001740/**
Yinghai Lu2f320522012-01-21 02:08:22 -08001741 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
1742 * @bridge: PCI bridge for the bus to scan
1743 *
1744 * Scan a PCI bus and child buses for new devices, add them,
1745 * and enable them, resizing bridge mmio/io resource if necessary
1746 * and possible. The caller must ensure the child devices are already
1747 * removed for resizing to occur.
1748 *
1749 * Returns the max number of subordinate bus discovered.
1750 */
1751unsigned int __ref pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
1752{
1753 unsigned int max;
1754 struct pci_bus *bus = bridge->subordinate;
1755
1756 max = pci_scan_child_bus(bus);
1757
1758 pci_assign_unassigned_bridge_resources(bridge);
1759
1760 pci_bus_add_devices(bus);
1761
1762 return max;
1763}
1764
Linus Torvalds1da177e2005-04-16 15:20:36 -07001765EXPORT_SYMBOL(pci_add_new_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001766EXPORT_SYMBOL(pci_scan_slot);
1767EXPORT_SYMBOL(pci_scan_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001768EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1769#endif
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001770
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05001771static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001772{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05001773 const struct pci_dev *a = to_pci_dev(d_a);
1774 const struct pci_dev *b = to_pci_dev(d_b);
1775
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001776 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1777 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1778
1779 if (a->bus->number < b->bus->number) return -1;
1780 else if (a->bus->number > b->bus->number) return 1;
1781
1782 if (a->devfn < b->devfn) return -1;
1783 else if (a->devfn > b->devfn) return 1;
1784
1785 return 0;
1786}
1787
Greg Kroah-Hartman5ff580c2008-02-14 14:56:56 -08001788void __init pci_sort_breadthfirst(void)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001789{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05001790 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001791}