Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #ifndef __RADEON_H__ |
| 29 | #define __RADEON_H__ |
| 30 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 31 | /* TODO: Here are things that needs to be done : |
| 32 | * - surface allocator & initializer : (bit like scratch reg) should |
| 33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
| 34 | * related to surface |
| 35 | * - WB : write back stuff (do it bit like scratch reg things) |
| 36 | * - Vblank : look at Jesse's rework and what we should do |
| 37 | * - r600/r700: gart & cp |
| 38 | * - cs : clean cs ioctl use bitmap & things like that. |
| 39 | * - power management stuff |
| 40 | * - Barrier in gart code |
| 41 | * - Unmappabled vram ? |
| 42 | * - TESTING, TESTING, TESTING |
| 43 | */ |
| 44 | |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 45 | /* Initialization path: |
| 46 | * We expect that acceleration initialization might fail for various |
| 47 | * reasons even thought we work hard to make it works on most |
| 48 | * configurations. In order to still have a working userspace in such |
| 49 | * situation the init path must succeed up to the memory controller |
| 50 | * initialization point. Failure before this point are considered as |
| 51 | * fatal error. Here is the init callchain : |
| 52 | * radeon_device_init perform common structure, mutex initialization |
| 53 | * asic_init setup the GPU memory layout and perform all |
| 54 | * one time initialization (failure in this |
| 55 | * function are considered fatal) |
| 56 | * asic_startup setup the GPU acceleration, in order to |
| 57 | * follow guideline the first thing this |
| 58 | * function should do is setting the GPU |
| 59 | * memory controller (only MC setup failure |
| 60 | * are considered as fatal) |
| 61 | */ |
| 62 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 63 | #include <asm/atomic.h> |
| 64 | #include <linux/wait.h> |
| 65 | #include <linux/list.h> |
| 66 | #include <linux/kref.h> |
| 67 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 68 | #include <ttm/ttm_bo_api.h> |
| 69 | #include <ttm/ttm_bo_driver.h> |
| 70 | #include <ttm/ttm_placement.h> |
| 71 | #include <ttm/ttm_module.h> |
| 72 | |
Dave Airlie | c214271 | 2009-09-22 08:50:10 +1000 | [diff] [blame] | 73 | #include "radeon_family.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 74 | #include "radeon_mode.h" |
| 75 | #include "radeon_reg.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 76 | |
| 77 | /* |
| 78 | * Modules parameters. |
| 79 | */ |
| 80 | extern int radeon_no_wb; |
| 81 | extern int radeon_modeset; |
| 82 | extern int radeon_dynclks; |
| 83 | extern int radeon_r4xx_atom; |
| 84 | extern int radeon_agpmode; |
| 85 | extern int radeon_vram_limit; |
| 86 | extern int radeon_gart_size; |
| 87 | extern int radeon_benchmarking; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 88 | extern int radeon_testing; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 89 | extern int radeon_connector_table; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 90 | extern int radeon_tv; |
Alex Deucher | b27b637 | 2009-12-09 17:44:25 -0500 | [diff] [blame] | 91 | extern int radeon_new_pll; |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 92 | extern int radeon_dynpm; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 93 | extern int radeon_audio; |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 94 | extern int radeon_disp_priority; |
Alex Deucher | e2b0a8e | 2010-03-17 02:07:37 -0400 | [diff] [blame] | 95 | extern int radeon_hw_i2c; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 96 | |
| 97 | /* |
| 98 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
| 99 | * symbol; |
| 100 | */ |
| 101 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 102 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 103 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 104 | #define RADEON_IB_POOL_SIZE 16 |
| 105 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
| 106 | #define RADEONFB_CONN_LIMIT 4 |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 107 | #define RADEON_BIOS_NUM_SCRATCH 8 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 108 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 109 | /* |
| 110 | * Errata workarounds. |
| 111 | */ |
| 112 | enum radeon_pll_errata { |
| 113 | CHIP_ERRATA_R300_CG = 0x00000001, |
| 114 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
| 115 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
| 116 | }; |
| 117 | |
| 118 | |
| 119 | struct radeon_device; |
| 120 | |
| 121 | |
| 122 | /* |
| 123 | * BIOS. |
| 124 | */ |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 125 | #define ATRM_BIOS_PAGE 4096 |
| 126 | |
Dave Airlie | 8edb381 | 2010-03-01 21:50:01 +1100 | [diff] [blame] | 127 | #if defined(CONFIG_VGA_SWITCHEROO) |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 128 | bool radeon_atrm_supported(struct pci_dev *pdev); |
| 129 | int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); |
Dave Airlie | 8edb381 | 2010-03-01 21:50:01 +1100 | [diff] [blame] | 130 | #else |
| 131 | static inline bool radeon_atrm_supported(struct pci_dev *pdev) |
| 132 | { |
| 133 | return false; |
| 134 | } |
| 135 | |
| 136 | static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ |
| 137 | return -EINVAL; |
| 138 | } |
| 139 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 140 | bool radeon_get_bios(struct radeon_device *rdev); |
| 141 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 142 | |
| 143 | /* |
| 144 | * Dummy page |
| 145 | */ |
| 146 | struct radeon_dummy_page { |
| 147 | struct page *page; |
| 148 | dma_addr_t addr; |
| 149 | }; |
| 150 | int radeon_dummy_page_init(struct radeon_device *rdev); |
| 151 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
| 152 | |
| 153 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 154 | /* |
| 155 | * Clocks |
| 156 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 157 | struct radeon_clock { |
| 158 | struct radeon_pll p1pll; |
| 159 | struct radeon_pll p2pll; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 160 | struct radeon_pll dcpll; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 161 | struct radeon_pll spll; |
| 162 | struct radeon_pll mpll; |
| 163 | /* 10 Khz units */ |
| 164 | uint32_t default_mclk; |
| 165 | uint32_t default_sclk; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 166 | uint32_t default_dispclk; |
| 167 | uint32_t dp_extclk; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 168 | }; |
| 169 | |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 170 | /* |
| 171 | * Power management |
| 172 | */ |
| 173 | int radeon_pm_init(struct radeon_device *rdev); |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 174 | void radeon_pm_fini(struct radeon_device *rdev); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 175 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 176 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
| 177 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 178 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 179 | /* |
| 180 | * Fences. |
| 181 | */ |
| 182 | struct radeon_fence_driver { |
| 183 | uint32_t scratch_reg; |
| 184 | atomic_t seq; |
| 185 | uint32_t last_seq; |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 186 | unsigned long last_jiffies; |
| 187 | unsigned long last_timeout; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 188 | wait_queue_head_t queue; |
| 189 | rwlock_t lock; |
| 190 | struct list_head created; |
| 191 | struct list_head emited; |
| 192 | struct list_head signaled; |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 193 | bool initialized; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 194 | }; |
| 195 | |
| 196 | struct radeon_fence { |
| 197 | struct radeon_device *rdev; |
| 198 | struct kref kref; |
| 199 | struct list_head list; |
| 200 | /* protected by radeon_fence.lock */ |
| 201 | uint32_t seq; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 202 | bool emited; |
| 203 | bool signaled; |
| 204 | }; |
| 205 | |
| 206 | int radeon_fence_driver_init(struct radeon_device *rdev); |
| 207 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
| 208 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); |
| 209 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); |
| 210 | void radeon_fence_process(struct radeon_device *rdev); |
| 211 | bool radeon_fence_signaled(struct radeon_fence *fence); |
| 212 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
| 213 | int radeon_fence_wait_next(struct radeon_device *rdev); |
| 214 | int radeon_fence_wait_last(struct radeon_device *rdev); |
| 215 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
| 216 | void radeon_fence_unref(struct radeon_fence **fence); |
| 217 | |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 218 | /* |
| 219 | * Tiling registers |
| 220 | */ |
| 221 | struct radeon_surface_reg { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 222 | struct radeon_bo *bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 223 | }; |
| 224 | |
| 225 | #define RADEON_GEM_MAX_SURFACES 8 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 226 | |
| 227 | /* |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 228 | * TTM. |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 229 | */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 230 | struct radeon_mman { |
| 231 | struct ttm_bo_global_ref bo_global_ref; |
| 232 | struct ttm_global_reference mem_global_ref; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 233 | struct ttm_bo_device bdev; |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 234 | bool mem_global_referenced; |
| 235 | bool initialized; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 236 | }; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 237 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 238 | struct radeon_bo { |
| 239 | /* Protected by gem.mutex */ |
| 240 | struct list_head list; |
| 241 | /* Protected by tbo.reserved */ |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 242 | u32 placements[3]; |
| 243 | struct ttm_placement placement; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 244 | struct ttm_buffer_object tbo; |
| 245 | struct ttm_bo_kmap_obj kmap; |
| 246 | unsigned pin_count; |
| 247 | void *kptr; |
| 248 | u32 tiling_flags; |
| 249 | u32 pitch; |
| 250 | int surface_reg; |
| 251 | /* Constant after initialization */ |
| 252 | struct radeon_device *rdev; |
| 253 | struct drm_gem_object *gobj; |
| 254 | }; |
| 255 | |
| 256 | struct radeon_bo_list { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 257 | struct list_head list; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 258 | struct radeon_bo *bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 259 | uint64_t gpu_offset; |
| 260 | unsigned rdomain; |
| 261 | unsigned wdomain; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 262 | u32 tiling_flags; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 263 | }; |
| 264 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 265 | /* |
| 266 | * GEM objects. |
| 267 | */ |
| 268 | struct radeon_gem { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 269 | struct mutex mutex; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 270 | struct list_head objects; |
| 271 | }; |
| 272 | |
| 273 | int radeon_gem_init(struct radeon_device *rdev); |
| 274 | void radeon_gem_fini(struct radeon_device *rdev); |
| 275 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 276 | int alignment, int initial_domain, |
| 277 | bool discardable, bool kernel, |
| 278 | struct drm_gem_object **obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 279 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
| 280 | uint64_t *gpu_addr); |
| 281 | void radeon_gem_object_unpin(struct drm_gem_object *obj); |
| 282 | |
| 283 | |
| 284 | /* |
| 285 | * GART structures, functions & helpers |
| 286 | */ |
| 287 | struct radeon_mc; |
| 288 | |
| 289 | struct radeon_gart_table_ram { |
| 290 | volatile uint32_t *ptr; |
| 291 | }; |
| 292 | |
| 293 | struct radeon_gart_table_vram { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 294 | struct radeon_bo *robj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 295 | volatile uint32_t *ptr; |
| 296 | }; |
| 297 | |
| 298 | union radeon_gart_table { |
| 299 | struct radeon_gart_table_ram ram; |
| 300 | struct radeon_gart_table_vram vram; |
| 301 | }; |
| 302 | |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 303 | #define RADEON_GPU_PAGE_SIZE 4096 |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 304 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 305 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 306 | struct radeon_gart { |
| 307 | dma_addr_t table_addr; |
| 308 | unsigned num_gpu_pages; |
| 309 | unsigned num_cpu_pages; |
| 310 | unsigned table_size; |
| 311 | union radeon_gart_table table; |
| 312 | struct page **pages; |
| 313 | dma_addr_t *pages_addr; |
| 314 | bool ready; |
| 315 | }; |
| 316 | |
| 317 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
| 318 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
| 319 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
| 320 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
| 321 | int radeon_gart_init(struct radeon_device *rdev); |
| 322 | void radeon_gart_fini(struct radeon_device *rdev); |
| 323 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
| 324 | int pages); |
| 325 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
| 326 | int pages, struct page **pagelist); |
| 327 | |
| 328 | |
| 329 | /* |
| 330 | * GPU MC structures, functions & helpers |
| 331 | */ |
| 332 | struct radeon_mc { |
| 333 | resource_size_t aper_size; |
| 334 | resource_size_t aper_base; |
| 335 | resource_size_t agp_base; |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 336 | /* for some chips with <= 32MB we need to lie |
| 337 | * about vram size near mc fb location */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 338 | u64 mc_vram_size; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 339 | u64 visible_vram_size; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 340 | u64 gtt_size; |
| 341 | u64 gtt_start; |
| 342 | u64 gtt_end; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 343 | u64 vram_start; |
| 344 | u64 vram_end; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 345 | unsigned vram_width; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 346 | u64 real_vram_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 347 | int vram_mtrr; |
| 348 | bool vram_is_ddr; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 349 | bool igp_sideport_enabled; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 350 | }; |
| 351 | |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 352 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
| 353 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 354 | |
| 355 | /* |
| 356 | * GPU scratch registers structures, functions & helpers |
| 357 | */ |
| 358 | struct radeon_scratch { |
| 359 | unsigned num_reg; |
| 360 | bool free[32]; |
| 361 | uint32_t reg[32]; |
| 362 | }; |
| 363 | |
| 364 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
| 365 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
| 366 | |
| 367 | |
| 368 | /* |
| 369 | * IRQS. |
| 370 | */ |
| 371 | struct radeon_irq { |
| 372 | bool installed; |
| 373 | bool sw_int; |
| 374 | /* FIXME: use a define max crtc rather than hardcode it */ |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 375 | bool crtc_vblank_int[6]; |
Rafał Miłecki | 73a6d3f | 2010-01-08 00:22:47 +0100 | [diff] [blame] | 376 | wait_queue_head_t vblank_queue; |
Alex Deucher | b500f68 | 2009-12-03 13:08:53 -0500 | [diff] [blame] | 377 | /* FIXME: use defines for max hpd/dacs */ |
| 378 | bool hpd[6]; |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 379 | /* FIXME: use defines for max HDMI blocks */ |
| 380 | bool hdmi[2]; |
Dave Airlie | 1614f8b | 2009-12-01 16:04:56 +1000 | [diff] [blame] | 381 | spinlock_t sw_lock; |
| 382 | int sw_refcount; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 383 | }; |
| 384 | |
| 385 | int radeon_irq_kms_init(struct radeon_device *rdev); |
| 386 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
Dave Airlie | 1614f8b | 2009-12-01 16:04:56 +1000 | [diff] [blame] | 387 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); |
| 388 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 389 | |
| 390 | /* |
| 391 | * CP & ring. |
| 392 | */ |
| 393 | struct radeon_ib { |
| 394 | struct list_head list; |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 395 | unsigned idx; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 396 | uint64_t gpu_addr; |
| 397 | struct radeon_fence *fence; |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 398 | uint32_t *ptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 399 | uint32_t length_dw; |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 400 | bool free; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 401 | }; |
| 402 | |
Dave Airlie | ecb114a | 2009-09-15 11:12:56 +1000 | [diff] [blame] | 403 | /* |
| 404 | * locking - |
| 405 | * mutex protects scheduled_ibs, ready, alloc_bm |
| 406 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 407 | struct radeon_ib_pool { |
| 408 | struct mutex mutex; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 409 | struct radeon_bo *robj; |
Jerome Glisse | 9f93ed3 | 2010-01-28 18:22:31 +0100 | [diff] [blame] | 410 | struct list_head bogus_ib; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 411 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
| 412 | bool ready; |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 413 | unsigned head_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 414 | }; |
| 415 | |
| 416 | struct radeon_cp { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 417 | struct radeon_bo *ring_obj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 418 | volatile uint32_t *ring; |
| 419 | unsigned rptr; |
| 420 | unsigned wptr; |
| 421 | unsigned wptr_old; |
| 422 | unsigned ring_size; |
| 423 | unsigned ring_free_dw; |
| 424 | int count_dw; |
| 425 | uint64_t gpu_addr; |
| 426 | uint32_t align_mask; |
| 427 | uint32_t ptr_mask; |
| 428 | struct mutex mutex; |
| 429 | bool ready; |
| 430 | }; |
| 431 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 432 | /* |
| 433 | * R6xx+ IH ring |
| 434 | */ |
| 435 | struct r600_ih { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 436 | struct radeon_bo *ring_obj; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 437 | volatile uint32_t *ring; |
| 438 | unsigned rptr; |
| 439 | unsigned wptr; |
| 440 | unsigned wptr_old; |
| 441 | unsigned ring_size; |
| 442 | uint64_t gpu_addr; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 443 | uint32_t ptr_mask; |
| 444 | spinlock_t lock; |
| 445 | bool enabled; |
| 446 | }; |
| 447 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 448 | struct r600_blit { |
Jerome Glisse | ff82f05 | 2010-01-22 15:19:00 +0100 | [diff] [blame] | 449 | struct mutex mutex; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 450 | struct radeon_bo *shader_obj; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 451 | u64 shader_gpu_addr; |
| 452 | u32 vs_offset, ps_offset; |
| 453 | u32 state_offset; |
| 454 | u32 state_len; |
| 455 | u32 vb_used, vb_total; |
| 456 | struct radeon_ib *vb_ib; |
| 457 | }; |
| 458 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 459 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
| 460 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
| 461 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
| 462 | int radeon_ib_pool_init(struct radeon_device *rdev); |
| 463 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
| 464 | int radeon_ib_test(struct radeon_device *rdev); |
Jerome Glisse | 9f93ed3 | 2010-01-28 18:22:31 +0100 | [diff] [blame] | 465 | extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 466 | /* Ring access between begin & end cannot sleep */ |
| 467 | void radeon_ring_free_size(struct radeon_device *rdev); |
| 468 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
| 469 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
| 470 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
| 471 | int radeon_ring_test(struct radeon_device *rdev); |
| 472 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); |
| 473 | void radeon_ring_fini(struct radeon_device *rdev); |
| 474 | |
| 475 | |
| 476 | /* |
| 477 | * CS. |
| 478 | */ |
| 479 | struct radeon_cs_reloc { |
| 480 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 481 | struct radeon_bo *robj; |
| 482 | struct radeon_bo_list lobj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 483 | uint32_t handle; |
| 484 | uint32_t flags; |
| 485 | }; |
| 486 | |
| 487 | struct radeon_cs_chunk { |
| 488 | uint32_t chunk_id; |
| 489 | uint32_t length_dw; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 490 | int kpage_idx[2]; |
| 491 | uint32_t *kpage[2]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 492 | uint32_t *kdata; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 493 | void __user *user_ptr; |
| 494 | int last_copied_page; |
| 495 | int last_page_index; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 496 | }; |
| 497 | |
| 498 | struct radeon_cs_parser { |
Jerome Glisse | c8c15ff | 2010-01-18 13:01:36 +0100 | [diff] [blame] | 499 | struct device *dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 500 | struct radeon_device *rdev; |
| 501 | struct drm_file *filp; |
| 502 | /* chunks */ |
| 503 | unsigned nchunks; |
| 504 | struct radeon_cs_chunk *chunks; |
| 505 | uint64_t *chunks_array; |
| 506 | /* IB */ |
| 507 | unsigned idx; |
| 508 | /* relocations */ |
| 509 | unsigned nrelocs; |
| 510 | struct radeon_cs_reloc *relocs; |
| 511 | struct radeon_cs_reloc **relocs_ptr; |
| 512 | struct list_head validated; |
| 513 | /* indices of various chunks */ |
| 514 | int chunk_ib_idx; |
| 515 | int chunk_relocs_idx; |
| 516 | struct radeon_ib *ib; |
| 517 | void *track; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 518 | unsigned family; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 519 | int parser_error; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 520 | }; |
| 521 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 522 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
| 523 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
| 524 | |
| 525 | |
| 526 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
| 527 | { |
| 528 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
| 529 | u32 pg_idx, pg_offset; |
| 530 | u32 idx_value = 0; |
| 531 | int new_page; |
| 532 | |
| 533 | pg_idx = (idx * 4) / PAGE_SIZE; |
| 534 | pg_offset = (idx * 4) % PAGE_SIZE; |
| 535 | |
| 536 | if (ibc->kpage_idx[0] == pg_idx) |
| 537 | return ibc->kpage[0][pg_offset/4]; |
| 538 | if (ibc->kpage_idx[1] == pg_idx) |
| 539 | return ibc->kpage[1][pg_offset/4]; |
| 540 | |
| 541 | new_page = radeon_cs_update_pages(p, pg_idx); |
| 542 | if (new_page < 0) { |
| 543 | p->parser_error = new_page; |
| 544 | return 0; |
| 545 | } |
| 546 | |
| 547 | idx_value = ibc->kpage[new_page][pg_offset/4]; |
| 548 | return idx_value; |
| 549 | } |
| 550 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 551 | struct radeon_cs_packet { |
| 552 | unsigned idx; |
| 553 | unsigned type; |
| 554 | unsigned reg; |
| 555 | unsigned opcode; |
| 556 | int count; |
| 557 | unsigned one_reg_wr; |
| 558 | }; |
| 559 | |
| 560 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
| 561 | struct radeon_cs_packet *pkt, |
| 562 | unsigned idx, unsigned reg); |
| 563 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
| 564 | struct radeon_cs_packet *pkt); |
| 565 | |
| 566 | |
| 567 | /* |
| 568 | * AGP |
| 569 | */ |
| 570 | int radeon_agp_init(struct radeon_device *rdev); |
Dave Airlie | 0ebf171 | 2009-11-05 15:39:10 +1000 | [diff] [blame] | 571 | void radeon_agp_resume(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 572 | void radeon_agp_fini(struct radeon_device *rdev); |
| 573 | |
| 574 | |
| 575 | /* |
| 576 | * Writeback |
| 577 | */ |
| 578 | struct radeon_wb { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 579 | struct radeon_bo *wb_obj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 580 | volatile uint32_t *wb; |
| 581 | uint64_t gpu_addr; |
| 582 | }; |
| 583 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 584 | /** |
| 585 | * struct radeon_pm - power management datas |
| 586 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
| 587 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
| 588 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
| 589 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
| 590 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
| 591 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
| 592 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
| 593 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
| 594 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
| 595 | * @sclk: GPU clock Mhz (core bandwith depends of this clock) |
| 596 | * @needed_bandwidth: current bandwidth needs |
| 597 | * |
| 598 | * It keeps track of various data needed to take powermanagement decision. |
| 599 | * Bandwith need is used to determine minimun clock of the GPU and memory. |
| 600 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
| 601 | * (type of memory, bus size, efficiency, ...) |
| 602 | */ |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 603 | enum radeon_pm_state { |
| 604 | PM_STATE_DISABLED, |
| 605 | PM_STATE_MINIMUM, |
| 606 | PM_STATE_PAUSED, |
| 607 | PM_STATE_ACTIVE |
| 608 | }; |
| 609 | enum radeon_pm_action { |
| 610 | PM_ACTION_NONE, |
| 611 | PM_ACTION_MINIMUM, |
| 612 | PM_ACTION_DOWNCLOCK, |
| 613 | PM_ACTION_UPCLOCK |
| 614 | }; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 615 | |
| 616 | enum radeon_voltage_type { |
| 617 | VOLTAGE_NONE = 0, |
| 618 | VOLTAGE_GPIO, |
| 619 | VOLTAGE_VDDC, |
| 620 | VOLTAGE_SW |
| 621 | }; |
| 622 | |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 623 | enum radeon_pm_state_type { |
| 624 | POWER_STATE_TYPE_DEFAULT, |
| 625 | POWER_STATE_TYPE_POWERSAVE, |
| 626 | POWER_STATE_TYPE_BATTERY, |
| 627 | POWER_STATE_TYPE_BALANCED, |
| 628 | POWER_STATE_TYPE_PERFORMANCE, |
| 629 | }; |
| 630 | |
Alex Deucher | 516d0e4 | 2009-12-23 14:28:05 -0500 | [diff] [blame] | 631 | enum radeon_pm_clock_mode_type { |
| 632 | POWER_MODE_TYPE_DEFAULT, |
| 633 | POWER_MODE_TYPE_LOW, |
| 634 | POWER_MODE_TYPE_MID, |
| 635 | POWER_MODE_TYPE_HIGH, |
| 636 | }; |
| 637 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 638 | struct radeon_voltage { |
| 639 | enum radeon_voltage_type type; |
| 640 | /* gpio voltage */ |
| 641 | struct radeon_gpio_rec gpio; |
| 642 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
| 643 | bool active_high; /* voltage drop is active when bit is high */ |
| 644 | /* VDDC voltage */ |
| 645 | u8 vddc_id; /* index into vddc voltage table */ |
| 646 | u8 vddci_id; /* index into vddci voltage table */ |
| 647 | bool vddci_enabled; |
| 648 | /* r6xx+ sw */ |
| 649 | u32 voltage; |
| 650 | }; |
| 651 | |
| 652 | struct radeon_pm_non_clock_info { |
| 653 | /* pcie lanes */ |
| 654 | int pcie_lanes; |
| 655 | /* standardized non-clock flags */ |
| 656 | u32 flags; |
| 657 | }; |
| 658 | |
| 659 | struct radeon_pm_clock_info { |
| 660 | /* memory clock */ |
| 661 | u32 mclk; |
| 662 | /* engine clock */ |
| 663 | u32 sclk; |
| 664 | /* voltage info */ |
| 665 | struct radeon_voltage voltage; |
| 666 | /* standardized clock flags - not sure we'll need these */ |
| 667 | u32 flags; |
| 668 | }; |
| 669 | |
| 670 | struct radeon_power_state { |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 671 | enum radeon_pm_state_type type; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 672 | /* XXX: use a define for num clock modes */ |
| 673 | struct radeon_pm_clock_info clock_info[8]; |
| 674 | /* number of valid clock modes in this power state */ |
| 675 | int num_clock_modes; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 676 | struct radeon_pm_clock_info *default_clock_mode; |
| 677 | /* non clock info about this state */ |
| 678 | struct radeon_pm_non_clock_info non_clock_info; |
| 679 | bool voltage_drop_active; |
| 680 | }; |
| 681 | |
Rafał Miłecki | 2745932 | 2010-02-11 22:16:36 +0000 | [diff] [blame] | 682 | /* |
| 683 | * Some modes are overclocked by very low value, accept them |
| 684 | */ |
| 685 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
| 686 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 687 | struct radeon_pm { |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 688 | struct mutex mutex; |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 689 | struct delayed_work idle_work; |
| 690 | enum radeon_pm_state state; |
| 691 | enum radeon_pm_action planned_action; |
| 692 | unsigned long action_timeout; |
| 693 | bool downclocked; |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 694 | int active_crtcs; |
| 695 | int req_vblank; |
Rafał Miłecki | 839461d | 2010-03-02 22:06:51 +0100 | [diff] [blame] | 696 | bool vblank_sync; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 697 | fixed20_12 max_bandwidth; |
| 698 | fixed20_12 igp_sideport_mclk; |
| 699 | fixed20_12 igp_system_mclk; |
| 700 | fixed20_12 igp_ht_link_clk; |
| 701 | fixed20_12 igp_ht_link_width; |
| 702 | fixed20_12 k8_bandwidth; |
| 703 | fixed20_12 sideport_bandwidth; |
| 704 | fixed20_12 ht_bandwidth; |
| 705 | fixed20_12 core_bandwidth; |
| 706 | fixed20_12 sclk; |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 707 | fixed20_12 mclk; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 708 | fixed20_12 needed_bandwidth; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 709 | /* XXX: use a define for num power modes */ |
| 710 | struct radeon_power_state power_state[8]; |
| 711 | /* number of valid power states */ |
| 712 | int num_power_states; |
| 713 | struct radeon_power_state *current_power_state; |
Rafał Miłecki | 9038dfd | 2010-02-20 23:15:04 +0000 | [diff] [blame] | 714 | struct radeon_pm_clock_info *current_clock_mode; |
Alex Deucher | 516d0e4 | 2009-12-23 14:28:05 -0500 | [diff] [blame] | 715 | struct radeon_power_state *requested_power_state; |
Rafał Miłecki | 9038dfd | 2010-02-20 23:15:04 +0000 | [diff] [blame] | 716 | struct radeon_pm_clock_info *requested_clock_mode; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 717 | struct radeon_power_state *default_power_state; |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 718 | struct radeon_i2c_chan *i2c_bus; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 719 | }; |
| 720 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 721 | |
| 722 | /* |
| 723 | * Benchmarking |
| 724 | */ |
| 725 | void radeon_benchmark(struct radeon_device *rdev); |
| 726 | |
| 727 | |
| 728 | /* |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 729 | * Testing |
| 730 | */ |
| 731 | void radeon_test_moves(struct radeon_device *rdev); |
| 732 | |
| 733 | |
| 734 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 735 | * Debugfs |
| 736 | */ |
| 737 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
| 738 | struct drm_info_list *files, |
| 739 | unsigned nfiles); |
| 740 | int radeon_debugfs_fence_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 741 | |
| 742 | |
| 743 | /* |
| 744 | * ASIC specific functions. |
| 745 | */ |
| 746 | struct radeon_asic { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 747 | int (*init)(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 748 | void (*fini)(struct radeon_device *rdev); |
| 749 | int (*resume)(struct radeon_device *rdev); |
| 750 | int (*suspend)(struct radeon_device *rdev); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 751 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 752 | bool (*gpu_is_lockup)(struct radeon_device *rdev); |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 753 | int (*asic_reset)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 754 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
| 755 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
| 756 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
| 757 | void (*cp_fini)(struct radeon_device *rdev); |
| 758 | void (*cp_disable)(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 759 | void (*cp_commit)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 760 | void (*ring_start)(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 761 | int (*ring_test)(struct radeon_device *rdev); |
| 762 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 763 | int (*irq_set)(struct radeon_device *rdev); |
| 764 | int (*irq_process)(struct radeon_device *rdev); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 765 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 766 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
| 767 | int (*cs_parse)(struct radeon_cs_parser *p); |
| 768 | int (*copy_blit)(struct radeon_device *rdev, |
| 769 | uint64_t src_offset, |
| 770 | uint64_t dst_offset, |
| 771 | unsigned num_pages, |
| 772 | struct radeon_fence *fence); |
| 773 | int (*copy_dma)(struct radeon_device *rdev, |
| 774 | uint64_t src_offset, |
| 775 | uint64_t dst_offset, |
| 776 | unsigned num_pages, |
| 777 | struct radeon_fence *fence); |
| 778 | int (*copy)(struct radeon_device *rdev, |
| 779 | uint64_t src_offset, |
| 780 | uint64_t dst_offset, |
| 781 | unsigned num_pages, |
| 782 | struct radeon_fence *fence); |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 783 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 784 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 785 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 786 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 787 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 788 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
| 789 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 790 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
| 791 | uint32_t tiling_flags, uint32_t pitch, |
| 792 | uint32_t offset, uint32_t obj_size); |
Daniel Vetter | 9479c54 | 2010-03-11 21:19:16 +0000 | [diff] [blame] | 793 | void (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 794 | void (*bandwidth_update)(struct radeon_device *rdev); |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 795 | void (*hpd_init)(struct radeon_device *rdev); |
| 796 | void (*hpd_fini)(struct radeon_device *rdev); |
| 797 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 798 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 799 | /* ioctl hw specific callback. Some hw might want to perform special |
| 800 | * operation on specific ioctl. For instance on wait idle some hw |
| 801 | * might want to perform and HDP flush through MMIO as it seems that |
| 802 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed |
| 803 | * through ring. |
| 804 | */ |
| 805 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); |
Alex Deucher | def9ba9 | 2010-04-22 12:39:58 -0400 | [diff] [blame^] | 806 | bool (*gui_idle)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 807 | }; |
| 808 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 809 | /* |
| 810 | * Asic structures |
| 811 | */ |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 812 | struct r100_gpu_lockup { |
| 813 | unsigned long last_jiffies; |
| 814 | u32 last_cp_rptr; |
| 815 | }; |
| 816 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 817 | struct r100_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 818 | const unsigned *reg_safe_bm; |
| 819 | unsigned reg_safe_bm_size; |
| 820 | u32 hdp_cntl; |
| 821 | struct r100_gpu_lockup lockup; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 822 | }; |
| 823 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 824 | struct r300_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 825 | const unsigned *reg_safe_bm; |
| 826 | unsigned reg_safe_bm_size; |
| 827 | u32 resync_scratch; |
| 828 | u32 hdp_cntl; |
| 829 | struct r100_gpu_lockup lockup; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 830 | }; |
| 831 | |
| 832 | struct r600_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 833 | unsigned max_pipes; |
| 834 | unsigned max_tile_pipes; |
| 835 | unsigned max_simds; |
| 836 | unsigned max_backends; |
| 837 | unsigned max_gprs; |
| 838 | unsigned max_threads; |
| 839 | unsigned max_stack_entries; |
| 840 | unsigned max_hw_contexts; |
| 841 | unsigned max_gs_threads; |
| 842 | unsigned sx_max_export_size; |
| 843 | unsigned sx_max_export_pos_size; |
| 844 | unsigned sx_max_export_smx_size; |
| 845 | unsigned sq_num_cf_insts; |
| 846 | unsigned tiling_nbanks; |
| 847 | unsigned tiling_npipes; |
| 848 | unsigned tiling_group_size; |
| 849 | struct r100_gpu_lockup lockup; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 850 | }; |
| 851 | |
| 852 | struct rv770_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 853 | unsigned max_pipes; |
| 854 | unsigned max_tile_pipes; |
| 855 | unsigned max_simds; |
| 856 | unsigned max_backends; |
| 857 | unsigned max_gprs; |
| 858 | unsigned max_threads; |
| 859 | unsigned max_stack_entries; |
| 860 | unsigned max_hw_contexts; |
| 861 | unsigned max_gs_threads; |
| 862 | unsigned sx_max_export_size; |
| 863 | unsigned sx_max_export_pos_size; |
| 864 | unsigned sx_max_export_smx_size; |
| 865 | unsigned sq_num_cf_insts; |
| 866 | unsigned sx_num_of_sets; |
| 867 | unsigned sc_prim_fifo_size; |
| 868 | unsigned sc_hiz_tile_fifo_size; |
| 869 | unsigned sc_earlyz_tile_fifo_fize; |
| 870 | unsigned tiling_nbanks; |
| 871 | unsigned tiling_npipes; |
| 872 | unsigned tiling_group_size; |
| 873 | struct r100_gpu_lockup lockup; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 874 | }; |
| 875 | |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 876 | struct evergreen_asic { |
| 877 | unsigned num_ses; |
| 878 | unsigned max_pipes; |
| 879 | unsigned max_tile_pipes; |
| 880 | unsigned max_simds; |
| 881 | unsigned max_backends; |
| 882 | unsigned max_gprs; |
| 883 | unsigned max_threads; |
| 884 | unsigned max_stack_entries; |
| 885 | unsigned max_hw_contexts; |
| 886 | unsigned max_gs_threads; |
| 887 | unsigned sx_max_export_size; |
| 888 | unsigned sx_max_export_pos_size; |
| 889 | unsigned sx_max_export_smx_size; |
| 890 | unsigned sq_num_cf_insts; |
| 891 | unsigned sx_num_of_sets; |
| 892 | unsigned sc_prim_fifo_size; |
| 893 | unsigned sc_hiz_tile_fifo_size; |
| 894 | unsigned sc_earlyz_tile_fifo_size; |
| 895 | unsigned tiling_nbanks; |
| 896 | unsigned tiling_npipes; |
| 897 | unsigned tiling_group_size; |
| 898 | }; |
| 899 | |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 900 | union radeon_asic_config { |
| 901 | struct r300_asic r300; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 902 | struct r100_asic r100; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 903 | struct r600_asic r600; |
| 904 | struct rv770_asic rv770; |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 905 | struct evergreen_asic evergreen; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 906 | }; |
| 907 | |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 908 | /* |
| 909 | * asic initizalization from radeon_asic.c |
| 910 | */ |
| 911 | void radeon_agp_disable(struct radeon_device *rdev); |
| 912 | int radeon_asic_init(struct radeon_device *rdev); |
| 913 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 914 | |
| 915 | /* |
| 916 | * IOCTL. |
| 917 | */ |
| 918 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, |
| 919 | struct drm_file *filp); |
| 920 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, |
| 921 | struct drm_file *filp); |
| 922 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 923 | struct drm_file *file_priv); |
| 924 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 925 | struct drm_file *file_priv); |
| 926 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 927 | struct drm_file *file_priv); |
| 928 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 929 | struct drm_file *file_priv); |
| 930 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 931 | struct drm_file *filp); |
| 932 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 933 | struct drm_file *filp); |
| 934 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 935 | struct drm_file *filp); |
| 936 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, |
| 937 | struct drm_file *filp); |
| 938 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 939 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
| 940 | struct drm_file *filp); |
| 941 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, |
| 942 | struct drm_file *filp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 943 | |
| 944 | |
| 945 | /* |
| 946 | * Core structure, functions and helpers. |
| 947 | */ |
| 948 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
| 949 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
| 950 | |
| 951 | struct radeon_device { |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 952 | struct device *dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 953 | struct drm_device *ddev; |
| 954 | struct pci_dev *pdev; |
| 955 | /* ASIC */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 956 | union radeon_asic_config config; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 957 | enum radeon_family family; |
| 958 | unsigned long flags; |
| 959 | int usec_timeout; |
| 960 | enum radeon_pll_errata pll_errata; |
| 961 | int num_gb_pipes; |
Alex Deucher | f779b3e | 2009-08-19 19:11:39 -0400 | [diff] [blame] | 962 | int num_z_pipes; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 963 | int disp_priority; |
| 964 | /* BIOS */ |
| 965 | uint8_t *bios; |
| 966 | bool is_atom_bios; |
| 967 | uint16_t bios_header_start; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 968 | struct radeon_bo *stollen_vga_memory; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 969 | /* Register mmio */ |
Dave Airlie | 4c9bc75 | 2009-06-29 18:29:12 +1000 | [diff] [blame] | 970 | resource_size_t rmmio_base; |
| 971 | resource_size_t rmmio_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 972 | void *rmmio; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 973 | radeon_rreg_t mc_rreg; |
| 974 | radeon_wreg_t mc_wreg; |
| 975 | radeon_rreg_t pll_rreg; |
| 976 | radeon_wreg_t pll_wreg; |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 977 | uint32_t pcie_reg_mask; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 978 | radeon_rreg_t pciep_rreg; |
| 979 | radeon_wreg_t pciep_wreg; |
| 980 | struct radeon_clock clock; |
| 981 | struct radeon_mc mc; |
| 982 | struct radeon_gart gart; |
| 983 | struct radeon_mode_info mode_info; |
| 984 | struct radeon_scratch scratch; |
| 985 | struct radeon_mman mman; |
| 986 | struct radeon_fence_driver fence_drv; |
| 987 | struct radeon_cp cp; |
| 988 | struct radeon_ib_pool ib_pool; |
| 989 | struct radeon_irq irq; |
| 990 | struct radeon_asic *asic; |
| 991 | struct radeon_gem gem; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 992 | struct radeon_pm pm; |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 993 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 994 | struct mutex cs_mutex; |
| 995 | struct radeon_wb wb; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 996 | struct radeon_dummy_page dummy_page; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 997 | bool gpu_lockup; |
| 998 | bool shutdown; |
| 999 | bool suspend; |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 1000 | bool need_dma32; |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 1001 | bool accel_working; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1002 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1003 | const struct firmware *me_fw; /* all family ME firmware */ |
| 1004 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1005 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1006 | struct r600_blit r600_blit; |
Alex Deucher | 3e5cb98 | 2009-10-16 12:21:24 -0400 | [diff] [blame] | 1007 | int msi_enabled; /* msi enabled */ |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1008 | struct r600_ih ih; /* r6/700 interrupt ring */ |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 1009 | struct workqueue_struct *wq; |
| 1010 | struct work_struct hotplug_work; |
Alex Deucher | 18917b6 | 2010-02-01 16:02:25 -0500 | [diff] [blame] | 1011 | int num_crtc; /* number of crtcs */ |
Alex Deucher | 40bacf1 | 2009-12-23 03:23:21 -0500 | [diff] [blame] | 1012 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1013 | |
| 1014 | /* audio stuff */ |
| 1015 | struct timer_list audio_timer; |
| 1016 | int audio_channels; |
| 1017 | int audio_rate; |
| 1018 | int audio_bits_per_sample; |
| 1019 | uint8_t audio_status_bits; |
| 1020 | uint8_t audio_category_code; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1021 | |
| 1022 | bool powered_down; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1023 | }; |
| 1024 | |
| 1025 | int radeon_device_init(struct radeon_device *rdev, |
| 1026 | struct drm_device *ddev, |
| 1027 | struct pci_dev *pdev, |
| 1028 | uint32_t flags); |
| 1029 | void radeon_device_fini(struct radeon_device *rdev); |
| 1030 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
| 1031 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1032 | /* r600 blit */ |
| 1033 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); |
| 1034 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); |
| 1035 | void r600_kms_blit_copy(struct radeon_device *rdev, |
| 1036 | u64 src_gpu_addr, u64 dst_gpu_addr, |
| 1037 | int size_bytes); |
| 1038 | |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1039 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
| 1040 | { |
Alex Deucher | 07bec2d | 2010-01-13 19:09:12 -0500 | [diff] [blame] | 1041 | if (reg < rdev->rmmio_size) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1042 | return readl(((void __iomem *)rdev->rmmio) + reg); |
| 1043 | else { |
| 1044 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
| 1045 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
| 1046 | } |
| 1047 | } |
| 1048 | |
| 1049 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 1050 | { |
Alex Deucher | 07bec2d | 2010-01-13 19:09:12 -0500 | [diff] [blame] | 1051 | if (reg < rdev->rmmio_size) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1052 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
| 1053 | else { |
| 1054 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
| 1055 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
| 1056 | } |
| 1057 | } |
| 1058 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1059 | /* |
| 1060 | * Cast helper |
| 1061 | */ |
| 1062 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1063 | |
| 1064 | /* |
| 1065 | * Registers read & write functions. |
| 1066 | */ |
| 1067 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) |
| 1068 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1069 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1070 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1071 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1072 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 1073 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 1074 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
| 1075 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
| 1076 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
| 1077 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1078 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
| 1079 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
Rafał Miłecki | aa5120d | 2010-02-18 20:24:28 +0000 | [diff] [blame] | 1080 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
| 1081 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1082 | #define WREG32_P(reg, val, mask) \ |
| 1083 | do { \ |
| 1084 | uint32_t tmp_ = RREG32(reg); \ |
| 1085 | tmp_ &= (mask); \ |
| 1086 | tmp_ |= ((val) & ~(mask)); \ |
| 1087 | WREG32(reg, tmp_); \ |
| 1088 | } while (0) |
| 1089 | #define WREG32_PLL_P(reg, val, mask) \ |
| 1090 | do { \ |
| 1091 | uint32_t tmp_ = RREG32_PLL(reg); \ |
| 1092 | tmp_ &= (mask); \ |
| 1093 | tmp_ |= ((val) & ~(mask)); \ |
| 1094 | WREG32_PLL(reg, tmp_); \ |
| 1095 | } while (0) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1096 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1097 | |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1098 | /* |
| 1099 | * Indirect registers accessor |
| 1100 | */ |
| 1101 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
| 1102 | { |
| 1103 | uint32_t r; |
| 1104 | |
| 1105 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
| 1106 | r = RREG32(RADEON_PCIE_DATA); |
| 1107 | return r; |
| 1108 | } |
| 1109 | |
| 1110 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 1111 | { |
| 1112 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
| 1113 | WREG32(RADEON_PCIE_DATA, (v)); |
| 1114 | } |
| 1115 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1116 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
| 1117 | |
| 1118 | |
| 1119 | /* |
| 1120 | * ASICs helpers. |
| 1121 | */ |
Dave Airlie | b995e43 | 2009-07-14 02:02:32 +1000 | [diff] [blame] | 1122 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
| 1123 | (rdev->pdev->device == 0x5969)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1124 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
| 1125 | (rdev->family == CHIP_RV200) || \ |
| 1126 | (rdev->family == CHIP_RS100) || \ |
| 1127 | (rdev->family == CHIP_RS200) || \ |
| 1128 | (rdev->family == CHIP_RV250) || \ |
| 1129 | (rdev->family == CHIP_RV280) || \ |
| 1130 | (rdev->family == CHIP_RS300)) |
| 1131 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
| 1132 | (rdev->family == CHIP_RV350) || \ |
| 1133 | (rdev->family == CHIP_R350) || \ |
| 1134 | (rdev->family == CHIP_RV380) || \ |
| 1135 | (rdev->family == CHIP_R420) || \ |
| 1136 | (rdev->family == CHIP_R423) || \ |
| 1137 | (rdev->family == CHIP_RV410) || \ |
| 1138 | (rdev->family == CHIP_RS400) || \ |
| 1139 | (rdev->family == CHIP_RS480)) |
| 1140 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
| 1141 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
| 1142 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1143 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1144 | |
| 1145 | /* |
| 1146 | * BIOS helpers. |
| 1147 | */ |
| 1148 | #define RBIOS8(i) (rdev->bios[i]) |
| 1149 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
| 1150 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
| 1151 | |
| 1152 | int radeon_combios_init(struct radeon_device *rdev); |
| 1153 | void radeon_combios_fini(struct radeon_device *rdev); |
| 1154 | int radeon_atombios_init(struct radeon_device *rdev); |
| 1155 | void radeon_atombios_fini(struct radeon_device *rdev); |
| 1156 | |
| 1157 | |
| 1158 | /* |
| 1159 | * RING helpers. |
| 1160 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1161 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
| 1162 | { |
| 1163 | #if DRM_DEBUG_CODE |
| 1164 | if (rdev->cp.count_dw <= 0) { |
| 1165 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
| 1166 | } |
| 1167 | #endif |
| 1168 | rdev->cp.ring[rdev->cp.wptr++] = v; |
| 1169 | rdev->cp.wptr &= rdev->cp.ptr_mask; |
| 1170 | rdev->cp.count_dw--; |
| 1171 | rdev->cp.ring_free_dw--; |
| 1172 | } |
| 1173 | |
| 1174 | |
| 1175 | /* |
| 1176 | * ASICs macro. |
| 1177 | */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1178 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1179 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
| 1180 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
| 1181 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1182 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1183 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1184 | #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev)) |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1185 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1186 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
| 1187 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1188 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1189 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1190 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
| 1191 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1192 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
| 1193 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 1194 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1195 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
| 1196 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
| 1197 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) |
| 1198 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1199 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1200 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1201 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
Rafał Miłecki | 93e7de7 | 2009-11-04 23:34:10 +0100 | [diff] [blame] | 1202 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 1203 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1204 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
| 1205 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1206 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
| 1207 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1208 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 1209 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
| 1210 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) |
| 1211 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) |
| 1212 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) |
Alex Deucher | def9ba9 | 2010-04-22 12:39:58 -0400 | [diff] [blame^] | 1213 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1214 | |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 1215 | /* Common functions */ |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 1216 | /* AGP */ |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1217 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 1218 | extern void radeon_agp_disable(struct radeon_device *rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 1219 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 1220 | extern void radeon_gart_restore(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1221 | extern int radeon_modeset_init(struct radeon_device *rdev); |
| 1222 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1223 | extern bool radeon_card_posted(struct radeon_device *rdev); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1224 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 1225 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 1226 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1227 | extern int radeon_clocks_init(struct radeon_device *rdev); |
| 1228 | extern void radeon_clocks_fini(struct radeon_device *rdev); |
| 1229 | extern void radeon_scratch_init(struct radeon_device *rdev); |
| 1230 | extern void radeon_surface_init(struct radeon_device *rdev); |
| 1231 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 1232 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 1233 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 1234 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 1235 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1236 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
| 1237 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1238 | extern int radeon_resume_kms(struct drm_device *dev); |
| 1239 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 1240 | |
Jerome Glisse | a18d7ea | 2009-09-09 22:23:27 +0200 | [diff] [blame] | 1241 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1242 | extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp); |
| 1243 | extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1244 | |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 1245 | /* rv200,rv250,rv280 */ |
| 1246 | extern void r200_set_safe_registers(struct radeon_device *rdev); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1247 | |
| 1248 | /* r300,r350,rv350,rv370,rv380 */ |
| 1249 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
| 1250 | extern void r300_mc_program(struct radeon_device *rdev); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1251 | extern void r300_mc_init(struct radeon_device *rdev); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 1252 | extern void r300_clock_startup(struct radeon_device *rdev); |
| 1253 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 1254 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
| 1255 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
| 1256 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1257 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
Jerome Glisse | a18d7ea | 2009-09-09 22:23:27 +0200 | [diff] [blame] | 1258 | |
Jerome Glisse | 905b682 | 2009-09-09 22:24:20 +0200 | [diff] [blame] | 1259 | /* r420,r423,rv410 */ |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1260 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
| 1261 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1262 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 1263 | extern void r420_pipes_init(struct radeon_device *rdev); |
Jerome Glisse | 905b682 | 2009-09-09 22:24:20 +0200 | [diff] [blame] | 1264 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1265 | /* rv515 */ |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 1266 | struct rv515_mc_save { |
| 1267 | u32 d1vga_control; |
| 1268 | u32 d2vga_control; |
| 1269 | u32 vga_render_control; |
| 1270 | u32 vga_hdp_control; |
| 1271 | u32 d1crtc_control; |
| 1272 | u32 d2crtc_control; |
| 1273 | }; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1274 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 1275 | extern void rv515_vga_render_disable(struct radeon_device *rdev); |
| 1276 | extern void rv515_set_safe_registers(struct radeon_device *rdev); |
Jerome Glisse | f0ed1f6 | 2009-09-28 20:39:19 +0200 | [diff] [blame] | 1277 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
| 1278 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); |
| 1279 | extern void rv515_clock_startup(struct radeon_device *rdev); |
| 1280 | extern void rv515_debugfs(struct radeon_device *rdev); |
| 1281 | extern int rv515_suspend(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1282 | |
Jerome Glisse | 3bc6853 | 2009-10-01 09:39:24 +0200 | [diff] [blame] | 1283 | /* rs400 */ |
| 1284 | extern int rs400_gart_init(struct radeon_device *rdev); |
| 1285 | extern int rs400_gart_enable(struct radeon_device *rdev); |
| 1286 | extern void rs400_gart_adjust_size(struct radeon_device *rdev); |
| 1287 | extern void rs400_gart_disable(struct radeon_device *rdev); |
| 1288 | extern void rs400_gart_fini(struct radeon_device *rdev); |
| 1289 | |
| 1290 | /* rs600 */ |
| 1291 | extern void rs600_set_safe_registers(struct radeon_device *rdev); |
Jerome Glisse | ac447df | 2009-09-30 22:18:43 +0200 | [diff] [blame] | 1292 | extern int rs600_irq_set(struct radeon_device *rdev); |
| 1293 | extern void rs600_irq_disable(struct radeon_device *rdev); |
Jerome Glisse | 3bc6853 | 2009-10-01 09:39:24 +0200 | [diff] [blame] | 1294 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1295 | /* rs690, rs740 */ |
| 1296 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, |
| 1297 | struct drm_display_mode *mode1, |
| 1298 | struct drm_display_mode *mode2); |
| 1299 | |
| 1300 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1301 | extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1302 | extern bool r600_card_posted(struct radeon_device *rdev); |
| 1303 | extern void r600_cp_stop(struct radeon_device *rdev); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 1304 | extern int r600_cp_start(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1305 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
| 1306 | extern int r600_cp_resume(struct radeon_device *rdev); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 1307 | extern void r600_cp_fini(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1308 | extern int r600_count_pipe_bits(uint32_t val); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1309 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 1310 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1311 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| 1312 | extern int r600_ib_test(struct radeon_device *rdev); |
| 1313 | extern int r600_ring_test(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1314 | extern void r600_wb_fini(struct radeon_device *rdev); |
Jerome Glisse | 81cc35b | 2009-10-01 18:02:12 +0200 | [diff] [blame] | 1315 | extern int r600_wb_enable(struct radeon_device *rdev); |
| 1316 | extern void r600_wb_disable(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1317 | extern void r600_scratch_init(struct radeon_device *rdev); |
| 1318 | extern int r600_blit_init(struct radeon_device *rdev); |
| 1319 | extern void r600_blit_fini(struct radeon_device *rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1320 | extern int r600_init_microcode(struct radeon_device *rdev); |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1321 | extern int r600_asic_reset(struct radeon_device *rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1322 | /* r600 irq */ |
| 1323 | extern int r600_irq_init(struct radeon_device *rdev); |
| 1324 | extern void r600_irq_fini(struct radeon_device *rdev); |
| 1325 | extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); |
| 1326 | extern int r600_irq_set(struct radeon_device *rdev); |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 1327 | extern void r600_irq_suspend(struct radeon_device *rdev); |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 1328 | extern void r600_disable_interrupts(struct radeon_device *rdev); |
| 1329 | extern void r600_rlc_stop(struct radeon_device *rdev); |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 1330 | /* r600 audio */ |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1331 | extern int r600_audio_init(struct radeon_device *rdev); |
| 1332 | extern int r600_audio_tmds_index(struct drm_encoder *encoder); |
| 1333 | extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); |
Christian König | 58bd086 | 2010-04-05 22:14:55 +0200 | [diff] [blame] | 1334 | extern int r600_audio_channels(struct radeon_device *rdev); |
| 1335 | extern int r600_audio_bits_per_sample(struct radeon_device *rdev); |
| 1336 | extern int r600_audio_rate(struct radeon_device *rdev); |
| 1337 | extern uint8_t r600_audio_status_bits(struct radeon_device *rdev); |
| 1338 | extern uint8_t r600_audio_category_code(struct radeon_device *rdev); |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 1339 | extern void r600_audio_schedule_polling(struct radeon_device *rdev); |
Christian König | 58bd086 | 2010-04-05 22:14:55 +0200 | [diff] [blame] | 1340 | extern void r600_audio_enable_polling(struct drm_encoder *encoder); |
| 1341 | extern void r600_audio_disable_polling(struct drm_encoder *encoder); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1342 | extern void r600_audio_fini(struct radeon_device *rdev); |
| 1343 | extern void r600_hdmi_init(struct drm_encoder *encoder); |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 1344 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
| 1345 | extern void r600_hdmi_disable(struct drm_encoder *encoder); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1346 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
| 1347 | extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
Christian König | 58bd086 | 2010-04-05 22:14:55 +0200 | [diff] [blame] | 1348 | extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1349 | |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 1350 | extern void r700_cp_stop(struct radeon_device *rdev); |
| 1351 | extern void r700_cp_fini(struct radeon_device *rdev); |
Alex Deucher | 0ca2ab5 | 2010-02-26 13:57:45 -0500 | [diff] [blame] | 1352 | extern void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
| 1353 | extern int evergreen_irq_set(struct radeon_device *rdev); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 1354 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1355 | /* evergreen */ |
| 1356 | struct evergreen_mc_save { |
| 1357 | u32 vga_control[6]; |
| 1358 | u32 vga_render_control; |
| 1359 | u32 vga_hdp_control; |
| 1360 | u32 crtc_control[6]; |
| 1361 | }; |
| 1362 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1363 | #include "radeon_object.h" |
| 1364 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1365 | #endif |