Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright © 2006-2007 Intel Corporation |
| 4 | * Jesse Barnes <jesse.barnes@intel.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 23 | * DEALINGS IN THE SOFTWARE. |
| 24 | * |
| 25 | * Authors: |
| 26 | * Eric Anholt <eric@anholt.net> |
| 27 | */ |
| 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 30 | #include <linux/delay.h> |
| 31 | #include "drmP.h" |
| 32 | #include "drm.h" |
| 33 | #include "drm_crtc.h" |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 34 | #include "drm_edid.h" |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 35 | #include "intel_drv.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include "i915_drm.h" |
| 37 | #include "i915_drv.h" |
| 38 | #include "intel_sdvo_regs.h" |
| 39 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 40 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) |
| 41 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) |
| 42 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) |
| 43 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0) |
| 44 | |
| 45 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ |
| 46 | SDVO_TV_MASK) |
| 47 | |
| 48 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) |
| 49 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 50 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 51 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 52 | |
Chris Wilson | 2e88e40 | 2010-08-07 11:01:27 +0100 | [diff] [blame] | 53 | static const char *tv_format_names[] = { |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 54 | "NTSC_M" , "NTSC_J" , "NTSC_443", |
| 55 | "PAL_B" , "PAL_D" , "PAL_G" , |
| 56 | "PAL_H" , "PAL_I" , "PAL_M" , |
| 57 | "PAL_N" , "PAL_NC" , "PAL_60" , |
| 58 | "SECAM_B" , "SECAM_D" , "SECAM_G" , |
| 59 | "SECAM_K" , "SECAM_K1", "SECAM_L" , |
| 60 | "SECAM_60" |
| 61 | }; |
| 62 | |
| 63 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) |
| 64 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 65 | struct intel_sdvo { |
| 66 | struct intel_encoder base; |
| 67 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 68 | struct i2c_adapter *i2c; |
Keith Packard | f9c10a9 | 2009-05-30 12:16:25 -0700 | [diff] [blame] | 69 | u8 slave_addr; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 70 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 71 | struct i2c_adapter ddc; |
| 72 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 73 | /* Register for the SDVO device: SDVOB or SDVOC */ |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 74 | int sdvo_reg; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 75 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 76 | /* Active outputs controlled by this SDVO output */ |
| 77 | uint16_t controlled_output; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 78 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 79 | /* |
| 80 | * Capabilities of the SDVO device returned by |
| 81 | * i830_sdvo_get_capabilities() |
| 82 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 83 | struct intel_sdvo_caps caps; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 84 | |
| 85 | /* Pixel clock limitations reported by the SDVO device, in kHz */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 86 | int pixel_clock_min, pixel_clock_max; |
| 87 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 88 | /* |
| 89 | * For multiple function SDVO device, |
| 90 | * this is for current attached outputs. |
| 91 | */ |
| 92 | uint16_t attached_output; |
| 93 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 94 | /** |
| 95 | * This is set if we're going to treat the device as TV-out. |
| 96 | * |
| 97 | * While we have these nice friendly flags for output types that ought |
| 98 | * to decide this for us, the S-Video output on our HDMI+S-Video card |
| 99 | * shows up as RGB1 (VGA). |
| 100 | */ |
| 101 | bool is_tv; |
| 102 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 103 | /* This is for current tv format name */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 104 | int tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 105 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 106 | /** |
| 107 | * This is set if we treat the device as HDMI, instead of DVI. |
| 108 | */ |
| 109 | bool is_hdmi; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 110 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 111 | /** |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 112 | * This is set if we detect output of sdvo device as LVDS and |
| 113 | * have a valid fixed mode to use with the panel. |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 114 | */ |
| 115 | bool is_lvds; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 116 | |
| 117 | /** |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 118 | * This is sdvo fixed pannel mode pointer |
| 119 | */ |
| 120 | struct drm_display_mode *sdvo_lvds_fixed_mode; |
| 121 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 122 | /* |
| 123 | * supported encoding mode, used to determine whether HDMI is |
| 124 | * supported |
| 125 | */ |
| 126 | struct intel_sdvo_encode encode; |
| 127 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 128 | /* DDC bus used by this SDVO encoder */ |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 129 | uint8_t ddc_bus; |
| 130 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 131 | /* Input timings for adjusted_mode */ |
| 132 | struct intel_sdvo_dtd input_dtd; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 133 | }; |
| 134 | |
| 135 | struct intel_sdvo_connector { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 136 | struct intel_connector base; |
| 137 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 138 | /* Mark the type of connector */ |
| 139 | uint16_t output_flag; |
| 140 | |
| 141 | /* This contains all current supported TV format */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 142 | u8 tv_format_supported[TV_FORMAT_NUM]; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 143 | int format_supported_num; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 144 | struct drm_property *tv_format; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 145 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 146 | /* add the property for the SDVO-TV */ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 147 | struct drm_property *left; |
| 148 | struct drm_property *right; |
| 149 | struct drm_property *top; |
| 150 | struct drm_property *bottom; |
| 151 | struct drm_property *hpos; |
| 152 | struct drm_property *vpos; |
| 153 | struct drm_property *contrast; |
| 154 | struct drm_property *saturation; |
| 155 | struct drm_property *hue; |
| 156 | struct drm_property *sharpness; |
| 157 | struct drm_property *flicker_filter; |
| 158 | struct drm_property *flicker_filter_adaptive; |
| 159 | struct drm_property *flicker_filter_2d; |
| 160 | struct drm_property *tv_chroma_filter; |
| 161 | struct drm_property *tv_luma_filter; |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 162 | struct drm_property *dot_crawl; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 163 | |
| 164 | /* add the property for the SDVO-TV/LVDS */ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 165 | struct drm_property *brightness; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 166 | |
| 167 | /* Add variable to record current setting for the above property */ |
| 168 | u32 left_margin, right_margin, top_margin, bottom_margin; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 169 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 170 | /* this is to get the range of margin.*/ |
| 171 | u32 max_hscan, max_vscan; |
| 172 | u32 max_hpos, cur_hpos; |
| 173 | u32 max_vpos, cur_vpos; |
| 174 | u32 cur_brightness, max_brightness; |
| 175 | u32 cur_contrast, max_contrast; |
| 176 | u32 cur_saturation, max_saturation; |
| 177 | u32 cur_hue, max_hue; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 178 | u32 cur_sharpness, max_sharpness; |
| 179 | u32 cur_flicker_filter, max_flicker_filter; |
| 180 | u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; |
| 181 | u32 cur_flicker_filter_2d, max_flicker_filter_2d; |
| 182 | u32 cur_tv_chroma_filter, max_tv_chroma_filter; |
| 183 | u32 cur_tv_luma_filter, max_tv_luma_filter; |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 184 | u32 cur_dot_crawl, max_dot_crawl; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 185 | }; |
| 186 | |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 187 | static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 188 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 189 | return container_of(encoder, struct intel_sdvo, base.base); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 190 | } |
| 191 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 192 | static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) |
| 193 | { |
| 194 | return container_of(intel_attached_encoder(connector), |
| 195 | struct intel_sdvo, base); |
| 196 | } |
| 197 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 198 | static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) |
| 199 | { |
| 200 | return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); |
| 201 | } |
| 202 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 203 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 204 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 205 | static bool |
| 206 | intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
| 207 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 208 | int type); |
| 209 | static bool |
| 210 | intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
| 211 | struct intel_sdvo_connector *intel_sdvo_connector); |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 212 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 213 | /** |
| 214 | * Writes the SDVOB or SDVOC with the given value, but always writes both |
| 215 | * SDVOB and SDVOC to work around apparent hardware issues (according to |
| 216 | * comments in the BIOS). |
| 217 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 218 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 219 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 220 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 221 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 222 | u32 bval = val, cval = val; |
| 223 | int i; |
| 224 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 225 | if (intel_sdvo->sdvo_reg == PCH_SDVOB) { |
| 226 | I915_WRITE(intel_sdvo->sdvo_reg, val); |
| 227 | I915_READ(intel_sdvo->sdvo_reg); |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 228 | return; |
| 229 | } |
| 230 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 231 | if (intel_sdvo->sdvo_reg == SDVOB) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 232 | cval = I915_READ(SDVOC); |
| 233 | } else { |
| 234 | bval = I915_READ(SDVOB); |
| 235 | } |
| 236 | /* |
| 237 | * Write the registers twice for luck. Sometimes, |
| 238 | * writing them only once doesn't appear to 'stick'. |
| 239 | * The BIOS does this too. Yay, magic |
| 240 | */ |
| 241 | for (i = 0; i < 2; i++) |
| 242 | { |
| 243 | I915_WRITE(SDVOB, bval); |
| 244 | I915_READ(SDVOB); |
| 245 | I915_WRITE(SDVOC, cval); |
| 246 | I915_READ(SDVOC); |
| 247 | } |
| 248 | } |
| 249 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 250 | static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 251 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 252 | struct i2c_msg msgs[] = { |
| 253 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 254 | .addr = intel_sdvo->slave_addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 255 | .flags = 0, |
| 256 | .len = 1, |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 257 | .buf = &addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 258 | }, |
| 259 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 260 | .addr = intel_sdvo->slave_addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 261 | .flags = I2C_M_RD, |
| 262 | .len = 1, |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 263 | .buf = ch, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 264 | } |
| 265 | }; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 266 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 267 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 268 | if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 269 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 270 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 271 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 272 | return false; |
| 273 | } |
| 274 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 275 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} |
| 276 | /** Mapping of command numbers to names, for debug output */ |
Tobias Klauser | 005568b | 2009-02-09 22:02:42 +0100 | [diff] [blame] | 277 | static const struct _sdvo_cmd_name { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 278 | u8 cmd; |
Chris Wilson | 2e88e40 | 2010-08-07 11:01:27 +0100 | [diff] [blame] | 279 | const char *name; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 280 | } sdvo_cmd_names[] = { |
| 281 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), |
| 282 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), |
| 283 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), |
| 284 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), |
| 285 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), |
| 286 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), |
| 287 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), |
| 288 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), |
| 289 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), |
| 290 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), |
| 291 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), |
| 292 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), |
| 293 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), |
| 294 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), |
| 295 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), |
| 296 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), |
| 297 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), |
| 298 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
| 299 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), |
| 300 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
| 301 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), |
| 302 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), |
| 303 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), |
| 304 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), |
| 305 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), |
| 306 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), |
| 307 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), |
| 308 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), |
| 309 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), |
| 310 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), |
| 311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), |
| 312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), |
| 313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), |
| 314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), |
| 315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), |
| 317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), |
| 318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), |
| 319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), |
| 322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), |
| 323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 324 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 325 | /* Add the op code for SDVO enhancements */ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), |
| 327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), |
| 328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), |
| 329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), |
| 330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), |
| 331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), |
| 333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), |
| 334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), |
| 335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), |
| 336 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), |
| 337 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), |
| 338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), |
| 339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), |
| 340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), |
| 341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), |
| 342 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), |
| 343 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), |
| 344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), |
| 345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), |
| 346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), |
| 347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), |
| 348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), |
| 349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), |
| 351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), |
| 352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), |
| 353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), |
| 354 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), |
| 355 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), |
| 356 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), |
| 357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), |
| 358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), |
| 359 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), |
| 360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), |
| 361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), |
| 362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), |
| 363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), |
| 364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), |
| 365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), |
| 366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), |
| 367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), |
| 368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), |
| 369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), |
| 370 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 371 | /* HDMI op code */ |
| 372 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), |
| 373 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), |
| 374 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), |
| 375 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), |
| 376 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), |
| 377 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), |
| 378 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), |
| 379 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), |
| 380 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), |
| 381 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), |
| 382 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), |
| 383 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), |
| 384 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), |
| 385 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), |
| 386 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), |
| 387 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), |
| 388 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), |
| 389 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), |
| 390 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), |
| 391 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 392 | }; |
| 393 | |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 394 | #define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 395 | #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC") |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 396 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 397 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 398 | const void *args, int args_len) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 399 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 400 | int i; |
| 401 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 402 | DRM_DEBUG_KMS("%s: W: %02X ", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 403 | SDVO_NAME(intel_sdvo), cmd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 404 | for (i = 0; i < args_len; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 405 | DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 406 | for (; i < 8; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 407 | DRM_LOG_KMS(" "); |
Kulikov Vasiliy | 04ad327 | 2010-06-28 15:54:56 +0400 | [diff] [blame] | 408 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 409 | if (cmd == sdvo_cmd_names[i].cmd) { |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 410 | DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 411 | break; |
| 412 | } |
| 413 | } |
Kulikov Vasiliy | 04ad327 | 2010-06-28 15:54:56 +0400 | [diff] [blame] | 414 | if (i == ARRAY_SIZE(sdvo_cmd_names)) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 415 | DRM_LOG_KMS("(%02X)", cmd); |
| 416 | DRM_LOG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 417 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 418 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 419 | static const char *cmd_status_names[] = { |
| 420 | "Power on", |
| 421 | "Success", |
| 422 | "Not supported", |
| 423 | "Invalid arg", |
| 424 | "Pending", |
| 425 | "Target not specified", |
| 426 | "Scaling not supported" |
| 427 | }; |
| 428 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 429 | static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
| 430 | const void *args, int args_len) |
| 431 | { |
| 432 | u8 buf[args_len*2 + 2], status; |
| 433 | struct i2c_msg msgs[args_len + 3]; |
| 434 | int i, ret; |
| 435 | |
| 436 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); |
| 437 | |
| 438 | for (i = 0; i < args_len; i++) { |
| 439 | msgs[i].addr = intel_sdvo->slave_addr; |
| 440 | msgs[i].flags = 0; |
| 441 | msgs[i].len = 2; |
| 442 | msgs[i].buf = buf + 2 *i; |
| 443 | buf[2*i + 0] = SDVO_I2C_ARG_0 - i; |
| 444 | buf[2*i + 1] = ((u8*)args)[i]; |
| 445 | } |
| 446 | msgs[i].addr = intel_sdvo->slave_addr; |
| 447 | msgs[i].flags = 0; |
| 448 | msgs[i].len = 2; |
| 449 | msgs[i].buf = buf + 2*i; |
| 450 | buf[2*i + 0] = SDVO_I2C_OPCODE; |
| 451 | buf[2*i + 1] = cmd; |
| 452 | |
| 453 | /* the following two are to read the response */ |
| 454 | status = SDVO_I2C_CMD_STATUS; |
| 455 | msgs[i+1].addr = intel_sdvo->slave_addr; |
| 456 | msgs[i+1].flags = 0; |
| 457 | msgs[i+1].len = 1; |
| 458 | msgs[i+1].buf = &status; |
| 459 | |
| 460 | msgs[i+2].addr = intel_sdvo->slave_addr; |
| 461 | msgs[i+2].flags = I2C_M_RD; |
| 462 | msgs[i+2].len = 1; |
| 463 | msgs[i+2].buf = &status; |
| 464 | |
| 465 | ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); |
| 466 | if (ret < 0) { |
| 467 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); |
| 468 | return false; |
| 469 | } |
| 470 | if (ret != i+3) { |
| 471 | /* failure in I2C transfer */ |
| 472 | DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); |
| 473 | return false; |
| 474 | } |
| 475 | |
| 476 | i = 3; |
| 477 | while (status == SDVO_CMD_STATUS_PENDING && i--) { |
| 478 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 479 | SDVO_I2C_CMD_STATUS, |
| 480 | &status)) |
| 481 | return false; |
| 482 | } |
| 483 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 484 | DRM_DEBUG_KMS("command returns response %s [%d]\n", |
| 485 | status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP ? cmd_status_names[status] : "???", |
| 486 | status); |
| 487 | return false; |
| 488 | } |
| 489 | |
| 490 | return true; |
| 491 | } |
| 492 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 493 | static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, |
| 494 | void *response, int response_len) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 495 | { |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 496 | u8 retry = 5; |
| 497 | u8 status; |
Zhenyu Wang | 33b5296 | 2009-03-24 14:02:40 +0800 | [diff] [blame] | 498 | int i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 499 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 500 | /* |
| 501 | * The documentation states that all commands will be |
| 502 | * processed within 15µs, and that we need only poll |
| 503 | * the status byte a maximum of 3 times in order for the |
| 504 | * command to be complete. |
| 505 | * |
| 506 | * Check 5 times in case the hardware failed to read the docs. |
| 507 | */ |
| 508 | do { |
| 509 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 510 | SDVO_I2C_CMD_STATUS, |
| 511 | &status)) |
| 512 | return false; |
| 513 | } while (status == SDVO_CMD_STATUS_PENDING && --retry); |
| 514 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 515 | DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 516 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 517 | DRM_LOG_KMS("(%s)", cmd_status_names[status]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 518 | else |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 519 | DRM_LOG_KMS("(??? %d)", status); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 520 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 521 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 522 | goto log_fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 523 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 524 | /* Read the command response */ |
| 525 | for (i = 0; i < response_len; i++) { |
| 526 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 527 | SDVO_I2C_RETURN_0 + i, |
| 528 | &((u8 *)response)[i])) |
| 529 | goto log_fail; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 530 | DRM_LOG_KMS(" %02X", ((u8 *)response)[i]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 531 | } |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 532 | DRM_LOG_KMS("\n"); |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 533 | return true; |
| 534 | |
| 535 | log_fail: |
| 536 | DRM_LOG_KMS("\n"); |
| 537 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 538 | } |
| 539 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 540 | static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 541 | { |
| 542 | if (mode->clock >= 100000) |
| 543 | return 1; |
| 544 | else if (mode->clock >= 50000) |
| 545 | return 2; |
| 546 | else |
| 547 | return 4; |
| 548 | } |
| 549 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 550 | static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, |
| 551 | u8 ddc_bus) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 552 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 553 | return intel_sdvo_write_cmd(intel_sdvo, |
| 554 | SDVO_CMD_SET_CONTROL_BUS_SWITCH, |
| 555 | &ddc_bus, 1); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 556 | } |
| 557 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 558 | static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) |
| 559 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 560 | return intel_sdvo_write_cmd(intel_sdvo, cmd, data, len); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 561 | } |
| 562 | |
| 563 | static bool |
| 564 | intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) |
| 565 | { |
| 566 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) |
| 567 | return false; |
| 568 | |
| 569 | return intel_sdvo_read_response(intel_sdvo, value, len); |
| 570 | } |
| 571 | |
| 572 | static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 573 | { |
| 574 | struct intel_sdvo_set_target_input_args targets = {0}; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 575 | return intel_sdvo_set_value(intel_sdvo, |
| 576 | SDVO_CMD_SET_TARGET_INPUT, |
| 577 | &targets, sizeof(targets)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 578 | } |
| 579 | |
| 580 | /** |
| 581 | * Return whether each input is trained. |
| 582 | * |
| 583 | * This function is making an assumption about the layout of the response, |
| 584 | * which should be checked against the docs. |
| 585 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 586 | static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 587 | { |
| 588 | struct intel_sdvo_get_trained_inputs_response response; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 589 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 590 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, |
| 591 | &response, sizeof(response))) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 592 | return false; |
| 593 | |
| 594 | *input_1 = response.input0_trained; |
| 595 | *input_2 = response.input1_trained; |
| 596 | return true; |
| 597 | } |
| 598 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 599 | static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 600 | u16 outputs) |
| 601 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 602 | return intel_sdvo_set_value(intel_sdvo, |
| 603 | SDVO_CMD_SET_ACTIVE_OUTPUTS, |
| 604 | &outputs, sizeof(outputs)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 605 | } |
| 606 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 607 | static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 608 | int mode) |
| 609 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 610 | u8 state = SDVO_ENCODER_STATE_ON; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 611 | |
| 612 | switch (mode) { |
| 613 | case DRM_MODE_DPMS_ON: |
| 614 | state = SDVO_ENCODER_STATE_ON; |
| 615 | break; |
| 616 | case DRM_MODE_DPMS_STANDBY: |
| 617 | state = SDVO_ENCODER_STATE_STANDBY; |
| 618 | break; |
| 619 | case DRM_MODE_DPMS_SUSPEND: |
| 620 | state = SDVO_ENCODER_STATE_SUSPEND; |
| 621 | break; |
| 622 | case DRM_MODE_DPMS_OFF: |
| 623 | state = SDVO_ENCODER_STATE_OFF; |
| 624 | break; |
| 625 | } |
| 626 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 627 | return intel_sdvo_set_value(intel_sdvo, |
| 628 | SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 629 | } |
| 630 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 631 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 632 | int *clock_min, |
| 633 | int *clock_max) |
| 634 | { |
| 635 | struct intel_sdvo_pixel_clock_range clocks; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 636 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 637 | if (!intel_sdvo_get_value(intel_sdvo, |
| 638 | SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, |
| 639 | &clocks, sizeof(clocks))) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 640 | return false; |
| 641 | |
| 642 | /* Convert the values from units of 10 kHz to kHz. */ |
| 643 | *clock_min = clocks.min * 10; |
| 644 | *clock_max = clocks.max * 10; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 645 | return true; |
| 646 | } |
| 647 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 648 | static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 649 | u16 outputs) |
| 650 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 651 | return intel_sdvo_set_value(intel_sdvo, |
| 652 | SDVO_CMD_SET_TARGET_OUTPUT, |
| 653 | &outputs, sizeof(outputs)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 654 | } |
| 655 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 656 | static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 657 | struct intel_sdvo_dtd *dtd) |
| 658 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 659 | return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
| 660 | intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 661 | } |
| 662 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 663 | static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 664 | struct intel_sdvo_dtd *dtd) |
| 665 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 666 | return intel_sdvo_set_timing(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 667 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); |
| 668 | } |
| 669 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 670 | static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 671 | struct intel_sdvo_dtd *dtd) |
| 672 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 673 | return intel_sdvo_set_timing(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 674 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); |
| 675 | } |
| 676 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 677 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 678 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 679 | uint16_t clock, |
| 680 | uint16_t width, |
| 681 | uint16_t height) |
| 682 | { |
| 683 | struct intel_sdvo_preferred_input_timing_args args; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 684 | |
Zhenyu Wang | e642c6f | 2009-03-24 14:02:42 +0800 | [diff] [blame] | 685 | memset(&args, 0, sizeof(args)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 686 | args.clock = clock; |
| 687 | args.width = width; |
| 688 | args.height = height; |
Zhenyu Wang | e642c6f | 2009-03-24 14:02:42 +0800 | [diff] [blame] | 689 | args.interlace = 0; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 690 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 691 | if (intel_sdvo->is_lvds && |
| 692 | (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || |
| 693 | intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 694 | args.scaled = 1; |
| 695 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 696 | return intel_sdvo_set_value(intel_sdvo, |
| 697 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, |
| 698 | &args, sizeof(args)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 699 | } |
| 700 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 701 | static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 702 | struct intel_sdvo_dtd *dtd) |
| 703 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 704 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, |
| 705 | &dtd->part1, sizeof(dtd->part1)) && |
| 706 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, |
| 707 | &dtd->part2, sizeof(dtd->part2)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 708 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 709 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 710 | static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 711 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 712 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 713 | } |
| 714 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 715 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 716 | const struct drm_display_mode *mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 717 | { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 718 | uint16_t width, height; |
| 719 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; |
| 720 | uint16_t h_sync_offset, v_sync_offset; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 721 | |
| 722 | width = mode->crtc_hdisplay; |
| 723 | height = mode->crtc_vdisplay; |
| 724 | |
| 725 | /* do some mode translations */ |
| 726 | h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start; |
| 727 | h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; |
| 728 | |
| 729 | v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start; |
| 730 | v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; |
| 731 | |
| 732 | h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start; |
| 733 | v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start; |
| 734 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 735 | dtd->part1.clock = mode->clock / 10; |
| 736 | dtd->part1.h_active = width & 0xff; |
| 737 | dtd->part1.h_blank = h_blank_len & 0xff; |
| 738 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 739 | ((h_blank_len >> 8) & 0xf); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 740 | dtd->part1.v_active = height & 0xff; |
| 741 | dtd->part1.v_blank = v_blank_len & 0xff; |
| 742 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 743 | ((v_blank_len >> 8) & 0xf); |
| 744 | |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 745 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 746 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
| 747 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 748 | (v_sync_len & 0xf); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 749 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 750 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
| 751 | ((v_sync_len & 0x30) >> 4); |
| 752 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 753 | dtd->part2.dtd_flags = 0x18; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 754 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 755 | dtd->part2.dtd_flags |= 0x2; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 756 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 757 | dtd->part2.dtd_flags |= 0x4; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 758 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 759 | dtd->part2.sdvo_flags = 0; |
| 760 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; |
| 761 | dtd->part2.reserved = 0; |
| 762 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 763 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 764 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 765 | const struct intel_sdvo_dtd *dtd) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 766 | { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 767 | mode->hdisplay = dtd->part1.h_active; |
| 768 | mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; |
| 769 | mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 770 | mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 771 | mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; |
| 772 | mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; |
| 773 | mode->htotal = mode->hdisplay + dtd->part1.h_blank; |
| 774 | mode->htotal += (dtd->part1.h_high & 0xf) << 8; |
| 775 | |
| 776 | mode->vdisplay = dtd->part1.v_active; |
| 777 | mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; |
| 778 | mode->vsync_start = mode->vdisplay; |
| 779 | mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 780 | mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 781 | mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; |
| 782 | mode->vsync_end = mode->vsync_start + |
| 783 | (dtd->part2.v_sync_off_width & 0xf); |
| 784 | mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; |
| 785 | mode->vtotal = mode->vdisplay + dtd->part1.v_blank; |
| 786 | mode->vtotal += (dtd->part1.v_high & 0xf) << 8; |
| 787 | |
| 788 | mode->clock = dtd->part1.clock * 10; |
| 789 | |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 790 | mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 791 | if (dtd->part2.dtd_flags & 0x2) |
| 792 | mode->flags |= DRM_MODE_FLAG_PHSYNC; |
| 793 | if (dtd->part2.dtd_flags & 0x4) |
| 794 | mode->flags |= DRM_MODE_FLAG_PVSYNC; |
| 795 | } |
| 796 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 797 | static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 798 | struct intel_sdvo_encode *encode) |
| 799 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 800 | if (intel_sdvo_get_value(intel_sdvo, |
| 801 | SDVO_CMD_GET_SUPP_ENCODE, |
| 802 | encode, sizeof(*encode))) |
| 803 | return true; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 804 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 805 | /* non-support means DVI */ |
| 806 | memset(encode, 0, sizeof(*encode)); |
| 807 | return false; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 808 | } |
| 809 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 810 | static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 811 | uint8_t mode) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 812 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 813 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 814 | } |
| 815 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 816 | static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 817 | uint8_t mode) |
| 818 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 819 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 820 | } |
| 821 | |
| 822 | #if 0 |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 823 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 824 | { |
| 825 | int i, j; |
| 826 | uint8_t set_buf_index[2]; |
| 827 | uint8_t av_split; |
| 828 | uint8_t buf_size; |
| 829 | uint8_t buf[48]; |
| 830 | uint8_t *pos; |
| 831 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 832 | intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 833 | |
| 834 | for (i = 0; i <= av_split; i++) { |
| 835 | set_buf_index[0] = i; set_buf_index[1] = 0; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 836 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 837 | set_buf_index, 2); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 838 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); |
| 839 | intel_sdvo_read_response(encoder, &buf_size, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 840 | |
| 841 | pos = buf; |
| 842 | for (j = 0; j <= buf_size; j += 8) { |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 843 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 844 | NULL, 0); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 845 | intel_sdvo_read_response(encoder, pos, 8); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 846 | pos += 8; |
| 847 | } |
| 848 | } |
| 849 | } |
| 850 | #endif |
| 851 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 852 | static bool intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo, |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 853 | int index, |
| 854 | uint8_t *data, int8_t size, uint8_t tx_rate) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 855 | { |
| 856 | uint8_t set_buf_index[2]; |
| 857 | |
| 858 | set_buf_index[0] = index; |
| 859 | set_buf_index[1] = 0; |
| 860 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 861 | if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX, |
| 862 | set_buf_index, 2)) |
| 863 | return false; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 864 | |
| 865 | for (; size > 0; size -= 8) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 866 | if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8)) |
| 867 | return false; |
| 868 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 869 | data += 8; |
| 870 | } |
| 871 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 872 | return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 873 | } |
| 874 | |
| 875 | static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size) |
| 876 | { |
| 877 | uint8_t csum = 0; |
| 878 | int i; |
| 879 | |
| 880 | for (i = 0; i < size; i++) |
| 881 | csum += data[i]; |
| 882 | |
| 883 | return 0x100 - csum; |
| 884 | } |
| 885 | |
| 886 | #define DIP_TYPE_AVI 0x82 |
| 887 | #define DIP_VERSION_AVI 0x2 |
| 888 | #define DIP_LEN_AVI 13 |
| 889 | |
| 890 | struct dip_infoframe { |
| 891 | uint8_t type; |
| 892 | uint8_t version; |
| 893 | uint8_t len; |
| 894 | uint8_t checksum; |
| 895 | union { |
| 896 | struct { |
| 897 | /* Packet Byte #1 */ |
| 898 | uint8_t S:2; |
| 899 | uint8_t B:2; |
| 900 | uint8_t A:1; |
| 901 | uint8_t Y:2; |
| 902 | uint8_t rsvd1:1; |
| 903 | /* Packet Byte #2 */ |
| 904 | uint8_t R:4; |
| 905 | uint8_t M:2; |
| 906 | uint8_t C:2; |
| 907 | /* Packet Byte #3 */ |
| 908 | uint8_t SC:2; |
| 909 | uint8_t Q:2; |
| 910 | uint8_t EC:3; |
| 911 | uint8_t ITC:1; |
| 912 | /* Packet Byte #4 */ |
| 913 | uint8_t VIC:7; |
| 914 | uint8_t rsvd2:1; |
| 915 | /* Packet Byte #5 */ |
| 916 | uint8_t PR:4; |
| 917 | uint8_t rsvd3:4; |
| 918 | /* Packet Byte #6~13 */ |
| 919 | uint16_t top_bar_end; |
| 920 | uint16_t bottom_bar_start; |
| 921 | uint16_t left_bar_end; |
| 922 | uint16_t right_bar_start; |
| 923 | } avi; |
| 924 | struct { |
| 925 | /* Packet Byte #1 */ |
| 926 | uint8_t channel_count:3; |
| 927 | uint8_t rsvd1:1; |
| 928 | uint8_t coding_type:4; |
| 929 | /* Packet Byte #2 */ |
| 930 | uint8_t sample_size:2; /* SS0, SS1 */ |
| 931 | uint8_t sample_frequency:3; |
| 932 | uint8_t rsvd2:3; |
| 933 | /* Packet Byte #3 */ |
| 934 | uint8_t coding_type_private:5; |
| 935 | uint8_t rsvd3:3; |
| 936 | /* Packet Byte #4 */ |
| 937 | uint8_t channel_allocation; |
| 938 | /* Packet Byte #5 */ |
| 939 | uint8_t rsvd4:3; |
| 940 | uint8_t level_shift:4; |
| 941 | uint8_t downmix_inhibit:1; |
| 942 | } audio; |
| 943 | uint8_t payload[28]; |
| 944 | } __attribute__ ((packed)) u; |
| 945 | } __attribute__((packed)); |
| 946 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 947 | static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 948 | struct drm_display_mode * mode) |
| 949 | { |
| 950 | struct dip_infoframe avi_if = { |
| 951 | .type = DIP_TYPE_AVI, |
| 952 | .version = DIP_VERSION_AVI, |
| 953 | .len = DIP_LEN_AVI, |
| 954 | }; |
| 955 | |
| 956 | avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if, |
| 957 | 4 + avi_if.len); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 958 | return intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if, |
| 959 | 4 + avi_if.len, |
| 960 | SDVO_HBUF_TX_VSYNC); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 961 | } |
| 962 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 963 | static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 964 | { |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 965 | struct intel_sdvo_tv_format format; |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 966 | uint32_t format_map; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 967 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 968 | format_map = 1 << intel_sdvo->tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 969 | memset(&format, 0, sizeof(format)); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 970 | memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 971 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 972 | BUILD_BUG_ON(sizeof(format) != 6); |
| 973 | return intel_sdvo_set_value(intel_sdvo, |
| 974 | SDVO_CMD_SET_TV_FORMAT, |
| 975 | &format, sizeof(format)); |
| 976 | } |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 977 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 978 | static bool |
| 979 | intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, |
| 980 | struct drm_display_mode *mode) |
| 981 | { |
| 982 | struct intel_sdvo_dtd output_dtd; |
| 983 | |
| 984 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 985 | intel_sdvo->attached_output)) |
| 986 | return false; |
| 987 | |
| 988 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
| 989 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
| 990 | return false; |
| 991 | |
| 992 | return true; |
| 993 | } |
| 994 | |
| 995 | static bool |
| 996 | intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo, |
| 997 | struct drm_display_mode *mode, |
| 998 | struct drm_display_mode *adjusted_mode) |
| 999 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1000 | /* Reset the input timing to the screen. Assume always input 0. */ |
| 1001 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
| 1002 | return false; |
| 1003 | |
| 1004 | if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, |
| 1005 | mode->clock / 10, |
| 1006 | mode->hdisplay, |
| 1007 | mode->vdisplay)) |
| 1008 | return false; |
| 1009 | |
| 1010 | if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1011 | &intel_sdvo->input_dtd)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1012 | return false; |
| 1013 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1014 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1015 | |
| 1016 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1017 | return true; |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1018 | } |
| 1019 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1020 | static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, |
| 1021 | struct drm_display_mode *mode, |
| 1022 | struct drm_display_mode *adjusted_mode) |
| 1023 | { |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 1024 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1025 | int multiplier; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1026 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1027 | /* We need to construct preferred input timings based on our |
| 1028 | * output timings. To do that, we have to set the output |
| 1029 | * timings, even though this isn't really the right place in |
| 1030 | * the sequence to do it. Oh well. |
| 1031 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1032 | if (intel_sdvo->is_tv) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1033 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1034 | return false; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1035 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1036 | (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo, |
| 1037 | mode, |
| 1038 | adjusted_mode); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1039 | } else if (intel_sdvo->is_lvds) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1040 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1041 | intel_sdvo->sdvo_lvds_fixed_mode)) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1042 | return false; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1043 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1044 | (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo, |
| 1045 | mode, |
| 1046 | adjusted_mode); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1047 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1048 | |
| 1049 | /* Make the CRTC code factor in the SDVO pixel multiplier. The |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1050 | * SDVO device will factor out the multiplier during mode_set. |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1051 | */ |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1052 | multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode); |
| 1053 | intel_mode_set_pixel_multiplier(adjusted_mode, multiplier); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1054 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1055 | return true; |
| 1056 | } |
| 1057 | |
| 1058 | static void intel_sdvo_mode_set(struct drm_encoder *encoder, |
| 1059 | struct drm_display_mode *mode, |
| 1060 | struct drm_display_mode *adjusted_mode) |
| 1061 | { |
| 1062 | struct drm_device *dev = encoder->dev; |
| 1063 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1064 | struct drm_crtc *crtc = encoder->crtc; |
| 1065 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 1066 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1067 | u32 sdvox; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1068 | struct intel_sdvo_in_out_map in_out; |
| 1069 | struct intel_sdvo_dtd input_dtd; |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1070 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
| 1071 | int rate; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1072 | |
| 1073 | if (!mode) |
| 1074 | return; |
| 1075 | |
| 1076 | /* First, set the input mapping for the first input to our controlled |
| 1077 | * output. This is only correct if we're a single-input device, in |
| 1078 | * which case the first input is the output from the appropriate SDVO |
| 1079 | * channel on the motherboard. In a two-input device, the first input |
| 1080 | * will be SDVOB and the second SDVOC. |
| 1081 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1082 | in_out.in0 = intel_sdvo->attached_output; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1083 | in_out.in1 = 0; |
| 1084 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1085 | intel_sdvo_set_value(intel_sdvo, |
| 1086 | SDVO_CMD_SET_IN_OUT_MAP, |
| 1087 | &in_out, sizeof(in_out)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1088 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1089 | /* Set the output timings to the screen */ |
| 1090 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 1091 | intel_sdvo->attached_output)) |
| 1092 | return; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1093 | |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1094 | /* We have tried to get input timing in mode_fixup, and filled into |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1095 | * adjusted_mode. |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1096 | */ |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1097 | if (intel_sdvo->is_tv || intel_sdvo->is_lvds) { |
| 1098 | input_dtd = intel_sdvo->input_dtd; |
| 1099 | } else { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1100 | /* Set the output timing to the screen */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1101 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 1102 | intel_sdvo->attached_output)) |
| 1103 | return; |
| 1104 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1105 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1106 | (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1107 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1108 | |
| 1109 | /* Set the input timing to the screen. Assume always input 0. */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1110 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
| 1111 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1112 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1113 | if (intel_sdvo->is_hdmi && |
| 1114 | !intel_sdvo_set_avi_infoframe(intel_sdvo, mode)) |
| 1115 | return; |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1116 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1117 | if (intel_sdvo->is_tv && |
| 1118 | !intel_sdvo_set_tv_format(intel_sdvo)) |
| 1119 | return; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1120 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1121 | (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1122 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1123 | switch (pixel_multiplier) { |
| 1124 | default: |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1125 | case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; |
| 1126 | case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; |
| 1127 | case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1128 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1129 | if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) |
| 1130 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1131 | |
| 1132 | /* Set the SDVO control regs. */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1133 | if (INTEL_INFO(dev)->gen >= 4) { |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1134 | sdvox = SDVO_BORDER_ENABLE; |
Adam Jackson | 81a14b4 | 2010-07-16 14:46:32 -0400 | [diff] [blame] | 1135 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1136 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; |
| 1137 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1138 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1139 | } else { |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1140 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1141 | switch (intel_sdvo->sdvo_reg) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1142 | case SDVOB: |
| 1143 | sdvox &= SDVOB_PRESERVE_MASK; |
| 1144 | break; |
| 1145 | case SDVOC: |
| 1146 | sdvox &= SDVOC_PRESERVE_MASK; |
| 1147 | break; |
| 1148 | } |
| 1149 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; |
| 1150 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1151 | if (intel_crtc->pipe == 1) |
| 1152 | sdvox |= SDVO_PIPE_B_SELECT; |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1153 | if (intel_sdvo->is_hdmi) |
| 1154 | sdvox |= SDVO_AUDIO_ENABLE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1155 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1156 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1157 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
| 1158 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
| 1159 | /* done in crtc_mode_set as it lives inside the dpll register */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1160 | } else { |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1161 | sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1162 | } |
| 1163 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1164 | if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1165 | sdvox |= SDVO_STALL_SELECT; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1166 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1167 | } |
| 1168 | |
| 1169 | static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) |
| 1170 | { |
| 1171 | struct drm_device *dev = encoder->dev; |
| 1172 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 1173 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1174 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1175 | u32 temp; |
| 1176 | |
| 1177 | if (mode != DRM_MODE_DPMS_ON) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1178 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1179 | if (0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1180 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1181 | |
| 1182 | if (mode == DRM_MODE_DPMS_OFF) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1183 | temp = I915_READ(intel_sdvo->sdvo_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1184 | if ((temp & SDVO_ENABLE) != 0) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1185 | intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1186 | } |
| 1187 | } |
| 1188 | } else { |
| 1189 | bool input1, input2; |
| 1190 | int i; |
| 1191 | u8 status; |
| 1192 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1193 | temp = I915_READ(intel_sdvo->sdvo_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1194 | if ((temp & SDVO_ENABLE) == 0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1195 | intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1196 | for (i = 0; i < 2; i++) |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1197 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1198 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1199 | status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1200 | /* Warn if the device reported failure to sync. |
| 1201 | * A lot of SDVO devices fail to notify of sync, but it's |
| 1202 | * a given it the status is a success, we succeeded. |
| 1203 | */ |
| 1204 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1205 | DRM_DEBUG_KMS("First %s output reported failure to " |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1206 | "sync\n", SDVO_NAME(intel_sdvo)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1207 | } |
| 1208 | |
| 1209 | if (0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1210 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
| 1211 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1212 | } |
| 1213 | return; |
| 1214 | } |
| 1215 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1216 | static int intel_sdvo_mode_valid(struct drm_connector *connector, |
| 1217 | struct drm_display_mode *mode) |
| 1218 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1219 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1220 | |
| 1221 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 1222 | return MODE_NO_DBLESCAN; |
| 1223 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1224 | if (intel_sdvo->pixel_clock_min > mode->clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1225 | return MODE_CLOCK_LOW; |
| 1226 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1227 | if (intel_sdvo->pixel_clock_max < mode->clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1228 | return MODE_CLOCK_HIGH; |
| 1229 | |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1230 | if (intel_sdvo->is_lvds) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1231 | if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1232 | return MODE_PANEL; |
| 1233 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1234 | if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1235 | return MODE_PANEL; |
| 1236 | } |
| 1237 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1238 | return MODE_OK; |
| 1239 | } |
| 1240 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1241 | static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1242 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 1243 | if (!intel_sdvo_get_value(intel_sdvo, |
| 1244 | SDVO_CMD_GET_DEVICE_CAPS, |
| 1245 | caps, sizeof(*caps))) |
| 1246 | return false; |
| 1247 | |
| 1248 | DRM_DEBUG_KMS("SDVO capabilities:\n" |
| 1249 | " vendor_id: %d\n" |
| 1250 | " device_id: %d\n" |
| 1251 | " device_rev_id: %d\n" |
| 1252 | " sdvo_version_major: %d\n" |
| 1253 | " sdvo_version_minor: %d\n" |
| 1254 | " sdvo_inputs_mask: %d\n" |
| 1255 | " smooth_scaling: %d\n" |
| 1256 | " sharp_scaling: %d\n" |
| 1257 | " up_scaling: %d\n" |
| 1258 | " down_scaling: %d\n" |
| 1259 | " stall_support: %d\n" |
| 1260 | " output_flags: %d\n", |
| 1261 | caps->vendor_id, |
| 1262 | caps->device_id, |
| 1263 | caps->device_rev_id, |
| 1264 | caps->sdvo_version_major, |
| 1265 | caps->sdvo_version_minor, |
| 1266 | caps->sdvo_inputs_mask, |
| 1267 | caps->smooth_scaling, |
| 1268 | caps->sharp_scaling, |
| 1269 | caps->up_scaling, |
| 1270 | caps->down_scaling, |
| 1271 | caps->stall_support, |
| 1272 | caps->output_flags); |
| 1273 | |
| 1274 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1275 | } |
| 1276 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1277 | /* No use! */ |
| 1278 | #if 0 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1279 | struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB) |
| 1280 | { |
| 1281 | struct drm_connector *connector = NULL; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1282 | struct intel_sdvo *iout = NULL; |
| 1283 | struct intel_sdvo *sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1284 | |
| 1285 | /* find the sdvo connector */ |
| 1286 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1287 | iout = to_intel_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1288 | |
| 1289 | if (iout->type != INTEL_OUTPUT_SDVO) |
| 1290 | continue; |
| 1291 | |
| 1292 | sdvo = iout->dev_priv; |
| 1293 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1294 | if (sdvo->sdvo_reg == SDVOB && sdvoB) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1295 | return connector; |
| 1296 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1297 | if (sdvo->sdvo_reg == SDVOC && !sdvoB) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1298 | return connector; |
| 1299 | |
| 1300 | } |
| 1301 | |
| 1302 | return NULL; |
| 1303 | } |
| 1304 | |
| 1305 | int intel_sdvo_supports_hotplug(struct drm_connector *connector) |
| 1306 | { |
| 1307 | u8 response[2]; |
| 1308 | u8 status; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1309 | struct intel_sdvo *intel_sdvo; |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1310 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1311 | |
| 1312 | if (!connector) |
| 1313 | return 0; |
| 1314 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1315 | intel_sdvo = to_intel_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1316 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1317 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, |
| 1318 | &response, 2) && response[0]; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1319 | } |
| 1320 | |
| 1321 | void intel_sdvo_set_hotplug(struct drm_connector *connector, int on) |
| 1322 | { |
| 1323 | u8 response[2]; |
| 1324 | u8 status; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1325 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1326 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1327 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); |
| 1328 | intel_sdvo_read_response(intel_sdvo, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1329 | |
| 1330 | if (on) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1331 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); |
| 1332 | status = intel_sdvo_read_response(intel_sdvo, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1333 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1334 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1335 | } else { |
| 1336 | response[0] = 0; |
| 1337 | response[1] = 0; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1338 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1339 | } |
| 1340 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1341 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); |
| 1342 | intel_sdvo_read_response(intel_sdvo, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1343 | } |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1344 | #endif |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1345 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1346 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1347 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1348 | { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1349 | int caps = 0; |
| 1350 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1351 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1352 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) |
| 1353 | caps++; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1354 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1355 | (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)) |
| 1356 | caps++; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1357 | if (intel_sdvo->caps.output_flags & |
Roel Kluin | 19e1f88 | 2009-08-09 13:50:53 +0200 | [diff] [blame] | 1358 | (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1)) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1359 | caps++; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1360 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1361 | (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1)) |
| 1362 | caps++; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1363 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1364 | (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1)) |
| 1365 | caps++; |
| 1366 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1367 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1368 | (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1)) |
| 1369 | caps++; |
| 1370 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1371 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1372 | (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)) |
| 1373 | caps++; |
| 1374 | |
| 1375 | return (caps > 1); |
| 1376 | } |
| 1377 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1378 | static struct edid * |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 1379 | intel_sdvo_get_edid(struct drm_connector *connector) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1380 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 1381 | struct intel_sdvo *sdvo = intel_attached_sdvo(connector); |
| 1382 | return drm_get_edid(connector, &sdvo->ddc); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1383 | } |
| 1384 | |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1385 | static struct drm_connector * |
| 1386 | intel_find_analog_connector(struct drm_device *dev) |
| 1387 | { |
| 1388 | struct drm_connector *connector; |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1389 | struct intel_sdvo *encoder; |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1390 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1391 | list_for_each_entry(encoder, |
| 1392 | &dev->mode_config.encoder_list, |
| 1393 | base.base.head) { |
| 1394 | if (encoder->base.type == INTEL_OUTPUT_ANALOG) { |
| 1395 | list_for_each_entry(connector, |
| 1396 | &dev->mode_config.connector_list, |
| 1397 | head) { |
| 1398 | if (&encoder->base == |
| 1399 | intel_attached_encoder(connector)) |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1400 | return connector; |
| 1401 | } |
| 1402 | } |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1403 | } |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1404 | |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1405 | return NULL; |
| 1406 | } |
| 1407 | |
| 1408 | static int |
| 1409 | intel_analog_is_connected(struct drm_device *dev) |
| 1410 | { |
| 1411 | struct drm_connector *analog_connector; |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1412 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1413 | analog_connector = intel_find_analog_connector(dev); |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1414 | if (!analog_connector) |
| 1415 | return false; |
| 1416 | |
Chris Wilson | 930a9e2 | 2010-09-14 11:07:23 +0100 | [diff] [blame] | 1417 | if (analog_connector->funcs->detect(analog_connector, false) == |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1418 | connector_status_disconnected) |
| 1419 | return false; |
| 1420 | |
| 1421 | return true; |
| 1422 | } |
| 1423 | |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1424 | /* Mac mini hack -- use the same DDC as the analog connector */ |
| 1425 | static struct edid * |
| 1426 | intel_sdvo_get_analog_edid(struct drm_connector *connector) |
| 1427 | { |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1428 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1429 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1430 | if (!intel_analog_is_connected(connector->dev)) |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1431 | return NULL; |
| 1432 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1433 | return drm_get_edid(connector, &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter); |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1434 | } |
| 1435 | |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1436 | enum drm_connector_status |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1437 | intel_sdvo_hdmi_sink_detect(struct drm_connector *connector) |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1438 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1439 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1440 | enum drm_connector_status status; |
| 1441 | struct edid *edid; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1442 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 1443 | edid = intel_sdvo_get_edid(connector); |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1444 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1445 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 1446 | u8 ddc, saved_ddc = intel_sdvo->ddc_bus; |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1447 | |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1448 | /* |
| 1449 | * Don't use the 1 as the argument of DDC bus switch to get |
| 1450 | * the EDID. It is used for SDVO SPD ROM. |
| 1451 | */ |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1452 | for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 1453 | intel_sdvo->ddc_bus = ddc; |
| 1454 | edid = intel_sdvo_get_edid(connector); |
| 1455 | if (edid) |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1456 | break; |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1457 | } |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 1458 | /* |
| 1459 | * If we found the EDID on the other bus, |
| 1460 | * assume that is the correct DDC bus. |
| 1461 | */ |
| 1462 | if (edid == NULL) |
| 1463 | intel_sdvo->ddc_bus = saved_ddc; |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1464 | } |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1465 | |
| 1466 | /* |
| 1467 | * When there is no edid and no monitor is connected with VGA |
| 1468 | * port, try to use the CRT ddc to read the EDID for DVI-connector. |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1469 | */ |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1470 | if (edid == NULL) |
| 1471 | edid = intel_sdvo_get_analog_edid(connector); |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1472 | |
Chris Wilson | 2f551c8 | 2010-09-15 10:42:50 +0100 | [diff] [blame] | 1473 | status = connector_status_unknown; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1474 | if (edid != NULL) { |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1475 | /* DDC bus is shared, match EDID to connector type */ |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1476 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
| 1477 | status = connector_status_connected; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1478 | intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid); |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1479 | } |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1480 | connector->display_info.raw_edid = NULL; |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1481 | kfree(edid); |
| 1482 | } |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1483 | |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1484 | return status; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1485 | } |
| 1486 | |
Chris Wilson | 7b334fc | 2010-09-09 23:51:02 +0100 | [diff] [blame] | 1487 | static enum drm_connector_status |
Chris Wilson | 930a9e2 | 2010-09-14 11:07:23 +0100 | [diff] [blame] | 1488 | intel_sdvo_detect(struct drm_connector *connector, bool force) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1489 | { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1490 | uint16_t response; |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1491 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1492 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1493 | enum drm_connector_status ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1494 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1495 | if (!intel_sdvo_write_cmd(intel_sdvo, |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 1496 | SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1497 | return connector_status_unknown; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1498 | if (intel_sdvo->is_tv) { |
Zhao Yakui | d09c23d | 2009-11-06 15:39:56 +0800 | [diff] [blame] | 1499 | /* add 30ms delay when the output type is SDVO-TV */ |
| 1500 | mdelay(30); |
| 1501 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1502 | if (!intel_sdvo_read_response(intel_sdvo, &response, 2)) |
| 1503 | return connector_status_unknown; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1504 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 1505 | DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", |
| 1506 | response & 0xff, response >> 8, |
| 1507 | intel_sdvo_connector->output_flag); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1508 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1509 | if (response == 0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1510 | return connector_status_disconnected; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1511 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1512 | intel_sdvo->attached_output = response; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1513 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1514 | if ((intel_sdvo_connector->output_flag & response) == 0) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1515 | ret = connector_status_disconnected; |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1516 | else if (response & SDVO_TMDS_MASK) |
| 1517 | ret = intel_sdvo_hdmi_sink_detect(connector); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1518 | else |
| 1519 | ret = connector_status_connected; |
| 1520 | |
| 1521 | /* May update encoder flag for like clock for SDVO TV, etc.*/ |
| 1522 | if (ret == connector_status_connected) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1523 | intel_sdvo->is_tv = false; |
| 1524 | intel_sdvo->is_lvds = false; |
| 1525 | intel_sdvo->base.needs_tv_clock = false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1526 | |
| 1527 | if (response & SDVO_TV_MASK) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1528 | intel_sdvo->is_tv = true; |
| 1529 | intel_sdvo->base.needs_tv_clock = true; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1530 | } |
| 1531 | if (response & SDVO_LVDS_MASK) |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1532 | intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1533 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1534 | |
| 1535 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1536 | } |
| 1537 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1538 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1539 | { |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1540 | struct edid *edid; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1541 | |
| 1542 | /* set the bus switch and get the modes */ |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 1543 | edid = intel_sdvo_get_edid(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1544 | |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1545 | /* |
| 1546 | * Mac mini hack. On this device, the DVI-I connector shares one DDC |
| 1547 | * link between analog and digital outputs. So, if the regular SDVO |
| 1548 | * DDC fails, check to see if the analog output is disconnected, in |
| 1549 | * which case we'll look there for the digital DDC data. |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1550 | */ |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1551 | if (edid == NULL) |
| 1552 | edid = intel_sdvo_get_analog_edid(connector); |
| 1553 | |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1554 | if (edid != NULL) { |
| 1555 | drm_mode_connector_update_edid_property(connector, edid); |
| 1556 | drm_add_edid_modes(connector, edid); |
| 1557 | connector->display_info.raw_edid = NULL; |
| 1558 | kfree(edid); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1559 | } |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1560 | } |
| 1561 | |
| 1562 | /* |
| 1563 | * Set of SDVO TV modes. |
| 1564 | * Note! This is in reply order (see loop in get_tv_modes). |
| 1565 | * XXX: all 60Hz refresh? |
| 1566 | */ |
| 1567 | struct drm_display_mode sdvo_tv_modes[] = { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1568 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
| 1569 | 416, 0, 200, 201, 232, 233, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1570 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1571 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
| 1572 | 416, 0, 240, 241, 272, 273, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1573 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1574 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
| 1575 | 496, 0, 300, 301, 332, 333, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1576 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1577 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
| 1578 | 736, 0, 350, 351, 382, 383, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1579 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1580 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
| 1581 | 736, 0, 400, 401, 432, 433, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1582 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1583 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
| 1584 | 736, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1585 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1586 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
| 1587 | 800, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1588 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1589 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
| 1590 | 800, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1591 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1592 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
| 1593 | 816, 0, 350, 351, 382, 383, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1594 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1595 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
| 1596 | 816, 0, 400, 401, 432, 433, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1597 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1598 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
| 1599 | 816, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1600 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1601 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
| 1602 | 816, 0, 540, 541, 572, 573, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1603 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1604 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
| 1605 | 816, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1606 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1607 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
| 1608 | 864, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1609 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1610 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
| 1611 | 896, 0, 600, 601, 632, 633, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1612 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1613 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
| 1614 | 928, 0, 624, 625, 656, 657, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1615 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1616 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
| 1617 | 1016, 0, 766, 767, 798, 799, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1618 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1619 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
| 1620 | 1120, 0, 768, 769, 800, 801, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1621 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1622 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
| 1623 | 1376, 0, 1024, 1025, 1056, 1057, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1624 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
| 1625 | }; |
| 1626 | |
| 1627 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) |
| 1628 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1629 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1630 | struct intel_sdvo_sdtv_resolution_request tv_res; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1631 | uint32_t reply = 0, format_map = 0; |
| 1632 | int i; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1633 | |
| 1634 | /* Read the list of supported input resolutions for the selected TV |
| 1635 | * format. |
| 1636 | */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1637 | format_map = 1 << intel_sdvo->tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1638 | memcpy(&tv_res, &format_map, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1639 | min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1640 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1641 | if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) |
| 1642 | return; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1643 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1644 | BUILD_BUG_ON(sizeof(tv_res) != 3); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 1645 | if (!intel_sdvo_write_cmd(intel_sdvo, |
| 1646 | SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1647 | &tv_res, sizeof(tv_res))) |
| 1648 | return; |
| 1649 | if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1650 | return; |
| 1651 | |
| 1652 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1653 | if (reply & (1 << i)) { |
| 1654 | struct drm_display_mode *nmode; |
| 1655 | nmode = drm_mode_duplicate(connector->dev, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1656 | &sdvo_tv_modes[i]); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1657 | if (nmode) |
| 1658 | drm_mode_probed_add(connector, nmode); |
| 1659 | } |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1660 | } |
| 1661 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1662 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
| 1663 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1664 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1665 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1666 | struct drm_display_mode *newmode; |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1667 | |
| 1668 | /* |
| 1669 | * Attempt to get the mode list from DDC. |
| 1670 | * Assume that the preferred modes are |
| 1671 | * arranged in priority order. |
| 1672 | */ |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1673 | intel_ddc_get_modes(connector, intel_sdvo->i2c); |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1674 | if (list_empty(&connector->probed_modes) == false) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1675 | goto end; |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1676 | |
| 1677 | /* Fetch modes from VBT */ |
| 1678 | if (dev_priv->sdvo_lvds_vbt_mode != NULL) { |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1679 | newmode = drm_mode_duplicate(connector->dev, |
| 1680 | dev_priv->sdvo_lvds_vbt_mode); |
| 1681 | if (newmode != NULL) { |
| 1682 | /* Guarantee the mode is preferred */ |
| 1683 | newmode->type = (DRM_MODE_TYPE_PREFERRED | |
| 1684 | DRM_MODE_TYPE_DRIVER); |
| 1685 | drm_mode_probed_add(connector, newmode); |
| 1686 | } |
| 1687 | } |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1688 | |
| 1689 | end: |
| 1690 | list_for_each_entry(newmode, &connector->probed_modes, head) { |
| 1691 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1692 | intel_sdvo->sdvo_lvds_fixed_mode = |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1693 | drm_mode_duplicate(connector->dev, newmode); |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1694 | |
| 1695 | drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, |
| 1696 | 0); |
| 1697 | |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1698 | intel_sdvo->is_lvds = true; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1699 | break; |
| 1700 | } |
| 1701 | } |
| 1702 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1703 | } |
| 1704 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1705 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
| 1706 | { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1707 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1708 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1709 | if (IS_TV(intel_sdvo_connector)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1710 | intel_sdvo_get_tv_modes(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1711 | else if (IS_LVDS(intel_sdvo_connector)) |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1712 | intel_sdvo_get_lvds_modes(connector); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1713 | else |
| 1714 | intel_sdvo_get_ddc_modes(connector); |
| 1715 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1716 | return !list_empty(&connector->probed_modes); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1717 | } |
| 1718 | |
Chris Wilson | fcc8d67 | 2010-08-04 13:50:27 +0100 | [diff] [blame] | 1719 | static void |
| 1720 | intel_sdvo_destroy_enhance_property(struct drm_connector *connector) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1721 | { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1722 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1723 | struct drm_device *dev = connector->dev; |
| 1724 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1725 | if (intel_sdvo_connector->left) |
| 1726 | drm_property_destroy(dev, intel_sdvo_connector->left); |
| 1727 | if (intel_sdvo_connector->right) |
| 1728 | drm_property_destroy(dev, intel_sdvo_connector->right); |
| 1729 | if (intel_sdvo_connector->top) |
| 1730 | drm_property_destroy(dev, intel_sdvo_connector->top); |
| 1731 | if (intel_sdvo_connector->bottom) |
| 1732 | drm_property_destroy(dev, intel_sdvo_connector->bottom); |
| 1733 | if (intel_sdvo_connector->hpos) |
| 1734 | drm_property_destroy(dev, intel_sdvo_connector->hpos); |
| 1735 | if (intel_sdvo_connector->vpos) |
| 1736 | drm_property_destroy(dev, intel_sdvo_connector->vpos); |
| 1737 | if (intel_sdvo_connector->saturation) |
| 1738 | drm_property_destroy(dev, intel_sdvo_connector->saturation); |
| 1739 | if (intel_sdvo_connector->contrast) |
| 1740 | drm_property_destroy(dev, intel_sdvo_connector->contrast); |
| 1741 | if (intel_sdvo_connector->hue) |
| 1742 | drm_property_destroy(dev, intel_sdvo_connector->hue); |
| 1743 | if (intel_sdvo_connector->sharpness) |
| 1744 | drm_property_destroy(dev, intel_sdvo_connector->sharpness); |
| 1745 | if (intel_sdvo_connector->flicker_filter) |
| 1746 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter); |
| 1747 | if (intel_sdvo_connector->flicker_filter_2d) |
| 1748 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d); |
| 1749 | if (intel_sdvo_connector->flicker_filter_adaptive) |
| 1750 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive); |
| 1751 | if (intel_sdvo_connector->tv_luma_filter) |
| 1752 | drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter); |
| 1753 | if (intel_sdvo_connector->tv_chroma_filter) |
| 1754 | drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter); |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 1755 | if (intel_sdvo_connector->dot_crawl) |
| 1756 | drm_property_destroy(dev, intel_sdvo_connector->dot_crawl); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1757 | if (intel_sdvo_connector->brightness) |
| 1758 | drm_property_destroy(dev, intel_sdvo_connector->brightness); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1759 | } |
| 1760 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1761 | static void intel_sdvo_destroy(struct drm_connector *connector) |
| 1762 | { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1763 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1764 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1765 | if (intel_sdvo_connector->tv_format) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1766 | drm_property_destroy(connector->dev, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1767 | intel_sdvo_connector->tv_format); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1768 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1769 | intel_sdvo_destroy_enhance_property(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1770 | drm_sysfs_connector_remove(connector); |
| 1771 | drm_connector_cleanup(connector); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1772 | kfree(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1773 | } |
| 1774 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1775 | static int |
| 1776 | intel_sdvo_set_property(struct drm_connector *connector, |
| 1777 | struct drm_property *property, |
| 1778 | uint64_t val) |
| 1779 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1780 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1781 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1782 | uint16_t temp_value; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1783 | uint8_t cmd; |
| 1784 | int ret; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1785 | |
| 1786 | ret = drm_connector_property_set_value(connector, property, val); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1787 | if (ret) |
| 1788 | return ret; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1789 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1790 | #define CHECK_PROPERTY(name, NAME) \ |
| 1791 | if (intel_sdvo_connector->name == property) { \ |
| 1792 | if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ |
| 1793 | if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ |
| 1794 | cmd = SDVO_CMD_SET_##NAME; \ |
| 1795 | intel_sdvo_connector->cur_##name = temp_value; \ |
| 1796 | goto set_value; \ |
| 1797 | } |
| 1798 | |
| 1799 | if (property == intel_sdvo_connector->tv_format) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1800 | if (val >= TV_FORMAT_NUM) |
| 1801 | return -EINVAL; |
| 1802 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1803 | if (intel_sdvo->tv_format_index == |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1804 | intel_sdvo_connector->tv_format_supported[val]) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1805 | return 0; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1806 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1807 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1808 | goto done; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1809 | } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1810 | temp_value = val; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1811 | if (intel_sdvo_connector->left == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1812 | drm_connector_property_set_value(connector, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1813 | intel_sdvo_connector->right, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1814 | if (intel_sdvo_connector->left_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1815 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1816 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1817 | intel_sdvo_connector->left_margin = temp_value; |
| 1818 | intel_sdvo_connector->right_margin = temp_value; |
| 1819 | temp_value = intel_sdvo_connector->max_hscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1820 | intel_sdvo_connector->left_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1821 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1822 | goto set_value; |
| 1823 | } else if (intel_sdvo_connector->right == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1824 | drm_connector_property_set_value(connector, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1825 | intel_sdvo_connector->left, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1826 | if (intel_sdvo_connector->right_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1827 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1828 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1829 | intel_sdvo_connector->left_margin = temp_value; |
| 1830 | intel_sdvo_connector->right_margin = temp_value; |
| 1831 | temp_value = intel_sdvo_connector->max_hscan - |
| 1832 | intel_sdvo_connector->left_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1833 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1834 | goto set_value; |
| 1835 | } else if (intel_sdvo_connector->top == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1836 | drm_connector_property_set_value(connector, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1837 | intel_sdvo_connector->bottom, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1838 | if (intel_sdvo_connector->top_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1839 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1840 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1841 | intel_sdvo_connector->top_margin = temp_value; |
| 1842 | intel_sdvo_connector->bottom_margin = temp_value; |
| 1843 | temp_value = intel_sdvo_connector->max_vscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1844 | intel_sdvo_connector->top_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1845 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1846 | goto set_value; |
| 1847 | } else if (intel_sdvo_connector->bottom == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1848 | drm_connector_property_set_value(connector, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1849 | intel_sdvo_connector->top, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1850 | if (intel_sdvo_connector->bottom_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1851 | return 0; |
| 1852 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1853 | intel_sdvo_connector->top_margin = temp_value; |
| 1854 | intel_sdvo_connector->bottom_margin = temp_value; |
| 1855 | temp_value = intel_sdvo_connector->max_vscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1856 | intel_sdvo_connector->top_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1857 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1858 | goto set_value; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1859 | } |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1860 | CHECK_PROPERTY(hpos, HPOS) |
| 1861 | CHECK_PROPERTY(vpos, VPOS) |
| 1862 | CHECK_PROPERTY(saturation, SATURATION) |
| 1863 | CHECK_PROPERTY(contrast, CONTRAST) |
| 1864 | CHECK_PROPERTY(hue, HUE) |
| 1865 | CHECK_PROPERTY(brightness, BRIGHTNESS) |
| 1866 | CHECK_PROPERTY(sharpness, SHARPNESS) |
| 1867 | CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) |
| 1868 | CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) |
| 1869 | CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) |
| 1870 | CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) |
| 1871 | CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 1872 | CHECK_PROPERTY(dot_crawl, DOT_CRAWL) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1873 | } |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1874 | |
| 1875 | return -EINVAL; /* unknown property */ |
| 1876 | |
| 1877 | set_value: |
| 1878 | if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) |
| 1879 | return -EIO; |
| 1880 | |
| 1881 | |
| 1882 | done: |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1883 | if (intel_sdvo->base.base.crtc) { |
| 1884 | struct drm_crtc *crtc = intel_sdvo->base.base.crtc; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1885 | drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1886 | crtc->y, crtc->fb); |
| 1887 | } |
| 1888 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1889 | return 0; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1890 | #undef CHECK_PROPERTY |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1891 | } |
| 1892 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1893 | static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { |
| 1894 | .dpms = intel_sdvo_dpms, |
| 1895 | .mode_fixup = intel_sdvo_mode_fixup, |
| 1896 | .prepare = intel_encoder_prepare, |
| 1897 | .mode_set = intel_sdvo_mode_set, |
| 1898 | .commit = intel_encoder_commit, |
| 1899 | }; |
| 1900 | |
| 1901 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { |
Keith Packard | c9fb15f | 2009-05-30 20:42:28 -0700 | [diff] [blame] | 1902 | .dpms = drm_helper_connector_dpms, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1903 | .detect = intel_sdvo_detect, |
| 1904 | .fill_modes = drm_helper_probe_single_connector_modes, |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1905 | .set_property = intel_sdvo_set_property, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1906 | .destroy = intel_sdvo_destroy, |
| 1907 | }; |
| 1908 | |
| 1909 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { |
| 1910 | .get_modes = intel_sdvo_get_modes, |
| 1911 | .mode_valid = intel_sdvo_mode_valid, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1912 | .best_encoder = intel_best_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1913 | }; |
| 1914 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 1915 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1916 | { |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 1917 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1918 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1919 | if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1920 | drm_mode_destroy(encoder->dev, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1921 | intel_sdvo->sdvo_lvds_fixed_mode); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1922 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 1923 | i2c_del_adapter(&intel_sdvo->ddc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1924 | intel_encoder_destroy(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1925 | } |
| 1926 | |
| 1927 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { |
| 1928 | .destroy = intel_sdvo_enc_destroy, |
| 1929 | }; |
| 1930 | |
Chris Wilson | b66d842 | 2010-08-12 15:26:41 +0100 | [diff] [blame] | 1931 | static void |
| 1932 | intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) |
| 1933 | { |
| 1934 | uint16_t mask = 0; |
| 1935 | unsigned int num_bits; |
| 1936 | |
| 1937 | /* Make a mask of outputs less than or equal to our own priority in the |
| 1938 | * list. |
| 1939 | */ |
| 1940 | switch (sdvo->controlled_output) { |
| 1941 | case SDVO_OUTPUT_LVDS1: |
| 1942 | mask |= SDVO_OUTPUT_LVDS1; |
| 1943 | case SDVO_OUTPUT_LVDS0: |
| 1944 | mask |= SDVO_OUTPUT_LVDS0; |
| 1945 | case SDVO_OUTPUT_TMDS1: |
| 1946 | mask |= SDVO_OUTPUT_TMDS1; |
| 1947 | case SDVO_OUTPUT_TMDS0: |
| 1948 | mask |= SDVO_OUTPUT_TMDS0; |
| 1949 | case SDVO_OUTPUT_RGB1: |
| 1950 | mask |= SDVO_OUTPUT_RGB1; |
| 1951 | case SDVO_OUTPUT_RGB0: |
| 1952 | mask |= SDVO_OUTPUT_RGB0; |
| 1953 | break; |
| 1954 | } |
| 1955 | |
| 1956 | /* Count bits to find what number we are in the priority list. */ |
| 1957 | mask &= sdvo->caps.output_flags; |
| 1958 | num_bits = hweight16(mask); |
| 1959 | /* If more than 3 outputs, default to DDC bus 3 for now. */ |
| 1960 | if (num_bits > 3) |
| 1961 | num_bits = 3; |
| 1962 | |
| 1963 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ |
| 1964 | sdvo->ddc_bus = 1 << num_bits; |
| 1965 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1966 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1967 | /** |
| 1968 | * Choose the appropriate DDC bus for control bus switch command for this |
| 1969 | * SDVO output based on the controlled output. |
| 1970 | * |
| 1971 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS |
| 1972 | * outputs, then LVDS outputs. |
| 1973 | */ |
| 1974 | static void |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 1975 | intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1976 | struct intel_sdvo *sdvo, u32 reg) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1977 | { |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 1978 | struct sdvo_device_mapping *mapping; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1979 | |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 1980 | if (IS_SDVOB(reg)) |
| 1981 | mapping = &(dev_priv->sdvo_mappings[0]); |
| 1982 | else |
| 1983 | mapping = &(dev_priv->sdvo_mappings[1]); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1984 | |
Chris Wilson | b66d842 | 2010-08-12 15:26:41 +0100 | [diff] [blame] | 1985 | if (mapping->initialized) |
| 1986 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); |
| 1987 | else |
| 1988 | intel_sdvo_guess_ddc_bus(sdvo); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1989 | } |
| 1990 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 1991 | static void |
| 1992 | intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, |
| 1993 | struct intel_sdvo *sdvo, u32 reg) |
| 1994 | { |
| 1995 | struct sdvo_device_mapping *mapping; |
| 1996 | u8 pin, speed; |
| 1997 | |
| 1998 | if (IS_SDVOB(reg)) |
| 1999 | mapping = &dev_priv->sdvo_mappings[0]; |
| 2000 | else |
| 2001 | mapping = &dev_priv->sdvo_mappings[1]; |
| 2002 | |
| 2003 | pin = GMBUS_PORT_DPB; |
| 2004 | speed = GMBUS_RATE_1MHZ >> 8; |
| 2005 | if (mapping->initialized) { |
| 2006 | pin = mapping->i2c_pin; |
| 2007 | speed = mapping->i2c_speed; |
| 2008 | } |
| 2009 | |
| 2010 | sdvo->i2c = &dev_priv->gmbus[pin].adapter; |
| 2011 | intel_gmbus_set_speed(sdvo->i2c, speed); |
| 2012 | intel_gmbus_force_bit(sdvo->i2c, true); |
| 2013 | } |
| 2014 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2015 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2016 | intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2017 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2018 | return intel_sdvo_set_target_output(intel_sdvo, |
| 2019 | device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1) && |
| 2020 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, |
| 2021 | &intel_sdvo->is_hdmi, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2022 | } |
| 2023 | |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2024 | static u8 |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2025 | intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg) |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2026 | { |
| 2027 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2028 | struct sdvo_device_mapping *my_mapping, *other_mapping; |
| 2029 | |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2030 | if (IS_SDVOB(sdvo_reg)) { |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2031 | my_mapping = &dev_priv->sdvo_mappings[0]; |
| 2032 | other_mapping = &dev_priv->sdvo_mappings[1]; |
| 2033 | } else { |
| 2034 | my_mapping = &dev_priv->sdvo_mappings[1]; |
| 2035 | other_mapping = &dev_priv->sdvo_mappings[0]; |
| 2036 | } |
| 2037 | |
| 2038 | /* If the BIOS described our SDVO device, take advantage of it. */ |
| 2039 | if (my_mapping->slave_addr) |
| 2040 | return my_mapping->slave_addr; |
| 2041 | |
| 2042 | /* If the BIOS only described a different SDVO device, use the |
| 2043 | * address that it isn't using. |
| 2044 | */ |
| 2045 | if (other_mapping->slave_addr) { |
| 2046 | if (other_mapping->slave_addr == 0x70) |
| 2047 | return 0x72; |
| 2048 | else |
| 2049 | return 0x70; |
| 2050 | } |
| 2051 | |
| 2052 | /* No SDVO device info is found for another DVO port, |
| 2053 | * so use mapping assumption we had before BIOS parsing. |
| 2054 | */ |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2055 | if (IS_SDVOB(sdvo_reg)) |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2056 | return 0x70; |
| 2057 | else |
| 2058 | return 0x72; |
| 2059 | } |
| 2060 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2061 | static void |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2062 | intel_sdvo_connector_init(struct intel_sdvo_connector *connector, |
| 2063 | struct intel_sdvo *encoder) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2064 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2065 | drm_connector_init(encoder->base.base.dev, |
| 2066 | &connector->base.base, |
| 2067 | &intel_sdvo_connector_funcs, |
| 2068 | connector->base.base.connector_type); |
Zhao Yakui | 6070a4a | 2010-02-08 21:35:12 +0800 | [diff] [blame] | 2069 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2070 | drm_connector_helper_add(&connector->base.base, |
| 2071 | &intel_sdvo_connector_helper_funcs); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2072 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2073 | connector->base.base.interlace_allowed = 0; |
| 2074 | connector->base.base.doublescan_allowed = 0; |
| 2075 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2076 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2077 | intel_connector_attach_encoder(&connector->base, &encoder->base); |
| 2078 | drm_sysfs_connector_add(&connector->base.base); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2079 | } |
| 2080 | |
| 2081 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2082 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2083 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2084 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2085 | struct drm_connector *connector; |
| 2086 | struct intel_connector *intel_connector; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2087 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2088 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2089 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2090 | if (!intel_sdvo_connector) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2091 | return false; |
| 2092 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2093 | if (device == 0) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2094 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2095 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2096 | } else if (device == 1) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2097 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2098 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2099 | } |
| 2100 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2101 | intel_connector = &intel_sdvo_connector->base; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2102 | connector = &intel_connector->base; |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 2103 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2104 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; |
| 2105 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; |
| 2106 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2107 | if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode) |
| 2108 | && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device) |
| 2109 | && intel_sdvo->is_hdmi) { |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2110 | /* enable hdmi encoding mode if supported */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2111 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); |
| 2112 | intel_sdvo_set_colorimetry(intel_sdvo, |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2113 | SDVO_COLORIMETRY_RGB256); |
| 2114 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
| 2115 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2116 | intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
| 2117 | (1 << INTEL_ANALOG_CLONE_BIT)); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2118 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2119 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2120 | |
| 2121 | return true; |
| 2122 | } |
| 2123 | |
| 2124 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2125 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2126 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2127 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2128 | struct drm_connector *connector; |
| 2129 | struct intel_connector *intel_connector; |
| 2130 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2131 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2132 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2133 | if (!intel_sdvo_connector) |
| 2134 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2135 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2136 | intel_connector = &intel_sdvo_connector->base; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2137 | connector = &intel_connector->base; |
| 2138 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; |
| 2139 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2140 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2141 | intel_sdvo->controlled_output |= type; |
| 2142 | intel_sdvo_connector->output_flag = type; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2143 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2144 | intel_sdvo->is_tv = true; |
| 2145 | intel_sdvo->base.needs_tv_clock = true; |
| 2146 | intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2147 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2148 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2149 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2150 | if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2151 | goto err; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2152 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2153 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2154 | goto err; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2155 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2156 | return true; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2157 | |
| 2158 | err: |
Chris Wilson | fcc8d67 | 2010-08-04 13:50:27 +0100 | [diff] [blame] | 2159 | intel_sdvo_destroy_enhance_property(connector); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2160 | kfree(intel_sdvo_connector); |
| 2161 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2162 | } |
| 2163 | |
| 2164 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2165 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2166 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2167 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2168 | struct drm_connector *connector; |
| 2169 | struct intel_connector *intel_connector; |
| 2170 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2171 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2172 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2173 | if (!intel_sdvo_connector) |
| 2174 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2175 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2176 | intel_connector = &intel_sdvo_connector->base; |
| 2177 | connector = &intel_connector->base; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2178 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
| 2179 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; |
| 2180 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2181 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2182 | if (device == 0) { |
| 2183 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; |
| 2184 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; |
| 2185 | } else if (device == 1) { |
| 2186 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; |
| 2187 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; |
| 2188 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2189 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2190 | intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
| 2191 | (1 << INTEL_ANALOG_CLONE_BIT)); |
| 2192 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2193 | intel_sdvo_connector_init(intel_sdvo_connector, |
| 2194 | intel_sdvo); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2195 | return true; |
| 2196 | } |
| 2197 | |
| 2198 | static bool |
| 2199 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) |
| 2200 | { |
| 2201 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2202 | struct drm_connector *connector; |
| 2203 | struct intel_connector *intel_connector; |
| 2204 | struct intel_sdvo_connector *intel_sdvo_connector; |
| 2205 | |
| 2206 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2207 | if (!intel_sdvo_connector) |
| 2208 | return false; |
| 2209 | |
| 2210 | intel_connector = &intel_sdvo_connector->base; |
| 2211 | connector = &intel_connector->base; |
| 2212 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; |
| 2213 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; |
| 2214 | |
| 2215 | if (device == 0) { |
| 2216 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; |
| 2217 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; |
| 2218 | } else if (device == 1) { |
| 2219 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; |
| 2220 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; |
| 2221 | } |
| 2222 | |
| 2223 | intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2224 | (1 << INTEL_SDVO_LVDS_CLONE_BIT)); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2225 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2226 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2227 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2228 | goto err; |
| 2229 | |
| 2230 | return true; |
| 2231 | |
| 2232 | err: |
Chris Wilson | fcc8d67 | 2010-08-04 13:50:27 +0100 | [diff] [blame] | 2233 | intel_sdvo_destroy_enhance_property(connector); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2234 | kfree(intel_sdvo_connector); |
| 2235 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2236 | } |
Zhao Yakui | 6070a4a | 2010-02-08 21:35:12 +0800 | [diff] [blame] | 2237 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2238 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2239 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2240 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2241 | intel_sdvo->is_tv = false; |
| 2242 | intel_sdvo->base.needs_tv_clock = false; |
| 2243 | intel_sdvo->is_lvds = false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2244 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2245 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2246 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2247 | if (flags & SDVO_OUTPUT_TMDS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2248 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2249 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2250 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2251 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2252 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2253 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2254 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2255 | /* TV has no XXX1 function block */ |
Zhenyu Wang | a1f4b7ff | 2010-03-29 23:16:13 +0800 | [diff] [blame] | 2256 | if (flags & SDVO_OUTPUT_SVID0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2257 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2258 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2259 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2260 | if (flags & SDVO_OUTPUT_CVBS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2261 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2262 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2263 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2264 | if (flags & SDVO_OUTPUT_RGB0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2265 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2266 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2267 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2268 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2269 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2270 | return false; |
Zhao Yakui | 2dd8738 | 2010-01-27 16:32:46 +0800 | [diff] [blame] | 2271 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2272 | if (flags & SDVO_OUTPUT_LVDS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2273 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2274 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2275 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2276 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2277 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2278 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2279 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2280 | if ((flags & SDVO_OUTPUT_MASK) == 0) { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2281 | unsigned char bytes[2]; |
| 2282 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2283 | intel_sdvo->controlled_output = 0; |
| 2284 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2); |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2285 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2286 | SDVO_NAME(intel_sdvo), |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2287 | bytes[0], bytes[1]); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2288 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2289 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2290 | intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1); |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2291 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2292 | return true; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2293 | } |
| 2294 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2295 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
| 2296 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2297 | int type) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2298 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2299 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2300 | struct intel_sdvo_tv_format format; |
| 2301 | uint32_t format_map, i; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2302 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2303 | if (!intel_sdvo_set_target_output(intel_sdvo, type)) |
| 2304 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2305 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2306 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2307 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, |
| 2308 | &format, sizeof(format))) |
| 2309 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2310 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2311 | memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2312 | |
| 2313 | if (format_map == 0) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2314 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2315 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2316 | intel_sdvo_connector->format_supported_num = 0; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2317 | for (i = 0 ; i < TV_FORMAT_NUM; i++) |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2318 | if (format_map & (1 << i)) |
| 2319 | intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2320 | |
| 2321 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2322 | intel_sdvo_connector->tv_format = |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2323 | drm_property_create(dev, DRM_MODE_PROP_ENUM, |
| 2324 | "mode", intel_sdvo_connector->format_supported_num); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2325 | if (!intel_sdvo_connector->tv_format) |
Chris Wilson | fcc8d67 | 2010-08-04 13:50:27 +0100 | [diff] [blame] | 2326 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2327 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2328 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2329 | drm_property_add_enum( |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2330 | intel_sdvo_connector->tv_format, i, |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2331 | i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2332 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2333 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2334 | drm_connector_attach_property(&intel_sdvo_connector->base.base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2335 | intel_sdvo_connector->tv_format, 0); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2336 | return true; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2337 | |
| 2338 | } |
| 2339 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2340 | #define ENHANCEMENT(name, NAME) do { \ |
| 2341 | if (enhancements.name) { \ |
| 2342 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ |
| 2343 | !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ |
| 2344 | return false; \ |
| 2345 | intel_sdvo_connector->max_##name = data_value[0]; \ |
| 2346 | intel_sdvo_connector->cur_##name = response; \ |
| 2347 | intel_sdvo_connector->name = \ |
| 2348 | drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \ |
| 2349 | if (!intel_sdvo_connector->name) return false; \ |
| 2350 | intel_sdvo_connector->name->values[0] = 0; \ |
| 2351 | intel_sdvo_connector->name->values[1] = data_value[0]; \ |
| 2352 | drm_connector_attach_property(connector, \ |
| 2353 | intel_sdvo_connector->name, \ |
| 2354 | intel_sdvo_connector->cur_##name); \ |
| 2355 | DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ |
| 2356 | data_value[0], data_value[1], response); \ |
| 2357 | } \ |
| 2358 | } while(0) |
| 2359 | |
| 2360 | static bool |
| 2361 | intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, |
| 2362 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2363 | struct intel_sdvo_enhancements_reply enhancements) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2364 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2365 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2366 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2367 | uint16_t response, data_value[2]; |
| 2368 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2369 | /* when horizontal overscan is supported, Add the left/right property */ |
| 2370 | if (enhancements.overscan_h) { |
| 2371 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2372 | SDVO_CMD_GET_MAX_OVERSCAN_H, |
| 2373 | &data_value, 4)) |
| 2374 | return false; |
| 2375 | |
| 2376 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2377 | SDVO_CMD_GET_OVERSCAN_H, |
| 2378 | &response, 2)) |
| 2379 | return false; |
| 2380 | |
| 2381 | intel_sdvo_connector->max_hscan = data_value[0]; |
| 2382 | intel_sdvo_connector->left_margin = data_value[0] - response; |
| 2383 | intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; |
| 2384 | intel_sdvo_connector->left = |
| 2385 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2386 | "left_margin", 2); |
| 2387 | if (!intel_sdvo_connector->left) |
| 2388 | return false; |
| 2389 | |
| 2390 | intel_sdvo_connector->left->values[0] = 0; |
| 2391 | intel_sdvo_connector->left->values[1] = data_value[0]; |
| 2392 | drm_connector_attach_property(connector, |
| 2393 | intel_sdvo_connector->left, |
| 2394 | intel_sdvo_connector->left_margin); |
| 2395 | |
| 2396 | intel_sdvo_connector->right = |
| 2397 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2398 | "right_margin", 2); |
| 2399 | if (!intel_sdvo_connector->right) |
| 2400 | return false; |
| 2401 | |
| 2402 | intel_sdvo_connector->right->values[0] = 0; |
| 2403 | intel_sdvo_connector->right->values[1] = data_value[0]; |
| 2404 | drm_connector_attach_property(connector, |
| 2405 | intel_sdvo_connector->right, |
| 2406 | intel_sdvo_connector->right_margin); |
| 2407 | DRM_DEBUG_KMS("h_overscan: max %d, " |
| 2408 | "default %d, current %d\n", |
| 2409 | data_value[0], data_value[1], response); |
| 2410 | } |
| 2411 | |
| 2412 | if (enhancements.overscan_v) { |
| 2413 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2414 | SDVO_CMD_GET_MAX_OVERSCAN_V, |
| 2415 | &data_value, 4)) |
| 2416 | return false; |
| 2417 | |
| 2418 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2419 | SDVO_CMD_GET_OVERSCAN_V, |
| 2420 | &response, 2)) |
| 2421 | return false; |
| 2422 | |
| 2423 | intel_sdvo_connector->max_vscan = data_value[0]; |
| 2424 | intel_sdvo_connector->top_margin = data_value[0] - response; |
| 2425 | intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; |
| 2426 | intel_sdvo_connector->top = |
| 2427 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2428 | "top_margin", 2); |
| 2429 | if (!intel_sdvo_connector->top) |
| 2430 | return false; |
| 2431 | |
| 2432 | intel_sdvo_connector->top->values[0] = 0; |
| 2433 | intel_sdvo_connector->top->values[1] = data_value[0]; |
| 2434 | drm_connector_attach_property(connector, |
| 2435 | intel_sdvo_connector->top, |
| 2436 | intel_sdvo_connector->top_margin); |
| 2437 | |
| 2438 | intel_sdvo_connector->bottom = |
| 2439 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2440 | "bottom_margin", 2); |
| 2441 | if (!intel_sdvo_connector->bottom) |
| 2442 | return false; |
| 2443 | |
| 2444 | intel_sdvo_connector->bottom->values[0] = 0; |
| 2445 | intel_sdvo_connector->bottom->values[1] = data_value[0]; |
| 2446 | drm_connector_attach_property(connector, |
| 2447 | intel_sdvo_connector->bottom, |
| 2448 | intel_sdvo_connector->bottom_margin); |
| 2449 | DRM_DEBUG_KMS("v_overscan: max %d, " |
| 2450 | "default %d, current %d\n", |
| 2451 | data_value[0], data_value[1], response); |
| 2452 | } |
| 2453 | |
| 2454 | ENHANCEMENT(hpos, HPOS); |
| 2455 | ENHANCEMENT(vpos, VPOS); |
| 2456 | ENHANCEMENT(saturation, SATURATION); |
| 2457 | ENHANCEMENT(contrast, CONTRAST); |
| 2458 | ENHANCEMENT(hue, HUE); |
| 2459 | ENHANCEMENT(sharpness, SHARPNESS); |
| 2460 | ENHANCEMENT(brightness, BRIGHTNESS); |
| 2461 | ENHANCEMENT(flicker_filter, FLICKER_FILTER); |
| 2462 | ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); |
| 2463 | ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); |
| 2464 | ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); |
| 2465 | ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); |
| 2466 | |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 2467 | if (enhancements.dot_crawl) { |
| 2468 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) |
| 2469 | return false; |
| 2470 | |
| 2471 | intel_sdvo_connector->max_dot_crawl = 1; |
| 2472 | intel_sdvo_connector->cur_dot_crawl = response & 0x1; |
| 2473 | intel_sdvo_connector->dot_crawl = |
| 2474 | drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2); |
| 2475 | if (!intel_sdvo_connector->dot_crawl) |
| 2476 | return false; |
| 2477 | |
| 2478 | intel_sdvo_connector->dot_crawl->values[0] = 0; |
| 2479 | intel_sdvo_connector->dot_crawl->values[1] = 1; |
| 2480 | drm_connector_attach_property(connector, |
| 2481 | intel_sdvo_connector->dot_crawl, |
| 2482 | intel_sdvo_connector->cur_dot_crawl); |
| 2483 | DRM_DEBUG_KMS("dot crawl: current %d\n", response); |
| 2484 | } |
| 2485 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2486 | return true; |
| 2487 | } |
| 2488 | |
| 2489 | static bool |
| 2490 | intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, |
| 2491 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2492 | struct intel_sdvo_enhancements_reply enhancements) |
| 2493 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2494 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2495 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
| 2496 | uint16_t response, data_value[2]; |
| 2497 | |
| 2498 | ENHANCEMENT(brightness, BRIGHTNESS); |
| 2499 | |
| 2500 | return true; |
| 2501 | } |
| 2502 | #undef ENHANCEMENT |
| 2503 | |
| 2504 | static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
| 2505 | struct intel_sdvo_connector *intel_sdvo_connector) |
| 2506 | { |
| 2507 | union { |
| 2508 | struct intel_sdvo_enhancements_reply reply; |
| 2509 | uint16_t response; |
| 2510 | } enhancements; |
| 2511 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2512 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2513 | SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2514 | &enhancements, sizeof(enhancements))) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2515 | return false; |
| 2516 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2517 | if (enhancements.response == 0) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2518 | DRM_DEBUG_KMS("No enhancement is supported\n"); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2519 | return true; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2520 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2521 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2522 | if (IS_TV(intel_sdvo_connector)) |
| 2523 | return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
| 2524 | else if(IS_LVDS(intel_sdvo_connector)) |
| 2525 | return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
| 2526 | else |
| 2527 | return true; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 2528 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2529 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 2530 | static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, |
| 2531 | struct i2c_msg *msgs, |
| 2532 | int num) |
| 2533 | { |
| 2534 | struct intel_sdvo *sdvo = adapter->algo_data; |
| 2535 | |
| 2536 | if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) |
| 2537 | return -EIO; |
| 2538 | |
| 2539 | return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); |
| 2540 | } |
| 2541 | |
| 2542 | static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) |
| 2543 | { |
| 2544 | struct intel_sdvo *sdvo = adapter->algo_data; |
| 2545 | return sdvo->i2c->algo->functionality(sdvo->i2c); |
| 2546 | } |
| 2547 | |
| 2548 | static const struct i2c_algorithm intel_sdvo_ddc_proxy = { |
| 2549 | .master_xfer = intel_sdvo_ddc_proxy_xfer, |
| 2550 | .functionality = intel_sdvo_ddc_proxy_func |
| 2551 | }; |
| 2552 | |
| 2553 | static bool |
| 2554 | intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, |
| 2555 | struct drm_device *dev) |
| 2556 | { |
| 2557 | sdvo->ddc.owner = THIS_MODULE; |
| 2558 | sdvo->ddc.class = I2C_CLASS_DDC; |
| 2559 | snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); |
| 2560 | sdvo->ddc.dev.parent = &dev->pdev->dev; |
| 2561 | sdvo->ddc.algo_data = sdvo; |
| 2562 | sdvo->ddc.algo = &intel_sdvo_ddc_proxy; |
| 2563 | |
| 2564 | return i2c_add_adapter(&sdvo->ddc) == 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2565 | } |
| 2566 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2567 | bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2568 | { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2569 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2570 | struct intel_encoder *intel_encoder; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2571 | struct intel_sdvo *intel_sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2572 | int i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2573 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2574 | intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL); |
| 2575 | if (!intel_sdvo) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2576 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2577 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 2578 | if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) { |
| 2579 | kfree(intel_sdvo); |
| 2580 | return false; |
| 2581 | } |
| 2582 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2583 | intel_sdvo->sdvo_reg = sdvo_reg; |
Keith Packard | 308cd3a | 2009-06-14 11:56:18 -0700 | [diff] [blame] | 2584 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2585 | intel_encoder = &intel_sdvo->base; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2586 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
Chris Wilson | 373a3cf | 2010-09-15 12:03:59 +0100 | [diff] [blame] | 2587 | /* encoder type will be decided later */ |
| 2588 | drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2589 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 2590 | intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1; |
| 2591 | intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2592 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2593 | /* Read the regs to test if we can talk to the device */ |
| 2594 | for (i = 0; i < 0x40; i++) { |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2595 | u8 byte; |
| 2596 | |
| 2597 | if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 2598 | DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2599 | IS_SDVOB(sdvo_reg) ? 'B' : 'C'); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2600 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2601 | } |
| 2602 | } |
| 2603 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2604 | if (IS_SDVOB(sdvo_reg)) |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2605 | dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS; |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2606 | else |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2607 | dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2608 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2609 | drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2610 | |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 2611 | /* In default case sdvo lvds is false */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2612 | if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2613 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2614 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2615 | if (intel_sdvo_output_setup(intel_sdvo, |
| 2616 | intel_sdvo->caps.output_flags) != true) { |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2617 | DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2618 | IS_SDVOB(sdvo_reg) ? 'B' : 'C'); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2619 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2620 | } |
| 2621 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2622 | intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2623 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2624 | /* Set the input timing to the screen. Assume always input 0. */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2625 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2626 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2627 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2628 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
| 2629 | &intel_sdvo->pixel_clock_min, |
| 2630 | &intel_sdvo->pixel_clock_max)) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2631 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2632 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 2633 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 2634 | "clock range %dMHz - %dMHz, " |
| 2635 | "input 1: %c, input 2: %c, " |
| 2636 | "output 1: %c, output 2: %c\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2637 | SDVO_NAME(intel_sdvo), |
| 2638 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, |
| 2639 | intel_sdvo->caps.device_rev_id, |
| 2640 | intel_sdvo->pixel_clock_min / 1000, |
| 2641 | intel_sdvo->pixel_clock_max / 1000, |
| 2642 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', |
| 2643 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 2644 | /* check currently supported outputs */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2645 | intel_sdvo->caps.output_flags & |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2646 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2647 | intel_sdvo->caps.output_flags & |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2648 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2649 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2650 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2651 | err: |
Chris Wilson | 373a3cf | 2010-09-15 12:03:59 +0100 | [diff] [blame] | 2652 | drm_encoder_cleanup(&intel_encoder->base); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame^] | 2653 | i2c_del_adapter(&intel_sdvo->ddc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2654 | kfree(intel_sdvo); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2655 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2656 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2657 | } |