blob: a8828ed639b3027c476fc7d82d4d6607221b2ae1 [file] [log] [blame]
Zhang Wei173acc72008-03-01 07:42:48 -07001/*
2 * Freescale MPC85xx, MPC83xx DMA Engine support
3 *
Li Yange2c8e4252010-11-11 20:16:29 +08004 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
Zhang Wei173acc72008-03-01 07:42:48 -07005 *
6 * Author:
7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
9 *
10 * Description:
11 * DMA engine driver for Freescale MPC8540 DMA controller, which is
12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
Stefan Weilc2e07b32010-08-03 19:44:52 +020013 * The support for MPC8349 DMA controller is also added.
Zhang Wei173acc72008-03-01 07:42:48 -070014 *
Ira W. Snydera7aea372009-04-23 16:17:54 -070015 * This driver instructs the DMA controller to issue the PCI Read Multiple
16 * command for PCI read operations, instead of using the default PCI Read Line
17 * command. Please be aware that this setting may result in read pre-fetching
18 * on some platforms.
19 *
Zhang Wei173acc72008-03-01 07:42:48 -070020 * This is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 */
26
27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/pci.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Zhang Wei173acc72008-03-01 07:42:48 -070031#include <linux/interrupt.h>
32#include <linux/dmaengine.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
35#include <linux/dmapool.h>
Rob Herring5af50732013-09-17 14:28:33 -050036#include <linux/of_address.h>
37#include <linux/of_irq.h>
Zhang Wei173acc72008-03-01 07:42:48 -070038#include <linux/of_platform.h>
Vinod Koul0a5642b2014-10-11 21:16:44 +053039#include <linux/fsldma.h>
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000040#include "dmaengine.h"
Zhang Wei173acc72008-03-01 07:42:48 -070041#include "fsldma.h"
42
Ira Snyderb1584712011-03-03 07:54:55 +000043#define chan_dbg(chan, fmt, arg...) \
44 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
45#define chan_err(chan, fmt, arg...) \
46 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
Ira Snyderc14330412010-09-30 11:46:45 +000047
Ira Snyderb1584712011-03-03 07:54:55 +000048static const char msg_ld_oom[] = "No free memory for link descriptor";
Zhang Wei173acc72008-03-01 07:42:48 -070049
Ira Snydere8bd84d2011-03-03 07:54:54 +000050/*
51 * Register Helpers
52 */
Zhang Wei173acc72008-03-01 07:42:48 -070053
Ira Snydera1c03312010-01-06 13:34:05 +000054static void set_sr(struct fsldma_chan *chan, u32 val)
Zhang Wei173acc72008-03-01 07:42:48 -070055{
Ira Snydera1c03312010-01-06 13:34:05 +000056 DMA_OUT(chan, &chan->regs->sr, val, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070057}
58
Ira Snydera1c03312010-01-06 13:34:05 +000059static u32 get_sr(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070060{
Ira Snydera1c03312010-01-06 13:34:05 +000061 return DMA_IN(chan, &chan->regs->sr, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070062}
63
Hongbo Zhangccdce9a2014-04-18 16:17:45 +080064static void set_mr(struct fsldma_chan *chan, u32 val)
65{
66 DMA_OUT(chan, &chan->regs->mr, val, 32);
67}
68
69static u32 get_mr(struct fsldma_chan *chan)
70{
71 return DMA_IN(chan, &chan->regs->mr, 32);
72}
73
Ira Snydera1c03312010-01-06 13:34:05 +000074static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
Zhang Wei173acc72008-03-01 07:42:48 -070075{
Ira Snydera1c03312010-01-06 13:34:05 +000076 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
Zhang Wei173acc72008-03-01 07:42:48 -070077}
78
Ira Snydera1c03312010-01-06 13:34:05 +000079static dma_addr_t get_cdar(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070080{
Ira Snydera1c03312010-01-06 13:34:05 +000081 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
Zhang Wei173acc72008-03-01 07:42:48 -070082}
83
Hongbo Zhangccdce9a2014-04-18 16:17:45 +080084static void set_bcr(struct fsldma_chan *chan, u32 val)
85{
86 DMA_OUT(chan, &chan->regs->bcr, val, 32);
87}
88
Ira Snydera1c03312010-01-06 13:34:05 +000089static u32 get_bcr(struct fsldma_chan *chan)
Zhang Weif79abb62008-03-18 18:45:00 -070090{
Ira Snydera1c03312010-01-06 13:34:05 +000091 return DMA_IN(chan, &chan->regs->bcr, 32);
Zhang Weif79abb62008-03-18 18:45:00 -070092}
93
Ira Snydere8bd84d2011-03-03 07:54:54 +000094/*
95 * Descriptor Helpers
96 */
97
Zhang Wei173acc72008-03-01 07:42:48 -070098static void set_desc_cnt(struct fsldma_chan *chan,
99 struct fsl_dma_ld_hw *hw, u32 count)
Zhang Wei173acc72008-03-01 07:42:48 -0700100{
Zhang Wei173acc72008-03-01 07:42:48 -0700101 hw->count = CPU_TO_DMA(chan, count, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700102}
103
Zhang Wei173acc72008-03-01 07:42:48 -0700104static void set_desc_src(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +0000105 struct fsl_dma_ld_hw *hw, dma_addr_t src)
Zhang Wei173acc72008-03-01 07:42:48 -0700106{
Zhang Wei173acc72008-03-01 07:42:48 -0700107 u64 snoop_bits;
Dan Williams900325a2009-03-02 15:33:46 -0700108
Zhang Wei173acc72008-03-01 07:42:48 -0700109 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
110 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
111 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700112}
113
Zhang Wei173acc72008-03-01 07:42:48 -0700114static void set_desc_dst(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +0000115 struct fsl_dma_ld_hw *hw, dma_addr_t dst)
Zhang Wei173acc72008-03-01 07:42:48 -0700116{
117 u64 snoop_bits;
118
119 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
120 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
121 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
122}
123
124static void set_desc_next(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +0000125 struct fsl_dma_ld_hw *hw, dma_addr_t next)
Zhang Wei173acc72008-03-01 07:42:48 -0700126{
127 u64 snoop_bits;
128
129 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
130 ? FSL_DMA_SNEN : 0;
131 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
132}
133
Ira Snyder31f43062011-03-03 07:54:57 +0000134static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
Zhang Wei173acc72008-03-01 07:42:48 -0700135{
Ira Snyder776c8942009-05-15 11:33:20 -0700136 u64 snoop_bits;
137
Ira Snydera1c03312010-01-06 13:34:05 +0000138 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
Ira Snyder776c8942009-05-15 11:33:20 -0700139 ? FSL_DMA_SNEN : 0;
140
Ira Snydera1c03312010-01-06 13:34:05 +0000141 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
142 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
Ira Snyder776c8942009-05-15 11:33:20 -0700143 | snoop_bits, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700144}
145
Ira Snydere8bd84d2011-03-03 07:54:54 +0000146/*
147 * DMA Engine Hardware Control Helpers
148 */
Zhang Wei173acc72008-03-01 07:42:48 -0700149
Ira Snydere8bd84d2011-03-03 07:54:54 +0000150static void dma_init(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700151{
Ira Snydere8bd84d2011-03-03 07:54:54 +0000152 /* Reset the channel */
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800153 set_mr(chan, 0);
Zhang Wei173acc72008-03-01 07:42:48 -0700154
Ira Snydere8bd84d2011-03-03 07:54:54 +0000155 switch (chan->feature & FSL_DMA_IP_MASK) {
156 case FSL_DMA_IP_85XX:
157 /* Set the channel to below modes:
158 * EIE - Error interrupt enable
Ira Snydere8bd84d2011-03-03 07:54:54 +0000159 * EOLNIE - End of links interrupt enable
160 * BWC - Bandwidth sharing among channels
161 */
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800162 set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE
163 | FSL_DMA_MR_EOLNIE);
Ira Snydere8bd84d2011-03-03 07:54:54 +0000164 break;
165 case FSL_DMA_IP_83XX:
166 /* Set the channel to below modes:
167 * EOTIE - End-of-transfer interrupt enable
168 * PRC_RM - PCI read multiple
169 */
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800170 set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM);
Ira Snydere8bd84d2011-03-03 07:54:54 +0000171 break;
172 }
Zhang Wei173acc72008-03-01 07:42:48 -0700173}
174
175static int dma_is_idle(struct fsldma_chan *chan)
176{
177 u32 sr = get_sr(chan);
178 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
179}
180
Ira Snyderf04cd402011-03-03 07:54:58 +0000181/*
182 * Start the DMA controller
183 *
184 * Preconditions:
185 * - the CDAR register must point to the start descriptor
186 * - the MRn[CS] bit must be cleared
187 */
Zhang Wei173acc72008-03-01 07:42:48 -0700188static void dma_start(struct fsldma_chan *chan)
189{
190 u32 mode;
191
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800192 mode = get_mr(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700193
Ira Snyderf04cd402011-03-03 07:54:58 +0000194 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800195 set_bcr(chan, 0);
Ira Snyderf04cd402011-03-03 07:54:58 +0000196 mode |= FSL_DMA_MR_EMP_EN;
197 } else {
198 mode &= ~FSL_DMA_MR_EMP_EN;
Zhang Wei173acc72008-03-01 07:42:48 -0700199 }
200
Ira Snyderf04cd402011-03-03 07:54:58 +0000201 if (chan->feature & FSL_DMA_CHAN_START_EXT) {
Zhang Wei173acc72008-03-01 07:42:48 -0700202 mode |= FSL_DMA_MR_EMS_EN;
Ira Snyderf04cd402011-03-03 07:54:58 +0000203 } else {
204 mode &= ~FSL_DMA_MR_EMS_EN;
Zhang Wei173acc72008-03-01 07:42:48 -0700205 mode |= FSL_DMA_MR_CS;
Ira Snyderf04cd402011-03-03 07:54:58 +0000206 }
Zhang Wei173acc72008-03-01 07:42:48 -0700207
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800208 set_mr(chan, mode);
Zhang Wei173acc72008-03-01 07:42:48 -0700209}
210
211static void dma_halt(struct fsldma_chan *chan)
212{
213 u32 mode;
214 int i;
215
Ira Snydera00ae342011-03-03 07:55:01 +0000216 /* read the mode register */
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800217 mode = get_mr(chan);
Ira Snydera00ae342011-03-03 07:55:01 +0000218
219 /*
220 * The 85xx controller supports channel abort, which will stop
221 * the current transfer. On 83xx, this bit is the transfer error
222 * mask bit, which should not be changed.
223 */
224 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
225 mode |= FSL_DMA_MR_CA;
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800226 set_mr(chan, mode);
Ira Snydera00ae342011-03-03 07:55:01 +0000227
228 mode &= ~FSL_DMA_MR_CA;
229 }
230
231 /* stop the DMA controller */
232 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800233 set_mr(chan, mode);
Zhang Wei173acc72008-03-01 07:42:48 -0700234
Ira Snydera00ae342011-03-03 07:55:01 +0000235 /* wait for the DMA controller to become idle */
Zhang Wei173acc72008-03-01 07:42:48 -0700236 for (i = 0; i < 100; i++) {
237 if (dma_is_idle(chan))
238 return;
239
240 udelay(10);
241 }
242
243 if (!dma_is_idle(chan))
Ira Snyderb1584712011-03-03 07:54:55 +0000244 chan_err(chan, "DMA halt timeout!\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700245}
246
Zhang Wei173acc72008-03-01 07:42:48 -0700247/**
248 * fsl_chan_set_src_loop_size - Set source address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000249 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700250 * @size : Address loop size, 0 for disable loop
251 *
252 * The set source address hold transfer size. The source
253 * address hold or loop transfer size is when the DMA transfer
254 * data from source address (SA), if the loop size is 4, the DMA will
255 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
256 * SA + 1 ... and so on.
257 */
Ira Snydera1c03312010-01-06 13:34:05 +0000258static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700259{
Ira Snyder272ca652010-01-06 13:33:59 +0000260 u32 mode;
261
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800262 mode = get_mr(chan);
Ira Snyder272ca652010-01-06 13:33:59 +0000263
Zhang Wei173acc72008-03-01 07:42:48 -0700264 switch (size) {
265 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000266 mode &= ~FSL_DMA_MR_SAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700267 break;
268 case 1:
269 case 2:
270 case 4:
271 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000272 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
Zhang Wei173acc72008-03-01 07:42:48 -0700273 break;
274 }
Ira Snyder272ca652010-01-06 13:33:59 +0000275
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800276 set_mr(chan, mode);
Zhang Wei173acc72008-03-01 07:42:48 -0700277}
278
279/**
Ira Snyder738f5f72010-01-06 13:34:02 +0000280 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000281 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700282 * @size : Address loop size, 0 for disable loop
283 *
284 * The set destination address hold transfer size. The destination
285 * address hold or loop transfer size is when the DMA transfer
286 * data to destination address (TA), if the loop size is 4, the DMA will
287 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
288 * TA + 1 ... and so on.
289 */
Ira Snydera1c03312010-01-06 13:34:05 +0000290static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700291{
Ira Snyder272ca652010-01-06 13:33:59 +0000292 u32 mode;
293
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800294 mode = get_mr(chan);
Ira Snyder272ca652010-01-06 13:33:59 +0000295
Zhang Wei173acc72008-03-01 07:42:48 -0700296 switch (size) {
297 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000298 mode &= ~FSL_DMA_MR_DAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700299 break;
300 case 1:
301 case 2:
302 case 4:
303 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000304 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
Zhang Wei173acc72008-03-01 07:42:48 -0700305 break;
306 }
Ira Snyder272ca652010-01-06 13:33:59 +0000307
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800308 set_mr(chan, mode);
Zhang Wei173acc72008-03-01 07:42:48 -0700309}
310
311/**
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700312 * fsl_chan_set_request_count - Set DMA Request Count for external control
Ira Snydera1c03312010-01-06 13:34:05 +0000313 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700314 * @size : Number of bytes to transfer in a single request
315 *
316 * The Freescale DMA channel can be controlled by the external signal DREQ#.
317 * The DMA request count is how many bytes are allowed to transfer before
318 * pausing the channel, after which a new assertion of DREQ# resumes channel
319 * operation.
320 *
321 * A size of 0 disables external pause control. The maximum size is 1024.
322 */
Ira Snydera1c03312010-01-06 13:34:05 +0000323static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700324{
Ira Snyder272ca652010-01-06 13:33:59 +0000325 u32 mode;
326
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700327 BUG_ON(size > 1024);
Ira Snyder272ca652010-01-06 13:33:59 +0000328
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800329 mode = get_mr(chan);
Ira Snyder272ca652010-01-06 13:33:59 +0000330 mode |= (__ilog2(size) << 24) & 0x0f000000;
331
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800332 set_mr(chan, mode);
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700333}
334
335/**
Zhang Wei173acc72008-03-01 07:42:48 -0700336 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
Ira Snydera1c03312010-01-06 13:34:05 +0000337 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700338 * @enable : 0 is disabled, 1 is enabled.
Zhang Wei173acc72008-03-01 07:42:48 -0700339 *
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700340 * The Freescale DMA channel can be controlled by the external signal DREQ#.
341 * The DMA Request Count feature should be used in addition to this feature
342 * to set the number of bytes to transfer before pausing the channel.
Zhang Wei173acc72008-03-01 07:42:48 -0700343 */
Ira Snydera1c03312010-01-06 13:34:05 +0000344static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700345{
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700346 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000347 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700348 else
Ira Snydera1c03312010-01-06 13:34:05 +0000349 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700350}
351
352/**
353 * fsl_chan_toggle_ext_start - Toggle channel external start status
Ira Snydera1c03312010-01-06 13:34:05 +0000354 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700355 * @enable : 0 is disabled, 1 is enabled.
356 *
357 * If enable the external start, the channel can be started by an
358 * external DMA start pin. So the dma_start() does not start the
359 * transfer immediately. The DMA channel will wait for the
360 * control pin asserted.
361 */
Ira Snydera1c03312010-01-06 13:34:05 +0000362static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700363{
364 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000365 chan->feature |= FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700366 else
Ira Snydera1c03312010-01-06 13:34:05 +0000367 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700368}
369
Vinod Koul0a5642b2014-10-11 21:16:44 +0530370int fsl_dma_external_start(struct dma_chan *dchan, int enable)
371{
372 struct fsldma_chan *chan;
373
374 if (!dchan)
375 return -EINVAL;
376
377 chan = to_fsl_chan(dchan);
378
379 fsl_chan_toggle_ext_start(chan, enable);
380 return 0;
381}
382EXPORT_SYMBOL_GPL(fsl_dma_external_start);
383
Ira Snyder31f43062011-03-03 07:54:57 +0000384static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000385{
386 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
387
388 if (list_empty(&chan->ld_pending))
389 goto out_splice;
390
391 /*
392 * Add the hardware descriptor to the chain of hardware descriptors
393 * that already exists in memory.
394 *
395 * This will un-set the EOL bit of the existing transaction, and the
396 * last link in this transaction will become the EOL descriptor.
397 */
398 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
399
400 /*
401 * Add the software descriptor and all children to the list
402 * of pending transactions
403 */
404out_splice:
405 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
406}
407
Zhang Wei173acc72008-03-01 07:42:48 -0700408static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
409{
Ira Snydera1c03312010-01-06 13:34:05 +0000410 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
Dan Williamseda34232009-09-08 17:53:02 -0700411 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
412 struct fsl_desc_sw *child;
Dan Williamsbbc76562013-12-09 11:16:00 -0800413 dma_cookie_t cookie = -EINVAL;
Zhang Wei173acc72008-03-01 07:42:48 -0700414
Hongbo Zhang2baff572014-05-21 16:03:01 +0800415 spin_lock_bh(&chan->desc_lock);
Zhang Wei173acc72008-03-01 07:42:48 -0700416
Hongbo Zhang14c6a332014-05-21 16:03:02 +0800417#ifdef CONFIG_PM
418 if (unlikely(chan->pm_state != RUNNING)) {
419 chan_dbg(chan, "cannot submit due to suspend\n");
420 spin_unlock_bh(&chan->desc_lock);
421 return -1;
422 }
423#endif
424
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000425 /*
426 * assign cookies to all of the software descriptors
427 * that make up this transaction
428 */
Dan Williamseda34232009-09-08 17:53:02 -0700429 list_for_each_entry(child, &desc->tx_list, node) {
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000430 cookie = dma_cookie_assign(&child->async_tx);
Ira Snyderbcfb7462009-05-15 14:27:16 -0700431 }
432
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000433 /* put this transaction onto the tail of the pending queue */
Ira Snydera1c03312010-01-06 13:34:05 +0000434 append_ld_queue(chan, desc);
Zhang Wei173acc72008-03-01 07:42:48 -0700435
Hongbo Zhang2baff572014-05-21 16:03:01 +0800436 spin_unlock_bh(&chan->desc_lock);
Zhang Wei173acc72008-03-01 07:42:48 -0700437
438 return cookie;
439}
440
441/**
Hongbo Zhang86d19a52014-04-18 16:17:47 +0800442 * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool.
443 * @chan : Freescale DMA channel
444 * @desc: descriptor to be freed
445 */
446static void fsl_dma_free_descriptor(struct fsldma_chan *chan,
447 struct fsl_desc_sw *desc)
448{
449 list_del(&desc->node);
450 chan_dbg(chan, "LD %p free\n", desc);
451 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
452}
453
454/**
Zhang Wei173acc72008-03-01 07:42:48 -0700455 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
Ira Snydera1c03312010-01-06 13:34:05 +0000456 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700457 *
458 * Return - The descriptor allocated. NULL for failed.
459 */
Ira Snyder31f43062011-03-03 07:54:57 +0000460static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700461{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000462 struct fsl_desc_sw *desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700463 dma_addr_t pdesc;
Zhang Wei173acc72008-03-01 07:42:48 -0700464
Julia Lawall43764552016-04-29 22:09:12 +0200465 desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000466 if (!desc) {
Ira Snyderb1584712011-03-03 07:54:55 +0000467 chan_dbg(chan, "out of memory for link descriptor\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000468 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700469 }
470
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000471 INIT_LIST_HEAD(&desc->tx_list);
472 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
473 desc->async_tx.tx_submit = fsl_dma_tx_submit;
474 desc->async_tx.phys = pdesc;
475
Ira Snyder0ab09c32011-03-03 07:54:56 +0000476 chan_dbg(chan, "LD %p allocated\n", desc);
Ira Snyder0ab09c32011-03-03 07:54:56 +0000477
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000478 return desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700479}
480
Zhang Wei173acc72008-03-01 07:42:48 -0700481/**
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800482 * fsldma_clean_completed_descriptor - free all descriptors which
483 * has been completed and acked
484 * @chan: Freescale DMA channel
485 *
486 * This function is used on all completed and acked descriptors.
487 * All descriptors should only be freed in this function.
488 */
489static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan)
490{
491 struct fsl_desc_sw *desc, *_desc;
492
493 /* Run the callback for each descriptor, in order */
494 list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node)
495 if (async_tx_test_ack(&desc->async_tx))
496 fsl_dma_free_descriptor(chan, desc);
497}
498
499/**
500 * fsldma_run_tx_complete_actions - cleanup a single link descriptor
501 * @chan: Freescale DMA channel
502 * @desc: descriptor to cleanup and free
503 * @cookie: Freescale DMA transaction identifier
504 *
505 * This function is used on a descriptor which has been executed by the DMA
506 * controller. It will run any callbacks, submit any dependencies.
507 */
508static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan,
509 struct fsl_desc_sw *desc, dma_cookie_t cookie)
510{
511 struct dma_async_tx_descriptor *txd = &desc->async_tx;
512 dma_cookie_t ret = cookie;
513
514 BUG_ON(txd->cookie < 0);
515
516 if (txd->cookie > 0) {
517 ret = txd->cookie;
518
519 /* Run the link descriptor callback function */
520 if (txd->callback) {
521 chan_dbg(chan, "LD %p callback\n", desc);
522 txd->callback(txd->callback_param);
523 }
Xuelin Shia9af3162016-03-08 14:02:01 +0800524
525 dma_descriptor_unmap(txd);
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800526 }
527
528 /* Run any dependencies */
529 dma_run_dependencies(txd);
530
531 return ret;
532}
533
534/**
535 * fsldma_clean_running_descriptor - move the completed descriptor from
536 * ld_running to ld_completed
537 * @chan: Freescale DMA channel
538 * @desc: the descriptor which is completed
539 *
540 * Free the descriptor directly if acked by async_tx api, or move it to
541 * queue ld_completed.
542 */
543static void fsldma_clean_running_descriptor(struct fsldma_chan *chan,
544 struct fsl_desc_sw *desc)
545{
546 /* Remove from the list of transactions */
547 list_del(&desc->node);
548
549 /*
550 * the client is allowed to attach dependent operations
551 * until 'ack' is set
552 */
553 if (!async_tx_test_ack(&desc->async_tx)) {
554 /*
555 * Move this descriptor to the list of descriptors which is
556 * completed, but still awaiting the 'ack' bit to be set.
557 */
558 list_add_tail(&desc->node, &chan->ld_completed);
559 return;
560 }
561
562 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
563}
564
565/**
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800566 * fsl_chan_xfer_ld_queue - transfer any pending transactions
567 * @chan : Freescale DMA channel
568 *
569 * HARDWARE STATE: idle
570 * LOCKING: must hold chan->desc_lock
571 */
572static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
573{
574 struct fsl_desc_sw *desc;
575
576 /*
577 * If the list of pending descriptors is empty, then we
578 * don't need to do any work at all
579 */
580 if (list_empty(&chan->ld_pending)) {
581 chan_dbg(chan, "no pending LDs\n");
582 return;
583 }
584
585 /*
586 * The DMA controller is not idle, which means that the interrupt
587 * handler will start any queued transactions when it runs after
588 * this transaction finishes
589 */
590 if (!chan->idle) {
591 chan_dbg(chan, "DMA controller still busy\n");
592 return;
593 }
594
595 /*
596 * If there are some link descriptors which have not been
597 * transferred, we need to start the controller
598 */
599
600 /*
601 * Move all elements from the queue of pending transactions
602 * onto the list of running transactions
603 */
604 chan_dbg(chan, "idle, starting controller\n");
605 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
606 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
607
608 /*
609 * The 85xx DMA controller doesn't clear the channel start bit
610 * automatically at the end of a transfer. Therefore we must clear
611 * it in software before starting the transfer.
612 */
613 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
614 u32 mode;
615
616 mode = get_mr(chan);
617 mode &= ~FSL_DMA_MR_CS;
618 set_mr(chan, mode);
619 }
620
621 /*
622 * Program the descriptor's address into the DMA controller,
623 * then start the DMA transaction
624 */
625 set_cdar(chan, desc->async_tx.phys);
626 get_cdar(chan);
627
628 dma_start(chan);
629 chan->idle = false;
630}
631
632/**
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800633 * fsldma_cleanup_descriptors - cleanup link descriptors which are completed
634 * and move them to ld_completed to free until flag 'ack' is set
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800635 * @chan: Freescale DMA channel
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800636 *
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800637 * This function is used on descriptors which have been executed by the DMA
638 * controller. It will run any callbacks, submit any dependencies, then
639 * free these descriptors if flag 'ack' is set.
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800640 */
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800641static void fsldma_cleanup_descriptors(struct fsldma_chan *chan)
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800642{
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800643 struct fsl_desc_sw *desc, *_desc;
644 dma_cookie_t cookie = 0;
645 dma_addr_t curr_phys = get_cdar(chan);
646 int seen_current = 0;
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800647
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800648 fsldma_clean_completed_descriptor(chan);
649
650 /* Run the callback for each descriptor, in order */
651 list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
652 /*
653 * do not advance past the current descriptor loaded into the
654 * hardware channel, subsequent descriptors are either in
655 * process or have not been submitted
656 */
657 if (seen_current)
658 break;
659
660 /*
661 * stop the search if we reach the current descriptor and the
662 * channel is busy
663 */
664 if (desc->async_tx.phys == curr_phys) {
665 seen_current = 1;
666 if (!dma_is_idle(chan))
667 break;
668 }
669
670 cookie = fsldma_run_tx_complete_actions(chan, desc, cookie);
671
672 fsldma_clean_running_descriptor(chan, desc);
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800673 }
674
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800675 /*
676 * Start any pending transactions automatically
677 *
678 * In the ideal case, we keep the DMA controller busy while we go
679 * ahead and free the descriptors below.
680 */
681 fsl_chan_xfer_ld_queue(chan);
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800682
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800683 if (cookie > 0)
684 chan->common.completed_cookie = cookie;
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800685}
686
687/**
Zhang Wei173acc72008-03-01 07:42:48 -0700688 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000689 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700690 *
691 * This function will create a dma pool for descriptor allocation.
692 *
693 * Return - The number of descriptors allocated.
694 */
Ira Snydera1c03312010-01-06 13:34:05 +0000695static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700696{
Ira Snydera1c03312010-01-06 13:34:05 +0000697 struct fsldma_chan *chan = to_fsl_chan(dchan);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700698
699 /* Has this channel already been allocated? */
Ira Snydera1c03312010-01-06 13:34:05 +0000700 if (chan->desc_pool)
Timur Tabi77cd62e2008-09-26 17:00:11 -0700701 return 1;
Zhang Wei173acc72008-03-01 07:42:48 -0700702
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000703 /*
704 * We need the descriptor to be aligned to 32bytes
Zhang Wei173acc72008-03-01 07:42:48 -0700705 * for meeting FSL DMA specification requirement.
706 */
Ira Snyderb1584712011-03-03 07:54:55 +0000707 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000708 sizeof(struct fsl_desc_sw),
709 __alignof__(struct fsl_desc_sw), 0);
Ira Snydera1c03312010-01-06 13:34:05 +0000710 if (!chan->desc_pool) {
Ira Snyderb1584712011-03-03 07:54:55 +0000711 chan_err(chan, "unable to allocate descriptor pool\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000712 return -ENOMEM;
Zhang Wei173acc72008-03-01 07:42:48 -0700713 }
714
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000715 /* there is at least one descriptor free to be allocated */
Zhang Wei173acc72008-03-01 07:42:48 -0700716 return 1;
717}
718
719/**
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000720 * fsldma_free_desc_list - Free all descriptors in a queue
721 * @chan: Freescae DMA channel
722 * @list: the list to free
723 *
724 * LOCKING: must hold chan->desc_lock
725 */
726static void fsldma_free_desc_list(struct fsldma_chan *chan,
727 struct list_head *list)
728{
729 struct fsl_desc_sw *desc, *_desc;
730
Hongbo Zhang86d19a52014-04-18 16:17:47 +0800731 list_for_each_entry_safe(desc, _desc, list, node)
732 fsl_dma_free_descriptor(chan, desc);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000733}
734
735static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
736 struct list_head *list)
737{
738 struct fsl_desc_sw *desc, *_desc;
739
Hongbo Zhang86d19a52014-04-18 16:17:47 +0800740 list_for_each_entry_safe_reverse(desc, _desc, list, node)
741 fsl_dma_free_descriptor(chan, desc);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000742}
743
744/**
Zhang Wei173acc72008-03-01 07:42:48 -0700745 * fsl_dma_free_chan_resources - Free all resources of the channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000746 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700747 */
Ira Snydera1c03312010-01-06 13:34:05 +0000748static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700749{
Ira Snydera1c03312010-01-06 13:34:05 +0000750 struct fsldma_chan *chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700751
Ira Snyderb1584712011-03-03 07:54:55 +0000752 chan_dbg(chan, "free all channel resources\n");
Hongbo Zhang2baff572014-05-21 16:03:01 +0800753 spin_lock_bh(&chan->desc_lock);
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800754 fsldma_cleanup_descriptors(chan);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000755 fsldma_free_desc_list(chan, &chan->ld_pending);
756 fsldma_free_desc_list(chan, &chan->ld_running);
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800757 fsldma_free_desc_list(chan, &chan->ld_completed);
Hongbo Zhang2baff572014-05-21 16:03:01 +0800758 spin_unlock_bh(&chan->desc_lock);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700759
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000760 dma_pool_destroy(chan->desc_pool);
Ira Snydera1c03312010-01-06 13:34:05 +0000761 chan->desc_pool = NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700762}
763
Zhang Wei2187c262008-03-13 17:45:28 -0700764static struct dma_async_tx_descriptor *
Ira Snyder31f43062011-03-03 07:54:57 +0000765fsl_dma_prep_memcpy(struct dma_chan *dchan,
766 dma_addr_t dma_dst, dma_addr_t dma_src,
Zhang Wei173acc72008-03-01 07:42:48 -0700767 size_t len, unsigned long flags)
768{
Ira Snydera1c03312010-01-06 13:34:05 +0000769 struct fsldma_chan *chan;
Zhang Wei173acc72008-03-01 07:42:48 -0700770 struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
771 size_t copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700772
Ira Snydera1c03312010-01-06 13:34:05 +0000773 if (!dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700774 return NULL;
775
776 if (!len)
777 return NULL;
778
Ira Snydera1c03312010-01-06 13:34:05 +0000779 chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700780
781 do {
782
783 /* Allocate the link descriptor from DMA pool */
Ira Snydera1c03312010-01-06 13:34:05 +0000784 new = fsl_dma_alloc_descriptor(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700785 if (!new) {
Ira Snyderb1584712011-03-03 07:54:55 +0000786 chan_err(chan, "%s\n", msg_ld_oom);
Ira Snyder2e077f82009-05-15 09:59:46 -0700787 goto fail;
Zhang Wei173acc72008-03-01 07:42:48 -0700788 }
Zhang Wei173acc72008-03-01 07:42:48 -0700789
Zhang Wei56822842008-03-13 10:45:27 -0700790 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
Zhang Wei173acc72008-03-01 07:42:48 -0700791
Ira Snydera1c03312010-01-06 13:34:05 +0000792 set_desc_cnt(chan, &new->hw, copy);
793 set_desc_src(chan, &new->hw, dma_src);
794 set_desc_dst(chan, &new->hw, dma_dst);
Zhang Wei173acc72008-03-01 07:42:48 -0700795
796 if (!first)
797 first = new;
798 else
Ira Snydera1c03312010-01-06 13:34:05 +0000799 set_desc_next(chan, &prev->hw, new->async_tx.phys);
Zhang Wei173acc72008-03-01 07:42:48 -0700800
801 new->async_tx.cookie = 0;
Dan Williams636bdea2008-04-17 20:17:26 -0700802 async_tx_ack(&new->async_tx);
Zhang Wei173acc72008-03-01 07:42:48 -0700803
804 prev = new;
805 len -= copy;
806 dma_src += copy;
Ira Snyder738f5f72010-01-06 13:34:02 +0000807 dma_dst += copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700808
809 /* Insert the link descriptor to the LD ring */
Dan Williamseda34232009-09-08 17:53:02 -0700810 list_add_tail(&new->node, &first->tx_list);
Zhang Wei173acc72008-03-01 07:42:48 -0700811 } while (len);
812
Dan Williams636bdea2008-04-17 20:17:26 -0700813 new->async_tx.flags = flags; /* client is in control of this ack */
Zhang Wei173acc72008-03-01 07:42:48 -0700814 new->async_tx.cookie = -EBUSY;
815
Ira Snyder31f43062011-03-03 07:54:57 +0000816 /* Set End-of-link to the last link descriptor of new list */
Ira Snydera1c03312010-01-06 13:34:05 +0000817 set_ld_eol(chan, new);
Zhang Wei173acc72008-03-01 07:42:48 -0700818
Ira Snyder2e077f82009-05-15 09:59:46 -0700819 return &first->async_tx;
820
821fail:
822 if (!first)
823 return NULL;
824
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000825 fsldma_free_desc_list_reverse(chan, &first->tx_list);
Ira Snyder2e077f82009-05-15 09:59:46 -0700826 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700827}
828
Ira Snyderc14330412010-09-30 11:46:45 +0000829static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
830 struct scatterlist *dst_sg, unsigned int dst_nents,
831 struct scatterlist *src_sg, unsigned int src_nents,
832 unsigned long flags)
833{
834 struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
835 struct fsldma_chan *chan = to_fsl_chan(dchan);
836 size_t dst_avail, src_avail;
837 dma_addr_t dst, src;
838 size_t len;
839
840 /* basic sanity checks */
841 if (dst_nents == 0 || src_nents == 0)
842 return NULL;
843
844 if (dst_sg == NULL || src_sg == NULL)
845 return NULL;
846
847 /*
848 * TODO: should we check that both scatterlists have the same
849 * TODO: number of bytes in total? Is that really an error?
850 */
851
852 /* get prepared for the loop */
853 dst_avail = sg_dma_len(dst_sg);
854 src_avail = sg_dma_len(src_sg);
855
856 /* run until we are out of scatterlist entries */
857 while (true) {
858
859 /* create the largest transaction possible */
860 len = min_t(size_t, src_avail, dst_avail);
861 len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT);
862 if (len == 0)
863 goto fetch;
864
865 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
866 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
867
868 /* allocate and populate the descriptor */
869 new = fsl_dma_alloc_descriptor(chan);
870 if (!new) {
Ira Snyderb1584712011-03-03 07:54:55 +0000871 chan_err(chan, "%s\n", msg_ld_oom);
Ira Snyderc14330412010-09-30 11:46:45 +0000872 goto fail;
873 }
Ira Snyderc14330412010-09-30 11:46:45 +0000874
875 set_desc_cnt(chan, &new->hw, len);
876 set_desc_src(chan, &new->hw, src);
877 set_desc_dst(chan, &new->hw, dst);
878
879 if (!first)
880 first = new;
881 else
882 set_desc_next(chan, &prev->hw, new->async_tx.phys);
883
884 new->async_tx.cookie = 0;
885 async_tx_ack(&new->async_tx);
886 prev = new;
887
888 /* Insert the link descriptor to the LD ring */
889 list_add_tail(&new->node, &first->tx_list);
890
891 /* update metadata */
892 dst_avail -= len;
893 src_avail -= len;
894
895fetch:
896 /* fetch the next dst scatterlist entry */
897 if (dst_avail == 0) {
898
899 /* no more entries: we're done */
900 if (dst_nents == 0)
901 break;
902
903 /* fetch the next entry: if there are no more: done */
904 dst_sg = sg_next(dst_sg);
905 if (dst_sg == NULL)
906 break;
907
908 dst_nents--;
909 dst_avail = sg_dma_len(dst_sg);
910 }
911
912 /* fetch the next src scatterlist entry */
913 if (src_avail == 0) {
914
915 /* no more entries: we're done */
916 if (src_nents == 0)
917 break;
918
919 /* fetch the next entry: if there are no more: done */
920 src_sg = sg_next(src_sg);
921 if (src_sg == NULL)
922 break;
923
924 src_nents--;
925 src_avail = sg_dma_len(src_sg);
926 }
927 }
928
929 new->async_tx.flags = flags; /* client is in control of this ack */
930 new->async_tx.cookie = -EBUSY;
931
932 /* Set End-of-link to the last link descriptor of new list */
933 set_ld_eol(chan, new);
934
935 return &first->async_tx;
936
937fail:
938 if (!first)
939 return NULL;
940
941 fsldma_free_desc_list_reverse(chan, &first->tx_list);
942 return NULL;
943}
944
Maxime Ripardb7f75522014-11-17 14:42:24 +0100945static int fsl_dma_device_terminate_all(struct dma_chan *dchan)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700946{
Ira Snydera1c03312010-01-06 13:34:05 +0000947 struct fsldma_chan *chan;
Linus Walleijc3635c72010-03-26 16:44:01 -0700948
Ira Snydera1c03312010-01-06 13:34:05 +0000949 if (!dchan)
Linus Walleijc3635c72010-03-26 16:44:01 -0700950 return -EINVAL;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700951
Ira Snydera1c03312010-01-06 13:34:05 +0000952 chan = to_fsl_chan(dchan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700953
Maxime Ripardb7f75522014-11-17 14:42:24 +0100954 spin_lock_bh(&chan->desc_lock);
Ira Snyderf04cd402011-03-03 07:54:58 +0000955
Maxime Ripardb7f75522014-11-17 14:42:24 +0100956 /* Halt the DMA engine */
957 dma_halt(chan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700958
Maxime Ripardb7f75522014-11-17 14:42:24 +0100959 /* Remove and free all of the descriptors in the LD queue */
960 fsldma_free_desc_list(chan, &chan->ld_pending);
961 fsldma_free_desc_list(chan, &chan->ld_running);
962 fsldma_free_desc_list(chan, &chan->ld_completed);
963 chan->idle = true;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700964
Maxime Ripardb7f75522014-11-17 14:42:24 +0100965 spin_unlock_bh(&chan->desc_lock);
Linus Walleijc3635c72010-03-26 16:44:01 -0700966 return 0;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700967}
968
Maxime Ripardb7f75522014-11-17 14:42:24 +0100969static int fsl_dma_device_config(struct dma_chan *dchan,
970 struct dma_slave_config *config)
971{
972 struct fsldma_chan *chan;
973 int size;
974
975 if (!dchan)
976 return -EINVAL;
977
978 chan = to_fsl_chan(dchan);
979
980 /* make sure the channel supports setting burst size */
981 if (!chan->set_request_count)
982 return -ENXIO;
983
984 /* we set the controller burst size depending on direction */
985 if (config->direction == DMA_MEM_TO_DEV)
986 size = config->dst_addr_width * config->dst_maxburst;
987 else
988 size = config->src_addr_width * config->src_maxburst;
989
990 chan->set_request_count(chan, size);
991 return 0;
992}
993
994
Ira Snyderbbea0b62009-09-08 17:53:04 -0700995/**
Zhang Wei173acc72008-03-01 07:42:48 -0700996 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
Ira Snydera1c03312010-01-06 13:34:05 +0000997 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700998 */
Ira Snydera1c03312010-01-06 13:34:05 +0000999static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -07001000{
Ira Snydera1c03312010-01-06 13:34:05 +00001001 struct fsldma_chan *chan = to_fsl_chan(dchan);
Ira Snyderdc8d4092011-03-03 07:55:00 +00001002
Hongbo Zhang2baff572014-05-21 16:03:01 +08001003 spin_lock_bh(&chan->desc_lock);
Ira Snydera1c03312010-01-06 13:34:05 +00001004 fsl_chan_xfer_ld_queue(chan);
Hongbo Zhang2baff572014-05-21 16:03:01 +08001005 spin_unlock_bh(&chan->desc_lock);
Zhang Wei173acc72008-03-01 07:42:48 -07001006}
1007
Zhang Wei173acc72008-03-01 07:42:48 -07001008/**
Linus Walleij07934482010-03-26 16:50:49 -07001009 * fsl_tx_status - Determine the DMA status
Ira Snydera1c03312010-01-06 13:34:05 +00001010 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -07001011 */
Linus Walleij07934482010-03-26 16:50:49 -07001012static enum dma_status fsl_tx_status(struct dma_chan *dchan,
Zhang Wei173acc72008-03-01 07:42:48 -07001013 dma_cookie_t cookie,
Linus Walleij07934482010-03-26 16:50:49 -07001014 struct dma_tx_state *txstate)
Zhang Wei173acc72008-03-01 07:42:48 -07001015{
Hongbo Zhang43452fa2014-05-21 16:03:03 +08001016 struct fsldma_chan *chan = to_fsl_chan(dchan);
1017 enum dma_status ret;
1018
1019 ret = dma_cookie_status(dchan, cookie, txstate);
1020 if (ret == DMA_COMPLETE)
1021 return ret;
1022
1023 spin_lock_bh(&chan->desc_lock);
1024 fsldma_cleanup_descriptors(chan);
1025 spin_unlock_bh(&chan->desc_lock);
1026
Andy Shevchenko9b0b0bd2013-05-27 15:14:35 +03001027 return dma_cookie_status(dchan, cookie, txstate);
Zhang Wei173acc72008-03-01 07:42:48 -07001028}
1029
Ira Snyderd3f620b2010-01-06 13:34:04 +00001030/*----------------------------------------------------------------------------*/
1031/* Interrupt Handling */
1032/*----------------------------------------------------------------------------*/
1033
Ira Snydere7a29152010-01-06 13:34:03 +00001034static irqreturn_t fsldma_chan_irq(int irq, void *data)
Zhang Wei173acc72008-03-01 07:42:48 -07001035{
Ira Snydera1c03312010-01-06 13:34:05 +00001036 struct fsldma_chan *chan = data;
Ira Snydera1c03312010-01-06 13:34:05 +00001037 u32 stat;
Zhang Wei173acc72008-03-01 07:42:48 -07001038
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001039 /* save and clear the status register */
Ira Snydera1c03312010-01-06 13:34:05 +00001040 stat = get_sr(chan);
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001041 set_sr(chan, stat);
Ira Snyderb1584712011-03-03 07:54:55 +00001042 chan_dbg(chan, "irq: stat = 0x%x\n", stat);
Zhang Wei173acc72008-03-01 07:42:48 -07001043
Ira Snyderf04cd402011-03-03 07:54:58 +00001044 /* check that this was really our device */
Zhang Wei173acc72008-03-01 07:42:48 -07001045 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
1046 if (!stat)
1047 return IRQ_NONE;
1048
1049 if (stat & FSL_DMA_SR_TE)
Ira Snyderb1584712011-03-03 07:54:55 +00001050 chan_err(chan, "Transfer Error!\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001051
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001052 /*
1053 * Programming Error
Zhang Weif79abb62008-03-18 18:45:00 -07001054 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
Masanari Iidad73111c2012-08-04 23:37:53 +09001055 * trigger a PE interrupt.
Zhang Weif79abb62008-03-18 18:45:00 -07001056 */
1057 if (stat & FSL_DMA_SR_PE) {
Ira Snyderb1584712011-03-03 07:54:55 +00001058 chan_dbg(chan, "irq: Programming Error INT\n");
Zhang Weif79abb62008-03-18 18:45:00 -07001059 stat &= ~FSL_DMA_SR_PE;
Ira Snyderf04cd402011-03-03 07:54:58 +00001060 if (get_bcr(chan) != 0)
1061 chan_err(chan, "Programming Error!\n");
Zhang Wei1c629792008-04-17 20:17:25 -07001062 }
1063
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001064 /*
1065 * For MPC8349, EOCDI event need to update cookie
Zhang Wei1c629792008-04-17 20:17:25 -07001066 * and start the next transfer if it exist.
1067 */
1068 if (stat & FSL_DMA_SR_EOCDI) {
Ira Snyderb1584712011-03-03 07:54:55 +00001069 chan_dbg(chan, "irq: End-of-Chain link INT\n");
Zhang Wei1c629792008-04-17 20:17:25 -07001070 stat &= ~FSL_DMA_SR_EOCDI;
Zhang Wei173acc72008-03-01 07:42:48 -07001071 }
1072
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001073 /*
1074 * If it current transfer is the end-of-transfer,
Zhang Wei173acc72008-03-01 07:42:48 -07001075 * we should clear the Channel Start bit for
1076 * prepare next transfer.
1077 */
Zhang Wei1c629792008-04-17 20:17:25 -07001078 if (stat & FSL_DMA_SR_EOLNI) {
Ira Snyderb1584712011-03-03 07:54:55 +00001079 chan_dbg(chan, "irq: End-of-link INT\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001080 stat &= ~FSL_DMA_SR_EOLNI;
Zhang Wei173acc72008-03-01 07:42:48 -07001081 }
1082
Ira Snyderf04cd402011-03-03 07:54:58 +00001083 /* check that the DMA controller is really idle */
1084 if (!dma_is_idle(chan))
1085 chan_err(chan, "irq: controller not idle!\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001086
Ira Snyderf04cd402011-03-03 07:54:58 +00001087 /* check that we handled all of the bits */
1088 if (stat)
1089 chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
1090
1091 /*
1092 * Schedule the tasklet to handle all cleanup of the current
1093 * transaction. It will start a new transaction if there is
1094 * one pending.
1095 */
Ira Snydera1c03312010-01-06 13:34:05 +00001096 tasklet_schedule(&chan->tasklet);
Ira Snyderf04cd402011-03-03 07:54:58 +00001097 chan_dbg(chan, "irq: Exit\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001098 return IRQ_HANDLED;
1099}
1100
Zhang Wei173acc72008-03-01 07:42:48 -07001101static void dma_do_tasklet(unsigned long data)
1102{
Ira Snydera1c03312010-01-06 13:34:05 +00001103 struct fsldma_chan *chan = (struct fsldma_chan *)data;
Ira Snyderf04cd402011-03-03 07:54:58 +00001104
1105 chan_dbg(chan, "tasklet entry\n");
1106
Hongbo Zhang2baff572014-05-21 16:03:01 +08001107 spin_lock_bh(&chan->desc_lock);
Ira Snyderdc8d4092011-03-03 07:55:00 +00001108
Ira Snyderdc8d4092011-03-03 07:55:00 +00001109 /* the hardware is now idle and ready for more */
Ira Snyderf04cd402011-03-03 07:54:58 +00001110 chan->idle = true;
Ira Snyderdc8d4092011-03-03 07:55:00 +00001111
Hongbo Zhang43452fa2014-05-21 16:03:03 +08001112 /* Run all cleanup for descriptors which have been completed */
1113 fsldma_cleanup_descriptors(chan);
1114
Hongbo Zhang2baff572014-05-21 16:03:01 +08001115 spin_unlock_bh(&chan->desc_lock);
Ira Snyderf04cd402011-03-03 07:54:58 +00001116
Ira Snyderf04cd402011-03-03 07:54:58 +00001117 chan_dbg(chan, "tasklet exit\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001118}
1119
Ira Snyderd3f620b2010-01-06 13:34:04 +00001120static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
1121{
1122 struct fsldma_device *fdev = data;
1123 struct fsldma_chan *chan;
1124 unsigned int handled = 0;
1125 u32 gsr, mask;
1126 int i;
1127
1128 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1129 : in_le32(fdev->regs);
1130 mask = 0xff000000;
1131 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1132
1133 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1134 chan = fdev->chan[i];
1135 if (!chan)
1136 continue;
1137
1138 if (gsr & mask) {
1139 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1140 fsldma_chan_irq(irq, chan);
1141 handled++;
1142 }
1143
1144 gsr &= ~mask;
1145 mask >>= 8;
1146 }
1147
1148 return IRQ_RETVAL(handled);
1149}
1150
1151static void fsldma_free_irqs(struct fsldma_device *fdev)
1152{
1153 struct fsldma_chan *chan;
1154 int i;
1155
1156 if (fdev->irq != NO_IRQ) {
1157 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1158 free_irq(fdev->irq, fdev);
1159 return;
1160 }
1161
1162 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1163 chan = fdev->chan[i];
1164 if (chan && chan->irq != NO_IRQ) {
Ira Snyderb1584712011-03-03 07:54:55 +00001165 chan_dbg(chan, "free per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001166 free_irq(chan->irq, chan);
1167 }
1168 }
1169}
1170
1171static int fsldma_request_irqs(struct fsldma_device *fdev)
1172{
1173 struct fsldma_chan *chan;
1174 int ret;
1175 int i;
1176
1177 /* if we have a per-controller IRQ, use that */
1178 if (fdev->irq != NO_IRQ) {
1179 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1180 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1181 "fsldma-controller", fdev);
1182 return ret;
1183 }
1184
1185 /* no per-controller IRQ, use the per-channel IRQs */
1186 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1187 chan = fdev->chan[i];
1188 if (!chan)
1189 continue;
1190
1191 if (chan->irq == NO_IRQ) {
Ira Snyderb1584712011-03-03 07:54:55 +00001192 chan_err(chan, "interrupts property missing in device tree\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001193 ret = -ENODEV;
1194 goto out_unwind;
1195 }
1196
Ira Snyderb1584712011-03-03 07:54:55 +00001197 chan_dbg(chan, "request per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001198 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1199 "fsldma-chan", chan);
1200 if (ret) {
Ira Snyderb1584712011-03-03 07:54:55 +00001201 chan_err(chan, "unable to request per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001202 goto out_unwind;
1203 }
1204 }
1205
1206 return 0;
1207
1208out_unwind:
1209 for (/* none */; i >= 0; i--) {
1210 chan = fdev->chan[i];
1211 if (!chan)
1212 continue;
1213
1214 if (chan->irq == NO_IRQ)
1215 continue;
1216
1217 free_irq(chan->irq, chan);
1218 }
1219
1220 return ret;
1221}
1222
Ira Snydera4f56d42010-01-06 13:34:01 +00001223/*----------------------------------------------------------------------------*/
1224/* OpenFirmware Subsystem */
1225/*----------------------------------------------------------------------------*/
1226
Bill Pemberton463a1f82012-11-19 13:22:55 -05001227static int fsl_dma_chan_probe(struct fsldma_device *fdev,
Timur Tabi77cd62e2008-09-26 17:00:11 -07001228 struct device_node *node, u32 feature, const char *compatible)
Zhang Wei173acc72008-03-01 07:42:48 -07001229{
Ira Snydera1c03312010-01-06 13:34:05 +00001230 struct fsldma_chan *chan;
Ira Snyder4ce0e952010-01-06 13:34:00 +00001231 struct resource res;
Zhang Wei173acc72008-03-01 07:42:48 -07001232 int err;
1233
Zhang Wei173acc72008-03-01 07:42:48 -07001234 /* alloc channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001235 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1236 if (!chan) {
Ira Snydere7a29152010-01-06 13:34:03 +00001237 dev_err(fdev->dev, "no free memory for DMA channels!\n");
1238 err = -ENOMEM;
1239 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001240 }
1241
Ira Snydere7a29152010-01-06 13:34:03 +00001242 /* ioremap registers for use */
Ira Snydera1c03312010-01-06 13:34:05 +00001243 chan->regs = of_iomap(node, 0);
1244 if (!chan->regs) {
Ira Snydere7a29152010-01-06 13:34:03 +00001245 dev_err(fdev->dev, "unable to ioremap registers\n");
1246 err = -ENOMEM;
Ira Snydera1c03312010-01-06 13:34:05 +00001247 goto out_free_chan;
Ira Snydere7a29152010-01-06 13:34:03 +00001248 }
1249
Ira Snyder4ce0e952010-01-06 13:34:00 +00001250 err = of_address_to_resource(node, 0, &res);
Zhang Wei173acc72008-03-01 07:42:48 -07001251 if (err) {
Ira Snydere7a29152010-01-06 13:34:03 +00001252 dev_err(fdev->dev, "unable to find 'reg' property\n");
1253 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001254 }
1255
Ira Snydera1c03312010-01-06 13:34:05 +00001256 chan->feature = feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001257 if (!fdev->feature)
Ira Snydera1c03312010-01-06 13:34:05 +00001258 fdev->feature = chan->feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001259
Ira Snydere7a29152010-01-06 13:34:03 +00001260 /*
1261 * If the DMA device's feature is different than the feature
1262 * of its channels, report the bug
Zhang Wei173acc72008-03-01 07:42:48 -07001263 */
Ira Snydera1c03312010-01-06 13:34:05 +00001264 WARN_ON(fdev->feature != chan->feature);
Zhang Wei173acc72008-03-01 07:42:48 -07001265
Ira Snydera1c03312010-01-06 13:34:05 +00001266 chan->dev = fdev->dev;
Hongbo Zhang8de7a7d2013-09-26 17:33:43 +08001267 chan->id = (res.start & 0xfff) < 0x300 ?
1268 ((res.start - 0x100) & 0xfff) >> 7 :
1269 ((res.start - 0x200) & 0xfff) >> 7;
Ira Snydera1c03312010-01-06 13:34:05 +00001270 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
Ira Snydere7a29152010-01-06 13:34:03 +00001271 dev_err(fdev->dev, "too many channels for device\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001272 err = -EINVAL;
Ira Snydere7a29152010-01-06 13:34:03 +00001273 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001274 }
Zhang Wei173acc72008-03-01 07:42:48 -07001275
Ira Snydera1c03312010-01-06 13:34:05 +00001276 fdev->chan[chan->id] = chan;
1277 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
Ira Snyderb1584712011-03-03 07:54:55 +00001278 snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
Ira Snydere7a29152010-01-06 13:34:03 +00001279
1280 /* Initialize the channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001281 dma_init(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001282
1283 /* Clear cdar registers */
Ira Snydera1c03312010-01-06 13:34:05 +00001284 set_cdar(chan, 0);
Zhang Wei173acc72008-03-01 07:42:48 -07001285
Ira Snydera1c03312010-01-06 13:34:05 +00001286 switch (chan->feature & FSL_DMA_IP_MASK) {
Zhang Wei173acc72008-03-01 07:42:48 -07001287 case FSL_DMA_IP_85XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001288 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
Zhang Wei173acc72008-03-01 07:42:48 -07001289 case FSL_DMA_IP_83XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001290 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1291 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1292 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1293 chan->set_request_count = fsl_chan_set_request_count;
Zhang Wei173acc72008-03-01 07:42:48 -07001294 }
1295
Ira Snydera1c03312010-01-06 13:34:05 +00001296 spin_lock_init(&chan->desc_lock);
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001297 INIT_LIST_HEAD(&chan->ld_pending);
1298 INIT_LIST_HEAD(&chan->ld_running);
Hongbo Zhang43452fa2014-05-21 16:03:03 +08001299 INIT_LIST_HEAD(&chan->ld_completed);
Ira Snyderf04cd402011-03-03 07:54:58 +00001300 chan->idle = true;
Hongbo Zhang14c6a332014-05-21 16:03:02 +08001301#ifdef CONFIG_PM
1302 chan->pm_state = RUNNING;
1303#endif
Zhang Wei173acc72008-03-01 07:42:48 -07001304
Ira Snydera1c03312010-01-06 13:34:05 +00001305 chan->common.device = &fdev->common;
Russell King - ARM Linux8ac69542012-03-06 22:36:27 +00001306 dma_cookie_init(&chan->common);
Zhang Wei173acc72008-03-01 07:42:48 -07001307
Ira Snyderd3f620b2010-01-06 13:34:04 +00001308 /* find the IRQ line, if it exists in the device tree */
Ira Snydera1c03312010-01-06 13:34:05 +00001309 chan->irq = irq_of_parse_and_map(node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001310
Zhang Wei173acc72008-03-01 07:42:48 -07001311 /* Add the channel to DMA device channel list */
Ira Snydera1c03312010-01-06 13:34:05 +00001312 list_add_tail(&chan->common.device_node, &fdev->common.channels);
Zhang Wei173acc72008-03-01 07:42:48 -07001313
Ira Snydera1c03312010-01-06 13:34:05 +00001314 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1315 chan->irq != NO_IRQ ? chan->irq : fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001316
1317 return 0;
Li Yang51ee87f2008-05-29 23:25:45 -07001318
Ira Snydere7a29152010-01-06 13:34:03 +00001319out_iounmap_regs:
Ira Snydera1c03312010-01-06 13:34:05 +00001320 iounmap(chan->regs);
1321out_free_chan:
1322 kfree(chan);
Ira Snydere7a29152010-01-06 13:34:03 +00001323out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001324 return err;
1325}
1326
Ira Snydera1c03312010-01-06 13:34:05 +00001327static void fsl_dma_chan_remove(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -07001328{
Ira Snydera1c03312010-01-06 13:34:05 +00001329 irq_dispose_mapping(chan->irq);
1330 list_del(&chan->common.device_node);
1331 iounmap(chan->regs);
1332 kfree(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001333}
1334
Bill Pemberton463a1f82012-11-19 13:22:55 -05001335static int fsldma_of_probe(struct platform_device *op)
Zhang Wei173acc72008-03-01 07:42:48 -07001336{
Ira Snydera4f56d42010-01-06 13:34:01 +00001337 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001338 struct device_node *child;
Ira Snydere7a29152010-01-06 13:34:03 +00001339 int err;
Zhang Wei173acc72008-03-01 07:42:48 -07001340
Ira Snydera4f56d42010-01-06 13:34:01 +00001341 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
Zhang Wei173acc72008-03-01 07:42:48 -07001342 if (!fdev) {
Ira Snydere7a29152010-01-06 13:34:03 +00001343 dev_err(&op->dev, "No enough memory for 'priv'\n");
1344 err = -ENOMEM;
1345 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001346 }
Ira Snydere7a29152010-01-06 13:34:03 +00001347
1348 fdev->dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001349 INIT_LIST_HEAD(&fdev->common.channels);
1350
Ira Snydere7a29152010-01-06 13:34:03 +00001351 /* ioremap the registers for use */
Grant Likely61c7a082010-04-13 16:12:29 -07001352 fdev->regs = of_iomap(op->dev.of_node, 0);
Ira Snydere7a29152010-01-06 13:34:03 +00001353 if (!fdev->regs) {
1354 dev_err(&op->dev, "unable to ioremap registers\n");
1355 err = -ENOMEM;
1356 goto out_free_fdev;
Zhang Wei173acc72008-03-01 07:42:48 -07001357 }
1358
Ira Snyderd3f620b2010-01-06 13:34:04 +00001359 /* map the channel IRQ if it exists, but don't hookup the handler yet */
Grant Likely61c7a082010-04-13 16:12:29 -07001360 fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001361
Zhang Wei173acc72008-03-01 07:42:48 -07001362 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
Ira Snyderc14330412010-09-30 11:46:45 +00001363 dma_cap_set(DMA_SG, fdev->common.cap_mask);
Ira Snyderbbea0b62009-09-08 17:53:04 -07001364 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
Zhang Wei173acc72008-03-01 07:42:48 -07001365 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1366 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
Zhang Wei173acc72008-03-01 07:42:48 -07001367 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
Ira Snyderc14330412010-09-30 11:46:45 +00001368 fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
Linus Walleij07934482010-03-26 16:50:49 -07001369 fdev->common.device_tx_status = fsl_tx_status;
Zhang Wei173acc72008-03-01 07:42:48 -07001370 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
Maxime Ripardb7f75522014-11-17 14:42:24 +01001371 fdev->common.device_config = fsl_dma_device_config;
1372 fdev->common.device_terminate_all = fsl_dma_device_terminate_all;
Ira Snydere7a29152010-01-06 13:34:03 +00001373 fdev->common.dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001374
Kevin Hao75dc1772015-01-08 18:38:16 +08001375 fdev->common.src_addr_widths = FSL_DMA_BUSWIDTHS;
1376 fdev->common.dst_addr_widths = FSL_DMA_BUSWIDTHS;
1377 fdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1378 fdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1379
Li Yange2c8e4252010-11-11 20:16:29 +08001380 dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
1381
Jingoo Handd3daca2013-05-24 10:10:13 +09001382 platform_set_drvdata(op, fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001383
Ira Snydere7a29152010-01-06 13:34:03 +00001384 /*
1385 * We cannot use of_platform_bus_probe() because there is no
1386 * of_platform_bus_remove(). Instead, we manually instantiate every DMA
Timur Tabi77cd62e2008-09-26 17:00:11 -07001387 * channel object.
1388 */
Grant Likely61c7a082010-04-13 16:12:29 -07001389 for_each_child_of_node(op->dev.of_node, child) {
Ira Snydere7a29152010-01-06 13:34:03 +00001390 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001391 fsl_dma_chan_probe(fdev, child,
1392 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1393 "fsl,eloplus-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001394 }
1395
1396 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001397 fsl_dma_chan_probe(fdev, child,
1398 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1399 "fsl,elo-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001400 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001401 }
Zhang Wei173acc72008-03-01 07:42:48 -07001402
Ira Snyderd3f620b2010-01-06 13:34:04 +00001403 /*
1404 * Hookup the IRQ handler(s)
1405 *
1406 * If we have a per-controller interrupt, we prefer that to the
1407 * per-channel interrupts to reduce the number of shared interrupt
1408 * handlers on the same IRQ line
1409 */
1410 err = fsldma_request_irqs(fdev);
1411 if (err) {
1412 dev_err(fdev->dev, "unable to request IRQs\n");
1413 goto out_free_fdev;
1414 }
1415
Zhang Wei173acc72008-03-01 07:42:48 -07001416 dma_async_device_register(&fdev->common);
1417 return 0;
1418
Ira Snydere7a29152010-01-06 13:34:03 +00001419out_free_fdev:
Ira Snyderd3f620b2010-01-06 13:34:04 +00001420 irq_dispose_mapping(fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001421 kfree(fdev);
Ira Snydere7a29152010-01-06 13:34:03 +00001422out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001423 return err;
1424}
1425
Grant Likely2dc11582010-08-06 09:25:50 -06001426static int fsldma_of_remove(struct platform_device *op)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001427{
Ira Snydera4f56d42010-01-06 13:34:01 +00001428 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001429 unsigned int i;
1430
Jingoo Handd3daca2013-05-24 10:10:13 +09001431 fdev = platform_get_drvdata(op);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001432 dma_async_device_unregister(&fdev->common);
1433
Ira Snyderd3f620b2010-01-06 13:34:04 +00001434 fsldma_free_irqs(fdev);
1435
Ira Snydere7a29152010-01-06 13:34:03 +00001436 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001437 if (fdev->chan[i])
1438 fsl_dma_chan_remove(fdev->chan[i]);
Ira Snydere7a29152010-01-06 13:34:03 +00001439 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001440
Ira Snydere7a29152010-01-06 13:34:03 +00001441 iounmap(fdev->regs);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001442 kfree(fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001443
1444 return 0;
1445}
1446
Hongbo Zhang14c6a332014-05-21 16:03:02 +08001447#ifdef CONFIG_PM
1448static int fsldma_suspend_late(struct device *dev)
1449{
1450 struct platform_device *pdev = to_platform_device(dev);
1451 struct fsldma_device *fdev = platform_get_drvdata(pdev);
1452 struct fsldma_chan *chan;
1453 int i;
1454
1455 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1456 chan = fdev->chan[i];
1457 if (!chan)
1458 continue;
1459
1460 spin_lock_bh(&chan->desc_lock);
1461 if (unlikely(!chan->idle))
1462 goto out;
1463 chan->regs_save.mr = get_mr(chan);
1464 chan->pm_state = SUSPENDED;
1465 spin_unlock_bh(&chan->desc_lock);
1466 }
1467 return 0;
1468
1469out:
1470 for (; i >= 0; i--) {
1471 chan = fdev->chan[i];
1472 if (!chan)
1473 continue;
1474 chan->pm_state = RUNNING;
1475 spin_unlock_bh(&chan->desc_lock);
1476 }
1477 return -EBUSY;
1478}
1479
1480static int fsldma_resume_early(struct device *dev)
1481{
1482 struct platform_device *pdev = to_platform_device(dev);
1483 struct fsldma_device *fdev = platform_get_drvdata(pdev);
1484 struct fsldma_chan *chan;
1485 u32 mode;
1486 int i;
1487
1488 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1489 chan = fdev->chan[i];
1490 if (!chan)
1491 continue;
1492
1493 spin_lock_bh(&chan->desc_lock);
1494 mode = chan->regs_save.mr
1495 & ~FSL_DMA_MR_CS & ~FSL_DMA_MR_CC & ~FSL_DMA_MR_CA;
1496 set_mr(chan, mode);
1497 chan->pm_state = RUNNING;
1498 spin_unlock_bh(&chan->desc_lock);
1499 }
1500
1501 return 0;
1502}
1503
1504static const struct dev_pm_ops fsldma_pm_ops = {
1505 .suspend_late = fsldma_suspend_late,
1506 .resume_early = fsldma_resume_early,
1507};
1508#endif
1509
Márton Németh4b1cf1f2010-02-02 23:41:06 -07001510static const struct of_device_id fsldma_of_ids[] = {
Hongbo Zhang8de7a7d2013-09-26 17:33:43 +08001511 { .compatible = "fsl,elo3-dma", },
Kumar Gala049c9d42008-03-31 11:13:21 -05001512 { .compatible = "fsl,eloplus-dma", },
1513 { .compatible = "fsl,elo-dma", },
Zhang Wei173acc72008-03-01 07:42:48 -07001514 {}
1515};
Luis de Bethencourt7522c242015-09-16 22:57:17 +02001516MODULE_DEVICE_TABLE(of, fsldma_of_ids);
Zhang Wei173acc72008-03-01 07:42:48 -07001517
Ira W. Snyder8faa7cf2011-04-07 10:33:03 -07001518static struct platform_driver fsldma_of_driver = {
Grant Likely40182942010-04-13 16:13:02 -07001519 .driver = {
1520 .name = "fsl-elo-dma",
Grant Likely40182942010-04-13 16:13:02 -07001521 .of_match_table = fsldma_of_ids,
Hongbo Zhang14c6a332014-05-21 16:03:02 +08001522#ifdef CONFIG_PM
1523 .pm = &fsldma_pm_ops,
1524#endif
Grant Likely40182942010-04-13 16:13:02 -07001525 },
1526 .probe = fsldma_of_probe,
1527 .remove = fsldma_of_remove,
Zhang Wei173acc72008-03-01 07:42:48 -07001528};
1529
Ira Snydera4f56d42010-01-06 13:34:01 +00001530/*----------------------------------------------------------------------------*/
1531/* Module Init / Exit */
1532/*----------------------------------------------------------------------------*/
1533
1534static __init int fsldma_init(void)
Zhang Wei173acc72008-03-01 07:42:48 -07001535{
Hongbo Zhang8de7a7d2013-09-26 17:33:43 +08001536 pr_info("Freescale Elo series DMA driver\n");
Grant Likely00006122011-02-22 19:59:54 -07001537 return platform_driver_register(&fsldma_of_driver);
Zhang Wei173acc72008-03-01 07:42:48 -07001538}
1539
Ira Snydera4f56d42010-01-06 13:34:01 +00001540static void __exit fsldma_exit(void)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001541{
Grant Likely00006122011-02-22 19:59:54 -07001542 platform_driver_unregister(&fsldma_of_driver);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001543}
1544
Ira Snydera4f56d42010-01-06 13:34:01 +00001545subsys_initcall(fsldma_init);
1546module_exit(fsldma_exit);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001547
Hongbo Zhang8de7a7d2013-09-26 17:33:43 +08001548MODULE_DESCRIPTION("Freescale Elo series DMA driver");
Timur Tabi77cd62e2008-09-26 17:00:11 -07001549MODULE_LICENSE("GPL");