Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Freescale MPC85xx, MPC83xx DMA Engine support |
| 3 | * |
Li Yang | e2c8e425 | 2010-11-11 20:16:29 +0800 | [diff] [blame] | 4 | * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved. |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 5 | * |
| 6 | * Author: |
| 7 | * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 |
| 8 | * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 |
| 9 | * |
| 10 | * Description: |
| 11 | * DMA engine driver for Freescale MPC8540 DMA controller, which is |
| 12 | * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. |
Stefan Weil | c2e07b3 | 2010-08-03 19:44:52 +0200 | [diff] [blame] | 13 | * The support for MPC8349 DMA controller is also added. |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 14 | * |
Ira W. Snyder | a7aea37 | 2009-04-23 16:17:54 -0700 | [diff] [blame] | 15 | * This driver instructs the DMA controller to issue the PCI Read Multiple |
| 16 | * command for PCI read operations, instead of using the default PCI Read Line |
| 17 | * command. Please be aware that this setting may result in read pre-fetching |
| 18 | * on some platforms. |
| 19 | * |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 20 | * This is free software; you can redistribute it and/or modify |
| 21 | * it under the terms of the GNU General Public License as published by |
| 22 | * the Free Software Foundation; either version 2 of the License, or |
| 23 | * (at your option) any later version. |
| 24 | * |
| 25 | */ |
| 26 | |
| 27 | #include <linux/init.h> |
| 28 | #include <linux/module.h> |
| 29 | #include <linux/pci.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 30 | #include <linux/slab.h> |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 31 | #include <linux/interrupt.h> |
| 32 | #include <linux/dmaengine.h> |
| 33 | #include <linux/delay.h> |
| 34 | #include <linux/dma-mapping.h> |
| 35 | #include <linux/dmapool.h> |
Rob Herring | 5af5073 | 2013-09-17 14:28:33 -0500 | [diff] [blame] | 36 | #include <linux/of_address.h> |
| 37 | #include <linux/of_irq.h> |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 38 | #include <linux/of_platform.h> |
Vinod Koul | 0a5642b | 2014-10-11 21:16:44 +0530 | [diff] [blame] | 39 | #include <linux/fsldma.h> |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 40 | #include "dmaengine.h" |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 41 | #include "fsldma.h" |
| 42 | |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 43 | #define chan_dbg(chan, fmt, arg...) \ |
| 44 | dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg) |
| 45 | #define chan_err(chan, fmt, arg...) \ |
| 46 | dev_err(chan->dev, "%s: " fmt, chan->name, ##arg) |
Ira Snyder | c1433041 | 2010-09-30 11:46:45 +0000 | [diff] [blame] | 47 | |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 48 | static const char msg_ld_oom[] = "No free memory for link descriptor"; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 49 | |
Ira Snyder | e8bd84d | 2011-03-03 07:54:54 +0000 | [diff] [blame] | 50 | /* |
| 51 | * Register Helpers |
| 52 | */ |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 53 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 54 | static void set_sr(struct fsldma_chan *chan, u32 val) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 55 | { |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 56 | DMA_OUT(chan, &chan->regs->sr, val, 32); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 57 | } |
| 58 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 59 | static u32 get_sr(struct fsldma_chan *chan) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 60 | { |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 61 | return DMA_IN(chan, &chan->regs->sr, 32); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 62 | } |
| 63 | |
Hongbo Zhang | ccdce9a | 2014-04-18 16:17:45 +0800 | [diff] [blame] | 64 | static void set_mr(struct fsldma_chan *chan, u32 val) |
| 65 | { |
| 66 | DMA_OUT(chan, &chan->regs->mr, val, 32); |
| 67 | } |
| 68 | |
| 69 | static u32 get_mr(struct fsldma_chan *chan) |
| 70 | { |
| 71 | return DMA_IN(chan, &chan->regs->mr, 32); |
| 72 | } |
| 73 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 74 | static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 75 | { |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 76 | DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 77 | } |
| 78 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 79 | static dma_addr_t get_cdar(struct fsldma_chan *chan) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 80 | { |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 81 | return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 82 | } |
| 83 | |
Hongbo Zhang | ccdce9a | 2014-04-18 16:17:45 +0800 | [diff] [blame] | 84 | static void set_bcr(struct fsldma_chan *chan, u32 val) |
| 85 | { |
| 86 | DMA_OUT(chan, &chan->regs->bcr, val, 32); |
| 87 | } |
| 88 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 89 | static u32 get_bcr(struct fsldma_chan *chan) |
Zhang Wei | f79abb6 | 2008-03-18 18:45:00 -0700 | [diff] [blame] | 90 | { |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 91 | return DMA_IN(chan, &chan->regs->bcr, 32); |
Zhang Wei | f79abb6 | 2008-03-18 18:45:00 -0700 | [diff] [blame] | 92 | } |
| 93 | |
Ira Snyder | e8bd84d | 2011-03-03 07:54:54 +0000 | [diff] [blame] | 94 | /* |
| 95 | * Descriptor Helpers |
| 96 | */ |
| 97 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 98 | static void set_desc_cnt(struct fsldma_chan *chan, |
| 99 | struct fsl_dma_ld_hw *hw, u32 count) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 100 | { |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 101 | hw->count = CPU_TO_DMA(chan, count, 32); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 102 | } |
| 103 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 104 | static void set_desc_src(struct fsldma_chan *chan, |
Ira Snyder | 31f4306 | 2011-03-03 07:54:57 +0000 | [diff] [blame] | 105 | struct fsl_dma_ld_hw *hw, dma_addr_t src) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 106 | { |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 107 | u64 snoop_bits; |
Dan Williams | 900325a | 2009-03-02 15:33:46 -0700 | [diff] [blame] | 108 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 109 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
| 110 | ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; |
| 111 | hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 112 | } |
| 113 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 114 | static void set_desc_dst(struct fsldma_chan *chan, |
Ira Snyder | 31f4306 | 2011-03-03 07:54:57 +0000 | [diff] [blame] | 115 | struct fsl_dma_ld_hw *hw, dma_addr_t dst) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 116 | { |
| 117 | u64 snoop_bits; |
| 118 | |
| 119 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
| 120 | ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; |
| 121 | hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); |
| 122 | } |
| 123 | |
| 124 | static void set_desc_next(struct fsldma_chan *chan, |
Ira Snyder | 31f4306 | 2011-03-03 07:54:57 +0000 | [diff] [blame] | 125 | struct fsl_dma_ld_hw *hw, dma_addr_t next) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 126 | { |
| 127 | u64 snoop_bits; |
| 128 | |
| 129 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
| 130 | ? FSL_DMA_SNEN : 0; |
| 131 | hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); |
| 132 | } |
| 133 | |
Ira Snyder | 31f4306 | 2011-03-03 07:54:57 +0000 | [diff] [blame] | 134 | static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 135 | { |
Ira Snyder | 776c894 | 2009-05-15 11:33:20 -0700 | [diff] [blame] | 136 | u64 snoop_bits; |
| 137 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 138 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
Ira Snyder | 776c894 | 2009-05-15 11:33:20 -0700 | [diff] [blame] | 139 | ? FSL_DMA_SNEN : 0; |
| 140 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 141 | desc->hw.next_ln_addr = CPU_TO_DMA(chan, |
| 142 | DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL |
Ira Snyder | 776c894 | 2009-05-15 11:33:20 -0700 | [diff] [blame] | 143 | | snoop_bits, 64); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 144 | } |
| 145 | |
Ira Snyder | e8bd84d | 2011-03-03 07:54:54 +0000 | [diff] [blame] | 146 | /* |
| 147 | * DMA Engine Hardware Control Helpers |
| 148 | */ |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 149 | |
Ira Snyder | e8bd84d | 2011-03-03 07:54:54 +0000 | [diff] [blame] | 150 | static void dma_init(struct fsldma_chan *chan) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 151 | { |
Ira Snyder | e8bd84d | 2011-03-03 07:54:54 +0000 | [diff] [blame] | 152 | /* Reset the channel */ |
Hongbo Zhang | ccdce9a | 2014-04-18 16:17:45 +0800 | [diff] [blame] | 153 | set_mr(chan, 0); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 154 | |
Ira Snyder | e8bd84d | 2011-03-03 07:54:54 +0000 | [diff] [blame] | 155 | switch (chan->feature & FSL_DMA_IP_MASK) { |
| 156 | case FSL_DMA_IP_85XX: |
| 157 | /* Set the channel to below modes: |
| 158 | * EIE - Error interrupt enable |
Ira Snyder | e8bd84d | 2011-03-03 07:54:54 +0000 | [diff] [blame] | 159 | * EOLNIE - End of links interrupt enable |
| 160 | * BWC - Bandwidth sharing among channels |
| 161 | */ |
Hongbo Zhang | ccdce9a | 2014-04-18 16:17:45 +0800 | [diff] [blame] | 162 | set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE |
| 163 | | FSL_DMA_MR_EOLNIE); |
Ira Snyder | e8bd84d | 2011-03-03 07:54:54 +0000 | [diff] [blame] | 164 | break; |
| 165 | case FSL_DMA_IP_83XX: |
| 166 | /* Set the channel to below modes: |
| 167 | * EOTIE - End-of-transfer interrupt enable |
| 168 | * PRC_RM - PCI read multiple |
| 169 | */ |
Hongbo Zhang | ccdce9a | 2014-04-18 16:17:45 +0800 | [diff] [blame] | 170 | set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM); |
Ira Snyder | e8bd84d | 2011-03-03 07:54:54 +0000 | [diff] [blame] | 171 | break; |
| 172 | } |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 173 | } |
| 174 | |
| 175 | static int dma_is_idle(struct fsldma_chan *chan) |
| 176 | { |
| 177 | u32 sr = get_sr(chan); |
| 178 | return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); |
| 179 | } |
| 180 | |
Ira Snyder | f04cd40 | 2011-03-03 07:54:58 +0000 | [diff] [blame] | 181 | /* |
| 182 | * Start the DMA controller |
| 183 | * |
| 184 | * Preconditions: |
| 185 | * - the CDAR register must point to the start descriptor |
| 186 | * - the MRn[CS] bit must be cleared |
| 187 | */ |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 188 | static void dma_start(struct fsldma_chan *chan) |
| 189 | { |
| 190 | u32 mode; |
| 191 | |
Hongbo Zhang | ccdce9a | 2014-04-18 16:17:45 +0800 | [diff] [blame] | 192 | mode = get_mr(chan); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 193 | |
Ira Snyder | f04cd40 | 2011-03-03 07:54:58 +0000 | [diff] [blame] | 194 | if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { |
Hongbo Zhang | ccdce9a | 2014-04-18 16:17:45 +0800 | [diff] [blame] | 195 | set_bcr(chan, 0); |
Ira Snyder | f04cd40 | 2011-03-03 07:54:58 +0000 | [diff] [blame] | 196 | mode |= FSL_DMA_MR_EMP_EN; |
| 197 | } else { |
| 198 | mode &= ~FSL_DMA_MR_EMP_EN; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 199 | } |
| 200 | |
Ira Snyder | f04cd40 | 2011-03-03 07:54:58 +0000 | [diff] [blame] | 201 | if (chan->feature & FSL_DMA_CHAN_START_EXT) { |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 202 | mode |= FSL_DMA_MR_EMS_EN; |
Ira Snyder | f04cd40 | 2011-03-03 07:54:58 +0000 | [diff] [blame] | 203 | } else { |
| 204 | mode &= ~FSL_DMA_MR_EMS_EN; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 205 | mode |= FSL_DMA_MR_CS; |
Ira Snyder | f04cd40 | 2011-03-03 07:54:58 +0000 | [diff] [blame] | 206 | } |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 207 | |
Hongbo Zhang | ccdce9a | 2014-04-18 16:17:45 +0800 | [diff] [blame] | 208 | set_mr(chan, mode); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 209 | } |
| 210 | |
| 211 | static void dma_halt(struct fsldma_chan *chan) |
| 212 | { |
| 213 | u32 mode; |
| 214 | int i; |
| 215 | |
Ira Snyder | a00ae34 | 2011-03-03 07:55:01 +0000 | [diff] [blame] | 216 | /* read the mode register */ |
Hongbo Zhang | ccdce9a | 2014-04-18 16:17:45 +0800 | [diff] [blame] | 217 | mode = get_mr(chan); |
Ira Snyder | a00ae34 | 2011-03-03 07:55:01 +0000 | [diff] [blame] | 218 | |
| 219 | /* |
| 220 | * The 85xx controller supports channel abort, which will stop |
| 221 | * the current transfer. On 83xx, this bit is the transfer error |
| 222 | * mask bit, which should not be changed. |
| 223 | */ |
| 224 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { |
| 225 | mode |= FSL_DMA_MR_CA; |
Hongbo Zhang | ccdce9a | 2014-04-18 16:17:45 +0800 | [diff] [blame] | 226 | set_mr(chan, mode); |
Ira Snyder | a00ae34 | 2011-03-03 07:55:01 +0000 | [diff] [blame] | 227 | |
| 228 | mode &= ~FSL_DMA_MR_CA; |
| 229 | } |
| 230 | |
| 231 | /* stop the DMA controller */ |
| 232 | mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN); |
Hongbo Zhang | ccdce9a | 2014-04-18 16:17:45 +0800 | [diff] [blame] | 233 | set_mr(chan, mode); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 234 | |
Ira Snyder | a00ae34 | 2011-03-03 07:55:01 +0000 | [diff] [blame] | 235 | /* wait for the DMA controller to become idle */ |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 236 | for (i = 0; i < 100; i++) { |
| 237 | if (dma_is_idle(chan)) |
| 238 | return; |
| 239 | |
| 240 | udelay(10); |
| 241 | } |
| 242 | |
| 243 | if (!dma_is_idle(chan)) |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 244 | chan_err(chan, "DMA halt timeout!\n"); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 245 | } |
| 246 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 247 | /** |
| 248 | * fsl_chan_set_src_loop_size - Set source address hold transfer size |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 249 | * @chan : Freescale DMA channel |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 250 | * @size : Address loop size, 0 for disable loop |
| 251 | * |
| 252 | * The set source address hold transfer size. The source |
| 253 | * address hold or loop transfer size is when the DMA transfer |
| 254 | * data from source address (SA), if the loop size is 4, the DMA will |
| 255 | * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, |
| 256 | * SA + 1 ... and so on. |
| 257 | */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 258 | static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 259 | { |
Ira Snyder | 272ca65 | 2010-01-06 13:33:59 +0000 | [diff] [blame] | 260 | u32 mode; |
| 261 | |
Hongbo Zhang | ccdce9a | 2014-04-18 16:17:45 +0800 | [diff] [blame] | 262 | mode = get_mr(chan); |
Ira Snyder | 272ca65 | 2010-01-06 13:33:59 +0000 | [diff] [blame] | 263 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 264 | switch (size) { |
| 265 | case 0: |
Ira Snyder | 272ca65 | 2010-01-06 13:33:59 +0000 | [diff] [blame] | 266 | mode &= ~FSL_DMA_MR_SAHE; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 267 | break; |
| 268 | case 1: |
| 269 | case 2: |
| 270 | case 4: |
| 271 | case 8: |
Ira Snyder | 272ca65 | 2010-01-06 13:33:59 +0000 | [diff] [blame] | 272 | mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 273 | break; |
| 274 | } |
Ira Snyder | 272ca65 | 2010-01-06 13:33:59 +0000 | [diff] [blame] | 275 | |
Hongbo Zhang | ccdce9a | 2014-04-18 16:17:45 +0800 | [diff] [blame] | 276 | set_mr(chan, mode); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 277 | } |
| 278 | |
| 279 | /** |
Ira Snyder | 738f5f7 | 2010-01-06 13:34:02 +0000 | [diff] [blame] | 280 | * fsl_chan_set_dst_loop_size - Set destination address hold transfer size |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 281 | * @chan : Freescale DMA channel |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 282 | * @size : Address loop size, 0 for disable loop |
| 283 | * |
| 284 | * The set destination address hold transfer size. The destination |
| 285 | * address hold or loop transfer size is when the DMA transfer |
| 286 | * data to destination address (TA), if the loop size is 4, the DMA will |
| 287 | * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, |
| 288 | * TA + 1 ... and so on. |
| 289 | */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 290 | static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 291 | { |
Ira Snyder | 272ca65 | 2010-01-06 13:33:59 +0000 | [diff] [blame] | 292 | u32 mode; |
| 293 | |
Hongbo Zhang | ccdce9a | 2014-04-18 16:17:45 +0800 | [diff] [blame] | 294 | mode = get_mr(chan); |
Ira Snyder | 272ca65 | 2010-01-06 13:33:59 +0000 | [diff] [blame] | 295 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 296 | switch (size) { |
| 297 | case 0: |
Ira Snyder | 272ca65 | 2010-01-06 13:33:59 +0000 | [diff] [blame] | 298 | mode &= ~FSL_DMA_MR_DAHE; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 299 | break; |
| 300 | case 1: |
| 301 | case 2: |
| 302 | case 4: |
| 303 | case 8: |
Ira Snyder | 272ca65 | 2010-01-06 13:33:59 +0000 | [diff] [blame] | 304 | mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 305 | break; |
| 306 | } |
Ira Snyder | 272ca65 | 2010-01-06 13:33:59 +0000 | [diff] [blame] | 307 | |
Hongbo Zhang | ccdce9a | 2014-04-18 16:17:45 +0800 | [diff] [blame] | 308 | set_mr(chan, mode); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 309 | } |
| 310 | |
| 311 | /** |
Ira Snyder | e6c7ecb | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 312 | * fsl_chan_set_request_count - Set DMA Request Count for external control |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 313 | * @chan : Freescale DMA channel |
Ira Snyder | e6c7ecb | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 314 | * @size : Number of bytes to transfer in a single request |
| 315 | * |
| 316 | * The Freescale DMA channel can be controlled by the external signal DREQ#. |
| 317 | * The DMA request count is how many bytes are allowed to transfer before |
| 318 | * pausing the channel, after which a new assertion of DREQ# resumes channel |
| 319 | * operation. |
| 320 | * |
| 321 | * A size of 0 disables external pause control. The maximum size is 1024. |
| 322 | */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 323 | static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) |
Ira Snyder | e6c7ecb | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 324 | { |
Ira Snyder | 272ca65 | 2010-01-06 13:33:59 +0000 | [diff] [blame] | 325 | u32 mode; |
| 326 | |
Ira Snyder | e6c7ecb | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 327 | BUG_ON(size > 1024); |
Ira Snyder | 272ca65 | 2010-01-06 13:33:59 +0000 | [diff] [blame] | 328 | |
Hongbo Zhang | ccdce9a | 2014-04-18 16:17:45 +0800 | [diff] [blame] | 329 | mode = get_mr(chan); |
Ira Snyder | 272ca65 | 2010-01-06 13:33:59 +0000 | [diff] [blame] | 330 | mode |= (__ilog2(size) << 24) & 0x0f000000; |
| 331 | |
Hongbo Zhang | ccdce9a | 2014-04-18 16:17:45 +0800 | [diff] [blame] | 332 | set_mr(chan, mode); |
Ira Snyder | e6c7ecb | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 333 | } |
| 334 | |
| 335 | /** |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 336 | * fsl_chan_toggle_ext_pause - Toggle channel external pause status |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 337 | * @chan : Freescale DMA channel |
Ira Snyder | e6c7ecb | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 338 | * @enable : 0 is disabled, 1 is enabled. |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 339 | * |
Ira Snyder | e6c7ecb | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 340 | * The Freescale DMA channel can be controlled by the external signal DREQ#. |
| 341 | * The DMA Request Count feature should be used in addition to this feature |
| 342 | * to set the number of bytes to transfer before pausing the channel. |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 343 | */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 344 | static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 345 | { |
Ira Snyder | e6c7ecb | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 346 | if (enable) |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 347 | chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; |
Ira Snyder | e6c7ecb | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 348 | else |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 349 | chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 350 | } |
| 351 | |
| 352 | /** |
| 353 | * fsl_chan_toggle_ext_start - Toggle channel external start status |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 354 | * @chan : Freescale DMA channel |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 355 | * @enable : 0 is disabled, 1 is enabled. |
| 356 | * |
| 357 | * If enable the external start, the channel can be started by an |
| 358 | * external DMA start pin. So the dma_start() does not start the |
| 359 | * transfer immediately. The DMA channel will wait for the |
| 360 | * control pin asserted. |
| 361 | */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 362 | static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 363 | { |
| 364 | if (enable) |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 365 | chan->feature |= FSL_DMA_CHAN_START_EXT; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 366 | else |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 367 | chan->feature &= ~FSL_DMA_CHAN_START_EXT; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 368 | } |
| 369 | |
Vinod Koul | 0a5642b | 2014-10-11 21:16:44 +0530 | [diff] [blame] | 370 | int fsl_dma_external_start(struct dma_chan *dchan, int enable) |
| 371 | { |
| 372 | struct fsldma_chan *chan; |
| 373 | |
| 374 | if (!dchan) |
| 375 | return -EINVAL; |
| 376 | |
| 377 | chan = to_fsl_chan(dchan); |
| 378 | |
| 379 | fsl_chan_toggle_ext_start(chan, enable); |
| 380 | return 0; |
| 381 | } |
| 382 | EXPORT_SYMBOL_GPL(fsl_dma_external_start); |
| 383 | |
Ira Snyder | 31f4306 | 2011-03-03 07:54:57 +0000 | [diff] [blame] | 384 | static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 385 | { |
| 386 | struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); |
| 387 | |
| 388 | if (list_empty(&chan->ld_pending)) |
| 389 | goto out_splice; |
| 390 | |
| 391 | /* |
| 392 | * Add the hardware descriptor to the chain of hardware descriptors |
| 393 | * that already exists in memory. |
| 394 | * |
| 395 | * This will un-set the EOL bit of the existing transaction, and the |
| 396 | * last link in this transaction will become the EOL descriptor. |
| 397 | */ |
| 398 | set_desc_next(chan, &tail->hw, desc->async_tx.phys); |
| 399 | |
| 400 | /* |
| 401 | * Add the software descriptor and all children to the list |
| 402 | * of pending transactions |
| 403 | */ |
| 404 | out_splice: |
| 405 | list_splice_tail_init(&desc->tx_list, &chan->ld_pending); |
| 406 | } |
| 407 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 408 | static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) |
| 409 | { |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 410 | struct fsldma_chan *chan = to_fsl_chan(tx->chan); |
Dan Williams | eda3423 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 411 | struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); |
| 412 | struct fsl_desc_sw *child; |
Dan Williams | bbc7656 | 2013-12-09 11:16:00 -0800 | [diff] [blame] | 413 | dma_cookie_t cookie = -EINVAL; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 414 | |
Hongbo Zhang | 2baff57 | 2014-05-21 16:03:01 +0800 | [diff] [blame] | 415 | spin_lock_bh(&chan->desc_lock); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 416 | |
Hongbo Zhang | 14c6a33 | 2014-05-21 16:03:02 +0800 | [diff] [blame] | 417 | #ifdef CONFIG_PM |
| 418 | if (unlikely(chan->pm_state != RUNNING)) { |
| 419 | chan_dbg(chan, "cannot submit due to suspend\n"); |
| 420 | spin_unlock_bh(&chan->desc_lock); |
| 421 | return -1; |
| 422 | } |
| 423 | #endif |
| 424 | |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 425 | /* |
| 426 | * assign cookies to all of the software descriptors |
| 427 | * that make up this transaction |
| 428 | */ |
Dan Williams | eda3423 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 429 | list_for_each_entry(child, &desc->tx_list, node) { |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 430 | cookie = dma_cookie_assign(&child->async_tx); |
Ira Snyder | bcfb746 | 2009-05-15 14:27:16 -0700 | [diff] [blame] | 431 | } |
| 432 | |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 433 | /* put this transaction onto the tail of the pending queue */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 434 | append_ld_queue(chan, desc); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 435 | |
Hongbo Zhang | 2baff57 | 2014-05-21 16:03:01 +0800 | [diff] [blame] | 436 | spin_unlock_bh(&chan->desc_lock); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 437 | |
| 438 | return cookie; |
| 439 | } |
| 440 | |
| 441 | /** |
Hongbo Zhang | 86d19a5 | 2014-04-18 16:17:47 +0800 | [diff] [blame] | 442 | * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool. |
| 443 | * @chan : Freescale DMA channel |
| 444 | * @desc: descriptor to be freed |
| 445 | */ |
| 446 | static void fsl_dma_free_descriptor(struct fsldma_chan *chan, |
| 447 | struct fsl_desc_sw *desc) |
| 448 | { |
| 449 | list_del(&desc->node); |
| 450 | chan_dbg(chan, "LD %p free\n", desc); |
| 451 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
| 452 | } |
| 453 | |
| 454 | /** |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 455 | * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 456 | * @chan : Freescale DMA channel |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 457 | * |
| 458 | * Return - The descriptor allocated. NULL for failed. |
| 459 | */ |
Ira Snyder | 31f4306 | 2011-03-03 07:54:57 +0000 | [diff] [blame] | 460 | static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 461 | { |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 462 | struct fsl_desc_sw *desc; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 463 | dma_addr_t pdesc; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 464 | |
Julia Lawall | 4376455 | 2016-04-29 22:09:12 +0200 | [diff] [blame] | 465 | desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &pdesc); |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 466 | if (!desc) { |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 467 | chan_dbg(chan, "out of memory for link descriptor\n"); |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 468 | return NULL; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 469 | } |
| 470 | |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 471 | INIT_LIST_HEAD(&desc->tx_list); |
| 472 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); |
| 473 | desc->async_tx.tx_submit = fsl_dma_tx_submit; |
| 474 | desc->async_tx.phys = pdesc; |
| 475 | |
Ira Snyder | 0ab09c3 | 2011-03-03 07:54:56 +0000 | [diff] [blame] | 476 | chan_dbg(chan, "LD %p allocated\n", desc); |
Ira Snyder | 0ab09c3 | 2011-03-03 07:54:56 +0000 | [diff] [blame] | 477 | |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 478 | return desc; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 479 | } |
| 480 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 481 | /** |
Hongbo Zhang | 43452fa | 2014-05-21 16:03:03 +0800 | [diff] [blame] | 482 | * fsldma_clean_completed_descriptor - free all descriptors which |
| 483 | * has been completed and acked |
| 484 | * @chan: Freescale DMA channel |
| 485 | * |
| 486 | * This function is used on all completed and acked descriptors. |
| 487 | * All descriptors should only be freed in this function. |
| 488 | */ |
| 489 | static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan) |
| 490 | { |
| 491 | struct fsl_desc_sw *desc, *_desc; |
| 492 | |
| 493 | /* Run the callback for each descriptor, in order */ |
| 494 | list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node) |
| 495 | if (async_tx_test_ack(&desc->async_tx)) |
| 496 | fsl_dma_free_descriptor(chan, desc); |
| 497 | } |
| 498 | |
| 499 | /** |
| 500 | * fsldma_run_tx_complete_actions - cleanup a single link descriptor |
| 501 | * @chan: Freescale DMA channel |
| 502 | * @desc: descriptor to cleanup and free |
| 503 | * @cookie: Freescale DMA transaction identifier |
| 504 | * |
| 505 | * This function is used on a descriptor which has been executed by the DMA |
| 506 | * controller. It will run any callbacks, submit any dependencies. |
| 507 | */ |
| 508 | static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan, |
| 509 | struct fsl_desc_sw *desc, dma_cookie_t cookie) |
| 510 | { |
| 511 | struct dma_async_tx_descriptor *txd = &desc->async_tx; |
| 512 | dma_cookie_t ret = cookie; |
| 513 | |
| 514 | BUG_ON(txd->cookie < 0); |
| 515 | |
| 516 | if (txd->cookie > 0) { |
| 517 | ret = txd->cookie; |
| 518 | |
| 519 | /* Run the link descriptor callback function */ |
| 520 | if (txd->callback) { |
| 521 | chan_dbg(chan, "LD %p callback\n", desc); |
| 522 | txd->callback(txd->callback_param); |
| 523 | } |
Xuelin Shi | a9af316 | 2016-03-08 14:02:01 +0800 | [diff] [blame] | 524 | |
| 525 | dma_descriptor_unmap(txd); |
Hongbo Zhang | 43452fa | 2014-05-21 16:03:03 +0800 | [diff] [blame] | 526 | } |
| 527 | |
| 528 | /* Run any dependencies */ |
| 529 | dma_run_dependencies(txd); |
| 530 | |
| 531 | return ret; |
| 532 | } |
| 533 | |
| 534 | /** |
| 535 | * fsldma_clean_running_descriptor - move the completed descriptor from |
| 536 | * ld_running to ld_completed |
| 537 | * @chan: Freescale DMA channel |
| 538 | * @desc: the descriptor which is completed |
| 539 | * |
| 540 | * Free the descriptor directly if acked by async_tx api, or move it to |
| 541 | * queue ld_completed. |
| 542 | */ |
| 543 | static void fsldma_clean_running_descriptor(struct fsldma_chan *chan, |
| 544 | struct fsl_desc_sw *desc) |
| 545 | { |
| 546 | /* Remove from the list of transactions */ |
| 547 | list_del(&desc->node); |
| 548 | |
| 549 | /* |
| 550 | * the client is allowed to attach dependent operations |
| 551 | * until 'ack' is set |
| 552 | */ |
| 553 | if (!async_tx_test_ack(&desc->async_tx)) { |
| 554 | /* |
| 555 | * Move this descriptor to the list of descriptors which is |
| 556 | * completed, but still awaiting the 'ack' bit to be set. |
| 557 | */ |
| 558 | list_add_tail(&desc->node, &chan->ld_completed); |
| 559 | return; |
| 560 | } |
| 561 | |
| 562 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
| 563 | } |
| 564 | |
| 565 | /** |
Hongbo Zhang | 2a5ecb7 | 2014-04-18 16:17:48 +0800 | [diff] [blame] | 566 | * fsl_chan_xfer_ld_queue - transfer any pending transactions |
| 567 | * @chan : Freescale DMA channel |
| 568 | * |
| 569 | * HARDWARE STATE: idle |
| 570 | * LOCKING: must hold chan->desc_lock |
| 571 | */ |
| 572 | static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) |
| 573 | { |
| 574 | struct fsl_desc_sw *desc; |
| 575 | |
| 576 | /* |
| 577 | * If the list of pending descriptors is empty, then we |
| 578 | * don't need to do any work at all |
| 579 | */ |
| 580 | if (list_empty(&chan->ld_pending)) { |
| 581 | chan_dbg(chan, "no pending LDs\n"); |
| 582 | return; |
| 583 | } |
| 584 | |
| 585 | /* |
| 586 | * The DMA controller is not idle, which means that the interrupt |
| 587 | * handler will start any queued transactions when it runs after |
| 588 | * this transaction finishes |
| 589 | */ |
| 590 | if (!chan->idle) { |
| 591 | chan_dbg(chan, "DMA controller still busy\n"); |
| 592 | return; |
| 593 | } |
| 594 | |
| 595 | /* |
| 596 | * If there are some link descriptors which have not been |
| 597 | * transferred, we need to start the controller |
| 598 | */ |
| 599 | |
| 600 | /* |
| 601 | * Move all elements from the queue of pending transactions |
| 602 | * onto the list of running transactions |
| 603 | */ |
| 604 | chan_dbg(chan, "idle, starting controller\n"); |
| 605 | desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); |
| 606 | list_splice_tail_init(&chan->ld_pending, &chan->ld_running); |
| 607 | |
| 608 | /* |
| 609 | * The 85xx DMA controller doesn't clear the channel start bit |
| 610 | * automatically at the end of a transfer. Therefore we must clear |
| 611 | * it in software before starting the transfer. |
| 612 | */ |
| 613 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { |
| 614 | u32 mode; |
| 615 | |
| 616 | mode = get_mr(chan); |
| 617 | mode &= ~FSL_DMA_MR_CS; |
| 618 | set_mr(chan, mode); |
| 619 | } |
| 620 | |
| 621 | /* |
| 622 | * Program the descriptor's address into the DMA controller, |
| 623 | * then start the DMA transaction |
| 624 | */ |
| 625 | set_cdar(chan, desc->async_tx.phys); |
| 626 | get_cdar(chan); |
| 627 | |
| 628 | dma_start(chan); |
| 629 | chan->idle = false; |
| 630 | } |
| 631 | |
| 632 | /** |
Hongbo Zhang | 43452fa | 2014-05-21 16:03:03 +0800 | [diff] [blame] | 633 | * fsldma_cleanup_descriptors - cleanup link descriptors which are completed |
| 634 | * and move them to ld_completed to free until flag 'ack' is set |
Hongbo Zhang | 2a5ecb7 | 2014-04-18 16:17:48 +0800 | [diff] [blame] | 635 | * @chan: Freescale DMA channel |
Hongbo Zhang | 2a5ecb7 | 2014-04-18 16:17:48 +0800 | [diff] [blame] | 636 | * |
Hongbo Zhang | 43452fa | 2014-05-21 16:03:03 +0800 | [diff] [blame] | 637 | * This function is used on descriptors which have been executed by the DMA |
| 638 | * controller. It will run any callbacks, submit any dependencies, then |
| 639 | * free these descriptors if flag 'ack' is set. |
Hongbo Zhang | 2a5ecb7 | 2014-04-18 16:17:48 +0800 | [diff] [blame] | 640 | */ |
Hongbo Zhang | 43452fa | 2014-05-21 16:03:03 +0800 | [diff] [blame] | 641 | static void fsldma_cleanup_descriptors(struct fsldma_chan *chan) |
Hongbo Zhang | 2a5ecb7 | 2014-04-18 16:17:48 +0800 | [diff] [blame] | 642 | { |
Hongbo Zhang | 43452fa | 2014-05-21 16:03:03 +0800 | [diff] [blame] | 643 | struct fsl_desc_sw *desc, *_desc; |
| 644 | dma_cookie_t cookie = 0; |
| 645 | dma_addr_t curr_phys = get_cdar(chan); |
| 646 | int seen_current = 0; |
Hongbo Zhang | 2a5ecb7 | 2014-04-18 16:17:48 +0800 | [diff] [blame] | 647 | |
Hongbo Zhang | 43452fa | 2014-05-21 16:03:03 +0800 | [diff] [blame] | 648 | fsldma_clean_completed_descriptor(chan); |
| 649 | |
| 650 | /* Run the callback for each descriptor, in order */ |
| 651 | list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) { |
| 652 | /* |
| 653 | * do not advance past the current descriptor loaded into the |
| 654 | * hardware channel, subsequent descriptors are either in |
| 655 | * process or have not been submitted |
| 656 | */ |
| 657 | if (seen_current) |
| 658 | break; |
| 659 | |
| 660 | /* |
| 661 | * stop the search if we reach the current descriptor and the |
| 662 | * channel is busy |
| 663 | */ |
| 664 | if (desc->async_tx.phys == curr_phys) { |
| 665 | seen_current = 1; |
| 666 | if (!dma_is_idle(chan)) |
| 667 | break; |
| 668 | } |
| 669 | |
| 670 | cookie = fsldma_run_tx_complete_actions(chan, desc, cookie); |
| 671 | |
| 672 | fsldma_clean_running_descriptor(chan, desc); |
Hongbo Zhang | 2a5ecb7 | 2014-04-18 16:17:48 +0800 | [diff] [blame] | 673 | } |
| 674 | |
Hongbo Zhang | 43452fa | 2014-05-21 16:03:03 +0800 | [diff] [blame] | 675 | /* |
| 676 | * Start any pending transactions automatically |
| 677 | * |
| 678 | * In the ideal case, we keep the DMA controller busy while we go |
| 679 | * ahead and free the descriptors below. |
| 680 | */ |
| 681 | fsl_chan_xfer_ld_queue(chan); |
Hongbo Zhang | 2a5ecb7 | 2014-04-18 16:17:48 +0800 | [diff] [blame] | 682 | |
Hongbo Zhang | 43452fa | 2014-05-21 16:03:03 +0800 | [diff] [blame] | 683 | if (cookie > 0) |
| 684 | chan->common.completed_cookie = cookie; |
Hongbo Zhang | 2a5ecb7 | 2014-04-18 16:17:48 +0800 | [diff] [blame] | 685 | } |
| 686 | |
| 687 | /** |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 688 | * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 689 | * @chan : Freescale DMA channel |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 690 | * |
| 691 | * This function will create a dma pool for descriptor allocation. |
| 692 | * |
| 693 | * Return - The number of descriptors allocated. |
| 694 | */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 695 | static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 696 | { |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 697 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 698 | |
| 699 | /* Has this channel already been allocated? */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 700 | if (chan->desc_pool) |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 701 | return 1; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 702 | |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 703 | /* |
| 704 | * We need the descriptor to be aligned to 32bytes |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 705 | * for meeting FSL DMA specification requirement. |
| 706 | */ |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 707 | chan->desc_pool = dma_pool_create(chan->name, chan->dev, |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 708 | sizeof(struct fsl_desc_sw), |
| 709 | __alignof__(struct fsl_desc_sw), 0); |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 710 | if (!chan->desc_pool) { |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 711 | chan_err(chan, "unable to allocate descriptor pool\n"); |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 712 | return -ENOMEM; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 713 | } |
| 714 | |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 715 | /* there is at least one descriptor free to be allocated */ |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 716 | return 1; |
| 717 | } |
| 718 | |
| 719 | /** |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 720 | * fsldma_free_desc_list - Free all descriptors in a queue |
| 721 | * @chan: Freescae DMA channel |
| 722 | * @list: the list to free |
| 723 | * |
| 724 | * LOCKING: must hold chan->desc_lock |
| 725 | */ |
| 726 | static void fsldma_free_desc_list(struct fsldma_chan *chan, |
| 727 | struct list_head *list) |
| 728 | { |
| 729 | struct fsl_desc_sw *desc, *_desc; |
| 730 | |
Hongbo Zhang | 86d19a5 | 2014-04-18 16:17:47 +0800 | [diff] [blame] | 731 | list_for_each_entry_safe(desc, _desc, list, node) |
| 732 | fsl_dma_free_descriptor(chan, desc); |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 733 | } |
| 734 | |
| 735 | static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, |
| 736 | struct list_head *list) |
| 737 | { |
| 738 | struct fsl_desc_sw *desc, *_desc; |
| 739 | |
Hongbo Zhang | 86d19a5 | 2014-04-18 16:17:47 +0800 | [diff] [blame] | 740 | list_for_each_entry_safe_reverse(desc, _desc, list, node) |
| 741 | fsl_dma_free_descriptor(chan, desc); |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 742 | } |
| 743 | |
| 744 | /** |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 745 | * fsl_dma_free_chan_resources - Free all resources of the channel. |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 746 | * @chan : Freescale DMA channel |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 747 | */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 748 | static void fsl_dma_free_chan_resources(struct dma_chan *dchan) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 749 | { |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 750 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 751 | |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 752 | chan_dbg(chan, "free all channel resources\n"); |
Hongbo Zhang | 2baff57 | 2014-05-21 16:03:01 +0800 | [diff] [blame] | 753 | spin_lock_bh(&chan->desc_lock); |
Hongbo Zhang | 43452fa | 2014-05-21 16:03:03 +0800 | [diff] [blame] | 754 | fsldma_cleanup_descriptors(chan); |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 755 | fsldma_free_desc_list(chan, &chan->ld_pending); |
| 756 | fsldma_free_desc_list(chan, &chan->ld_running); |
Hongbo Zhang | 43452fa | 2014-05-21 16:03:03 +0800 | [diff] [blame] | 757 | fsldma_free_desc_list(chan, &chan->ld_completed); |
Hongbo Zhang | 2baff57 | 2014-05-21 16:03:01 +0800 | [diff] [blame] | 758 | spin_unlock_bh(&chan->desc_lock); |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 759 | |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 760 | dma_pool_destroy(chan->desc_pool); |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 761 | chan->desc_pool = NULL; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 762 | } |
| 763 | |
Zhang Wei | 2187c26 | 2008-03-13 17:45:28 -0700 | [diff] [blame] | 764 | static struct dma_async_tx_descriptor * |
Ira Snyder | 31f4306 | 2011-03-03 07:54:57 +0000 | [diff] [blame] | 765 | fsl_dma_prep_memcpy(struct dma_chan *dchan, |
| 766 | dma_addr_t dma_dst, dma_addr_t dma_src, |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 767 | size_t len, unsigned long flags) |
| 768 | { |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 769 | struct fsldma_chan *chan; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 770 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new; |
| 771 | size_t copy; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 772 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 773 | if (!dchan) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 774 | return NULL; |
| 775 | |
| 776 | if (!len) |
| 777 | return NULL; |
| 778 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 779 | chan = to_fsl_chan(dchan); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 780 | |
| 781 | do { |
| 782 | |
| 783 | /* Allocate the link descriptor from DMA pool */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 784 | new = fsl_dma_alloc_descriptor(chan); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 785 | if (!new) { |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 786 | chan_err(chan, "%s\n", msg_ld_oom); |
Ira Snyder | 2e077f8 | 2009-05-15 09:59:46 -0700 | [diff] [blame] | 787 | goto fail; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 788 | } |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 789 | |
Zhang Wei | 5682284 | 2008-03-13 10:45:27 -0700 | [diff] [blame] | 790 | copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 791 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 792 | set_desc_cnt(chan, &new->hw, copy); |
| 793 | set_desc_src(chan, &new->hw, dma_src); |
| 794 | set_desc_dst(chan, &new->hw, dma_dst); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 795 | |
| 796 | if (!first) |
| 797 | first = new; |
| 798 | else |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 799 | set_desc_next(chan, &prev->hw, new->async_tx.phys); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 800 | |
| 801 | new->async_tx.cookie = 0; |
Dan Williams | 636bdea | 2008-04-17 20:17:26 -0700 | [diff] [blame] | 802 | async_tx_ack(&new->async_tx); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 803 | |
| 804 | prev = new; |
| 805 | len -= copy; |
| 806 | dma_src += copy; |
Ira Snyder | 738f5f7 | 2010-01-06 13:34:02 +0000 | [diff] [blame] | 807 | dma_dst += copy; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 808 | |
| 809 | /* Insert the link descriptor to the LD ring */ |
Dan Williams | eda3423 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 810 | list_add_tail(&new->node, &first->tx_list); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 811 | } while (len); |
| 812 | |
Dan Williams | 636bdea | 2008-04-17 20:17:26 -0700 | [diff] [blame] | 813 | new->async_tx.flags = flags; /* client is in control of this ack */ |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 814 | new->async_tx.cookie = -EBUSY; |
| 815 | |
Ira Snyder | 31f4306 | 2011-03-03 07:54:57 +0000 | [diff] [blame] | 816 | /* Set End-of-link to the last link descriptor of new list */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 817 | set_ld_eol(chan, new); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 818 | |
Ira Snyder | 2e077f8 | 2009-05-15 09:59:46 -0700 | [diff] [blame] | 819 | return &first->async_tx; |
| 820 | |
| 821 | fail: |
| 822 | if (!first) |
| 823 | return NULL; |
| 824 | |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 825 | fsldma_free_desc_list_reverse(chan, &first->tx_list); |
Ira Snyder | 2e077f8 | 2009-05-15 09:59:46 -0700 | [diff] [blame] | 826 | return NULL; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 827 | } |
| 828 | |
Ira Snyder | c1433041 | 2010-09-30 11:46:45 +0000 | [diff] [blame] | 829 | static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan, |
| 830 | struct scatterlist *dst_sg, unsigned int dst_nents, |
| 831 | struct scatterlist *src_sg, unsigned int src_nents, |
| 832 | unsigned long flags) |
| 833 | { |
| 834 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; |
| 835 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
| 836 | size_t dst_avail, src_avail; |
| 837 | dma_addr_t dst, src; |
| 838 | size_t len; |
| 839 | |
| 840 | /* basic sanity checks */ |
| 841 | if (dst_nents == 0 || src_nents == 0) |
| 842 | return NULL; |
| 843 | |
| 844 | if (dst_sg == NULL || src_sg == NULL) |
| 845 | return NULL; |
| 846 | |
| 847 | /* |
| 848 | * TODO: should we check that both scatterlists have the same |
| 849 | * TODO: number of bytes in total? Is that really an error? |
| 850 | */ |
| 851 | |
| 852 | /* get prepared for the loop */ |
| 853 | dst_avail = sg_dma_len(dst_sg); |
| 854 | src_avail = sg_dma_len(src_sg); |
| 855 | |
| 856 | /* run until we are out of scatterlist entries */ |
| 857 | while (true) { |
| 858 | |
| 859 | /* create the largest transaction possible */ |
| 860 | len = min_t(size_t, src_avail, dst_avail); |
| 861 | len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT); |
| 862 | if (len == 0) |
| 863 | goto fetch; |
| 864 | |
| 865 | dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail; |
| 866 | src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail; |
| 867 | |
| 868 | /* allocate and populate the descriptor */ |
| 869 | new = fsl_dma_alloc_descriptor(chan); |
| 870 | if (!new) { |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 871 | chan_err(chan, "%s\n", msg_ld_oom); |
Ira Snyder | c1433041 | 2010-09-30 11:46:45 +0000 | [diff] [blame] | 872 | goto fail; |
| 873 | } |
Ira Snyder | c1433041 | 2010-09-30 11:46:45 +0000 | [diff] [blame] | 874 | |
| 875 | set_desc_cnt(chan, &new->hw, len); |
| 876 | set_desc_src(chan, &new->hw, src); |
| 877 | set_desc_dst(chan, &new->hw, dst); |
| 878 | |
| 879 | if (!first) |
| 880 | first = new; |
| 881 | else |
| 882 | set_desc_next(chan, &prev->hw, new->async_tx.phys); |
| 883 | |
| 884 | new->async_tx.cookie = 0; |
| 885 | async_tx_ack(&new->async_tx); |
| 886 | prev = new; |
| 887 | |
| 888 | /* Insert the link descriptor to the LD ring */ |
| 889 | list_add_tail(&new->node, &first->tx_list); |
| 890 | |
| 891 | /* update metadata */ |
| 892 | dst_avail -= len; |
| 893 | src_avail -= len; |
| 894 | |
| 895 | fetch: |
| 896 | /* fetch the next dst scatterlist entry */ |
| 897 | if (dst_avail == 0) { |
| 898 | |
| 899 | /* no more entries: we're done */ |
| 900 | if (dst_nents == 0) |
| 901 | break; |
| 902 | |
| 903 | /* fetch the next entry: if there are no more: done */ |
| 904 | dst_sg = sg_next(dst_sg); |
| 905 | if (dst_sg == NULL) |
| 906 | break; |
| 907 | |
| 908 | dst_nents--; |
| 909 | dst_avail = sg_dma_len(dst_sg); |
| 910 | } |
| 911 | |
| 912 | /* fetch the next src scatterlist entry */ |
| 913 | if (src_avail == 0) { |
| 914 | |
| 915 | /* no more entries: we're done */ |
| 916 | if (src_nents == 0) |
| 917 | break; |
| 918 | |
| 919 | /* fetch the next entry: if there are no more: done */ |
| 920 | src_sg = sg_next(src_sg); |
| 921 | if (src_sg == NULL) |
| 922 | break; |
| 923 | |
| 924 | src_nents--; |
| 925 | src_avail = sg_dma_len(src_sg); |
| 926 | } |
| 927 | } |
| 928 | |
| 929 | new->async_tx.flags = flags; /* client is in control of this ack */ |
| 930 | new->async_tx.cookie = -EBUSY; |
| 931 | |
| 932 | /* Set End-of-link to the last link descriptor of new list */ |
| 933 | set_ld_eol(chan, new); |
| 934 | |
| 935 | return &first->async_tx; |
| 936 | |
| 937 | fail: |
| 938 | if (!first) |
| 939 | return NULL; |
| 940 | |
| 941 | fsldma_free_desc_list_reverse(chan, &first->tx_list); |
| 942 | return NULL; |
| 943 | } |
| 944 | |
Maxime Ripard | b7f7552 | 2014-11-17 14:42:24 +0100 | [diff] [blame] | 945 | static int fsl_dma_device_terminate_all(struct dma_chan *dchan) |
Ira Snyder | bbea0b6 | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 946 | { |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 947 | struct fsldma_chan *chan; |
Linus Walleij | c3635c7 | 2010-03-26 16:44:01 -0700 | [diff] [blame] | 948 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 949 | if (!dchan) |
Linus Walleij | c3635c7 | 2010-03-26 16:44:01 -0700 | [diff] [blame] | 950 | return -EINVAL; |
Ira Snyder | bbea0b6 | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 951 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 952 | chan = to_fsl_chan(dchan); |
Ira Snyder | bbea0b6 | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 953 | |
Maxime Ripard | b7f7552 | 2014-11-17 14:42:24 +0100 | [diff] [blame] | 954 | spin_lock_bh(&chan->desc_lock); |
Ira Snyder | f04cd40 | 2011-03-03 07:54:58 +0000 | [diff] [blame] | 955 | |
Maxime Ripard | b7f7552 | 2014-11-17 14:42:24 +0100 | [diff] [blame] | 956 | /* Halt the DMA engine */ |
| 957 | dma_halt(chan); |
Ira Snyder | bbea0b6 | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 958 | |
Maxime Ripard | b7f7552 | 2014-11-17 14:42:24 +0100 | [diff] [blame] | 959 | /* Remove and free all of the descriptors in the LD queue */ |
| 960 | fsldma_free_desc_list(chan, &chan->ld_pending); |
| 961 | fsldma_free_desc_list(chan, &chan->ld_running); |
| 962 | fsldma_free_desc_list(chan, &chan->ld_completed); |
| 963 | chan->idle = true; |
Ira Snyder | bbea0b6 | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 964 | |
Maxime Ripard | b7f7552 | 2014-11-17 14:42:24 +0100 | [diff] [blame] | 965 | spin_unlock_bh(&chan->desc_lock); |
Linus Walleij | c3635c7 | 2010-03-26 16:44:01 -0700 | [diff] [blame] | 966 | return 0; |
Ira Snyder | bbea0b6 | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 967 | } |
| 968 | |
Maxime Ripard | b7f7552 | 2014-11-17 14:42:24 +0100 | [diff] [blame] | 969 | static int fsl_dma_device_config(struct dma_chan *dchan, |
| 970 | struct dma_slave_config *config) |
| 971 | { |
| 972 | struct fsldma_chan *chan; |
| 973 | int size; |
| 974 | |
| 975 | if (!dchan) |
| 976 | return -EINVAL; |
| 977 | |
| 978 | chan = to_fsl_chan(dchan); |
| 979 | |
| 980 | /* make sure the channel supports setting burst size */ |
| 981 | if (!chan->set_request_count) |
| 982 | return -ENXIO; |
| 983 | |
| 984 | /* we set the controller burst size depending on direction */ |
| 985 | if (config->direction == DMA_MEM_TO_DEV) |
| 986 | size = config->dst_addr_width * config->dst_maxburst; |
| 987 | else |
| 988 | size = config->src_addr_width * config->src_maxburst; |
| 989 | |
| 990 | chan->set_request_count(chan, size); |
| 991 | return 0; |
| 992 | } |
| 993 | |
| 994 | |
Ira Snyder | bbea0b6 | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 995 | /** |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 996 | * fsl_dma_memcpy_issue_pending - Issue the DMA start command |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 997 | * @chan : Freescale DMA channel |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 998 | */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 999 | static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1000 | { |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1001 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
Ira Snyder | dc8d409 | 2011-03-03 07:55:00 +0000 | [diff] [blame] | 1002 | |
Hongbo Zhang | 2baff57 | 2014-05-21 16:03:01 +0800 | [diff] [blame] | 1003 | spin_lock_bh(&chan->desc_lock); |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1004 | fsl_chan_xfer_ld_queue(chan); |
Hongbo Zhang | 2baff57 | 2014-05-21 16:03:01 +0800 | [diff] [blame] | 1005 | spin_unlock_bh(&chan->desc_lock); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1006 | } |
| 1007 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1008 | /** |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1009 | * fsl_tx_status - Determine the DMA status |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1010 | * @chan : Freescale DMA channel |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1011 | */ |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1012 | static enum dma_status fsl_tx_status(struct dma_chan *dchan, |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1013 | dma_cookie_t cookie, |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1014 | struct dma_tx_state *txstate) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1015 | { |
Hongbo Zhang | 43452fa | 2014-05-21 16:03:03 +0800 | [diff] [blame] | 1016 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
| 1017 | enum dma_status ret; |
| 1018 | |
| 1019 | ret = dma_cookie_status(dchan, cookie, txstate); |
| 1020 | if (ret == DMA_COMPLETE) |
| 1021 | return ret; |
| 1022 | |
| 1023 | spin_lock_bh(&chan->desc_lock); |
| 1024 | fsldma_cleanup_descriptors(chan); |
| 1025 | spin_unlock_bh(&chan->desc_lock); |
| 1026 | |
Andy Shevchenko | 9b0b0bd | 2013-05-27 15:14:35 +0300 | [diff] [blame] | 1027 | return dma_cookie_status(dchan, cookie, txstate); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1028 | } |
| 1029 | |
Ira Snyder | d3f620b | 2010-01-06 13:34:04 +0000 | [diff] [blame] | 1030 | /*----------------------------------------------------------------------------*/ |
| 1031 | /* Interrupt Handling */ |
| 1032 | /*----------------------------------------------------------------------------*/ |
| 1033 | |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1034 | static irqreturn_t fsldma_chan_irq(int irq, void *data) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1035 | { |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1036 | struct fsldma_chan *chan = data; |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1037 | u32 stat; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1038 | |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 1039 | /* save and clear the status register */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1040 | stat = get_sr(chan); |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 1041 | set_sr(chan, stat); |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 1042 | chan_dbg(chan, "irq: stat = 0x%x\n", stat); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1043 | |
Ira Snyder | f04cd40 | 2011-03-03 07:54:58 +0000 | [diff] [blame] | 1044 | /* check that this was really our device */ |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1045 | stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); |
| 1046 | if (!stat) |
| 1047 | return IRQ_NONE; |
| 1048 | |
| 1049 | if (stat & FSL_DMA_SR_TE) |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 1050 | chan_err(chan, "Transfer Error!\n"); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1051 | |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 1052 | /* |
| 1053 | * Programming Error |
Zhang Wei | f79abb6 | 2008-03-18 18:45:00 -0700 | [diff] [blame] | 1054 | * The DMA_INTERRUPT async_tx is a NULL transfer, which will |
Masanari Iida | d73111c | 2012-08-04 23:37:53 +0900 | [diff] [blame] | 1055 | * trigger a PE interrupt. |
Zhang Wei | f79abb6 | 2008-03-18 18:45:00 -0700 | [diff] [blame] | 1056 | */ |
| 1057 | if (stat & FSL_DMA_SR_PE) { |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 1058 | chan_dbg(chan, "irq: Programming Error INT\n"); |
Zhang Wei | f79abb6 | 2008-03-18 18:45:00 -0700 | [diff] [blame] | 1059 | stat &= ~FSL_DMA_SR_PE; |
Ira Snyder | f04cd40 | 2011-03-03 07:54:58 +0000 | [diff] [blame] | 1060 | if (get_bcr(chan) != 0) |
| 1061 | chan_err(chan, "Programming Error!\n"); |
Zhang Wei | 1c62979 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 1062 | } |
| 1063 | |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 1064 | /* |
| 1065 | * For MPC8349, EOCDI event need to update cookie |
Zhang Wei | 1c62979 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 1066 | * and start the next transfer if it exist. |
| 1067 | */ |
| 1068 | if (stat & FSL_DMA_SR_EOCDI) { |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 1069 | chan_dbg(chan, "irq: End-of-Chain link INT\n"); |
Zhang Wei | 1c62979 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 1070 | stat &= ~FSL_DMA_SR_EOCDI; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1071 | } |
| 1072 | |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 1073 | /* |
| 1074 | * If it current transfer is the end-of-transfer, |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1075 | * we should clear the Channel Start bit for |
| 1076 | * prepare next transfer. |
| 1077 | */ |
Zhang Wei | 1c62979 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 1078 | if (stat & FSL_DMA_SR_EOLNI) { |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 1079 | chan_dbg(chan, "irq: End-of-link INT\n"); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1080 | stat &= ~FSL_DMA_SR_EOLNI; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1081 | } |
| 1082 | |
Ira Snyder | f04cd40 | 2011-03-03 07:54:58 +0000 | [diff] [blame] | 1083 | /* check that the DMA controller is really idle */ |
| 1084 | if (!dma_is_idle(chan)) |
| 1085 | chan_err(chan, "irq: controller not idle!\n"); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1086 | |
Ira Snyder | f04cd40 | 2011-03-03 07:54:58 +0000 | [diff] [blame] | 1087 | /* check that we handled all of the bits */ |
| 1088 | if (stat) |
| 1089 | chan_err(chan, "irq: unhandled sr 0x%08x\n", stat); |
| 1090 | |
| 1091 | /* |
| 1092 | * Schedule the tasklet to handle all cleanup of the current |
| 1093 | * transaction. It will start a new transaction if there is |
| 1094 | * one pending. |
| 1095 | */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1096 | tasklet_schedule(&chan->tasklet); |
Ira Snyder | f04cd40 | 2011-03-03 07:54:58 +0000 | [diff] [blame] | 1097 | chan_dbg(chan, "irq: Exit\n"); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1098 | return IRQ_HANDLED; |
| 1099 | } |
| 1100 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1101 | static void dma_do_tasklet(unsigned long data) |
| 1102 | { |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1103 | struct fsldma_chan *chan = (struct fsldma_chan *)data; |
Ira Snyder | f04cd40 | 2011-03-03 07:54:58 +0000 | [diff] [blame] | 1104 | |
| 1105 | chan_dbg(chan, "tasklet entry\n"); |
| 1106 | |
Hongbo Zhang | 2baff57 | 2014-05-21 16:03:01 +0800 | [diff] [blame] | 1107 | spin_lock_bh(&chan->desc_lock); |
Ira Snyder | dc8d409 | 2011-03-03 07:55:00 +0000 | [diff] [blame] | 1108 | |
Ira Snyder | dc8d409 | 2011-03-03 07:55:00 +0000 | [diff] [blame] | 1109 | /* the hardware is now idle and ready for more */ |
Ira Snyder | f04cd40 | 2011-03-03 07:54:58 +0000 | [diff] [blame] | 1110 | chan->idle = true; |
Ira Snyder | dc8d409 | 2011-03-03 07:55:00 +0000 | [diff] [blame] | 1111 | |
Hongbo Zhang | 43452fa | 2014-05-21 16:03:03 +0800 | [diff] [blame] | 1112 | /* Run all cleanup for descriptors which have been completed */ |
| 1113 | fsldma_cleanup_descriptors(chan); |
| 1114 | |
Hongbo Zhang | 2baff57 | 2014-05-21 16:03:01 +0800 | [diff] [blame] | 1115 | spin_unlock_bh(&chan->desc_lock); |
Ira Snyder | f04cd40 | 2011-03-03 07:54:58 +0000 | [diff] [blame] | 1116 | |
Ira Snyder | f04cd40 | 2011-03-03 07:54:58 +0000 | [diff] [blame] | 1117 | chan_dbg(chan, "tasklet exit\n"); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1118 | } |
| 1119 | |
Ira Snyder | d3f620b | 2010-01-06 13:34:04 +0000 | [diff] [blame] | 1120 | static irqreturn_t fsldma_ctrl_irq(int irq, void *data) |
| 1121 | { |
| 1122 | struct fsldma_device *fdev = data; |
| 1123 | struct fsldma_chan *chan; |
| 1124 | unsigned int handled = 0; |
| 1125 | u32 gsr, mask; |
| 1126 | int i; |
| 1127 | |
| 1128 | gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) |
| 1129 | : in_le32(fdev->regs); |
| 1130 | mask = 0xff000000; |
| 1131 | dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); |
| 1132 | |
| 1133 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
| 1134 | chan = fdev->chan[i]; |
| 1135 | if (!chan) |
| 1136 | continue; |
| 1137 | |
| 1138 | if (gsr & mask) { |
| 1139 | dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); |
| 1140 | fsldma_chan_irq(irq, chan); |
| 1141 | handled++; |
| 1142 | } |
| 1143 | |
| 1144 | gsr &= ~mask; |
| 1145 | mask >>= 8; |
| 1146 | } |
| 1147 | |
| 1148 | return IRQ_RETVAL(handled); |
| 1149 | } |
| 1150 | |
| 1151 | static void fsldma_free_irqs(struct fsldma_device *fdev) |
| 1152 | { |
| 1153 | struct fsldma_chan *chan; |
| 1154 | int i; |
| 1155 | |
| 1156 | if (fdev->irq != NO_IRQ) { |
| 1157 | dev_dbg(fdev->dev, "free per-controller IRQ\n"); |
| 1158 | free_irq(fdev->irq, fdev); |
| 1159 | return; |
| 1160 | } |
| 1161 | |
| 1162 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
| 1163 | chan = fdev->chan[i]; |
| 1164 | if (chan && chan->irq != NO_IRQ) { |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 1165 | chan_dbg(chan, "free per-channel IRQ\n"); |
Ira Snyder | d3f620b | 2010-01-06 13:34:04 +0000 | [diff] [blame] | 1166 | free_irq(chan->irq, chan); |
| 1167 | } |
| 1168 | } |
| 1169 | } |
| 1170 | |
| 1171 | static int fsldma_request_irqs(struct fsldma_device *fdev) |
| 1172 | { |
| 1173 | struct fsldma_chan *chan; |
| 1174 | int ret; |
| 1175 | int i; |
| 1176 | |
| 1177 | /* if we have a per-controller IRQ, use that */ |
| 1178 | if (fdev->irq != NO_IRQ) { |
| 1179 | dev_dbg(fdev->dev, "request per-controller IRQ\n"); |
| 1180 | ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, |
| 1181 | "fsldma-controller", fdev); |
| 1182 | return ret; |
| 1183 | } |
| 1184 | |
| 1185 | /* no per-controller IRQ, use the per-channel IRQs */ |
| 1186 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
| 1187 | chan = fdev->chan[i]; |
| 1188 | if (!chan) |
| 1189 | continue; |
| 1190 | |
| 1191 | if (chan->irq == NO_IRQ) { |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 1192 | chan_err(chan, "interrupts property missing in device tree\n"); |
Ira Snyder | d3f620b | 2010-01-06 13:34:04 +0000 | [diff] [blame] | 1193 | ret = -ENODEV; |
| 1194 | goto out_unwind; |
| 1195 | } |
| 1196 | |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 1197 | chan_dbg(chan, "request per-channel IRQ\n"); |
Ira Snyder | d3f620b | 2010-01-06 13:34:04 +0000 | [diff] [blame] | 1198 | ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, |
| 1199 | "fsldma-chan", chan); |
| 1200 | if (ret) { |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 1201 | chan_err(chan, "unable to request per-channel IRQ\n"); |
Ira Snyder | d3f620b | 2010-01-06 13:34:04 +0000 | [diff] [blame] | 1202 | goto out_unwind; |
| 1203 | } |
| 1204 | } |
| 1205 | |
| 1206 | return 0; |
| 1207 | |
| 1208 | out_unwind: |
| 1209 | for (/* none */; i >= 0; i--) { |
| 1210 | chan = fdev->chan[i]; |
| 1211 | if (!chan) |
| 1212 | continue; |
| 1213 | |
| 1214 | if (chan->irq == NO_IRQ) |
| 1215 | continue; |
| 1216 | |
| 1217 | free_irq(chan->irq, chan); |
| 1218 | } |
| 1219 | |
| 1220 | return ret; |
| 1221 | } |
| 1222 | |
Ira Snyder | a4f56d4 | 2010-01-06 13:34:01 +0000 | [diff] [blame] | 1223 | /*----------------------------------------------------------------------------*/ |
| 1224 | /* OpenFirmware Subsystem */ |
| 1225 | /*----------------------------------------------------------------------------*/ |
| 1226 | |
Bill Pemberton | 463a1f8 | 2012-11-19 13:22:55 -0500 | [diff] [blame] | 1227 | static int fsl_dma_chan_probe(struct fsldma_device *fdev, |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1228 | struct device_node *node, u32 feature, const char *compatible) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1229 | { |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1230 | struct fsldma_chan *chan; |
Ira Snyder | 4ce0e95 | 2010-01-06 13:34:00 +0000 | [diff] [blame] | 1231 | struct resource res; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1232 | int err; |
| 1233 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1234 | /* alloc channel */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1235 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
| 1236 | if (!chan) { |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1237 | dev_err(fdev->dev, "no free memory for DMA channels!\n"); |
| 1238 | err = -ENOMEM; |
| 1239 | goto out_return; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1240 | } |
| 1241 | |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1242 | /* ioremap registers for use */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1243 | chan->regs = of_iomap(node, 0); |
| 1244 | if (!chan->regs) { |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1245 | dev_err(fdev->dev, "unable to ioremap registers\n"); |
| 1246 | err = -ENOMEM; |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1247 | goto out_free_chan; |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1248 | } |
| 1249 | |
Ira Snyder | 4ce0e95 | 2010-01-06 13:34:00 +0000 | [diff] [blame] | 1250 | err = of_address_to_resource(node, 0, &res); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1251 | if (err) { |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1252 | dev_err(fdev->dev, "unable to find 'reg' property\n"); |
| 1253 | goto out_iounmap_regs; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1254 | } |
| 1255 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1256 | chan->feature = feature; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1257 | if (!fdev->feature) |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1258 | fdev->feature = chan->feature; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1259 | |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1260 | /* |
| 1261 | * If the DMA device's feature is different than the feature |
| 1262 | * of its channels, report the bug |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1263 | */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1264 | WARN_ON(fdev->feature != chan->feature); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1265 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1266 | chan->dev = fdev->dev; |
Hongbo Zhang | 8de7a7d | 2013-09-26 17:33:43 +0800 | [diff] [blame] | 1267 | chan->id = (res.start & 0xfff) < 0x300 ? |
| 1268 | ((res.start - 0x100) & 0xfff) >> 7 : |
| 1269 | ((res.start - 0x200) & 0xfff) >> 7; |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1270 | if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1271 | dev_err(fdev->dev, "too many channels for device\n"); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1272 | err = -EINVAL; |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1273 | goto out_iounmap_regs; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1274 | } |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1275 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1276 | fdev->chan[chan->id] = chan; |
| 1277 | tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); |
Ira Snyder | b158471 | 2011-03-03 07:54:55 +0000 | [diff] [blame] | 1278 | snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id); |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1279 | |
| 1280 | /* Initialize the channel */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1281 | dma_init(chan); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1282 | |
| 1283 | /* Clear cdar registers */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1284 | set_cdar(chan, 0); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1285 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1286 | switch (chan->feature & FSL_DMA_IP_MASK) { |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1287 | case FSL_DMA_IP_85XX: |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1288 | chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1289 | case FSL_DMA_IP_83XX: |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1290 | chan->toggle_ext_start = fsl_chan_toggle_ext_start; |
| 1291 | chan->set_src_loop_size = fsl_chan_set_src_loop_size; |
| 1292 | chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; |
| 1293 | chan->set_request_count = fsl_chan_set_request_count; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1294 | } |
| 1295 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1296 | spin_lock_init(&chan->desc_lock); |
Ira Snyder | 9c3a50b | 2010-01-06 13:34:06 +0000 | [diff] [blame] | 1297 | INIT_LIST_HEAD(&chan->ld_pending); |
| 1298 | INIT_LIST_HEAD(&chan->ld_running); |
Hongbo Zhang | 43452fa | 2014-05-21 16:03:03 +0800 | [diff] [blame] | 1299 | INIT_LIST_HEAD(&chan->ld_completed); |
Ira Snyder | f04cd40 | 2011-03-03 07:54:58 +0000 | [diff] [blame] | 1300 | chan->idle = true; |
Hongbo Zhang | 14c6a33 | 2014-05-21 16:03:02 +0800 | [diff] [blame] | 1301 | #ifdef CONFIG_PM |
| 1302 | chan->pm_state = RUNNING; |
| 1303 | #endif |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1304 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1305 | chan->common.device = &fdev->common; |
Russell King - ARM Linux | 8ac6954 | 2012-03-06 22:36:27 +0000 | [diff] [blame] | 1306 | dma_cookie_init(&chan->common); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1307 | |
Ira Snyder | d3f620b | 2010-01-06 13:34:04 +0000 | [diff] [blame] | 1308 | /* find the IRQ line, if it exists in the device tree */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1309 | chan->irq = irq_of_parse_and_map(node, 0); |
Ira Snyder | d3f620b | 2010-01-06 13:34:04 +0000 | [diff] [blame] | 1310 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1311 | /* Add the channel to DMA device channel list */ |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1312 | list_add_tail(&chan->common.device_node, &fdev->common.channels); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1313 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1314 | dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, |
| 1315 | chan->irq != NO_IRQ ? chan->irq : fdev->irq); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1316 | |
| 1317 | return 0; |
Li Yang | 51ee87f | 2008-05-29 23:25:45 -0700 | [diff] [blame] | 1318 | |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1319 | out_iounmap_regs: |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1320 | iounmap(chan->regs); |
| 1321 | out_free_chan: |
| 1322 | kfree(chan); |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1323 | out_return: |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1324 | return err; |
| 1325 | } |
| 1326 | |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1327 | static void fsl_dma_chan_remove(struct fsldma_chan *chan) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1328 | { |
Ira Snyder | a1c0331 | 2010-01-06 13:34:05 +0000 | [diff] [blame] | 1329 | irq_dispose_mapping(chan->irq); |
| 1330 | list_del(&chan->common.device_node); |
| 1331 | iounmap(chan->regs); |
| 1332 | kfree(chan); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1333 | } |
| 1334 | |
Bill Pemberton | 463a1f8 | 2012-11-19 13:22:55 -0500 | [diff] [blame] | 1335 | static int fsldma_of_probe(struct platform_device *op) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1336 | { |
Ira Snyder | a4f56d4 | 2010-01-06 13:34:01 +0000 | [diff] [blame] | 1337 | struct fsldma_device *fdev; |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1338 | struct device_node *child; |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1339 | int err; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1340 | |
Ira Snyder | a4f56d4 | 2010-01-06 13:34:01 +0000 | [diff] [blame] | 1341 | fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1342 | if (!fdev) { |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1343 | dev_err(&op->dev, "No enough memory for 'priv'\n"); |
| 1344 | err = -ENOMEM; |
| 1345 | goto out_return; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1346 | } |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1347 | |
| 1348 | fdev->dev = &op->dev; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1349 | INIT_LIST_HEAD(&fdev->common.channels); |
| 1350 | |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1351 | /* ioremap the registers for use */ |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 1352 | fdev->regs = of_iomap(op->dev.of_node, 0); |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1353 | if (!fdev->regs) { |
| 1354 | dev_err(&op->dev, "unable to ioremap registers\n"); |
| 1355 | err = -ENOMEM; |
| 1356 | goto out_free_fdev; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1357 | } |
| 1358 | |
Ira Snyder | d3f620b | 2010-01-06 13:34:04 +0000 | [diff] [blame] | 1359 | /* map the channel IRQ if it exists, but don't hookup the handler yet */ |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 1360 | fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
Ira Snyder | d3f620b | 2010-01-06 13:34:04 +0000 | [diff] [blame] | 1361 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1362 | dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); |
Ira Snyder | c1433041 | 2010-09-30 11:46:45 +0000 | [diff] [blame] | 1363 | dma_cap_set(DMA_SG, fdev->common.cap_mask); |
Ira Snyder | bbea0b6 | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 1364 | dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1365 | fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; |
| 1366 | fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1367 | fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; |
Ira Snyder | c1433041 | 2010-09-30 11:46:45 +0000 | [diff] [blame] | 1368 | fdev->common.device_prep_dma_sg = fsl_dma_prep_sg; |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1369 | fdev->common.device_tx_status = fsl_tx_status; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1370 | fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; |
Maxime Ripard | b7f7552 | 2014-11-17 14:42:24 +0100 | [diff] [blame] | 1371 | fdev->common.device_config = fsl_dma_device_config; |
| 1372 | fdev->common.device_terminate_all = fsl_dma_device_terminate_all; |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1373 | fdev->common.dev = &op->dev; |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1374 | |
Kevin Hao | 75dc177 | 2015-01-08 18:38:16 +0800 | [diff] [blame] | 1375 | fdev->common.src_addr_widths = FSL_DMA_BUSWIDTHS; |
| 1376 | fdev->common.dst_addr_widths = FSL_DMA_BUSWIDTHS; |
| 1377 | fdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); |
| 1378 | fdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; |
| 1379 | |
Li Yang | e2c8e425 | 2010-11-11 20:16:29 +0800 | [diff] [blame] | 1380 | dma_set_mask(&(op->dev), DMA_BIT_MASK(36)); |
| 1381 | |
Jingoo Han | dd3daca | 2013-05-24 10:10:13 +0900 | [diff] [blame] | 1382 | platform_set_drvdata(op, fdev); |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1383 | |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1384 | /* |
| 1385 | * We cannot use of_platform_bus_probe() because there is no |
| 1386 | * of_platform_bus_remove(). Instead, we manually instantiate every DMA |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1387 | * channel object. |
| 1388 | */ |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 1389 | for_each_child_of_node(op->dev.of_node, child) { |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1390 | if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1391 | fsl_dma_chan_probe(fdev, child, |
| 1392 | FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, |
| 1393 | "fsl,eloplus-dma-channel"); |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1394 | } |
| 1395 | |
| 1396 | if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1397 | fsl_dma_chan_probe(fdev, child, |
| 1398 | FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, |
| 1399 | "fsl,elo-dma-channel"); |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1400 | } |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1401 | } |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1402 | |
Ira Snyder | d3f620b | 2010-01-06 13:34:04 +0000 | [diff] [blame] | 1403 | /* |
| 1404 | * Hookup the IRQ handler(s) |
| 1405 | * |
| 1406 | * If we have a per-controller interrupt, we prefer that to the |
| 1407 | * per-channel interrupts to reduce the number of shared interrupt |
| 1408 | * handlers on the same IRQ line |
| 1409 | */ |
| 1410 | err = fsldma_request_irqs(fdev); |
| 1411 | if (err) { |
| 1412 | dev_err(fdev->dev, "unable to request IRQs\n"); |
| 1413 | goto out_free_fdev; |
| 1414 | } |
| 1415 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1416 | dma_async_device_register(&fdev->common); |
| 1417 | return 0; |
| 1418 | |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1419 | out_free_fdev: |
Ira Snyder | d3f620b | 2010-01-06 13:34:04 +0000 | [diff] [blame] | 1420 | irq_dispose_mapping(fdev->irq); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1421 | kfree(fdev); |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1422 | out_return: |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1423 | return err; |
| 1424 | } |
| 1425 | |
Grant Likely | 2dc1158 | 2010-08-06 09:25:50 -0600 | [diff] [blame] | 1426 | static int fsldma_of_remove(struct platform_device *op) |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1427 | { |
Ira Snyder | a4f56d4 | 2010-01-06 13:34:01 +0000 | [diff] [blame] | 1428 | struct fsldma_device *fdev; |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1429 | unsigned int i; |
| 1430 | |
Jingoo Han | dd3daca | 2013-05-24 10:10:13 +0900 | [diff] [blame] | 1431 | fdev = platform_get_drvdata(op); |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1432 | dma_async_device_unregister(&fdev->common); |
| 1433 | |
Ira Snyder | d3f620b | 2010-01-06 13:34:04 +0000 | [diff] [blame] | 1434 | fsldma_free_irqs(fdev); |
| 1435 | |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1436 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1437 | if (fdev->chan[i]) |
| 1438 | fsl_dma_chan_remove(fdev->chan[i]); |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1439 | } |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1440 | |
Ira Snyder | e7a2915 | 2010-01-06 13:34:03 +0000 | [diff] [blame] | 1441 | iounmap(fdev->regs); |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1442 | kfree(fdev); |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1443 | |
| 1444 | return 0; |
| 1445 | } |
| 1446 | |
Hongbo Zhang | 14c6a33 | 2014-05-21 16:03:02 +0800 | [diff] [blame] | 1447 | #ifdef CONFIG_PM |
| 1448 | static int fsldma_suspend_late(struct device *dev) |
| 1449 | { |
| 1450 | struct platform_device *pdev = to_platform_device(dev); |
| 1451 | struct fsldma_device *fdev = platform_get_drvdata(pdev); |
| 1452 | struct fsldma_chan *chan; |
| 1453 | int i; |
| 1454 | |
| 1455 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
| 1456 | chan = fdev->chan[i]; |
| 1457 | if (!chan) |
| 1458 | continue; |
| 1459 | |
| 1460 | spin_lock_bh(&chan->desc_lock); |
| 1461 | if (unlikely(!chan->idle)) |
| 1462 | goto out; |
| 1463 | chan->regs_save.mr = get_mr(chan); |
| 1464 | chan->pm_state = SUSPENDED; |
| 1465 | spin_unlock_bh(&chan->desc_lock); |
| 1466 | } |
| 1467 | return 0; |
| 1468 | |
| 1469 | out: |
| 1470 | for (; i >= 0; i--) { |
| 1471 | chan = fdev->chan[i]; |
| 1472 | if (!chan) |
| 1473 | continue; |
| 1474 | chan->pm_state = RUNNING; |
| 1475 | spin_unlock_bh(&chan->desc_lock); |
| 1476 | } |
| 1477 | return -EBUSY; |
| 1478 | } |
| 1479 | |
| 1480 | static int fsldma_resume_early(struct device *dev) |
| 1481 | { |
| 1482 | struct platform_device *pdev = to_platform_device(dev); |
| 1483 | struct fsldma_device *fdev = platform_get_drvdata(pdev); |
| 1484 | struct fsldma_chan *chan; |
| 1485 | u32 mode; |
| 1486 | int i; |
| 1487 | |
| 1488 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
| 1489 | chan = fdev->chan[i]; |
| 1490 | if (!chan) |
| 1491 | continue; |
| 1492 | |
| 1493 | spin_lock_bh(&chan->desc_lock); |
| 1494 | mode = chan->regs_save.mr |
| 1495 | & ~FSL_DMA_MR_CS & ~FSL_DMA_MR_CC & ~FSL_DMA_MR_CA; |
| 1496 | set_mr(chan, mode); |
| 1497 | chan->pm_state = RUNNING; |
| 1498 | spin_unlock_bh(&chan->desc_lock); |
| 1499 | } |
| 1500 | |
| 1501 | return 0; |
| 1502 | } |
| 1503 | |
| 1504 | static const struct dev_pm_ops fsldma_pm_ops = { |
| 1505 | .suspend_late = fsldma_suspend_late, |
| 1506 | .resume_early = fsldma_resume_early, |
| 1507 | }; |
| 1508 | #endif |
| 1509 | |
Márton Németh | 4b1cf1f | 2010-02-02 23:41:06 -0700 | [diff] [blame] | 1510 | static const struct of_device_id fsldma_of_ids[] = { |
Hongbo Zhang | 8de7a7d | 2013-09-26 17:33:43 +0800 | [diff] [blame] | 1511 | { .compatible = "fsl,elo3-dma", }, |
Kumar Gala | 049c9d4 | 2008-03-31 11:13:21 -0500 | [diff] [blame] | 1512 | { .compatible = "fsl,eloplus-dma", }, |
| 1513 | { .compatible = "fsl,elo-dma", }, |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1514 | {} |
| 1515 | }; |
Luis de Bethencourt | 7522c24 | 2015-09-16 22:57:17 +0200 | [diff] [blame] | 1516 | MODULE_DEVICE_TABLE(of, fsldma_of_ids); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1517 | |
Ira W. Snyder | 8faa7cf | 2011-04-07 10:33:03 -0700 | [diff] [blame] | 1518 | static struct platform_driver fsldma_of_driver = { |
Grant Likely | 4018294 | 2010-04-13 16:13:02 -0700 | [diff] [blame] | 1519 | .driver = { |
| 1520 | .name = "fsl-elo-dma", |
Grant Likely | 4018294 | 2010-04-13 16:13:02 -0700 | [diff] [blame] | 1521 | .of_match_table = fsldma_of_ids, |
Hongbo Zhang | 14c6a33 | 2014-05-21 16:03:02 +0800 | [diff] [blame] | 1522 | #ifdef CONFIG_PM |
| 1523 | .pm = &fsldma_pm_ops, |
| 1524 | #endif |
Grant Likely | 4018294 | 2010-04-13 16:13:02 -0700 | [diff] [blame] | 1525 | }, |
| 1526 | .probe = fsldma_of_probe, |
| 1527 | .remove = fsldma_of_remove, |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1528 | }; |
| 1529 | |
Ira Snyder | a4f56d4 | 2010-01-06 13:34:01 +0000 | [diff] [blame] | 1530 | /*----------------------------------------------------------------------------*/ |
| 1531 | /* Module Init / Exit */ |
| 1532 | /*----------------------------------------------------------------------------*/ |
| 1533 | |
| 1534 | static __init int fsldma_init(void) |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1535 | { |
Hongbo Zhang | 8de7a7d | 2013-09-26 17:33:43 +0800 | [diff] [blame] | 1536 | pr_info("Freescale Elo series DMA driver\n"); |
Grant Likely | 0000612 | 2011-02-22 19:59:54 -0700 | [diff] [blame] | 1537 | return platform_driver_register(&fsldma_of_driver); |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 1538 | } |
| 1539 | |
Ira Snyder | a4f56d4 | 2010-01-06 13:34:01 +0000 | [diff] [blame] | 1540 | static void __exit fsldma_exit(void) |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1541 | { |
Grant Likely | 0000612 | 2011-02-22 19:59:54 -0700 | [diff] [blame] | 1542 | platform_driver_unregister(&fsldma_of_driver); |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1543 | } |
| 1544 | |
Ira Snyder | a4f56d4 | 2010-01-06 13:34:01 +0000 | [diff] [blame] | 1545 | subsys_initcall(fsldma_init); |
| 1546 | module_exit(fsldma_exit); |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1547 | |
Hongbo Zhang | 8de7a7d | 2013-09-26 17:33:43 +0800 | [diff] [blame] | 1548 | MODULE_DESCRIPTION("Freescale Elo series DMA driver"); |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 1549 | MODULE_LICENSE("GPL"); |