Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Emilio López |
| 3 | * |
| 4 | * Emilio López <emilio@elopez.com.ar> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/clk-provider.h> |
| 18 | #include <linux/clkdev.h> |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 19 | #include <linux/of.h> |
| 20 | #include <linux/of_address.h> |
Hans de Goede | cfb0086 | 2014-02-07 16:21:49 +0100 | [diff] [blame] | 21 | #include <linux/reset-controller.h> |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 22 | |
| 23 | #include "clk-factors.h" |
| 24 | |
| 25 | static DEFINE_SPINLOCK(clk_lock); |
| 26 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 27 | /* Maximum number of parents our clocks have */ |
| 28 | #define SUNXI_MAX_PARENTS 5 |
| 29 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 30 | /** |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 31 | * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1 |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 32 | * PLL1 rate is calculated as follows |
| 33 | * rate = (parent_rate * n * (k + 1) >> p) / (m + 1); |
| 34 | * parent_rate is always 24Mhz |
| 35 | */ |
| 36 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 37 | static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 38 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 39 | { |
| 40 | u8 div; |
| 41 | |
| 42 | /* Normalize value to a 6M multiple */ |
| 43 | div = *freq / 6000000; |
| 44 | *freq = 6000000 * div; |
| 45 | |
| 46 | /* we were called to round the frequency, we can now return */ |
| 47 | if (n == NULL) |
| 48 | return; |
| 49 | |
| 50 | /* m is always zero for pll1 */ |
| 51 | *m = 0; |
| 52 | |
| 53 | /* k is 1 only on these cases */ |
| 54 | if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000) |
| 55 | *k = 1; |
| 56 | else |
| 57 | *k = 0; |
| 58 | |
| 59 | /* p will be 3 for divs under 10 */ |
| 60 | if (div < 10) |
| 61 | *p = 3; |
| 62 | |
| 63 | /* p will be 2 for divs between 10 - 20 and odd divs under 32 */ |
| 64 | else if (div < 20 || (div < 32 && (div & 1))) |
| 65 | *p = 2; |
| 66 | |
| 67 | /* p will be 1 for even divs under 32, divs under 40 and odd pairs |
| 68 | * of divs between 40-62 */ |
| 69 | else if (div < 40 || (div < 64 && (div & 2))) |
| 70 | *p = 1; |
| 71 | |
| 72 | /* any other entries have p = 0 */ |
| 73 | else |
| 74 | *p = 0; |
| 75 | |
| 76 | /* calculate a suitable n based on k and p */ |
| 77 | div <<= *p; |
| 78 | div /= (*k + 1); |
| 79 | *n = div / 4; |
| 80 | } |
| 81 | |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 82 | /** |
| 83 | * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1 |
| 84 | * PLL1 rate is calculated as follows |
| 85 | * rate = parent_rate * (n + 1) * (k + 1) / (m + 1); |
| 86 | * parent_rate should always be 24MHz |
| 87 | */ |
| 88 | static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate, |
| 89 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 90 | { |
| 91 | /* |
| 92 | * We can operate only on MHz, this will make our life easier |
| 93 | * later. |
| 94 | */ |
| 95 | u32 freq_mhz = *freq / 1000000; |
| 96 | u32 parent_freq_mhz = parent_rate / 1000000; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 97 | |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 98 | /* |
| 99 | * Round down the frequency to the closest multiple of either |
| 100 | * 6 or 16 |
| 101 | */ |
| 102 | u32 round_freq_6 = round_down(freq_mhz, 6); |
| 103 | u32 round_freq_16 = round_down(freq_mhz, 16); |
| 104 | |
| 105 | if (round_freq_6 > round_freq_16) |
| 106 | freq_mhz = round_freq_6; |
| 107 | else |
| 108 | freq_mhz = round_freq_16; |
| 109 | |
| 110 | *freq = freq_mhz * 1000000; |
| 111 | |
| 112 | /* |
| 113 | * If the factors pointer are null, we were just called to |
| 114 | * round down the frequency. |
| 115 | * Exit. |
| 116 | */ |
| 117 | if (n == NULL) |
| 118 | return; |
| 119 | |
| 120 | /* If the frequency is a multiple of 32 MHz, k is always 3 */ |
| 121 | if (!(freq_mhz % 32)) |
| 122 | *k = 3; |
| 123 | /* If the frequency is a multiple of 9 MHz, k is always 2 */ |
| 124 | else if (!(freq_mhz % 9)) |
| 125 | *k = 2; |
| 126 | /* If the frequency is a multiple of 8 MHz, k is always 1 */ |
| 127 | else if (!(freq_mhz % 8)) |
| 128 | *k = 1; |
| 129 | /* Otherwise, we don't use the k factor */ |
| 130 | else |
| 131 | *k = 0; |
| 132 | |
| 133 | /* |
| 134 | * If the frequency is a multiple of 2 but not a multiple of |
| 135 | * 3, m is 3. This is the first time we use 6 here, yet we |
| 136 | * will use it on several other places. |
| 137 | * We use this number because it's the lowest frequency we can |
| 138 | * generate (with n = 0, k = 0, m = 3), so every other frequency |
| 139 | * somehow relates to this frequency. |
| 140 | */ |
| 141 | if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4) |
| 142 | *m = 2; |
| 143 | /* |
| 144 | * If the frequency is a multiple of 6MHz, but the factor is |
| 145 | * odd, m will be 3 |
| 146 | */ |
| 147 | else if ((freq_mhz / 6) & 1) |
| 148 | *m = 3; |
| 149 | /* Otherwise, we end up with m = 1 */ |
| 150 | else |
| 151 | *m = 1; |
| 152 | |
| 153 | /* Calculate n thanks to the above factors we already got */ |
| 154 | *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1; |
| 155 | |
| 156 | /* |
| 157 | * If n end up being outbound, and that we can still decrease |
| 158 | * m, do it. |
| 159 | */ |
| 160 | if ((*n + 1) > 31 && (*m + 1) > 1) { |
| 161 | *n = (*n + 1) / 2 - 1; |
| 162 | *m = (*m + 1) / 2 - 1; |
| 163 | } |
| 164 | } |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 165 | |
| 166 | /** |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 167 | * sun4i_get_pll5_factors() - calculates n, k factors for PLL5 |
| 168 | * PLL5 rate is calculated as follows |
| 169 | * rate = parent_rate * n * (k + 1) |
| 170 | * parent_rate is always 24Mhz |
| 171 | */ |
| 172 | |
| 173 | static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate, |
| 174 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 175 | { |
| 176 | u8 div; |
| 177 | |
| 178 | /* Normalize value to a parent_rate multiple (24M) */ |
| 179 | div = *freq / parent_rate; |
| 180 | *freq = parent_rate * div; |
| 181 | |
| 182 | /* we were called to round the frequency, we can now return */ |
| 183 | if (n == NULL) |
| 184 | return; |
| 185 | |
| 186 | if (div < 31) |
| 187 | *k = 0; |
| 188 | else if (div / 2 < 31) |
| 189 | *k = 1; |
| 190 | else if (div / 3 < 31) |
| 191 | *k = 2; |
| 192 | else |
| 193 | *k = 3; |
| 194 | |
| 195 | *n = DIV_ROUND_UP(div, (*k+1)); |
| 196 | } |
| 197 | |
Maxime Ripard | 92ef67c | 2014-02-05 14:05:03 +0100 | [diff] [blame] | 198 | /** |
| 199 | * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6 |
| 200 | * PLL6 rate is calculated as follows |
| 201 | * rate = parent_rate * n * (k + 1) / 2 |
| 202 | * parent_rate is always 24Mhz |
| 203 | */ |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 204 | |
Maxime Ripard | 92ef67c | 2014-02-05 14:05:03 +0100 | [diff] [blame] | 205 | static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate, |
| 206 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 207 | { |
| 208 | u8 div; |
| 209 | |
| 210 | /* |
| 211 | * We always have 24MHz / 2, so we can just say that our |
| 212 | * parent clock is 12MHz. |
| 213 | */ |
| 214 | parent_rate = parent_rate / 2; |
| 215 | |
| 216 | /* Normalize value to a parent_rate multiple (24M / 2) */ |
| 217 | div = *freq / parent_rate; |
| 218 | *freq = parent_rate * div; |
| 219 | |
| 220 | /* we were called to round the frequency, we can now return */ |
| 221 | if (n == NULL) |
| 222 | return; |
| 223 | |
| 224 | *k = div / 32; |
| 225 | if (*k > 3) |
| 226 | *k = 3; |
| 227 | |
| 228 | *n = DIV_ROUND_UP(div, (*k+1)); |
| 229 | } |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 230 | |
| 231 | /** |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 232 | * sun4i_get_apb1_factors() - calculates m, p factors for APB1 |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 233 | * APB1 rate is calculated as follows |
| 234 | * rate = (parent_rate >> p) / (m + 1); |
| 235 | */ |
| 236 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 237 | static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 238 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 239 | { |
| 240 | u8 calcm, calcp; |
| 241 | |
| 242 | if (parent_rate < *freq) |
| 243 | *freq = parent_rate; |
| 244 | |
Emilio López | 2226013 | 2014-03-19 15:19:32 -0300 | [diff] [blame] | 245 | parent_rate = DIV_ROUND_UP(parent_rate, *freq); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 246 | |
| 247 | /* Invalid rate! */ |
| 248 | if (parent_rate > 32) |
| 249 | return; |
| 250 | |
| 251 | if (parent_rate <= 4) |
| 252 | calcp = 0; |
| 253 | else if (parent_rate <= 8) |
| 254 | calcp = 1; |
| 255 | else if (parent_rate <= 16) |
| 256 | calcp = 2; |
| 257 | else |
| 258 | calcp = 3; |
| 259 | |
| 260 | calcm = (parent_rate >> calcp) - 1; |
| 261 | |
| 262 | *freq = (parent_rate >> calcp) / (calcm + 1); |
| 263 | |
| 264 | /* we were called to round the frequency, we can now return */ |
| 265 | if (n == NULL) |
| 266 | return; |
| 267 | |
| 268 | *m = calcm; |
| 269 | *p = calcp; |
| 270 | } |
| 271 | |
| 272 | |
| 273 | |
| 274 | /** |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 275 | * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks |
Emilio López | 9ce71ca | 2014-03-19 15:19:33 -0300 | [diff] [blame] | 276 | * MOD0 rate is calculated as follows |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 277 | * rate = (parent_rate >> p) / (m + 1); |
| 278 | */ |
| 279 | |
| 280 | static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate, |
| 281 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 282 | { |
| 283 | u8 div, calcm, calcp; |
| 284 | |
| 285 | /* These clocks can only divide, so we will never be able to achieve |
| 286 | * frequencies higher than the parent frequency */ |
| 287 | if (*freq > parent_rate) |
| 288 | *freq = parent_rate; |
| 289 | |
Emilio López | 2226013 | 2014-03-19 15:19:32 -0300 | [diff] [blame] | 290 | div = DIV_ROUND_UP(parent_rate, *freq); |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 291 | |
| 292 | if (div < 16) |
| 293 | calcp = 0; |
| 294 | else if (div / 2 < 16) |
| 295 | calcp = 1; |
| 296 | else if (div / 4 < 16) |
| 297 | calcp = 2; |
| 298 | else |
| 299 | calcp = 3; |
| 300 | |
| 301 | calcm = DIV_ROUND_UP(div, 1 << calcp); |
| 302 | |
| 303 | *freq = (parent_rate >> calcp) / calcm; |
| 304 | |
| 305 | /* we were called to round the frequency, we can now return */ |
| 306 | if (n == NULL) |
| 307 | return; |
| 308 | |
| 309 | *m = calcm - 1; |
| 310 | *p = calcp; |
| 311 | } |
| 312 | |
| 313 | |
| 314 | |
| 315 | /** |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 316 | * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B |
| 317 | * CLK_OUT rate is calculated as follows |
| 318 | * rate = (parent_rate >> p) / (m + 1); |
| 319 | */ |
| 320 | |
| 321 | static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate, |
| 322 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 323 | { |
| 324 | u8 div, calcm, calcp; |
| 325 | |
| 326 | /* These clocks can only divide, so we will never be able to achieve |
| 327 | * frequencies higher than the parent frequency */ |
| 328 | if (*freq > parent_rate) |
| 329 | *freq = parent_rate; |
| 330 | |
Emilio López | 2226013 | 2014-03-19 15:19:32 -0300 | [diff] [blame] | 331 | div = DIV_ROUND_UP(parent_rate, *freq); |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 332 | |
| 333 | if (div < 32) |
| 334 | calcp = 0; |
| 335 | else if (div / 2 < 32) |
| 336 | calcp = 1; |
| 337 | else if (div / 4 < 32) |
| 338 | calcp = 2; |
| 339 | else |
| 340 | calcp = 3; |
| 341 | |
| 342 | calcm = DIV_ROUND_UP(div, 1 << calcp); |
| 343 | |
| 344 | *freq = (parent_rate >> calcp) / calcm; |
| 345 | |
| 346 | /* we were called to round the frequency, we can now return */ |
| 347 | if (n == NULL) |
| 348 | return; |
| 349 | |
| 350 | *m = calcm - 1; |
| 351 | *p = calcp; |
| 352 | } |
| 353 | |
Chen-Yu Tsai | e4c6d6c | 2014-02-10 18:35:47 +0800 | [diff] [blame] | 354 | /** |
Emilio López | 9571397 | 2014-05-02 17:57:16 +0200 | [diff] [blame] | 355 | * clk_sunxi_mmc_phase_control() - configures MMC clock phase control |
| 356 | */ |
| 357 | |
Hans de Goede | a97181a | 2014-05-12 14:04:47 +0200 | [diff] [blame] | 358 | void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output) |
Emilio López | 9571397 | 2014-05-02 17:57:16 +0200 | [diff] [blame] | 359 | { |
| 360 | #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) |
| 361 | #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw) |
| 362 | |
Hans de Goede | a97181a | 2014-05-12 14:04:47 +0200 | [diff] [blame] | 363 | struct clk_hw *hw = __clk_get_hw(clk); |
Emilio López | 9571397 | 2014-05-02 17:57:16 +0200 | [diff] [blame] | 364 | struct clk_composite *composite = to_clk_composite(hw); |
| 365 | struct clk_hw *rate_hw = composite->rate_hw; |
| 366 | struct clk_factors *factors = to_clk_factors(rate_hw); |
| 367 | unsigned long flags = 0; |
| 368 | u32 reg; |
| 369 | |
| 370 | if (factors->lock) |
| 371 | spin_lock_irqsave(factors->lock, flags); |
| 372 | |
| 373 | reg = readl(factors->reg); |
| 374 | |
| 375 | /* set sample clock phase control */ |
| 376 | reg &= ~(0x7 << 20); |
| 377 | reg |= ((sample & 0x7) << 20); |
| 378 | |
| 379 | /* set output clock phase control */ |
| 380 | reg &= ~(0x7 << 8); |
| 381 | reg |= ((output & 0x7) << 8); |
| 382 | |
| 383 | writel(reg, factors->reg); |
| 384 | |
| 385 | if (factors->lock) |
| 386 | spin_unlock_irqrestore(factors->lock, flags); |
| 387 | } |
| 388 | EXPORT_SYMBOL(clk_sunxi_mmc_phase_control); |
| 389 | |
| 390 | |
| 391 | /** |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 392 | * sunxi_factors_clk_setup() - Setup function for factor clocks |
| 393 | */ |
| 394 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 395 | #define SUNXI_FACTORS_MUX_MASK 0x3 |
| 396 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 397 | struct factors_data { |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 398 | int enable; |
| 399 | int mux; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 400 | struct clk_factors_config *table; |
| 401 | void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p); |
Chen-Yu Tsai | 667f542 | 2014-02-03 09:51:39 +0800 | [diff] [blame] | 402 | const char *name; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 403 | }; |
| 404 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 405 | static struct clk_factors_config sun4i_pll1_config = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 406 | .nshift = 8, |
| 407 | .nwidth = 5, |
| 408 | .kshift = 4, |
| 409 | .kwidth = 2, |
| 410 | .mshift = 0, |
| 411 | .mwidth = 2, |
| 412 | .pshift = 16, |
| 413 | .pwidth = 2, |
| 414 | }; |
| 415 | |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 416 | static struct clk_factors_config sun6i_a31_pll1_config = { |
| 417 | .nshift = 8, |
| 418 | .nwidth = 5, |
| 419 | .kshift = 4, |
| 420 | .kwidth = 2, |
| 421 | .mshift = 0, |
| 422 | .mwidth = 2, |
| 423 | }; |
| 424 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 425 | static struct clk_factors_config sun4i_pll5_config = { |
| 426 | .nshift = 8, |
| 427 | .nwidth = 5, |
| 428 | .kshift = 4, |
| 429 | .kwidth = 2, |
| 430 | }; |
| 431 | |
Maxime Ripard | 92ef67c | 2014-02-05 14:05:03 +0100 | [diff] [blame] | 432 | static struct clk_factors_config sun6i_a31_pll6_config = { |
| 433 | .nshift = 8, |
| 434 | .nwidth = 5, |
| 435 | .kshift = 4, |
| 436 | .kwidth = 2, |
| 437 | }; |
| 438 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 439 | static struct clk_factors_config sun4i_apb1_config = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 440 | .mshift = 0, |
| 441 | .mwidth = 5, |
| 442 | .pshift = 16, |
| 443 | .pwidth = 2, |
| 444 | }; |
| 445 | |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 446 | /* user manual says "n" but it's really "p" */ |
| 447 | static struct clk_factors_config sun4i_mod0_config = { |
| 448 | .mshift = 0, |
| 449 | .mwidth = 4, |
| 450 | .pshift = 16, |
| 451 | .pwidth = 2, |
| 452 | }; |
| 453 | |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 454 | /* user manual says "n" but it's really "p" */ |
| 455 | static struct clk_factors_config sun7i_a20_out_config = { |
| 456 | .mshift = 8, |
| 457 | .mwidth = 5, |
| 458 | .pshift = 20, |
| 459 | .pwidth = 2, |
| 460 | }; |
| 461 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 462 | static const struct factors_data sun4i_pll1_data __initconst = { |
Emilio López | d838ff3 | 2013-12-23 00:32:34 -0300 | [diff] [blame] | 463 | .enable = 31, |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 464 | .table = &sun4i_pll1_config, |
| 465 | .getter = sun4i_get_pll1_factors, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 466 | }; |
| 467 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 468 | static const struct factors_data sun6i_a31_pll1_data __initconst = { |
Emilio López | d838ff3 | 2013-12-23 00:32:34 -0300 | [diff] [blame] | 469 | .enable = 31, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 470 | .table = &sun6i_a31_pll1_config, |
| 471 | .getter = sun6i_a31_get_pll1_factors, |
| 472 | }; |
| 473 | |
Emilio López | 5a8ddf2 | 2014-03-19 15:19:30 -0300 | [diff] [blame] | 474 | static const struct factors_data sun7i_a20_pll4_data __initconst = { |
| 475 | .enable = 31, |
| 476 | .table = &sun4i_pll5_config, |
| 477 | .getter = sun4i_get_pll5_factors, |
| 478 | }; |
| 479 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 480 | static const struct factors_data sun4i_pll5_data __initconst = { |
| 481 | .enable = 31, |
| 482 | .table = &sun4i_pll5_config, |
| 483 | .getter = sun4i_get_pll5_factors, |
Chen-Yu Tsai | 667f542 | 2014-02-03 09:51:39 +0800 | [diff] [blame] | 484 | .name = "pll5", |
| 485 | }; |
| 486 | |
| 487 | static const struct factors_data sun4i_pll6_data __initconst = { |
| 488 | .enable = 31, |
| 489 | .table = &sun4i_pll5_config, |
| 490 | .getter = sun4i_get_pll5_factors, |
| 491 | .name = "pll6", |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 492 | }; |
| 493 | |
Maxime Ripard | 92ef67c | 2014-02-05 14:05:03 +0100 | [diff] [blame] | 494 | static const struct factors_data sun6i_a31_pll6_data __initconst = { |
| 495 | .enable = 31, |
| 496 | .table = &sun6i_a31_pll6_config, |
| 497 | .getter = sun6i_a31_get_pll6_factors, |
| 498 | }; |
| 499 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 500 | static const struct factors_data sun4i_apb1_data __initconst = { |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 501 | .table = &sun4i_apb1_config, |
| 502 | .getter = sun4i_get_apb1_factors, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 503 | }; |
| 504 | |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 505 | static const struct factors_data sun4i_mod0_data __initconst = { |
| 506 | .enable = 31, |
| 507 | .mux = 24, |
| 508 | .table = &sun4i_mod0_config, |
| 509 | .getter = sun4i_get_mod0_factors, |
| 510 | }; |
| 511 | |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 512 | static const struct factors_data sun7i_a20_out_data __initconst = { |
| 513 | .enable = 31, |
| 514 | .mux = 24, |
| 515 | .table = &sun7i_a20_out_config, |
| 516 | .getter = sun7i_a20_get_out_factors, |
| 517 | }; |
| 518 | |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 519 | static struct clk * __init sunxi_factors_clk_setup(struct device_node *node, |
| 520 | const struct factors_data *data) |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 521 | { |
| 522 | struct clk *clk; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 523 | struct clk_factors *factors; |
| 524 | struct clk_gate *gate = NULL; |
| 525 | struct clk_mux *mux = NULL; |
| 526 | struct clk_hw *gate_hw = NULL; |
| 527 | struct clk_hw *mux_hw = NULL; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 528 | const char *clk_name = node->name; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 529 | const char *parents[SUNXI_MAX_PARENTS]; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 530 | void *reg; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 531 | int i = 0; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 532 | |
| 533 | reg = of_iomap(node, 0); |
| 534 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 535 | /* if we have a mux, we will have >1 parents */ |
| 536 | while (i < SUNXI_MAX_PARENTS && |
| 537 | (parents[i] = of_clk_get_parent_name(node, i)) != NULL) |
| 538 | i++; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 539 | |
Chen-Yu Tsai | 667f542 | 2014-02-03 09:51:39 +0800 | [diff] [blame] | 540 | /* |
| 541 | * some factor clocks, such as pll5 and pll6, may have multiple |
| 542 | * outputs, and have their name designated in factors_data |
| 543 | */ |
| 544 | if (data->name) |
| 545 | clk_name = data->name; |
| 546 | else |
| 547 | of_property_read_string(node, "clock-output-names", &clk_name); |
Emilio López | 76192dc | 2013-12-23 00:32:40 -0300 | [diff] [blame] | 548 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 549 | factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL); |
| 550 | if (!factors) |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 551 | return NULL; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 552 | |
| 553 | /* Add a gate if this factor clock can be gated */ |
| 554 | if (data->enable) { |
| 555 | gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); |
| 556 | if (!gate) { |
| 557 | kfree(factors); |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 558 | return NULL; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 559 | } |
| 560 | |
| 561 | /* set up gate properties */ |
| 562 | gate->reg = reg; |
| 563 | gate->bit_idx = data->enable; |
| 564 | gate->lock = &clk_lock; |
| 565 | gate_hw = &gate->hw; |
| 566 | } |
| 567 | |
| 568 | /* Add a mux if this factor clock can be muxed */ |
| 569 | if (data->mux) { |
| 570 | mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); |
| 571 | if (!mux) { |
| 572 | kfree(factors); |
| 573 | kfree(gate); |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 574 | return NULL; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 575 | } |
| 576 | |
| 577 | /* set up gate properties */ |
| 578 | mux->reg = reg; |
| 579 | mux->shift = data->mux; |
| 580 | mux->mask = SUNXI_FACTORS_MUX_MASK; |
| 581 | mux->lock = &clk_lock; |
| 582 | mux_hw = &mux->hw; |
| 583 | } |
| 584 | |
| 585 | /* set up factors properties */ |
| 586 | factors->reg = reg; |
| 587 | factors->config = data->table; |
| 588 | factors->get_factors = data->getter; |
| 589 | factors->lock = &clk_lock; |
| 590 | |
| 591 | clk = clk_register_composite(NULL, clk_name, |
| 592 | parents, i, |
| 593 | mux_hw, &clk_mux_ops, |
| 594 | &factors->hw, &clk_factors_ops, |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 595 | gate_hw, &clk_gate_ops, 0); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 596 | |
Axel Lin | ee85e9b | 2013-07-12 16:15:15 +0800 | [diff] [blame] | 597 | if (!IS_ERR(clk)) { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 598 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 599 | clk_register_clkdev(clk, clk_name, NULL); |
| 600 | } |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 601 | |
| 602 | return clk; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 603 | } |
| 604 | |
| 605 | |
| 606 | |
| 607 | /** |
| 608 | * sunxi_mux_clk_setup() - Setup function for muxes |
| 609 | */ |
| 610 | |
| 611 | #define SUNXI_MUX_GATE_WIDTH 2 |
| 612 | |
| 613 | struct mux_data { |
| 614 | u8 shift; |
| 615 | }; |
| 616 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 617 | static const struct mux_data sun4i_cpu_mux_data __initconst = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 618 | .shift = 16, |
| 619 | }; |
| 620 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 621 | static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 622 | .shift = 12, |
| 623 | }; |
| 624 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 625 | static const struct mux_data sun4i_apb1_mux_data __initconst = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 626 | .shift = 24, |
| 627 | }; |
| 628 | |
| 629 | static void __init sunxi_mux_clk_setup(struct device_node *node, |
| 630 | struct mux_data *data) |
| 631 | { |
| 632 | struct clk *clk; |
| 633 | const char *clk_name = node->name; |
Emilio López | edaf3fb | 2013-12-23 00:32:33 -0300 | [diff] [blame] | 634 | const char *parents[SUNXI_MAX_PARENTS]; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 635 | void *reg; |
| 636 | int i = 0; |
| 637 | |
| 638 | reg = of_iomap(node, 0); |
| 639 | |
Emilio López | edaf3fb | 2013-12-23 00:32:33 -0300 | [diff] [blame] | 640 | while (i < SUNXI_MAX_PARENTS && |
| 641 | (parents[i] = of_clk_get_parent_name(node, i)) != NULL) |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 642 | i++; |
| 643 | |
Chen-Yu Tsai | f64111e | 2014-02-03 09:51:37 +0800 | [diff] [blame] | 644 | of_property_read_string(node, "clock-output-names", &clk_name); |
| 645 | |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 646 | clk = clk_register_mux(NULL, clk_name, parents, i, |
| 647 | CLK_SET_RATE_NO_REPARENT, reg, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 648 | data->shift, SUNXI_MUX_GATE_WIDTH, |
| 649 | 0, &clk_lock); |
| 650 | |
| 651 | if (clk) { |
| 652 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 653 | clk_register_clkdev(clk, clk_name, NULL); |
| 654 | } |
| 655 | } |
| 656 | |
| 657 | |
| 658 | |
| 659 | /** |
| 660 | * sunxi_divider_clk_setup() - Setup function for simple divider clocks |
| 661 | */ |
| 662 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 663 | struct div_data { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 664 | u8 shift; |
| 665 | u8 pow; |
| 666 | u8 width; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 667 | }; |
| 668 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 669 | static const struct div_data sun4i_axi_data __initconst = { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 670 | .shift = 0, |
| 671 | .pow = 0, |
| 672 | .width = 2, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 673 | }; |
| 674 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 675 | static const struct div_data sun4i_ahb_data __initconst = { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 676 | .shift = 4, |
| 677 | .pow = 1, |
| 678 | .width = 2, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 679 | }; |
| 680 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 681 | static const struct div_data sun4i_apb0_data __initconst = { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 682 | .shift = 8, |
| 683 | .pow = 1, |
| 684 | .width = 2, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 685 | }; |
| 686 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 687 | static const struct div_data sun6i_a31_apb2_div_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 688 | .shift = 0, |
| 689 | .pow = 0, |
| 690 | .width = 4, |
| 691 | }; |
| 692 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 693 | static void __init sunxi_divider_clk_setup(struct device_node *node, |
| 694 | struct div_data *data) |
| 695 | { |
| 696 | struct clk *clk; |
| 697 | const char *clk_name = node->name; |
| 698 | const char *clk_parent; |
| 699 | void *reg; |
| 700 | |
| 701 | reg = of_iomap(node, 0); |
| 702 | |
| 703 | clk_parent = of_clk_get_parent_name(node, 0); |
| 704 | |
Chen-Yu Tsai | f64111e | 2014-02-03 09:51:37 +0800 | [diff] [blame] | 705 | of_property_read_string(node, "clock-output-names", &clk_name); |
| 706 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 707 | clk = clk_register_divider(NULL, clk_name, clk_parent, 0, |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 708 | reg, data->shift, data->width, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 709 | data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0, |
| 710 | &clk_lock); |
| 711 | if (clk) { |
| 712 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 713 | clk_register_clkdev(clk, clk_name, NULL); |
| 714 | } |
| 715 | } |
| 716 | |
| 717 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 718 | |
| 719 | /** |
Hans de Goede | cfb0086 | 2014-02-07 16:21:49 +0100 | [diff] [blame] | 720 | * sunxi_gates_reset... - reset bits in leaf gate clk registers handling |
| 721 | */ |
| 722 | |
| 723 | struct gates_reset_data { |
| 724 | void __iomem *reg; |
| 725 | spinlock_t *lock; |
| 726 | struct reset_controller_dev rcdev; |
| 727 | }; |
| 728 | |
| 729 | static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev, |
| 730 | unsigned long id) |
| 731 | { |
| 732 | struct gates_reset_data *data = container_of(rcdev, |
| 733 | struct gates_reset_data, |
| 734 | rcdev); |
| 735 | unsigned long flags; |
| 736 | u32 reg; |
| 737 | |
| 738 | spin_lock_irqsave(data->lock, flags); |
| 739 | |
| 740 | reg = readl(data->reg); |
| 741 | writel(reg & ~BIT(id), data->reg); |
| 742 | |
| 743 | spin_unlock_irqrestore(data->lock, flags); |
| 744 | |
| 745 | return 0; |
| 746 | } |
| 747 | |
| 748 | static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev, |
| 749 | unsigned long id) |
| 750 | { |
| 751 | struct gates_reset_data *data = container_of(rcdev, |
| 752 | struct gates_reset_data, |
| 753 | rcdev); |
| 754 | unsigned long flags; |
| 755 | u32 reg; |
| 756 | |
| 757 | spin_lock_irqsave(data->lock, flags); |
| 758 | |
| 759 | reg = readl(data->reg); |
| 760 | writel(reg | BIT(id), data->reg); |
| 761 | |
| 762 | spin_unlock_irqrestore(data->lock, flags); |
| 763 | |
| 764 | return 0; |
| 765 | } |
| 766 | |
| 767 | static struct reset_control_ops sunxi_gates_reset_ops = { |
| 768 | .assert = sunxi_gates_reset_assert, |
| 769 | .deassert = sunxi_gates_reset_deassert, |
| 770 | }; |
| 771 | |
| 772 | /** |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 773 | * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks |
| 774 | */ |
| 775 | |
| 776 | #define SUNXI_GATES_MAX_SIZE 64 |
| 777 | |
| 778 | struct gates_data { |
| 779 | DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE); |
Hans de Goede | cfb0086 | 2014-02-07 16:21:49 +0100 | [diff] [blame] | 780 | u32 reset_mask; |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 781 | }; |
| 782 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 783 | static const struct gates_data sun4i_axi_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 784 | .mask = {1}, |
| 785 | }; |
| 786 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 787 | static const struct gates_data sun4i_ahb_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 788 | .mask = {0x7F77FFF, 0x14FB3F}, |
| 789 | }; |
| 790 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 791 | static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = { |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 792 | .mask = {0x147667e7, 0x185915}, |
| 793 | }; |
| 794 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 795 | static const struct gates_data sun5i_a13_ahb_gates_data __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 796 | .mask = {0x107067e7, 0x185111}, |
| 797 | }; |
| 798 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 799 | static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 800 | .mask = {0xEDFE7F62, 0x794F931}, |
| 801 | }; |
| 802 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 803 | static const struct gates_data sun7i_a20_ahb_gates_data __initconst = { |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 804 | .mask = { 0x12f77fff, 0x16ff3f }, |
| 805 | }; |
| 806 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 807 | static const struct gates_data sun4i_apb0_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 808 | .mask = {0x4EF}, |
| 809 | }; |
| 810 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 811 | static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = { |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 812 | .mask = {0x469}, |
| 813 | }; |
| 814 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 815 | static const struct gates_data sun5i_a13_apb0_gates_data __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 816 | .mask = {0x61}, |
| 817 | }; |
| 818 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 819 | static const struct gates_data sun7i_a20_apb0_gates_data __initconst = { |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 820 | .mask = { 0x4ff }, |
| 821 | }; |
| 822 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 823 | static const struct gates_data sun4i_apb1_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 824 | .mask = {0xFF00F7}, |
| 825 | }; |
| 826 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 827 | static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = { |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 828 | .mask = {0xf0007}, |
| 829 | }; |
| 830 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 831 | static const struct gates_data sun5i_a13_apb1_gates_data __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 832 | .mask = {0xa0007}, |
| 833 | }; |
| 834 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 835 | static const struct gates_data sun6i_a31_apb1_gates_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 836 | .mask = {0x3031}, |
| 837 | }; |
| 838 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 839 | static const struct gates_data sun6i_a31_apb2_gates_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 840 | .mask = {0x3F000F}, |
| 841 | }; |
| 842 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 843 | static const struct gates_data sun7i_a20_apb1_gates_data __initconst = { |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 844 | .mask = { 0xff80ff }, |
| 845 | }; |
| 846 | |
Roman Byshko | 5abdbf2 | 2014-02-07 16:21:50 +0100 | [diff] [blame] | 847 | static const struct gates_data sun4i_a10_usb_gates_data __initconst = { |
| 848 | .mask = {0x1C0}, |
| 849 | .reset_mask = 0x07, |
| 850 | }; |
| 851 | |
| 852 | static const struct gates_data sun5i_a13_usb_gates_data __initconst = { |
| 853 | .mask = {0x140}, |
| 854 | .reset_mask = 0x03, |
| 855 | }; |
| 856 | |
Maxime Ripard | e0e7943 | 2014-05-13 17:44:15 +0200 | [diff] [blame] | 857 | static const struct gates_data sun6i_a31_usb_gates_data __initconst = { |
| 858 | .mask = { BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8) }, |
| 859 | .reset_mask = BIT(2) | BIT(1) | BIT(0), |
| 860 | }; |
| 861 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 862 | static void __init sunxi_gates_clk_setup(struct device_node *node, |
| 863 | struct gates_data *data) |
| 864 | { |
| 865 | struct clk_onecell_data *clk_data; |
Hans de Goede | cfb0086 | 2014-02-07 16:21:49 +0100 | [diff] [blame] | 866 | struct gates_reset_data *reset_data; |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 867 | const char *clk_parent; |
| 868 | const char *clk_name; |
| 869 | void *reg; |
| 870 | int qty; |
| 871 | int i = 0; |
| 872 | int j = 0; |
| 873 | int ignore; |
| 874 | |
| 875 | reg = of_iomap(node, 0); |
| 876 | |
| 877 | clk_parent = of_clk_get_parent_name(node, 0); |
| 878 | |
| 879 | /* Worst-case size approximation and memory allocation */ |
| 880 | qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE); |
| 881 | clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); |
| 882 | if (!clk_data) |
| 883 | return; |
| 884 | clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL); |
| 885 | if (!clk_data->clks) { |
| 886 | kfree(clk_data); |
| 887 | return; |
| 888 | } |
| 889 | |
| 890 | for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) { |
| 891 | of_property_read_string_index(node, "clock-output-names", |
| 892 | j, &clk_name); |
| 893 | |
| 894 | /* No driver claims this clock, but it should remain gated */ |
| 895 | ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0; |
| 896 | |
| 897 | clk_data->clks[i] = clk_register_gate(NULL, clk_name, |
| 898 | clk_parent, ignore, |
| 899 | reg + 4 * (i/32), i % 32, |
| 900 | 0, &clk_lock); |
| 901 | WARN_ON(IS_ERR(clk_data->clks[i])); |
| 902 | |
| 903 | j++; |
| 904 | } |
| 905 | |
| 906 | /* Adjust to the real max */ |
| 907 | clk_data->clk_num = i; |
| 908 | |
| 909 | of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
Hans de Goede | cfb0086 | 2014-02-07 16:21:49 +0100 | [diff] [blame] | 910 | |
| 911 | /* Register a reset controler for gates with reset bits */ |
| 912 | if (data->reset_mask == 0) |
| 913 | return; |
| 914 | |
| 915 | reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL); |
| 916 | if (!reset_data) |
| 917 | return; |
| 918 | |
| 919 | reset_data->reg = reg; |
| 920 | reset_data->lock = &clk_lock; |
| 921 | reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1; |
| 922 | reset_data->rcdev.ops = &sunxi_gates_reset_ops; |
| 923 | reset_data->rcdev.of_node = node; |
| 924 | reset_controller_register(&reset_data->rcdev); |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 925 | } |
| 926 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 927 | |
| 928 | |
| 929 | /** |
| 930 | * sunxi_divs_clk_setup() helper data |
| 931 | */ |
| 932 | |
| 933 | #define SUNXI_DIVS_MAX_QTY 2 |
| 934 | #define SUNXI_DIVISOR_WIDTH 2 |
| 935 | |
| 936 | struct divs_data { |
| 937 | const struct factors_data *factors; /* data for the factor clock */ |
| 938 | struct { |
| 939 | u8 fixed; /* is it a fixed divisor? if not... */ |
| 940 | struct clk_div_table *table; /* is it a table based divisor? */ |
| 941 | u8 shift; /* otherwise it's a normal divisor with this shift */ |
| 942 | u8 pow; /* is it power-of-two based? */ |
| 943 | u8 gate; /* is it independently gateable? */ |
| 944 | } div[SUNXI_DIVS_MAX_QTY]; |
| 945 | }; |
| 946 | |
| 947 | static struct clk_div_table pll6_sata_tbl[] = { |
| 948 | { .val = 0, .div = 6, }, |
| 949 | { .val = 1, .div = 12, }, |
| 950 | { .val = 2, .div = 18, }, |
| 951 | { .val = 3, .div = 24, }, |
| 952 | { } /* sentinel */ |
| 953 | }; |
| 954 | |
| 955 | static const struct divs_data pll5_divs_data __initconst = { |
| 956 | .factors = &sun4i_pll5_data, |
| 957 | .div = { |
| 958 | { .shift = 0, .pow = 0, }, /* M, DDR */ |
| 959 | { .shift = 16, .pow = 1, }, /* P, other */ |
| 960 | } |
| 961 | }; |
| 962 | |
| 963 | static const struct divs_data pll6_divs_data __initconst = { |
Chen-Yu Tsai | 667f542 | 2014-02-03 09:51:39 +0800 | [diff] [blame] | 964 | .factors = &sun4i_pll6_data, |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 965 | .div = { |
| 966 | { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */ |
| 967 | { .fixed = 2 }, /* P, other */ |
| 968 | } |
| 969 | }; |
| 970 | |
| 971 | /** |
| 972 | * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks |
| 973 | * |
| 974 | * These clocks look something like this |
| 975 | * ________________________ |
| 976 | * | ___divisor 1---|----> to consumer |
| 977 | * parent >--| pll___/___divisor 2---|----> to consumer |
| 978 | * | \_______________|____> to consumer |
| 979 | * |________________________| |
| 980 | */ |
| 981 | |
| 982 | static void __init sunxi_divs_clk_setup(struct device_node *node, |
| 983 | struct divs_data *data) |
| 984 | { |
| 985 | struct clk_onecell_data *clk_data; |
Chen-Yu Tsai | 97e36b3 | 2014-02-03 09:51:40 +0800 | [diff] [blame] | 986 | const char *parent; |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 987 | const char *clk_name; |
| 988 | struct clk **clks, *pclk; |
| 989 | struct clk_hw *gate_hw, *rate_hw; |
| 990 | const struct clk_ops *rate_ops; |
| 991 | struct clk_gate *gate = NULL; |
| 992 | struct clk_fixed_factor *fix_factor; |
| 993 | struct clk_divider *divider; |
| 994 | void *reg; |
| 995 | int i = 0; |
| 996 | int flags, clkflags; |
| 997 | |
| 998 | /* Set up factor clock that we will be dividing */ |
| 999 | pclk = sunxi_factors_clk_setup(node, data->factors); |
Chen-Yu Tsai | 97e36b3 | 2014-02-03 09:51:40 +0800 | [diff] [blame] | 1000 | parent = __clk_get_name(pclk); |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1001 | |
| 1002 | reg = of_iomap(node, 0); |
| 1003 | |
| 1004 | clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); |
| 1005 | if (!clk_data) |
| 1006 | return; |
| 1007 | |
Emilio López | d193368 | 2014-01-24 22:32:41 -0300 | [diff] [blame] | 1008 | clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL); |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1009 | if (!clks) |
| 1010 | goto free_clkdata; |
| 1011 | |
| 1012 | clk_data->clks = clks; |
| 1013 | |
| 1014 | /* It's not a good idea to have automatic reparenting changing |
| 1015 | * our RAM clock! */ |
| 1016 | clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; |
| 1017 | |
| 1018 | for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) { |
| 1019 | if (of_property_read_string_index(node, "clock-output-names", |
| 1020 | i, &clk_name) != 0) |
| 1021 | break; |
| 1022 | |
| 1023 | gate_hw = NULL; |
| 1024 | rate_hw = NULL; |
| 1025 | rate_ops = NULL; |
| 1026 | |
| 1027 | /* If this leaf clock can be gated, create a gate */ |
| 1028 | if (data->div[i].gate) { |
| 1029 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); |
| 1030 | if (!gate) |
| 1031 | goto free_clks; |
| 1032 | |
| 1033 | gate->reg = reg; |
| 1034 | gate->bit_idx = data->div[i].gate; |
| 1035 | gate->lock = &clk_lock; |
| 1036 | |
| 1037 | gate_hw = &gate->hw; |
| 1038 | } |
| 1039 | |
| 1040 | /* Leaves can be fixed or configurable divisors */ |
| 1041 | if (data->div[i].fixed) { |
| 1042 | fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL); |
| 1043 | if (!fix_factor) |
| 1044 | goto free_gate; |
| 1045 | |
| 1046 | fix_factor->mult = 1; |
| 1047 | fix_factor->div = data->div[i].fixed; |
| 1048 | |
| 1049 | rate_hw = &fix_factor->hw; |
| 1050 | rate_ops = &clk_fixed_factor_ops; |
| 1051 | } else { |
| 1052 | divider = kzalloc(sizeof(*divider), GFP_KERNEL); |
| 1053 | if (!divider) |
| 1054 | goto free_gate; |
| 1055 | |
| 1056 | flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0; |
| 1057 | |
| 1058 | divider->reg = reg; |
| 1059 | divider->shift = data->div[i].shift; |
| 1060 | divider->width = SUNXI_DIVISOR_WIDTH; |
| 1061 | divider->flags = flags; |
| 1062 | divider->lock = &clk_lock; |
| 1063 | divider->table = data->div[i].table; |
| 1064 | |
| 1065 | rate_hw = ÷r->hw; |
| 1066 | rate_ops = &clk_divider_ops; |
| 1067 | } |
| 1068 | |
| 1069 | /* Wrap the (potential) gate and the divisor on a composite |
| 1070 | * clock to unify them */ |
| 1071 | clks[i] = clk_register_composite(NULL, clk_name, &parent, 1, |
| 1072 | NULL, NULL, |
| 1073 | rate_hw, rate_ops, |
| 1074 | gate_hw, &clk_gate_ops, |
| 1075 | clkflags); |
| 1076 | |
| 1077 | WARN_ON(IS_ERR(clk_data->clks[i])); |
| 1078 | clk_register_clkdev(clks[i], clk_name, NULL); |
| 1079 | } |
| 1080 | |
| 1081 | /* The last clock available on the getter is the parent */ |
| 1082 | clks[i++] = pclk; |
| 1083 | |
| 1084 | /* Adjust to the real max */ |
| 1085 | clk_data->clk_num = i; |
| 1086 | |
| 1087 | of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| 1088 | |
| 1089 | return; |
| 1090 | |
| 1091 | free_gate: |
| 1092 | kfree(gate); |
| 1093 | free_clks: |
| 1094 | kfree(clks); |
| 1095 | free_clkdata: |
| 1096 | kfree(clk_data); |
| 1097 | } |
| 1098 | |
| 1099 | |
| 1100 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1101 | /* Matches for factors clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 1102 | static const struct of_device_id clk_factors_match[] __initconst = { |
Maxime Ripard | fd1b22f | 2014-02-06 09:55:57 +0100 | [diff] [blame] | 1103 | {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1104 | {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,}, |
Emilio López | 5a8ddf2 | 2014-03-19 15:19:30 -0300 | [diff] [blame] | 1105 | {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,}, |
Maxime Ripard | 92ef67c | 2014-02-05 14:05:03 +0100 | [diff] [blame] | 1106 | {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,}, |
Maxime Ripard | fd1b22f | 2014-02-06 09:55:57 +0100 | [diff] [blame] | 1107 | {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,}, |
| 1108 | {.compatible = "allwinner,sun4i-a10-mod0-clk", .data = &sun4i_mod0_data,}, |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 1109 | {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1110 | {} |
| 1111 | }; |
| 1112 | |
| 1113 | /* Matches for divider clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 1114 | static const struct of_device_id clk_div_match[] __initconst = { |
Maxime Ripard | fd1b22f | 2014-02-06 09:55:57 +0100 | [diff] [blame] | 1115 | {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,}, |
| 1116 | {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,}, |
| 1117 | {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1118 | {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1119 | {} |
| 1120 | }; |
| 1121 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1122 | /* Matches for divided outputs */ |
| 1123 | static const struct of_device_id clk_divs_match[] __initconst = { |
Maxime Ripard | fd1b22f | 2014-02-06 09:55:57 +0100 | [diff] [blame] | 1124 | {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,}, |
| 1125 | {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,}, |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1126 | {} |
| 1127 | }; |
| 1128 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1129 | /* Matches for mux clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 1130 | static const struct of_device_id clk_mux_match[] __initconst = { |
Maxime Ripard | fd1b22f | 2014-02-06 09:55:57 +0100 | [diff] [blame] | 1131 | {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,}, |
| 1132 | {.compatible = "allwinner,sun4i-a10-apb1-mux-clk", .data = &sun4i_apb1_mux_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1133 | {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1134 | {} |
| 1135 | }; |
| 1136 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 1137 | /* Matches for gate clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 1138 | static const struct of_device_id clk_gates_match[] __initconst = { |
Maxime Ripard | fd1b22f | 2014-02-06 09:55:57 +0100 | [diff] [blame] | 1139 | {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,}, |
| 1140 | {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,}, |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 1141 | {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1142 | {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1143 | {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,}, |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 1144 | {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,}, |
Maxime Ripard | fd1b22f | 2014-02-06 09:55:57 +0100 | [diff] [blame] | 1145 | {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,}, |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 1146 | {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1147 | {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,}, |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 1148 | {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,}, |
Maxime Ripard | fd1b22f | 2014-02-06 09:55:57 +0100 | [diff] [blame] | 1149 | {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,}, |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 1150 | {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1151 | {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1152 | {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,}, |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 1153 | {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1154 | {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,}, |
Roman Byshko | 5abdbf2 | 2014-02-07 16:21:50 +0100 | [diff] [blame] | 1155 | {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,}, |
| 1156 | {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,}, |
Maxime Ripard | e0e7943 | 2014-05-13 17:44:15 +0200 | [diff] [blame] | 1157 | {.compatible = "allwinner,sun6i-a31-usb-clk", .data = &sun6i_a31_usb_gates_data,}, |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 1158 | {} |
| 1159 | }; |
| 1160 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1161 | static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match, |
| 1162 | void *function) |
| 1163 | { |
| 1164 | struct device_node *np; |
| 1165 | const struct div_data *data; |
| 1166 | const struct of_device_id *match; |
| 1167 | void (*setup_function)(struct device_node *, const void *) = function; |
| 1168 | |
Rob Herring | cb7d5f4 | 2014-05-12 11:24:31 -0500 | [diff] [blame] | 1169 | for_each_matching_node_and_match(np, clk_match, &match) { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1170 | data = match->data; |
| 1171 | setup_function(np, data); |
| 1172 | } |
| 1173 | } |
| 1174 | |
Maxime Ripard | 134a669 | 2014-05-09 22:33:39 -0500 | [diff] [blame] | 1175 | static void __init sunxi_init_clocks(const char *clocks[], int nclocks) |
Emilio López | 8e6a4c4 | 2013-09-20 22:03:12 -0300 | [diff] [blame] | 1176 | { |
Maxime Ripard | 134a669 | 2014-05-09 22:33:39 -0500 | [diff] [blame] | 1177 | unsigned int i; |
Emilio López | 8e6a4c4 | 2013-09-20 22:03:12 -0300 | [diff] [blame] | 1178 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1179 | /* Register factor clocks */ |
| 1180 | of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup); |
| 1181 | |
| 1182 | /* Register divider clocks */ |
| 1183 | of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup); |
| 1184 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1185 | /* Register divided output clocks */ |
| 1186 | of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup); |
| 1187 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1188 | /* Register mux clocks */ |
| 1189 | of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup); |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 1190 | |
| 1191 | /* Register gate clocks */ |
| 1192 | of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup); |
Emilio López | 8e6a4c4 | 2013-09-20 22:03:12 -0300 | [diff] [blame] | 1193 | |
Maxime Ripard | 134a669 | 2014-05-09 22:33:39 -0500 | [diff] [blame] | 1194 | /* Protect the clocks that needs to stay on */ |
| 1195 | for (i = 0; i < nclocks; i++) { |
| 1196 | struct clk *clk = clk_get(NULL, clocks[i]); |
| 1197 | |
| 1198 | if (!IS_ERR(clk)) |
| 1199 | clk_prepare_enable(clk); |
| 1200 | } |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1201 | } |
Maxime Ripard | 134a669 | 2014-05-09 22:33:39 -0500 | [diff] [blame] | 1202 | |
| 1203 | static const char *sun4i_a10_critical_clocks[] __initdata = { |
| 1204 | "pll5_ddr", |
| 1205 | }; |
| 1206 | |
| 1207 | static void __init sun4i_a10_init_clocks(struct device_node *node) |
| 1208 | { |
| 1209 | sunxi_init_clocks(sun4i_a10_critical_clocks, |
| 1210 | ARRAY_SIZE(sun4i_a10_critical_clocks)); |
| 1211 | } |
| 1212 | CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks); |
| 1213 | |
| 1214 | static const char *sun5i_critical_clocks[] __initdata = { |
| 1215 | "mbus", |
| 1216 | "pll5_ddr", |
| 1217 | }; |
| 1218 | |
| 1219 | static void __init sun5i_init_clocks(struct device_node *node) |
| 1220 | { |
| 1221 | sunxi_init_clocks(sun5i_critical_clocks, |
| 1222 | ARRAY_SIZE(sun5i_critical_clocks)); |
| 1223 | } |
| 1224 | CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks); |
| 1225 | CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks); |
| 1226 | CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks); |
| 1227 | |
| 1228 | static const char *sun6i_critical_clocks[] __initdata = { |
Maxime Ripard | 2df73f4 | 2014-05-09 22:33:40 -0500 | [diff] [blame^] | 1229 | "cpu", |
Maxime Ripard | 134a669 | 2014-05-09 22:33:39 -0500 | [diff] [blame] | 1230 | }; |
| 1231 | |
| 1232 | static void __init sun6i_init_clocks(struct device_node *node) |
| 1233 | { |
| 1234 | sunxi_init_clocks(sun6i_critical_clocks, |
| 1235 | ARRAY_SIZE(sun6i_critical_clocks)); |
| 1236 | } |
| 1237 | CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks); |