Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1 | /* |
Pierre Ossman | 70f1048 | 2007-07-11 20:04:50 +0200 | [diff] [blame] | 2 | * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3 | * |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 4 | * Header file for Host Controller registers and I/O accessors. |
| 5 | * |
Pierre Ossman | b69c905 | 2008-03-08 23:44:25 +0100 | [diff] [blame] | 6 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
Pierre Ossman | 643f720 | 2006-09-30 23:27:52 -0700 | [diff] [blame] | 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or (at |
| 11 | * your option) any later version. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 12 | */ |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 13 | #ifndef __SDHCI_HW_H |
| 14 | #define __SDHCI_HW_H |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 15 | |
Andrew Morton | 0c7ad10 | 2008-07-25 19:44:35 -0700 | [diff] [blame] | 16 | #include <linux/scatterlist.h> |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 17 | #include <linux/compiler.h> |
| 18 | #include <linux/types.h> |
| 19 | #include <linux/io.h> |
Sahitya Tummala | 4c196de | 2014-10-31 14:00:12 +0530 | [diff] [blame] | 20 | #include <linux/ratelimit.h> |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 21 | #include <linux/mmc/host.h> |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 22 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 23 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 24 | * Controller registers |
| 25 | */ |
| 26 | |
| 27 | #define SDHCI_DMA_ADDRESS 0x00 |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 28 | #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 29 | |
| 30 | #define SDHCI_BLOCK_SIZE 0x04 |
Pierre Ossman | bab7696 | 2006-07-02 16:51:35 +0100 | [diff] [blame] | 31 | #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 32 | |
| 33 | #define SDHCI_BLOCK_COUNT 0x06 |
| 34 | |
| 35 | #define SDHCI_ARGUMENT 0x08 |
| 36 | |
| 37 | #define SDHCI_TRANSFER_MODE 0x0C |
| 38 | #define SDHCI_TRNS_DMA 0x01 |
| 39 | #define SDHCI_TRNS_BLK_CNT_EN 0x02 |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 40 | #define SDHCI_TRNS_AUTO_CMD12 0x04 |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 41 | #define SDHCI_TRNS_AUTO_CMD23 0x08 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 42 | #define SDHCI_TRNS_READ 0x10 |
| 43 | #define SDHCI_TRNS_MULTI 0x20 |
| 44 | |
| 45 | #define SDHCI_COMMAND 0x0E |
| 46 | #define SDHCI_CMD_RESP_MASK 0x03 |
| 47 | #define SDHCI_CMD_CRC 0x08 |
| 48 | #define SDHCI_CMD_INDEX 0x10 |
| 49 | #define SDHCI_CMD_DATA 0x20 |
Richard Zhu | 574e3f5 | 2011-03-21 13:22:14 +0800 | [diff] [blame] | 50 | #define SDHCI_CMD_ABORTCMD 0xC0 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 51 | |
| 52 | #define SDHCI_CMD_RESP_NONE 0x00 |
| 53 | #define SDHCI_CMD_RESP_LONG 0x01 |
| 54 | #define SDHCI_CMD_RESP_SHORT 0x02 |
| 55 | #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 |
| 56 | |
| 57 | #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) |
Aries Lee | 22113ef | 2010-12-15 08:14:24 +0100 | [diff] [blame] | 58 | #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 59 | |
| 60 | #define SDHCI_RESPONSE 0x10 |
| 61 | |
| 62 | #define SDHCI_BUFFER 0x20 |
| 63 | |
| 64 | #define SDHCI_PRESENT_STATE 0x24 |
| 65 | #define SDHCI_CMD_INHIBIT 0x00000001 |
| 66 | #define SDHCI_DATA_INHIBIT 0x00000002 |
| 67 | #define SDHCI_DOING_WRITE 0x00000100 |
| 68 | #define SDHCI_DOING_READ 0x00000200 |
| 69 | #define SDHCI_SPACE_AVAILABLE 0x00000400 |
| 70 | #define SDHCI_DATA_AVAILABLE 0x00000800 |
| 71 | #define SDHCI_CARD_PRESENT 0x00010000 |
| 72 | #define SDHCI_WRITE_PROTECT 0x00080000 |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 73 | #define SDHCI_DATA_LVL_MASK 0x00F00000 |
| 74 | #define SDHCI_DATA_LVL_SHIFT 20 |
Yi Sun | 7756a96d | 2014-09-09 02:13:59 +0000 | [diff] [blame] | 75 | #define SDHCI_DATA_0_LVL_MASK 0x00100000 |
Michael Walle | b0921d5 | 2016-11-15 11:13:16 +0100 | [diff] [blame] | 76 | #define SDHCI_CMD_LVL 0x01000000 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 77 | |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 78 | #define SDHCI_HOST_CONTROL 0x28 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 79 | #define SDHCI_CTRL_LED 0x01 |
| 80 | #define SDHCI_CTRL_4BITBUS 0x02 |
Pierre Ossman | 077df88 | 2006-11-08 23:06:35 +0100 | [diff] [blame] | 81 | #define SDHCI_CTRL_HISPD 0x04 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 82 | #define SDHCI_CTRL_DMA_MASK 0x18 |
| 83 | #define SDHCI_CTRL_SDMA 0x00 |
| 84 | #define SDHCI_CTRL_ADMA1 0x08 |
| 85 | #define SDHCI_CTRL_ADMA32 0x10 |
| 86 | #define SDHCI_CTRL_ADMA64 0x18 |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 87 | #define SDHCI_CTRL_8BITBUS 0x20 |
Zach Brown | 3794c54 | 2016-09-16 10:01:42 -0500 | [diff] [blame] | 88 | #define SDHCI_CTRL_CDTEST_INS 0x40 |
| 89 | #define SDHCI_CTRL_CDTEST_EN 0x80 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 90 | |
| 91 | #define SDHCI_POWER_CONTROL 0x29 |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 92 | #define SDHCI_POWER_ON 0x01 |
| 93 | #define SDHCI_POWER_180 0x0A |
| 94 | #define SDHCI_POWER_300 0x0C |
| 95 | #define SDHCI_POWER_330 0x0E |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 96 | |
| 97 | #define SDHCI_BLOCK_GAP_CONTROL 0x2A |
| 98 | |
Nicolas Pitre | 2df3b71 | 2007-09-29 10:46:20 -0400 | [diff] [blame] | 99 | #define SDHCI_WAKE_UP_CONTROL 0x2B |
Daniel Drake | 5f61970 | 2010-11-04 22:20:39 +0000 | [diff] [blame] | 100 | #define SDHCI_WAKE_ON_INT 0x01 |
| 101 | #define SDHCI_WAKE_ON_INSERT 0x02 |
| 102 | #define SDHCI_WAKE_ON_REMOVE 0x04 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 103 | |
| 104 | #define SDHCI_CLOCK_CONTROL 0x2C |
| 105 | #define SDHCI_DIVIDER_SHIFT 8 |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 106 | #define SDHCI_DIVIDER_HI_SHIFT 6 |
| 107 | #define SDHCI_DIV_MASK 0xFF |
| 108 | #define SDHCI_DIV_MASK_LEN 8 |
| 109 | #define SDHCI_DIV_HI_MASK 0x300 |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 110 | #define SDHCI_PROG_CLOCK_MODE 0x0020 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 111 | #define SDHCI_CLOCK_CARD_EN 0x0004 |
| 112 | #define SDHCI_CLOCK_INT_STABLE 0x0002 |
| 113 | #define SDHCI_CLOCK_INT_EN 0x0001 |
| 114 | |
| 115 | #define SDHCI_TIMEOUT_CONTROL 0x2E |
| 116 | |
| 117 | #define SDHCI_SOFTWARE_RESET 0x2F |
| 118 | #define SDHCI_RESET_ALL 0x01 |
| 119 | #define SDHCI_RESET_CMD 0x02 |
| 120 | #define SDHCI_RESET_DATA 0x04 |
| 121 | |
| 122 | #define SDHCI_INT_STATUS 0x30 |
| 123 | #define SDHCI_INT_ENABLE 0x34 |
| 124 | #define SDHCI_SIGNAL_ENABLE 0x38 |
| 125 | #define SDHCI_INT_RESPONSE 0x00000001 |
| 126 | #define SDHCI_INT_DATA_END 0x00000002 |
Haijun Zhang | a4071fb | 2012-12-04 10:41:28 +0800 | [diff] [blame] | 127 | #define SDHCI_INT_BLK_GAP 0x00000004 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 128 | #define SDHCI_INT_DMA_END 0x00000008 |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 129 | #define SDHCI_INT_SPACE_AVAIL 0x00000010 |
| 130 | #define SDHCI_INT_DATA_AVAIL 0x00000020 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 131 | #define SDHCI_INT_CARD_INSERT 0x00000040 |
| 132 | #define SDHCI_INT_CARD_REMOVE 0x00000080 |
| 133 | #define SDHCI_INT_CARD_INT 0x00000100 |
Dong Aisheng | f37b20e | 2016-07-12 15:46:17 +0800 | [diff] [blame] | 134 | #define SDHCI_INT_RETUNE 0x00001000 |
Pierre Ossman | 964f9ce | 2007-07-20 18:20:36 +0200 | [diff] [blame] | 135 | #define SDHCI_INT_ERROR 0x00008000 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 136 | #define SDHCI_INT_TIMEOUT 0x00010000 |
| 137 | #define SDHCI_INT_CRC 0x00020000 |
| 138 | #define SDHCI_INT_END_BIT 0x00040000 |
| 139 | #define SDHCI_INT_INDEX 0x00080000 |
| 140 | #define SDHCI_INT_DATA_TIMEOUT 0x00100000 |
| 141 | #define SDHCI_INT_DATA_CRC 0x00200000 |
| 142 | #define SDHCI_INT_DATA_END_BIT 0x00400000 |
| 143 | #define SDHCI_INT_BUS_POWER 0x00800000 |
Asutosh Das | 09f36d0 | 2013-07-23 16:20:34 +0530 | [diff] [blame] | 144 | #define SDHCI_INT_AUTO_CMD_ERR 0x01000000 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 145 | #define SDHCI_INT_ADMA_ERROR 0x02000000 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 146 | |
| 147 | #define SDHCI_INT_NORMAL_MASK 0x00007FFF |
| 148 | #define SDHCI_INT_ERROR_MASK 0xFFFF8000 |
| 149 | |
| 150 | #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ |
Asutosh Das | 09f36d0 | 2013-07-23 16:20:34 +0530 | [diff] [blame] | 151 | SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \ |
| 152 | SDHCI_INT_AUTO_CMD_ERR) |
| 153 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 154 | #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 155 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 156 | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ |
Haijun Zhang | a4071fb | 2012-12-04 10:41:28 +0800 | [diff] [blame] | 157 | SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ |
| 158 | SDHCI_INT_BLK_GAP) |
Asutosh Das | 3621b37 | 2014-10-17 16:36:47 +0530 | [diff] [blame] | 159 | |
| 160 | #define SDHCI_INT_CMDQ_EN (0x1 << 14) |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 161 | #define SDHCI_INT_ALL_MASK ((unsigned int)-1) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 162 | |
Asutosh Das | 09f36d0 | 2013-07-23 16:20:34 +0530 | [diff] [blame] | 163 | #define SDHCI_AUTO_CMD_ERR 0x3C |
| 164 | #define SDHCI_AUTO_CMD12_NOT_EXEC 0x0001 |
| 165 | #define SDHCI_AUTO_CMD_TIMEOUT_ERR 0x0002 |
| 166 | #define SDHCI_AUTO_CMD_CRC_ERR 0x0004 |
| 167 | #define SDHCI_AUTO_CMD_ENDBIT_ERR 0x0008 |
| 168 | #define SDHCI_AUTO_CMD_INDEX_ERR 0x0010 |
| 169 | #define SDHCI_AUTO_CMD12_NOT_ISSUED 0x0080 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 170 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 171 | #define SDHCI_HOST_CONTROL2 0x3E |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 172 | #define SDHCI_CTRL_UHS_MASK 0x0007 |
| 173 | #define SDHCI_CTRL_UHS_SDR12 0x0000 |
| 174 | #define SDHCI_CTRL_UHS_SDR25 0x0001 |
| 175 | #define SDHCI_CTRL_UHS_SDR50 0x0002 |
| 176 | #define SDHCI_CTRL_UHS_SDR104 0x0003 |
| 177 | #define SDHCI_CTRL_UHS_DDR50 0x0004 |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 178 | #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 179 | #define SDHCI_CTRL_VDD_180 0x0008 |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 180 | #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 |
| 181 | #define SDHCI_CTRL_DRV_TYPE_B 0x0000 |
| 182 | #define SDHCI_CTRL_DRV_TYPE_A 0x0010 |
| 183 | #define SDHCI_CTRL_DRV_TYPE_C 0x0020 |
| 184 | #define SDHCI_CTRL_DRV_TYPE_D 0x0030 |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 185 | #define SDHCI_CTRL_EXEC_TUNING 0x0040 |
| 186 | #define SDHCI_CTRL_TUNED_CLK 0x0080 |
Ritesh Harjani | ce4b8f8 | 2015-11-25 10:37:21 +0530 | [diff] [blame] | 187 | #define SDHCI_CTRL_ASYNC_INT_ENABLE 0x4000 |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 188 | #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 189 | |
| 190 | #define SDHCI_CAPABILITIES 0x40 |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 191 | #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F |
| 192 | #define SDHCI_TIMEOUT_CLK_SHIFT 0 |
| 193 | #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 194 | #define SDHCI_CLOCK_BASE_MASK 0x00003F00 |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 195 | #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 196 | #define SDHCI_CLOCK_BASE_SHIFT 8 |
Pierre Ossman | 1d676e0 | 2006-07-02 16:52:10 +0100 | [diff] [blame] | 197 | #define SDHCI_MAX_BLOCK_MASK 0x00030000 |
| 198 | #define SDHCI_MAX_BLOCK_SHIFT 16 |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 199 | #define SDHCI_CAN_DO_8BIT 0x00040000 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 200 | #define SDHCI_CAN_DO_ADMA2 0x00080000 |
| 201 | #define SDHCI_CAN_DO_ADMA1 0x00100000 |
Pierre Ossman | 077df88 | 2006-11-08 23:06:35 +0100 | [diff] [blame] | 202 | #define SDHCI_CAN_DO_HISPD 0x00200000 |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 203 | #define SDHCI_CAN_DO_SDMA 0x00400000 |
Stefan Wahren | e71d4b8 | 2016-07-02 19:23:13 +0000 | [diff] [blame] | 204 | #define SDHCI_CAN_DO_SUSPEND 0x00800000 |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 205 | #define SDHCI_CAN_VDD_330 0x01000000 |
| 206 | #define SDHCI_CAN_VDD_300 0x02000000 |
| 207 | #define SDHCI_CAN_VDD_180 0x04000000 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 208 | #define SDHCI_CAN_64BIT 0x10000000 |
Ritesh Harjani | ce4b8f8 | 2015-11-25 10:37:21 +0530 | [diff] [blame] | 209 | #define SDHCI_CAN_ASYNC_INT 0x20000000 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 210 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 211 | #define SDHCI_SUPPORT_SDR50 0x00000001 |
| 212 | #define SDHCI_SUPPORT_SDR104 0x00000002 |
| 213 | #define SDHCI_SUPPORT_DDR50 0x00000004 |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 214 | #define SDHCI_DRIVER_TYPE_A 0x00000010 |
| 215 | #define SDHCI_DRIVER_TYPE_C 0x00000020 |
| 216 | #define SDHCI_DRIVER_TYPE_D 0x00000040 |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 217 | #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 |
| 218 | #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 |
| 219 | #define SDHCI_USE_SDR50_TUNING 0x00002000 |
| 220 | #define SDHCI_RETUNING_MODE_MASK 0x0000C000 |
| 221 | #define SDHCI_RETUNING_MODE_SHIFT 14 |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 222 | #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 |
| 223 | #define SDHCI_CLOCK_MUL_SHIFT 16 |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 224 | #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 225 | |
Philip Rakity | e8120ad | 2010-11-30 00:55:23 -0500 | [diff] [blame] | 226 | #define SDHCI_CAPABILITIES_1 0x44 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 227 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 228 | #define SDHCI_MAX_CURRENT 0x48 |
Philip Rakity | bad37e1 | 2012-05-27 18:36:44 -0700 | [diff] [blame] | 229 | #define SDHCI_MAX_CURRENT_LIMIT 0xFF |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 230 | #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF |
| 231 | #define SDHCI_MAX_CURRENT_330_SHIFT 0 |
| 232 | #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 |
| 233 | #define SDHCI_MAX_CURRENT_300_SHIFT 8 |
| 234 | #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 |
| 235 | #define SDHCI_MAX_CURRENT_180_SHIFT 16 |
| 236 | #define SDHCI_MAX_CURRENT_MULTIPLIER 4 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 237 | |
| 238 | /* 4C-4F reserved for more max current */ |
| 239 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 240 | #define SDHCI_SET_ACMD12_ERROR 0x50 |
| 241 | #define SDHCI_SET_INT_ERROR 0x52 |
| 242 | |
| 243 | #define SDHCI_ADMA_ERROR 0x54 |
| 244 | |
| 245 | /* 55-57 reserved */ |
| 246 | |
| 247 | #define SDHCI_ADMA_ADDRESS 0x58 |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 248 | #define SDHCI_ADMA_ADDRESS_HI 0x5C |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 249 | |
| 250 | /* 60-FB reserved */ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 251 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 252 | #define SDHCI_PRESET_FOR_SDR12 0x66 |
| 253 | #define SDHCI_PRESET_FOR_SDR25 0x68 |
| 254 | #define SDHCI_PRESET_FOR_SDR50 0x6A |
| 255 | #define SDHCI_PRESET_FOR_SDR104 0x6C |
| 256 | #define SDHCI_PRESET_FOR_DDR50 0x6E |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 257 | #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 258 | #define SDHCI_PRESET_DRV_MASK 0xC000 |
| 259 | #define SDHCI_PRESET_DRV_SHIFT 14 |
| 260 | #define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400 |
| 261 | #define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10 |
| 262 | #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF |
| 263 | #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 |
| 264 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 265 | #define SDHCI_SLOT_INT_STATUS 0xFC |
| 266 | |
| 267 | #define SDHCI_HOST_VERSION 0xFE |
Pierre Ossman | 4a96550 | 2006-06-30 02:22:29 -0700 | [diff] [blame] | 268 | #define SDHCI_VENDOR_VER_MASK 0xFF00 |
| 269 | #define SDHCI_VENDOR_VER_SHIFT 8 |
| 270 | #define SDHCI_SPEC_VER_MASK 0x00FF |
| 271 | #define SDHCI_SPEC_VER_SHIFT 0 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 272 | #define SDHCI_SPEC_100 0 |
| 273 | #define SDHCI_SPEC_200 1 |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 274 | #define SDHCI_SPEC_300 2 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 275 | |
Zhangfei Gao | 0397526 | 2010-09-20 15:15:18 -0400 | [diff] [blame] | 276 | /* |
| 277 | * End of controller registers. |
| 278 | */ |
| 279 | |
| 280 | #define SDHCI_MAX_DIV_SPEC_200 256 |
| 281 | #define SDHCI_MAX_DIV_SPEC_300 2046 |
| 282 | |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 283 | /* |
| 284 | * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. |
| 285 | */ |
| 286 | #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) |
| 287 | #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) |
| 288 | |
Adrian Hunter | 739d46d | 2014-11-04 12:42:44 +0200 | [diff] [blame] | 289 | /* ADMA2 32-bit DMA descriptor size */ |
| 290 | #define SDHCI_ADMA2_32_DESC_SZ 8 |
| 291 | |
Adrian Hunter | 0545230 | 2014-11-04 12:42:45 +0200 | [diff] [blame] | 292 | /* ADMA2 32-bit descriptor */ |
| 293 | struct sdhci_adma2_32_desc { |
| 294 | __le16 cmd; |
| 295 | __le16 len; |
| 296 | __le32 addr; |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 297 | } __packed __aligned(4); |
| 298 | |
| 299 | /* ADMA2 data alignment */ |
| 300 | #define SDHCI_ADMA2_ALIGN 4 |
| 301 | #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) |
| 302 | |
| 303 | /* |
| 304 | * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte |
| 305 | * alignment for the descriptor table even in 32-bit DMA mode. Memory |
| 306 | * allocation is at least 8 byte aligned anyway, so just stipulate 8 always. |
| 307 | */ |
| 308 | #define SDHCI_ADMA2_DESC_ALIGN 8 |
Adrian Hunter | 0545230 | 2014-11-04 12:42:45 +0200 | [diff] [blame] | 309 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 310 | /* ADMA2 64-bit DMA descriptor size */ |
| 311 | #define SDHCI_ADMA2_64_DESC_SZ 12 |
| 312 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 313 | /* |
| 314 | * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte |
| 315 | * aligned. |
| 316 | */ |
| 317 | struct sdhci_adma2_64_desc { |
| 318 | __le16 cmd; |
| 319 | __le16 len; |
| 320 | __le32 addr_lo; |
| 321 | __le32 addr_hi; |
| 322 | } __packed __aligned(4); |
| 323 | |
Adrian Hunter | 739d46d | 2014-11-04 12:42:44 +0200 | [diff] [blame] | 324 | #define ADMA2_TRAN_VALID 0x21 |
| 325 | #define ADMA2_NOP_END_VALID 0x3 |
| 326 | #define ADMA2_END 0x2 |
| 327 | |
Adrian Hunter | 4fb213f | 2014-11-04 12:42:43 +0200 | [diff] [blame] | 328 | /* |
| 329 | * Maximum segments assuming a 512KiB maximum requisition size and a minimum |
| 330 | * 4KiB page size. |
| 331 | */ |
| 332 | #define SDHCI_MAX_SEGS 128 |
| 333 | |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 334 | /* Allow for a a command request and a data request at the same time */ |
| 335 | #define SDHCI_MAX_MRQS 2 |
| 336 | |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 337 | enum sdhci_cookie { |
| 338 | COOKIE_UNMAPPED, |
Russell King | 94538e5 | 2016-01-26 13:40:37 +0000 | [diff] [blame] | 339 | COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ |
| 340 | COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 341 | }; |
| 342 | |
Sujit Reddy Thumma | 360bbf4 | 2013-06-19 20:15:37 +0530 | [diff] [blame] | 343 | enum sdhci_power_policy { |
| 344 | SDHCI_PERFORMANCE_MODE, |
| 345 | SDHCI_POWER_SAVE_MODE, |
Gilad Broner | c788a67 | 2015-09-08 15:39:11 +0300 | [diff] [blame] | 346 | SDHCI_POWER_POLICY_NUM /* Always keep this one last */ |
Sujit Reddy Thumma | 360bbf4 | 2013-06-19 20:15:37 +0530 | [diff] [blame] | 347 | }; |
| 348 | |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 349 | struct sdhci_host { |
| 350 | /* Data set by hardware interface driver */ |
| 351 | const char *hw_name; /* Hardware bus name */ |
| 352 | |
| 353 | unsigned int quirks; /* Deviations from spec. */ |
| 354 | |
| 355 | /* Controller doesn't honor resets unless we touch the clock register */ |
| 356 | #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) |
| 357 | /* Controller has bad caps bits, but really supports DMA */ |
| 358 | #define SDHCI_QUIRK_FORCE_DMA (1<<1) |
| 359 | /* Controller doesn't like to be reset when there is no card inserted. */ |
| 360 | #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) |
| 361 | /* Controller doesn't like clearing the power reg before a change */ |
| 362 | #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) |
| 363 | /* Controller has flaky internal state so reset it on each ios change */ |
| 364 | #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) |
| 365 | /* Controller has an unusable DMA engine */ |
| 366 | #define SDHCI_QUIRK_BROKEN_DMA (1<<5) |
| 367 | /* Controller has an unusable ADMA engine */ |
| 368 | #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) |
| 369 | /* Controller can only DMA from 32-bit aligned addresses */ |
| 370 | #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) |
| 371 | /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ |
| 372 | #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) |
| 373 | /* Controller can only ADMA chunks that are a multiple of 32 bits */ |
| 374 | #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) |
| 375 | /* Controller needs to be reset after each request to stay stable */ |
| 376 | #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) |
| 377 | /* Controller needs voltage and power writes to happen separately */ |
| 378 | #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) |
| 379 | /* Controller provides an incorrect timeout value for transfers */ |
| 380 | #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) |
| 381 | /* Controller has an issue with buffer bits for small transfers */ |
| 382 | #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) |
| 383 | /* Controller does not provide transfer-complete interrupt when not busy */ |
| 384 | #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) |
| 385 | /* Controller has unreliable card detection */ |
| 386 | #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) |
| 387 | /* Controller reports inverted write-protect state */ |
| 388 | #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) |
| 389 | /* Controller does not like fast PIO transfers */ |
| 390 | #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) |
| 391 | /* Controller has to be forced to use block size of 2048 bytes */ |
| 392 | #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) |
| 393 | /* Controller cannot do multi-block transfers */ |
| 394 | #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) |
| 395 | /* Controller can only handle 1-bit data transfers */ |
| 396 | #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) |
| 397 | /* Controller needs 10ms delay between applying power and clock */ |
| 398 | #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) |
| 399 | /* Controller uses SDCLK instead of TMCLK for data timeouts */ |
| 400 | #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) |
| 401 | /* Controller reports wrong base clock capability */ |
| 402 | #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) |
| 403 | /* Controller cannot support End Attribute in NOP ADMA descriptor */ |
| 404 | #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) |
| 405 | /* Controller is missing device caps. Use caps provided by host */ |
| 406 | #define SDHCI_QUIRK_MISSING_CAPS (1<<27) |
| 407 | /* Controller uses Auto CMD12 command to stop the transfer */ |
| 408 | #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) |
| 409 | /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ |
| 410 | #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) |
| 411 | /* Controller treats ADMA descriptors with length 0000h incorrectly */ |
| 412 | #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) |
| 413 | /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ |
| 414 | #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) |
| 415 | |
| 416 | unsigned int quirks2; /* More deviations from spec. */ |
| 417 | |
| 418 | #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) |
| 419 | #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) |
| 420 | /* The system physically doesn't support 1.8v, even if the host does */ |
| 421 | #define SDHCI_QUIRK2_NO_1_8_V (1<<2) |
| 422 | #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) |
| 423 | #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) |
| 424 | /* Controller has a non-standard host control register */ |
| 425 | #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) |
| 426 | /* Controller does not support HS200 */ |
| 427 | #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) |
| 428 | /* Controller does not support DDR50 */ |
| 429 | #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) |
| 430 | /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ |
| 431 | #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) |
| 432 | /* Controller does not support 64-bit DMA */ |
| 433 | #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) |
| 434 | /* need clear transfer mode register before send cmd */ |
| 435 | #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) |
| 436 | /* Capability register bit-63 indicates HS400 support */ |
| 437 | #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) |
| 438 | /* forced tuned clock */ |
| 439 | #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) |
| 440 | /* disable the block count for single block transactions */ |
| 441 | #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) |
| 442 | /* Controller broken with using ACMD23 */ |
| 443 | #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) |
Suneel Garapati | d1955c3 | 2015-06-09 13:01:50 +0530 | [diff] [blame] | 444 | /* Broken Clock divider zero in controller */ |
| 445 | #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) |
Venkat Gopalakrishnan | a58f91f | 2012-09-17 16:00:15 -0700 | [diff] [blame] | 446 | /* |
| 447 | * Read Transfer Active/ Write Transfer Active may be not |
| 448 | * de-asserted after end of transaction. Issue reset for DAT line. |
| 449 | */ |
| 450 | #define SDHCI_QUIRK2_RDWR_TX_ACTIVE_EOT (1<<17) |
| 451 | /* |
| 452 | * Slow interrupt clearance at 400KHz may cause |
| 453 | * host controller driver interrupt handler to |
| 454 | * be called twice. |
| 455 | */ |
| 456 | #define SDHCI_QUIRK2_SLOW_INT_CLR (1<<18) |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 457 | |
Venkat Gopalakrishnan | d6f9e5b | 2014-12-16 15:07:12 -0800 | [diff] [blame] | 458 | /* |
| 459 | * If the base clock can be scalable, then there should be no further |
| 460 | * clock dividing as the input clock itself will be scaled down to |
| 461 | * required frequency. |
| 462 | */ |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 463 | #define SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK (1<<19) |
| 464 | |
Sahitya Tummala | 87d4394 | 2013-04-12 11:49:11 +0530 | [diff] [blame] | 465 | /* |
| 466 | * Ignore data timeout error for R1B commands as there will be no |
| 467 | * data associated and the busy timeout value for these commands |
| 468 | * could be lager than the maximum timeout value that controller |
| 469 | * can handle. |
| 470 | */ |
Krishna Konda | 79fdcc2 | 2015-09-26 17:55:48 -0700 | [diff] [blame] | 471 | #define SDHCI_QUIRK2_IGNORE_DATATOUT_FOR_R1BCMD (1<<20) |
Sahitya Tummala | 87d4394 | 2013-04-12 11:49:11 +0530 | [diff] [blame] | 472 | |
Sahitya Tummala | 314162c | 2013-04-12 12:11:20 +0530 | [diff] [blame] | 473 | /* |
| 474 | * The preset value registers are not properly initialized by |
| 475 | * some hardware and hence preset value must not be enabled for |
| 476 | * such controllers. |
| 477 | */ |
Krishna Konda | 79fdcc2 | 2015-09-26 17:55:48 -0700 | [diff] [blame] | 478 | #define SDHCI_QUIRK2_BROKEN_PRESET_VALUE (1<<21) |
Sahitya Tummala | 7c9780d | 2013-04-12 11:59:25 +0530 | [diff] [blame] | 479 | /* |
| 480 | * Some controllers define the usage of 0xF in data timeout counter |
| 481 | * register (0x2E) which is actually a reserved bit as per |
| 482 | * specification. |
| 483 | */ |
Krishna Konda | 79fdcc2 | 2015-09-26 17:55:48 -0700 | [diff] [blame] | 484 | #define SDHCI_QUIRK2_USE_RESERVED_MAX_TIMEOUT (1<<22) |
Sahitya Tummala | a5733ab5 | 2013-06-10 16:32:51 +0530 | [diff] [blame] | 485 | /* |
| 486 | * This is applicable for controllers that advertize timeout clock |
| 487 | * value in capabilities register (bit 5-0) as just 50MHz whereas the |
| 488 | * base clock frequency is 200MHz. So, the controller internally |
| 489 | * multiplies the value in timeout control register by 4 with the |
| 490 | * assumption that driver always uses fixed timeout clock value from |
| 491 | * capabilities register to calculate the timeout. But when the driver |
| 492 | * uses SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK base clock frequency is directly |
| 493 | * controller by driver and it's rate varies upto max. 200MHz. This new quirk |
| 494 | * will be used in such cases to avoid controller mulplication when timeout is |
| 495 | * calculated based on the base clock. |
| 496 | */ |
| 497 | #define SDHCI_QUIRK2_DIVIDE_TOUT_BY_4 (1 << 23) |
Sahitya Tummala | 314162c | 2013-04-12 12:11:20 +0530 | [diff] [blame] | 498 | |
Asutosh Das | 214b966 | 2013-06-13 14:27:42 +0530 | [diff] [blame] | 499 | /* |
| 500 | * Some SDHC controllers are unable to handle data-end bit error in |
| 501 | * 1-bit mode of SDIO. |
| 502 | */ |
| 503 | #define SDHCI_QUIRK2_IGN_DATA_END_BIT_ERROR (1<<24) |
Pavan Anamula | e1ec2a7 | 2015-08-25 15:00:25 +0530 | [diff] [blame] | 504 | |
| 505 | /* Use reset workaround in case sdhci reset timeouts */ |
| 506 | #define SDHCI_QUIRK2_USE_RESET_WORKAROUND (1<<26) |
| 507 | |
Pavan Anamula | 5b76150 | 2015-07-23 18:45:37 +0530 | [diff] [blame] | 508 | /* Some controllers doesn't have have any LED control */ |
| 509 | #define SDHCI_QUIRK2_BROKEN_LED_CONTROL (1<<27) |
| 510 | |
Sahitya Tummala | 05709df | 2016-04-01 14:29:22 +0530 | [diff] [blame] | 511 | /* |
| 512 | * Some controllers doesn't follow the tuning procedure as defined in spec. |
| 513 | * The tuning data has to be compared from SW driver to validate the correct |
| 514 | * phase. |
| 515 | */ |
| 516 | #define SDHCI_QUIRK2_NON_STANDARD_TUNING (1 << 28) |
Sahitya Tummala | 01b9a92 | 2016-04-05 15:27:36 +0530 | [diff] [blame] | 517 | /* |
| 518 | * Some controllers may use PIO mode to workaround HW issues in ADMA for |
| 519 | * eMMC tuning commands. |
| 520 | */ |
Veerabhadrarao Badiganti | a5b8ac6 | 2017-09-07 15:14:49 +0530 | [diff] [blame] | 521 | #define SDHCI_QUIRK2_USE_PIO_FOR_EMMC_TUNING (1 << 29) |
Sahitya Tummala | 01b9a92 | 2016-04-05 15:27:36 +0530 | [diff] [blame] | 522 | |
Sahitya Tummala | 05709df | 2016-04-01 14:29:22 +0530 | [diff] [blame] | 523 | |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 524 | int irq; /* Device IRQ */ |
| 525 | void __iomem *ioaddr; /* Mapped address */ |
| 526 | |
| 527 | const struct sdhci_ops *ops; /* Low level hw interface */ |
| 528 | |
| 529 | /* Internal data */ |
| 530 | struct mmc_host *mmc; /* MMC structure */ |
Adrian Hunter | bf60e59 | 2016-02-09 16:12:35 +0200 | [diff] [blame] | 531 | struct mmc_host_ops mmc_host_ops; /* MMC host ops */ |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 532 | u64 dma_mask; /* custom DMA mask */ |
Pavan Anamula | eeb3b14 | 2015-07-22 18:17:32 +0530 | [diff] [blame] | 533 | u64 coherent_dma_mask; |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 534 | |
Masahiro Yamada | 74479c5 | 2016-04-14 13:19:40 +0900 | [diff] [blame] | 535 | #if IS_ENABLED(CONFIG_LEDS_CLASS) |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 536 | struct led_classdev led; /* LED control */ |
| 537 | char led_name[32]; |
| 538 | #endif |
| 539 | |
| 540 | spinlock_t lock; /* Mutex */ |
| 541 | |
| 542 | int flags; /* Host attributes */ |
| 543 | #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ |
| 544 | #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ |
| 545 | #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ |
| 546 | #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ |
| 547 | #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 548 | #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ |
| 549 | #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ |
| 550 | #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ |
| 551 | #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 552 | #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ |
| 553 | #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ |
Adrian Hunter | 8cb851a | 2016-06-29 16:24:16 +0300 | [diff] [blame] | 554 | #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ |
| 555 | #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ |
| 556 | #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ |
Ritesh Harjani | ce4b8f8 | 2015-11-25 10:37:21 +0530 | [diff] [blame] | 557 | #define SDHCI_HOST_IRQ_STATUS (1<<17) /* host->irq status */ |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 558 | |
| 559 | unsigned int version; /* SDHCI spec. version */ |
| 560 | |
| 561 | unsigned int max_clk; /* Max possible freq (MHz) */ |
| 562 | unsigned int timeout_clk; /* Timeout freq (KHz) */ |
| 563 | unsigned int clk_mul; /* Clock Muliplier value */ |
| 564 | |
| 565 | unsigned int clock; /* Current clock (MHz) */ |
| 566 | u8 pwr; /* Current voltage */ |
| 567 | |
| 568 | bool runtime_suspended; /* Host is runtime suspended */ |
| 569 | bool bus_on; /* Bus power prevents runtime suspend */ |
| 570 | bool preset_enabled; /* Preset is enabled */ |
Adrian Hunter | ed1563d | 2016-06-29 16:24:29 +0300 | [diff] [blame] | 571 | bool pending_reset; /* Cmd/data reset is pending */ |
Sayali Lokhande | 9efe657 | 2017-07-12 09:22:38 +0530 | [diff] [blame] | 572 | bool cdr_support; |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 573 | |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 574 | struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 575 | struct mmc_request *mrq; /* Current request */ |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 576 | struct mmc_command *cmd; /* Current command */ |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 577 | struct mmc_command *data_cmd; /* Current data command */ |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 578 | struct mmc_data *data; /* Current data request */ |
| 579 | unsigned int data_early:1; /* Data finished before cmd */ |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 580 | |
| 581 | struct sg_mapping_iter sg_miter; /* SG state for PIO */ |
| 582 | unsigned int blocks; /* remaining PIO blocks */ |
| 583 | |
| 584 | int sg_count; /* Mapped sg entries */ |
| 585 | |
| 586 | void *adma_table; /* ADMA descriptor table */ |
| 587 | void *align_buffer; /* Bounce buffer */ |
| 588 | |
| 589 | size_t adma_table_sz; /* ADMA descriptor table size */ |
| 590 | size_t align_buffer_sz; /* Bounce buffer size */ |
| 591 | |
| 592 | dma_addr_t adma_addr; /* Mapped ADMA descr. table */ |
| 593 | dma_addr_t align_addr; /* Mapped bounce buffer */ |
| 594 | |
| 595 | unsigned int desc_sz; /* ADMA descriptor size */ |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 596 | |
| 597 | struct tasklet_struct finish_tasklet; /* Tasklet structures */ |
| 598 | |
| 599 | struct timer_list timer; /* Timer for timeouts */ |
Adrian Hunter | d7422fb | 2016-06-29 16:24:33 +0300 | [diff] [blame] | 600 | struct timer_list data_timer; /* Timer for data timeouts */ |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 601 | |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 602 | u32 caps; /* CAPABILITY_0 */ |
| 603 | u32 caps1; /* CAPABILITY_1 */ |
Adrian Hunter | 6132a3b | 2016-06-29 16:24:18 +0300 | [diff] [blame] | 604 | bool read_caps; /* Capability flags have been read */ |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 605 | |
| 606 | unsigned int ocr_avail_sdio; /* OCR bit masks */ |
| 607 | unsigned int ocr_avail_sd; |
| 608 | unsigned int ocr_avail_mmc; |
| 609 | u32 ocr_mask; /* available voltages */ |
| 610 | |
| 611 | unsigned timing; /* Current timing */ |
| 612 | |
| 613 | u32 thread_isr; |
| 614 | |
| 615 | /* cached registers */ |
| 616 | u32 ier; |
| 617 | |
| 618 | wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ |
| 619 | unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ |
| 620 | |
| 621 | unsigned int tuning_count; /* Timer count for re-tuning */ |
| 622 | unsigned int tuning_mode; /* Re-tuning mode supported by host */ |
| 623 | #define SDHCI_TUNING_MODE_1 0 |
Dong Aisheng | f37b20e | 2016-07-12 15:46:17 +0800 | [diff] [blame] | 624 | #define SDHCI_TUNING_MODE_2 1 |
| 625 | #define SDHCI_TUNING_MODE_3 2 |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 626 | |
Sahitya Tummala | 16dabee | 2013-04-08 12:53:44 +0530 | [diff] [blame] | 627 | ktime_t data_start_time; |
Sahitya Tummala | c6f48d4 | 2013-03-10 07:03:17 +0530 | [diff] [blame] | 628 | |
Sujit Reddy Thumma | 360bbf4 | 2013-06-19 20:15:37 +0530 | [diff] [blame] | 629 | enum sdhci_power_policy power_policy; |
| 630 | |
Ritesh Harjani | ce4b8f8 | 2015-11-25 10:37:21 +0530 | [diff] [blame] | 631 | bool sdio_irq_async_status; |
Sahitya Tummala | 9325fb0 | 2015-05-08 11:53:29 +0530 | [diff] [blame] | 632 | bool is_crypto_en; |
Sahitya Tummala | 4eca099 | 2015-05-08 11:14:23 +0530 | [diff] [blame] | 633 | bool crypto_reset_reqd; |
Ritesh Harjani | ce4b8f8 | 2015-11-25 10:37:21 +0530 | [diff] [blame] | 634 | |
Sahitya Tummala | 9e7fadb | 2013-08-07 18:40:29 +0530 | [diff] [blame] | 635 | u32 auto_cmd_err_sts; |
Sahitya Tummala | 4c196de | 2014-10-31 14:00:12 +0530 | [diff] [blame] | 636 | struct ratelimit_state dbg_dump_rs; |
Asutosh Das | 3621b37 | 2014-10-17 16:36:47 +0530 | [diff] [blame] | 637 | struct cmdq_host *cq_host; |
Pavan Anamula | e1ec2a7 | 2015-08-25 15:00:25 +0530 | [diff] [blame] | 638 | int reset_wa_applied; /* reset workaround status */ |
| 639 | ktime_t reset_wa_t; /* time when the reset workaround is applied */ |
| 640 | int reset_wa_cnt; /* total number of times workaround is used */ |
Asutosh Das | 3621b37 | 2014-10-17 16:36:47 +0530 | [diff] [blame] | 641 | |
Ulf Hansson | 83f13cc | 2015-03-04 10:19:14 +0100 | [diff] [blame] | 642 | unsigned long private[0] ____cacheline_aligned; |
| 643 | }; |
| 644 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 645 | struct sdhci_ops { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 646 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 647 | u32 (*read_l)(struct sdhci_host *host, int reg); |
| 648 | u16 (*read_w)(struct sdhci_host *host, int reg); |
| 649 | u8 (*read_b)(struct sdhci_host *host, int reg); |
| 650 | void (*write_l)(struct sdhci_host *host, u32 val, int reg); |
| 651 | void (*write_w)(struct sdhci_host *host, u16 val, int reg); |
| 652 | void (*write_b)(struct sdhci_host *host, u8 val, int reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 653 | #endif |
| 654 | |
Anton Vorontsov | 8114634 | 2009-03-17 00:13:59 +0300 | [diff] [blame] | 655 | void (*set_clock)(struct sdhci_host *host, unsigned int clock); |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 656 | void (*set_power)(struct sdhci_host *host, unsigned char mode, |
| 657 | unsigned short vdd); |
Anton Vorontsov | 8114634 | 2009-03-17 00:13:59 +0300 | [diff] [blame] | 658 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 659 | int (*enable_dma)(struct sdhci_host *host); |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 660 | unsigned int (*get_max_clock)(struct sdhci_host *host); |
Anton Vorontsov | a9e58f2 | 2009-07-29 15:04:16 -0700 | [diff] [blame] | 661 | unsigned int (*get_min_clock)(struct sdhci_host *host); |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 662 | unsigned int (*get_timeout_clock)(struct sdhci_host *host); |
Aisheng Dong | a6ff5ae | 2014-08-27 15:26:27 +0800 | [diff] [blame] | 663 | unsigned int (*get_max_timeout_count)(struct sdhci_host *host); |
Aisheng Dong | b45e668 | 2014-08-27 15:26:29 +0800 | [diff] [blame] | 664 | void (*set_timeout)(struct sdhci_host *host, |
| 665 | struct mmc_command *cmd); |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 666 | void (*set_bus_width)(struct sdhci_host *host, int width); |
Philip Rakity | 643a81f | 2010-09-23 08:24:32 -0700 | [diff] [blame] | 667 | void (*platform_send_init_74_clocks)(struct sdhci_host *host, |
| 668 | u8 power_mode); |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 669 | unsigned int (*get_ro)(struct sdhci_host *host); |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 670 | void (*reset)(struct sdhci_host *host, u8 mask); |
Dong Aisheng | 4525181 | 2013-09-13 19:11:30 +0800 | [diff] [blame] | 671 | int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); |
Sahitya Tummala | 9325fb0 | 2015-05-08 11:53:29 +0530 | [diff] [blame] | 672 | int (*crypto_engine_cfg)(struct sdhci_host *host, |
| 673 | struct mmc_request *mrq, u32 slot); |
Veerabhadrarao Badiganti | dec5880 | 2017-01-31 11:21:37 +0530 | [diff] [blame] | 674 | int (*crypto_engine_cmdq_cfg)(struct sdhci_host *host, |
| 675 | struct mmc_request *mrq, u32 slot, u64 *ice_ctx); |
Veerabhadrarao Badiganti | f271be4 | 2017-03-08 06:35:21 +0530 | [diff] [blame] | 676 | int (*crypto_engine_cfg_end)(struct sdhci_host *host, |
| 677 | struct mmc_request *mrq); |
Sahitya Tummala | 9325fb0 | 2015-05-08 11:53:29 +0530 | [diff] [blame] | 678 | int (*crypto_engine_reset)(struct sdhci_host *host); |
Sahitya Tummala | 82a1975 | 2015-09-01 16:44:08 +0530 | [diff] [blame] | 679 | void (*crypto_cfg_reset)(struct sdhci_host *host, unsigned int slot); |
Russell King | 13e6450 | 2014-04-25 12:59:20 +0100 | [diff] [blame] | 680 | void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); |
Adrian Hunter | 20758b6 | 2011-08-29 16:42:12 +0300 | [diff] [blame] | 681 | void (*hw_reset)(struct sdhci_host *host); |
Haijun Zhang | a4071fb | 2012-12-04 10:41:28 +0800 | [diff] [blame] | 682 | void (*adma_workaround)(struct sdhci_host *host, u32 intmask); |
Asutosh Das | 648f9d1 | 2013-01-10 21:11:04 +0530 | [diff] [blame] | 683 | unsigned int (*get_max_segments)(void); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 684 | #define REQ_BUS_OFF (1 << 0) |
| 685 | #define REQ_BUS_ON (1 << 1) |
| 686 | #define REQ_IO_LOW (1 << 2) |
| 687 | #define REQ_IO_HIGH (1 << 3) |
Christian Daudt | 722e128 | 2013-06-20 14:26:36 -0700 | [diff] [blame] | 688 | void (*card_event)(struct sdhci_host *host); |
Ritesh Harjani | 9ce9ecf | 2015-05-27 15:32:40 +0530 | [diff] [blame] | 689 | int (*enhanced_strobe)(struct sdhci_host *host); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 690 | void (*platform_bus_voting)(struct sdhci_host *host, u32 enable); |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 691 | void (*toggle_cdr)(struct sdhci_host *host, bool enable); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 692 | void (*check_power_status)(struct sdhci_host *host, u32 req_type); |
Asutosh Das | b58499d | 2013-07-30 19:07:29 +0530 | [diff] [blame] | 693 | int (*config_auto_tuning_cmd)(struct sdhci_host *host, |
| 694 | bool enable, |
| 695 | u32 type); |
Asutosh Das | 30ec599 | 2013-11-08 12:31:48 +0530 | [diff] [blame] | 696 | int (*enable_controller_clock)(struct sdhci_host *host); |
Asutosh Das | 3621b37 | 2014-10-17 16:36:47 +0530 | [diff] [blame] | 697 | void (*clear_set_dumpregs)(struct sdhci_host *host, bool set); |
Ritesh Harjani | 1f6d762 | 2015-07-15 13:31:06 +0530 | [diff] [blame] | 698 | void (*enhanced_strobe_mask)(struct sdhci_host *host, bool set); |
Sahitya Tummala | 91d315e | 2013-08-02 09:17:54 +0530 | [diff] [blame] | 699 | void (*dump_vendor_regs)(struct sdhci_host *host); |
Vincent Yang | 9d967a6 | 2015-01-20 16:05:15 +0800 | [diff] [blame] | 700 | void (*voltage_switch)(struct sdhci_host *host); |
Adrian Hunter | cb84964 | 2015-02-06 14:12:59 +0200 | [diff] [blame] | 701 | int (*select_drive_strength)(struct sdhci_host *host, |
| 702 | struct mmc_card *card, |
| 703 | unsigned int max_dtr, int host_drv, |
| 704 | int card_drv, int *drv_type); |
Sahitya Tummala | d300470 | 2015-08-06 13:58:47 +0530 | [diff] [blame] | 705 | int (*notify_load)(struct sdhci_host *host, enum mmc_load state); |
Pavan Anamula | e1ec2a7 | 2015-08-25 15:00:25 +0530 | [diff] [blame] | 706 | void (*reset_workaround)(struct sdhci_host *host, u32 enable); |
Gilad Broner | 07d92eb | 2015-09-29 16:57:21 +0300 | [diff] [blame] | 707 | void (*init)(struct sdhci_host *host); |
| 708 | void (*pre_req)(struct sdhci_host *host, struct mmc_request *req); |
| 709 | void (*post_req)(struct sdhci_host *host, struct mmc_request *req); |
Sahitya Tummala | cba7e83 | 2014-09-19 15:43:37 +0530 | [diff] [blame] | 710 | unsigned int (*get_current_limit)(struct sdhci_host *host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 711 | }; |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 712 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 713 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
| 714 | |
| 715 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) |
| 716 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 717 | if (unlikely(host->ops->write_l)) |
| 718 | host->ops->write_l(host, val, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 719 | else |
| 720 | writel(val, host->ioaddr + reg); |
| 721 | } |
| 722 | |
| 723 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
| 724 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 725 | if (unlikely(host->ops->write_w)) |
| 726 | host->ops->write_w(host, val, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 727 | else |
| 728 | writew(val, host->ioaddr + reg); |
| 729 | } |
| 730 | |
| 731 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) |
| 732 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 733 | if (unlikely(host->ops->write_b)) |
| 734 | host->ops->write_b(host, val, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 735 | else |
| 736 | writeb(val, host->ioaddr + reg); |
| 737 | } |
| 738 | |
| 739 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) |
| 740 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 741 | if (unlikely(host->ops->read_l)) |
| 742 | return host->ops->read_l(host, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 743 | else |
| 744 | return readl(host->ioaddr + reg); |
| 745 | } |
| 746 | |
| 747 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) |
| 748 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 749 | if (unlikely(host->ops->read_w)) |
| 750 | return host->ops->read_w(host, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 751 | else |
| 752 | return readw(host->ioaddr + reg); |
| 753 | } |
| 754 | |
| 755 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) |
| 756 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 757 | if (unlikely(host->ops->read_b)) |
| 758 | return host->ops->read_b(host, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 759 | else |
| 760 | return readb(host->ioaddr + reg); |
| 761 | } |
| 762 | |
| 763 | #else |
| 764 | |
| 765 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) |
| 766 | { |
| 767 | writel(val, host->ioaddr + reg); |
| 768 | } |
| 769 | |
| 770 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
| 771 | { |
| 772 | writew(val, host->ioaddr + reg); |
| 773 | } |
| 774 | |
| 775 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) |
| 776 | { |
| 777 | writeb(val, host->ioaddr + reg); |
| 778 | } |
| 779 | |
| 780 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) |
| 781 | { |
| 782 | return readl(host->ioaddr + reg); |
| 783 | } |
| 784 | |
| 785 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) |
| 786 | { |
| 787 | return readw(host->ioaddr + reg); |
| 788 | } |
| 789 | |
| 790 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) |
| 791 | { |
| 792 | return readb(host->ioaddr + reg); |
| 793 | } |
| 794 | |
| 795 | #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 796 | |
| 797 | extern struct sdhci_host *sdhci_alloc_host(struct device *dev, |
| 798 | size_t priv_size); |
| 799 | extern void sdhci_free_host(struct sdhci_host *host); |
| 800 | |
| 801 | static inline void *sdhci_priv(struct sdhci_host *host) |
| 802 | { |
| 803 | return (void *)host->private; |
| 804 | } |
| 805 | |
Marek Szyprowski | 17866e1 | 2010-08-10 18:01:58 -0700 | [diff] [blame] | 806 | extern void sdhci_card_detect(struct sdhci_host *host); |
Adrian Hunter | 6132a3b | 2016-06-29 16:24:18 +0300 | [diff] [blame] | 807 | extern void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, |
| 808 | u32 *caps1); |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 809 | extern int sdhci_setup_host(struct sdhci_host *host); |
| 810 | extern int __sdhci_add_host(struct sdhci_host *host); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 811 | extern int sdhci_add_host(struct sdhci_host *host); |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 812 | extern void sdhci_remove_host(struct sdhci_host *host, int dead); |
Dong Aisheng | c0e55129 | 2013-09-13 19:11:31 +0800 | [diff] [blame] | 813 | extern void sdhci_send_command(struct sdhci_host *host, |
| 814 | struct mmc_command *cmd); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 815 | |
Adrian Hunter | 6132a3b | 2016-06-29 16:24:18 +0300 | [diff] [blame] | 816 | static inline void sdhci_read_caps(struct sdhci_host *host) |
| 817 | { |
| 818 | __sdhci_read_caps(host, NULL, NULL, NULL); |
| 819 | } |
| 820 | |
Russell King | be13855 | 2014-04-25 12:55:56 +0100 | [diff] [blame] | 821 | static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) |
| 822 | { |
| 823 | return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); |
| 824 | } |
| 825 | |
Ludovic Desroches | fb9ee04 | 2016-04-07 11:13:08 +0200 | [diff] [blame] | 826 | u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, |
| 827 | unsigned int *actual_clock); |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 828 | void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 829 | void sdhci_set_power(struct sdhci_host *host, unsigned char mode, |
| 830 | unsigned short vdd); |
Adrian Hunter | 606d313 | 2016-10-05 12:11:22 +0300 | [diff] [blame] | 831 | void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, |
| 832 | unsigned short vdd); |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 833 | void sdhci_set_bus_width(struct sdhci_host *host, int width); |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 834 | void sdhci_reset(struct sdhci_host *host, u8 mask); |
Russell King | 96d7b78 | 2014-04-25 12:59:26 +0100 | [diff] [blame] | 835 | void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 836 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 837 | #ifdef CONFIG_PM |
Manuel Lauss | 29495aa | 2011-11-03 11:09:45 +0100 | [diff] [blame] | 838 | extern int sdhci_suspend_host(struct sdhci_host *host); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 839 | extern int sdhci_resume_host(struct sdhci_host *host); |
Daniel Drake | 5f61970 | 2010-11-04 22:20:39 +0000 | [diff] [blame] | 840 | extern void sdhci_enable_irq_wakeups(struct sdhci_host *host); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 841 | extern int sdhci_runtime_suspend_host(struct sdhci_host *host); |
| 842 | extern int sdhci_runtime_resume_host(struct sdhci_host *host); |
| 843 | #endif |
| 844 | |
Ritesh Harjani | ce4b8f8 | 2015-11-25 10:37:21 +0530 | [diff] [blame] | 845 | void sdhci_cfg_irq(struct sdhci_host *host, bool enable, bool sync); |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 846 | #endif /* __SDHCI_HW_H */ |