blob: 23f2824e8d5626d755fa2f8e5b0543eaf75def6c [file] [log] [blame]
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +03001/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
Liad Kaufman553452e2015-04-16 17:21:12 +03008 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +030010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
Emmanuel Grumbach410dc5a2013-02-18 09:22:28 +020026 * in the file called COPYING.
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +030027 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
Liad Kaufman553452e2015-04-16 17:21:12 +030034 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
35 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +030036 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -080065#include <linux/pci.h>
66#include <linux/pci-aspm.h>
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -070067#include <linux/interrupt.h>
Emmanuel Grumbach87e56662011-08-25 23:10:50 -070068#include <linux/debugfs.h>
Emmanuel Grumbachcf614292012-01-08 16:33:58 +020069#include <linux/sched.h>
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -070070#include <linux/bitops.h>
71#include <linux/gfp.h>
Emmanuel Grumbach48eb7b32014-07-08 19:45:17 +030072#include <linux/vmalloc.h>
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -070073
Johannes Berg82575102012-04-03 16:44:37 -070074#include "iwl-drv.h"
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +030075#include "iwl-trans.h"
Emmanuel Grumbach522376d2011-09-06 09:31:19 -070076#include "iwl-csr.h"
77#include "iwl-prph.h"
Emmanuel Grumbachcb6bb122015-01-25 10:36:31 +020078#include "iwl-scd.h"
Emmanuel Grumbach7a10e3e42011-09-06 09:31:21 -070079#include "iwl-agn-hw.h"
Johannes Berg4d075002014-04-24 10:41:31 +020080#include "iwl-fw-error-dump.h"
Johannes Berg6468a012012-05-16 19:13:54 +020081#include "internal.h"
Liad Kaufman06d51e02014-11-23 13:56:21 +020082#include "iwl-fh.h"
Johannes Berg0439bb62012-03-05 11:24:45 -080083
Arik Nemtsovfe457732014-11-17 15:46:37 +020084/* extended range in FW SRAM */
85#define IWL_FW_MEM_EXTENDED_START 0x40000
86#define IWL_FW_MEM_EXTENDED_END 0x57FFF
87
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +030088static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
89{
90 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
91
92 if (!trans_pcie->fw_mon_page)
93 return;
94
95 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
96 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
97 __free_pages(trans_pcie->fw_mon_page,
98 get_order(trans_pcie->fw_mon_size));
99 trans_pcie->fw_mon_page = NULL;
100 trans_pcie->fw_mon_phys = 0;
101 trans_pcie->fw_mon_size = 0;
102}
103
Emmanuel Grumbach96c285d2015-04-14 23:14:48 +0300104static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +0300105{
106 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Liad Kaufman553452e2015-04-16 17:21:12 +0300107 struct page *page = NULL;
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +0300108 dma_addr_t phys;
Emmanuel Grumbach96c285d2015-04-14 23:14:48 +0300109 u32 size = 0;
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +0300110 u8 power;
111
Emmanuel Grumbach96c285d2015-04-14 23:14:48 +0300112 if (!max_power) {
113 /* default max_power is maximum */
114 max_power = 26;
115 } else {
116 max_power += 11;
117 }
118
119 if (WARN(max_power > 26,
120 "External buffer size for monitor is too big %d, check the FW TLV\n",
121 max_power))
122 return;
123
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +0300124 if (trans_pcie->fw_mon_page) {
125 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
126 trans_pcie->fw_mon_size,
127 DMA_FROM_DEVICE);
128 return;
129 }
130
131 phys = 0;
Emmanuel Grumbach96c285d2015-04-14 23:14:48 +0300132 for (power = max_power; power >= 11; power--) {
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +0300133 int order;
134
135 size = BIT(power);
136 order = get_order(size);
137 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
138 order);
139 if (!page)
140 continue;
141
142 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
143 DMA_FROM_DEVICE);
144 if (dma_mapping_error(trans->dev, phys)) {
145 __free_pages(page, order);
Liad Kaufman553452e2015-04-16 17:21:12 +0300146 page = NULL;
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +0300147 continue;
148 }
149 IWL_INFO(trans,
150 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
151 size, order);
152 break;
153 }
154
Emmanuel Grumbach40a76902014-09-18 15:44:04 +0300155 if (WARN_ON_ONCE(!page))
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +0300156 return;
157
Emmanuel Grumbach96c285d2015-04-14 23:14:48 +0300158 if (power != max_power)
159 IWL_ERR(trans,
160 "Sorry - debug buffer is only %luK while you requested %luK\n",
161 (unsigned long)BIT(power - 10),
162 (unsigned long)BIT(max_power - 10));
163
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +0300164 trans_pcie->fw_mon_page = page;
165 trans_pcie->fw_mon_phys = phys;
166 trans_pcie->fw_mon_size = size;
167}
168
Alexander Bondara812cba2014-02-18 16:45:00 +0100169static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
170{
171 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
172 ((reg & 0x0000ffff) | (2 << 28)));
173 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
174}
175
176static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
177{
178 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
179 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
180 ((reg & 0x0000ffff) | (3 << 28)));
181}
182
Johannes Bergddaf5a52013-01-08 11:25:44 +0100183static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300184{
Avri Altman95411d02015-05-11 11:04:34 +0300185 if (!trans->cfg->apmg_not_supported)
186 return;
187
Johannes Bergddaf5a52013-01-08 11:25:44 +0100188 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
189 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
190 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
191 ~APMG_PS_CTRL_MSK_PWR_SRC);
192 else
193 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
194 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
195 ~APMG_PS_CTRL_MSK_PWR_SRC);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300196}
197
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +0200198/* PCI registers */
199#define PCI_CFG_RETRY_TIMEOUT 0x041
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +0200200
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200201static void iwl_pcie_apm_config(struct iwl_trans *trans)
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +0200202{
Johannes Berg20d3b642012-05-16 22:54:29 +0200203 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200204 u16 lctl;
Emmanuel Grumbach9180ac52014-09-23 23:02:41 +0300205 u16 cap;
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +0200206
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +0200207 /*
208 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
209 * Check if BIOS (or OS) enabled L1-ASPM on this device.
210 * If so (likely), disable L0S, so device moves directly L0->L1;
211 * costs negligible amount of power savings.
212 * If not (unlikely), enable L0S, so there is at least some
213 * power savings, even without L1.
214 */
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200215 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
Emmanuel Grumbach9180ac52014-09-23 23:02:41 +0300216 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +0200217 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
Emmanuel Grumbach9180ac52014-09-23 23:02:41 +0300218 else
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +0200219 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
Bjorn Helgaas438a0f02012-12-05 13:51:21 -0700220 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
Emmanuel Grumbach9180ac52014-09-23 23:02:41 +0300221
222 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
223 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
224 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
225 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
226 trans->ltr_enabled ? "En" : "Dis");
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +0200227}
228
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200229/*
230 * Start up NIC's basic functionality after it has been reset
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200231 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200232 * NOTE: This does not load uCode nor start the embedded processor
233 */
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200234static int iwl_pcie_apm_init(struct iwl_trans *trans)
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200235{
236 int ret = 0;
237 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
238
239 /*
240 * Use "set_bit" below rather than "write", to preserve any hardware
241 * bits already set by default after reset.
242 */
243
244 /* Disable L0S exit timer (platform NMI Work/Around) */
Eran Hararye4a9f8c2013-12-22 08:06:34 +0200245 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
246 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
247 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200248
249 /*
250 * Disable L0s without affecting L1;
251 * don't wait for ICH L0s (ICH bug W/A)
252 */
253 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
Johannes Berg20d3b642012-05-16 22:54:29 +0200254 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200255
256 /* Set FH wait threshold to maximum (HW error during stress W/A) */
257 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
258
259 /*
260 * Enable HAP INTA (interrupt from management bus) to
261 * wake device's PCI Express link L1a -> L0s
262 */
263 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
Johannes Berg20d3b642012-05-16 22:54:29 +0200264 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200265
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200266 iwl_pcie_apm_config(trans);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200267
268 /* Configure analog phase-lock-loop before activating to D0A */
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -0700269 if (trans->cfg->base_params->pll_cfg_val)
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200270 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -0700271 trans->cfg->base_params->pll_cfg_val);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200272
273 /*
274 * Set "initialization complete" bit to move adapter from
275 * D0U* --> D0A* (powered-up active) state.
276 */
277 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
278
279 /*
280 * Wait for clock stabilization; once stabilized, access to
281 * device-internal resources is supported, e.g. iwl_write_prph()
282 * and accesses to uCode SRAM.
283 */
284 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
Johannes Berg20d3b642012-05-16 22:54:29 +0200285 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
286 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200287 if (ret < 0) {
288 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
289 goto out;
290 }
291
Emmanuel Grumbach2d93aee2013-12-24 14:15:41 +0200292 if (trans->cfg->host_interrupt_operation_mode) {
293 /*
294 * This is a bit of an abuse - This is needed for 7260 / 3160
295 * only check host_interrupt_operation_mode even if this is
296 * not related to host_interrupt_operation_mode.
297 *
298 * Enable the oscillator to count wake up time for L1 exit. This
299 * consumes slightly more power (100uA) - but allows to be sure
300 * that we wake up from L1 on time.
301 *
302 * This looks weird: read twice the same register, discard the
303 * value, set a bit, and yet again, read that same register
304 * just to discard the value. But that's the way the hardware
305 * seems to like it.
306 */
307 iwl_read_prph(trans, OSC_CLK);
308 iwl_read_prph(trans, OSC_CLK);
309 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_read_prph(trans, OSC_CLK);
312 }
313
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200314 /*
315 * Enable DMA clock and wait for it to stabilize.
316 *
Eran Harary3073d8c2013-12-29 14:09:59 +0200317 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
318 * bits do not disable clocks. This preserves any hardware
319 * bits already set by default in "CLK_CTRL_REG" after reset.
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200320 */
Avri Altman95411d02015-05-11 11:04:34 +0300321 if (!trans->cfg->apmg_not_supported) {
Eran Harary3073d8c2013-12-29 14:09:59 +0200322 iwl_write_prph(trans, APMG_CLK_EN_REG,
323 APMG_CLK_VAL_DMA_CLK_RQT);
324 udelay(20);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200325
Eran Harary3073d8c2013-12-29 14:09:59 +0200326 /* Disable L1-Active */
327 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
328 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200329
Eran Harary3073d8c2013-12-29 14:09:59 +0200330 /* Clear the interrupt in APMG if the NIC is in RFKILL */
331 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
332 APMG_RTC_INT_STT_RFKILL);
333 }
Emmanuel Grumbach889b1692013-07-25 13:14:34 +0300334
Arik Nemtsoveb7ff772013-12-01 12:30:38 +0200335 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200336
337out:
338 return ret;
339}
340
Alexander Bondara812cba2014-02-18 16:45:00 +0100341/*
342 * Enable LP XTAL to avoid HW bug where device may consume much power if
343 * FW is not loaded after device reset. LP XTAL is disabled by default
344 * after device HW reset. Do it only if XTAL is fed by internal source.
345 * Configure device's "persistence" mode to avoid resetting XTAL again when
346 * SHRD_HW_RST occurs in S3.
347 */
348static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
349{
350 int ret;
351 u32 apmg_gp1_reg;
352 u32 apmg_xtal_cfg_reg;
353 u32 dl_cfg_reg;
354
355 /* Force XTAL ON */
356 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
357 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
358
359 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
360 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
361
362 udelay(10);
363
364 /*
365 * Set "initialization complete" bit to move adapter from
366 * D0U* --> D0A* (powered-up active) state.
367 */
368 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
369
370 /*
371 * Wait for clock stabilization; once stabilized, access to
372 * device-internal resources is possible.
373 */
374 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
375 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
377 25000);
378 if (WARN_ON(ret < 0)) {
379 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
380 /* Release XTAL ON request */
381 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
382 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
383 return;
384 }
385
386 /*
387 * Clear "disable persistence" to avoid LP XTAL resetting when
388 * SHRD_HW_RST is applied in S3.
389 */
390 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
391 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
392
393 /*
394 * Force APMG XTAL to be active to prevent its disabling by HW
395 * caused by APMG idle state.
396 */
397 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
398 SHR_APMG_XTAL_CFG_REG);
399 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
400 apmg_xtal_cfg_reg |
401 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
402
403 /*
404 * Reset entire device again - do controller reset (results in
405 * SHRD_HW_RST). Turn MAC off before proceeding.
406 */
407 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
408
409 udelay(10);
410
411 /* Enable LP XTAL by indirect access through CSR */
412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
414 SHR_APMG_GP1_WF_XTAL_LP_EN |
415 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
416
417 /* Clear delay line clock power up */
418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
421
422 /*
423 * Enable persistence mode to avoid LP XTAL resetting when
424 * SHRD_HW_RST is applied in S3.
425 */
426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
428
429 /*
430 * Clear "initialization complete" bit to move adapter from
431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
432 */
433 iwl_clear_bit(trans, CSR_GP_CNTRL,
434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
435
436 /* Activates XTAL resources monitor */
437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
438 CSR_MONITOR_XTAL_RESOURCES);
439
440 /* Release XTAL ON request */
441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
443 udelay(10);
444
445 /* Release APMG XTAL */
446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
447 apmg_xtal_cfg_reg &
448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
449}
450
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200451static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200452{
453 int ret = 0;
454
455 /* stop device's busmaster DMA activity */
456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
457
458 ret = iwl_poll_bit(trans, CSR_RESET,
Johannes Berg20d3b642012-05-16 22:54:29 +0200459 CSR_RESET_REG_FLAG_MASTER_DISABLED,
460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
Emmanuel Grumbach7f2ac8f2014-10-23 08:53:21 +0300461 if (ret < 0)
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
463
464 IWL_DEBUG_INFO(trans, "stop master\n");
465
466 return ret;
467}
468
Emmanuel Grumbachb7aaeae2014-12-07 19:44:30 +0200469static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200470{
471 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
472
Emmanuel Grumbachb7aaeae2014-12-07 19:44:30 +0200473 if (op_mode_leave) {
474 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
475 iwl_pcie_apm_init(trans);
476
477 /* inform ME that we are leaving */
478 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
479 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
480 APMG_PCIDEV_STT_VAL_WAKE_ME);
481 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
482 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
483 CSR_HW_IF_CONFIG_REG_PREPARE |
484 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
485 mdelay(5);
486 }
487
Arik Nemtsoveb7ff772013-12-01 12:30:38 +0200488 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200489
490 /* Stop device's DMA activity */
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200491 iwl_pcie_apm_stop_master(trans);
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200492
Alexander Bondara812cba2014-02-18 16:45:00 +0100493 if (trans->cfg->lp_xtal_workaround) {
494 iwl_pcie_apm_lp_xtal_enable(trans);
495 return;
496 }
497
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200498 /* Reset the entire device */
499 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
500
501 udelay(10);
502
503 /*
504 * Clear "initialization complete" bit to move adapter from
505 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
506 */
507 iwl_clear_bit(trans, CSR_GP_CNTRL,
508 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
509}
510
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200511static int iwl_pcie_nic_init(struct iwl_trans *trans)
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300512{
Johannes Berg7b114882012-02-05 13:55:11 -0800513 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300514
515 /* nic_init */
Emmanuel Grumbach7b70bd62013-12-11 10:22:28 +0200516 spin_lock(&trans_pcie->irq_lock);
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200517 iwl_pcie_apm_init(trans);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300518
Emmanuel Grumbach7b70bd62013-12-11 10:22:28 +0200519 spin_unlock(&trans_pcie->irq_lock);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300520
Avri Altman95411d02015-05-11 11:04:34 +0300521 iwl_pcie_set_pwr(trans, false);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300522
Johannes Bergecdb9752012-03-06 13:31:03 -0800523 iwl_op_mode_nic_config(trans->op_mode);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300524
525 /* Allocate the RX queue, or reset if it is already allocated */
Emmanuel Grumbach9805c4462012-11-14 14:44:18 +0200526 iwl_pcie_rx_init(trans);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300527
528 /* Allocate or reset and init all Tx and Command queues */
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200529 if (iwl_pcie_tx_init(trans))
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300530 return -ENOMEM;
531
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -0700532 if (trans->cfg->base_params->shadow_reg_enable) {
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300533 /* enable shadow regs in HW */
Johannes Berg20d3b642012-05-16 22:54:29 +0200534 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
Meenakshi Venkataramand38069d2012-05-16 22:54:30 +0200535 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300536 }
537
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300538 return 0;
539}
540
541#define HW_READY_TIMEOUT (50)
542
543/* Note: returns poll_bit return value, which is >= 0 if success */
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200544static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300545{
546 int ret;
547
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200548 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
Johannes Berg20d3b642012-05-16 22:54:29 +0200549 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300550
551 /* See if we got it */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200552 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
Johannes Berg20d3b642012-05-16 22:54:29 +0200553 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
555 HW_READY_TIMEOUT);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300556
Emmanuel Grumbach6a08f512014-11-04 20:16:00 +0200557 if (ret >= 0)
558 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
559
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700560 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300561 return ret;
562}
563
564/* Note: returns standard 0/-ERROR code */
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200565static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300566{
567 int ret;
Emmanuel Grumbach289e5502012-08-05 16:55:06 +0300568 int t = 0;
Emmanuel Grumbach501fd982014-05-08 12:15:22 +0300569 int iter;
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300570
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700571 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300572
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200573 ret = iwl_pcie_set_hw_ready(trans);
Emmanuel Grumbachebb76782012-01-08 13:24:57 +0200574 /* If the card is ready, exit 0 */
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300575 if (ret >= 0)
576 return 0;
577
Emmanuel Grumbach501fd982014-05-08 12:15:22 +0300578 for (iter = 0; iter < 10; iter++) {
579 /* If HW is not ready, prepare the conditions to check again */
580 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
581 CSR_HW_IF_CONFIG_REG_PREPARE);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300582
Emmanuel Grumbach501fd982014-05-08 12:15:22 +0300583 do {
584 ret = iwl_pcie_set_hw_ready(trans);
585 if (ret >= 0)
586 return 0;
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300587
Emmanuel Grumbach501fd982014-05-08 12:15:22 +0300588 usleep_range(200, 1000);
589 t += 200;
590 } while (t < 150000);
591 msleep(25);
592 }
593
Emmanuel Grumbach7f2ac8f2014-10-23 08:53:21 +0300594 IWL_ERR(trans, "Couldn't prepare the card\n");
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300595
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300596 return ret;
597}
598
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200599/*
600 * ucode
601 */
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200602static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
Johannes Berg83f84d72012-09-10 11:50:18 +0200603 dma_addr_t phy_addr, u32 byte_cnt)
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200604{
Johannes Berg13df1aa2012-03-06 13:31:00 -0800605 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200606 int ret;
607
Johannes Berg13df1aa2012-03-06 13:31:00 -0800608 trans_pcie->ucode_write_complete = false;
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200609
610 iwl_write_direct32(trans,
Johannes Berg20d3b642012-05-16 22:54:29 +0200611 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
612 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200613
614 iwl_write_direct32(trans,
Johannes Berg20d3b642012-05-16 22:54:29 +0200615 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
616 dst_addr);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200617
618 iwl_write_direct32(trans,
Johannes Berg83f84d72012-09-10 11:50:18 +0200619 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
620 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200621
622 iwl_write_direct32(trans,
Johannes Berg20d3b642012-05-16 22:54:29 +0200623 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
624 (iwl_get_dma_hi_addr(phy_addr)
625 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200626
627 iwl_write_direct32(trans,
Johannes Berg20d3b642012-05-16 22:54:29 +0200628 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
629 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
630 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
631 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200632
633 iwl_write_direct32(trans,
Johannes Berg20d3b642012-05-16 22:54:29 +0200634 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
636 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
637 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200638
Johannes Berg13df1aa2012-03-06 13:31:00 -0800639 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
640 trans_pcie->ucode_write_complete, 5 * HZ);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200641 if (!ret) {
Johannes Berg83f84d72012-09-10 11:50:18 +0200642 IWL_ERR(trans, "Failed to load firmware chunk!\n");
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200643 return -ETIMEDOUT;
644 }
645
646 return 0;
647}
648
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200649static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
Johannes Berg83f84d72012-09-10 11:50:18 +0200650 const struct fw_desc *section)
651{
652 u8 *v_addr;
653 dma_addr_t p_addr;
Liad Kaufmanbaa21e82014-12-02 14:28:45 +0200654 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
Johannes Berg83f84d72012-09-10 11:50:18 +0200655 int ret = 0;
656
657 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
658 section_num);
659
Emmanuel Grumbachc5715732013-04-30 14:33:04 +0300660 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
661 GFP_KERNEL | __GFP_NOWARN);
662 if (!v_addr) {
663 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
664 chunk_sz = PAGE_SIZE;
665 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
666 &p_addr, GFP_KERNEL);
667 if (!v_addr)
668 return -ENOMEM;
669 }
Johannes Berg83f84d72012-09-10 11:50:18 +0200670
Emmanuel Grumbachc5715732013-04-30 14:33:04 +0300671 for (offset = 0; offset < section->len; offset += chunk_sz) {
Arik Nemtsovfe457732014-11-17 15:46:37 +0200672 u32 copy_size, dst_addr;
673 bool extended_addr = false;
Johannes Berg83f84d72012-09-10 11:50:18 +0200674
Emmanuel Grumbachc5715732013-04-30 14:33:04 +0300675 copy_size = min_t(u32, chunk_sz, section->len - offset);
Arik Nemtsovfe457732014-11-17 15:46:37 +0200676 dst_addr = section->offset + offset;
677
678 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
679 dst_addr <= IWL_FW_MEM_EXTENDED_END)
680 extended_addr = true;
681
682 if (extended_addr)
683 iwl_set_bits_prph(trans, LMPM_CHICK,
684 LMPM_CHICK_EXTENDED_ADDR_SPACE);
Johannes Berg83f84d72012-09-10 11:50:18 +0200685
686 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
Arik Nemtsovfe457732014-11-17 15:46:37 +0200687 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
688 copy_size);
689
690 if (extended_addr)
691 iwl_clear_bits_prph(trans, LMPM_CHICK,
692 LMPM_CHICK_EXTENDED_ADDR_SPACE);
693
Johannes Berg83f84d72012-09-10 11:50:18 +0200694 if (ret) {
695 IWL_ERR(trans,
696 "Could not load the [%d] uCode section\n",
697 section_num);
698 break;
699 }
700 }
701
Emmanuel Grumbachc5715732013-04-30 14:33:04 +0300702 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
Johannes Berg83f84d72012-09-10 11:50:18 +0200703 return ret;
704}
705
Eran Harary16bc1192015-03-03 13:53:28 +0200706/*
707 * Driver Takes the ownership on secure machine before FW load
708 * and prevent race with the BT load.
709 * W/A for ROM bug. (should be remove in the next Si step)
710 */
711static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
712{
713 u32 val, loop = 1000;
714
Eran Harary1e167072015-03-19 13:01:07 +0200715 /*
716 * Check the RSA semaphore is accessible.
717 * If the HW isn't locked and the rsa semaphore isn't accessible,
718 * we are in trouble.
719 */
Eran Harary16bc1192015-03-03 13:53:28 +0200720 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
721 if (val & (BIT(1) | BIT(17))) {
Eran Harary1e167072015-03-19 13:01:07 +0200722 IWL_INFO(trans,
723 "can't access the RSA semaphore it is write protected\n");
Eran Harary16bc1192015-03-03 13:53:28 +0200724 return 0;
725 }
726
727 /* take ownership on the AUX IF */
728 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
729 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
730
731 do {
732 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
733 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
734 if (val == 0x1) {
735 iwl_write_prph(trans, RSA_ENABLE, 0);
736 return 0;
737 }
738
739 udelay(10);
740 loop--;
741 } while (loop > 0);
742
743 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
744 return -EIO;
745}
746
Emmanuel Grumbach5dd9c682015-03-05 13:06:13 +0200747static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
748 const struct fw_img *image,
749 int cpu,
750 int *first_ucode_section)
Eran Hararye2d6f4e2013-10-02 13:53:40 +0300751{
752 int shift_param;
Eran Hararydcab8ec2014-10-19 12:20:14 +0200753 int i, ret = 0, sec_num = 0x1;
754 u32 val, last_read_idx = 0;
Eran Hararye2d6f4e2013-10-02 13:53:40 +0300755
756 if (cpu == 1) {
757 shift_param = 0;
Eran Harary034846c2014-01-29 08:10:17 +0200758 *first_ucode_section = 0;
Eran Hararye2d6f4e2013-10-02 13:53:40 +0300759 } else {
760 shift_param = 16;
Eran Harary034846c2014-01-29 08:10:17 +0200761 (*first_ucode_section)++;
Eran Hararye2d6f4e2013-10-02 13:53:40 +0300762 }
763
Eran Harary034846c2014-01-29 08:10:17 +0200764 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
765 last_read_idx = i;
766
767 if (!image->sec[i].data ||
768 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
769 IWL_DEBUG_FW(trans,
770 "Break since Data not valid or Empty section, sec = %d\n",
771 i);
Eran Harary189fa2f2014-01-23 16:26:32 +0200772 break;
Eran Harary034846c2014-01-29 08:10:17 +0200773 }
774
Eran Harary189fa2f2014-01-23 16:26:32 +0200775 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
776 if (ret)
777 return ret;
Eran Hararydcab8ec2014-10-19 12:20:14 +0200778
779 /* Notify the ucode of the loaded section number and status */
780 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
781 val = val | (sec_num << shift_param);
782 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
783 sec_num = (sec_num << 1) | 0x1;
Eran Harary189fa2f2014-01-23 16:26:32 +0200784 }
Eran Hararye2d6f4e2013-10-02 13:53:40 +0300785
Eran Harary034846c2014-01-29 08:10:17 +0200786 *first_ucode_section = last_read_idx;
787
Eran Hararyafb88912015-01-20 15:37:34 +0200788 if (cpu == 1)
789 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
790 else
791 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
792
Eran Harary189fa2f2014-01-23 16:26:32 +0200793 return 0;
794}
Eran Hararye2d6f4e2013-10-02 13:53:40 +0300795
Eran Harary189fa2f2014-01-23 16:26:32 +0200796static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
797 const struct fw_img *image,
Eran Harary034846c2014-01-29 08:10:17 +0200798 int cpu,
799 int *first_ucode_section)
Eran Harary189fa2f2014-01-23 16:26:32 +0200800{
801 int shift_param;
Eran Harary189fa2f2014-01-23 16:26:32 +0200802 int i, ret = 0;
Eran Harary034846c2014-01-29 08:10:17 +0200803 u32 last_read_idx = 0;
Eran Harary189fa2f2014-01-23 16:26:32 +0200804
805 if (cpu == 1) {
806 shift_param = 0;
Eran Harary034846c2014-01-29 08:10:17 +0200807 *first_ucode_section = 0;
Eran Harary189fa2f2014-01-23 16:26:32 +0200808 } else {
809 shift_param = 16;
Eran Harary034846c2014-01-29 08:10:17 +0200810 (*first_ucode_section)++;
Eran Hararye2d6f4e2013-10-02 13:53:40 +0300811 }
812
Eran Harary034846c2014-01-29 08:10:17 +0200813 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
814 last_read_idx = i;
815
816 if (!image->sec[i].data ||
817 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
818 IWL_DEBUG_FW(trans,
819 "Break since Data not valid or Empty section, sec = %d\n",
820 i);
Eran Harary189fa2f2014-01-23 16:26:32 +0200821 break;
Eran Harary034846c2014-01-29 08:10:17 +0200822 }
823
Eran Harary189fa2f2014-01-23 16:26:32 +0200824 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
825 if (ret)
826 return ret;
Eran Hararye2d6f4e2013-10-02 13:53:40 +0300827 }
828
Eran Harary189fa2f2014-01-23 16:26:32 +0200829 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
830 iwl_set_bits_prph(trans,
831 CSR_UCODE_LOAD_STATUS_ADDR,
832 (LMPM_CPU_UCODE_LOADING_COMPLETED |
833 LMPM_CPU_HDRS_LOADING_COMPLETED |
834 LMPM_CPU_UCODE_LOADING_STARTED) <<
835 shift_param);
836
Eran Harary034846c2014-01-29 08:10:17 +0200837 *first_ucode_section = last_read_idx;
838
Eran Hararye2d6f4e2013-10-02 13:53:40 +0300839 return 0;
840}
841
Liad Kaufman09e350f2014-11-17 11:41:07 +0200842static void iwl_pcie_apply_destination(struct iwl_trans *trans)
843{
844 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
845 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
846 int i;
847
848 if (dest->version)
849 IWL_ERR(trans,
850 "DBG DEST version is %d - expect issues\n",
851 dest->version);
852
853 IWL_INFO(trans, "Applying debug destination %s\n",
854 get_fw_dbg_mode_string(dest->monitor_mode));
855
856 if (dest->monitor_mode == EXTERNAL_MODE)
Emmanuel Grumbach96c285d2015-04-14 23:14:48 +0300857 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
Liad Kaufman09e350f2014-11-17 11:41:07 +0200858 else
859 IWL_WARN(trans, "PCI should have external buffer debug\n");
860
861 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
862 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
863 u32 val = le32_to_cpu(dest->reg_ops[i].val);
864
865 switch (dest->reg_ops[i].op) {
866 case CSR_ASSIGN:
867 iwl_write32(trans, addr, val);
868 break;
869 case CSR_SETBIT:
870 iwl_set_bit(trans, addr, BIT(val));
871 break;
872 case CSR_CLEARBIT:
873 iwl_clear_bit(trans, addr, BIT(val));
874 break;
875 case PRPH_ASSIGN:
876 iwl_write_prph(trans, addr, val);
877 break;
878 case PRPH_SETBIT:
879 iwl_set_bits_prph(trans, addr, BIT(val));
880 break;
881 case PRPH_CLEARBIT:
882 iwl_clear_bits_prph(trans, addr, BIT(val));
883 break;
884 default:
885 IWL_ERR(trans, "FW debug - unknown OP %d\n",
886 dest->reg_ops[i].op);
887 break;
888 }
889 }
890
891 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
892 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
893 trans_pcie->fw_mon_phys >> dest->base_shift);
894 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
895 (trans_pcie->fw_mon_phys +
896 trans_pcie->fw_mon_size) >> dest->end_shift);
897 }
898}
899
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200900static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
Johannes Berg0692fe42012-03-06 13:30:37 -0800901 const struct fw_img *image)
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200902{
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +0300903 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Eran Harary189fa2f2014-01-23 16:26:32 +0200904 int ret = 0;
Eran Harary034846c2014-01-29 08:10:17 +0200905 int first_ucode_section;
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200906
Eran Hararydcab8ec2014-10-19 12:20:14 +0200907 IWL_DEBUG_FW(trans, "working with %s CPU\n",
Eran Hararye2d6f4e2013-10-02 13:53:40 +0300908 image->is_dual_cpus ? "Dual" : "Single");
909
Eran Hararydcab8ec2014-10-19 12:20:14 +0200910 /* load to FW the binary non secured sections of CPU1 */
911 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
912 if (ret)
913 return ret;
Eran Hararye2d6f4e2013-10-02 13:53:40 +0300914
915 if (image->is_dual_cpus) {
Eran Harary189fa2f2014-01-23 16:26:32 +0200916 /* set CPU2 header address */
917 iwl_write_prph(trans,
918 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
919 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
Eran Hararye2d6f4e2013-10-02 13:53:40 +0300920
Eran Harary189fa2f2014-01-23 16:26:32 +0200921 /* load to FW the binary sections of CPU2 */
Eran Hararydcab8ec2014-10-19 12:20:14 +0200922 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
923 &first_ucode_section);
Eran Harary189fa2f2014-01-23 16:26:32 +0200924 if (ret)
925 return ret;
Eran Hararye2d6f4e2013-10-02 13:53:40 +0300926 }
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200927
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +0300928 /* supported for 7000 only for the moment */
929 if (iwlwifi_mod_params.fw_monitor &&
930 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
Emmanuel Grumbach96c285d2015-04-14 23:14:48 +0300931 iwl_pcie_alloc_fw_monitor(trans, 0);
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +0300932
933 if (trans_pcie->fw_mon_size) {
934 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
935 trans_pcie->fw_mon_phys >> 4);
936 iwl_write_prph(trans, MON_BUFF_END_ADDR,
937 (trans_pcie->fw_mon_phys +
938 trans_pcie->fw_mon_size) >> 4);
939 }
Liad Kaufman09e350f2014-11-17 11:41:07 +0200940 } else if (trans->dbg_dest_tlv) {
941 iwl_pcie_apply_destination(trans);
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +0300942 }
943
Eran Hararye12ba842013-12-02 12:18:10 +0200944 /* release CPU reset */
Emmanuel Grumbach5dd9c682015-03-05 13:06:13 +0200945 iwl_write32(trans, CSR_RESET, 0);
Eran Hararye12ba842013-12-02 12:18:10 +0200946
Eran Hararydcab8ec2014-10-19 12:20:14 +0200947 return 0;
948}
Eran Harary189fa2f2014-01-23 16:26:32 +0200949
Emmanuel Grumbach5dd9c682015-03-05 13:06:13 +0200950static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
951 const struct fw_img *image)
Eran Hararydcab8ec2014-10-19 12:20:14 +0200952{
953 int ret = 0;
954 int first_ucode_section;
Eran Hararydcab8ec2014-10-19 12:20:14 +0200955
956 IWL_DEBUG_FW(trans, "working with %s CPU\n",
957 image->is_dual_cpus ? "Dual" : "Single");
958
Emmanuel Grumbacha2227ce2015-02-04 16:35:03 +0200959 if (trans->dbg_dest_tlv)
960 iwl_pcie_apply_destination(trans);
961
Eran Harary16bc1192015-03-03 13:53:28 +0200962 /* TODO: remove in the next Si step */
963 ret = iwl_pcie_rsa_race_bug_wa(trans);
964 if (ret)
965 return ret;
966
Eran Hararydcab8ec2014-10-19 12:20:14 +0200967 /* configure the ucode to be ready to get the secured image */
968 /* release CPU reset */
969 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
970
971 /* load to FW the binary Secured sections of CPU1 */
Emmanuel Grumbach5dd9c682015-03-05 13:06:13 +0200972 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
973 &first_ucode_section);
Eran Hararydcab8ec2014-10-19 12:20:14 +0200974 if (ret)
975 return ret;
976
977 /* load to FW the binary sections of CPU2 */
Emmanuel Grumbach47dbab22015-04-28 21:32:47 +0300978 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
979 &first_ucode_section);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200980}
981
Johannes Berg0692fe42012-03-06 13:30:37 -0800982static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
Emmanuel Grumbach6ae02f32012-12-24 11:10:43 +0200983 const struct fw_img *fw, bool run_in_rfkill)
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300984{
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +0300985 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Johannes Bergc9eec952012-03-06 13:30:43 -0800986 bool hw_rfkill;
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +0300987 int ret;
988
989 mutex_lock(&trans_pcie->mutex);
990
991 /* Someone called stop_device, don't try to start_fw */
992 if (trans_pcie->is_down) {
993 IWL_WARN(trans,
994 "Can't start_fw since the HW hasn't been started\n");
995 ret = EIO;
996 goto out;
997 }
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300998
Johannes Berg496bab32012-03-06 13:30:45 -0800999 /* This may fail if AMT took ownership of the device */
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +02001000 if (iwl_pcie_prepare_card_hw(trans)) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001001 IWL_WARN(trans, "Exit HW not ready\n");
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001002 ret = -EIO;
1003 goto out;
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +03001004 }
1005
Emmanuel Grumbach8c46bb72012-03-28 09:57:46 +02001006 iwl_enable_rfkill_int(trans);
1007
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +03001008 /* If platform's RF_KILL switch is NOT set to KILL */
Emmanuel Grumbach8d425512012-03-28 11:00:58 +02001009 hw_rfkill = iwl_is_rfkill_set(trans);
Emmanuel Grumbach46200202013-03-13 16:38:32 +02001010 if (hw_rfkill)
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001011 set_bit(STATUS_RFKILL, &trans->status);
Emmanuel Grumbach46200202013-03-13 16:38:32 +02001012 else
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001013 clear_bit(STATUS_RFKILL, &trans->status);
Johannes Berg14cfca72014-02-25 20:50:53 +01001014 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001015 if (hw_rfkill && !run_in_rfkill) {
1016 ret = -ERFKILL;
1017 goto out;
1018 }
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +03001019
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001020 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +03001021
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +02001022 ret = iwl_pcie_nic_init(trans);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +03001023 if (ret) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001024 IWL_ERR(trans, "Unable to init nic\n");
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001025 goto out;
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +03001026 }
1027
1028 /* make sure rfkill handshake bits are cleared */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001029 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1030 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +03001031 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1032
1033 /* clear (again), then enable host interrupts */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001034 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001035 iwl_enable_interrupts(trans);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +03001036
1037 /* really make sure rfkill handshake bits are cleared */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001038 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1039 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +03001040
Emmanuel Grumbachcf614292012-01-08 16:33:58 +02001041 /* Load the given image to the HW */
Emmanuel Grumbach5dd9c682015-03-05 13:06:13 +02001042 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001043 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
Eran Hararydcab8ec2014-10-19 12:20:14 +02001044 else
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001045 ret = iwl_pcie_load_given_ucode(trans, fw);
1046
1047out:
1048 mutex_unlock(&trans_pcie->mutex);
1049 return ret;
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001050}
1051
Emmanuel Grumbachadca1232012-10-25 23:08:27 +02001052static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
Emmanuel Grumbached6a3802012-01-02 16:10:08 +02001053{
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001054 iwl_pcie_reset_ict(trans);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001055 iwl_pcie_tx_start(trans, scd_addr);
Emmanuel Grumbachc170b862011-07-08 08:46:12 -07001056}
1057
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001058static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
Emmanuel Grumbachae2c30b2011-08-25 23:11:20 -07001059{
Emmanuel Grumbach43e58852011-11-09 16:50:50 -08001060 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach3dc33742013-12-22 15:13:01 +02001061 bool hw_rfkill, was_hw_rfkill;
1062
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001063 lockdep_assert_held(&trans_pcie->mutex);
1064
1065 if (trans_pcie->is_down)
1066 return;
1067
1068 trans_pcie->is_down = true;
1069
Emmanuel Grumbach3dc33742013-12-22 15:13:01 +02001070 was_hw_rfkill = iwl_is_rfkill_set(trans);
Emmanuel Grumbachae2c30b2011-08-25 23:11:20 -07001071
Emmanuel Grumbach43e58852011-11-09 16:50:50 -08001072 /* tell the device to stop sending interrupts */
Emmanuel Grumbach7b70bd62013-12-11 10:22:28 +02001073 spin_lock(&trans_pcie->irq_lock);
Emmanuel Grumbachae2c30b2011-08-25 23:11:20 -07001074 iwl_disable_interrupts(trans);
Emmanuel Grumbach7b70bd62013-12-11 10:22:28 +02001075 spin_unlock(&trans_pcie->irq_lock);
Emmanuel Grumbachae2c30b2011-08-25 23:11:20 -07001076
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +03001077 /* device going down, Stop using ICT table */
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001078 iwl_pcie_disable_ict(trans);
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +03001079
1080 /*
1081 * If a HW restart happens during firmware loading,
1082 * then the firmware loading might call this function
1083 * and later it might be called again due to the
1084 * restart. So don't process again if the device is
1085 * already dead.
1086 */
Emmanuel Grumbach31b8b342014-11-02 15:48:09 +02001087 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1088 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001089 iwl_pcie_tx_stop(trans);
Emmanuel Grumbach9805c4462012-11-14 14:44:18 +02001090 iwl_pcie_rx_stop(trans);
Johannes Berg63791032012-09-06 15:33:42 +02001091
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +03001092 /* Power-down device's busmaster DMA clocks */
Avri Altman95411d02015-05-11 11:04:34 +03001093 if (!trans->cfg->apmg_not_supported) {
Avri Altman1aa02b52015-04-29 05:11:10 +03001094 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1095 APMG_CLK_VAL_DMA_CLK_RQT);
1096 udelay(5);
1097 }
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +03001098 }
1099
1100 /* Make sure (redundant) we've released our request to stay awake */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001101 iwl_clear_bit(trans, CSR_GP_CNTRL,
Johannes Berg20d3b642012-05-16 22:54:29 +02001102 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +03001103
1104 /* Stop the device, and put it in low power state */
Emmanuel Grumbachb7aaeae2014-12-07 19:44:30 +02001105 iwl_pcie_apm_stop(trans, false);
Emmanuel Grumbach43e58852011-11-09 16:50:50 -08001106
Emmanuel Grumbach03d6c3b2014-12-03 10:39:07 +02001107 /* stop and reset the on-board processor */
1108 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1109 udelay(20);
1110
1111 /*
1112 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1113 * This is a bug in certain verions of the hardware.
1114 * Certain devices also keep sending HW RF kill interrupt all
1115 * the time, unless the interrupt is ACKed even if the interrupt
1116 * should be masked. Re-ACK all the interrupts here.
Emmanuel Grumbach43e58852011-11-09 16:50:50 -08001117 */
Emmanuel Grumbach7b70bd62013-12-11 10:22:28 +02001118 spin_lock(&trans_pcie->irq_lock);
Emmanuel Grumbach43e58852011-11-09 16:50:50 -08001119 iwl_disable_interrupts(trans);
Emmanuel Grumbach7b70bd62013-12-11 10:22:28 +02001120 spin_unlock(&trans_pcie->irq_lock);
Emmanuel Grumbach43e58852011-11-09 16:50:50 -08001121
Don Fry74fda972012-03-20 16:36:54 -07001122
1123 /* clear all status bits */
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001124 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1125 clear_bit(STATUS_INT_ENABLED, &trans->status);
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001126 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1127 clear_bit(STATUS_RFKILL, &trans->status);
Arik Nemtsova4082842013-11-24 19:10:46 +02001128
1129 /*
1130 * Even if we stop the HW, we still want the RF kill
1131 * interrupt
1132 */
1133 iwl_enable_rfkill_int(trans);
1134
1135 /*
1136 * Check again since the RF kill state may have changed while
1137 * all the interrupts were disabled, in this case we couldn't
1138 * receive the RF kill interrupt and update the state in the
1139 * op_mode.
Emmanuel Grumbach3dc33742013-12-22 15:13:01 +02001140 * Don't call the op_mode if the rkfill state hasn't changed.
1141 * This allows the op_mode to call stop_device from the rfkill
1142 * notification without endless recursion. Under very rare
1143 * circumstances, we might have a small recursion if the rfkill
1144 * state changed exactly now while we were called from stop_device.
1145 * This is very unlikely but can happen and is supported.
Arik Nemtsova4082842013-11-24 19:10:46 +02001146 */
1147 hw_rfkill = iwl_is_rfkill_set(trans);
1148 if (hw_rfkill)
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001149 set_bit(STATUS_RFKILL, &trans->status);
Arik Nemtsova4082842013-11-24 19:10:46 +02001150 else
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001151 clear_bit(STATUS_RFKILL, &trans->status);
Emmanuel Grumbach3dc33742013-12-22 15:13:01 +02001152 if (hw_rfkill != was_hw_rfkill)
Johannes Berg14cfca72014-02-25 20:50:53 +01001153 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
Emmanuel Grumbach655e5cf2014-11-30 17:06:11 +02001154
1155 /* re-take ownership to prevent other users from stealing the deivce */
1156 iwl_pcie_prepare_card_hw(trans);
Johannes Berg14cfca72014-02-25 20:50:53 +01001157}
1158
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001159static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1160{
1161 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1162
1163 mutex_lock(&trans_pcie->mutex);
1164 _iwl_trans_pcie_stop_device(trans, low_power);
1165 mutex_unlock(&trans_pcie->mutex);
1166}
1167
Johannes Berg14cfca72014-02-25 20:50:53 +01001168void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1169{
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001170 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1171 IWL_TRANS_GET_PCIE_TRANS(trans);
1172
1173 lockdep_assert_held(&trans_pcie->mutex);
1174
Johannes Berg14cfca72014-02-25 20:50:53 +01001175 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001176 _iwl_trans_pcie_stop_device(trans, true);
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +03001177}
1178
Johannes Bergdebff612013-05-14 13:53:45 +02001179static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
Johannes Berg2dd4f9f2012-03-05 11:24:35 -08001180{
Johannes Berg2dd4f9f2012-03-05 11:24:35 -08001181 iwl_disable_interrupts(trans);
Johannes Bergdebff612013-05-14 13:53:45 +02001182
1183 /*
1184 * in testing mode, the host stays awake and the
1185 * hardware won't be reset (not even partially)
1186 */
1187 if (test)
1188 return;
1189
Johannes Bergddaf5a52013-01-08 11:25:44 +01001190 iwl_pcie_disable_ict(trans);
1191
Johannes Berg2dd4f9f2012-03-05 11:24:35 -08001192 iwl_clear_bit(trans, CSR_GP_CNTRL,
1193 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
Johannes Bergddaf5a52013-01-08 11:25:44 +01001194 iwl_clear_bit(trans, CSR_GP_CNTRL,
1195 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1196
1197 /*
1198 * reset TX queues -- some of their registers reset during S3
1199 * so if we don't reset everything here the D3 image would try
1200 * to execute some invalid memory upon resume
1201 */
1202 iwl_trans_pcie_tx_reset(trans);
1203
1204 iwl_pcie_set_pwr(trans, true);
1205}
1206
1207static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
Johannes Bergdebff612013-05-14 13:53:45 +02001208 enum iwl_d3_status *status,
1209 bool test)
Johannes Bergddaf5a52013-01-08 11:25:44 +01001210{
1211 u32 val;
1212 int ret;
1213
Johannes Bergdebff612013-05-14 13:53:45 +02001214 if (test) {
1215 iwl_enable_interrupts(trans);
1216 *status = IWL_D3_STATUS_ALIVE;
1217 return 0;
1218 }
1219
Johannes Bergddaf5a52013-01-08 11:25:44 +01001220 /*
1221 * Also enables interrupts - none will happen as the device doesn't
1222 * know we're waking it up, only when the opmode actually tells it
1223 * after this call.
1224 */
1225 iwl_pcie_reset_ict(trans);
1226
1227 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1228 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1229
Emmanuel Grumbach01e58a22014-10-27 09:14:32 +02001230 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1231 udelay(2);
1232
Johannes Bergddaf5a52013-01-08 11:25:44 +01001233 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1234 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1235 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1236 25000);
Emmanuel Grumbach7f2ac8f2014-10-23 08:53:21 +03001237 if (ret < 0) {
Johannes Bergddaf5a52013-01-08 11:25:44 +01001238 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1239 return ret;
1240 }
1241
Emmanuel Grumbacha3ead652014-10-12 13:23:40 +03001242 iwl_pcie_set_pwr(trans, false);
1243
Johannes Bergddaf5a52013-01-08 11:25:44 +01001244 iwl_trans_pcie_tx_reset(trans);
1245
1246 ret = iwl_pcie_rx_init(trans);
1247 if (ret) {
1248 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1249 return ret;
1250 }
1251
Emmanuel Grumbacha3ead652014-10-12 13:23:40 +03001252 val = iwl_read32(trans, CSR_RESET);
1253 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1254 *status = IWL_D3_STATUS_RESET;
1255 else
1256 *status = IWL_D3_STATUS_ALIVE;
1257
Johannes Bergddaf5a52013-01-08 11:25:44 +01001258 return 0;
Johannes Berg2dd4f9f2012-03-05 11:24:35 -08001259}
1260
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001261static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
Emmanuel Grumbacha27367d2011-07-04 09:06:44 +03001262{
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001263 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Johannes Bergc9eec952012-03-06 13:30:43 -08001264 bool hw_rfkill;
Johannes Berga8b691e2012-12-27 23:08:06 +01001265 int err;
Emmanuel Grumbach34c1b7b2011-07-04 08:58:19 +03001266
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001267 lockdep_assert_held(&trans_pcie->mutex);
1268
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +02001269 err = iwl_pcie_prepare_card_hw(trans);
Emmanuel Grumbachebb76782012-01-08 13:24:57 +02001270 if (err) {
Johannes Bergd6f1c312012-06-28 16:49:29 +02001271 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
Johannes Berga8b691e2012-12-27 23:08:06 +01001272 return err;
Emmanuel Grumbachebb76782012-01-08 13:24:57 +02001273 }
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +02001274
Emmanuel Grumbach29974942013-07-24 10:19:06 +03001275 /* Reset the entire device */
Eran Hararyce836c72013-12-11 08:13:50 +02001276 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
Emmanuel Grumbach29974942013-07-24 10:19:06 +03001277
1278 usleep_range(10, 15);
1279
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +02001280 iwl_pcie_apm_init(trans);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +02001281
Emmanuel Grumbach226c02c2012-03-28 10:33:09 +02001282 /* From now on, the op_mode will be kept updated about RF kill state */
1283 iwl_enable_rfkill_int(trans);
1284
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001285 /* Set is_down to false here so that...*/
1286 trans_pcie->is_down = false;
1287
Emmanuel Grumbach8d425512012-03-28 11:00:58 +02001288 hw_rfkill = iwl_is_rfkill_set(trans);
Emmanuel Grumbach46200202013-03-13 16:38:32 +02001289 if (hw_rfkill)
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001290 set_bit(STATUS_RFKILL, &trans->status);
Emmanuel Grumbach46200202013-03-13 16:38:32 +02001291 else
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001292 clear_bit(STATUS_RFKILL, &trans->status);
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001293 /* ... rfkill can call stop_device and set it false if needed */
Johannes Berg14cfca72014-02-25 20:50:53 +01001294 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
Emmanuel Grumbachd48e2072012-01-08 13:48:21 +02001295
Johannes Berga8b691e2012-12-27 23:08:06 +01001296 return 0;
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +03001297}
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07001298
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001299static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1300{
1301 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1302 int ret;
1303
1304 mutex_lock(&trans_pcie->mutex);
1305 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1306 mutex_unlock(&trans_pcie->mutex);
1307
1308 return ret;
1309}
1310
Arik Nemtsova4082842013-11-24 19:10:46 +02001311static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +02001312{
Johannes Berg20d3b642012-05-16 22:54:29 +02001313 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbachd23f78e2012-03-28 10:34:02 +02001314
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001315 mutex_lock(&trans_pcie->mutex);
1316
Arik Nemtsova4082842013-11-24 19:10:46 +02001317 /* disable interrupts - don't enable HW RF kill interrupt */
Emmanuel Grumbach7b70bd62013-12-11 10:22:28 +02001318 spin_lock(&trans_pcie->irq_lock);
David Spinadelee7d7372012-08-12 08:14:04 +03001319 iwl_disable_interrupts(trans);
Emmanuel Grumbach7b70bd62013-12-11 10:22:28 +02001320 spin_unlock(&trans_pcie->irq_lock);
David Spinadelee7d7372012-08-12 08:14:04 +03001321
Emmanuel Grumbachb7aaeae2014-12-07 19:44:30 +02001322 iwl_pcie_apm_stop(trans, true);
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +02001323
Emmanuel Grumbach7b70bd62013-12-11 10:22:28 +02001324 spin_lock(&trans_pcie->irq_lock);
Emmanuel Grumbach218733c2012-03-31 08:28:38 -07001325 iwl_disable_interrupts(trans);
Emmanuel Grumbach7b70bd62013-12-11 10:22:28 +02001326 spin_unlock(&trans_pcie->irq_lock);
Emmanuel Grumbach218733c2012-03-31 08:28:38 -07001327
Emmanuel Grumbach8d96bb62012-12-04 22:53:30 +02001328 iwl_pcie_disable_ict(trans);
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03001329 mutex_unlock(&trans_pcie->mutex);
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +02001330}
1331
Emmanuel Grumbach03905492012-01-03 13:48:07 +02001332static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1333{
Stanislaw Gruszka05f5b972012-03-07 09:52:26 -08001334 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
Emmanuel Grumbach03905492012-01-03 13:48:07 +02001335}
1336
1337static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1338{
Stanislaw Gruszka05f5b972012-03-07 09:52:26 -08001339 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
Emmanuel Grumbach03905492012-01-03 13:48:07 +02001340}
1341
1342static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1343{
Stanislaw Gruszka05f5b972012-03-07 09:52:26 -08001344 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
Emmanuel Grumbach03905492012-01-03 13:48:07 +02001345}
1346
Emmanuel Grumbach6a06b6c2012-12-02 13:07:30 +02001347static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1348{
Amnon Pazf9477c12013-02-27 11:28:16 +02001349 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1350 ((reg & 0x000FFFFF) | (3 << 24)));
Emmanuel Grumbach6a06b6c2012-12-02 13:07:30 +02001351 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1352}
1353
1354static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1355 u32 val)
1356{
1357 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
Amnon Pazf9477c12013-02-27 11:28:16 +02001358 ((addr & 0x000FFFFF) | (3 << 24)));
Emmanuel Grumbach6a06b6c2012-12-02 13:07:30 +02001359 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1360}
1361
Johannes Bergf14d6b32014-03-21 13:30:03 +01001362static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1363{
1364 WARN_ON(1);
1365 return 0;
1366}
1367
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -08001368static void iwl_trans_pcie_configure(struct iwl_trans *trans,
Johannes Berg9eae88f2012-03-15 13:26:52 -07001369 const struct iwl_trans_config *trans_cfg)
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -08001370{
1371 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1372
1373 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
Emmanuel Grumbachb04db9a2012-06-21 11:53:44 +03001374 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
Emmanuel Grumbach4cf677f2015-01-12 14:38:29 +02001375 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
Johannes Bergd663ee72012-03-10 13:00:07 -08001376 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1377 trans_pcie->n_no_reclaim_cmds = 0;
1378 else
1379 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1380 if (trans_pcie->n_no_reclaim_cmds)
1381 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1382 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
Johannes Berg9eae88f2012-03-15 13:26:52 -07001383
Johannes Bergb2cf4102012-04-09 17:46:51 -07001384 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1385 if (trans_pcie->rx_buf_size_8k)
1386 trans_pcie->rx_page_order = get_order(8 * 1024);
1387 else
1388 trans_pcie->rx_page_order = get_order(4 * 1024);
Johannes Berg7c5ba4a2012-04-09 17:46:54 -07001389
Johannes Bergd9fb6462012-03-26 08:23:39 -07001390 trans_pcie->command_names = trans_cfg->command_names;
Emmanuel Grumbach046db342012-12-05 15:07:54 +02001391 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
Emmanuel Grumbach3a736bc2014-09-10 11:16:41 +03001392 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
Johannes Bergf14d6b32014-03-21 13:30:03 +01001393
Eliad Peller483f3ab2015-03-04 10:38:32 +02001394 /* init ref_count to 1 (should be cleared when ucode is loaded) */
1395 trans_pcie->ref_count = 1;
1396
Johannes Bergf14d6b32014-03-21 13:30:03 +01001397 /* Initialize NAPI here - it should be before registering to mac80211
1398 * in the opmode but after the HW struct is allocated.
1399 * As this function may be called again in some corner cases don't
1400 * do anything if NAPI was already initialized.
1401 */
1402 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1403 init_dummy_netdev(&trans_pcie->napi_dev);
1404 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1405 &trans_pcie->napi_dev,
1406 iwl_pcie_dummy_napi_poll, 64);
1407 }
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -08001408}
1409
Johannes Bergd1ff5252012-04-12 06:24:30 -07001410void iwl_trans_pcie_free(struct iwl_trans *trans)
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07001411{
Johannes Berg20d3b642012-05-16 22:54:29 +02001412 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001413
Johannes Berg0aa86df2012-12-27 22:58:21 +01001414 synchronize_irq(trans_pcie->pci_dev->irq);
Johannes Berg0aa86df2012-12-27 22:58:21 +01001415
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001416 iwl_pcie_tx_free(trans);
Emmanuel Grumbach9805c4462012-11-14 14:44:18 +02001417 iwl_pcie_rx_free(trans);
Johannes Berg63791032012-09-06 15:33:42 +02001418
Johannes Berga8b691e2012-12-27 23:08:06 +01001419 free_irq(trans_pcie->pci_dev->irq, trans);
1420 iwl_pcie_free_ict(trans);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001421
1422 pci_disable_msi(trans_pcie->pci_dev);
Stanislaw Gruszka05f5b972012-03-07 09:52:26 -08001423 iounmap(trans_pcie->hw_base);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001424 pci_release_regions(trans_pcie->pci_dev);
1425 pci_disable_device(trans_pcie->pci_dev);
1426
Johannes Bergf14d6b32014-03-21 13:30:03 +01001427 if (trans_pcie->napi.poll)
1428 netif_napi_del(&trans_pcie->napi);
1429
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +03001430 iwl_pcie_free_fw_monitor(trans);
1431
Johannes Berg7b501d12015-05-22 11:28:58 +02001432 iwl_trans_free(trans);
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07001433}
1434
Don Fry47107e82012-03-15 13:27:06 -07001435static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1436{
Don Fry47107e82012-03-15 13:27:06 -07001437 if (state)
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001438 set_bit(STATUS_TPOWER_PMI, &trans->status);
Don Fry47107e82012-03-15 13:27:06 -07001439 else
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001440 clear_bit(STATUS_TPOWER_PMI, &trans->status);
Don Fry47107e82012-03-15 13:27:06 -07001441}
1442
Lilach Edelsteine56b04e2013-01-16 11:34:49 +02001443static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1444 unsigned long *flags)
Emmanuel Grumbach7a65d172012-12-24 15:01:24 +02001445{
1446 int ret;
Johannes Bergcfb4e622013-06-20 22:02:05 +02001447 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1448
1449 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
Emmanuel Grumbach7a65d172012-12-24 15:01:24 +02001450
Ilan Peerfc8a3502015-05-13 14:34:07 +03001451 if (trans_pcie->cmd_hold_nic_awake)
Emmanuel Grumbachb9439492013-12-22 15:09:40 +02001452 goto out;
1453
Emmanuel Grumbach7a65d172012-12-24 15:01:24 +02001454 /* this bit wakes up the NIC */
Lilach Edelsteine139dc42013-01-13 13:31:10 +02001455 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1456 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
Emmanuel Grumbach01e58a22014-10-27 09:14:32 +02001457 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1458 udelay(2);
Emmanuel Grumbach7a65d172012-12-24 15:01:24 +02001459
1460 /*
1461 * These bits say the device is running, and should keep running for
1462 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1463 * but they do not indicate that embedded SRAM is restored yet;
1464 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1465 * to/from host DRAM when sleeping/waking for power-saving.
1466 * Each direction takes approximately 1/4 millisecond; with this
1467 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1468 * series of register accesses are expected (e.g. reading Event Log),
1469 * to keep device from sleeping.
1470 *
1471 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1472 * SRAM is okay/restored. We don't check that here because this call
1473 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1474 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1475 *
1476 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1477 * and do not save/restore SRAM when power cycling.
1478 */
1479 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1480 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1481 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1482 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1483 if (unlikely(ret < 0)) {
1484 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1485 if (!silent) {
1486 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1487 WARN_ONCE(1,
1488 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1489 val);
Johannes Bergcfb4e622013-06-20 22:02:05 +02001490 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
Emmanuel Grumbach7a65d172012-12-24 15:01:24 +02001491 return false;
1492 }
1493 }
1494
Emmanuel Grumbachb9439492013-12-22 15:09:40 +02001495out:
Lilach Edelsteine56b04e2013-01-16 11:34:49 +02001496 /*
1497 * Fool sparse by faking we release the lock - sparse will
1498 * track nic_access anyway.
1499 */
Johannes Bergcfb4e622013-06-20 22:02:05 +02001500 __release(&trans_pcie->reg_lock);
Emmanuel Grumbach7a65d172012-12-24 15:01:24 +02001501 return true;
1502}
1503
Lilach Edelsteine56b04e2013-01-16 11:34:49 +02001504static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1505 unsigned long *flags)
Emmanuel Grumbach7a65d172012-12-24 15:01:24 +02001506{
Johannes Bergcfb4e622013-06-20 22:02:05 +02001507 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Lilach Edelsteine56b04e2013-01-16 11:34:49 +02001508
Johannes Bergcfb4e622013-06-20 22:02:05 +02001509 lockdep_assert_held(&trans_pcie->reg_lock);
Lilach Edelsteine56b04e2013-01-16 11:34:49 +02001510
1511 /*
1512 * Fool sparse by faking we acquiring the lock - sparse will
1513 * track nic_access anyway.
1514 */
Johannes Bergcfb4e622013-06-20 22:02:05 +02001515 __acquire(&trans_pcie->reg_lock);
Lilach Edelsteine56b04e2013-01-16 11:34:49 +02001516
Ilan Peerfc8a3502015-05-13 14:34:07 +03001517 if (trans_pcie->cmd_hold_nic_awake)
Emmanuel Grumbachb9439492013-12-22 15:09:40 +02001518 goto out;
1519
Lilach Edelsteine139dc42013-01-13 13:31:10 +02001520 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1521 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
Emmanuel Grumbach7a65d172012-12-24 15:01:24 +02001522 /*
1523 * Above we read the CSR_GP_CNTRL register, which will flush
1524 * any previous writes, but we need the write that clears the
1525 * MAC_ACCESS_REQ bit to be performed before any other writes
1526 * scheduled on different CPUs (after we drop reg_lock).
1527 */
1528 mmiowb();
Emmanuel Grumbachb9439492013-12-22 15:09:40 +02001529out:
Johannes Bergcfb4e622013-06-20 22:02:05 +02001530 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
Emmanuel Grumbach7a65d172012-12-24 15:01:24 +02001531}
1532
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +02001533static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1534 void *buf, int dwords)
1535{
1536 unsigned long flags;
1537 int offs, ret = 0;
1538 u32 *vals = buf;
1539
Lilach Edelsteine56b04e2013-01-16 11:34:49 +02001540 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +02001541 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1542 for (offs = 0; offs < dwords; offs++)
1543 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
Lilach Edelsteine56b04e2013-01-16 11:34:49 +02001544 iwl_trans_release_nic_access(trans, &flags);
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +02001545 } else {
1546 ret = -EBUSY;
1547 }
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +02001548 return ret;
1549}
1550
1551static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
Emmanuel Grumbachbf0fd5d2013-05-13 17:05:27 +03001552 const void *buf, int dwords)
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +02001553{
1554 unsigned long flags;
1555 int offs, ret = 0;
Emmanuel Grumbachbf0fd5d2013-05-13 17:05:27 +03001556 const u32 *vals = buf;
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +02001557
Lilach Edelsteine56b04e2013-01-16 11:34:49 +02001558 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +02001559 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1560 for (offs = 0; offs < dwords; offs++)
Emmanuel Grumbach01387ff2013-01-09 11:37:59 +02001561 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1562 vals ? vals[offs] : 0);
Lilach Edelsteine56b04e2013-01-16 11:34:49 +02001563 iwl_trans_release_nic_access(trans, &flags);
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +02001564 } else {
1565 ret = -EBUSY;
1566 }
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +02001567 return ret;
1568}
Emmanuel Grumbach7a65d172012-12-24 15:01:24 +02001569
Emmanuel Grumbache0b8d402015-01-20 17:02:40 +02001570static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1571 unsigned long txqs,
1572 bool freeze)
1573{
1574 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1575 int queue;
1576
1577 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1578 struct iwl_txq *txq = &trans_pcie->txq[queue];
1579 unsigned long now;
1580
1581 spin_lock_bh(&txq->lock);
1582
1583 now = jiffies;
1584
1585 if (txq->frozen == freeze)
1586 goto next_queue;
1587
1588 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1589 freeze ? "Freezing" : "Waking", queue);
1590
1591 txq->frozen = freeze;
1592
1593 if (txq->q.read_ptr == txq->q.write_ptr)
1594 goto next_queue;
1595
1596 if (freeze) {
1597 if (unlikely(time_after(now,
1598 txq->stuck_timer.expires))) {
1599 /*
1600 * The timer should have fired, maybe it is
1601 * spinning right now on the lock.
1602 */
1603 goto next_queue;
1604 }
1605 /* remember how long until the timer fires */
1606 txq->frozen_expiry_remainder =
1607 txq->stuck_timer.expires - now;
1608 del_timer(&txq->stuck_timer);
1609 goto next_queue;
1610 }
1611
1612 /*
1613 * Wake a non-empty queue -> arm timer with the
1614 * remainder before it froze
1615 */
1616 mod_timer(&txq->stuck_timer,
1617 now + txq->frozen_expiry_remainder);
1618
1619next_queue:
1620 spin_unlock_bh(&txq->lock);
1621 }
1622}
1623
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07001624#define IWL_FLUSH_WAIT_MS 2000
1625
Emmanuel Grumbach3cafdbe2014-03-24 11:23:51 +02001626static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07001627{
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001628 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001629 struct iwl_txq *txq;
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07001630 struct iwl_queue *q;
1631 int cnt;
1632 unsigned long now = jiffies;
Emmanuel Grumbach1c3fea82013-01-02 12:12:25 +02001633 u32 scd_sram_addr;
1634 u8 buf[16];
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07001635 int ret = 0;
1636
1637 /* waiting for all the tx frames complete might take a while */
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -07001638 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
Emmanuel Grumbachfa1a91f2014-03-24 11:25:48 +02001639 u8 wr_ptr;
1640
Wey-Yi Guy9ba19472012-03-09 10:12:42 -08001641 if (cnt == trans_pcie->cmd_queue)
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07001642 continue;
Emmanuel Grumbach3cafdbe2014-03-24 11:23:51 +02001643 if (!test_bit(cnt, trans_pcie->queue_used))
1644 continue;
1645 if (!(BIT(cnt) & txq_bm))
1646 continue;
Emmanuel Grumbach748fa67c2014-03-27 10:06:29 +02001647
1648 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001649 txq = &trans_pcie->txq[cnt];
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07001650 q = &txq->q;
Emmanuel Grumbachfa1a91f2014-03-24 11:25:48 +02001651 wr_ptr = ACCESS_ONCE(q->write_ptr);
1652
1653 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1654 !time_after(jiffies,
1655 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1656 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1657
1658 if (WARN_ONCE(wr_ptr != write_ptr,
1659 "WR pointer moved while flushing %d -> %d\n",
1660 wr_ptr, write_ptr))
1661 return -ETIMEDOUT;
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07001662 msleep(1);
Emmanuel Grumbachfa1a91f2014-03-24 11:25:48 +02001663 }
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07001664
1665 if (q->read_ptr != q->write_ptr) {
Emmanuel Grumbach1c3fea82013-01-02 12:12:25 +02001666 IWL_ERR(trans,
1667 "fail to flush all tx fifo queues Q %d\n", cnt);
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07001668 ret = -ETIMEDOUT;
1669 break;
1670 }
Emmanuel Grumbach748fa67c2014-03-27 10:06:29 +02001671 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07001672 }
Emmanuel Grumbach1c3fea82013-01-02 12:12:25 +02001673
1674 if (!ret)
1675 return 0;
1676
1677 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1678 txq->q.read_ptr, txq->q.write_ptr);
1679
1680 scd_sram_addr = trans_pcie->scd_base_addr +
1681 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1682 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1683
1684 iwl_print_hex_error(trans, buf, sizeof(buf));
1685
1686 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1687 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1688 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1689
1690 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1691 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1692 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1693 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1694 u32 tbl_dw =
1695 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1696 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1697
1698 if (cnt & 0x1)
1699 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1700 else
1701 tbl_dw = tbl_dw & 0x0000FFFF;
1702
1703 IWL_ERR(trans,
1704 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1705 cnt, active ? "" : "in", fifo, tbl_dw,
Johannes Berg83f32a42014-04-24 09:57:40 +02001706 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1707 (TFD_QUEUE_SIZE_MAX - 1),
Emmanuel Grumbach1c3fea82013-01-02 12:12:25 +02001708 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1709 }
1710
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07001711 return ret;
1712}
1713
Lilach Edelsteine139dc42013-01-13 13:31:10 +02001714static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1715 u32 mask, u32 value)
1716{
Lilach Edelsteine56b04e2013-01-16 11:34:49 +02001717 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Lilach Edelsteine139dc42013-01-13 13:31:10 +02001718 unsigned long flags;
1719
Lilach Edelsteine56b04e2013-01-16 11:34:49 +02001720 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
Lilach Edelsteine139dc42013-01-13 13:31:10 +02001721 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
Lilach Edelsteine56b04e2013-01-16 11:34:49 +02001722 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
Lilach Edelsteine139dc42013-01-13 13:31:10 +02001723}
1724
Eliad Peller7616f332014-11-20 17:33:43 +02001725void iwl_trans_pcie_ref(struct iwl_trans *trans)
1726{
1727 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1728 unsigned long flags;
1729
1730 if (iwlwifi_mod_params.d0i3_disable)
1731 return;
1732
1733 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1734 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1735 trans_pcie->ref_count++;
1736 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1737}
1738
1739void iwl_trans_pcie_unref(struct iwl_trans *trans)
1740{
1741 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1742 unsigned long flags;
1743
1744 if (iwlwifi_mod_params.d0i3_disable)
1745 return;
1746
1747 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1748 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1749 if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1750 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1751 return;
1752 }
1753 trans_pcie->ref_count--;
1754 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1755}
1756
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001757static const char *get_csr_string(int cmd)
1758{
Johannes Bergd9fb6462012-03-26 08:23:39 -07001759#define IWL_CMD(x) case x: return #x
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001760 switch (cmd) {
1761 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1762 IWL_CMD(CSR_INT_COALESCING);
1763 IWL_CMD(CSR_INT);
1764 IWL_CMD(CSR_INT_MASK);
1765 IWL_CMD(CSR_FH_INT_STATUS);
1766 IWL_CMD(CSR_GPIO_IN);
1767 IWL_CMD(CSR_RESET);
1768 IWL_CMD(CSR_GP_CNTRL);
1769 IWL_CMD(CSR_HW_REV);
1770 IWL_CMD(CSR_EEPROM_REG);
1771 IWL_CMD(CSR_EEPROM_GP);
1772 IWL_CMD(CSR_OTP_GP_REG);
1773 IWL_CMD(CSR_GIO_REG);
1774 IWL_CMD(CSR_GP_UCODE_REG);
1775 IWL_CMD(CSR_GP_DRIVER_REG);
1776 IWL_CMD(CSR_UCODE_DRV_GP1);
1777 IWL_CMD(CSR_UCODE_DRV_GP2);
1778 IWL_CMD(CSR_LED_REG);
1779 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1780 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1781 IWL_CMD(CSR_ANA_PLL_CFG);
1782 IWL_CMD(CSR_HW_REV_WA_REG);
Alexander Bondara812cba2014-02-18 16:45:00 +01001783 IWL_CMD(CSR_MONITOR_STATUS_REG);
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001784 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1785 default:
1786 return "UNKNOWN";
1787 }
Johannes Bergd9fb6462012-03-26 08:23:39 -07001788#undef IWL_CMD
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001789}
1790
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001791void iwl_pcie_dump_csr(struct iwl_trans *trans)
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001792{
1793 int i;
1794 static const u32 csr_tbl[] = {
1795 CSR_HW_IF_CONFIG_REG,
1796 CSR_INT_COALESCING,
1797 CSR_INT,
1798 CSR_INT_MASK,
1799 CSR_FH_INT_STATUS,
1800 CSR_GPIO_IN,
1801 CSR_RESET,
1802 CSR_GP_CNTRL,
1803 CSR_HW_REV,
1804 CSR_EEPROM_REG,
1805 CSR_EEPROM_GP,
1806 CSR_OTP_GP_REG,
1807 CSR_GIO_REG,
1808 CSR_GP_UCODE_REG,
1809 CSR_GP_DRIVER_REG,
1810 CSR_UCODE_DRV_GP1,
1811 CSR_UCODE_DRV_GP2,
1812 CSR_LED_REG,
1813 CSR_DRAM_INT_TBL_REG,
1814 CSR_GIO_CHICKEN_BITS,
1815 CSR_ANA_PLL_CFG,
Alexander Bondara812cba2014-02-18 16:45:00 +01001816 CSR_MONITOR_STATUS_REG,
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001817 CSR_HW_REV_WA_REG,
1818 CSR_DBG_HPET_MEM_REG
1819 };
1820 IWL_ERR(trans, "CSR values:\n");
1821 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1822 "CSR_INT_PERIODIC_REG)\n");
1823 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1824 IWL_ERR(trans, " %25s: 0X%08x\n",
1825 get_csr_string(csr_tbl[i]),
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001826 iwl_read32(trans, csr_tbl[i]));
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001827 }
1828}
1829
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001830#ifdef CONFIG_IWLWIFI_DEBUGFS
1831/* create and remove of files */
1832#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -07001833 if (!debugfs_create_file(#name, mode, parent, trans, \
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001834 &iwl_dbgfs_##name##_ops)) \
Meenakshi Venkataraman9da987a2012-07-16 18:43:56 -07001835 goto err; \
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001836} while (0)
1837
1838/* file operation */
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001839#define DEBUGFS_READ_FILE_OPS(name) \
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001840static const struct file_operations iwl_dbgfs_##name##_ops = { \
1841 .read = iwl_dbgfs_##name##_read, \
Stephen Boyd234e3402012-04-05 14:25:11 -07001842 .open = simple_open, \
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001843 .llseek = generic_file_llseek, \
1844};
1845
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001846#define DEBUGFS_WRITE_FILE_OPS(name) \
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001847static const struct file_operations iwl_dbgfs_##name##_ops = { \
1848 .write = iwl_dbgfs_##name##_write, \
Stephen Boyd234e3402012-04-05 14:25:11 -07001849 .open = simple_open, \
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001850 .llseek = generic_file_llseek, \
1851};
1852
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001853#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001854static const struct file_operations iwl_dbgfs_##name##_ops = { \
1855 .write = iwl_dbgfs_##name##_write, \
1856 .read = iwl_dbgfs_##name##_read, \
Stephen Boyd234e3402012-04-05 14:25:11 -07001857 .open = simple_open, \
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001858 .llseek = generic_file_llseek, \
1859};
1860
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001861static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
Johannes Berg20d3b642012-05-16 22:54:29 +02001862 char __user *user_buf,
1863 size_t count, loff_t *ppos)
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001864{
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -07001865 struct iwl_trans *trans = file->private_data;
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001866 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001867 struct iwl_txq *txq;
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001868 struct iwl_queue *q;
1869 char *buf;
1870 int pos = 0;
1871 int cnt;
1872 int ret;
Wey-Yi Guy1745e4402012-03-09 11:13:40 -08001873 size_t bufsz;
1874
Emmanuel Grumbache0b8d402015-01-20 17:02:40 +02001875 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001876
Johannes Bergf9e75442012-03-30 09:37:39 +02001877 if (!trans_pcie->txq)
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001878 return -EAGAIN;
Johannes Bergf9e75442012-03-30 09:37:39 +02001879
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001880 buf = kzalloc(bufsz, GFP_KERNEL);
1881 if (!buf)
1882 return -ENOMEM;
1883
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -07001884 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001885 txq = &trans_pcie->txq[cnt];
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001886 q = &txq->q;
1887 pos += scnprintf(buf + pos, bufsz - pos,
Emmanuel Grumbache0b8d402015-01-20 17:02:40 +02001888 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001889 cnt, q->read_ptr, q->write_ptr,
Johannes Berg9eae88f2012-03-15 13:26:52 -07001890 !!test_bit(cnt, trans_pcie->queue_used),
Andy Lutomirskif40faf62014-06-07 09:13:44 -07001891 !!test_bit(cnt, trans_pcie->queue_stopped),
Emmanuel Grumbache0b8d402015-01-20 17:02:40 +02001892 txq->need_update, txq->frozen,
Andy Lutomirskif40faf62014-06-07 09:13:44 -07001893 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001894 }
1895 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1896 kfree(buf);
1897 return ret;
1898}
1899
1900static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
Johannes Berg20d3b642012-05-16 22:54:29 +02001901 char __user *user_buf,
1902 size_t count, loff_t *ppos)
1903{
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -07001904 struct iwl_trans *trans = file->private_data;
Johannes Berg20d3b642012-05-16 22:54:29 +02001905 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001906 struct iwl_rxq *rxq = &trans_pcie->rxq;
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001907 char buf[256];
1908 int pos = 0;
1909 const size_t bufsz = sizeof(buf);
1910
1911 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1912 rxq->read);
1913 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1914 rxq->write);
Andy Lutomirskif40faf62014-06-07 09:13:44 -07001915 pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1916 rxq->write_actual);
1917 pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1918 rxq->need_update);
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001919 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1920 rxq->free_count);
1921 if (rxq->rb_stts) {
1922 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1923 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1924 } else {
1925 pos += scnprintf(buf + pos, bufsz - pos,
1926 "closed_rb_num: Not Allocated\n");
1927 }
1928 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1929}
1930
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07001931static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1932 char __user *user_buf,
Johannes Berg20d3b642012-05-16 22:54:29 +02001933 size_t count, loff_t *ppos)
1934{
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07001935 struct iwl_trans *trans = file->private_data;
Johannes Berg20d3b642012-05-16 22:54:29 +02001936 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07001937 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1938
1939 int pos = 0;
1940 char *buf;
1941 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1942 ssize_t ret;
1943
1944 buf = kzalloc(bufsz, GFP_KERNEL);
Johannes Bergf9e75442012-03-30 09:37:39 +02001945 if (!buf)
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07001946 return -ENOMEM;
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07001947
1948 pos += scnprintf(buf + pos, bufsz - pos,
1949 "Interrupt Statistics Report:\n");
1950
1951 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1952 isr_stats->hw);
1953 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1954 isr_stats->sw);
1955 if (isr_stats->sw || isr_stats->hw) {
1956 pos += scnprintf(buf + pos, bufsz - pos,
1957 "\tLast Restarting Code: 0x%X\n",
1958 isr_stats->err_code);
1959 }
1960#ifdef CONFIG_IWLWIFI_DEBUG
1961 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1962 isr_stats->sch);
1963 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1964 isr_stats->alive);
1965#endif
1966 pos += scnprintf(buf + pos, bufsz - pos,
1967 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1968
1969 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1970 isr_stats->ctkill);
1971
1972 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1973 isr_stats->wakeup);
1974
1975 pos += scnprintf(buf + pos, bufsz - pos,
1976 "Rx command responses:\t\t %u\n", isr_stats->rx);
1977
1978 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1979 isr_stats->tx);
1980
1981 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1982 isr_stats->unhandled);
1983
1984 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1985 kfree(buf);
1986 return ret;
1987}
1988
1989static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1990 const char __user *user_buf,
1991 size_t count, loff_t *ppos)
1992{
1993 struct iwl_trans *trans = file->private_data;
Johannes Berg20d3b642012-05-16 22:54:29 +02001994 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07001995 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1996
1997 char buf[8];
1998 int buf_size;
1999 u32 reset_flag;
2000
2001 memset(buf, 0, sizeof(buf));
2002 buf_size = min(count, sizeof(buf) - 1);
2003 if (copy_from_user(buf, user_buf, buf_size))
2004 return -EFAULT;
2005 if (sscanf(buf, "%x", &reset_flag) != 1)
2006 return -EFAULT;
2007 if (reset_flag == 0)
2008 memset(isr_stats, 0, sizeof(*isr_stats));
2009
2010 return count;
2011}
2012
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07002013static ssize_t iwl_dbgfs_csr_write(struct file *file,
Johannes Berg20d3b642012-05-16 22:54:29 +02002014 const char __user *user_buf,
2015 size_t count, loff_t *ppos)
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07002016{
2017 struct iwl_trans *trans = file->private_data;
2018 char buf[8];
2019 int buf_size;
2020 int csr;
2021
2022 memset(buf, 0, sizeof(buf));
2023 buf_size = min(count, sizeof(buf) - 1);
2024 if (copy_from_user(buf, user_buf, buf_size))
2025 return -EFAULT;
2026 if (sscanf(buf, "%d", &csr) != 1)
2027 return -EFAULT;
2028
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02002029 iwl_pcie_dump_csr(trans);
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07002030
2031 return count;
2032}
2033
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07002034static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
Johannes Berg20d3b642012-05-16 22:54:29 +02002035 char __user *user_buf,
2036 size_t count, loff_t *ppos)
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07002037{
2038 struct iwl_trans *trans = file->private_data;
Johannes Berg94543a82012-08-21 18:57:10 +02002039 char *buf = NULL;
Johannes Berg56c24772014-01-21 21:19:18 +01002040 ssize_t ret;
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07002041
Johannes Berg56c24772014-01-21 21:19:18 +01002042 ret = iwl_dump_fh(trans, &buf);
2043 if (ret < 0)
2044 return ret;
2045 if (!buf)
2046 return -EINVAL;
2047 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2048 kfree(buf);
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07002049 return ret;
2050}
2051
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07002052DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07002053DEBUGFS_READ_FILE_OPS(fh_reg);
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07002054DEBUGFS_READ_FILE_OPS(rx_queue);
2055DEBUGFS_READ_FILE_OPS(tx_queue);
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07002056DEBUGFS_WRITE_FILE_OPS(csr);
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07002057
2058/*
2059 * Create the debugfs files and directories
2060 *
2061 */
2062static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
Johannes Berg20d3b642012-05-16 22:54:29 +02002063 struct dentry *dir)
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07002064{
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07002065 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2066 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07002067 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07002068 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2069 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07002070 return 0;
Meenakshi Venkataraman9da987a2012-07-16 18:43:56 -07002071
2072err:
2073 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2074 return -ENOMEM;
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07002075}
Johannes Bergaadede62014-10-09 17:01:36 +02002076#else
2077static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2078 struct dentry *dir)
2079{
2080 return 0;
2081}
2082#endif /*CONFIG_IWLWIFI_DEBUGFS */
Johannes Berg4d075002014-04-24 10:41:31 +02002083
2084static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2085{
2086 u32 cmdlen = 0;
2087 int i;
2088
2089 for (i = 0; i < IWL_NUM_OF_TBS; i++)
2090 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2091
2092 return cmdlen;
2093}
2094
Emmanuel Grumbach67c65f22014-06-26 11:27:51 +03002095static const struct {
2096 u32 start, end;
2097} iwl_prph_dump_addr[] = {
2098 { .start = 0x00a00000, .end = 0x00a00000 },
2099 { .start = 0x00a0000c, .end = 0x00a00024 },
2100 { .start = 0x00a0002c, .end = 0x00a0003c },
2101 { .start = 0x00a00410, .end = 0x00a00418 },
2102 { .start = 0x00a00420, .end = 0x00a00420 },
2103 { .start = 0x00a00428, .end = 0x00a00428 },
2104 { .start = 0x00a00430, .end = 0x00a0043c },
2105 { .start = 0x00a00444, .end = 0x00a00444 },
2106 { .start = 0x00a004c0, .end = 0x00a004cc },
2107 { .start = 0x00a004d8, .end = 0x00a004d8 },
2108 { .start = 0x00a004e0, .end = 0x00a004f0 },
2109 { .start = 0x00a00840, .end = 0x00a00840 },
2110 { .start = 0x00a00850, .end = 0x00a00858 },
2111 { .start = 0x00a01004, .end = 0x00a01008 },
2112 { .start = 0x00a01010, .end = 0x00a01010 },
2113 { .start = 0x00a01018, .end = 0x00a01018 },
2114 { .start = 0x00a01024, .end = 0x00a01024 },
2115 { .start = 0x00a0102c, .end = 0x00a01034 },
2116 { .start = 0x00a0103c, .end = 0x00a01040 },
2117 { .start = 0x00a01048, .end = 0x00a01094 },
2118 { .start = 0x00a01c00, .end = 0x00a01c20 },
2119 { .start = 0x00a01c58, .end = 0x00a01c58 },
2120 { .start = 0x00a01c7c, .end = 0x00a01c7c },
2121 { .start = 0x00a01c28, .end = 0x00a01c54 },
2122 { .start = 0x00a01c5c, .end = 0x00a01c5c },
Emmanuel Grumbach6a65bd52015-02-25 16:06:46 +02002123 { .start = 0x00a01c60, .end = 0x00a01cdc },
Emmanuel Grumbach67c65f22014-06-26 11:27:51 +03002124 { .start = 0x00a01ce0, .end = 0x00a01d0c },
2125 { .start = 0x00a01d18, .end = 0x00a01d20 },
2126 { .start = 0x00a01d2c, .end = 0x00a01d30 },
2127 { .start = 0x00a01d40, .end = 0x00a01d5c },
2128 { .start = 0x00a01d80, .end = 0x00a01d80 },
Emmanuel Grumbach6a65bd52015-02-25 16:06:46 +02002129 { .start = 0x00a01d98, .end = 0x00a01d9c },
2130 { .start = 0x00a01da8, .end = 0x00a01da8 },
2131 { .start = 0x00a01db8, .end = 0x00a01df4 },
Emmanuel Grumbach67c65f22014-06-26 11:27:51 +03002132 { .start = 0x00a01dc0, .end = 0x00a01dfc },
2133 { .start = 0x00a01e00, .end = 0x00a01e2c },
2134 { .start = 0x00a01e40, .end = 0x00a01e60 },
Emmanuel Grumbach6a65bd52015-02-25 16:06:46 +02002135 { .start = 0x00a01e68, .end = 0x00a01e6c },
2136 { .start = 0x00a01e74, .end = 0x00a01e74 },
Emmanuel Grumbach67c65f22014-06-26 11:27:51 +03002137 { .start = 0x00a01e84, .end = 0x00a01e90 },
2138 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
Emmanuel Grumbach6a65bd52015-02-25 16:06:46 +02002139 { .start = 0x00a01ed0, .end = 0x00a01ee0 },
2140 { .start = 0x00a01f00, .end = 0x00a01f1c },
2141 { .start = 0x00a01f44, .end = 0x00a01ffc },
Emmanuel Grumbach67c65f22014-06-26 11:27:51 +03002142 { .start = 0x00a02000, .end = 0x00a02048 },
2143 { .start = 0x00a02068, .end = 0x00a020f0 },
2144 { .start = 0x00a02100, .end = 0x00a02118 },
2145 { .start = 0x00a02140, .end = 0x00a0214c },
2146 { .start = 0x00a02168, .end = 0x00a0218c },
2147 { .start = 0x00a021c0, .end = 0x00a021c0 },
2148 { .start = 0x00a02400, .end = 0x00a02410 },
2149 { .start = 0x00a02418, .end = 0x00a02420 },
2150 { .start = 0x00a02428, .end = 0x00a0242c },
2151 { .start = 0x00a02434, .end = 0x00a02434 },
2152 { .start = 0x00a02440, .end = 0x00a02460 },
2153 { .start = 0x00a02468, .end = 0x00a024b0 },
2154 { .start = 0x00a024c8, .end = 0x00a024cc },
2155 { .start = 0x00a02500, .end = 0x00a02504 },
2156 { .start = 0x00a0250c, .end = 0x00a02510 },
2157 { .start = 0x00a02540, .end = 0x00a02554 },
2158 { .start = 0x00a02580, .end = 0x00a025f4 },
2159 { .start = 0x00a02600, .end = 0x00a0260c },
2160 { .start = 0x00a02648, .end = 0x00a02650 },
2161 { .start = 0x00a02680, .end = 0x00a02680 },
2162 { .start = 0x00a026c0, .end = 0x00a026d0 },
2163 { .start = 0x00a02700, .end = 0x00a0270c },
2164 { .start = 0x00a02804, .end = 0x00a02804 },
2165 { .start = 0x00a02818, .end = 0x00a0281c },
2166 { .start = 0x00a02c00, .end = 0x00a02db4 },
2167 { .start = 0x00a02df4, .end = 0x00a02fb0 },
2168 { .start = 0x00a03000, .end = 0x00a03014 },
2169 { .start = 0x00a0301c, .end = 0x00a0302c },
2170 { .start = 0x00a03034, .end = 0x00a03038 },
2171 { .start = 0x00a03040, .end = 0x00a03048 },
2172 { .start = 0x00a03060, .end = 0x00a03068 },
2173 { .start = 0x00a03070, .end = 0x00a03074 },
2174 { .start = 0x00a0307c, .end = 0x00a0307c },
2175 { .start = 0x00a03080, .end = 0x00a03084 },
2176 { .start = 0x00a0308c, .end = 0x00a03090 },
2177 { .start = 0x00a03098, .end = 0x00a03098 },
2178 { .start = 0x00a030a0, .end = 0x00a030a0 },
2179 { .start = 0x00a030a8, .end = 0x00a030b4 },
2180 { .start = 0x00a030bc, .end = 0x00a030bc },
2181 { .start = 0x00a030c0, .end = 0x00a0312c },
2182 { .start = 0x00a03c00, .end = 0x00a03c5c },
2183 { .start = 0x00a04400, .end = 0x00a04454 },
2184 { .start = 0x00a04460, .end = 0x00a04474 },
2185 { .start = 0x00a044c0, .end = 0x00a044ec },
2186 { .start = 0x00a04500, .end = 0x00a04504 },
2187 { .start = 0x00a04510, .end = 0x00a04538 },
2188 { .start = 0x00a04540, .end = 0x00a04548 },
2189 { .start = 0x00a04560, .end = 0x00a0457c },
2190 { .start = 0x00a04590, .end = 0x00a04598 },
2191 { .start = 0x00a045c0, .end = 0x00a045f4 },
2192};
2193
2194static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2195 struct iwl_fw_error_dump_data **data)
2196{
2197 struct iwl_fw_error_dump_prph *prph;
2198 unsigned long flags;
2199 u32 prph_len = 0, i;
2200
2201 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2202 return 0;
2203
2204 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2205 /* The range includes both boundaries */
2206 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2207 iwl_prph_dump_addr[i].start + 4;
2208 int reg;
2209 __le32 *val;
2210
Liad Kaufman87dd6342014-11-10 19:25:22 +02002211 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
Emmanuel Grumbach67c65f22014-06-26 11:27:51 +03002212
2213 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2214 (*data)->len = cpu_to_le32(sizeof(*prph) +
2215 num_bytes_in_chunk);
2216 prph = (void *)(*data)->data;
2217 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2218 val = (void *)prph->data;
2219
2220 for (reg = iwl_prph_dump_addr[i].start;
2221 reg <= iwl_prph_dump_addr[i].end;
2222 reg += 4)
2223 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2224 reg));
2225 *data = iwl_fw_error_next_data(*data);
2226 }
2227
2228 iwl_trans_release_nic_access(trans, &flags);
2229
2230 return prph_len;
2231}
2232
Emmanuel Grumbach473ad712014-07-08 19:44:25 +03002233#define IWL_CSR_TO_DUMP (0x250)
2234
2235static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2236 struct iwl_fw_error_dump_data **data)
2237{
2238 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2239 __le32 *val;
2240 int i;
2241
2242 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2243 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2244 val = (void *)(*data)->data;
2245
2246 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2247 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2248
2249 *data = iwl_fw_error_next_data(*data);
2250
2251 return csr_len;
2252}
2253
Liad Kaufman06d51e02014-11-23 13:56:21 +02002254static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2255 struct iwl_fw_error_dump_data **data)
2256{
2257 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2258 unsigned long flags;
2259 __le32 *val;
2260 int i;
2261
2262 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2263 return 0;
2264
2265 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2266 (*data)->len = cpu_to_le32(fh_regs_len);
2267 val = (void *)(*data)->data;
2268
2269 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2270 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2271
2272 iwl_trans_release_nic_access(trans, &flags);
2273
2274 *data = iwl_fw_error_next_data(*data);
2275
2276 return sizeof(**data) + fh_regs_len;
2277}
2278
Liad Kaufmancc79ef62015-01-05 14:06:14 +02002279static u32
2280iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2281 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2282 u32 monitor_len)
2283{
2284 u32 buf_size_in_dwords = (monitor_len >> 2);
2285 u32 *buffer = (u32 *)fw_mon_data->data;
2286 unsigned long flags;
2287 u32 i;
2288
2289 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2290 return 0;
2291
2292 __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2293 for (i = 0; i < buf_size_in_dwords; i++)
2294 buffer[i] = __iwl_read_prph(trans, MON_DMARB_RD_DATA_ADDR);
2295 __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2296
2297 iwl_trans_release_nic_access(trans, &flags);
2298
2299 return monitor_len;
2300}
2301
Emmanuel Grumbach48eb7b32014-07-08 19:45:17 +03002302static
2303struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
Johannes Berg4d075002014-04-24 10:41:31 +02002304{
2305 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2306 struct iwl_fw_error_dump_data *data;
2307 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2308 struct iwl_fw_error_dump_txcmd *txcmd;
Emmanuel Grumbach48eb7b32014-07-08 19:45:17 +03002309 struct iwl_trans_dump_data *dump_data;
Johannes Berg4d075002014-04-24 10:41:31 +02002310 u32 len;
Liad Kaufman99684ae2014-11-17 11:44:03 +02002311 u32 monitor_len;
Johannes Berg4d075002014-04-24 10:41:31 +02002312 int i, ptr;
2313
Emmanuel Grumbach473ad712014-07-08 19:44:25 +03002314 /* transport dump header */
2315 len = sizeof(*dump_data);
2316
2317 /* host commands */
2318 len += sizeof(*data) +
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +03002319 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2320
Emmanuel Grumbach473ad712014-07-08 19:44:25 +03002321 /* CSR registers */
2322 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2323
2324 /* PRPH registers */
Emmanuel Grumbach67c65f22014-06-26 11:27:51 +03002325 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2326 /* The range includes both boundaries */
2327 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2328 iwl_prph_dump_addr[i].start + 4;
2329
2330 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2331 num_bytes_in_chunk;
2332 }
2333
Liad Kaufman06d51e02014-11-23 13:56:21 +02002334 /* FH registers */
2335 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2336
Emmanuel Grumbach473ad712014-07-08 19:44:25 +03002337 /* FW monitor */
Liad Kaufman99684ae2014-11-17 11:44:03 +02002338 if (trans_pcie->fw_mon_page) {
Emmanuel Grumbachc544e9c2014-06-26 09:54:23 +03002339 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
Liad Kaufman99684ae2014-11-17 11:44:03 +02002340 trans_pcie->fw_mon_size;
2341 monitor_len = trans_pcie->fw_mon_size;
2342 } else if (trans->dbg_dest_tlv) {
2343 u32 base, end;
2344
2345 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2346 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2347
2348 base = iwl_read_prph(trans, base) <<
2349 trans->dbg_dest_tlv->base_shift;
2350 end = iwl_read_prph(trans, end) <<
2351 trans->dbg_dest_tlv->end_shift;
2352
2353 /* Make "end" point to the actual end */
Liad Kaufmancc79ef62015-01-05 14:06:14 +02002354 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2355 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
Liad Kaufman99684ae2014-11-17 11:44:03 +02002356 end += (1 << trans->dbg_dest_tlv->end_shift);
2357 monitor_len = end - base;
2358 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2359 monitor_len;
2360 } else {
2361 monitor_len = 0;
2362 }
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +03002363
Emmanuel Grumbach48eb7b32014-07-08 19:45:17 +03002364 dump_data = vzalloc(len);
2365 if (!dump_data)
2366 return NULL;
Johannes Berg4d075002014-04-24 10:41:31 +02002367
2368 len = 0;
Emmanuel Grumbach48eb7b32014-07-08 19:45:17 +03002369 data = (void *)dump_data->data;
Johannes Berg4d075002014-04-24 10:41:31 +02002370 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2371 txcmd = (void *)data->data;
2372 spin_lock_bh(&cmdq->lock);
2373 ptr = cmdq->q.write_ptr;
2374 for (i = 0; i < cmdq->q.n_window; i++) {
2375 u8 idx = get_cmd_index(&cmdq->q, ptr);
2376 u32 caplen, cmdlen;
2377
2378 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2379 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2380
2381 if (cmdlen) {
2382 len += sizeof(*txcmd) + caplen;
2383 txcmd->cmdlen = cpu_to_le32(cmdlen);
2384 txcmd->caplen = cpu_to_le32(caplen);
2385 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2386 txcmd = (void *)((u8 *)txcmd->data + caplen);
2387 }
2388
2389 ptr = iwl_queue_dec_wrap(ptr);
2390 }
2391 spin_unlock_bh(&cmdq->lock);
2392
2393 data->len = cpu_to_le32(len);
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +03002394 len += sizeof(*data);
Emmanuel Grumbach67c65f22014-06-26 11:27:51 +03002395 data = iwl_fw_error_next_data(data);
2396
2397 len += iwl_trans_pcie_dump_prph(trans, &data);
Emmanuel Grumbach473ad712014-07-08 19:44:25 +03002398 len += iwl_trans_pcie_dump_csr(trans, &data);
Liad Kaufman06d51e02014-11-23 13:56:21 +02002399 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
Emmanuel Grumbach67c65f22014-06-26 11:27:51 +03002400 /* data is already pointing to the next section */
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +03002401
Liad Kaufman99684ae2014-11-17 11:44:03 +02002402 if ((trans_pcie->fw_mon_page &&
2403 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2404 trans->dbg_dest_tlv) {
Emmanuel Grumbachc544e9c2014-06-26 09:54:23 +03002405 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
Liad Kaufman99684ae2014-11-17 11:44:03 +02002406 u32 base, write_ptr, wrap_cnt;
2407
2408 /* If there was a dest TLV - use the values from there */
2409 if (trans->dbg_dest_tlv) {
2410 write_ptr =
2411 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2412 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2413 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2414 } else {
2415 base = MON_BUFF_BASE_ADDR;
2416 write_ptr = MON_BUFF_WRPTR;
2417 wrap_cnt = MON_BUFF_CYCLE_CNT;
2418 }
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +03002419
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +03002420 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +03002421 fw_mon_data = (void *)data->data;
2422 fw_mon_data->fw_mon_wr_ptr =
Liad Kaufman99684ae2014-11-17 11:44:03 +02002423 cpu_to_le32(iwl_read_prph(trans, write_ptr));
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +03002424 fw_mon_data->fw_mon_cycle_cnt =
Liad Kaufman99684ae2014-11-17 11:44:03 +02002425 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +03002426 fw_mon_data->fw_mon_base_ptr =
Liad Kaufman99684ae2014-11-17 11:44:03 +02002427 cpu_to_le32(iwl_read_prph(trans, base));
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +03002428
Liad Kaufman99684ae2014-11-17 11:44:03 +02002429 len += sizeof(*data) + sizeof(*fw_mon_data);
2430 if (trans_pcie->fw_mon_page) {
Liad Kaufman99684ae2014-11-17 11:44:03 +02002431 /*
2432 * The firmware is now asserted, it won't write anything
2433 * to the buffer. CPU can take ownership to fetch the
2434 * data. The buffer will be handed back to the device
2435 * before the firmware will be restarted.
2436 */
2437 dma_sync_single_for_cpu(trans->dev,
2438 trans_pcie->fw_mon_phys,
2439 trans_pcie->fw_mon_size,
2440 DMA_FROM_DEVICE);
2441 memcpy(fw_mon_data->data,
2442 page_address(trans_pcie->fw_mon_page),
2443 trans_pcie->fw_mon_size);
2444
Liad Kaufmancc79ef62015-01-05 14:06:14 +02002445 monitor_len = trans_pcie->fw_mon_size;
2446 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
Liad Kaufman99684ae2014-11-17 11:44:03 +02002447 /*
2448 * Update pointers to reflect actual values after
2449 * shifting
2450 */
2451 base = iwl_read_prph(trans, base) <<
2452 trans->dbg_dest_tlv->base_shift;
2453 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2454 monitor_len / sizeof(u32));
Liad Kaufmancc79ef62015-01-05 14:06:14 +02002455 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2456 monitor_len =
2457 iwl_trans_pci_dump_marbh_monitor(trans,
2458 fw_mon_data,
2459 monitor_len);
2460 } else {
2461 /* Didn't match anything - output no monitor data */
2462 monitor_len = 0;
Liad Kaufman99684ae2014-11-17 11:44:03 +02002463 }
Liad Kaufmancc79ef62015-01-05 14:06:14 +02002464
2465 len += monitor_len;
2466 data->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
Emmanuel Grumbachc2d20202014-06-01 08:05:52 +03002467 }
2468
Emmanuel Grumbach48eb7b32014-07-08 19:45:17 +03002469 dump_data->len = len;
2470
2471 return dump_data;
Johannes Berg4d075002014-04-24 10:41:31 +02002472}
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07002473
Johannes Bergd1ff5252012-04-12 06:24:30 -07002474static const struct iwl_trans_ops trans_ops_pcie = {
Emmanuel Grumbach57a1dc82012-01-08 13:22:16 +02002475 .start_hw = iwl_trans_pcie_start_hw,
Arik Nemtsova4082842013-11-24 19:10:46 +02002476 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
Emmanuel Grumbached6a3802012-01-02 16:10:08 +02002477 .fw_alive = iwl_trans_pcie_fw_alive,
Emmanuel Grumbachcf614292012-01-08 16:33:58 +02002478 .start_fw = iwl_trans_pcie_start_fw,
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07002479 .stop_device = iwl_trans_pcie_stop_device,
2480
Johannes Bergddaf5a52013-01-08 11:25:44 +01002481 .d3_suspend = iwl_trans_pcie_d3_suspend,
2482 .d3_resume = iwl_trans_pcie_d3_resume,
Johannes Berg2dd4f9f2012-03-05 11:24:35 -08002483
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02002484 .send_cmd = iwl_trans_pcie_send_hcmd,
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07002485
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07002486 .tx = iwl_trans_pcie_tx,
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07002487 .reclaim = iwl_trans_pcie_reclaim,
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07002488
Emmanuel Grumbachd0624be2012-05-29 13:07:30 +03002489 .txq_disable = iwl_trans_pcie_txq_disable,
Emmanuel Grumbach4beaf6c2012-05-29 11:29:10 +03002490 .txq_enable = iwl_trans_pcie_txq_enable,
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07002491
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07002492 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07002493
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02002494 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
Emmanuel Grumbache0b8d402015-01-20 17:02:40 +02002495 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07002496
Emmanuel Grumbach03905492012-01-03 13:48:07 +02002497 .write8 = iwl_trans_pcie_write8,
2498 .write32 = iwl_trans_pcie_write32,
2499 .read32 = iwl_trans_pcie_read32,
Emmanuel Grumbach6a06b6c2012-12-02 13:07:30 +02002500 .read_prph = iwl_trans_pcie_read_prph,
2501 .write_prph = iwl_trans_pcie_write_prph,
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +02002502 .read_mem = iwl_trans_pcie_read_mem,
2503 .write_mem = iwl_trans_pcie_write_mem,
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -08002504 .configure = iwl_trans_pcie_configure,
Don Fry47107e82012-03-15 13:27:06 -07002505 .set_pmi = iwl_trans_pcie_set_pmi,
Emmanuel Grumbach7a65d172012-12-24 15:01:24 +02002506 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
Lilach Edelsteine139dc42013-01-13 13:31:10 +02002507 .release_nic_access = iwl_trans_pcie_release_nic_access,
2508 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
Johannes Berg4d075002014-04-24 10:41:31 +02002509
Eliad Peller7616f332014-11-20 17:33:43 +02002510 .ref = iwl_trans_pcie_ref,
2511 .unref = iwl_trans_pcie_unref,
2512
Johannes Berg4d075002014-04-24 10:41:31 +02002513 .dump_data = iwl_trans_pcie_dump_data,
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07002514};
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002515
Emmanuel Grumbach87ce05a2012-03-26 09:03:18 -07002516struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -07002517 const struct pci_device_id *ent,
2518 const struct iwl_cfg *cfg)
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002519{
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002520 struct iwl_trans_pcie *trans_pcie;
2521 struct iwl_trans *trans;
2522 u16 pci_cmd;
2523 int err;
2524
Johannes Berg7b501d12015-05-22 11:28:58 +02002525 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2526 &pdev->dev, cfg, &trans_ops_pcie, 0);
2527 if (!trans)
2528 return ERR_PTR(-ENOMEM);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002529
2530 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2531
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002532 trans_pcie->trans = trans;
Johannes Berg7b114882012-02-05 13:55:11 -08002533 spin_lock_init(&trans_pcie->irq_lock);
Lilach Edelsteine56b04e2013-01-16 11:34:49 +02002534 spin_lock_init(&trans_pcie->reg_lock);
Johannes Bergdad33ec2015-01-19 21:09:09 +01002535 spin_lock_init(&trans_pcie->ref_lock);
Emmanuel Grumbachfa9f3282015-06-11 20:45:49 +03002536 mutex_init(&trans_pcie->mutex);
Johannes Berg13df1aa2012-03-06 13:31:00 -08002537 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002538
Johannes Bergd819c6c2013-09-30 11:02:46 +02002539 err = pci_enable_device(pdev);
2540 if (err)
2541 goto out_no_pci;
2542
Emmanuel Grumbachf2532b02013-07-02 15:47:29 +03002543 if (!cfg->base_params->pcie_l1_allowed) {
2544 /*
2545 * W/A - seems to solve weird behavior. We need to remove this
2546 * if we don't want to stay in L1 all the time. This wastes a
2547 * lot of power.
2548 */
2549 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2550 PCIE_LINK_STATE_L1 |
2551 PCIE_LINK_STATE_CLKPM);
2552 }
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002553
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002554 pci_set_master(pdev);
2555
2556 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2557 if (!err)
2558 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2559 if (err) {
2560 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2561 if (!err)
2562 err = pci_set_consistent_dma_mask(pdev,
Johannes Berg20d3b642012-05-16 22:54:29 +02002563 DMA_BIT_MASK(32));
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002564 /* both attempts failed: */
2565 if (err) {
Joe Perches6a4b09f2012-10-28 01:05:47 -07002566 dev_err(&pdev->dev, "No suitable DMA available\n");
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002567 goto out_pci_disable_device;
2568 }
2569 }
2570
2571 err = pci_request_regions(pdev, DRV_NAME);
2572 if (err) {
Joe Perches6a4b09f2012-10-28 01:05:47 -07002573 dev_err(&pdev->dev, "pci_request_regions failed\n");
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002574 goto out_pci_disable_device;
2575 }
2576
Stanislaw Gruszka05f5b972012-03-07 09:52:26 -08002577 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002578 if (!trans_pcie->hw_base) {
Joe Perches6a4b09f2012-10-28 01:05:47 -07002579 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002580 err = -ENODEV;
2581 goto out_pci_release_regions;
2582 }
2583
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002584 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2585 * PCI Tx retries from interfering with C3 CPU state */
2586 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2587
Emmanuel Grumbach83f7a852014-04-13 16:03:11 +03002588 trans->dev = &pdev->dev;
2589 trans_pcie->pci_dev = pdev;
2590 iwl_disable_interrupts(trans);
2591
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002592 err = pci_enable_msi(pdev);
Emmanuel Grumbach9f904b32012-11-13 13:35:43 +02002593 if (err) {
Joe Perches6a4b09f2012-10-28 01:05:47 -07002594 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
Emmanuel Grumbach9f904b32012-11-13 13:35:43 +02002595 /* enable rfkill interrupt: hw bug w/a */
2596 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2597 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2598 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2599 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2600 }
2601 }
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002602
Emmanuel Grumbach08079a42012-01-09 16:23:00 +02002603 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
Liad Kaufmanb513ee72014-06-01 17:21:33 +03002604 /*
2605 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2606 * changed, and now the revision step also includes bit 0-1 (no more
2607 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2608 * in the old format.
2609 */
Eran Harary7a42baa2015-02-25 14:24:51 +02002610 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2611 unsigned long flags;
2612 int ret;
2613
Liad Kaufmanb513ee72014-06-01 17:21:33 +03002614 trans->hw_rev = (trans->hw_rev & 0xfff0) |
Liad Kaufman1fc0e222014-09-17 13:28:50 +03002615 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
Liad Kaufmanb513ee72014-06-01 17:21:33 +03002616
Eran Harary7a42baa2015-02-25 14:24:51 +02002617 /*
2618 * in-order to recognize C step driver should read chip version
2619 * id located at the AUX bus MISC address space.
2620 */
2621 iwl_set_bit(trans, CSR_GP_CNTRL,
2622 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2623 udelay(2);
2624
2625 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2626 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2627 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2628 25000);
2629 if (ret < 0) {
2630 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2631 goto out_pci_disable_msi;
2632 }
2633
2634 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
2635 u32 hw_step;
2636
2637 hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG);
2638 hw_step |= ENABLE_WFPM;
2639 __iwl_write_prph(trans, WFPM_CTRL_REG, hw_step);
2640 hw_step = __iwl_read_prph(trans, AUX_MISC_REG);
2641 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2642 if (hw_step == 0x3)
2643 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2644 (SILICON_C_STEP << 2);
2645 iwl_trans_release_nic_access(trans, &flags);
2646 }
2647 }
2648
Emmanuel Grumbach99673ee2012-01-08 21:19:45 +02002649 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
Emmanuel Grumbach9ca85962012-01-08 21:19:45 +02002650 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2651 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002652
Meenakshi Venkataraman69a10b22012-03-10 13:00:09 -08002653 /* Initialize the wait queue for commands */
Emmanuel Grumbachf946b522012-10-25 17:25:52 +02002654 init_waitqueue_head(&trans_pcie->wait_command_queue);
Meenakshi Venkataraman69a10b22012-03-10 13:00:09 -08002655
Johannes Berga8b691e2012-12-27 23:08:06 +01002656 if (iwl_pcie_alloc_ict(trans))
Johannes Berg7b501d12015-05-22 11:28:58 +02002657 goto out_pci_disable_msi;
Johannes Berga8b691e2012-12-27 23:08:06 +01002658
Emmanuel Grumbach85bf9da2013-12-09 11:48:30 +02002659 err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
Luciano Coelho6965a352013-08-10 16:35:45 +03002660 iwl_pcie_irq_handler,
2661 IRQF_SHARED, DRV_NAME, trans);
2662 if (err) {
Johannes Berga8b691e2012-12-27 23:08:06 +01002663 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2664 goto out_free_ict;
2665 }
2666
Emmanuel Grumbach83f7a852014-04-13 16:03:11 +03002667 trans_pcie->inta_mask = CSR_INI_SET_MASK;
Eliad Peller67359432014-12-09 15:23:54 +02002668 trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
Emmanuel Grumbach83f7a852014-04-13 16:03:11 +03002669
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002670 return trans;
2671
Johannes Berga8b691e2012-12-27 23:08:06 +01002672out_free_ict:
2673 iwl_pcie_free_ict(trans);
Emmanuel Grumbach59c647b2012-05-24 19:24:34 +03002674out_pci_disable_msi:
2675 pci_disable_msi(pdev);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002676out_pci_release_regions:
2677 pci_release_regions(pdev);
2678out_pci_disable_device:
2679 pci_disable_device(pdev);
2680out_no_pci:
Johannes Berg7b501d12015-05-22 11:28:58 +02002681 iwl_trans_free(trans);
Luciano Coelho6965a352013-08-10 16:35:45 +03002682 return ERR_PTR(err);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002683}