blob: 08e2c6a6e11885eb4f69a0de97beed62f5630194 [file] [log] [blame]
Wu Fengguang9e9c9f22009-11-06 11:06:22 +08001/*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Zhenyu Wang <zhenyu.z.wang@intel.com>
25 * Wu Fengguang <fengguang.wu@intel.com>
26 *
27 */
28
Wu Fengguang020abdb2010-04-19 13:13:06 +080029#define _GNU_SOURCE
Wu Fengguang9e9c9f22009-11-06 11:06:22 +080030#include <unistd.h>
Wu Fengguang020abdb2010-04-19 13:13:06 +080031#include <stdlib.h>
32#include <stdio.h>
33#include <string.h>
34#include <err.h>
Wu Fengguang9e9c9f22009-11-06 11:06:22 +080035#include <arpa/inet.h>
36#include "intel_gpu_tools.h"
37
Wu Fengguang020abdb2010-04-19 13:13:06 +080038static uint32_t devid;
39
40
41#define BITSTO(n) (n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - 1)
42#define BITMASK(high, low) (BITSTO(high+1) & ~BITSTO(low))
43#define BITS(reg, high, low) (((reg) & (BITMASK(high, low))) >> (low))
44#define BIT(reg, n) BITS(reg, n, n)
45
46#define min_t(type, x, y) ({ \
47 type __min1 = (x); \
48 type __min2 = (y); \
49 __min1 < __min2 ? __min1: __min2; })
50
51#define OPNAME(names, index) \
52 names[min_t(unsigned int, index, ARRAY_SIZE(names) - 1)]
53
54#define dump_reg(reg, desc) \
55 do { \
56 dword = INREG(reg); \
57 printf("%-21s 0x%08x %s\n", # reg, dword, desc); \
58 } while (0)
59
60
61static char *pixel_clock[] = {
62 [0] = "25.2 / 1.001 MHz",
63 [1] = "25.2 MHz",
64 [2] = "27 MHz",
65 [3] = "27 * 1.001 MHz",
66 [4] = "54 MHz",
67 [5] = "54 * 1.001 MHz",
68 [6] = "74.25 / 1.001 MHz",
69 [7] = "74.25 MHz",
70 [8] = "148.5 / 1.001 MHz",
71 [9] = "148.5 MHz",
72 [10] = "Reserved",
73};
74
75static char *power_state[] = {
76 [0] = "D0",
77 [1] = "D1",
78 [2] = "D2",
79 [3] = "D3",
80};
81
82static char *stream_type[] = {
83 [0] = "default samples",
84 [1] = "one bit stream",
85 [2] = "DST stream",
86 [3] = "MLP stream",
87 [4] = "Reserved",
88};
89
90static char *dip_port[] = {
91 [0] = "Reserved",
92 [1] = "Digital Port B",
93 [2] = "Digital Port C",
94 [3] = "Digital Port D",
95};
96
97static char *dip_index[] = {
98 [0] = "Audio DIP",
99 [1] = "ACP DIP",
100 [2] = "ISRC1 DIP",
101 [3] = "ISRC2 DIP",
102 [4] = "Reserved",
103};
104
105static char *dip_trans[] = {
106 [0] = "disabled",
107 [1] = "reserved",
108 [2] = "send once",
109 [3] = "best effort",
110};
111
112static char *video_dip_index[] = {
113 [0] = "AVI DIP",
114 [1] = "Vendor-specific DIP",
Wu Fengguangf3f84bb2011-11-12 11:12:55 +0800115 [2] = "Gamut Metadata DIP",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800116 [3] = "Source Product Description DIP",
117};
118
119static char *video_dip_trans[] = {
120 [0] = "send once",
121 [1] = "send every vsync",
122 [2] = "send at least every other vsync",
123 [3] = "reserved",
124};
125
126static char *trans_to_port_sel[] = {
127 [0] = "no port",
128 [1] = "Digital Port B",
129 [2] = "Digital Port B",
130 [3] = "Digital Port B",
131 [4] = "Digital Port B",
Alan Coopersmithc4610062012-01-06 14:37:19 -0800132 [5] = "reserved",
133 [6] = "reserved",
134 [7] = "reserved",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800135};
136
137static char *transcoder_select[] = {
138 [0] = "Transcoder A",
139 [1] = "Transcoder B",
140 [2] = "Transcoder C",
141 [3] = "reserved",
142};
143
144static char *dp_port_width[] = {
145 [0] = "x1 mode",
146 [1] = "x2 mode",
Wu Fengguangcf4c12f2011-11-12 11:12:46 +0800147 [2] = "reserved",
148 [3] = "x4 mode",
Alan Coopersmithc4610062012-01-06 14:37:19 -0800149 [4] = "reserved",
150 [5] = "reserved",
151 [6] = "reserved",
152 [7] = "reserved",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800153};
154
Wu Fengguang12861a92011-11-12 11:12:47 +0800155static char *bits_per_sample[] = {
156 [0] = "reserved",
157 [1] = "16 bits",
158 [2] = "24 bits",
159 [3] = "32 bits",
160 [4] = "20 bits",
161 [5] = "reserved",
162};
163
Wu Fengguangee949582011-11-12 11:12:53 +0800164static char *sdvo_hdmi_encoding[] = {
165 [0] = "SDVO",
166 [1] = "reserved",
167 [2] = "TMDS",
168 [3] = "reserved",
169};
Wu Fengguang12861a92011-11-12 11:12:47 +0800170
Wu Fengguang020abdb2010-04-19 13:13:06 +0800171static void do_self_tests(void)
172{
173 if (BIT(1, 0) != 1)
174 exit(1);
175 if (BIT(0x80000000, 31) != 1)
176 exit(2);
177 if (BITS(0xc0000000, 31, 30) != 3)
178 exit(3);
179}
180
181/*
182 * EagleLake registers
183 */
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800184#define AUD_CONFIG 0x62000
185#define AUD_DEBUG 0x62010
186#define AUD_VID_DID 0x62020
187#define AUD_RID 0x62024
188#define AUD_SUBN_CNT 0x62028
189#define AUD_FUNC_GRP 0x62040
190#define AUD_SUBN_CNT2 0x62044
191#define AUD_GRP_CAP 0x62048
192#define AUD_PWRST 0x6204c
193#define AUD_SUPPWR 0x62050
194#define AUD_SID 0x62054
195#define AUD_OUT_CWCAP 0x62070
196#define AUD_OUT_PCMSIZE 0x62074
197#define AUD_OUT_STR 0x62078
198#define AUD_OUT_DIG_CNVT 0x6207c
199#define AUD_OUT_CH_STR 0x62080
200#define AUD_OUT_STR_DESC 0x62084
201#define AUD_PINW_CAP 0x620a0
202#define AUD_PIN_CAP 0x620a4
203#define AUD_PINW_CONNLNG 0x620a8
204#define AUD_PINW_CONNLST 0x620ac
205#define AUD_PINW_CNTR 0x620b0
206#define AUD_PINW_UNSOLRESP 0x620b8
207#define AUD_CNTL_ST 0x620b4
208#define AUD_PINW_CONFIG 0x620bc
209#define AUD_HDMIW_STATUS 0x620d4
210#define AUD_HDMIW_HDMIEDID 0x6210c
211#define AUD_HDMIW_INFOFR 0x62118
212#define AUD_CONV_CHCNT 0x62120
213#define AUD_CTS_ENABLE 0x62128
214
215#define VIDEO_DIP_CTL 0x61170
216#define VIDEO_DIP_ENABLE (1<<31)
217#define VIDEO_DIP_ENABLE_AVI (1<<21)
218#define VIDEO_DIP_ENABLE_VENDOR (1<<22)
219#define VIDEO_DIP_ENABLE_SPD (1<<24)
220#define VIDEO_DIP_BUF_AVI (0<<19)
221#define VIDEO_DIP_BUF_VENDOR (1<<19)
222#define VIDEO_DIP_BUF_SPD (3<<19)
223#define VIDEO_DIP_TRANS_ONCE (0<<16)
224#define VIDEO_DIP_TRANS_1 (1<<16)
225#define VIDEO_DIP_TRANS_2 (2<<16)
226
227#define AUDIO_HOTPLUG_EN (1<<24)
228
229
Wu Fengguang020abdb2010-04-19 13:13:06 +0800230static void dump_eaglelake(void)
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800231{
232 uint32_t dword;
233 int i;
234
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800235 /* printf("%-18s %8s %s\n\n", "register name", "raw value", "description"); */
236
237 dump_reg(VIDEO_DIP_CTL, "Video DIP Control");
238 dump_reg(SDVOB, "Digital Display Port B Control Register");
239 dump_reg(SDVOC, "Digital Display Port C Control Register");
240 dump_reg(PORT_HOTPLUG_EN, "Hot Plug Detect Enable");
241
242 dump_reg(AUD_CONFIG, "Audio Configuration");
243 dump_reg(AUD_DEBUG, "Audio Debug");
244 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
245 dump_reg(AUD_RID, "Audio Revision ID");
246 dump_reg(AUD_SUBN_CNT, "Audio Subordinate Node Count");
247 dump_reg(AUD_FUNC_GRP, "Audio Function Group Type");
248 dump_reg(AUD_SUBN_CNT2, "Audio Subordinate Node Count");
249 dump_reg(AUD_GRP_CAP, "Audio Function Group Capabilities");
250 dump_reg(AUD_PWRST, "Audio Power State");
251 dump_reg(AUD_SUPPWR, "Audio Supported Power States");
252 dump_reg(AUD_SID, "Audio Root Node Subsystem ID");
253 dump_reg(AUD_OUT_CWCAP, "Audio Output Converter Widget Capabilities");
254 dump_reg(AUD_OUT_PCMSIZE, "Audio PCM Size and Rates");
255 dump_reg(AUD_OUT_STR, "Audio Stream Formats");
256 dump_reg(AUD_OUT_DIG_CNVT, "Audio Digital Converter");
257 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
258 dump_reg(AUD_OUT_STR_DESC, "Audio Stream Descriptor Format");
259 dump_reg(AUD_PINW_CAP, "Audio Pin Complex Widget Capabilities");
260 dump_reg(AUD_PIN_CAP, "Audio Pin Capabilities");
261 dump_reg(AUD_PINW_CONNLNG, "Audio Connection List Length");
262 dump_reg(AUD_PINW_CONNLST, "Audio Connection List Entry");
263 dump_reg(AUD_PINW_CNTR, "Audio Pin Widget Control");
264 dump_reg(AUD_PINW_UNSOLRESP,"Audio Unsolicited Response Enable");
265 dump_reg(AUD_CNTL_ST, "Audio Control State Register");
266 dump_reg(AUD_PINW_CONFIG, "Audio Configuration Default");
267 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
268 dump_reg(AUD_HDMIW_HDMIEDID,"Audio HDMI Data EDID Block");
269 dump_reg(AUD_HDMIW_INFOFR, "Audio HDMI Widget Data Island Packet");
270 dump_reg(AUD_CONV_CHCNT, "Audio Converter Channel Count");
271 dump_reg(AUD_CTS_ENABLE, "Audio CTS Programming Enable");
272
273 printf("\nDetails:\n\n");
274
275 dword = INREG(AUD_VID_DID);
276 printf("AUD_VID_DID vendor id\t\t\t0x%x\n", dword >> 16);
277 printf("AUD_VID_DID device id\t\t\t0x%x\n", dword & 0xffff);
278
279 dword = INREG(AUD_RID);
280 printf("AUD_RID major revision\t\t\t0x%lx\n", BITS(dword, 23, 20));
281 printf("AUD_RID minor revision\t\t\t0x%lx\n", BITS(dword, 19, 16));
282 printf("AUD_RID revision id\t\t\t0x%lx\n", BITS(dword, 15, 8));
283 printf("AUD_RID stepping id\t\t\t0x%lx\n", BITS(dword, 7, 0));
284
285 dword = INREG(SDVOB);
286 printf("SDVOB enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
287 printf("SDVOB HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
288 printf("SDVOB SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
289 printf("SDVOB null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
290 printf("SDVOB audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
291
292 dword = INREG(SDVOC);
293 printf("SDVOC enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
294 printf("SDVOC HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
295 printf("SDVOC SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
296 printf("SDVOC null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
297 printf("SDVOC audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
298
299 dword = INREG(PORT_HOTPLUG_EN);
300 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port B\t%ld\n", BIT(dword, 29)),
301 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port C\t%ld\n", BIT(dword, 28)),
302 printf("PORT_HOTPLUG_EN DisplayPort port D\t%ld\n", BIT(dword, 27)),
303 printf("PORT_HOTPLUG_EN SDVOB\t\t\t%ld\n", BIT(dword, 26)),
304 printf("PORT_HOTPLUG_EN SDVOC\t\t\t%ld\n", BIT(dword, 25)),
305 printf("PORT_HOTPLUG_EN audio\t\t\t%ld\n", BIT(dword, 24)),
306 printf("PORT_HOTPLUG_EN TV\t\t\t%ld\n", BIT(dword, 23)),
307 printf("PORT_HOTPLUG_EN CRT\t\t\t%ld\n", BIT(dword, 9)),
308
309 dword = INREG(VIDEO_DIP_CTL);
310 printf("VIDEO_DIP_CTL enable graphics DIP\t%ld\n", BIT(dword, 31)),
311 printf("VIDEO_DIP_CTL port select\t\t[0x%lx] %s\n",
312 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
313 printf("VIDEO_DIP_CTL DIP buffer trans active\t%lu\n", BIT(dword, 28));
314 printf("VIDEO_DIP_CTL AVI DIP enabled\t\t%lu\n", BIT(dword, 21));
315 printf("VIDEO_DIP_CTL vendor DIP enabled\t%lu\n", BIT(dword, 22));
316 printf("VIDEO_DIP_CTL SPD DIP enabled\t\t%lu\n", BIT(dword, 24));
317 printf("VIDEO_DIP_CTL DIP buffer index\t\t[0x%lx] %s\n",
318 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
319 printf("VIDEO_DIP_CTL DIP trans freq\t\t[0x%lx] %s\n",
320 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
321 printf("VIDEO_DIP_CTL DIP buffer size\t\t%lu\n", BITS(dword, 11, 8));
322 printf("VIDEO_DIP_CTL DIP address\t\t%lu\n", BITS(dword, 3, 0));
323
324 dword = INREG(AUD_CONFIG);
325 printf("AUD_CONFIG pixel clock\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
326 OPNAME(pixel_clock, BITS(dword, 19, 16)));
327 printf("AUD_CONFIG fabrication enabled\t\t%lu\n", BITS(dword, 2, 2));
328 printf("AUD_CONFIG professional use allowed\t%lu\n", BIT(dword, 1));
329 printf("AUD_CONFIG fuse enabled\t\t\t%lu\n", BIT(dword, 0));
330
331 dword = INREG(AUD_DEBUG);
332 printf("AUD_DEBUG function reset\t\t%lu\n", BIT(dword, 0));
333
334 dword = INREG(AUD_SUBN_CNT);
335 printf("AUD_SUBN_CNT starting node number\t0x%lx\n", BITS(dword, 23, 16));
336 printf("AUD_SUBN_CNT total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
337
338 dword = INREG(AUD_SUBN_CNT2);
339 printf("AUD_SUBN_CNT2 starting node number\t0x%lx\n", BITS(dword, 24, 16));
340 printf("AUD_SUBN_CNT2 total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
341
342 dword = INREG(AUD_FUNC_GRP);
343 printf("AUD_FUNC_GRP unsol capable\t\t%lu\n", BIT(dword, 8));
344 printf("AUD_FUNC_GRP node type\t\t\t0x%lx\n", BITS(dword, 7, 0));
345
346 dword = INREG(AUD_GRP_CAP);
347 printf("AUD_GRP_CAP beep 0\t\t\t%lu\n", BIT(dword, 16));
348 printf("AUD_GRP_CAP input delay\t\t\t%lu\n", BITS(dword, 11, 8));
349 printf("AUD_GRP_CAP output delay\t\t%lu\n", BITS(dword, 3, 0));
350
351 dword = INREG(AUD_PWRST);
352 printf("AUD_PWRST device power state\t\t%s\n",
353 power_state[BITS(dword, 5, 4)]);
354 printf("AUD_PWRST device power state setting\t%s\n",
355 power_state[BITS(dword, 1, 0)]);
356
357 dword = INREG(AUD_SUPPWR);
358 printf("AUD_SUPPWR support D0\t\t\t%lu\n", BIT(dword, 0));
359 printf("AUD_SUPPWR support D1\t\t\t%lu\n", BIT(dword, 1));
360 printf("AUD_SUPPWR support D2\t\t\t%lu\n", BIT(dword, 2));
361 printf("AUD_SUPPWR support D3\t\t\t%lu\n", BIT(dword, 3));
362
363 dword = INREG(AUD_OUT_CWCAP);
364 printf("AUD_OUT_CWCAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
365 printf("AUD_OUT_CWCAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
366 printf("AUD_OUT_CWCAP channel count\t\t%lu\n",
367 BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
368 printf("AUD_OUT_CWCAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
369 printf("AUD_OUT_CWCAP power control\t\t%lu\n", BIT(dword, 10));
370 printf("AUD_OUT_CWCAP digital\t\t\t%lu\n", BIT(dword, 9));
371 printf("AUD_OUT_CWCAP conn list\t\t\t%lu\n", BIT(dword, 8));
372 printf("AUD_OUT_CWCAP unsol\t\t\t%lu\n", BIT(dword, 7));
373 printf("AUD_OUT_CWCAP mute\t\t\t%lu\n", BIT(dword, 5));
374 printf("AUD_OUT_CWCAP format override\t\t%lu\n", BIT(dword, 4));
375 printf("AUD_OUT_CWCAP amp param override\t%lu\n", BIT(dword, 3));
376 printf("AUD_OUT_CWCAP out amp present\t\t%lu\n", BIT(dword, 2));
377 printf("AUD_OUT_CWCAP in amp present\t\t%lu\n", BIT(dword, 1));
378
379 dword = INREG(AUD_OUT_DIG_CNVT);
380 printf("AUD_OUT_DIG_CNVT SPDIF category\t\t0x%lx\n", BITS(dword, 14, 8));
381 printf("AUD_OUT_DIG_CNVT SPDIF level\t\t%lu\n", BIT(dword, 7));
382 printf("AUD_OUT_DIG_CNVT professional\t\t%lu\n", BIT(dword, 6));
383 printf("AUD_OUT_DIG_CNVT non PCM\t\t%lu\n", BIT(dword, 5));
384 printf("AUD_OUT_DIG_CNVT copyright asserted\t%lu\n", BIT(dword, 4));
385 printf("AUD_OUT_DIG_CNVT filter preemphasis\t%lu\n", BIT(dword, 3));
386 printf("AUD_OUT_DIG_CNVT validity config\t%lu\n", BIT(dword, 2));
387 printf("AUD_OUT_DIG_CNVT validity flag\t\t%lu\n", BIT(dword, 1));
388 printf("AUD_OUT_DIG_CNVT digital enable\t\t%lu\n", BIT(dword, 0));
389
390 dword = INREG(AUD_OUT_CH_STR);
391 printf("AUD_OUT_CH_STR stream id\t\t0x%lx\n", BITS(dword, 7, 4));
Wu Fengguang5032f682011-11-12 11:12:41 +0800392 printf("AUD_OUT_CH_STR lowest channel\t\t%lu\n", BITS(dword, 3, 0));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800393
394 dword = INREG(AUD_OUT_STR_DESC);
Wu Fengguang5032f682011-11-12 11:12:41 +0800395 printf("AUD_OUT_STR_DESC stream channels\t%lu\n", BITS(dword, 3, 0) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +0800396 printf("AUD_OUT_STR_DESC Bits per Sample\t[%#lx] %s\n",
397 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800398
399 dword = INREG(AUD_PINW_CAP);
400 printf("AUD_PINW_CAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
401 printf("AUD_PINW_CAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
Wu Fengguang5032f682011-11-12 11:12:41 +0800402 printf("AUD_PINW_CAP channel count\t\t%lu\n",
403 BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800404 printf("AUD_PINW_CAP HDCP\t\t\t%lu\n", BIT(dword, 12));
405 printf("AUD_PINW_CAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
406 printf("AUD_PINW_CAP power control\t\t%lu\n", BIT(dword, 10));
407 printf("AUD_PINW_CAP digital\t\t\t%lu\n", BIT(dword, 9));
408 printf("AUD_PINW_CAP conn list\t\t\t%lu\n", BIT(dword, 8));
409 printf("AUD_PINW_CAP unsol\t\t\t%lu\n", BIT(dword, 7));
410 printf("AUD_PINW_CAP mute\t\t\t%lu\n", BIT(dword, 5));
411 printf("AUD_PINW_CAP format override\t\t%lu\n", BIT(dword, 4));
412 printf("AUD_PINW_CAP amp param override\t\t%lu\n", BIT(dword, 3));
413 printf("AUD_PINW_CAP out amp present\t\t%lu\n", BIT(dword, 2));
414 printf("AUD_PINW_CAP in amp present\t\t%lu\n", BIT(dword, 1));
415
416
417 dword = INREG(AUD_PIN_CAP);
418 printf("AUD_PIN_CAP EAPD\t\t\t%lu\n", BIT(dword, 16));
419 printf("AUD_PIN_CAP HDMI\t\t\t%lu\n", BIT(dword, 7));
420 printf("AUD_PIN_CAP output\t\t\t%lu\n", BIT(dword, 4));
421 printf("AUD_PIN_CAP presence detect\t\t%lu\n", BIT(dword, 2));
422
423 dword = INREG(AUD_PINW_CNTR);
424 printf("AUD_PINW_CNTR mute status\t\t%lu\n", BIT(dword, 8));
425 printf("AUD_PINW_CNTR out enable\t\t%lu\n", BIT(dword, 6));
426 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
427 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
428 printf("AUD_PINW_CNTR stream type\t\t[0x%lx] %s\n",
429 BITS(dword, 2, 0),
430 OPNAME(stream_type, BITS(dword, 2, 0)));
431
432 dword = INREG(AUD_PINW_UNSOLRESP);
433 printf("AUD_PINW_UNSOLRESP enable unsol resp\t%lu\n", BIT(dword, 31));
434
435 dword = INREG(AUD_CNTL_ST);
436 printf("AUD_CNTL_ST DIP audio enabled\t\t%lu\n", BIT(dword, 21));
437 printf("AUD_CNTL_ST DIP ACP enabled\t\t%lu\n", BIT(dword, 22));
438 printf("AUD_CNTL_ST DIP ISRCx enabled\t\t%lu\n", BIT(dword, 23));
439 printf("AUD_CNTL_ST DIP port select\t\t[0x%lx] %s\n",
440 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
441 printf("AUD_CNTL_ST DIP buffer index\t\t[0x%lx] %s\n",
442 BITS(dword, 20, 18), OPNAME(dip_index, BITS(dword, 20, 18)));
443 printf("AUD_CNTL_ST DIP trans freq\t\t[0x%lx] %s\n",
444 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
445 printf("AUD_CNTL_ST DIP address\t\t\t%lu\n", BITS(dword, 3, 0));
446 printf("AUD_CNTL_ST CP ready\t\t\t%lu\n", BIT(dword, 15));
447 printf("AUD_CNTL_ST ELD valid\t\t\t%lu\n", BIT(dword, 14));
448 printf("AUD_CNTL_ST ELD ack\t\t\t%lu\n", BIT(dword, 4));
449 printf("AUD_CNTL_ST ELD bufsize\t\t\t%lu\n", BITS(dword, 13, 9));
450 printf("AUD_CNTL_ST ELD address\t\t\t%lu\n", BITS(dword, 8, 5));
451
452 dword = INREG(AUD_HDMIW_STATUS);
453 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK underrun\t%lu\n", BIT(dword, 31));
454 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK overrun\t%lu\n", BIT(dword, 30));
455 printf("AUD_HDMIW_STATUS BCLK/CDCLK underrun\t%lu\n", BIT(dword, 29));
456 printf("AUD_HDMIW_STATUS BCLK/CDCLK overrun\t%lu\n", BIT(dword, 28));
457
458 dword = INREG(AUD_CONV_CHCNT);
459 printf("AUD_CONV_CHCNT HDMI HBR enabled\t\t%lu\n", BITS(dword, 15, 14));
460 printf("AUD_CONV_CHCNT HDMI channel count\t%lu\n", BITS(dword, 11, 8) + 1);
461
462 printf("AUD_CONV_CHCNT HDMI channel mapping:\n");
463 for (i = 0; i < 8; i++) {
464 OUTREG(AUD_CONV_CHCNT, i);
465 dword = INREG(AUD_CONV_CHCNT);
466 printf("\t\t\t\t\t[0x%x] %u => %lu \n", dword, i, BITS(dword, 7, 4));
467 }
468
Wu Fengguangf32aecb2011-11-12 11:12:50 +0800469 printf("AUD_HDMIW_HDMIEDID HDMI ELD:\n\t");
470 dword = INREG(AUD_CNTL_ST);
471 dword &= ~BITMASK(8, 5);
472 OUTREG(AUD_CNTL_ST, dword);
473 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
474 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID)));
475 printf("\n");
476
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800477 printf("AUD_HDMIW_INFOFR HDMI audio Infoframe:\n\t");
478 dword = INREG(AUD_CNTL_ST);
479 dword &= ~BITMASK(20, 18);
480 dword &= ~BITMASK(3, 0);
481 OUTREG(AUD_CNTL_ST, dword);
482 for (i = 0; i < 8; i++)
483 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR)));
484 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800485}
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800486
Wu Fengguang020abdb2010-04-19 13:13:06 +0800487#undef AUD_RID
488#undef AUD_VID_DID
489#undef AUD_PWRST
490#undef AUD_OUT_CH_STR
491#undef AUD_HDMIW_STATUS
492
493/*
494 * IronLake registers
495 */
496#define AUD_CONFIG_A 0xE2000
497#define AUD_CONFIG_B 0xE2100
498#define AUD_CTS_ENABLE_A 0xE2028
499#define AUD_CTS_ENABLE_B 0xE2128
500#define AUD_MISC_CTRL_A 0xE2010
501#define AUD_MISC_CTRL_B 0xE2110
502#define AUD_VID_DID 0xE2020
503#define AUD_RID 0xE2024
504#define AUD_PWRST 0xE204C
505#define AUD_PORT_EN_HD_CFG 0xE207C
506#define AUD_OUT_DIG_CNVT_A 0xE2080
507#define AUD_OUT_DIG_CNVT_B 0xE2180
508#define AUD_OUT_CH_STR 0xE2088
509#define AUD_OUT_STR_DESC_A 0xE2084
510#define AUD_OUT_STR_DESC_B 0xE2184
511#define AUD_PINW_CONNLNG_LIST 0xE20A8
512#define AUD_PINW_CONNLNG_SEL 0xE20AC
513#define AUD_CNTL_ST_A 0xE20B4
514#define AUD_CNTL_ST_B 0xE21B4
515#define AUD_CNTL_ST2 0xE20C0
516#define AUD_HDMIW_STATUS 0xE20D4
517#define AUD_HDMIW_HDMIEDID_A 0xE2050
518#define AUD_HDMIW_HDMIEDID_B 0xE2150
519#define AUD_HDMIW_INFOFR_A 0xE2054
520#define AUD_HDMIW_INFOFR_B 0xE2154
521
522static void dump_ironlake(void)
523{
524 uint32_t dword;
525 int i;
526
527 dump_reg(HDMIB, "sDVO/HDMI Port B Control");
528 dump_reg(HDMIC, "HDMI Port C Control");
529 dump_reg(HDMID, "HDMI Port D Control");
Wu Fengguangb5ca6b42011-11-12 11:12:48 +0800530 dump_reg(PCH_DP_B, "DisplayPort B Control Register");
531 dump_reg(PCH_DP_C, "DisplayPort C Control Register");
532 dump_reg(PCH_DP_D, "DisplayPort D Control Register");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800533 dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
534 dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
535 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
536 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800537 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
538 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
539 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
540 dump_reg(AUD_RID, "Audio Revision ID");
541 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
542 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800543 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
544 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800545 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800546 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
547 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800548 dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
549 dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800550 dump_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A");
551 dump_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800552 dump_reg(AUD_CNTL_ST2, "Audio Control State 2");
553 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800554 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
555 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
556 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
557 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800558
559 printf("\nDetails:\n\n");
560
561 dword = INREG(AUD_VID_DID);
562 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
563 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
564
565 dword = INREG(AUD_RID);
566 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
567 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
568 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
569 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
570
571 dword = INREG(HDMIB);
572 printf("HDMIB HDMIB_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
573 printf("HDMIB Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
574 printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang821e07d2011-11-12 11:12:54 +0800575 printf("HDMIB SDVOB Hot Plug Interrupt Detect Enable\t\t%lu\n", BIT(dword, 23));
Wu Fengguang305443c2011-11-12 11:12:43 +0800576 printf("HDMIB Digital_Port_B_Detected\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguangee949582011-11-12 11:12:53 +0800577 printf("HDMIB Encoding\t\t\t\t\t\t[0x%lx] %s\n",
578 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
Wu Fengguang020abdb2010-04-19 13:13:06 +0800579 printf("HDMIB Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
580 printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
581
582 dword = INREG(HDMIC);
583 printf("HDMIC HDMIC_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
584 printf("HDMIC Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
585 printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang305443c2011-11-12 11:12:43 +0800586 printf("HDMIC Digital_Port_C_Detected\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguangee949582011-11-12 11:12:53 +0800587 printf("HDMIC Encoding\t\t\t\t\t\t[0x%lx] %s\n",
588 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
Wu Fengguang020abdb2010-04-19 13:13:06 +0800589 printf("HDMIC Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
590 printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
591
592 dword = INREG(HDMID);
593 printf("HDMID HDMID_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
594 printf("HDMID Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
595 printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
596 printf("HDMID Digital_Port_D_Detected\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguangee949582011-11-12 11:12:53 +0800597 printf("HDMID Encoding\t\t\t\t\t\t[0x%lx] %s\n",
598 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
Wu Fengguang020abdb2010-04-19 13:13:06 +0800599 printf("HDMID Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
600 printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
601
Wu Fengguangb5ca6b42011-11-12 11:12:48 +0800602 dword = INREG(PCH_DP_B);
603 printf("PCH_DP_B DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
604 printf("PCH_DP_B Transcoder_Select\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
605 printf("PCH_DP_B Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
606 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
607 printf("PCH_DP_B Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
608 printf("PCH_DP_B HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
609 printf("PCH_DP_B Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
610
611 dword = INREG(PCH_DP_C);
612 printf("PCH_DP_C DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
613 printf("PCH_DP_C Transcoder_Select\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
614 printf("PCH_DP_C Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
615 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
616 printf("PCH_DP_C Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
617 printf("PCH_DP_C HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
618 printf("PCH_DP_C Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
619
620 dword = INREG(PCH_DP_D);
621 printf("PCH_DP_D DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
622 printf("PCH_DP_D Transcoder_Select\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
623 printf("PCH_DP_D Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
624 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
625 printf("PCH_DP_D Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
626 printf("PCH_DP_D HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
627 printf("PCH_DP_D Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
628
Wu Fengguang020abdb2010-04-19 13:13:06 +0800629 dword = INREG(AUD_CONFIG_A);
630 printf("AUD_CONFIG_A Pixel_Clock\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
631 OPNAME(pixel_clock, BITS(dword, 19, 16)));
632 dword = INREG(AUD_CONFIG_B);
633 printf("AUD_CONFIG_B Pixel_Clock\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
634 OPNAME(pixel_clock, BITS(dword, 19, 16)));
635
636 dword = INREG(AUD_CTS_ENABLE_A);
637 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
638 printf("AUD_CTS_ENABLE_A CTS/M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
639 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
640 dword = INREG(AUD_CTS_ENABLE_B);
641 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
642 printf("AUD_CTS_ENABLE_B CTS/M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
643 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
644
645 dword = INREG(AUD_MISC_CTRL_A);
646 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
647 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
648 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
649 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
650 dword = INREG(AUD_MISC_CTRL_B);
651 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
652 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
653 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
654 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
655
656 dword = INREG(AUD_PWRST);
657 printf("AUD_PWRST Function_Group_Device_Power_State_Current\t%s\n", power_state[BITS(dword, 23, 22)]);
658 printf("AUD_PWRST Function_Group_Device_Power_State_Set \t%s\n", power_state[BITS(dword, 21, 20)]);
659 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
660 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
661 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
662 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
663 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
664 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
665 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
666 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
667 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
668 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
669
670 dword = INREG(AUD_PORT_EN_HD_CFG);
671 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
672 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
673 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
674 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
675 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 12));
676 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 13));
677 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 14));
678 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 16));
679 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 17));
680 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 18));
681
682 dword = INREG(AUD_OUT_DIG_CNVT_A);
683 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
684 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
685 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
686 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +0800687 printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800688 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
689 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
690 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
691 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
Wu Fengguangd6bdaf02011-11-12 11:12:42 +0800692 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800693
694 dword = INREG(AUD_OUT_DIG_CNVT_B);
695 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
696 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
697 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
698 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +0800699 printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800700 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
701 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
702 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
703 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
Wu Fengguangd6bdaf02011-11-12 11:12:42 +0800704 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800705
706 printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n");
707 for (i = 0; i < 8; i++) {
708 OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16));
709 dword = INREG(AUD_OUT_CH_STR);
710 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
711 1 + BITS(dword, 3, 0),
712 1 + BITS(dword, 7, 4),
713 1 + BITS(dword, 15, 12),
714 1 + BITS(dword, 23, 20));
715 }
716
717 dword = INREG(AUD_OUT_STR_DESC_A);
718 printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +0800719 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +0800720 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n",
721 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800722 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
723
724 dword = INREG(AUD_OUT_STR_DESC_B);
725 printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +0800726 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +0800727 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n",
728 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800729 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
730
731 dword = INREG(AUD_PINW_CONNLNG_SEL);
732 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%lu\n", BITS(dword, 7, 0));
733 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%lu\n", BITS(dword, 15, 8));
734 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%lu\n", BITS(dword, 23, 16));
735
736 dword = INREG(AUD_CNTL_ST_A);
737 printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n",
738 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
739 printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
Wu Fengguangd6e38ff2011-11-12 11:12:39 +0800740 printf("AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800741 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
742 printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n",
743 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
744 printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
745 printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
Wu Fengguangc0635c32011-11-12 11:12:51 +0800746 printf("AUD_CNTL_ST_A ELD_access_address\t\t\t%lu\n", BITS(dword, 9, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800747
748 dword = INREG(AUD_CNTL_ST_B);
749 printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n",
750 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
751 printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
Wu Fengguangd6e38ff2011-11-12 11:12:39 +0800752 printf("AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800753 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
754 printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n",
755 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
756 printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
757 printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
Wu Fengguangc0635c32011-11-12 11:12:51 +0800758 printf("AUD_CNTL_ST_B ELD_access_address\t\t\t%lu\n", BITS(dword, 9, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800759
760 dword = INREG(AUD_CNTL_ST2);
761 printf("AUD_CNTL_ST2 CP_ReadyB\t\t\t\t\t%lu\n", BIT(dword, 1));
762 printf("AUD_CNTL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
763 printf("AUD_CNTL_ST2 CP_ReadyC\t\t\t\t\t%lu\n", BIT(dword, 5));
764 printf("AUD_CNTL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
765 printf("AUD_CNTL_ST2 CP_ReadyD\t\t\t\t\t%lu\n", BIT(dword, 9));
766 printf("AUD_CNTL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
767
768 dword = INREG(AUD_HDMIW_STATUS);
769 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
770 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
771 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
772 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
773 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
774 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 29));
775
776 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
777 dword = INREG(AUD_CNTL_ST_A);
778 dword &= ~BITMASK(9, 5);
779 OUTREG(AUD_CNTL_ST_A, dword);
780 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
781 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
782 printf("\n");
783
784 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
785 dword = INREG(AUD_CNTL_ST_B);
786 dword &= ~BITMASK(9, 5);
787 OUTREG(AUD_CNTL_ST_B, dword);
788 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
789 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
790 printf("\n");
791
792 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
793 dword = INREG(AUD_CNTL_ST_A);
794 dword &= ~BITMASK(20, 18);
795 dword &= ~BITMASK(3, 0);
796 OUTREG(AUD_CNTL_ST_A, dword);
797 for (i = 0; i < 8; i++)
798 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
799 printf("\n");
800
801 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
802 dword = INREG(AUD_CNTL_ST_B);
803 dword &= ~BITMASK(20, 18);
804 dword &= ~BITMASK(3, 0);
805 OUTREG(AUD_CNTL_ST_B, dword);
806 for (i = 0; i < 8; i++)
807 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
808 printf("\n");
809
810}
811
812
813#undef AUD_CONFIG_A
814#undef AUD_MISC_CTRL_A
815#undef AUD_VID_DID
816#undef AUD_RID
817#undef AUD_CTS_ENABLE_A
818#undef AUD_PWRST
819#undef AUD_HDMIW_HDMIEDID_A
820#undef AUD_HDMIW_INFOFR_A
821#undef AUD_PORT_EN_HD_CFG
822#undef AUD_OUT_DIG_CNVT_A
823#undef AUD_OUT_STR_DESC_A
824#undef AUD_OUT_CH_STR
825#undef AUD_PINW_CONNLNG_LIST
826#undef AUD_CNTL_ST_A
827#undef AUD_HDMIW_STATUS
828#undef AUD_CONFIG_B
829#undef AUD_MISC_CTRL_B
830#undef AUD_CTS_ENABLE_B
831#undef AUD_HDMIW_HDMIEDID_B
832#undef AUD_HDMIW_INFOFR_B
833#undef AUD_OUT_DIG_CNVT_B
834#undef AUD_OUT_STR_DESC_B
835#undef AUD_CNTL_ST_B
836
837/*
838 * CougarPoint registers
839 */
Wu Fengguang97d20312011-11-12 11:12:45 +0800840#define DP_CTL_B 0xE4100
Wu Fengguang020abdb2010-04-19 13:13:06 +0800841#define DP_CTL_C 0xE4200
842#define DP_AUX_CTL_C 0xE4210
843#define DP_AUX_TST_C 0xE4228
844#define SPORT_DDI_CRC_C 0xE4250
845#define SPORT_DDI_CRC_R 0xE4264
846#define DP_CTL_D 0xE4300
847#define DP_AUX_CTL_D 0xE4310
848#define DP_AUX_TST_D 0xE4328
849#define SPORT_DDI_CRC_CTL_D 0xE4350
850#define AUD_CONFIG_A 0xE5000
851#define AUD_MISC_CTRL_A 0xE5010
852#define AUD_VID_DID 0xE5020
853#define AUD_RID 0xE5024
854#define AUD_CTS_ENABLE_A 0xE5028
855#define AUD_PWRST 0xE504C
856#define AUD_HDMIW_HDMIEDID_A 0xE5050
857#define AUD_HDMIW_INFOFR_A 0xE5054
858#define AUD_PORT_EN_HD_CFG 0xE507C
859#define AUD_OUT_DIG_CNVT_A 0xE5080
860#define AUD_OUT_STR_DESC_A 0xE5084
861#define AUD_OUT_CH_STR 0xE5088
862#define AUD_PINW_CONNLNG_LIST 0xE50A8
863#define AUD_PINW_CONNLNG_SELA 0xE50AC
864#define AUD_CNTL_ST_A 0xE50B4
865#define AUD_CNTRL_ST2 0xE50C0
866#define AUD_CNTRL_ST3 0xE50C4
867#define AUD_HDMIW_STATUS 0xE50D4
868#define AUD_CONFIG_B 0xE5100
869#define AUD_MISC_CTRL_B 0xE5110
870#define AUD_CTS_ENABLE_B 0xE5128
871#define AUD_HDMIW_HDMIEDID_B 0xE5150
872#define AUD_HDMIW_INFOFR_B 0xE5154
873#define AUD_OUT_DIG_CNVT_B 0xE5180
874#define AUD_OUT_STR_DESC_B 0xE5184
875#define AUD_CNTL_ST_B 0xE51B4
876#define AUD_CONFIG_C 0xE5200
877#define AUD_MISC_CTRL_C 0xE5210
878#define AUD_CTS_ENABLE_C 0xE5228
879#define AUD_HDMIW_HDMIEDID_C 0xE5250
880#define AUD_HDMIW_INFOFR_C 0xE5254
881#define AUD_OUT_DIG_CNVT_C 0xE5280
882#define AUD_OUT_STR_DESC_C 0xE5284
883#define AUD_CNTL_ST_C 0xE52B4
884#define AUD_CONFIG_D 0xE5300
885#define AUD_MISC_CTRL_D 0xE5310
886#define AUD_CTS_ENABLE_D 0xE5328
887#define AUD_HDMIW_HDMIEDID_D 0xE5350
888#define AUD_HDMIW_INFOFR_D 0xE5354
889#define AUD_OUT_DIG_CNVT_D 0xE5380
890#define AUD_OUT_STR_DESC_D 0xE5384
891#define AUD_CNTL_ST_D 0xE53B4
892
Wu Fengguange321f132011-11-12 11:12:52 +0800893#define VIDEO_DIP_CTL_A 0xE0200
894#define VIDEO_DIP_CTL_B 0xE1200
895#define VIDEO_DIP_CTL_C 0xE2200
896#define VIDEO_DIP_CTL_D 0xE3200
897
Wu Fengguang020abdb2010-04-19 13:13:06 +0800898
899static void dump_cpt(void)
900{
901 uint32_t dword;
902 int i;
903
904 dump_reg(HDMIB, "sDVO/HDMI Port B Control");
905 dump_reg(HDMIC, "HDMI Port C Control");
906 dump_reg(HDMID, "HDMI Port D Control");
Wu Fengguang97d20312011-11-12 11:12:45 +0800907 dump_reg(DP_CTL_B, "DisplayPort B Control");
908 dump_reg(DP_CTL_C, "DisplayPort C Control");
909 dump_reg(DP_CTL_D, "DisplayPort D Control");
910 dump_reg(TRANS_DP_CTL_A, "Transcoder A DisplayPort Control");
911 dump_reg(TRANS_DP_CTL_B, "Transcoder B DisplayPort Control");
912 dump_reg(TRANS_DP_CTL_C, "Transcoder C DisplayPort Control");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800913 dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
914 dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
915 dump_reg(AUD_CONFIG_C, "Audio Configuration - Transcoder C");
916 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
917 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
918 dump_reg(AUD_CTS_ENABLE_C, "Audio CTS Programming Enable - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800919 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
920 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
921 dump_reg(AUD_MISC_CTRL_C, "Audio MISC Control for Transcoder C");
922 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
923 dump_reg(AUD_RID, "Audio Revision ID");
924 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
925 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800926 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
927 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
928 dump_reg(AUD_OUT_DIG_CNVT_C, "Audio Digital Converter - Conv C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800929 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800930 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
931 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
932 dump_reg(AUD_OUT_STR_DESC_C, "Audio Stream Descriptor Format - Conv C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800933 dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
934 dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800935 dump_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A");
936 dump_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B");
937 dump_reg(AUD_CNTL_ST_C, "Audio Control State Register - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800938 dump_reg(AUD_CNTRL_ST2, "Audio Control State 2");
939 dump_reg(AUD_CNTRL_ST3, "Audio Control State 3");
940 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800941 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
942 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
943 dump_reg(AUD_HDMIW_HDMIEDID_C, "HDMI Data EDID Block - Transcoder C");
944 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
945 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
946 dump_reg(AUD_HDMIW_INFOFR_C, "Audio Widget Data Island Packet - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800947
948 printf("\nDetails:\n\n");
949
Wu Fengguange321f132011-11-12 11:12:52 +0800950 dword = INREG(VIDEO_DIP_CTL_A);
951 printf("VIDEO_DIP_CTL_A Enable_Graphics_DIP\t\t\t%ld\n", BIT(dword, 31)),
952 printf("VIDEO_DIP_CTL_A GCP_DIP_enable\t\t\t\t%ld\n", BIT(dword, 25)),
953 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable AVI\t\t%lu\n", BIT(dword, 21));
954 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Vendor\t\t%lu\n", BIT(dword, 22));
955 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Gamut\t\t%lu\n", BIT(dword, 23));
956 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Source \t\t%lu\n", BIT(dword, 24));
957 printf("VIDEO_DIP_CTL_A Video_DIP_buffer_index\t\t\t[0x%lx] %s\n",
958 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
959 printf("VIDEO_DIP_CTL_A Video_DIP_frequency\t\t\t[0x%lx] %s\n",
960 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
961 printf("VIDEO_DIP_CTL_A Video_DIP_buffer_size\t\t\t%lu\n", BITS(dword, 11, 8));
962 printf("VIDEO_DIP_CTL_A Video_DIP_access_address\t\t%lu\n", BITS(dword, 3, 0));
963
964 dword = INREG(VIDEO_DIP_CTL_B);
965 printf("VIDEO_DIP_CTL_B Enable_Graphics_DIP\t\t\t%ld\n", BIT(dword, 31)),
966 printf("VIDEO_DIP_CTL_B GCP_DIP_enable\t\t\t\t%ld\n", BIT(dword, 25)),
967 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable AVI\t\t%lu\n", BIT(dword, 21));
968 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Vendor\t\t%lu\n", BIT(dword, 22));
969 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Gamut\t\t%lu\n", BIT(dword, 23));
970 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Source \t\t%lu\n", BIT(dword, 24));
971 printf("VIDEO_DIP_CTL_B Video_DIP_buffer_index\t\t\t[0x%lx] %s\n",
972 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
973 printf("VIDEO_DIP_CTL_B Video_DIP_frequency\t\t\t[0x%lx] %s\n",
974 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
975 printf("VIDEO_DIP_CTL_B Video_DIP_buffer_size\t\t\t%lu\n", BITS(dword, 11, 8));
976 printf("VIDEO_DIP_CTL_B Video_DIP_access_address\t\t%lu\n", BITS(dword, 3, 0));
977
978 dword = INREG(VIDEO_DIP_CTL_C);
979 printf("VIDEO_DIP_CTL_C Enable_Graphics_DIP\t\t\t%ld\n", BIT(dword, 31)),
980 printf("VIDEO_DIP_CTL_C GCP_DIP_enable\t\t\t\t%ld\n", BIT(dword, 25)),
981 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable AVI\t\t%lu\n", BIT(dword, 21));
982 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Vendor\t\t%lu\n", BIT(dword, 22));
983 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Gamut\t\t%lu\n", BIT(dword, 23));
984 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Source \t\t%lu\n", BIT(dword, 24));
985 printf("VIDEO_DIP_CTL_C Video_DIP_buffer_index\t\t\t[0x%lx] %s\n",
986 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
987 printf("VIDEO_DIP_CTL_C Video_DIP_frequency\t\t\t[0x%lx] %s\n",
988 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
989 printf("VIDEO_DIP_CTL_C Video_DIP_buffer_size\t\t\t%lu\n", BITS(dword, 11, 8));
990 printf("VIDEO_DIP_CTL_C Video_DIP_access_address\t\t%lu\n", BITS(dword, 3, 0));
991
Wu Fengguang020abdb2010-04-19 13:13:06 +0800992 dword = INREG(AUD_VID_DID);
993 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
994 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
995
996 dword = INREG(AUD_RID);
997 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
998 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
999 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
1000 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
1001
1002 dword = INREG(HDMIB);
1003 printf("HDMIB Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
1004 printf("HDMIB Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
1005 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
1006 printf("HDMIB sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
1007 printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang821e07d2011-11-12 11:12:54 +08001008 printf("HDMIB SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n", BIT(dword, 23));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001009 printf("HDMIB Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguangee949582011-11-12 11:12:53 +08001010 printf("HDMIB Encoding\t\t\t\t\t\t[0x%lx] %s\n",
1011 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
Wu Fengguang020abdb2010-04-19 13:13:06 +08001012 printf("HDMIB HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
1013 printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
1014
1015 dword = INREG(HDMIC);
1016 printf("HDMIC Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
1017 printf("HDMIC Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
1018 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
1019 printf("HDMIC sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
1020 printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang821e07d2011-11-12 11:12:54 +08001021 printf("HDMIC SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n", BIT(dword, 23));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001022 printf("HDMIC Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguangee949582011-11-12 11:12:53 +08001023 printf("HDMIC Encoding\t\t\t\t\t\t[0x%lx] %s\n",
1024 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
Wu Fengguang020abdb2010-04-19 13:13:06 +08001025 printf("HDMIC HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
1026 printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
1027
1028 dword = INREG(HDMID);
1029 printf("HDMID Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
1030 printf("HDMID Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
1031 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
1032 printf("HDMID sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
1033 printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang821e07d2011-11-12 11:12:54 +08001034 printf("HDMID SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n", BIT(dword, 23));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001035 printf("HDMID Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguangee949582011-11-12 11:12:53 +08001036 printf("HDMID Encoding\t\t\t\t\t\t[0x%lx] %s\n",
1037 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
Wu Fengguang020abdb2010-04-19 13:13:06 +08001038 printf("HDMID HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
1039 printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
1040
Wu Fengguang97d20312011-11-12 11:12:45 +08001041 dword = INREG(DP_CTL_B);
1042 printf("DP_CTL_B DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
1043 printf("DP_CTL_B Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +08001044 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +08001045 printf("DP_CTL_B Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
1046 printf("DP_CTL_B HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
1047 printf("DP_CTL_B Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001048
Wu Fengguang97d20312011-11-12 11:12:45 +08001049 dword = INREG(DP_CTL_C);
1050 printf("DP_CTL_C DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
1051 printf("DP_CTL_C Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +08001052 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +08001053 printf("DP_CTL_C Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
1054 printf("DP_CTL_C HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
1055 printf("DP_CTL_C Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001056
Wu Fengguang97d20312011-11-12 11:12:45 +08001057 dword = INREG(DP_CTL_D);
1058 printf("DP_CTL_D DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
1059 printf("DP_CTL_D Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +08001060 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +08001061 printf("DP_CTL_D Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
1062 printf("DP_CTL_D HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
1063 printf("DP_CTL_D Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001064
1065 dword = INREG(AUD_CONFIG_A);
1066 printf("AUD_CONFIG_A Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
1067 OPNAME(pixel_clock, BITS(dword, 19, 16)));
1068 dword = INREG(AUD_CONFIG_B);
1069 printf("AUD_CONFIG_B Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
1070 OPNAME(pixel_clock, BITS(dword, 19, 16)));
1071 dword = INREG(AUD_CONFIG_C);
1072 printf("AUD_CONFIG_C Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
1073 OPNAME(pixel_clock, BITS(dword, 19, 16)));
1074
1075 dword = INREG(AUD_CTS_ENABLE_A);
1076 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
1077 printf("AUD_CTS_ENABLE_A CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
1078 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
1079 dword = INREG(AUD_CTS_ENABLE_B);
1080 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
1081 printf("AUD_CTS_ENABLE_B CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
1082 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
1083 dword = INREG(AUD_CTS_ENABLE_C);
1084 printf("AUD_CTS_ENABLE_C Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
1085 printf("AUD_CTS_ENABLE_C CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
1086 printf("AUD_CTS_ENABLE_C CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
1087
1088 dword = INREG(AUD_MISC_CTRL_A);
1089 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1090 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1091 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1092 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
1093 dword = INREG(AUD_MISC_CTRL_B);
1094 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1095 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1096 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1097 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
1098 dword = INREG(AUD_MISC_CTRL_C);
1099 printf("AUD_MISC_CTRL_C Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1100 printf("AUD_MISC_CTRL_C Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1101 printf("AUD_MISC_CTRL_C Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1102 printf("AUD_MISC_CTRL_C Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
1103
1104 dword = INREG(AUD_PWRST);
1105 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Curr \t%s\n", power_state[BITS(dword, 27, 26)]);
1106 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Set \t%s\n", power_state[BITS(dword, 25, 24)]);
1107 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
1108 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
1109 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
1110 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
1111 printf("AUD_PWRST ConvC_Widget_PwrSt_Curr \t%s\n", power_state[BITS(dword, 23, 22)]);
1112 printf("AUD_PWRST ConvC_Widget_PwrSt_Req \t%s\n", power_state[BITS(dword, 21, 20)]);
1113 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
1114 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
1115 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
1116 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
1117 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
1118 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
1119
1120 dword = INREG(AUD_PORT_EN_HD_CFG);
1121 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
1122 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
1123 printf("AUD_PORT_EN_HD_CFG Convertor_C_Digen\t\t\t%lu\n", BIT(dword, 2));
1124 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
1125 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
1126 printf("AUD_PORT_EN_HD_CFG ConvertorC_Stream_ID\t\t%lu\n", BITS(dword, 15, 12));
1127 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 16));
1128 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 17));
1129 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 18));
1130 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 20));
1131 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 21));
1132 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 22));
1133
1134 dword = INREG(AUD_OUT_DIG_CNVT_A);
1135 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
1136 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1137 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1138 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001139 printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001140 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1141 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
1142 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1143 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1144 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1145
1146 dword = INREG(AUD_OUT_DIG_CNVT_B);
1147 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
1148 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1149 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1150 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001151 printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001152 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1153 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
1154 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1155 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1156 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1157
1158 dword = INREG(AUD_OUT_DIG_CNVT_C);
1159 printf("AUD_OUT_DIG_CNVT_C V\t\t\t\t\t%lu\n", BIT(dword, 1));
1160 printf("AUD_OUT_DIG_CNVT_C VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1161 printf("AUD_OUT_DIG_CNVT_C PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1162 printf("AUD_OUT_DIG_CNVT_C Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001163 printf("AUD_OUT_DIG_CNVT_C NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001164 printf("AUD_OUT_DIG_CNVT_C PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1165 printf("AUD_OUT_DIG_CNVT_C Level\t\t\t\t%lu\n", BIT(dword, 7));
1166 printf("AUD_OUT_DIG_CNVT_C Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1167 printf("AUD_OUT_DIG_CNVT_C Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1168 printf("AUD_OUT_DIG_CNVT_C Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1169
1170 printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n");
1171 for (i = 0; i < 8; i++) {
1172 OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16));
1173 dword = INREG(AUD_OUT_CH_STR);
1174 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
1175 1 + BITS(dword, 3, 0),
1176 1 + BITS(dword, 7, 4),
1177 1 + BITS(dword, 15, 12),
1178 1 + BITS(dword, 23, 20));
1179 }
1180
1181 dword = INREG(AUD_OUT_STR_DESC_A);
1182 printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001183 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +08001184 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n",
1185 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001186 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1187
1188 dword = INREG(AUD_OUT_STR_DESC_B);
1189 printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001190 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +08001191 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n",
1192 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001193 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1194
1195 dword = INREG(AUD_OUT_STR_DESC_C);
1196 printf("AUD_OUT_STR_DESC_C HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001197 printf("AUD_OUT_STR_DESC_C Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +08001198 printf("AUD_OUT_STR_DESC_C Bits_per_Sample\t\t\t[%#lx] %s\n",
1199 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001200 printf("AUD_OUT_STR_DESC_C Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1201
1202 dword = INREG(AUD_PINW_CONNLNG_SEL);
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001203 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%#lx\n", BITS(dword, 7, 0));
1204 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%#lx\n", BITS(dword, 15, 8));
1205 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%#lx\n", BITS(dword, 23, 16));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001206
1207 dword = INREG(AUD_CNTL_ST_A);
1208 printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1209 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001210 printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1211 printf("AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001212 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1213 printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n",
1214 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1215 printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1216 printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1217
1218 dword = INREG(AUD_CNTL_ST_B);
1219 printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1220 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001221 printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1222 printf("AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001223 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1224 printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n",
1225 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1226 printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1227 printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1228
1229 dword = INREG(AUD_CNTL_ST_C);
1230 printf("AUD_CNTL_ST_C DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1231 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001232 printf("AUD_CNTL_ST_C DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1233 printf("AUD_CNTL_ST_C DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001234 printf("AUD_CNTL_ST_C DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1235 printf("AUD_CNTL_ST_C DIP_transmission_frequency\t\t[0x%lx] %s\n",
1236 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1237 printf("AUD_CNTL_ST_C ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1238 printf("AUD_CNTL_ST_C ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1239
1240 dword = INREG(AUD_CNTRL_ST2);
1241 printf("AUD_CNTRL_ST2 CP_ReadyB\t\t\t\t%lu\n", BIT(dword, 1));
1242 printf("AUD_CNTRL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
1243 printf("AUD_CNTRL_ST2 CP_ReadyC\t\t\t\t%lu\n", BIT(dword, 5));
1244 printf("AUD_CNTRL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
1245 printf("AUD_CNTRL_ST2 CP_ReadyD\t\t\t\t%lu\n", BIT(dword, 9));
1246 printf("AUD_CNTRL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
1247
1248 dword = INREG(AUD_CNTRL_ST3);
1249 printf("AUD_CNTRL_ST3 TransA_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 3));
1250 printf("AUD_CNTRL_ST3 TransA_to_Port_Sel\t\t\t[%#lx] %s\n",
1251 BITS(dword, 2, 0), trans_to_port_sel[BITS(dword, 2, 0)]);
1252 printf("AUD_CNTRL_ST3 TransB_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 7));
1253 printf("AUD_CNTRL_ST3 TransB_to_Port_Sel\t\t\t[%#lx] %s\n",
1254 BITS(dword, 6, 4), trans_to_port_sel[BITS(dword, 6, 4)]);
1255 printf("AUD_CNTRL_ST3 TransC_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 11));
1256 printf("AUD_CNTRL_ST3 TransC_to_Port_Sel\t\t\t[%#lx] %s\n",
1257 BITS(dword, 10, 8), trans_to_port_sel[BITS(dword, 10, 8)]);
1258
1259 dword = INREG(AUD_HDMIW_STATUS);
1260 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 27));
1261 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 26));
1262 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
1263 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
1264 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
1265 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
1266 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
1267 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 24));
1268
1269 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
1270 dword = INREG(AUD_CNTL_ST_A);
1271 dword &= ~BITMASK(9, 5);
1272 OUTREG(AUD_CNTL_ST_A, dword);
1273 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1274 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
1275 printf("\n");
1276
1277 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
1278 dword = INREG(AUD_CNTL_ST_B);
1279 dword &= ~BITMASK(9, 5);
1280 OUTREG(AUD_CNTL_ST_B, dword);
1281 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1282 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
1283 printf("\n");
1284
1285 printf("AUD_HDMIW_HDMIEDID_C HDMI ELD:\n\t");
1286 dword = INREG(AUD_CNTL_ST_C);
1287 dword &= ~BITMASK(9, 5);
1288 OUTREG(AUD_CNTL_ST_C, dword);
1289 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1290 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_C)));
1291 printf("\n");
1292
1293 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
1294 dword = INREG(AUD_CNTL_ST_A);
1295 dword &= ~BITMASK(20, 18);
1296 dword &= ~BITMASK(3, 0);
1297 OUTREG(AUD_CNTL_ST_A, dword);
1298 for (i = 0; i < 8; i++)
1299 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
1300 printf("\n");
1301
1302 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
1303 dword = INREG(AUD_CNTL_ST_B);
1304 dword &= ~BITMASK(20, 18);
1305 dword &= ~BITMASK(3, 0);
1306 OUTREG(AUD_CNTL_ST_B, dword);
1307 for (i = 0; i < 8; i++)
1308 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
1309 printf("\n");
1310
1311 printf("AUD_HDMIW_INFOFR_C HDMI audio Infoframe:\n\t");
1312 dword = INREG(AUD_CNTL_ST_C);
1313 dword &= ~BITMASK(20, 18);
1314 dword &= ~BITMASK(3, 0);
1315 OUTREG(AUD_CNTL_ST_C, dword);
1316 for (i = 0; i < 8; i++)
1317 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_C)));
1318 printf("\n");
1319
1320}
1321
1322int main(int argc, char **argv)
1323{
1324 struct pci_device *pci_dev;
1325
1326 pci_dev = intel_get_pci_device();
1327 devid = pci_dev->device_id; /* XXX not true when mapping! */
1328
1329 do_self_tests();
1330
1331 if (argc == 2)
1332 intel_map_file(argv[1]);
1333 else
1334 intel_get_mmio(pci_dev);
1335
Wu Fengguang63e3c372011-11-12 11:12:44 +08001336 if (IS_GEN6(devid) || IS_GEN7(devid) || getenv("HAS_PCH_SPLIT")) {
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001337 printf("%s audio registers:\n\n",
1338 IS_GEN6(devid) ? "SandyBridge" : "IvyBridge");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001339 intel_check_pch();
1340 dump_cpt();
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001341 } else if (IS_GEN5(devid)) {
1342 printf("Ironlake audio registers:\n\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001343 dump_ironlake();
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001344 } else if (IS_G4X(devid)) {
1345 printf("G45 audio registers:\n\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001346 dump_eaglelake();
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001347 }
Wu Fengguang020abdb2010-04-19 13:13:06 +08001348
1349 return 0;
Wu Fengguang9e9c9f22009-11-06 11:06:22 +08001350}