Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 1 | /* |
Daniele Castagna | 7a755de | 2016-12-16 17:32:30 -0500 | [diff] [blame] | 2 | * Copyright 2014 The Chromium OS Authors. All rights reserved. |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 3 | * Use of this source code is governed by a BSD-style license that can be |
| 4 | * found in the LICENSE file. |
| 5 | */ |
| 6 | |
Gurchetan Singh | 46faf6b | 2016-08-05 14:40:07 -0700 | [diff] [blame] | 7 | #ifdef DRV_I915 |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 8 | |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 9 | #include <assert.h> |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 10 | #include <errno.h> |
Gurchetan Singh | 82a8eed | 2017-01-03 13:01:37 -0800 | [diff] [blame] | 11 | #include <i915_drm.h> |
Kristian H. Kristensen | 9c3fb32 | 2018-04-11 15:55:13 -0700 | [diff] [blame] | 12 | #include <stdbool.h> |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 13 | #include <stdio.h> |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 14 | #include <string.h> |
Gurchetan Singh | ef92053 | 2016-08-12 16:38:25 -0700 | [diff] [blame] | 15 | #include <sys/mman.h> |
Gurchetan Singh | cc35e69 | 2019-02-28 15:44:54 -0800 | [diff] [blame] | 16 | #include <unistd.h> |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 17 | #include <xf86drm.h> |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 18 | |
Gurchetan Singh | 46faf6b | 2016-08-05 14:40:07 -0700 | [diff] [blame] | 19 | #include "drv_priv.h" |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 20 | #include "helpers.h" |
| 21 | #include "util.h" |
| 22 | |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 23 | #define I915_CACHELINE_SIZE 64 |
| 24 | #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1) |
| 25 | |
Gurchetan Singh | 62a7f2e | 2019-07-25 20:48:28 -0700 | [diff] [blame] | 26 | static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB1555, |
| 27 | DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565, |
Gurchetan Singh | 71bc665 | 2018-09-17 17:42:05 -0700 | [diff] [blame] | 28 | DRM_FORMAT_XBGR2101010, DRM_FORMAT_XBGR8888, |
Gurchetan Singh | 62a7f2e | 2019-07-25 20:48:28 -0700 | [diff] [blame] | 29 | DRM_FORMAT_XRGB1555, DRM_FORMAT_XRGB2101010, |
| 30 | DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB2101010 }; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 31 | |
Tomasz Figa | b92e4f8 | 2017-06-22 16:52:43 +0900 | [diff] [blame] | 32 | static const uint32_t tileable_texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8, |
| 33 | DRM_FORMAT_UYVY, DRM_FORMAT_YUYV }; |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 34 | |
Tomasz Figa | b92e4f8 | 2017-06-22 16:52:43 +0900 | [diff] [blame] | 35 | static const uint32_t texture_source_formats[] = { DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID, |
Gurchetan Singh | 39490e9 | 2019-05-28 17:49:09 -0700 | [diff] [blame] | 36 | DRM_FORMAT_NV12, DRM_FORMAT_P010 }; |
Gurchetan Singh | 179687e | 2016-10-28 10:07:35 -0700 | [diff] [blame] | 37 | |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 38 | struct i915_device { |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 39 | uint32_t gen; |
| 40 | int32_t has_llc; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 41 | }; |
| 42 | |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 43 | static uint32_t i915_get_gen(int device_id) |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 44 | { |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 45 | const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE, |
| 46 | 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 }; |
Stéphane Marchesin | a39dfde | 2014-09-15 15:38:25 -0700 | [diff] [blame] | 47 | unsigned i; |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 48 | for (i = 0; i < ARRAY_SIZE(gen3_ids); i++) |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 49 | if (gen3_ids[i] == device_id) |
| 50 | return 3; |
| 51 | |
| 52 | return 4; |
| 53 | } |
| 54 | |
Kristian H. Kristensen | 9c3fb32 | 2018-04-11 15:55:13 -0700 | [diff] [blame] | 55 | /* |
| 56 | * We allow allocation of ARGB formats for SCANOUT if the corresponding XRGB |
| 57 | * formats supports it. It's up to the caller (chrome ozone) to ultimately not |
| 58 | * scan out ARGB if the display controller only supports XRGB, but we'll allow |
| 59 | * the allocation of the bo here. |
| 60 | */ |
| 61 | static bool format_compatible(const struct combination *combo, uint32_t format) |
| 62 | { |
| 63 | if (combo->format == format) |
| 64 | return true; |
| 65 | |
| 66 | switch (format) { |
| 67 | case DRM_FORMAT_XRGB8888: |
| 68 | return combo->format == DRM_FORMAT_ARGB8888; |
| 69 | case DRM_FORMAT_XBGR8888: |
| 70 | return combo->format == DRM_FORMAT_ABGR8888; |
| 71 | case DRM_FORMAT_RGBX8888: |
| 72 | return combo->format == DRM_FORMAT_RGBA8888; |
| 73 | case DRM_FORMAT_BGRX8888: |
| 74 | return combo->format == DRM_FORMAT_BGRA8888; |
| 75 | default: |
| 76 | return false; |
| 77 | } |
| 78 | } |
| 79 | |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 80 | static int i915_add_kms_item(struct driver *drv, const struct kms_item *item) |
| 81 | { |
| 82 | uint32_t i; |
| 83 | struct combination *combo; |
| 84 | |
| 85 | /* |
| 86 | * Older hardware can't scanout Y-tiled formats. Newer devices can, and |
| 87 | * report this functionality via format modifiers. |
| 88 | */ |
Gurchetan Singh | bc9a87d | 2017-11-03 17:17:35 -0700 | [diff] [blame] | 89 | for (i = 0; i < drv_array_size(drv->combos); i++) { |
| 90 | combo = (struct combination *)drv_array_at_idx(drv->combos, i); |
Kristian H. Kristensen | 9c3fb32 | 2018-04-11 15:55:13 -0700 | [diff] [blame] | 91 | if (!format_compatible(combo, item->format)) |
Tomasz Figa | e821cc2 | 2017-07-08 15:53:11 +0900 | [diff] [blame] | 92 | continue; |
| 93 | |
Gurchetan Singh | d118a0e | 2018-01-12 23:31:50 +0000 | [diff] [blame] | 94 | if (item->modifier == DRM_FORMAT_MOD_LINEAR && |
Tomasz Figa | e821cc2 | 2017-07-08 15:53:11 +0900 | [diff] [blame] | 95 | combo->metadata.tiling == I915_TILING_X) { |
| 96 | /* |
| 97 | * FIXME: drv_query_kms() does not report the available modifiers |
| 98 | * yet, but we know that all hardware can scanout from X-tiled |
| 99 | * buffers, so let's add this to our combinations, except for |
| 100 | * cursor, which must not be tiled. |
| 101 | */ |
Gurchetan Singh | a1892b2 | 2017-09-28 16:40:52 -0700 | [diff] [blame] | 102 | combo->use_flags |= item->use_flags & ~BO_USE_CURSOR; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 103 | } |
Tomasz Figa | e821cc2 | 2017-07-08 15:53:11 +0900 | [diff] [blame] | 104 | |
Kristian H. Kristensen | 3cb5bba | 2018-04-04 16:10:42 -0700 | [diff] [blame] | 105 | /* If we can scanout NV12, we support all tiling modes. */ |
| 106 | if (item->format == DRM_FORMAT_NV12) |
| 107 | combo->use_flags |= item->use_flags; |
| 108 | |
Tomasz Figa | e821cc2 | 2017-07-08 15:53:11 +0900 | [diff] [blame] | 109 | if (combo->metadata.modifier == item->modifier) |
Gurchetan Singh | a1892b2 | 2017-09-28 16:40:52 -0700 | [diff] [blame] | 110 | combo->use_flags |= item->use_flags; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | return 0; |
| 114 | } |
| 115 | |
| 116 | static int i915_add_combinations(struct driver *drv) |
| 117 | { |
| 118 | int ret; |
Gurchetan Singh | bc9a87d | 2017-11-03 17:17:35 -0700 | [diff] [blame] | 119 | uint32_t i; |
| 120 | struct drv_array *kms_items; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 121 | struct format_metadata metadata; |
Gurchetan Singh | a1892b2 | 2017-09-28 16:40:52 -0700 | [diff] [blame] | 122 | uint64_t render_use_flags, texture_use_flags; |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 123 | |
Gurchetan Singh | a1892b2 | 2017-09-28 16:40:52 -0700 | [diff] [blame] | 124 | render_use_flags = BO_USE_RENDER_MASK; |
| 125 | texture_use_flags = BO_USE_TEXTURE_MASK; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 126 | |
| 127 | metadata.tiling = I915_TILING_NONE; |
| 128 | metadata.priority = 1; |
Kristian H. Kristensen | bc8c593 | 2017-10-24 18:36:32 -0700 | [diff] [blame] | 129 | metadata.modifier = DRM_FORMAT_MOD_LINEAR; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 130 | |
Gurchetan Singh | d300145 | 2017-11-03 17:18:36 -0700 | [diff] [blame] | 131 | drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), |
| 132 | &metadata, render_use_flags); |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 133 | |
Gurchetan Singh | d300145 | 2017-11-03 17:18:36 -0700 | [diff] [blame] | 134 | drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats), |
| 135 | &metadata, texture_use_flags); |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 136 | |
Gurchetan Singh | d300145 | 2017-11-03 17:18:36 -0700 | [diff] [blame] | 137 | drv_add_combinations(drv, tileable_texture_source_formats, |
| 138 | ARRAY_SIZE(tileable_texture_source_formats), &metadata, |
| 139 | texture_use_flags); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 140 | |
Hirokazu Honda | 3b8d4d0 | 2019-07-31 16:35:52 +0900 | [diff] [blame^] | 141 | /* |
| 142 | * Chrome uses DMA-buf mmap to write to YV12 buffers, which are then accessed by the |
| 143 | * Video Encoder Accelerator (VEA). It could also support NV12 potentially in the future. |
| 144 | */ |
| 145 | drv_modify_combination(drv, DRM_FORMAT_YVU420, &metadata, BO_USE_HW_VIDEO_ENCODER); |
| 146 | drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata, BO_USE_HW_VIDEO_ENCODER); |
| 147 | |
Gurchetan Singh | 71bc665 | 2018-09-17 17:42:05 -0700 | [diff] [blame] | 148 | /* Android CTS tests require this. */ |
| 149 | drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK); |
| 150 | |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 151 | drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); |
| 152 | drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 153 | |
Tomasz Figa | d30c0a5 | 2017-07-05 17:50:18 +0900 | [diff] [blame] | 154 | /* IPU3 camera ISP supports only NV12 output. */ |
| 155 | drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata, |
Tomasz Figa | fd0b016 | 2017-07-11 18:28:02 +0900 | [diff] [blame] | 156 | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE); |
Tomasz Figa | d30c0a5 | 2017-07-05 17:50:18 +0900 | [diff] [blame] | 157 | /* |
| 158 | * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots |
| 159 | * from camera. |
| 160 | */ |
| 161 | drv_modify_combination(drv, DRM_FORMAT_R8, &metadata, |
Tomasz Figa | fd0b016 | 2017-07-11 18:28:02 +0900 | [diff] [blame] | 162 | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE); |
Tomasz Figa | d30c0a5 | 2017-07-05 17:50:18 +0900 | [diff] [blame] | 163 | |
Gurchetan Singh | a1892b2 | 2017-09-28 16:40:52 -0700 | [diff] [blame] | 164 | render_use_flags &= ~BO_USE_RENDERSCRIPT; |
| 165 | render_use_flags &= ~BO_USE_SW_WRITE_OFTEN; |
| 166 | render_use_flags &= ~BO_USE_SW_READ_OFTEN; |
| 167 | render_use_flags &= ~BO_USE_LINEAR; |
Gurchetan Singh | 2b1d689 | 2018-09-17 16:58:16 -0700 | [diff] [blame] | 168 | render_use_flags &= ~BO_USE_PROTECTED; |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 169 | |
Gurchetan Singh | a1892b2 | 2017-09-28 16:40:52 -0700 | [diff] [blame] | 170 | texture_use_flags &= ~BO_USE_RENDERSCRIPT; |
| 171 | texture_use_flags &= ~BO_USE_SW_WRITE_OFTEN; |
| 172 | texture_use_flags &= ~BO_USE_SW_READ_OFTEN; |
| 173 | texture_use_flags &= ~BO_USE_LINEAR; |
Gurchetan Singh | 2b1d689 | 2018-09-17 16:58:16 -0700 | [diff] [blame] | 174 | texture_use_flags &= ~BO_USE_PROTECTED; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 175 | |
| 176 | metadata.tiling = I915_TILING_X; |
| 177 | metadata.priority = 2; |
Tomasz Figa | e821cc2 | 2017-07-08 15:53:11 +0900 | [diff] [blame] | 178 | metadata.modifier = I915_FORMAT_MOD_X_TILED; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 179 | |
Gurchetan Singh | d300145 | 2017-11-03 17:18:36 -0700 | [diff] [blame] | 180 | drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), |
| 181 | &metadata, render_use_flags); |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 182 | |
Gurchetan Singh | d300145 | 2017-11-03 17:18:36 -0700 | [diff] [blame] | 183 | drv_add_combinations(drv, tileable_texture_source_formats, |
| 184 | ARRAY_SIZE(tileable_texture_source_formats), &metadata, |
| 185 | texture_use_flags); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 186 | |
| 187 | metadata.tiling = I915_TILING_Y; |
| 188 | metadata.priority = 3; |
Tomasz Figa | e821cc2 | 2017-07-08 15:53:11 +0900 | [diff] [blame] | 189 | metadata.modifier = I915_FORMAT_MOD_Y_TILED; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 190 | |
Gurchetan Singh | d300145 | 2017-11-03 17:18:36 -0700 | [diff] [blame] | 191 | drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), |
| 192 | &metadata, render_use_flags); |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 193 | |
Gurchetan Singh | d300145 | 2017-11-03 17:18:36 -0700 | [diff] [blame] | 194 | drv_add_combinations(drv, tileable_texture_source_formats, |
| 195 | ARRAY_SIZE(tileable_texture_source_formats), &metadata, |
| 196 | texture_use_flags); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 197 | |
Miguel Casas | cdb2554 | 2019-07-18 13:07:30 -0400 | [diff] [blame] | 198 | /* Support y-tiled NV12 and P010 for libva */ |
Gurchetan Singh | 86ddfdc | 2018-09-17 17:13:45 -0700 | [diff] [blame] | 199 | drv_add_combination(drv, DRM_FORMAT_NV12, &metadata, |
| 200 | BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER); |
Miguel Casas | cdb2554 | 2019-07-18 13:07:30 -0400 | [diff] [blame] | 201 | drv_add_combination(drv, DRM_FORMAT_P010, &metadata, |
| 202 | BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER); |
Kristian H. Kristensen | 3cb5bba | 2018-04-04 16:10:42 -0700 | [diff] [blame] | 203 | |
Gurchetan Singh | bc9a87d | 2017-11-03 17:17:35 -0700 | [diff] [blame] | 204 | kms_items = drv_query_kms(drv); |
| 205 | if (!kms_items) |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 206 | return 0; |
| 207 | |
Gurchetan Singh | bc9a87d | 2017-11-03 17:17:35 -0700 | [diff] [blame] | 208 | for (i = 0; i < drv_array_size(kms_items); i++) { |
| 209 | ret = i915_add_kms_item(drv, (struct kms_item *)drv_array_at_idx(kms_items, i)); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 210 | if (ret) { |
Gurchetan Singh | bc9a87d | 2017-11-03 17:17:35 -0700 | [diff] [blame] | 211 | drv_array_destroy(kms_items); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 212 | return ret; |
| 213 | } |
| 214 | } |
| 215 | |
Gurchetan Singh | bc9a87d | 2017-11-03 17:17:35 -0700 | [diff] [blame] | 216 | drv_array_destroy(kms_items); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 217 | return 0; |
| 218 | } |
| 219 | |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 220 | static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride, |
| 221 | uint32_t *aligned_height) |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 222 | { |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 223 | struct i915_device *i915 = bo->drv->priv; |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 224 | uint32_t horizontal_alignment; |
| 225 | uint32_t vertical_alignment; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 226 | |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 227 | switch (tiling) { |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 228 | default: |
| 229 | case I915_TILING_NONE: |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 230 | /* |
| 231 | * The Intel GPU doesn't need any alignment in linear mode, |
| 232 | * but libva requires the allocation stride to be aligned to |
| 233 | * 16 bytes and height to 4 rows. Further, we round up the |
| 234 | * horizontal alignment so that row start on a cache line (64 |
| 235 | * bytes). |
| 236 | */ |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 237 | horizontal_alignment = 64; |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 238 | vertical_alignment = 4; |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 239 | break; |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 240 | |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 241 | case I915_TILING_X: |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 242 | horizontal_alignment = 512; |
| 243 | vertical_alignment = 8; |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 244 | break; |
| 245 | |
| 246 | case I915_TILING_Y: |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 247 | if (i915->gen == 3) { |
| 248 | horizontal_alignment = 512; |
| 249 | vertical_alignment = 8; |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 250 | } else { |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 251 | horizontal_alignment = 128; |
| 252 | vertical_alignment = 32; |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 253 | } |
| 254 | break; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 255 | } |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 256 | |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 257 | *aligned_height = ALIGN(bo->height, vertical_alignment); |
| 258 | if (i915->gen > 3) { |
| 259 | *stride = ALIGN(*stride, horizontal_alignment); |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 260 | } else { |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 261 | while (*stride > horizontal_alignment) |
| 262 | horizontal_alignment <<= 1; |
| 263 | |
| 264 | *stride = horizontal_alignment; |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 265 | } |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 266 | |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 267 | if (i915->gen <= 3 && *stride > 8192) |
| 268 | return -EINVAL; |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 269 | |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 270 | return 0; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 271 | } |
| 272 | |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 273 | static void i915_clflush(void *start, size_t size) |
| 274 | { |
| 275 | void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK); |
| 276 | void *end = (void *)((uintptr_t)start + size); |
| 277 | |
| 278 | __builtin_ia32_mfence(); |
| 279 | while (p < end) { |
| 280 | __builtin_ia32_clflush(p); |
| 281 | p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE); |
| 282 | } |
| 283 | } |
| 284 | |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 285 | static int i915_init(struct driver *drv) |
| 286 | { |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 287 | int ret; |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 288 | int device_id; |
| 289 | struct i915_device *i915; |
| 290 | drm_i915_getparam_t get_param; |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 291 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 292 | i915 = calloc(1, sizeof(*i915)); |
| 293 | if (!i915) |
| 294 | return -ENOMEM; |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 295 | |
| 296 | memset(&get_param, 0, sizeof(get_param)); |
| 297 | get_param.param = I915_PARAM_CHIPSET_ID; |
| 298 | get_param.value = &device_id; |
| 299 | ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param); |
| 300 | if (ret) { |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 301 | drv_log("Failed to get I915_PARAM_CHIPSET_ID\n"); |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 302 | free(i915); |
Gurchetan Singh | 82a8eed | 2017-01-03 13:01:37 -0800 | [diff] [blame] | 303 | return -EINVAL; |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 304 | } |
| 305 | |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 306 | i915->gen = i915_get_gen(device_id); |
| 307 | |
| 308 | memset(&get_param, 0, sizeof(get_param)); |
| 309 | get_param.param = I915_PARAM_HAS_LLC; |
| 310 | get_param.value = &i915->has_llc; |
| 311 | ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param); |
| 312 | if (ret) { |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 313 | drv_log("Failed to get I915_PARAM_HAS_LLC\n"); |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 314 | free(i915); |
| 315 | return -EINVAL; |
| 316 | } |
| 317 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 318 | drv->priv = i915; |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 319 | |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 320 | return i915_add_combinations(drv); |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 321 | } |
| 322 | |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 323 | static int i915_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, uint32_t format) |
| 324 | { |
| 325 | uint32_t offset; |
| 326 | size_t plane; |
Gurchetan Singh | cc35e69 | 2019-02-28 15:44:54 -0800 | [diff] [blame] | 327 | int ret, pagesize; |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 328 | |
| 329 | offset = 0; |
Gurchetan Singh | cc35e69 | 2019-02-28 15:44:54 -0800 | [diff] [blame] | 330 | pagesize = getpagesize(); |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 331 | for (plane = 0; plane < drv_num_planes_from_format(format); plane++) { |
| 332 | uint32_t stride = drv_stride_from_format(format, width, plane); |
| 333 | uint32_t plane_height = drv_height_from_format(format, height, plane); |
| 334 | |
| 335 | if (bo->tiling != I915_TILING_NONE) |
Gurchetan Singh | cc35e69 | 2019-02-28 15:44:54 -0800 | [diff] [blame] | 336 | assert(IS_ALIGNED(offset, pagesize)); |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 337 | |
| 338 | ret = i915_align_dimensions(bo, bo->tiling, &stride, &plane_height); |
| 339 | if (ret) |
| 340 | return ret; |
| 341 | |
| 342 | bo->strides[plane] = stride; |
| 343 | bo->sizes[plane] = stride * plane_height; |
| 344 | bo->offsets[plane] = offset; |
| 345 | offset += bo->sizes[plane]; |
| 346 | } |
| 347 | |
Gurchetan Singh | cc35e69 | 2019-02-28 15:44:54 -0800 | [diff] [blame] | 348 | bo->total_size = ALIGN(offset, pagesize); |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 349 | |
| 350 | return 0; |
| 351 | } |
| 352 | |
Kristian H. Kristensen | 6061eab | 2017-10-03 13:53:19 -0700 | [diff] [blame] | 353 | static int i915_bo_create_for_modifier(struct bo *bo, uint32_t width, uint32_t height, |
| 354 | uint32_t format, uint64_t modifier) |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 355 | { |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 356 | int ret; |
Gurchetan Singh | 82a8eed | 2017-01-03 13:01:37 -0800 | [diff] [blame] | 357 | size_t plane; |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 358 | struct drm_i915_gem_create gem_create; |
| 359 | struct drm_i915_gem_set_tiling gem_set_tiling; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 360 | |
Kristian H. Kristensen | 6061eab | 2017-10-03 13:53:19 -0700 | [diff] [blame] | 361 | switch (modifier) { |
| 362 | case DRM_FORMAT_MOD_LINEAR: |
| 363 | bo->tiling = I915_TILING_NONE; |
| 364 | break; |
| 365 | case I915_FORMAT_MOD_X_TILED: |
| 366 | bo->tiling = I915_TILING_X; |
| 367 | break; |
| 368 | case I915_FORMAT_MOD_Y_TILED: |
Mark Yacoub | a086897 | 2019-07-25 11:08:07 -0400 | [diff] [blame] | 369 | case I915_FORMAT_MOD_Y_TILED_CCS: |
Kristian H. Kristensen | 6061eab | 2017-10-03 13:53:19 -0700 | [diff] [blame] | 370 | bo->tiling = I915_TILING_Y; |
| 371 | break; |
| 372 | } |
Owen Lin | bbb69fd | 2017-06-05 14:33:08 +0800 | [diff] [blame] | 373 | |
Kristian H. Kristensen | 2b8f89e | 2018-02-07 16:10:06 -0800 | [diff] [blame] | 374 | bo->format_modifiers[0] = modifier; |
| 375 | |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 376 | if (format == DRM_FORMAT_YVU420_ANDROID) { |
| 377 | /* |
| 378 | * We only need to be able to use this as a linear texture, |
| 379 | * which doesn't put any HW restrictions on how we lay it |
| 380 | * out. The Android format does require the stride to be a |
| 381 | * multiple of 16 and expects the Cr and Cb stride to be |
| 382 | * ALIGN(Y_stride / 2, 16), which we can make happen by |
| 383 | * aligning to 32 bytes here. |
| 384 | */ |
| 385 | uint32_t stride = ALIGN(width, 32); |
| 386 | drv_bo_from_format(bo, stride, height, format); |
Mark Yacoub | a086897 | 2019-07-25 11:08:07 -0400 | [diff] [blame] | 387 | } else if (modifier == I915_FORMAT_MOD_Y_TILED_CCS) { |
| 388 | /* |
| 389 | * For compressed surfaces, we need a color control surface |
| 390 | * (CCS). Color compression is only supported for Y tiled |
| 391 | * surfaces, and for each 32x16 tiles in the main surface we |
| 392 | * need a tile in the control surface. Y tiles are 128 bytes |
| 393 | * wide and 32 lines tall and we use that to first compute the |
| 394 | * width and height in tiles of the main surface. stride and |
| 395 | * height are already multiples of 128 and 32, respectively: |
| 396 | */ |
| 397 | uint32_t stride = drv_stride_from_format(format, width, 0); |
| 398 | uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128); |
| 399 | uint32_t height_in_tiles = DIV_ROUND_UP(height, 32); |
| 400 | uint32_t size = width_in_tiles * height_in_tiles * 4096; |
| 401 | uint32_t offset = 0; |
| 402 | |
| 403 | bo->strides[0] = width_in_tiles * 128; |
| 404 | bo->sizes[0] = size; |
| 405 | bo->offsets[0] = offset; |
| 406 | offset += size; |
| 407 | |
| 408 | /* |
| 409 | * Now, compute the width and height in tiles of the control |
| 410 | * surface by dividing and rounding up. |
| 411 | */ |
| 412 | uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32); |
| 413 | uint32_t ccs_height_in_tiles = DIV_ROUND_UP(height_in_tiles, 16); |
| 414 | uint32_t ccs_size = ccs_width_in_tiles * ccs_height_in_tiles * 4096; |
| 415 | |
| 416 | /* |
| 417 | * With stride and height aligned to y tiles, offset is |
| 418 | * already a multiple of 4096, which is the required alignment |
| 419 | * of the CCS. |
| 420 | */ |
| 421 | bo->strides[1] = ccs_width_in_tiles * 128; |
| 422 | bo->sizes[1] = ccs_size; |
| 423 | bo->offsets[1] = offset; |
| 424 | offset += ccs_size; |
| 425 | |
| 426 | bo->num_planes = 2; |
| 427 | bo->total_size = offset; |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 428 | } else { |
| 429 | i915_bo_from_format(bo, width, height, format); |
| 430 | } |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 431 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 432 | memset(&gem_create, 0, sizeof(gem_create)); |
| 433 | gem_create.size = bo->total_size; |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 434 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 435 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create); |
| 436 | if (ret) { |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 437 | drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size); |
Stéphane Marchesin | 6ac299f | 2019-03-21 12:23:29 -0700 | [diff] [blame] | 438 | return -errno; |
Ilja H. Friedel | f9d2ab7 | 2015-04-09 14:08:36 -0700 | [diff] [blame] | 439 | } |
Gurchetan Singh | 83dc4fb | 2016-07-19 15:52:33 -0700 | [diff] [blame] | 440 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 441 | for (plane = 0; plane < bo->num_planes; plane++) |
| 442 | bo->handles[plane].u32 = gem_create.handle; |
Daniel Nicoara | 1de26dc | 2014-09-25 18:53:19 -0400 | [diff] [blame] | 443 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 444 | memset(&gem_set_tiling, 0, sizeof(gem_set_tiling)); |
| 445 | gem_set_tiling.handle = bo->handles[0].u32; |
| 446 | gem_set_tiling.tiling_mode = bo->tiling; |
| 447 | gem_set_tiling.stride = bo->strides[0]; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 448 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 449 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling); |
| 450 | if (ret) { |
| 451 | struct drm_gem_close gem_close; |
| 452 | memset(&gem_close, 0, sizeof(gem_close)); |
| 453 | gem_close.handle = bo->handles[0].u32; |
| 454 | drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close); |
Gurchetan Singh | 82a8eed | 2017-01-03 13:01:37 -0800 | [diff] [blame] | 455 | |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 456 | drv_log("DRM_IOCTL_I915_GEM_SET_TILING failed with %d\n", errno); |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 457 | return -errno; |
| 458 | } |
| 459 | |
| 460 | return 0; |
| 461 | } |
| 462 | |
Kristian H. Kristensen | 6061eab | 2017-10-03 13:53:19 -0700 | [diff] [blame] | 463 | static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format, |
| 464 | uint64_t use_flags) |
| 465 | { |
| 466 | struct combination *combo; |
| 467 | |
| 468 | combo = drv_get_combination(bo->drv, format, use_flags); |
| 469 | if (!combo) |
| 470 | return -EINVAL; |
| 471 | |
| 472 | return i915_bo_create_for_modifier(bo, width, height, format, combo->metadata.modifier); |
| 473 | } |
| 474 | |
| 475 | static int i915_bo_create_with_modifiers(struct bo *bo, uint32_t width, uint32_t height, |
| 476 | uint32_t format, const uint64_t *modifiers, uint32_t count) |
| 477 | { |
| 478 | static const uint64_t modifier_order[] = { |
Mark Yacoub | a086897 | 2019-07-25 11:08:07 -0400 | [diff] [blame] | 479 | I915_FORMAT_MOD_Y_TILED_CCS, |
Gurchetan Singh | 2b1d689 | 2018-09-17 16:58:16 -0700 | [diff] [blame] | 480 | I915_FORMAT_MOD_Y_TILED, |
| 481 | I915_FORMAT_MOD_X_TILED, |
| 482 | DRM_FORMAT_MOD_LINEAR, |
Kristian H. Kristensen | 6061eab | 2017-10-03 13:53:19 -0700 | [diff] [blame] | 483 | }; |
| 484 | uint64_t modifier; |
| 485 | |
| 486 | modifier = drv_pick_modifier(modifiers, count, modifier_order, ARRAY_SIZE(modifier_order)); |
| 487 | |
Kristian H. Kristensen | 6061eab | 2017-10-03 13:53:19 -0700 | [diff] [blame] | 488 | return i915_bo_create_for_modifier(bo, width, height, format, modifier); |
| 489 | } |
| 490 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 491 | static void i915_close(struct driver *drv) |
Gurchetan Singh | 82a8eed | 2017-01-03 13:01:37 -0800 | [diff] [blame] | 492 | { |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 493 | free(drv->priv); |
| 494 | drv->priv = NULL; |
Gurchetan Singh | 82a8eed | 2017-01-03 13:01:37 -0800 | [diff] [blame] | 495 | } |
| 496 | |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 497 | static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data) |
| 498 | { |
| 499 | int ret; |
| 500 | struct drm_i915_gem_get_tiling gem_get_tiling; |
| 501 | |
| 502 | ret = drv_prime_bo_import(bo, data); |
| 503 | if (ret) |
| 504 | return ret; |
| 505 | |
| 506 | /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */ |
| 507 | memset(&gem_get_tiling, 0, sizeof(gem_get_tiling)); |
| 508 | gem_get_tiling.handle = bo->handles[0].u32; |
| 509 | |
| 510 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling); |
| 511 | if (ret) { |
Joe Kniss | 9e5d12a | 2017-06-29 11:54:22 -0700 | [diff] [blame] | 512 | drv_gem_bo_destroy(bo); |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 513 | drv_log("DRM_IOCTL_I915_GEM_GET_TILING failed.\n"); |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 514 | return ret; |
| 515 | } |
| 516 | |
| 517 | bo->tiling = gem_get_tiling.tiling_mode; |
| 518 | return 0; |
| 519 | } |
| 520 | |
Gurchetan Singh | ee43c30 | 2017-11-14 18:20:27 -0800 | [diff] [blame] | 521 | static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags) |
Gurchetan Singh | ef92053 | 2016-08-12 16:38:25 -0700 | [diff] [blame] | 522 | { |
| 523 | int ret; |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 524 | void *addr; |
Gurchetan Singh | ef92053 | 2016-08-12 16:38:25 -0700 | [diff] [blame] | 525 | |
Mark Yacoub | a086897 | 2019-07-25 11:08:07 -0400 | [diff] [blame] | 526 | if (bo->format_modifiers[0] == I915_FORMAT_MOD_Y_TILED_CCS) |
| 527 | return MAP_FAILED; |
| 528 | |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 529 | if (bo->tiling == I915_TILING_NONE) { |
| 530 | struct drm_i915_gem_mmap gem_map; |
| 531 | memset(&gem_map, 0, sizeof(gem_map)); |
Gurchetan Singh | ef92053 | 2016-08-12 16:38:25 -0700 | [diff] [blame] | 532 | |
Tomasz Figa | 39eb951 | 2018-11-01 00:45:31 +0900 | [diff] [blame] | 533 | /* TODO(b/118799155): We don't seem to have a good way to |
| 534 | * detect the use cases for which WC mapping is really needed. |
| 535 | * The current heuristic seems overly coarse and may be slowing |
| 536 | * down some other use cases unnecessarily. |
| 537 | * |
| 538 | * For now, care must be taken not to use WC mappings for |
| 539 | * Renderscript and camera use cases, as they're |
| 540 | * performance-sensitive. */ |
| 541 | if ((bo->use_flags & BO_USE_SCANOUT) && |
| 542 | !(bo->use_flags & |
| 543 | (BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))) |
Gurchetan Singh | 5af2023 | 2017-09-19 15:10:58 -0700 | [diff] [blame] | 544 | gem_map.flags = I915_MMAP_WC; |
| 545 | |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 546 | gem_map.handle = bo->handles[0].u32; |
| 547 | gem_map.offset = 0; |
| 548 | gem_map.size = bo->total_size; |
| 549 | |
| 550 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map); |
| 551 | if (ret) { |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 552 | drv_log("DRM_IOCTL_I915_GEM_MMAP failed\n"); |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 553 | return MAP_FAILED; |
| 554 | } |
| 555 | |
| 556 | addr = (void *)(uintptr_t)gem_map.addr_ptr; |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 557 | } else { |
| 558 | struct drm_i915_gem_mmap_gtt gem_map; |
| 559 | memset(&gem_map, 0, sizeof(gem_map)); |
| 560 | |
| 561 | gem_map.handle = bo->handles[0].u32; |
| 562 | |
| 563 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map); |
| 564 | if (ret) { |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 565 | drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n"); |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 566 | return MAP_FAILED; |
| 567 | } |
| 568 | |
Gurchetan Singh | cfb8876 | 2017-09-28 17:14:50 -0700 | [diff] [blame] | 569 | addr = mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd, |
| 570 | gem_map.offset); |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 571 | } |
| 572 | |
| 573 | if (addr == MAP_FAILED) { |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 574 | drv_log("i915 GEM mmap failed\n"); |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 575 | return addr; |
| 576 | } |
| 577 | |
Gurchetan Singh | ee43c30 | 2017-11-14 18:20:27 -0800 | [diff] [blame] | 578 | vma->length = bo->total_size; |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 579 | return addr; |
| 580 | } |
Gurchetan Singh | 1a31e60 | 2016-10-06 10:58:00 -0700 | [diff] [blame] | 581 | |
Gurchetan Singh | 47e629b | 2017-11-02 14:07:18 -0700 | [diff] [blame] | 582 | static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping) |
Gurchetan Singh | 2d1877f | 2017-10-10 14:12:46 -0700 | [diff] [blame] | 583 | { |
| 584 | int ret; |
| 585 | struct drm_i915_gem_set_domain set_domain; |
| 586 | |
| 587 | memset(&set_domain, 0, sizeof(set_domain)); |
| 588 | set_domain.handle = bo->handles[0].u32; |
| 589 | if (bo->tiling == I915_TILING_NONE) { |
| 590 | set_domain.read_domains = I915_GEM_DOMAIN_CPU; |
Gurchetan Singh | 47e629b | 2017-11-02 14:07:18 -0700 | [diff] [blame] | 591 | if (mapping->vma->map_flags & BO_MAP_WRITE) |
Gurchetan Singh | 2d1877f | 2017-10-10 14:12:46 -0700 | [diff] [blame] | 592 | set_domain.write_domain = I915_GEM_DOMAIN_CPU; |
| 593 | } else { |
| 594 | set_domain.read_domains = I915_GEM_DOMAIN_GTT; |
Gurchetan Singh | 47e629b | 2017-11-02 14:07:18 -0700 | [diff] [blame] | 595 | if (mapping->vma->map_flags & BO_MAP_WRITE) |
Gurchetan Singh | 2d1877f | 2017-10-10 14:12:46 -0700 | [diff] [blame] | 596 | set_domain.write_domain = I915_GEM_DOMAIN_GTT; |
| 597 | } |
| 598 | |
| 599 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain); |
| 600 | if (ret) { |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 601 | drv_log("DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret); |
Gurchetan Singh | 2d1877f | 2017-10-10 14:12:46 -0700 | [diff] [blame] | 602 | return ret; |
| 603 | } |
| 604 | |
| 605 | return 0; |
| 606 | } |
| 607 | |
Gurchetan Singh | 47e629b | 2017-11-02 14:07:18 -0700 | [diff] [blame] | 608 | static int i915_bo_flush(struct bo *bo, struct mapping *mapping) |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 609 | { |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 610 | struct i915_device *i915 = bo->drv->priv; |
| 611 | if (!i915->has_llc && bo->tiling == I915_TILING_NONE) |
Gurchetan Singh | 47e629b | 2017-11-02 14:07:18 -0700 | [diff] [blame] | 612 | i915_clflush(mapping->vma->addr, mapping->vma->length); |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 613 | |
Gurchetan Singh | 8e02e05 | 2017-09-14 14:18:43 -0700 | [diff] [blame] | 614 | return 0; |
Gurchetan Singh | ef92053 | 2016-08-12 16:38:25 -0700 | [diff] [blame] | 615 | } |
| 616 | |
Gurchetan Singh | 0d44d48 | 2019-06-04 19:39:51 -0700 | [diff] [blame] | 617 | static uint32_t i915_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags) |
Gurchetan Singh | bfba8c2 | 2016-08-16 17:57:10 -0700 | [diff] [blame] | 618 | { |
| 619 | switch (format) { |
Gurchetan Singh | f3b22da | 2016-11-21 10:46:38 -0800 | [diff] [blame] | 620 | case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED: |
Tomasz Figa | d30c0a5 | 2017-07-05 17:50:18 +0900 | [diff] [blame] | 621 | /* KBL camera subsystem requires NV12. */ |
Gurchetan Singh | a1892b2 | 2017-09-28 16:40:52 -0700 | [diff] [blame] | 622 | if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)) |
Tomasz Figa | d30c0a5 | 2017-07-05 17:50:18 +0900 | [diff] [blame] | 623 | return DRM_FORMAT_NV12; |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 624 | /*HACK: See b/28671744 */ |
Gurchetan Singh | f3b22da | 2016-11-21 10:46:38 -0800 | [diff] [blame] | 625 | return DRM_FORMAT_XBGR8888; |
| 626 | case DRM_FORMAT_FLEX_YCbCr_420_888: |
Tomasz Figa | b92e4f8 | 2017-06-22 16:52:43 +0900 | [diff] [blame] | 627 | /* |
| 628 | * KBL camera subsystem requires NV12. Our other use cases |
| 629 | * don't care: |
| 630 | * - Hardware video supports NV12, |
| 631 | * - USB Camera HALv3 supports NV12, |
| 632 | * - USB Camera HALv1 doesn't use this format. |
| 633 | * Moreover, NV12 is preferred for video, due to overlay |
| 634 | * support on SKL+. |
| 635 | */ |
| 636 | return DRM_FORMAT_NV12; |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 637 | default: |
| 638 | return format; |
Gurchetan Singh | bfba8c2 | 2016-08-16 17:57:10 -0700 | [diff] [blame] | 639 | } |
| 640 | } |
| 641 | |
Gurchetan Singh | 3e9d383 | 2017-10-31 10:36:25 -0700 | [diff] [blame] | 642 | const struct backend backend_i915 = { |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 643 | .name = "i915", |
Gurchetan Singh | d7c84fd | 2016-08-16 18:18:24 -0700 | [diff] [blame] | 644 | .init = i915_init, |
| 645 | .close = i915_close, |
| 646 | .bo_create = i915_bo_create, |
Kristian H. Kristensen | 6061eab | 2017-10-03 13:53:19 -0700 | [diff] [blame] | 647 | .bo_create_with_modifiers = i915_bo_create_with_modifiers, |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 648 | .bo_destroy = drv_gem_bo_destroy, |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 649 | .bo_import = i915_bo_import, |
Gurchetan Singh | d7c84fd | 2016-08-16 18:18:24 -0700 | [diff] [blame] | 650 | .bo_map = i915_bo_map, |
Gurchetan Singh | 8e02e05 | 2017-09-14 14:18:43 -0700 | [diff] [blame] | 651 | .bo_unmap = drv_bo_munmap, |
Gurchetan Singh | 2d1877f | 2017-10-10 14:12:46 -0700 | [diff] [blame] | 652 | .bo_invalidate = i915_bo_invalidate, |
Gurchetan Singh | 8e02e05 | 2017-09-14 14:18:43 -0700 | [diff] [blame] | 653 | .bo_flush = i915_bo_flush, |
Gurchetan Singh | bfba8c2 | 2016-08-16 17:57:10 -0700 | [diff] [blame] | 654 | .resolve_format = i915_resolve_format, |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 655 | }; |
| 656 | |
| 657 | #endif |