Blame - llvm/lib/Target/R600/AMDGPU.td - toolchain/llvm-project

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Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1	//===-- AMDIL.td - AMDIL Tablegen files --- tablegen --------------------===//
				2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//==-----------------------------------------------------------------------===//
				9
Tom Stellard	bc5b537	2014-06-13 16:38:59 +0000	[diff] [blame]	10	include "llvm/Target/Target.td"
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	11
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	12	//===----------------------------------------------------------------------===//
				13	// Subtarget Features
				14	//===----------------------------------------------------------------------===//
				15
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	16	// Debugging Features
				17
				18	def FeatureDumpCode : SubtargetFeature <"DumpCode",
				19	"DumpCode",
				20	"true",
				21	"Dump MachineInstrs in the CodeEmitter">;
				22
Tom Stellard	66df8a2	2013-11-18 19:43:44 +0000	[diff] [blame]	23	def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
Tom Stellard	ed0ceec	2013-10-10 17:11:12 +0000	[diff] [blame]	24	"EnableIRStructurizer",
Tom Stellard	66df8a2	2013-11-18 19:43:44 +0000	[diff] [blame]	25	"false",
				26	"Disable IR Structurizer">;
Tom Stellard	ed0ceec	2013-10-10 17:11:12 +0000	[diff] [blame]	27
Matt Arsenault	d9a23ab	2014-07-13 02:08:26 +0000	[diff] [blame]	28	def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
				29	"EnablePromoteAlloca",
				30	"true",
				31	"Enable promote alloca pass">;
				32
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	33	// Target features
				34
Tom Stellard	783893a	2013-11-18 19:43:33 +0000	[diff] [blame]	35	def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
				36	"EnableIfCvt",
				37	"false",
				38	"Disable the if conversion pass">;
				39
Matt Arsenault	f5e2997	2014-06-20 06:50:05 +0000	[diff] [blame]	40	def FeatureFP64 : SubtargetFeature<"fp64",
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	41	"FP64",
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	42	"true",
Matt Arsenault	f5e2997	2014-06-20 06:50:05 +0000	[diff] [blame]	43	"Enable double precision operations">;
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	44
Matt Arsenault	f171cf2	2014-07-14 23:40:49 +0000	[diff] [blame]	45	def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
				46	"FP64Denormals",
				47	"true",
				48	"Enable double precision denormal handling",
				49	[FeatureFP64]>;
				50
Matt Arsenault	b035a57	2015-01-29 19:34:25 +0000	[diff] [blame]	51	def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
				52	"FastFMAF32",
				53	"true",
				54	"Assuming f32 fma is at least as fast as mul + add",
				55	[]>;
				56
Matt Arsenault	f171cf2	2014-07-14 23:40:49 +0000	[diff] [blame]	57	// Some instructions do not support denormals despite this flag. Using
				58	// fp32 denormals also causes instructions to run at the double
				59	// precision rate for the device.
				60	def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
				61	"FP32Denormals",
				62	"true",
				63	"Enable single precision denormal handling">;
				64
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	65	def Feature64BitPtr : SubtargetFeature<"64BitPtr",
				66	"Is64bit",
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	67	"true",
Matt Arsenault	f5e2997	2014-06-20 06:50:05 +0000	[diff] [blame]	68	"Specify if 64-bit addressing should be used">;
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	69
				70	def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
				71	"R600ALUInst",
				72	"false",
Matt Arsenault	f5e2997	2014-06-20 06:50:05 +0000	[diff] [blame]	73	"Older version of ALU instructions encoding">;
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	74
				75	def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
				76	"HasVertexCache",
				77	"true",
Matt Arsenault	f5e2997	2014-06-20 06:50:05 +0000	[diff] [blame]	78	"Specify use of dedicated vertex cache">;
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	79
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	80	def FeatureCaymanISA : SubtargetFeature<"caymanISA",
				81	"CaymanISA",
				82	"true",
				83	"Use Cayman ISA">;
				84
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	85	def FeatureCFALUBug : SubtargetFeature<"cfalubug",
				86	"CFALUBug",
				87	"true",
				88	"GPU has CF_ALU bug">;
				89
Matt Arsenault	4103328	2014-10-10 22:01:59 +0000	[diff] [blame]	90	// XXX - This should probably be removed once enabled by default
				91	def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
				92	"EnableLoadStoreOpt",
				93	"true",
				94	"Enable SI load/store optimizer pass">;
				95
Matt Arsenault	3f98140	2014-09-15 15:41:53 +0000	[diff] [blame]	96	def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
				97	"FlatAddressSpace",
				98	"true",
				99	"Support flat address space">;
				100
Tom Stellard	e99fb65	2015-01-20 19:33:04 +0000	[diff] [blame]	101	def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
				102	"EnableVGPRSpilling",
				103	"true",
				104	"Enable spilling of VGPRs to scratch memory">;
				105
Tom Stellard	3498e4f	2013-06-07 20:28:55 +0000	[diff] [blame]	106	class SubtargetFeatureFetchLimit <string Value> :
				107	SubtargetFeature <"fetch"#Value,
				108	"TexVTXClauseSize",
				109	Value,
				110	"Limit the maximum number of fetches in a clause to "#Value>;
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	111
Tom Stellard	3498e4f	2013-06-07 20:28:55 +0000	[diff] [blame]	112	def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
				113	def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
				114
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	115	class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
				116	"wavefrontsize"#Value,
				117	"WavefrontSize",
				118	!cast<string>(Value),
				119	"The number of threads per wavefront">;
				120
				121	def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
				122	def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
				123	def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
				124
Tom Stellard	880a80a	2014-06-17 16:53:14 +0000	[diff] [blame]	125	class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
				126	"localmemorysize"#Value,
				127	"LocalMemorySize",
				128	!cast<string>(Value),
				129	"The size of local memory in bytes">;
				130
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	131	class SubtargetFeatureGeneration <string Value,
				132	list<SubtargetFeature> Implies> :
				133	SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
				134	Value#" GPU generation", Implies>;
				135
Tom Stellard	880a80a	2014-06-17 16:53:14 +0000	[diff] [blame]	136	def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
				137	def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
				138	def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
				139
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	140	def FeatureR600 : SubtargetFeatureGeneration<"R600",
Tom Stellard	880a80a	2014-06-17 16:53:14 +0000	[diff] [blame]	141	[FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	142
				143	def FeatureR700 : SubtargetFeatureGeneration<"R700",
Tom Stellard	880a80a	2014-06-17 16:53:14 +0000	[diff] [blame]	144	[FeatureFetchLimit16, FeatureLocalMemorySize0]>;
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	145
				146	def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
Tom Stellard	880a80a	2014-06-17 16:53:14 +0000	[diff] [blame]	147	[FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	148
				149	def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
Tom Stellard	880a80a	2014-06-17 16:53:14 +0000	[diff] [blame]	150	[FeatureFetchLimit16, FeatureWavefrontSize64,
				151	FeatureLocalMemorySize32768]
				152	>;
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	153
				154	def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
Tom Stellard	42639a5	2014-07-21 15:44:58 +0000	[diff] [blame]	155	[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
				156	FeatureWavefrontSize64]>;
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	157
Tom Stellard	6e1ee47	2013-10-29 16:37:28 +0000	[diff] [blame]	158	def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
Tom Stellard	42639a5	2014-07-21 15:44:58 +0000	[diff] [blame]	159	[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
Matt Arsenault	3f98140	2014-09-15 15:41:53 +0000	[diff] [blame]	160	FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	161
				162	def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
				163	[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
				164	FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
				165
Tom Stellard	3498e4f	2013-06-07 20:28:55 +0000	[diff] [blame]	166	//===----------------------------------------------------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	167
				168	def AMDGPUInstrInfo : InstrInfo {
				169	let guessInstructionProperties = 1;
Matt Arsenault	1ecac06	2015-02-18 02:15:32 +0000	[diff] [blame^]	170	let noNamedPositionallyEncodedOperands = 1;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	171	}
				172
Tom Stellard	9d7ddd5	2014-11-14 14:08:00 +0000	[diff] [blame]	173	def AMDGPUAsmParser : AsmParser {
				174	// Some of the R600 registers have the same name, so this crashes.
				175	// For example T0_XYZW and T0_XY both have the asm name T0.
				176	let ShouldEmitMatchRegisterName = 0;
				177	}
				178
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	179	def AMDGPU : Target {
				180	// Pull in Instruction Info:
				181	let InstructionSet = AMDGPUInstrInfo;
Tom Stellard	9d7ddd5	2014-11-14 14:08:00 +0000	[diff] [blame]	182	let AssemblyParsers = [AMDGPUAsmParser];
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	183	}
				184
Tom Stellard	bc5b537	2014-06-13 16:38:59 +0000	[diff] [blame]	185	// Dummy Instruction itineraries for pseudo instructions
				186	def ALU_NULL : FuncUnit;
				187	def NullALU : InstrItinClass;
				188
Tom Stellard	0e70de5	2014-05-16 20:56:45 +0000	[diff] [blame]	189	//===----------------------------------------------------------------------===//
				190	// Predicate helper class
				191	//===----------------------------------------------------------------------===//
				192
				193	class PredicateControl {
				194	Predicate SubtargetPredicate;
				195	list<Predicate> OtherPredicates = [];
				196	list<Predicate> Predicates = !listconcat([SubtargetPredicate],
				197	OtherPredicates);
				198	}
				199
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	200	// Include AMDGPU TD files
				201	include "R600Schedule.td"
				202	include "SISchedule.td"
				203	include "Processors.td"
				204	include "AMDGPUInstrInfo.td"
				205	include "AMDGPUIntrinsics.td"
				206	include "AMDGPURegisterInfo.td"
				207	include "AMDGPUInstructions.td"
Christian Konig	2c8f6d5	2013-03-07 09:03:52 +0000	[diff] [blame]	208	include "AMDGPUCallingConv.td"