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Quentin Colombet2ad1f852016-02-11 17:44:59 +00001//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file implements the MachineIRBuidler class.
11//===----------------------------------------------------------------------===//
12#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
13
14#include "llvm/CodeGen/MachineFunction.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
Tim Northover0f140c72016-09-09 11:46:34 +000017#include "llvm/CodeGen/MachineRegisterInfo.h"
Tim Northover09aac4a2017-01-26 23:39:14 +000018#include "llvm/IR/DebugInfo.h"
Quentin Colombet2ad1f852016-02-11 17:44:59 +000019#include "llvm/Target/TargetInstrInfo.h"
Quentin Colombet8fd67182016-02-11 21:16:56 +000020#include "llvm/Target/TargetOpcodes.h"
Quentin Colombet2ad1f852016-02-11 17:44:59 +000021#include "llvm/Target/TargetSubtargetInfo.h"
22
23using namespace llvm;
24
Quentin Colombet000b5802016-03-11 17:27:51 +000025void MachineIRBuilder::setMF(MachineFunction &MF) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000026 this->MF = &MF;
27 this->MBB = nullptr;
Tim Northover0f140c72016-09-09 11:46:34 +000028 this->MRI = &MF.getRegInfo();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000029 this->TII = MF.getSubtarget().getInstrInfo();
30 this->DL = DebugLoc();
Tim Northover05cc4852016-12-07 21:05:38 +000031 this->II = MachineBasicBlock::iterator();
Tim Northover438c77c2016-08-25 17:37:32 +000032 this->InsertedInstr = nullptr;
Quentin Colombet2ad1f852016-02-11 17:44:59 +000033}
34
Tim Northover05cc4852016-12-07 21:05:38 +000035void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000036 this->MBB = &MBB;
Tim Northover05cc4852016-12-07 21:05:38 +000037 this->II = MBB.end();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000038 assert(&getMF() == MBB.getParent() &&
39 "Basic block is in a different function");
40}
41
Tim Northover05cc4852016-12-07 21:05:38 +000042void MachineIRBuilder::setInstr(MachineInstr &MI) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000043 assert(MI.getParent() && "Instruction is not part of a basic block");
Quentin Colombet91ebd712016-03-11 17:27:47 +000044 setMBB(*MI.getParent());
Tim Northover05cc4852016-12-07 21:05:38 +000045 this->II = MI.getIterator();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000046}
47
Tim Northover05cc4852016-12-07 21:05:38 +000048void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator II) {
50 assert(MBB.getParent() == &getMF() &&
51 "Basic block is in a different function");
52 this->MBB = &MBB;
53 this->II = II;
Quentin Colombet2ad1f852016-02-11 17:44:59 +000054}
55
Tim Northover438c77c2016-08-25 17:37:32 +000056void MachineIRBuilder::recordInsertions(
57 std::function<void(MachineInstr *)> Inserted) {
Benjamin Kramer061f4a52017-01-13 14:39:03 +000058 InsertedInstr = std::move(Inserted);
Tim Northover438c77c2016-08-25 17:37:32 +000059}
60
61void MachineIRBuilder::stopRecordingInsertions() {
62 InsertedInstr = nullptr;
63}
64
Quentin Colombetf9b49342016-03-11 17:27:58 +000065//------------------------------------------------------------------------------
66// Build instruction variants.
67//------------------------------------------------------------------------------
Tim Northovercc5f7622016-07-26 16:45:26 +000068
Tim Northover0f140c72016-09-09 11:46:34 +000069MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
Tim Northovera5e38fa2016-09-22 13:49:25 +000070 return insertInstr(buildInstrNoInsert(Opcode));
71}
72
73MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
Tim Northovera51575f2016-07-29 17:43:52 +000074 MachineInstrBuilder MIB = BuildMI(getMF(), DL, getTII().get(Opcode));
Tim Northovera5e38fa2016-09-22 13:49:25 +000075 return MIB;
76}
77
78
79MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
Tim Northovera51575f2016-07-29 17:43:52 +000080 getMBB().insert(getInsertPt(), MIB);
Tim Northover438c77c2016-08-25 17:37:32 +000081 if (InsertedInstr)
82 InsertedInstr(MIB);
Tim Northovera51575f2016-07-29 17:43:52 +000083 return MIB;
Quentin Colombet74d7d2f2016-02-11 18:53:28 +000084}
85
Tim Northover09aac4a2017-01-26 23:39:14 +000086MachineInstrBuilder MachineIRBuilder::buildDirectDbgValue(
87 unsigned Reg, const MDNode *Variable, const MDNode *Expr) {
88 assert(isa<DILocalVariable>(Variable) && "not a variable");
89 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
90 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
91 "Expected inlined-at fields to agree");
92 return buildInstr(TargetOpcode::DBG_VALUE)
93 .addReg(Reg, RegState::Debug)
94 .addReg(0, RegState::Debug)
95 .addMetadata(Variable)
96 .addMetadata(Expr);
97}
98
99MachineInstrBuilder MachineIRBuilder::buildIndirectDbgValue(
100 unsigned Reg, unsigned Offset, const MDNode *Variable, const MDNode *Expr) {
101 assert(isa<DILocalVariable>(Variable) && "not a variable");
102 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
103 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
104 "Expected inlined-at fields to agree");
105 return buildInstr(TargetOpcode::DBG_VALUE)
106 .addReg(Reg, RegState::Debug)
107 .addImm(Offset)
108 .addMetadata(Variable)
109 .addMetadata(Expr);
110}
111
112MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
113 const MDNode *Variable,
114 const MDNode *Expr) {
115 assert(isa<DILocalVariable>(Variable) && "not a variable");
116 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
117 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
118 "Expected inlined-at fields to agree");
119 return buildInstr(TargetOpcode::DBG_VALUE)
120 .addFrameIndex(FI)
121 .addImm(0)
122 .addMetadata(Variable)
123 .addMetadata(Expr);
124}
125
126MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
127 unsigned Offset,
128 const MDNode *Variable,
129 const MDNode *Expr) {
130 assert(isa<DILocalVariable>(Variable) && "not a variable");
131 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
132 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
133 "Expected inlined-at fields to agree");
134 auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
135 if (auto *CI = dyn_cast<ConstantInt>(&C)) {
136 if (CI->getBitWidth() > 64)
137 MIB.addCImm(CI);
138 else
139 MIB.addImm(CI->getZExtValue());
Ahmed Bougacha4826bae2017-03-07 20:34:20 +0000140 } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
Ahmed Bougachaadce3ee2017-03-07 20:52:57 +0000141 MIB.addFPImm(CFP);
Ahmed Bougacha4826bae2017-03-07 20:34:20 +0000142 } else {
143 // Insert %noreg if we didn't find a usable constant and had to drop it.
144 MIB.addReg(0U);
145 }
Tim Northover09aac4a2017-01-26 23:39:14 +0000146
147 return MIB.addImm(Offset).addMetadata(Variable).addMetadata(Expr);
148}
149
Tim Northover0f140c72016-09-09 11:46:34 +0000150MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000151 assert(MRI->getType(Res).isPointer() && "invalid operand type");
Tim Northover0f140c72016-09-09 11:46:34 +0000152 return buildInstr(TargetOpcode::G_FRAME_INDEX)
Tim Northovera51575f2016-07-29 17:43:52 +0000153 .addDef(Res)
154 .addFrameIndex(Idx);
Tim Northoverbd505462016-07-22 16:59:52 +0000155}
Tim Northover33b07d62016-07-22 20:03:43 +0000156
Tim Northover032548f2016-09-12 12:10:41 +0000157MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res,
158 const GlobalValue *GV) {
159 assert(MRI->getType(Res).isPointer() && "invalid operand type");
160 assert(MRI->getType(Res).getAddressSpace() ==
161 GV->getType()->getAddressSpace() &&
162 "address space mismatch");
163
164 return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
165 .addDef(Res)
166 .addGlobalAddress(GV);
167}
168
Diana Picus05e704f2017-07-05 11:02:31 +0000169MachineInstrBuilder MachineIRBuilder::buildBinaryOp(unsigned Opcode, unsigned Res, unsigned Op0,
Tim Northover0f140c72016-09-09 11:46:34 +0000170 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000171 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
172 "invalid operand type");
173 assert(MRI->getType(Res) == MRI->getType(Op0) &&
174 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
175
Diana Picus05e704f2017-07-05 11:02:31 +0000176 return buildInstr(Opcode)
Tim Northovera51575f2016-07-29 17:43:52 +0000177 .addDef(Res)
178 .addUse(Op0)
179 .addUse(Op1);
Tim Northover33b07d62016-07-22 20:03:43 +0000180}
181
Diana Picus05e704f2017-07-05 11:02:31 +0000182MachineInstrBuilder MachineIRBuilder::buildAdd(unsigned Res, unsigned Op0,
183 unsigned Op1) {
184 return buildBinaryOp(TargetOpcode::G_ADD, Res, Op0, Op1);
185}
186
Tim Northovera7653b32016-09-12 11:20:22 +0000187MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0,
188 unsigned Op1) {
189 assert(MRI->getType(Res).isPointer() &&
190 MRI->getType(Res) == MRI->getType(Op0) && "type mismatch");
191 assert(MRI->getType(Op1).isScalar() && "invalid offset type");
192
193 return buildInstr(TargetOpcode::G_GEP)
194 .addDef(Res)
195 .addUse(Op0)
196 .addUse(Op1);
197}
198
Daniel Sanders4e523662017-06-13 23:42:32 +0000199Optional<MachineInstrBuilder>
200MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0,
201 const LLT &ValueTy, uint64_t Value) {
202 assert(Res == 0 && "Res is a result argument");
203 assert(ValueTy.isScalar() && "invalid offset type");
204
205 if (Value == 0) {
206 Res = Op0;
207 return None;
208 }
209
210 Res = MRI->createGenericVirtualRegister(MRI->getType(Op0));
211 unsigned TmpReg = MRI->createGenericVirtualRegister(ValueTy);
212
213 buildConstant(TmpReg, Value);
214 return buildGEP(Res, Op0, TmpReg);
215}
216
Tim Northoverc2f89562017-02-14 20:56:18 +0000217MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0,
218 uint32_t NumBits) {
219 assert(MRI->getType(Res).isPointer() &&
220 MRI->getType(Res) == MRI->getType(Op0) && "type mismatch");
221
222 return buildInstr(TargetOpcode::G_PTR_MASK)
223 .addDef(Res)
224 .addUse(Op0)
225 .addImm(NumBits);
226}
227
Tim Northover0f140c72016-09-09 11:46:34 +0000228MachineInstrBuilder MachineIRBuilder::buildSub(unsigned Res, unsigned Op0,
229 unsigned Op1) {
Diana Picus05e704f2017-07-05 11:02:31 +0000230 return buildBinaryOp(TargetOpcode::G_SUB, Res, Op0, Op1);
Tim Northovercecee562016-08-26 17:46:13 +0000231}
232
Tim Northover0f140c72016-09-09 11:46:34 +0000233MachineInstrBuilder MachineIRBuilder::buildMul(unsigned Res, unsigned Op0,
234 unsigned Op1) {
Diana Picus05e704f2017-07-05 11:02:31 +0000235 return buildBinaryOp(TargetOpcode::G_MUL, Res, Op0, Op1);
Tim Northovercecee562016-08-26 17:46:13 +0000236}
237
Tim Northoverc3e3f592017-02-03 18:22:45 +0000238MachineInstrBuilder MachineIRBuilder::buildAnd(unsigned Res, unsigned Op0,
239 unsigned Op1) {
Diana Picus05e704f2017-07-05 11:02:31 +0000240 return buildBinaryOp(TargetOpcode::G_AND, Res, Op0, Op1);
Tim Northoverc3e3f592017-02-03 18:22:45 +0000241}
242
Diana Picus05e704f2017-07-05 11:02:31 +0000243
Tim Northovera51575f2016-07-29 17:43:52 +0000244MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
Tim Northover0f140c72016-09-09 11:46:34 +0000245 return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
Tim Northovercc5f7622016-07-26 16:45:26 +0000246}
247
Kristof Beyls65a12c02017-01-30 09:13:18 +0000248MachineInstrBuilder MachineIRBuilder::buildBrIndirect(unsigned Tgt) {
Tim Northoverc9902362017-06-27 22:45:35 +0000249 assert(MRI->getType(Tgt).isPointer() && "invalid branch destination");
Kristof Beyls65a12c02017-01-30 09:13:18 +0000250 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
251}
252
Tim Northovera51575f2016-07-29 17:43:52 +0000253MachineInstrBuilder MachineIRBuilder::buildCopy(unsigned Res, unsigned Op) {
Tim Northover849fcca2017-06-27 21:41:40 +0000254 assert(MRI->getType(Res) == LLT() || MRI->getType(Op) == LLT() ||
255 MRI->getType(Res) == MRI->getType(Op));
Tim Northovera51575f2016-07-29 17:43:52 +0000256 return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op);
Tim Northover756eca32016-07-26 16:45:30 +0000257}
258
Tim Northover9267ac52016-12-05 21:47:07 +0000259MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res,
260 const ConstantInt &Val) {
261 LLT Ty = MRI->getType(Res);
Tim Northover1f8b1db2016-09-09 11:46:58 +0000262
Sam McCall03435f52016-12-06 10:14:36 +0000263 assert((Ty.isScalar() || Ty.isPointer()) && "invalid operand type");
Tim Northover9267ac52016-12-05 21:47:07 +0000264
265 const ConstantInt *NewVal = &Val;
266 if (Ty.getSizeInBits() != Val.getBitWidth())
267 NewVal = ConstantInt::get(MF->getFunction()->getContext(),
268 Val.getValue().sextOrTrunc(Ty.getSizeInBits()));
269
270 return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addCImm(NewVal);
271}
272
273MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res,
274 int64_t Val) {
275 auto IntN = IntegerType::get(MF->getFunction()->getContext(),
276 MRI->getType(Res).getSizeInBits());
277 ConstantInt *CI = ConstantInt::get(IntN, Val, true);
278 return buildConstant(Res, *CI);
Tim Northover9656f142016-08-04 20:54:13 +0000279}
280
Tim Northover0f140c72016-09-09 11:46:34 +0000281MachineInstrBuilder MachineIRBuilder::buildFConstant(unsigned Res,
282 const ConstantFP &Val) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000283 assert(MRI->getType(Res).isScalar() && "invalid operand type");
284
Tim Northover0f140c72016-09-09 11:46:34 +0000285 return buildInstr(TargetOpcode::G_FCONSTANT).addDef(Res).addFPImm(&Val);
Tim Northoverb16734f2016-08-19 20:09:15 +0000286}
287
Tim Northover0f140c72016-09-09 11:46:34 +0000288MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst,
Tim Northover69c2ba52016-07-29 17:58:00 +0000289 MachineBasicBlock &Dest) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000290 assert(MRI->getType(Tst).isScalar() && "invalid operand type");
291
Tim Northover0f140c72016-09-09 11:46:34 +0000292 return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
Tim Northover69c2ba52016-07-29 17:58:00 +0000293}
294
Tim Northover0f140c72016-09-09 11:46:34 +0000295MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr,
296 MachineMemOperand &MMO) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000297 assert(MRI->getType(Res).isValid() && "invalid operand type");
298 assert(MRI->getType(Addr).isPointer() && "invalid operand type");
299
Tim Northover0f140c72016-09-09 11:46:34 +0000300 return buildInstr(TargetOpcode::G_LOAD)
Tim Northovera51575f2016-07-29 17:43:52 +0000301 .addDef(Res)
302 .addUse(Addr)
303 .addMemOperand(&MMO);
Tim Northoverad2b7172016-07-26 20:23:26 +0000304}
305
Tim Northover0f140c72016-09-09 11:46:34 +0000306MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
307 MachineMemOperand &MMO) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000308 assert(MRI->getType(Val).isValid() && "invalid operand type");
309 assert(MRI->getType(Addr).isPointer() && "invalid operand type");
310
Tim Northover0f140c72016-09-09 11:46:34 +0000311 return buildInstr(TargetOpcode::G_STORE)
Tim Northovera51575f2016-07-29 17:43:52 +0000312 .addUse(Val)
313 .addUse(Addr)
314 .addMemOperand(&MMO);
Tim Northoverad2b7172016-07-26 20:23:26 +0000315}
316
Tim Northover0f140c72016-09-09 11:46:34 +0000317MachineInstrBuilder MachineIRBuilder::buildUAdde(unsigned Res,
318 unsigned CarryOut,
319 unsigned Op0, unsigned Op1,
320 unsigned CarryIn) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000321 assert(MRI->getType(Res).isScalar() && "invalid operand type");
322 assert(MRI->getType(Res) == MRI->getType(Op0) &&
323 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
324 assert(MRI->getType(CarryOut).isScalar() && "invalid operand type");
325 assert(MRI->getType(CarryOut) == MRI->getType(CarryIn) && "type mismatch");
326
Tim Northover0f140c72016-09-09 11:46:34 +0000327 return buildInstr(TargetOpcode::G_UADDE)
Tim Northover9656f142016-08-04 20:54:13 +0000328 .addDef(Res)
329 .addDef(CarryOut)
330 .addUse(Op0)
331 .addUse(Op1)
332 .addUse(CarryIn);
333}
334
Tim Northover0f140c72016-09-09 11:46:34 +0000335MachineInstrBuilder MachineIRBuilder::buildAnyExt(unsigned Res, unsigned Op) {
336 validateTruncExt(Res, Op, true);
337 return buildInstr(TargetOpcode::G_ANYEXT).addDef(Res).addUse(Op);
Tim Northover32335812016-08-04 18:35:11 +0000338}
339
Tim Northover0f140c72016-09-09 11:46:34 +0000340MachineInstrBuilder MachineIRBuilder::buildSExt(unsigned Res, unsigned Op) {
341 validateTruncExt(Res, Op, true);
342 return buildInstr(TargetOpcode::G_SEXT).addDef(Res).addUse(Op);
Tim Northover6cd4b232016-08-23 21:01:26 +0000343}
344
Tim Northover0f140c72016-09-09 11:46:34 +0000345MachineInstrBuilder MachineIRBuilder::buildZExt(unsigned Res, unsigned Op) {
346 validateTruncExt(Res, Op, true);
347 return buildInstr(TargetOpcode::G_ZEXT).addDef(Res).addUse(Op);
Tim Northover6cd4b232016-08-23 21:01:26 +0000348}
349
Tim Northovera7653b32016-09-12 11:20:22 +0000350MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(unsigned Res,
351 unsigned Op) {
Tim Northoverc9902362017-06-27 22:45:35 +0000352 assert(MRI->getType(Res).isScalar() || MRI->getType(Res).isVector());
353 assert(MRI->getType(Res).isScalar() == MRI->getType(Op).isScalar());
354
Tim Northovera7653b32016-09-12 11:20:22 +0000355 unsigned Opcode = TargetOpcode::COPY;
356 if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits())
357 Opcode = TargetOpcode::G_SEXT;
358 else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits())
359 Opcode = TargetOpcode::G_TRUNC;
Tim Northoverc9902362017-06-27 22:45:35 +0000360 else
361 assert(MRI->getType(Res) == MRI->getType(Op));
Tim Northovera7653b32016-09-12 11:20:22 +0000362
363 return buildInstr(Opcode).addDef(Res).addUse(Op);
364}
365
Tim Northoverc3e3f592017-02-03 18:22:45 +0000366MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(unsigned Res,
367 unsigned Op) {
Tim Northoverc9902362017-06-27 22:45:35 +0000368 assert(MRI->getType(Res).isScalar() || MRI->getType(Res).isVector());
369 assert(MRI->getType(Res).isScalar() == MRI->getType(Op).isScalar());
370
Tim Northoverc3e3f592017-02-03 18:22:45 +0000371 unsigned Opcode = TargetOpcode::COPY;
372 if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits())
373 Opcode = TargetOpcode::G_ZEXT;
374 else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits())
375 Opcode = TargetOpcode::G_TRUNC;
Tim Northoverc9902362017-06-27 22:45:35 +0000376 else
377 assert(MRI->getType(Res) == MRI->getType(Op));
Tim Northoverc3e3f592017-02-03 18:22:45 +0000378
379 return buildInstr(Opcode).addDef(Res).addUse(Op);
380}
381
Tim Northover95b6d5f2017-03-06 19:04:17 +0000382MachineInstrBuilder MachineIRBuilder::buildCast(unsigned Dst, unsigned Src) {
383 LLT SrcTy = MRI->getType(Src);
384 LLT DstTy = MRI->getType(Dst);
385 if (SrcTy == DstTy)
386 return buildCopy(Dst, Src);
387
388 unsigned Opcode;
389 if (SrcTy.isPointer() && DstTy.isScalar())
390 Opcode = TargetOpcode::G_PTRTOINT;
391 else if (DstTy.isPointer() && SrcTy.isScalar())
392 Opcode = TargetOpcode::G_INTTOPTR;
393 else {
394 assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
395 Opcode = TargetOpcode::G_BITCAST;
396 }
397
398 return buildInstr(Opcode).addDef(Dst).addUse(Src);
399}
400
Tim Northoverc2c545b2017-03-06 23:50:28 +0000401MachineInstrBuilder MachineIRBuilder::buildExtract(unsigned Res, unsigned Src,
402 uint64_t Index) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000403#ifndef NDEBUG
Tim Northover1f8b1db2016-09-09 11:46:58 +0000404 assert(MRI->getType(Src).isValid() && "invalid operand type");
Tim Northoverc2c545b2017-03-06 23:50:28 +0000405 assert(MRI->getType(Res).isValid() && "invalid operand type");
406 assert(Index + MRI->getType(Res).getSizeInBits() <=
407 MRI->getType(Src).getSizeInBits() &&
408 "extracting off end of register");
Tim Northover1f8b1db2016-09-09 11:46:58 +0000409#endif
410
Tim Northoverc2c545b2017-03-06 23:50:28 +0000411 if (MRI->getType(Res).getSizeInBits() == MRI->getType(Src).getSizeInBits()) {
412 assert(Index == 0 && "insertion past the end of a register");
413 return buildCast(Res, Src);
414 }
Tim Northover33b07d62016-07-22 20:03:43 +0000415
Tim Northoverc2c545b2017-03-06 23:50:28 +0000416 return buildInstr(TargetOpcode::G_EXTRACT)
417 .addDef(Res)
418 .addUse(Src)
419 .addImm(Index);
Tim Northover33b07d62016-07-22 20:03:43 +0000420}
421
Tim Northoverb57bf2a2017-06-23 16:15:37 +0000422void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
423 ArrayRef<uint64_t> Indices) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000424#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000425 assert(Ops.size() == Indices.size() && "incompatible args");
Tim Northover26b76f22016-08-19 18:32:14 +0000426 assert(!Ops.empty() && "invalid trivial sequence");
Tim Northover991b12b2016-08-30 20:51:25 +0000427 assert(std::is_sorted(Indices.begin(), Indices.end()) &&
428 "sequence offsets must be in ascending order");
Tim Northover91c81732016-08-19 17:17:06 +0000429
Tim Northover1f8b1db2016-09-09 11:46:58 +0000430 assert(MRI->getType(Res).isValid() && "invalid operand type");
431 for (auto Op : Ops)
432 assert(MRI->getType(Op).isValid() && "invalid operand type");
433#endif
434
Tim Northoverb57bf2a2017-06-23 16:15:37 +0000435 LLT ResTy = MRI->getType(Res);
436 LLT OpTy = MRI->getType(Ops[0]);
437 unsigned OpSize = OpTy.getSizeInBits();
438 bool MaybeMerge = true;
Tim Northover91c81732016-08-19 17:17:06 +0000439 for (unsigned i = 0; i < Ops.size(); ++i) {
Tim Northoverb57bf2a2017-06-23 16:15:37 +0000440 if (MRI->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
441 MaybeMerge = false;
442 break;
443 }
Tim Northover91c81732016-08-19 17:17:06 +0000444 }
Tim Northoverb57bf2a2017-06-23 16:15:37 +0000445
446 if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
447 buildMerge(Res, Ops);
448 return;
449 }
450
451 unsigned ResIn = MRI->createGenericVirtualRegister(ResTy);
452 buildUndef(ResIn);
453
454 for (unsigned i = 0; i < Ops.size(); ++i) {
455 unsigned ResOut =
456 i + 1 == Ops.size() ? Res : MRI->createGenericVirtualRegister(ResTy);
457 buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
458 ResIn = ResOut;
459 }
Tim Northover33b07d62016-07-22 20:03:43 +0000460}
Tim Northover5fb414d2016-07-29 22:32:36 +0000461
Tim Northover81dafc12017-03-06 18:36:40 +0000462MachineInstrBuilder MachineIRBuilder::buildUndef(unsigned Res) {
Tim Northoverff5e7e12017-06-30 20:27:36 +0000463 return buildInstr(TargetOpcode::G_IMPLICIT_DEF).addDef(Res);
Tim Northover81dafc12017-03-06 18:36:40 +0000464}
465
Tim Northoverbf017292017-03-03 22:46:09 +0000466MachineInstrBuilder MachineIRBuilder::buildMerge(unsigned Res,
467 ArrayRef<unsigned> Ops) {
468
469#ifndef NDEBUG
470 assert(!Ops.empty() && "invalid trivial sequence");
471 LLT Ty = MRI->getType(Ops[0]);
472 for (auto Reg : Ops)
473 assert(MRI->getType(Reg) == Ty && "type mismatch in input list");
474 assert(Ops.size() * MRI->getType(Ops[0]).getSizeInBits() ==
475 MRI->getType(Res).getSizeInBits() &&
476 "input operands do not cover output register");
477#endif
478
Tim Northoverc2d5e6d2017-06-26 20:34:13 +0000479 if (Ops.size() == 1)
Tim Northover849fcca2017-06-27 21:41:40 +0000480 return buildCast(Res, Ops[0]);
Tim Northoverc2d5e6d2017-06-26 20:34:13 +0000481
Tim Northoverbf017292017-03-03 22:46:09 +0000482 MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_MERGE_VALUES);
483 MIB.addDef(Res);
484 for (unsigned i = 0; i < Ops.size(); ++i)
485 MIB.addUse(Ops[i]);
486 return MIB;
487}
488
489MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res,
490 unsigned Op) {
491
492#ifndef NDEBUG
493 assert(!Res.empty() && "invalid trivial sequence");
494 LLT Ty = MRI->getType(Res[0]);
495 for (auto Reg : Res)
496 assert(MRI->getType(Reg) == Ty && "type mismatch in input list");
497 assert(Res.size() * MRI->getType(Res[0]).getSizeInBits() ==
498 MRI->getType(Op).getSizeInBits() &&
499 "input operands do not cover output register");
500#endif
501
502 MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_UNMERGE_VALUES);
503 for (unsigned i = 0; i < Res.size(); ++i)
504 MIB.addDef(Res[i]);
505 MIB.addUse(Op);
506 return MIB;
507}
508
Tim Northover3e6a7af2017-03-03 23:05:47 +0000509MachineInstrBuilder MachineIRBuilder::buildInsert(unsigned Res, unsigned Src,
510 unsigned Op, unsigned Index) {
Tim Northoverc9902362017-06-27 22:45:35 +0000511 assert(Index + MRI->getType(Op).getSizeInBits() <=
512 MRI->getType(Res).getSizeInBits() &&
513 "insertion past the end of a register");
514
Tim Northover95b6d5f2017-03-06 19:04:17 +0000515 if (MRI->getType(Res).getSizeInBits() == MRI->getType(Op).getSizeInBits()) {
Tim Northover95b6d5f2017-03-06 19:04:17 +0000516 return buildCast(Res, Op);
517 }
518
Tim Northover3e6a7af2017-03-03 23:05:47 +0000519 return buildInstr(TargetOpcode::G_INSERT)
520 .addDef(Res)
521 .addUse(Src)
522 .addUse(Op)
523 .addImm(Index);
524}
525
Tim Northover0f140c72016-09-09 11:46:34 +0000526MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
Tim Northover5fb414d2016-07-29 22:32:36 +0000527 unsigned Res,
528 bool HasSideEffects) {
529 auto MIB =
530 buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
Tim Northover0f140c72016-09-09 11:46:34 +0000531 : TargetOpcode::G_INTRINSIC);
Tim Northover5fb414d2016-07-29 22:32:36 +0000532 if (Res)
533 MIB.addDef(Res);
534 MIB.addIntrinsicID(ID);
535 return MIB;
536}
Tim Northover32335812016-08-04 18:35:11 +0000537
Tim Northover0f140c72016-09-09 11:46:34 +0000538MachineInstrBuilder MachineIRBuilder::buildTrunc(unsigned Res, unsigned Op) {
539 validateTruncExt(Res, Op, false);
540 return buildInstr(TargetOpcode::G_TRUNC).addDef(Res).addUse(Op);
Tim Northover32335812016-08-04 18:35:11 +0000541}
Tim Northoverde3aea0412016-08-17 20:25:25 +0000542
Tim Northover0f140c72016-09-09 11:46:34 +0000543MachineInstrBuilder MachineIRBuilder::buildFPTrunc(unsigned Res, unsigned Op) {
544 validateTruncExt(Res, Op, false);
545 return buildInstr(TargetOpcode::G_FPTRUNC).addDef(Res).addUse(Op);
Tim Northovera11be042016-08-19 22:40:08 +0000546}
547
Tim Northover0f140c72016-09-09 11:46:34 +0000548MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
Tim Northoverde3aea0412016-08-17 20:25:25 +0000549 unsigned Res, unsigned Op0,
550 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000551#ifndef NDEBUG
Tim Northover1f8b1db2016-09-09 11:46:58 +0000552 assert(MRI->getType(Op0) == MRI->getType(Op0) && "type mismatch");
553 assert(CmpInst::isIntPredicate(Pred) && "invalid predicate");
Tim Northover4cf0a482016-09-15 10:40:38 +0000554 if (MRI->getType(Op0).isScalar() || MRI->getType(Op0).isPointer())
Tim Northover1f8b1db2016-09-09 11:46:58 +0000555 assert(MRI->getType(Res).isScalar() && "type mismatch");
556 else
557 assert(MRI->getType(Res).isVector() &&
558 MRI->getType(Res).getNumElements() ==
559 MRI->getType(Op0).getNumElements() &&
560 "type mismatch");
561#endif
562
Tim Northover0f140c72016-09-09 11:46:34 +0000563 return buildInstr(TargetOpcode::G_ICMP)
Tim Northoverde3aea0412016-08-17 20:25:25 +0000564 .addDef(Res)
565 .addPredicate(Pred)
566 .addUse(Op0)
567 .addUse(Op1);
568}
Tim Northover5a28c362016-08-19 20:09:07 +0000569
Tim Northover0f140c72016-09-09 11:46:34 +0000570MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
Tim Northoverd5c23bc2016-08-19 20:48:16 +0000571 unsigned Res, unsigned Op0,
572 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000573#ifndef NDEBUG
574 assert((MRI->getType(Op0).isScalar() || MRI->getType(Op0).isVector()) &&
575 "invalid operand type");
576 assert(MRI->getType(Op0) == MRI->getType(Op1) && "type mismatch");
577 assert(CmpInst::isFPPredicate(Pred) && "invalid predicate");
578 if (MRI->getType(Op0).isScalar())
579 assert(MRI->getType(Res).isScalar() && "type mismatch");
580 else
581 assert(MRI->getType(Res).isVector() &&
582 MRI->getType(Res).getNumElements() ==
583 MRI->getType(Op0).getNumElements() &&
584 "type mismatch");
585#endif
586
Tim Northover0f140c72016-09-09 11:46:34 +0000587 return buildInstr(TargetOpcode::G_FCMP)
Tim Northoverd5c23bc2016-08-19 20:48:16 +0000588 .addDef(Res)
589 .addPredicate(Pred)
590 .addUse(Op0)
591 .addUse(Op1);
592}
593
Tim Northover0f140c72016-09-09 11:46:34 +0000594MachineInstrBuilder MachineIRBuilder::buildSelect(unsigned Res, unsigned Tst,
Tim Northover5a28c362016-08-19 20:09:07 +0000595 unsigned Op0, unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000596#ifndef NDEBUG
Tim Northoverf50f2f32016-12-06 18:38:34 +0000597 LLT ResTy = MRI->getType(Res);
598 assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
Tim Northover1f8b1db2016-09-09 11:46:58 +0000599 "invalid operand type");
Tim Northoverf50f2f32016-12-06 18:38:34 +0000600 assert(ResTy == MRI->getType(Op0) && ResTy == MRI->getType(Op1) &&
601 "type mismatch");
602 if (ResTy.isScalar() || ResTy.isPointer())
Tim Northover1f8b1db2016-09-09 11:46:58 +0000603 assert(MRI->getType(Tst).isScalar() && "type mismatch");
604 else
Ahmed Bougacha38455ea2017-03-07 20:53:03 +0000605 assert((MRI->getType(Tst).isScalar() ||
606 (MRI->getType(Tst).isVector() &&
607 MRI->getType(Tst).getNumElements() ==
608 MRI->getType(Op0).getNumElements())) &&
Tim Northover1f8b1db2016-09-09 11:46:58 +0000609 "type mismatch");
610#endif
611
Tim Northover0f140c72016-09-09 11:46:34 +0000612 return buildInstr(TargetOpcode::G_SELECT)
Tim Northover5a28c362016-08-19 20:09:07 +0000613 .addDef(Res)
614 .addUse(Tst)
615 .addUse(Op0)
616 .addUse(Op1);
617}
Tim Northoverbdf67c92016-08-23 21:01:33 +0000618
Volkan Keles04cb08c2017-03-10 19:08:28 +0000619MachineInstrBuilder MachineIRBuilder::buildInsertVectorElement(unsigned Res,
620 unsigned Val,
621 unsigned Elt,
622 unsigned Idx) {
623#ifndef NDEBUG
624 LLT ResTy = MRI->getType(Res);
625 LLT ValTy = MRI->getType(Val);
626 LLT EltTy = MRI->getType(Elt);
627 LLT IdxTy = MRI->getType(Idx);
628 assert(ResTy.isVector() && ValTy.isVector() && "invalid operand type");
Kristof Beyls0f36e682017-04-19 07:23:57 +0000629 assert(IdxTy.isScalar() && "invalid operand type");
Volkan Keles04cb08c2017-03-10 19:08:28 +0000630 assert(ResTy.getNumElements() == ValTy.getNumElements() && "type mismatch");
631 assert(ResTy.getElementType() == EltTy && "type mismatch");
632#endif
633
634 return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT)
635 .addDef(Res)
636 .addUse(Val)
637 .addUse(Elt)
638 .addUse(Idx);
639}
640
641MachineInstrBuilder MachineIRBuilder::buildExtractVectorElement(unsigned Res,
642 unsigned Val,
643 unsigned Idx) {
644#ifndef NDEBUG
645 LLT ResTy = MRI->getType(Res);
646 LLT ValTy = MRI->getType(Val);
647 LLT IdxTy = MRI->getType(Idx);
648 assert(ValTy.isVector() && "invalid operand type");
Kristof Beyls0f36e682017-04-19 07:23:57 +0000649 assert((ResTy.isScalar() || ResTy.isPointer()) && "invalid operand type");
650 assert(IdxTy.isScalar() && "invalid operand type");
Volkan Keles04cb08c2017-03-10 19:08:28 +0000651 assert(ValTy.getElementType() == ResTy && "type mismatch");
652#endif
653
654 return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT)
655 .addDef(Res)
656 .addUse(Val)
657 .addUse(Idx);
658}
659
Tim Northover0f140c72016-09-09 11:46:34 +0000660void MachineIRBuilder::validateTruncExt(unsigned Dst, unsigned Src,
661 bool IsExtend) {
Richard Smith418237b2016-08-23 22:14:15 +0000662#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000663 LLT SrcTy = MRI->getType(Src);
664 LLT DstTy = MRI->getType(Dst);
Tim Northoverbdf67c92016-08-23 21:01:33 +0000665
666 if (DstTy.isVector()) {
667 assert(SrcTy.isVector() && "mismatched cast between vecot and non-vector");
668 assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
669 "different number of elements in a trunc/ext");
670 } else
671 assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
672
673 if (IsExtend)
674 assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
675 "invalid narrowing extend");
676 else
677 assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
678 "invalid widening trunc");
Richard Smith418237b2016-08-23 22:14:15 +0000679#endif
Tim Northoverbdf67c92016-08-23 21:01:33 +0000680}