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gerrit-public.fairphone.software / toolchain / llvm-project / 3faabbbe85d51f5efb1f3f540fe7b81916144a2e / . / llvm / lib / CodeGen / TargetLoweringBase.cpp
blob: e9d38c10c86014b63cf3a8a76f19ec785ca80910 [file] [log] [blame]
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1//===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLoweringBase class.
11//
12//===----------------------------------------------------------------------===//
13
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]14#include "llvm/ADT/BitVector.h"
15#include "llvm/ADT/STLExtras.h"
Sanjay Patel0051efc2016-10-20 16:55:45 +0000[diff] [blame]16#include "llvm/ADT/StringExtras.h"
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]17#include "llvm/ADT/Triple.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]18#include "llvm/CodeGen/Analysis.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]21#include "llvm/CodeGen/MachineInstrBuilder.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]22#include "llvm/CodeGen/MachineJumpTableInfo.h"
Matthias Braun744c2152017-04-28 20:25:05 +0000[diff] [blame]23#include "llvm/CodeGen/MachineRegisterInfo.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]24#include "llvm/CodeGen/StackMaps.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]25#include "llvm/IR/DataLayout.h"
26#include "llvm/IR/DerivedTypes.h"
27#include "llvm/IR/GlobalVariable.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]28#include "llvm/IR/Mangler.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]29#include "llvm/MC/MCAsmInfo.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]30#include "llvm/MC/MCContext.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]31#include "llvm/MC/MCExpr.h"
Sanjay Pateld66607b2016-04-26 17:11:17 +0000[diff] [blame]32#include "llvm/Support/BranchProbability.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]33#include "llvm/Support/CommandLine.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Support/MathExtras.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +0000[diff] [blame]36#include "llvm/Target/TargetLowering.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]37#include "llvm/Target/TargetLoweringObjectFile.h"
38#include "llvm/Target/TargetMachine.h"
39#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]40#include "llvm/Target/TargetSubtargetInfo.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]41#include <cctype>
42using namespace llvm;
43
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]44static cl::opt<bool> JumpIsExpensiveOverride(
45 "jump-is-expensive", cl::init(false),
46 cl::desc("Do not create extra branches to split comparison logic."),
47 cl::Hidden);
48
Evandro Menezeseb97e352016-10-25 19:53:51 +0000[diff] [blame]49static cl::opt<unsigned> MinimumJumpTableEntries
50 ("min-jump-table-entries", cl::init(4), cl::Hidden,
51 cl::desc("Set minimum number of entries to use a jump table."));
52
Evandro Menezese45de8a2016-09-26 15:32:33 +0000[diff] [blame]53static cl::opt<unsigned> MaximumJumpTableSize
Evandro Menezeseb97e352016-10-25 19:53:51 +0000[diff] [blame]54 ("max-jump-table-size", cl::init(0), cl::Hidden,
55 cl::desc("Set maximum size of jump tables; zero for no limit."));
Evandro Menezese45de8a2016-09-26 15:32:33 +0000[diff] [blame]56
Jun Bum Lim919f9e82017-04-28 16:04:03 +0000[diff] [blame]57/// Minimum jump table density for normal functions.
58static cl::opt<unsigned>
59 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
60 cl::desc("Minimum density for building a jump table in "
61 "a normal function"));
62
63/// Minimum jump table density for -Os or -Oz functions.
64static cl::opt<unsigned> OptsizeJumpTableDensity(
65 "optsize-jump-table-density", cl::init(40), cl::Hidden,
66 cl::desc("Minimum density for building a jump table in "
67 "an optsize function"));
68
Sanjay Pateld66607b2016-04-26 17:11:17 +0000[diff] [blame]69// Although this default value is arbitrary, it is not random. It is assumed
70// that a condition that evaluates the same way by a higher percentage than this
71// is best represented as control flow. Therefore, the default value N should be
72// set such that the win from N% correct executions is greater than the loss
73// from (100 - N)% mispredicted executions for the majority of intended targets.
74static cl::opt<int> MinPercentageForPredictableBranch(
75 "min-predictable-branch", cl::init(99),
76 cl::desc("Minimum percentage (0-100) that a condition must be either true "
77 "or false to assume that the condition is predictable"),
78 cl::Hidden);
79
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]80/// InitLibcallNames - Set default libcall names.
81///
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]82static void InitLibcallNames(const char **Names, const Triple &TT) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]83 Names[RTLIB::SHL_I16] = "__ashlhi3";
84 Names[RTLIB::SHL_I32] = "__ashlsi3";
85 Names[RTLIB::SHL_I64] = "__ashldi3";
86 Names[RTLIB::SHL_I128] = "__ashlti3";
87 Names[RTLIB::SRL_I16] = "__lshrhi3";
88 Names[RTLIB::SRL_I32] = "__lshrsi3";
89 Names[RTLIB::SRL_I64] = "__lshrdi3";
90 Names[RTLIB::SRL_I128] = "__lshrti3";
91 Names[RTLIB::SRA_I16] = "__ashrhi3";
92 Names[RTLIB::SRA_I32] = "__ashrsi3";
93 Names[RTLIB::SRA_I64] = "__ashrdi3";
94 Names[RTLIB::SRA_I128] = "__ashrti3";
95 Names[RTLIB::MUL_I8] = "__mulqi3";
96 Names[RTLIB::MUL_I16] = "__mulhi3";
97 Names[RTLIB::MUL_I32] = "__mulsi3";
98 Names[RTLIB::MUL_I64] = "__muldi3";
99 Names[RTLIB::MUL_I128] = "__multi3";
100 Names[RTLIB::MULO_I32] = "__mulosi4";
101 Names[RTLIB::MULO_I64] = "__mulodi4";
102 Names[RTLIB::MULO_I128] = "__muloti4";
103 Names[RTLIB::SDIV_I8] = "__divqi3";
104 Names[RTLIB::SDIV_I16] = "__divhi3";
105 Names[RTLIB::SDIV_I32] = "__divsi3";
106 Names[RTLIB::SDIV_I64] = "__divdi3";
107 Names[RTLIB::SDIV_I128] = "__divti3";
108 Names[RTLIB::UDIV_I8] = "__udivqi3";
109 Names[RTLIB::UDIV_I16] = "__udivhi3";
110 Names[RTLIB::UDIV_I32] = "__udivsi3";
111 Names[RTLIB::UDIV_I64] = "__udivdi3";
112 Names[RTLIB::UDIV_I128] = "__udivti3";
113 Names[RTLIB::SREM_I8] = "__modqi3";
114 Names[RTLIB::SREM_I16] = "__modhi3";
115 Names[RTLIB::SREM_I32] = "__modsi3";
116 Names[RTLIB::SREM_I64] = "__moddi3";
117 Names[RTLIB::SREM_I128] = "__modti3";
118 Names[RTLIB::UREM_I8] = "__umodqi3";
119 Names[RTLIB::UREM_I16] = "__umodhi3";
120 Names[RTLIB::UREM_I32] = "__umodsi3";
121 Names[RTLIB::UREM_I64] = "__umoddi3";
122 Names[RTLIB::UREM_I128] = "__umodti3";
123
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]124 Names[RTLIB::NEG_I32] = "__negsi2";
125 Names[RTLIB::NEG_I64] = "__negdi2";
126 Names[RTLIB::ADD_F32] = "__addsf3";
127 Names[RTLIB::ADD_F64] = "__adddf3";
128 Names[RTLIB::ADD_F80] = "__addxf3";
129 Names[RTLIB::ADD_F128] = "__addtf3";
130 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
131 Names[RTLIB::SUB_F32] = "__subsf3";
132 Names[RTLIB::SUB_F64] = "__subdf3";
133 Names[RTLIB::SUB_F80] = "__subxf3";
134 Names[RTLIB::SUB_F128] = "__subtf3";
135 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
136 Names[RTLIB::MUL_F32] = "__mulsf3";
137 Names[RTLIB::MUL_F64] = "__muldf3";
138 Names[RTLIB::MUL_F80] = "__mulxf3";
139 Names[RTLIB::MUL_F128] = "__multf3";
140 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
141 Names[RTLIB::DIV_F32] = "__divsf3";
142 Names[RTLIB::DIV_F64] = "__divdf3";
143 Names[RTLIB::DIV_F80] = "__divxf3";
144 Names[RTLIB::DIV_F128] = "__divtf3";
145 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
146 Names[RTLIB::REM_F32] = "fmodf";
147 Names[RTLIB::REM_F64] = "fmod";
148 Names[RTLIB::REM_F80] = "fmodl";
149 Names[RTLIB::REM_F128] = "fmodl";
150 Names[RTLIB::REM_PPCF128] = "fmodl";
151 Names[RTLIB::FMA_F32] = "fmaf";
152 Names[RTLIB::FMA_F64] = "fma";
153 Names[RTLIB::FMA_F80] = "fmal";
154 Names[RTLIB::FMA_F128] = "fmal";
155 Names[RTLIB::FMA_PPCF128] = "fmal";
156 Names[RTLIB::POWI_F32] = "__powisf2";
157 Names[RTLIB::POWI_F64] = "__powidf2";
158 Names[RTLIB::POWI_F80] = "__powixf2";
159 Names[RTLIB::POWI_F128] = "__powitf2";
160 Names[RTLIB::POWI_PPCF128] = "__powitf2";
161 Names[RTLIB::SQRT_F32] = "sqrtf";
162 Names[RTLIB::SQRT_F64] = "sqrt";
163 Names[RTLIB::SQRT_F80] = "sqrtl";
164 Names[RTLIB::SQRT_F128] = "sqrtl";
165 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
166 Names[RTLIB::LOG_F32] = "logf";
167 Names[RTLIB::LOG_F64] = "log";
168 Names[RTLIB::LOG_F80] = "logl";
169 Names[RTLIB::LOG_F128] = "logl";
170 Names[RTLIB::LOG_PPCF128] = "logl";
171 Names[RTLIB::LOG2_F32] = "log2f";
172 Names[RTLIB::LOG2_F64] = "log2";
173 Names[RTLIB::LOG2_F80] = "log2l";
174 Names[RTLIB::LOG2_F128] = "log2l";
175 Names[RTLIB::LOG2_PPCF128] = "log2l";
176 Names[RTLIB::LOG10_F32] = "log10f";
177 Names[RTLIB::LOG10_F64] = "log10";
178 Names[RTLIB::LOG10_F80] = "log10l";
179 Names[RTLIB::LOG10_F128] = "log10l";
180 Names[RTLIB::LOG10_PPCF128] = "log10l";
181 Names[RTLIB::EXP_F32] = "expf";
182 Names[RTLIB::EXP_F64] = "exp";
183 Names[RTLIB::EXP_F80] = "expl";
184 Names[RTLIB::EXP_F128] = "expl";
185 Names[RTLIB::EXP_PPCF128] = "expl";
186 Names[RTLIB::EXP2_F32] = "exp2f";
187 Names[RTLIB::EXP2_F64] = "exp2";
188 Names[RTLIB::EXP2_F80] = "exp2l";
189 Names[RTLIB::EXP2_F128] = "exp2l";
190 Names[RTLIB::EXP2_PPCF128] = "exp2l";
191 Names[RTLIB::SIN_F32] = "sinf";
192 Names[RTLIB::SIN_F64] = "sin";
193 Names[RTLIB::SIN_F80] = "sinl";
194 Names[RTLIB::SIN_F128] = "sinl";
195 Names[RTLIB::SIN_PPCF128] = "sinl";
196 Names[RTLIB::COS_F32] = "cosf";
197 Names[RTLIB::COS_F64] = "cos";
198 Names[RTLIB::COS_F80] = "cosl";
199 Names[RTLIB::COS_F128] = "cosl";
200 Names[RTLIB::COS_PPCF128] = "cosl";
201 Names[RTLIB::POW_F32] = "powf";
202 Names[RTLIB::POW_F64] = "pow";
203 Names[RTLIB::POW_F80] = "powl";
204 Names[RTLIB::POW_F128] = "powl";
205 Names[RTLIB::POW_PPCF128] = "powl";
206 Names[RTLIB::CEIL_F32] = "ceilf";
207 Names[RTLIB::CEIL_F64] = "ceil";
208 Names[RTLIB::CEIL_F80] = "ceill";
209 Names[RTLIB::CEIL_F128] = "ceill";
210 Names[RTLIB::CEIL_PPCF128] = "ceill";
211 Names[RTLIB::TRUNC_F32] = "truncf";
212 Names[RTLIB::TRUNC_F64] = "trunc";
213 Names[RTLIB::TRUNC_F80] = "truncl";
214 Names[RTLIB::TRUNC_F128] = "truncl";
215 Names[RTLIB::TRUNC_PPCF128] = "truncl";
216 Names[RTLIB::RINT_F32] = "rintf";
217 Names[RTLIB::RINT_F64] = "rint";
218 Names[RTLIB::RINT_F80] = "rintl";
219 Names[RTLIB::RINT_F128] = "rintl";
220 Names[RTLIB::RINT_PPCF128] = "rintl";
221 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
222 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
223 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
224 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
225 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
Hal Finkel171817e2013-08-07 22:49:12 +0000[diff] [blame]226 Names[RTLIB::ROUND_F32] = "roundf";
227 Names[RTLIB::ROUND_F64] = "round";
228 Names[RTLIB::ROUND_F80] = "roundl";
229 Names[RTLIB::ROUND_F128] = "roundl";
230 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]231 Names[RTLIB::FLOOR_F32] = "floorf";
232 Names[RTLIB::FLOOR_F64] = "floor";
233 Names[RTLIB::FLOOR_F80] = "floorl";
234 Names[RTLIB::FLOOR_F128] = "floorl";
235 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Matt Arsenault7c936902014-10-21 23:01:01 +0000[diff] [blame]236 Names[RTLIB::FMIN_F32] = "fminf";
237 Names[RTLIB::FMIN_F64] = "fmin";
238 Names[RTLIB::FMIN_F80] = "fminl";
239 Names[RTLIB::FMIN_F128] = "fminl";
240 Names[RTLIB::FMIN_PPCF128] = "fminl";
241 Names[RTLIB::FMAX_F32] = "fmaxf";
242 Names[RTLIB::FMAX_F64] = "fmax";
243 Names[RTLIB::FMAX_F80] = "fmaxl";
244 Names[RTLIB::FMAX_F128] = "fmaxl";
245 Names[RTLIB::FMAX_PPCF128] = "fmaxl";
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]246 Names[RTLIB::ROUND_F32] = "roundf";
247 Names[RTLIB::ROUND_F64] = "round";
248 Names[RTLIB::ROUND_F80] = "roundl";
249 Names[RTLIB::ROUND_F128] = "roundl";
250 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]251 Names[RTLIB::COPYSIGN_F32] = "copysignf";
252 Names[RTLIB::COPYSIGN_F64] = "copysign";
253 Names[RTLIB::COPYSIGN_F80] = "copysignl";
254 Names[RTLIB::COPYSIGN_F128] = "copysignl";
255 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]256 Names[RTLIB::FPEXT_F32_PPCF128] = "__gcc_stoq";
257 Names[RTLIB::FPEXT_F64_PPCF128] = "__gcc_dtoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]258 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
259 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
260 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
James Y Knight7873fb92016-04-12 22:32:47 +0000[diff] [blame]261 if (TT.isOSDarwin()) {
262 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
263 // of the gnueabi-style __gnu_*_ieee.
264 // FIXME: What about other targets?
265 Names[RTLIB::FPEXT_F16_F32] = "__extendhfsf2";
266 Names[RTLIB::FPROUND_F32_F16] = "__truncsfhf2";
267 } else {
268 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
269 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
270 }
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]271 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2";
272 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2";
273 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2";
274 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]275 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
276 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
277 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]278 Names[RTLIB::FPROUND_PPCF128_F32] = "__gcc_qtos";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]279 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
280 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]281 Names[RTLIB::FPROUND_PPCF128_F64] = "__gcc_qtod";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]282 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
283 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
284 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]285 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
286 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
287 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
288 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
289 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
290 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
291 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
292 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
293 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]294 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__gcc_qtou";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]295 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
296 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]297 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
298 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
299 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]300 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
301 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
302 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
303 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
304 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
305 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
306 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
307 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
308 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
309 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
310 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
311 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
312 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
313 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
314 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
315 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]316 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__gcc_itoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]317 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
318 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
319 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
320 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
321 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
322 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
323 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
324 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
325 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
326 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
327 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
328 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
329 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
330 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]331 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__gcc_utoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]332 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
333 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
334 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
335 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
336 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
337 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
338 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
339 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
340 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
341 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
342 Names[RTLIB::OEQ_F32] = "__eqsf2";
343 Names[RTLIB::OEQ_F64] = "__eqdf2";
344 Names[RTLIB::OEQ_F128] = "__eqtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]345 Names[RTLIB::OEQ_PPCF128] = "__gcc_qeq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]346 Names[RTLIB::UNE_F32] = "__nesf2";
347 Names[RTLIB::UNE_F64] = "__nedf2";
348 Names[RTLIB::UNE_F128] = "__netf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]349 Names[RTLIB::UNE_PPCF128] = "__gcc_qne";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]350 Names[RTLIB::OGE_F32] = "__gesf2";
351 Names[RTLIB::OGE_F64] = "__gedf2";
352 Names[RTLIB::OGE_F128] = "__getf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]353 Names[RTLIB::OGE_PPCF128] = "__gcc_qge";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]354 Names[RTLIB::OLT_F32] = "__ltsf2";
355 Names[RTLIB::OLT_F64] = "__ltdf2";
356 Names[RTLIB::OLT_F128] = "__lttf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]357 Names[RTLIB::OLT_PPCF128] = "__gcc_qlt";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]358 Names[RTLIB::OLE_F32] = "__lesf2";
359 Names[RTLIB::OLE_F64] = "__ledf2";
360 Names[RTLIB::OLE_F128] = "__letf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]361 Names[RTLIB::OLE_PPCF128] = "__gcc_qle";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]362 Names[RTLIB::OGT_F32] = "__gtsf2";
363 Names[RTLIB::OGT_F64] = "__gtdf2";
364 Names[RTLIB::OGT_F128] = "__gttf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]365 Names[RTLIB::OGT_PPCF128] = "__gcc_qgt";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]366 Names[RTLIB::UO_F32] = "__unordsf2";
367 Names[RTLIB::UO_F64] = "__unorddf2";
368 Names[RTLIB::UO_F128] = "__unordtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]369 Names[RTLIB::UO_PPCF128] = "__gcc_qunord";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]370 Names[RTLIB::O_F32] = "__unordsf2";
371 Names[RTLIB::O_F64] = "__unorddf2";
372 Names[RTLIB::O_F128] = "__unordtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]373 Names[RTLIB::O_PPCF128] = "__gcc_qunord";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]374 Names[RTLIB::MEMCPY] = "memcpy";
375 Names[RTLIB::MEMMOVE] = "memmove";
376 Names[RTLIB::MEMSET] = "memset";
Daniel Neilson3faabbb2017-06-16 14:43:59 +0000[diff] [blame^]377 Names[RTLIB::MEMCPY_ELEMENT_UNORDERED_ATOMIC_1] =
378 "__llvm_memcpy_element_unordered_atomic_1";
379 Names[RTLIB::MEMCPY_ELEMENT_UNORDERED_ATOMIC_2] =
380 "__llvm_memcpy_element_unordered_atomic_2";
381 Names[RTLIB::MEMCPY_ELEMENT_UNORDERED_ATOMIC_4] =
382 "__llvm_memcpy_element_unordered_atomic_4";
383 Names[RTLIB::MEMCPY_ELEMENT_UNORDERED_ATOMIC_8] =
384 "__llvm_memcpy_element_unordered_atomic_8";
385 Names[RTLIB::MEMCPY_ELEMENT_UNORDERED_ATOMIC_16] =
386 "__llvm_memcpy_element_unordered_atomic_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]387 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
388 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
389 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
390 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
391 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]392 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]393 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
394 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
395 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
396 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]397 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]398 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
399 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
400 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
401 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]402 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]403 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
404 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
405 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
406 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]407 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]408 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
409 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
410 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
411 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]412 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]413 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
414 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
415 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
416 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]417 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]418 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
419 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
420 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
421 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]422 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]423 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
424 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
425 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
426 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]427 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
Tim Northovera564d322013-10-25 09:30:20 +0000[diff] [blame]428 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1";
429 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2";
430 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4";
431 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8";
432 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16";
433 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1";
434 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2";
435 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4";
436 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8";
437 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16";
438 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1";
439 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2";
440 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4";
441 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8";
442 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16";
443 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1";
444 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2";
445 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4";
446 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8";
447 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16";
James Y Knight19f6cce2016-04-12 20:18:48 +0000[diff] [blame]448
449 Names[RTLIB::ATOMIC_LOAD] = "__atomic_load";
450 Names[RTLIB::ATOMIC_LOAD_1] = "__atomic_load_1";
451 Names[RTLIB::ATOMIC_LOAD_2] = "__atomic_load_2";
452 Names[RTLIB::ATOMIC_LOAD_4] = "__atomic_load_4";
453 Names[RTLIB::ATOMIC_LOAD_8] = "__atomic_load_8";
454 Names[RTLIB::ATOMIC_LOAD_16] = "__atomic_load_16";
455
456 Names[RTLIB::ATOMIC_STORE] = "__atomic_store";
457 Names[RTLIB::ATOMIC_STORE_1] = "__atomic_store_1";
458 Names[RTLIB::ATOMIC_STORE_2] = "__atomic_store_2";
459 Names[RTLIB::ATOMIC_STORE_4] = "__atomic_store_4";
460 Names[RTLIB::ATOMIC_STORE_8] = "__atomic_store_8";
461 Names[RTLIB::ATOMIC_STORE_16] = "__atomic_store_16";
462
463 Names[RTLIB::ATOMIC_EXCHANGE] = "__atomic_exchange";
464 Names[RTLIB::ATOMIC_EXCHANGE_1] = "__atomic_exchange_1";
465 Names[RTLIB::ATOMIC_EXCHANGE_2] = "__atomic_exchange_2";
466 Names[RTLIB::ATOMIC_EXCHANGE_4] = "__atomic_exchange_4";
467 Names[RTLIB::ATOMIC_EXCHANGE_8] = "__atomic_exchange_8";
468 Names[RTLIB::ATOMIC_EXCHANGE_16] = "__atomic_exchange_16";
469
470 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE] = "__atomic_compare_exchange";
471 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_1] = "__atomic_compare_exchange_1";
472 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_2] = "__atomic_compare_exchange_2";
473 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_4] = "__atomic_compare_exchange_4";
474 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_8] = "__atomic_compare_exchange_8";
475 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_16] = "__atomic_compare_exchange_16";
476
477 Names[RTLIB::ATOMIC_FETCH_ADD_1] = "__atomic_fetch_add_1";
478 Names[RTLIB::ATOMIC_FETCH_ADD_2] = "__atomic_fetch_add_2";
479 Names[RTLIB::ATOMIC_FETCH_ADD_4] = "__atomic_fetch_add_4";
480 Names[RTLIB::ATOMIC_FETCH_ADD_8] = "__atomic_fetch_add_8";
481 Names[RTLIB::ATOMIC_FETCH_ADD_16] = "__atomic_fetch_add_16";
482 Names[RTLIB::ATOMIC_FETCH_SUB_1] = "__atomic_fetch_sub_1";
483 Names[RTLIB::ATOMIC_FETCH_SUB_2] = "__atomic_fetch_sub_2";
484 Names[RTLIB::ATOMIC_FETCH_SUB_4] = "__atomic_fetch_sub_4";
485 Names[RTLIB::ATOMIC_FETCH_SUB_8] = "__atomic_fetch_sub_8";
486 Names[RTLIB::ATOMIC_FETCH_SUB_16] = "__atomic_fetch_sub_16";
487 Names[RTLIB::ATOMIC_FETCH_AND_1] = "__atomic_fetch_and_1";
488 Names[RTLIB::ATOMIC_FETCH_AND_2] = "__atomic_fetch_and_2";
489 Names[RTLIB::ATOMIC_FETCH_AND_4] = "__atomic_fetch_and_4";
490 Names[RTLIB::ATOMIC_FETCH_AND_8] = "__atomic_fetch_and_8";
491 Names[RTLIB::ATOMIC_FETCH_AND_16] = "__atomic_fetch_and_16";
492 Names[RTLIB::ATOMIC_FETCH_OR_1] = "__atomic_fetch_or_1";
493 Names[RTLIB::ATOMIC_FETCH_OR_2] = "__atomic_fetch_or_2";
494 Names[RTLIB::ATOMIC_FETCH_OR_4] = "__atomic_fetch_or_4";
495 Names[RTLIB::ATOMIC_FETCH_OR_8] = "__atomic_fetch_or_8";
496 Names[RTLIB::ATOMIC_FETCH_OR_16] = "__atomic_fetch_or_16";
497 Names[RTLIB::ATOMIC_FETCH_XOR_1] = "__atomic_fetch_xor_1";
498 Names[RTLIB::ATOMIC_FETCH_XOR_2] = "__atomic_fetch_xor_2";
499 Names[RTLIB::ATOMIC_FETCH_XOR_4] = "__atomic_fetch_xor_4";
500 Names[RTLIB::ATOMIC_FETCH_XOR_8] = "__atomic_fetch_xor_8";
501 Names[RTLIB::ATOMIC_FETCH_XOR_16] = "__atomic_fetch_xor_16";
502 Names[RTLIB::ATOMIC_FETCH_NAND_1] = "__atomic_fetch_nand_1";
503 Names[RTLIB::ATOMIC_FETCH_NAND_2] = "__atomic_fetch_nand_2";
504 Names[RTLIB::ATOMIC_FETCH_NAND_4] = "__atomic_fetch_nand_4";
505 Names[RTLIB::ATOMIC_FETCH_NAND_8] = "__atomic_fetch_nand_8";
506 Names[RTLIB::ATOMIC_FETCH_NAND_16] = "__atomic_fetch_nand_16";
507
Daniel Sandersbf2c03e2016-06-21 12:29:03 +0000[diff] [blame]508 if (TT.isGNUEnvironment()) {
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]509 Names[RTLIB::SINCOS_F32] = "sincosf";
510 Names[RTLIB::SINCOS_F64] = "sincos";
511 Names[RTLIB::SINCOS_F80] = "sincosl";
512 Names[RTLIB::SINCOS_F128] = "sincosl";
513 Names[RTLIB::SINCOS_PPCF128] = "sincosl";
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]514 }
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]515
Simon Pilgrim2bfd9122014-11-29 19:18:21 +0000[diff] [blame]516 if (!TT.isOSOpenBSD()) {
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]517 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
Ahmed Bougacha6402ad22015-05-14 01:00:51 +0000[diff] [blame]518 }
Sanjoy Dasdf9ae702016-03-24 20:23:29 +0000[diff] [blame]519
520 Names[RTLIB::DEOPTIMIZE] = "__llvm_deoptimize";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]521}
522
Saleem Abdulrasool02d98512016-09-07 17:56:09 +0000[diff] [blame]523/// Set default libcall CallingConvs.
Saleem Abdulrasool92e33a32016-09-09 20:11:31 +0000[diff] [blame]524static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
Saleem Abdulrasool02d98512016-09-07 17:56:09 +0000[diff] [blame]525 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
526 CCs[LC] = CallingConv::C;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]527}
528
529/// getFPEXT - Return the FPEXT_*_* value for the given types, or
530/// UNKNOWN_LIBCALL if there is none.
531RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Tim Northoverf7a02c12014-07-21 09:13:56 +0000[diff] [blame]532 if (OpVT == MVT::f16) {
533 if (RetVT == MVT::f32)
534 return FPEXT_F16_F32;
535 } else if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]536 if (RetVT == MVT::f64)
537 return FPEXT_F32_F64;
538 if (RetVT == MVT::f128)
539 return FPEXT_F32_F128;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]540 if (RetVT == MVT::ppcf128)
541 return FPEXT_F32_PPCF128;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]542 } else if (OpVT == MVT::f64) {
543 if (RetVT == MVT::f128)
544 return FPEXT_F64_F128;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]545 else if (RetVT == MVT::ppcf128)
546 return FPEXT_F64_PPCF128;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]547 }
548
549 return UNKNOWN_LIBCALL;
550}
551
552/// getFPROUND - Return the FPROUND_*_* value for the given types, or
553/// UNKNOWN_LIBCALL if there is none.
554RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]555 if (RetVT == MVT::f16) {
556 if (OpVT == MVT::f32)
557 return FPROUND_F32_F16;
558 if (OpVT == MVT::f64)
559 return FPROUND_F64_F16;
560 if (OpVT == MVT::f80)
561 return FPROUND_F80_F16;
562 if (OpVT == MVT::f128)
563 return FPROUND_F128_F16;
564 if (OpVT == MVT::ppcf128)
565 return FPROUND_PPCF128_F16;
566 } else if (RetVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]567 if (OpVT == MVT::f64)
568 return FPROUND_F64_F32;
569 if (OpVT == MVT::f80)
570 return FPROUND_F80_F32;
571 if (OpVT == MVT::f128)
572 return FPROUND_F128_F32;
573 if (OpVT == MVT::ppcf128)
574 return FPROUND_PPCF128_F32;
575 } else if (RetVT == MVT::f64) {
576 if (OpVT == MVT::f80)
577 return FPROUND_F80_F64;
578 if (OpVT == MVT::f128)
579 return FPROUND_F128_F64;
580 if (OpVT == MVT::ppcf128)
581 return FPROUND_PPCF128_F64;
582 }
583
584 return UNKNOWN_LIBCALL;
585}
586
587/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
588/// UNKNOWN_LIBCALL if there is none.
589RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
590 if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]591 if (RetVT == MVT::i32)
592 return FPTOSINT_F32_I32;
593 if (RetVT == MVT::i64)
594 return FPTOSINT_F32_I64;
595 if (RetVT == MVT::i128)
596 return FPTOSINT_F32_I128;
597 } else if (OpVT == MVT::f64) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]598 if (RetVT == MVT::i32)
599 return FPTOSINT_F64_I32;
600 if (RetVT == MVT::i64)
601 return FPTOSINT_F64_I64;
602 if (RetVT == MVT::i128)
603 return FPTOSINT_F64_I128;
604 } else if (OpVT == MVT::f80) {
605 if (RetVT == MVT::i32)
606 return FPTOSINT_F80_I32;
607 if (RetVT == MVT::i64)
608 return FPTOSINT_F80_I64;
609 if (RetVT == MVT::i128)
610 return FPTOSINT_F80_I128;
611 } else if (OpVT == MVT::f128) {
612 if (RetVT == MVT::i32)
613 return FPTOSINT_F128_I32;
614 if (RetVT == MVT::i64)
615 return FPTOSINT_F128_I64;
616 if (RetVT == MVT::i128)
617 return FPTOSINT_F128_I128;
618 } else if (OpVT == MVT::ppcf128) {
619 if (RetVT == MVT::i32)
620 return FPTOSINT_PPCF128_I32;
621 if (RetVT == MVT::i64)
622 return FPTOSINT_PPCF128_I64;
623 if (RetVT == MVT::i128)
624 return FPTOSINT_PPCF128_I128;
625 }
626 return UNKNOWN_LIBCALL;
627}
628
629/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
630/// UNKNOWN_LIBCALL if there is none.
631RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
632 if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]633 if (RetVT == MVT::i32)
634 return FPTOUINT_F32_I32;
635 if (RetVT == MVT::i64)
636 return FPTOUINT_F32_I64;
637 if (RetVT == MVT::i128)
638 return FPTOUINT_F32_I128;
639 } else if (OpVT == MVT::f64) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]640 if (RetVT == MVT::i32)
641 return FPTOUINT_F64_I32;
642 if (RetVT == MVT::i64)
643 return FPTOUINT_F64_I64;
644 if (RetVT == MVT::i128)
645 return FPTOUINT_F64_I128;
646 } else if (OpVT == MVT::f80) {
647 if (RetVT == MVT::i32)
648 return FPTOUINT_F80_I32;
649 if (RetVT == MVT::i64)
650 return FPTOUINT_F80_I64;
651 if (RetVT == MVT::i128)
652 return FPTOUINT_F80_I128;
653 } else if (OpVT == MVT::f128) {
654 if (RetVT == MVT::i32)
655 return FPTOUINT_F128_I32;
656 if (RetVT == MVT::i64)
657 return FPTOUINT_F128_I64;
658 if (RetVT == MVT::i128)
659 return FPTOUINT_F128_I128;
660 } else if (OpVT == MVT::ppcf128) {
661 if (RetVT == MVT::i32)
662 return FPTOUINT_PPCF128_I32;
663 if (RetVT == MVT::i64)
664 return FPTOUINT_PPCF128_I64;
665 if (RetVT == MVT::i128)
666 return FPTOUINT_PPCF128_I128;
667 }
668 return UNKNOWN_LIBCALL;
669}
670
671/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
672/// UNKNOWN_LIBCALL if there is none.
673RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
674 if (OpVT == MVT::i32) {
675 if (RetVT == MVT::f32)
676 return SINTTOFP_I32_F32;
677 if (RetVT == MVT::f64)
678 return SINTTOFP_I32_F64;
679 if (RetVT == MVT::f80)
680 return SINTTOFP_I32_F80;
681 if (RetVT == MVT::f128)
682 return SINTTOFP_I32_F128;
683 if (RetVT == MVT::ppcf128)
684 return SINTTOFP_I32_PPCF128;
685 } else if (OpVT == MVT::i64) {
686 if (RetVT == MVT::f32)
687 return SINTTOFP_I64_F32;
688 if (RetVT == MVT::f64)
689 return SINTTOFP_I64_F64;
690 if (RetVT == MVT::f80)
691 return SINTTOFP_I64_F80;
692 if (RetVT == MVT::f128)
693 return SINTTOFP_I64_F128;
694 if (RetVT == MVT::ppcf128)
695 return SINTTOFP_I64_PPCF128;
696 } else if (OpVT == MVT::i128) {
697 if (RetVT == MVT::f32)
698 return SINTTOFP_I128_F32;
699 if (RetVT == MVT::f64)
700 return SINTTOFP_I128_F64;
701 if (RetVT == MVT::f80)
702 return SINTTOFP_I128_F80;
703 if (RetVT == MVT::f128)
704 return SINTTOFP_I128_F128;
705 if (RetVT == MVT::ppcf128)
706 return SINTTOFP_I128_PPCF128;
707 }
708 return UNKNOWN_LIBCALL;
709}
710
711/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
712/// UNKNOWN_LIBCALL if there is none.
713RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
714 if (OpVT == MVT::i32) {
715 if (RetVT == MVT::f32)
716 return UINTTOFP_I32_F32;
717 if (RetVT == MVT::f64)
718 return UINTTOFP_I32_F64;
719 if (RetVT == MVT::f80)
720 return UINTTOFP_I32_F80;
721 if (RetVT == MVT::f128)
722 return UINTTOFP_I32_F128;
723 if (RetVT == MVT::ppcf128)
724 return UINTTOFP_I32_PPCF128;
725 } else if (OpVT == MVT::i64) {
726 if (RetVT == MVT::f32)
727 return UINTTOFP_I64_F32;
728 if (RetVT == MVT::f64)
729 return UINTTOFP_I64_F64;
730 if (RetVT == MVT::f80)
731 return UINTTOFP_I64_F80;
732 if (RetVT == MVT::f128)
733 return UINTTOFP_I64_F128;
734 if (RetVT == MVT::ppcf128)
735 return UINTTOFP_I64_PPCF128;
736 } else if (OpVT == MVT::i128) {
737 if (RetVT == MVT::f32)
738 return UINTTOFP_I128_F32;
739 if (RetVT == MVT::f64)
740 return UINTTOFP_I128_F64;
741 if (RetVT == MVT::f80)
742 return UINTTOFP_I128_F80;
743 if (RetVT == MVT::f128)
744 return UINTTOFP_I128_F128;
745 if (RetVT == MVT::ppcf128)
746 return UINTTOFP_I128_PPCF128;
747 }
748 return UNKNOWN_LIBCALL;
749}
750
James Y Knightf44fc522016-03-16 22:12:04 +0000[diff] [blame]751RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
Benjamin Kramerc54c38e2015-03-05 20:04:29 +0000[diff] [blame]752#define OP_TO_LIBCALL(Name, Enum) \
753 case Name: \
754 switch (VT.SimpleTy) { \
755 default: \
756 return UNKNOWN_LIBCALL; \
757 case MVT::i8: \
758 return Enum##_1; \
759 case MVT::i16: \
760 return Enum##_2; \
761 case MVT::i32: \
762 return Enum##_4; \
763 case MVT::i64: \
764 return Enum##_8; \
765 case MVT::i128: \
766 return Enum##_16; \
767 }
768
769 switch (Opc) {
770 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
771 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
772 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
773 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
774 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
775 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
776 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
777 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
778 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
779 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
780 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
781 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
782 }
783
784#undef OP_TO_LIBCALL
785
786 return UNKNOWN_LIBCALL;
787}
788
Daniel Neilson3faabbb2017-06-16 14:43:59 +0000[diff] [blame^]789RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
Igor Laevsky4f31e522016-12-29 14:31:07 +0000[diff] [blame]790 switch (ElementSize) {
791 case 1:
Daniel Neilson3faabbb2017-06-16 14:43:59 +0000[diff] [blame^]792 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
Igor Laevsky4f31e522016-12-29 14:31:07 +0000[diff] [blame]793 case 2:
Daniel Neilson3faabbb2017-06-16 14:43:59 +0000[diff] [blame^]794 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
Igor Laevsky4f31e522016-12-29 14:31:07 +0000[diff] [blame]795 case 4:
Daniel Neilson3faabbb2017-06-16 14:43:59 +0000[diff] [blame^]796 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
Igor Laevsky4f31e522016-12-29 14:31:07 +0000[diff] [blame]797 case 8:
Daniel Neilson3faabbb2017-06-16 14:43:59 +0000[diff] [blame^]798 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
Igor Laevsky4f31e522016-12-29 14:31:07 +0000[diff] [blame]799 case 16:
Daniel Neilson3faabbb2017-06-16 14:43:59 +0000[diff] [blame^]800 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
Igor Laevsky4f31e522016-12-29 14:31:07 +0000[diff] [blame]801 default:
802 return UNKNOWN_LIBCALL;
803 }
Igor Laevsky4f31e522016-12-29 14:31:07 +0000[diff] [blame]804}
805
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]806/// InitCmpLibcallCCs - Set default comparison libcall CC.
807///
808static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
809 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
810 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
811 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
812 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]813 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]814 CCs[RTLIB::UNE_F32] = ISD::SETNE;
815 CCs[RTLIB::UNE_F64] = ISD::SETNE;
816 CCs[RTLIB::UNE_F128] = ISD::SETNE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]817 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]818 CCs[RTLIB::OGE_F32] = ISD::SETGE;
819 CCs[RTLIB::OGE_F64] = ISD::SETGE;
820 CCs[RTLIB::OGE_F128] = ISD::SETGE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]821 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]822 CCs[RTLIB::OLT_F32] = ISD::SETLT;
823 CCs[RTLIB::OLT_F64] = ISD::SETLT;
824 CCs[RTLIB::OLT_F128] = ISD::SETLT;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]825 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]826 CCs[RTLIB::OLE_F32] = ISD::SETLE;
827 CCs[RTLIB::OLE_F64] = ISD::SETLE;
828 CCs[RTLIB::OLE_F128] = ISD::SETLE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]829 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]830 CCs[RTLIB::OGT_F32] = ISD::SETGT;
831 CCs[RTLIB::OGT_F64] = ISD::SETGT;
832 CCs[RTLIB::OGT_F128] = ISD::SETGT;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]833 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]834 CCs[RTLIB::UO_F32] = ISD::SETNE;
835 CCs[RTLIB::UO_F64] = ISD::SETNE;
836 CCs[RTLIB::UO_F128] = ISD::SETNE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]837 CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]838 CCs[RTLIB::O_F32] = ISD::SETEQ;
839 CCs[RTLIB::O_F64] = ISD::SETEQ;
840 CCs[RTLIB::O_F128] = ISD::SETEQ;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]841 CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]842}
843
Aditya Nandakumar30531552014-11-13 21:29:21 +0000[diff] [blame]844/// NOTE: The TargetMachine owns TLOF.
Mehdi Aminia28d91d2015-03-10 02:37:25 +0000[diff] [blame]845TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]846 initActions();
847
848 // Perform these initializations only once.
Zaara Syeda3a7578c2017-05-31 17:12:38 +0000[diff] [blame]849 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove =
850 MaxLoadsPerMemcmp = 8;
851 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize =
852 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]853 UseUnderscoreSetJmp = false;
854 UseUnderscoreLongJmp = false;
Hal Finkeldecb0242014-01-02 21:13:43 +0000[diff] [blame]855 HasMultipleConditionRegisters = false;
Yi Jiangb23edeb2014-04-21 22:22:44 +0000[diff] [blame]856 HasExtractBitsInsn = false;
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]857 JumpIsExpensive = JumpIsExpensiveOverride;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]858 PredictableSelectIsExpensive = false;
Quentin Colombetfc2201e2014-12-17 01:36:17 +0000[diff] [blame]859 EnableExtLdPromotion = false;
Pedro Artigascaa56582014-08-08 16:46:53 +0000[diff] [blame]860 HasFloatingPointExceptions = true;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]861 StackPointerRegisterToSaveRestore = 0;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]862 BooleanContents = UndefinedBooleanContent;
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]863 BooleanFloatContents = UndefinedBooleanContent;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]864 BooleanVectorContents = UndefinedBooleanContent;
865 SchedPreferenceInfo = Sched::ILP;
866 JumpBufSize = 0;
867 JumpBufAlignment = 0;
868 MinFunctionAlignment = 0;
869 PrefFunctionAlignment = 0;
870 PrefLoopAlignment = 0;
Nirav Dave54e22f32017-03-14 00:34:14 +0000[diff] [blame]871 GatherAllAliasesMaxDepth = 18;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]872 MinStackArgumentAlignment = 1;
James Y Knight19f6cce2016-04-12 20:18:48 +0000[diff] [blame]873 // TODO: the default will be switched to 0 in the next commit, along
874 // with the Target-specific changes necessary.
875 MaxAtomicSizeInBitsSupported = 1024;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]876
James Y Knight148a6462016-06-17 18:11:48 +0000[diff] [blame]877 MinCmpXchgSizeInBits = 0;
878
James Y Knight7873fb92016-04-12 22:32:47 +0000[diff] [blame]879 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
880
Daniel Sanders110bf6d2015-06-24 13:25:57 +0000[diff] [blame]881 InitLibcallNames(LibcallRoutineNames, TM.getTargetTriple());
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]882 InitCmpLibcallCCs(CmpLibcallCCs);
Saleem Abdulrasool92e33a32016-09-09 20:11:31 +0000[diff] [blame]883 InitLibcallCallingConvs(LibcallCallingConvs);
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]884}
885
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]886void TargetLoweringBase::initActions() {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]887 // All operations default to being supported.
888 memset(OpActions, 0, sizeof(OpActions));
889 memset(LoadExtActions, 0, sizeof(LoadExtActions));
890 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
891 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
892 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Craig Topper00230802016-04-08 07:10:46 +0000[diff] [blame]893 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
894 std::fill(std::begin(TargetDAGCombineArray),
895 std::end(TargetDAGCombineArray), 0);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]896
897 // Set default actions for various operations.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]898 for (MVT VT : MVT::all_valuetypes()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]899 // Default all indexed load / store to expand.
900 for (unsigned IM = (unsigned)ISD::PRE_INC;
901 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]902 setIndexedLoadAction(IM, VT, Expand);
903 setIndexedStoreAction(IM, VT, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]904 }
905
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]906 // Most backends expect to see the node which just returns the value loaded.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]907 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand);
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]908
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]909 // These operations default to expand.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]910 setOperationAction(ISD::FGETSIGN, VT, Expand);
911 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
912 setOperationAction(ISD::FMINNUM, VT, Expand);
913 setOperationAction(ISD::FMAXNUM, VT, Expand);
James Molloy01cdecc2015-08-11 09:13:05 +0000[diff] [blame]914 setOperationAction(ISD::FMINNAN, VT, Expand);
915 setOperationAction(ISD::FMAXNAN, VT, Expand);
Matt Arsenault0dc54c42015-02-20 22:10:33 +0000[diff] [blame]916 setOperationAction(ISD::FMAD, VT, Expand);
James Molloy7e9776b2015-05-15 09:03:15 +0000[diff] [blame]917 setOperationAction(ISD::SMIN, VT, Expand);
918 setOperationAction(ISD::SMAX, VT, Expand);
919 setOperationAction(ISD::UMIN, VT, Expand);
920 setOperationAction(ISD::UMAX, VT, Expand);
Simon Pilgrimcf2da962017-03-14 21:26:58 +0000[diff] [blame]921 setOperationAction(ISD::ABS, VT, Expand);
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]922
Jan Vesely75395482015-04-29 16:30:46 +0000[diff] [blame]923 // Overflow operations default to expand
924 setOperationAction(ISD::SADDO, VT, Expand);
925 setOperationAction(ISD::SSUBO, VT, Expand);
926 setOperationAction(ISD::UADDO, VT, Expand);
927 setOperationAction(ISD::USUBO, VT, Expand);
928 setOperationAction(ISD::SMULO, VT, Expand);
929 setOperationAction(ISD::UMULO, VT, Expand);
Hal Finkelcd8664c2015-12-11 23:11:52 +0000[diff] [blame]930
Amaury Sechet8ac81f32017-04-30 19:24:09 +0000[diff] [blame]931 // ADDCARRY operations default to expand
932 setOperationAction(ISD::ADDCARRY, VT, Expand);
933 setOperationAction(ISD::SUBCARRY, VT, Expand);
Amaury Sechet251ea8a2017-06-01 11:14:17 +0000[diff] [blame]934 setOperationAction(ISD::SETCCCARRY, VT, Expand);
Amaury Sechet8ac81f32017-04-30 19:24:09 +0000[diff] [blame]935
Craig Topper33772c52016-04-28 03:34:31 +0000[diff] [blame]936 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
937 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
938 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
939
James Molloy90111f72015-11-12 12:29:09 +0000[diff] [blame]940 setOperationAction(ISD::BITREVERSE, VT, Expand);
941
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]942 // These library functions default to expand.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]943 setOperationAction(ISD::FROUND, VT, Expand);
Craig Topperf6d4dc52017-05-30 15:27:55 +0000[diff] [blame]944 setOperationAction(ISD::FPOWI, VT, Expand);
Hal Finkel0c5c01aa2013-08-19 23:35:46 +0000[diff] [blame]945
946 // These operations default to expand for vector types.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]947 if (VT.isVector()) {
948 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
949 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);
950 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
951 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand);
Chandler Carruthd3561f62014-07-09 22:53:04 +0000[diff] [blame]952 }
Yury Gribovd7dbb662015-12-01 11:40:55 +0000[diff] [blame]953
Etienne Bergeron22bfa832016-06-07 20:15:35 +0000[diff] [blame]954 // For most targets @llvm.get.dynamic.area.offset just returns 0.
Yury Gribovd7dbb662015-12-01 11:40:55 +0000[diff] [blame]955 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]956 }
957
958 // Most targets ignore the @llvm.prefetch intrinsic.
959 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
960
Ahmed Bougachaf9c19da2015-08-28 01:49:59 +0000[diff] [blame]961 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
962 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand);
963
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]964 // ConstantFP nodes default to expand. Targets can either change this to
965 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
966 // to optimize expansions for certain constants.
967 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
968 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
969 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
970 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
971 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
972
973 // These library functions default to expand.
Ahmed Bougacha2a20e272015-03-26 23:21:03 +0000[diff] [blame]974 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
975 setOperationAction(ISD::FLOG , VT, Expand);
976 setOperationAction(ISD::FLOG2, VT, Expand);
977 setOperationAction(ISD::FLOG10, VT, Expand);
978 setOperationAction(ISD::FEXP , VT, Expand);
979 setOperationAction(ISD::FEXP2, VT, Expand);
980 setOperationAction(ISD::FFLOOR, VT, Expand);
Ahmed Bougacha2a20e272015-03-26 23:21:03 +0000[diff] [blame]981 setOperationAction(ISD::FNEARBYINT, VT, Expand);
982 setOperationAction(ISD::FCEIL, VT, Expand);
983 setOperationAction(ISD::FRINT, VT, Expand);
984 setOperationAction(ISD::FTRUNC, VT, Expand);
985 setOperationAction(ISD::FROUND, VT, Expand);
986 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]987
988 // Default ISD::TRAP to expand (which turns it into abort).
989 setOperationAction(ISD::TRAP, MVT::Other, Expand);
990
991 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
992 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
993 //
994 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]995}
996
Mehdi Aminieaabc512015-07-09 15:12:23 +0000[diff] [blame]997MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
998 EVT) const {
Mehdi Amini9639d652015-07-09 02:09:20 +0000[diff] [blame]999 return MVT::getIntegerVT(8 * DL.getPointerSize(0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1000}
1001
Mehdi Amini9639d652015-07-09 02:09:20 +0000[diff] [blame]1002EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy,
1003 const DataLayout &DL) const {
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]1004 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
1005 if (LHSTy.isVector())
1006 return LHSTy;
Mehdi Aminieaabc512015-07-09 15:12:23 +0000[diff] [blame]1007 return getScalarShiftAmountTy(DL, LHSTy);
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]1008}
1009
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1010bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
1011 assert(isTypeLegal(VT));
1012 switch (Op) {
1013 default:
1014 return false;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1015 case ISD::SDIV:
1016 case ISD::UDIV:
1017 case ISD::SREM:
1018 case ISD::UREM:
1019 return true;
1020 }
1021}
1022
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]1023void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
1024 // If the command-line option was specified, ignore this request.
1025 if (!JumpIsExpensiveOverride.getNumOccurrences())
1026 JumpIsExpensive = isExpensive;
1027}
1028
Eric Christopher75dbd7c2015-02-25 22:41:30 +0000[diff] [blame]1029TargetLoweringBase::LegalizeKind
1030TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
1031 // If this is a simple type, use the ComputeRegisterProp mechanism.
1032 if (VT.isSimple()) {
1033 MVT SVT = VT.getSimpleVT();
1034 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1035 MVT NVT = TransformToType[SVT.SimpleTy];
1036 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1037
1038 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
1039 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) &&
1040 "Promote may not follow Expand or Promote");
1041
1042 if (LA == TypeSplitVector)
1043 return LegalizeKind(LA,
1044 EVT::getVectorVT(Context, SVT.getVectorElementType(),
1045 SVT.getVectorNumElements() / 2));
1046 if (LA == TypeScalarizeVector)
1047 return LegalizeKind(LA, SVT.getVectorElementType());
1048 return LegalizeKind(LA, NVT);
1049 }
1050
1051 // Handle Extended Scalar Types.
1052 if (!VT.isVector()) {
1053 assert(VT.isInteger() && "Float types must be simple");
1054 unsigned BitSize = VT.getSizeInBits();
1055 // First promote to a power-of-two size, then expand if necessary.
1056 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1057 EVT NVT = VT.getRoundIntegerType(Context);
1058 assert(NVT != VT && "Unable to round integer VT");
1059 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1060 // Avoid multi-step promotion.
1061 if (NextStep.first == TypePromoteInteger)
1062 return NextStep;
1063 // Return rounded integer type.
1064 return LegalizeKind(TypePromoteInteger, NVT);
1065 }
1066
1067 return LegalizeKind(TypeExpandInteger,
1068 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
1069 }
1070
1071 // Handle vector types.
1072 unsigned NumElts = VT.getVectorNumElements();
1073 EVT EltVT = VT.getVectorElementType();
1074
1075 // Vectors with only one element are always scalarized.
1076 if (NumElts == 1)
1077 return LegalizeKind(TypeScalarizeVector, EltVT);
1078
1079 // Try to widen vector elements until the element type is a power of two and
1080 // promote it to a legal type later on, for example:
1081 // <3 x i8> -> <4 x i8> -> <4 x i32>
1082 if (EltVT.isInteger()) {
1083 // Vectors with a number of elements that is not a power of two are always
1084 // widened, for example <3 x i8> -> <4 x i8>.
1085 if (!VT.isPow2VectorType()) {
1086 NumElts = (unsigned)NextPowerOf2(NumElts);
1087 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1088 return LegalizeKind(TypeWidenVector, NVT);
1089 }
1090
1091 // Examine the element type.
1092 LegalizeKind LK = getTypeConversion(Context, EltVT);
1093
1094 // If type is to be expanded, split the vector.
1095 // <4 x i140> -> <2 x i140>
1096 if (LK.first == TypeExpandInteger)
1097 return LegalizeKind(TypeSplitVector,
1098 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1099
1100 // Promote the integer element types until a legal vector type is found
1101 // or until the element integer type is too big. If a legal type was not
1102 // found, fallback to the usual mechanism of widening/splitting the
1103 // vector.
1104 EVT OldEltVT = EltVT;
1105 while (1) {
1106 // Increase the bitwidth of the element to the next pow-of-two
1107 // (which is greater than 8 bits).
1108 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
1109 .getRoundIntegerType(Context);
1110
1111 // Stop trying when getting a non-simple element type.
1112 // Note that vector elements may be greater than legal vector element
1113 // types. Example: X86 XMM registers hold 64bit element on 32bit
1114 // systems.
1115 if (!EltVT.isSimple())
1116 break;
1117
1118 // Build a new vector type and check if it is legal.
1119 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1120 // Found a legal promoted vector type.
1121 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1122 return LegalizeKind(TypePromoteInteger,
1123 EVT::getVectorVT(Context, EltVT, NumElts));
1124 }
1125
1126 // Reset the type to the unexpanded type if we did not find a legal vector
1127 // type with a promoted vector element type.
1128 EltVT = OldEltVT;
1129 }
1130
1131 // Try to widen the vector until a legal type is found.
1132 // If there is no wider legal type, split the vector.
1133 while (1) {
1134 // Round up to the next power of 2.
1135 NumElts = (unsigned)NextPowerOf2(NumElts);
1136
1137 // If there is no simple vector type with this many elements then there
1138 // cannot be a larger legal vector type. Note that this assumes that
1139 // there are no skipped intermediate vector types in the simple types.
1140 if (!EltVT.isSimple())
1141 break;
1142 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1143 if (LargerVector == MVT())
1144 break;
1145
1146 // If this type is legal then widen the vector.
1147 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1148 return LegalizeKind(TypeWidenVector, LargerVector);
1149 }
1150
1151 // Widen odd vectors to next power of two.
1152 if (!VT.isPow2VectorType()) {
1153 EVT NVT = VT.getPow2VectorType(Context);
1154 return LegalizeKind(TypeWidenVector, NVT);
1155 }
1156
1157 // Vectors with illegal element types are expanded.
1158 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1159 return LegalizeKind(TypeSplitVector, NVT);
1160}
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1161
1162static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1163 unsigned &NumIntermediates,
1164 MVT &RegisterVT,
1165 TargetLoweringBase *TLI) {
1166 // Figure out the right, legal destination reg to copy into.
1167 unsigned NumElts = VT.getVectorNumElements();
1168 MVT EltTy = VT.getVectorElementType();
1169
1170 unsigned NumVectorRegs = 1;
1171
1172 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1173 // could break down into LHS/RHS like LegalizeDAG does.
1174 if (!isPowerOf2_32(NumElts)) {
1175 NumVectorRegs = NumElts;
1176 NumElts = 1;
1177 }
1178
1179 // Divide the input until we get to a supported size. This will always
1180 // end with a scalar if the target doesn't support vectors.
1181 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
1182 NumElts >>= 1;
1183 NumVectorRegs <<= 1;
1184 }
1185
1186 NumIntermediates = NumVectorRegs;
1187
1188 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
1189 if (!TLI->isTypeLegal(NewVT))
1190 NewVT = EltTy;
1191 IntermediateVT = NewVT;
1192
1193 unsigned NewVTSize = NewVT.getSizeInBits();
1194
1195 // Convert sizes such as i33 to i64.
1196 if (!isPowerOf2_32(NewVTSize))
1197 NewVTSize = NextPowerOf2(NewVTSize);
1198
1199 MVT DestVT = TLI->getRegisterType(NewVT);
1200 RegisterVT = DestVT;
1201 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1202 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1203
1204 // Otherwise, promotion or legal types use the same number of registers as
1205 // the vector decimated to the appropriate level.
1206 return NumVectorRegs;
1207}
1208
1209/// isLegalRC - Return true if the value types that can be represented by the
1210/// specified register class are all legal.
Krzysztof Parzyszekc8e8e2a2017-04-24 19:51:12 +0000[diff] [blame]1211bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI,
1212 const TargetRegisterClass &RC) const {
1213 for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1214 if (isTypeLegal(*I))
1215 return true;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1216 return false;
1217}
1218
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1219/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1220/// sequence of memory operands that is recognized by PrologEpilogInserter.
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]1221MachineBasicBlock *
1222TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1223 MachineBasicBlock *MBB) const {
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]1224 MachineInstr *MI = &InitialMI;
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1225 MachineFunction &MF = *MI->getParent()->getParent();
Matthias Braun941a7052016-07-28 18:40:00 +0000[diff] [blame]1226 MachineFrameInfo &MFI = MF.getFrameInfo();
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1227
1228 // We're handling multiple types of operands here:
1229 // PATCHPOINT MetaArgs - live-in, read only, direct
1230 // STATEPOINT Deopt Spill - live-through, read only, indirect
1231 // STATEPOINT Deopt Alloca - live-through, read only, direct
1232 // (We're currently conservative and mark the deopt slots read/write in
1233 // practice.)
1234 // STATEPOINT GC Spill - live-through, read/write, indirect
1235 // STATEPOINT GC Alloca - live-through, read/write, direct
1236 // The live-in vs live-through is handled already (the live through ones are
1237 // all stack slots), but we need to handle the different type of stackmap
1238 // operands and memory effects here.
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1239
1240 // MI changes inside this loop as we grow operands.
1241 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
1242 MachineOperand &MO = MI->getOperand(OperIdx);
1243 if (!MO.isFI())
1244 continue;
1245
1246 // foldMemoryOperand builds a new MI after replacing a single FI operand
1247 // with the canonical set of five x86 addressing-mode operands.
1248 int FI = MO.getIndex();
1249 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1250
1251 // Copy operands before the frame-index.
1252 for (unsigned i = 0; i < OperIdx; ++i)
Diana Picus116bbab2017-01-13 09:58:52 +0000[diff] [blame]1253 MIB.add(MI->getOperand(i));
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1254 // Add frame index operands recognized by stackmaps.cpp
1255 if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1256 // indirect-mem-ref tag, size, #FI, offset.
1257 // Used for spills inserted by StatepointLowering. This codepath is not
1258 // used for patchpoints/stackmaps at all, for these spilling is done via
1259 // foldMemoryOperand callback only.
1260 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1261 MIB.addImm(StackMaps::IndirectMemRefOp);
1262 MIB.addImm(MFI.getObjectSize(FI));
Diana Picus116bbab2017-01-13 09:58:52 +0000[diff] [blame]1263 MIB.add(MI->getOperand(OperIdx));
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1264 MIB.addImm(0);
1265 } else {
1266 // direct-mem-ref tag, #FI, offset.
1267 // Used by patchpoint, and direct alloca arguments to statepoints
1268 MIB.addImm(StackMaps::DirectMemRefOp);
Diana Picus116bbab2017-01-13 09:58:52 +0000[diff] [blame]1269 MIB.add(MI->getOperand(OperIdx));
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1270 MIB.addImm(0);
1271 }
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1272 // Copy the operands after the frame index.
1273 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
Diana Picus116bbab2017-01-13 09:58:52 +0000[diff] [blame]1274 MIB.add(MI->getOperand(i));
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1275
1276 // Inherit previous memory operands.
1277 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1278 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1279
1280 // Add a new memory operand for this FI.
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1281 assert(MFI.getObjectOffset(FI) != -1);
Philip Reames0365f1a2014-12-01 22:52:56 +0000[diff] [blame]1282
Justin Lebar0af80cd2016-07-15 18:26:59 +0000[diff] [blame]1283 auto Flags = MachineMemOperand::MOLoad;
Philip Reames0365f1a2014-12-01 22:52:56 +0000[diff] [blame]1284 if (MI->getOpcode() == TargetOpcode::STATEPOINT) {
1285 Flags |= MachineMemOperand::MOStore;
1286 Flags |= MachineMemOperand::MOVolatile;
1287 }
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]1288 MachineMemOperand *MMO = MF.getMachineMemOperand(
Alex Lorenze40c8a22015-08-11 23:09:45 +0000[diff] [blame]1289 MachinePointerInfo::getFixedStack(MF, FI), Flags,
Mehdi Aminibd7287e2015-07-16 06:11:10 +0000[diff] [blame]1290 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI));
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1291 MIB->addMemOperand(MF, MMO);
1292
1293 // Replace the instruction and update the operand index.
1294 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1295 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1296 MI->eraseFromParent();
1297 MI = MIB;
1298 }
1299 return MBB;
1300}
1301
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1302/// findRepresentativeClass - Return the largest legal super-reg register class
1303/// of the register class for the specified type and its associated "cost".
Eric Christopher720ab842015-03-03 19:47:14 +0000[diff] [blame]1304// This function is in TargetLowering because it uses RegClassForVT which would
1305// need to be moved to TargetRegisterInfo and would necessitate moving
1306// isTypeLegal over as well - a massive change that would just require
1307// TargetLowering having a TargetRegisterInfo class member that it would use.
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1308std::pair<const TargetRegisterClass *, uint8_t>
1309TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1310 MVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1311 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1312 if (!RC)
1313 return std::make_pair(RC, 0);
1314
1315 // Compute the set of all super-register classes.
1316 BitVector SuperRegRC(TRI->getNumRegClasses());
1317 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1318 SuperRegRC.setBitsInMask(RCI.getMask());
1319
1320 // Find the first legal register class with the largest spill size.
1321 const TargetRegisterClass *BestRC = RC;
Francis Visoiu Mistrihb52e0362017-05-17 01:07:53 +0000[diff] [blame]1322 for (unsigned i : SuperRegRC.set_bits()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1323 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1324 // We want the largest possible spill size.
Krzysztof Parzyszek44e25f32017-04-24 18:55:33 +0000[diff] [blame]1325 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1326 continue;
Krzysztof Parzyszekc8e8e2a2017-04-24 19:51:12 +0000[diff] [blame]1327 if (!isLegalRC(*TRI, *SuperRC))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1328 continue;
1329 BestRC = SuperRC;
1330 }
1331 return std::make_pair(BestRC, 1);
1332}
1333
1334/// computeRegisterProperties - Once all of the register classes are added,
1335/// this allows us to compute derived properties we expose.
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1336void TargetLoweringBase::computeRegisterProperties(
1337 const TargetRegisterInfo *TRI) {
Craig Topper6438fc32014-11-17 00:26:50 +0000[diff] [blame]1338 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
1339 "Too many value types for ValueTypeActions to hold!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1340
1341 // Everything defaults to needing one register.
1342 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1343 NumRegistersForVT[i] = 1;
1344 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1345 }
1346 // ...except isVoid, which doesn't need any registers.
1347 NumRegistersForVT[MVT::isVoid] = 0;
1348
1349 // Find the largest integer register class.
1350 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]1351 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1352 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1353
1354 // Every integer value type larger than this largest register takes twice as
1355 // many registers to represent as the previous ValueType.
1356 for (unsigned ExpandedReg = LargestIntReg + 1;
1357 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1358 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1359 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1360 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1361 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1362 TypeExpandInteger);
1363 }
1364
1365 // Inspect all of the ValueType's smaller than the largest integer
1366 // register to see which ones need promotion.
1367 unsigned LegalIntReg = LargestIntReg;
1368 for (unsigned IntReg = LargestIntReg - 1;
1369 IntReg >= (unsigned)MVT::i1; --IntReg) {
1370 MVT IVT = (MVT::SimpleValueType)IntReg;
1371 if (isTypeLegal(IVT)) {
1372 LegalIntReg = IntReg;
1373 } else {
1374 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1375 (const MVT::SimpleValueType)LegalIntReg;
1376 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1377 }
1378 }
1379
1380 // ppcf128 type is really two f64's.
1381 if (!isTypeLegal(MVT::ppcf128)) {
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]1382 if (isTypeLegal(MVT::f64)) {
1383 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1384 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1385 TransformToType[MVT::ppcf128] = MVT::f64;
1386 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1387 } else {
1388 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1389 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1390 TransformToType[MVT::ppcf128] = MVT::i128;
1391 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1392 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1393 }
1394
Akira Hatanaka3d055582013-03-01 21:11:44 +0000[diff] [blame]1395 // Decide how to handle f128. If the target does not have native f128 support,
1396 // expand it to i128 and we will be generating soft float library calls.
1397 if (!isTypeLegal(MVT::f128)) {
1398 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1399 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1400 TransformToType[MVT::f128] = MVT::i128;
1401 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1402 }
1403
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1404 // Decide how to handle f64. If the target does not have native f64 support,
1405 // expand it to i64 and we will be generating soft float library calls.
1406 if (!isTypeLegal(MVT::f64)) {
1407 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1408 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1409 TransformToType[MVT::f64] = MVT::i64;
1410 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1411 }
1412
Ahmed Bougachaa0f35592015-03-28 01:22:37 +0000[diff] [blame]1413 // Decide how to handle f32. If the target does not have native f32 support,
1414 // expand it to i32 and we will be generating soft float library calls.
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1415 if (!isTypeLegal(MVT::f32)) {
Ahmed Bougachaa0f35592015-03-28 01:22:37 +0000[diff] [blame]1416 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1417 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1418 TransformToType[MVT::f32] = MVT::i32;
1419 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1420 }
1421
Oliver Stannard56358572015-11-09 11:03:18 +0000[diff] [blame]1422 // Decide how to handle f16. If the target does not have native f16 support,
1423 // promote it to f32, because there are no f16 library calls (except for
1424 // conversions).
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1425 if (!isTypeLegal(MVT::f16)) {
Oliver Stannard56358572015-11-09 11:03:18 +0000[diff] [blame]1426 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1427 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1428 TransformToType[MVT::f16] = MVT::f32;
1429 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1430 }
1431
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1432 // Loop over all of the vector value types to see which need transformations.
1433 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1434 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1435 MVT VT = (MVT::SimpleValueType) i;
1436 if (isTypeLegal(VT))
1437 continue;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1438
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1439 MVT EltVT = VT.getVectorElementType();
1440 unsigned NElts = VT.getVectorNumElements();
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1441 bool IsLegalWiderType = false;
1442 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1443 switch (PreferredAction) {
1444 case TypePromoteInteger: {
1445 // Try to promote the elements of integer vectors. If no legal
1446 // promotion was found, fall through to the widen-vector method.
Matt Arsenault940d19a2016-04-22 21:16:17 +0000[diff] [blame]1447 for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) {
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1448 MVT SVT = (MVT::SimpleValueType) nVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1449 // Promote vectors of integers to vectors with the same number
1450 // of elements, with a wider element type.
Sanjay Patel1ed771f2016-09-14 16:37:15 +0000[diff] [blame]1451 if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() &&
Matt Arsenault940d19a2016-04-22 21:16:17 +0000[diff] [blame]1452 SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1453 TransformToType[i] = SVT;
1454 RegisterTypeForVT[i] = SVT;
1455 NumRegistersForVT[i] = 1;
1456 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1457 IsLegalWiderType = true;
1458 break;
1459 }
1460 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1461 if (IsLegalWiderType)
1462 break;
Galina Kistanovabd79f732017-06-03 05:11:14 +0000[diff] [blame]1463 LLVM_FALLTHROUGH;
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1464 }
1465 case TypeWidenVector: {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1466 // Try to widen the vector.
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1467 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1468 MVT SVT = (MVT::SimpleValueType) nVT;
1469 if (SVT.getVectorElementType() == EltVT
1470 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1471 TransformToType[i] = SVT;
1472 RegisterTypeForVT[i] = SVT;
1473 NumRegistersForVT[i] = 1;
1474 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1475 IsLegalWiderType = true;
1476 break;
1477 }
1478 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1479 if (IsLegalWiderType)
1480 break;
Galina Kistanovabd79f732017-06-03 05:11:14 +0000[diff] [blame]1481 LLVM_FALLTHROUGH;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1482 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1483 case TypeSplitVector:
1484 case TypeScalarizeVector: {
1485 MVT IntermediateVT;
1486 MVT RegisterVT;
1487 unsigned NumIntermediates;
1488 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1489 NumIntermediates, RegisterVT, this);
1490 RegisterTypeForVT[i] = RegisterVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1491
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1492 MVT NVT = VT.getPow2VectorType();
1493 if (NVT == VT) {
1494 // Type is already a power of 2. The default action is to split.
1495 TransformToType[i] = MVT::Other;
1496 if (PreferredAction == TypeScalarizeVector)
1497 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1498 else if (PreferredAction == TypeSplitVector)
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1499 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1500 else
1501 // Set type action according to the number of elements.
1502 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
1503 : TypeSplitVector);
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1504 } else {
1505 TransformToType[i] = NVT;
1506 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1507 }
1508 break;
1509 }
1510 default:
1511 llvm_unreachable("Unknown vector legalization action!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1512 }
1513 }
1514
1515 // Determine the 'representative' register class for each value type.
1516 // An representative register class is the largest (meaning one which is
1517 // not a sub-register class / subreg register class) legal register class for
1518 // a group of value types. For example, on i386, i8, i16, and i32
1519 // representative would be GR32; while on x86_64 it's GR64.
1520 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1521 const TargetRegisterClass* RRC;
1522 uint8_t Cost;
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1523 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1524 RepRegClassForVT[i] = RRC;
1525 RepRegClassCostForVT[i] = Cost;
1526 }
1527}
1528
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1529EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1530 EVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1531 assert(!VT.isVector() && "No default SetCC type for vectors!");
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1532 return getPointerTy(DL).SimpleTy;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1533}
1534
1535MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1536 return MVT::i32; // return the default value
1537}
1538
1539/// getVectorTypeBreakdown - Vector types are broken down into some number of
1540/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1541/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1542/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1543///
1544/// This method returns the number of registers needed, and the VT for each
1545/// register. It also returns the VT and quantity of the intermediate values
1546/// before they are promoted/expanded.
1547///
1548unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1549 EVT &IntermediateVT,
1550 unsigned &NumIntermediates,
1551 MVT &RegisterVT) const {
1552 unsigned NumElts = VT.getVectorNumElements();
1553
1554 // If there is a wider vector type with the same element type as this one,
1555 // or a promoted vector type that has the same number of elements which
1556 // are wider, then we should convert to that legal vector type.
1557 // This handles things like <2 x float> -> <4 x float> and
1558 // <4 x i1> -> <4 x i32>.
1559 LegalizeTypeAction TA = getTypeAction(Context, VT);
1560 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1561 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1562 if (isTypeLegal(RegisterEVT)) {
1563 IntermediateVT = RegisterEVT;
1564 RegisterVT = RegisterEVT.getSimpleVT();
1565 NumIntermediates = 1;
1566 return 1;
1567 }
1568 }
1569
1570 // Figure out the right, legal destination reg to copy into.
1571 EVT EltTy = VT.getVectorElementType();
1572
1573 unsigned NumVectorRegs = 1;
1574
1575 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1576 // could break down into LHS/RHS like LegalizeDAG does.
1577 if (!isPowerOf2_32(NumElts)) {
1578 NumVectorRegs = NumElts;
1579 NumElts = 1;
1580 }
1581
1582 // Divide the input until we get to a supported size. This will always
1583 // end with a scalar if the target doesn't support vectors.
1584 while (NumElts > 1 && !isTypeLegal(
1585 EVT::getVectorVT(Context, EltTy, NumElts))) {
1586 NumElts >>= 1;
1587 NumVectorRegs <<= 1;
1588 }
1589
1590 NumIntermediates = NumVectorRegs;
1591
1592 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1593 if (!isTypeLegal(NewVT))
1594 NewVT = EltTy;
1595 IntermediateVT = NewVT;
1596
1597 MVT DestVT = getRegisterType(Context, NewVT);
1598 RegisterVT = DestVT;
1599 unsigned NewVTSize = NewVT.getSizeInBits();
1600
1601 // Convert sizes such as i33 to i64.
1602 if (!isPowerOf2_32(NewVTSize))
1603 NewVTSize = NextPowerOf2(NewVTSize);
1604
1605 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1606 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1607
1608 // Otherwise, promotion or legal types use the same number of registers as
1609 // the vector decimated to the appropriate level.
1610 return NumVectorRegs;
1611}
1612
1613/// Get the EVTs and ArgFlags collections that represent the legalized return
1614/// type of the given function. This does not require a DAG or a return value,
1615/// and is suitable for use before any DAGs for the function are constructed.
1616/// TODO: Move this out of TargetLowering.cpp.
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1617void llvm::GetReturnInfo(Type *ReturnType, AttributeList attr,
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1618 SmallVectorImpl<ISD::OutputArg> &Outs,
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame]1619 const TargetLowering &TLI, const DataLayout &DL) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1620 SmallVector<EVT, 4> ValueVTs;
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame]1621 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1622 unsigned NumValues = ValueVTs.size();
1623 if (NumValues == 0) return;
1624
1625 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1626 EVT VT = ValueVTs[j];
1627 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1628
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1629 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1630 ExtendKind = ISD::SIGN_EXTEND;
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1631 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1632 ExtendKind = ISD::ZERO_EXTEND;
1633
1634 // FIXME: C calling convention requires the return type to be promoted to
1635 // at least 32-bit. But this is not necessary for non-C calling
1636 // conventions. The frontend should mark functions whose return values
1637 // require promoting with signext or zeroext attributes.
1638 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1639 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1640 if (VT.bitsLT(MinVT))
1641 VT = MinVT;
1642 }
1643
Simon Dardis212cccb2017-06-09 14:37:08 +0000[diff] [blame]1644 unsigned NumParts =
1645 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), VT);
1646 MVT PartVT =
1647 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), VT);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1648
1649 // 'inreg' on function refers to return value
1650 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1651 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1652 Flags.setInReg();
1653
1654 // Propagate extension type if any
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1655 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1656 Flags.setSExt();
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1657 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1658 Flags.setZExt();
1659
1660 for (unsigned i = 0; i < NumParts; ++i)
Tom Stellard8d7d4de2013-10-23 00:44:24 +0000[diff] [blame]1661 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1662 }
1663}
1664
1665/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1666/// function arguments in the caller parameter area. This is the actual
1667/// alignment, not its logarithm.
Mehdi Amini5c183d52015-07-09 02:09:28 +0000[diff] [blame]1668unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty,
1669 const DataLayout &DL) const {
1670 return DL.getABITypeAlignment(Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1671}
1672
Sanjay Patel0f9dcf82015-07-29 18:24:18 +0000[diff] [blame]1673bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1674 const DataLayout &DL, EVT VT,
1675 unsigned AddrSpace,
1676 unsigned Alignment,
1677 bool *Fast) const {
1678 // Check if the specified alignment is sufficient based on the data layout.
1679 // TODO: While using the data layout works in practice, a better solution
1680 // would be to implement this check directly (make this a virtual function).
1681 // For example, the ABI alignment may change based on software platform while
1682 // this function should only be affected by hardware implementation.
1683 Type *Ty = VT.getTypeForEVT(Context);
1684 if (Alignment >= DL.getABITypeAlignment(Ty)) {
1685 // Assume that an access that meets the ABI-specified alignment is fast.
1686 if (Fast != nullptr)
1687 *Fast = true;
1688 return true;
1689 }
1690
1691 // This is a misaligned access.
1692 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast);
1693}
1694
Sanjay Pateld66607b2016-04-26 17:11:17 +0000[diff] [blame]1695BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const {
1696 return BranchProbability(MinPercentageForPredictableBranch, 100);
1697}
Sanjay Patel0f9dcf82015-07-29 18:24:18 +0000[diff] [blame]1698
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1699//===----------------------------------------------------------------------===//
1700// TargetTransformInfo Helpers
1701//===----------------------------------------------------------------------===//
1702
1703int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1704 enum InstructionOpcodes {
1705#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1706#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1707#include "llvm/IR/Instruction.def"
1708 };
1709 switch (static_cast<InstructionOpcodes>(Opcode)) {
1710 case Ret: return 0;
1711 case Br: return 0;
1712 case Switch: return 0;
1713 case IndirectBr: return 0;
1714 case Invoke: return 0;
1715 case Resume: return 0;
1716 case Unreachable: return 0;
David Majnemer654e1302015-07-31 17:58:14 +0000[diff] [blame]1717 case CleanupRet: return 0;
David Majnemer654e1302015-07-31 17:58:14 +0000[diff] [blame]1718 case CatchRet: return 0;
David Majnemer8a1c45d2015-12-12 05:38:55 +0000[diff] [blame]1719 case CatchPad: return 0;
1720 case CatchSwitch: return 0;
David Majnemer8a1c45d2015-12-12 05:38:55 +0000[diff] [blame]1721 case CleanupPad: return 0;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1722 case Add: return ISD::ADD;
1723 case FAdd: return ISD::FADD;
1724 case Sub: return ISD::SUB;
1725 case FSub: return ISD::FSUB;
1726 case Mul: return ISD::MUL;
1727 case FMul: return ISD::FMUL;
1728 case UDiv: return ISD::UDIV;
Benjamin Kramerce4b3fe2014-04-27 18:47:54 +0000[diff] [blame]1729 case SDiv: return ISD::SDIV;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1730 case FDiv: return ISD::FDIV;
1731 case URem: return ISD::UREM;
1732 case SRem: return ISD::SREM;
1733 case FRem: return ISD::FREM;
1734 case Shl: return ISD::SHL;
1735 case LShr: return ISD::SRL;
1736 case AShr: return ISD::SRA;
1737 case And: return ISD::AND;
1738 case Or: return ISD::OR;
1739 case Xor: return ISD::XOR;
1740 case Alloca: return 0;
1741 case Load: return ISD::LOAD;
1742 case Store: return ISD::STORE;
1743 case GetElementPtr: return 0;
1744 case Fence: return 0;
1745 case AtomicCmpXchg: return 0;
1746 case AtomicRMW: return 0;
1747 case Trunc: return ISD::TRUNCATE;
1748 case ZExt: return ISD::ZERO_EXTEND;
1749 case SExt: return ISD::SIGN_EXTEND;
1750 case FPToUI: return ISD::FP_TO_UINT;
1751 case FPToSI: return ISD::FP_TO_SINT;
1752 case UIToFP: return ISD::UINT_TO_FP;
1753 case SIToFP: return ISD::SINT_TO_FP;
1754 case FPTrunc: return ISD::FP_ROUND;
1755 case FPExt: return ISD::FP_EXTEND;
1756 case PtrToInt: return ISD::BITCAST;
1757 case IntToPtr: return ISD::BITCAST;
1758 case BitCast: return ISD::BITCAST;
Matt Arsenaultb03bd4d2013-11-15 01:34:59 +0000[diff] [blame]1759 case AddrSpaceCast: return ISD::ADDRSPACECAST;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1760 case ICmp: return ISD::SETCC;
1761 case FCmp: return ISD::SETCC;
1762 case PHI: return 0;
1763 case Call: return 0;
1764 case Select: return ISD::SELECT;
1765 case UserOp1: return 0;
1766 case UserOp2: return 0;
1767 case VAArg: return 0;
1768 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1769 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1770 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1771 case ExtractValue: return ISD::MERGE_VALUES;
1772 case InsertValue: return ISD::MERGE_VALUES;
1773 case LandingPad: return 0;
1774 }
1775
1776 llvm_unreachable("Unknown instruction type encountered!");
1777}
1778
Chandler Carruth93205eb2015-08-05 18:08:10 +0000[diff] [blame]1779std::pair<int, MVT>
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1780TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL,
1781 Type *Ty) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1782 LLVMContext &C = Ty->getContext();
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1783 EVT MTy = getValueType(DL, Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1784
Chandler Carruth93205eb2015-08-05 18:08:10 +0000[diff] [blame]1785 int Cost = 1;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1786 // We keep legalizing the type until we find a legal kind. We assume that
1787 // the only operation that costs anything is the split. After splitting
1788 // we need to handle two types.
1789 while (true) {
1790 LegalizeKind LK = getTypeConversion(C, MTy);
1791
1792 if (LK.first == TypeLegal)
1793 return std::make_pair(Cost, MTy.getSimpleVT());
1794
1795 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1796 Cost *= 2;
1797
Chih-Hung Hsiehed7d81e2015-12-03 22:02:40 +0000[diff] [blame]1798 // Do not loop with f128 type.
1799 if (MTy == LK.second)
1800 return std::make_pair(Cost, MTy.getSimpleVT());
1801
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1802 // Keep legalizing the type.
1803 MTy = LK.second;
1804 }
1805}
1806
David L Kreitzerd5c67552016-10-14 17:56:00 +0000[diff] [blame]1807Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1808 bool UseTLS) const {
1809 // compiler-rt provides a variable with a magic name. Targets that do not
1810 // link with compiler-rt may also provide such a variable.
1811 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1812 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1813 auto UnsafeStackPtr =
1814 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1815
1816 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1817
1818 if (!UnsafeStackPtr) {
1819 auto TLSModel = UseTLS ?
1820 GlobalValue::InitialExecTLSModel :
1821 GlobalValue::NotThreadLocal;
1822 // The global variable is not defined yet, define it ourselves.
1823 // We use the initial-exec TLS model because we do not support the
1824 // variable living anywhere other than in the main executable.
1825 UnsafeStackPtr = new GlobalVariable(
1826 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1827 UnsafeStackPtrVar, nullptr, TLSModel);
1828 } else {
1829 // The variable exists, check its type and attributes.
1830 if (UnsafeStackPtr->getValueType() != StackPtrTy)
1831 report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1832 if (UseTLS != UnsafeStackPtr->isThreadLocal())
1833 report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1834 (UseTLS ? "" : "not ") + "be thread-local");
1835 }
1836 return UnsafeStackPtr;
1837}
1838
Evgeniy Stepanovd1aad262015-10-26 18:28:25 +0000[diff] [blame]1839Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
1840 if (!TM.getTargetTriple().isAndroid())
David L Kreitzerd5c67552016-10-14 17:56:00 +0000[diff] [blame]1841 return getDefaultSafeStackPointerLocation(IRB, true);
Evgeniy Stepanovd1aad262015-10-26 18:28:25 +0000[diff] [blame]1842
1843 // Android provides a libc function to retrieve the address of the current
1844 // thread's unsafe stack pointer.
1845 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1846 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1847 Value *Fn = M->getOrInsertFunction("__safestack_pointer_address",
Serge Guelton59a2d7b2017-04-11 15:01:18 +0000[diff] [blame]1848 StackPtrTy->getPointerTo(0));
Evgeniy Stepanovd1aad262015-10-26 18:28:25 +0000[diff] [blame]1849 return IRB.CreateCall(Fn);
1850}
1851
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1852//===----------------------------------------------------------------------===//
1853// Loop Strength Reduction hooks
1854//===----------------------------------------------------------------------===//
1855
1856/// isLegalAddressingMode - Return true if the addressing mode represented
1857/// by AM is legal for this target, for a load/store of the specified type.
Mehdi Amini0cdec1e2015-07-09 02:09:40 +0000[diff] [blame]1858bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
1859 const AddrMode &AM, Type *Ty,
Matt Arsenaultbd7d80a2015-06-01 05:31:59 +0000[diff] [blame]1860 unsigned AS) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1861 // The default implementation of this implements a conservative RISCy, r+r and
1862 // r+i addr mode.
1863
1864 // Allows a sign-extended 16-bit immediate field.
1865 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1866 return false;
1867
1868 // No global is ever allowed as a base.
1869 if (AM.BaseGV)
1870 return false;
1871
1872 // Only support r+r,
1873 switch (AM.Scale) {
1874 case 0: // "r+i" or just "i", depending on HasBaseReg.
1875 break;
1876 case 1:
1877 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1878 return false;
1879 // Otherwise we have r+r or r+i.
1880 break;
1881 case 2:
1882 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1883 return false;
1884 // Allow 2*r as r+r.
1885 break;
Tom Stellard728d4172014-02-14 21:10:34 +0000[diff] [blame]1886 default: // Don't allow n * r
1887 return false;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1888 }
1889
1890 return true;
1891}
Tim Shen00127562016-04-08 21:26:31 +0000[diff] [blame]1892
1893//===----------------------------------------------------------------------===//
1894// Stack Protector
1895//===----------------------------------------------------------------------===//
1896
1897// For OpenBSD return its special guard variable. Otherwise return nullptr,
1898// so that SelectionDAG handle SSP.
1899Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const {
1900 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1901 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1902 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
Tim Shena5cc25e2016-08-22 18:26:27 +0000[diff] [blame]1903 return M.getOrInsertGlobal("__guard_local", PtrTy);
Tim Shen00127562016-04-08 21:26:31 +0000[diff] [blame]1904 }
1905 return nullptr;
1906}
1907
1908// Currently only support "standard" __stack_chk_guard.
1909// TODO: add LOAD_STACK_GUARD support.
1910void TargetLoweringBase::insertSSPDeclarations(Module &M) const {
1911 M.getOrInsertGlobal("__stack_chk_guard", Type::getInt8PtrTy(M.getContext()));
1912}
1913
1914// Currently only support "standard" __stack_chk_guard.
1915// TODO: add LOAD_STACK_GUARD support.
Tim Shena1d8bc52016-04-19 20:14:52 +0000[diff] [blame]1916Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const {
Davide Italianobd4243c2016-06-09 14:23:38 +0000[diff] [blame]1917 return M.getGlobalVariable("__stack_chk_guard", true);
Tim Shen00127562016-04-08 21:26:31 +0000[diff] [blame]1918}
Etienne Bergeron22bfa832016-06-07 20:15:35 +0000[diff] [blame]1919
1920Value *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const {
1921 return nullptr;
1922}
Evandro Menezese45de8a2016-09-26 15:32:33 +0000[diff] [blame]1923
Evandro Menezeseb97e352016-10-25 19:53:51 +0000[diff] [blame]1924unsigned TargetLoweringBase::getMinimumJumpTableEntries() const {
1925 return MinimumJumpTableEntries;
1926}
1927
1928void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) {
1929 MinimumJumpTableEntries = Val;
1930}
1931
Jun Bum Lim919f9e82017-04-28 16:04:03 +0000[diff] [blame]1932unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1933 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1934}
1935
Evandro Menezese45de8a2016-09-26 15:32:33 +0000[diff] [blame]1936unsigned TargetLoweringBase::getMaximumJumpTableSize() const {
1937 return MaximumJumpTableSize;
1938}
1939
1940void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) {
1941 MaximumJumpTableSize = Val;
1942}
Sanjay Patel0051efc2016-10-20 16:55:45 +0000[diff] [blame]1943
1944//===----------------------------------------------------------------------===//
1945// Reciprocal Estimates
1946//===----------------------------------------------------------------------===//
1947
1948/// Get the reciprocal estimate attribute string for a function that will
1949/// override the target defaults.
1950static StringRef getRecipEstimateForFunc(MachineFunction &MF) {
1951 const Function *F = MF.getFunction();
David Majnemere0ebdf42017-01-13 22:24:25 +0000[diff] [blame]1952 return F->getFnAttribute("reciprocal-estimates").getValueAsString();
Sanjay Patel0051efc2016-10-20 16:55:45 +0000[diff] [blame]1953}
1954
1955/// Construct a string for the given reciprocal operation of the given type.
1956/// This string should match the corresponding option to the front-end's
1957/// "-mrecip" flag assuming those strings have been passed through in an
1958/// attribute string. For example, "vec-divf" for a division of a vXf32.
1959static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
1960 std::string Name = VT.isVector() ? "vec-" : "";
1961
1962 Name += IsSqrt ? "sqrt" : "div";
1963
1964 // TODO: Handle "half" or other float types?
1965 if (VT.getScalarType() == MVT::f64) {
1966 Name += "d";
1967 } else {
1968 assert(VT.getScalarType() == MVT::f32 &&
1969 "Unexpected FP type for reciprocal estimate");
1970 Name += "f";
1971 }
1972
1973 return Name;
1974}
1975
1976/// Return the character position and value (a single numeric character) of a
1977/// customized refinement operation in the input string if it exists. Return
1978/// false if there is no customized refinement step count.
1979static bool parseRefinementStep(StringRef In, size_t &Position,
1980 uint8_t &Value) {
1981 const char RefStepToken = ':';
1982 Position = In.find(RefStepToken);
1983 if (Position == StringRef::npos)
1984 return false;
1985
1986 StringRef RefStepString = In.substr(Position + 1);
1987 // Allow exactly one numeric character for the additional refinement
1988 // step parameter.
1989 if (RefStepString.size() == 1) {
1990 char RefStepChar = RefStepString[0];
1991 if (RefStepChar >= '0' && RefStepChar <= '9') {
1992 Value = RefStepChar - '0';
1993 return true;
1994 }
1995 }
1996 report_fatal_error("Invalid refinement step for -recip.");
1997}
1998
1999/// For the input attribute string, return one of the ReciprocalEstimate enum
2000/// status values (enabled, disabled, or not specified) for this operation on
2001/// the specified data type.
2002static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2003 if (Override.empty())
2004 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2005
2006 SmallVector<StringRef, 4> OverrideVector;
2007 SplitString(Override, OverrideVector, ",");
2008 unsigned NumArgs = OverrideVector.size();
2009
2010 // Check if "all", "none", or "default" was specified.
2011 if (NumArgs == 1) {
2012 // Look for an optional setting of the number of refinement steps needed
2013 // for this type of reciprocal operation.
2014 size_t RefPos;
2015 uint8_t RefSteps;
2016 if (parseRefinementStep(Override, RefPos, RefSteps)) {
2017 // Split the string for further processing.
2018 Override = Override.substr(0, RefPos);
2019 }
2020
2021 // All reciprocal types are enabled.
2022 if (Override == "all")
2023 return TargetLoweringBase::ReciprocalEstimate::Enabled;
2024
2025 // All reciprocal types are disabled.
2026 if (Override == "none")
2027 return TargetLoweringBase::ReciprocalEstimate::Disabled;
2028
2029 // Target defaults for enablement are used.
2030 if (Override == "default")
2031 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2032 }
2033
2034 // The attribute string may omit the size suffix ('f'/'d').
2035 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2036 std::string VTNameNoSize = VTName;
Sanjay Patel501be9b2016-10-21 14:58:30 +0000[diff] [blame]2037 VTNameNoSize.pop_back();
Sanjay Patel0051efc2016-10-20 16:55:45 +0000[diff] [blame]2038 static const char DisabledPrefix = '!';
2039
2040 for (StringRef RecipType : OverrideVector) {
2041 size_t RefPos;
2042 uint8_t RefSteps;
2043 if (parseRefinementStep(RecipType, RefPos, RefSteps))
2044 RecipType = RecipType.substr(0, RefPos);
2045
2046 // Ignore the disablement token for string matching.
2047 bool IsDisabled = RecipType[0] == DisabledPrefix;
2048 if (IsDisabled)
2049 RecipType = RecipType.substr(1);
2050
2051 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2052 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
2053 : TargetLoweringBase::ReciprocalEstimate::Enabled;
2054 }
2055
2056 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2057}
2058
2059/// For the input attribute string, return the customized refinement step count
2060/// for this operation on the specified data type. If the step count does not
2061/// exist, return the ReciprocalEstimate enum value for unspecified.
2062static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2063 if (Override.empty())
2064 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2065
2066 SmallVector<StringRef, 4> OverrideVector;
2067 SplitString(Override, OverrideVector, ",");
2068 unsigned NumArgs = OverrideVector.size();
2069
2070 // Check if "all", "default", or "none" was specified.
2071 if (NumArgs == 1) {
2072 // Look for an optional setting of the number of refinement steps needed
2073 // for this type of reciprocal operation.
2074 size_t RefPos;
2075 uint8_t RefSteps;
2076 if (!parseRefinementStep(Override, RefPos, RefSteps))
2077 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2078
2079 // Split the string for further processing.
2080 Override = Override.substr(0, RefPos);
2081 assert(Override != "none" &&
2082 "Disabled reciprocals, but specifed refinement steps?");
2083
2084 // If this is a general override, return the specified number of steps.
2085 if (Override == "all" || Override == "default")
2086 return RefSteps;
2087 }
2088
2089 // The attribute string may omit the size suffix ('f'/'d').
2090 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2091 std::string VTNameNoSize = VTName;
Sanjay Patel501be9b2016-10-21 14:58:30 +0000[diff] [blame]2092 VTNameNoSize.pop_back();
Sanjay Patel0051efc2016-10-20 16:55:45 +0000[diff] [blame]2093
2094 for (StringRef RecipType : OverrideVector) {
2095 size_t RefPos;
2096 uint8_t RefSteps;
2097 if (!parseRefinementStep(RecipType, RefPos, RefSteps))
2098 continue;
2099
2100 RecipType = RecipType.substr(0, RefPos);
2101 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2102 return RefSteps;
2103 }
2104
2105 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2106}
2107
2108int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT,
2109 MachineFunction &MF) const {
2110 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
2111}
2112
2113int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT,
2114 MachineFunction &MF) const {
2115 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
2116}
2117
2118int TargetLoweringBase::getSqrtRefinementSteps(EVT VT,
2119 MachineFunction &MF) const {
2120 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
2121}
2122
2123int TargetLoweringBase::getDivRefinementSteps(EVT VT,
2124 MachineFunction &MF) const {
2125 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
2126}
Matthias Braun744c2152017-04-28 20:25:05 +0000[diff] [blame]2127
2128void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const {
2129 MF.getRegInfo().freezeReservedRegs(MF);
2130}