Blame - llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp - toolchain/llvm-project

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Jia Liu	b22310f	2012-02-18 12:03:15 +0000	[diff] [blame]	1	//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	9
				10	#define DEBUG_TYPE "arm-disassembler"
				11
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	12	#include "llvm/MC/MCDisassembler.h"
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	13	#include "MCTargetDesc/ARMAddressingModes.h"
				14	#include "MCTargetDesc/ARMBaseInfo.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	15	#include "MCTargetDesc/ARMMCExpr.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	16	#include "llvm/MC/MCContext.h"
				17	#include "llvm/MC/MCExpr.h"
				18	#include "llvm/MC/MCFixedLenDisassembler.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	19	#include "llvm/MC/MCInst.h"
Benjamin Kramer	48b5bbf	2011-11-11 12:39:41 +0000	[diff] [blame]	20	#include "llvm/MC/MCInstrDesc.h"
Dylan Noblesmith	7a3973d	2012-04-03 15:48:14 +0000	[diff] [blame]	21	#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	22	#include "llvm/Support/Debug.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	23	#include "llvm/Support/ErrorHandling.h"
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	24	#include "llvm/Support/LEB128.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	25	#include "llvm/Support/MemoryObject.h"
Evan Cheng	2bb4035	2011-08-24 18:08:43 +0000	[diff] [blame]	26	#include "llvm/Support/TargetRegistry.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	27	#include "llvm/Support/raw_ostream.h"
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	28	#include <vector>
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	29
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	30	using namespace llvm;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	31
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	32	typedef MCDisassembler::DecodeStatus DecodeStatus;
				33
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	34	namespace {
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	35	// Handles the condition code status of instructions in IT blocks
				36	class ITStatus
				37	{
				38	public:
				39	// Returns the condition code for instruction in IT block
				40	unsigned getITCC() {
				41	unsigned CC = ARMCC::AL;
				42	if (instrInITBlock())
				43	CC = ITStates.back();
				44	return CC;
				45	}
				46
				47	// Advances the IT block state to the next T or E
				48	void advanceITState() {
				49	ITStates.pop_back();
				50	}
				51
				52	// Returns true if the current instruction is in an IT block
				53	bool instrInITBlock() {
				54	return !ITStates.empty();
				55	}
				56
				57	// Returns true if current instruction is the last instruction in an IT block
				58	bool instrLastInITBlock() {
				59	return ITStates.size() == 1;
				60	}
				61
				62	// Called when decoding an IT instruction. Sets the IT state for the following
				63	// instructions that for the IT block. Firstcond and Mask correspond to the
				64	// fields in the IT instruction encoding.
				65	void setITState(char Firstcond, char Mask) {
				66	// (3 - the number of trailing zeros) is the number of then / else.
Richard Barton	f435b09	2012-04-27 08:42:59 +0000	[diff] [blame]	67	unsigned CondBit0 = Firstcond & 1;
Michael J. Spencer	df1ecbd7	2013-05-24 22:23:49 +0000	[diff] [blame]	68	unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	69	unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
				70	assert(NumTZ <= 3 && "Invalid IT mask!");
				71	// push condition codes onto the stack the correct order for the pops
				72	for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
				73	bool T = ((Mask >> Pos) & 1) == CondBit0;
				74	if (T)
				75	ITStates.push_back(CCBits);
				76	else
				77	ITStates.push_back(CCBits ^ 1);
				78	}
				79	ITStates.push_back(CCBits);
				80	}
				81
				82	private:
				83	std::vector<unsigned char> ITStates;
				84	};
				85	}
				86
				87	namespace {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	88	/// ARMDisassembler - ARM disassembler for all ARM platforms.
				89	class ARMDisassembler : public MCDisassembler {
				90	public:
				91	/// Constructor - Initializes the disassembler.
				92	///
James Molloy	4c493e8	2011-09-07 17:24:38 +0000	[diff] [blame]	93	ARMDisassembler(const MCSubtargetInfo &STI) :
				94	MCDisassembler(STI) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	95	}
				96
				97	~ARMDisassembler() {
				98	}
				99
				100	/// getInstruction - See MCDisassembler.
				101	DecodeStatus getInstruction(MCInst &instr,
				102	uint64_t &size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	103	const MemoryObject &region,
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	104	uint64_t address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	105	raw_ostream &vStream,
				106	raw_ostream &cStream) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	107	};
				108
				109	/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
				110	class ThumbDisassembler : public MCDisassembler {
				111	public:
				112	/// Constructor - Initializes the disassembler.
				113	///
James Molloy	4c493e8	2011-09-07 17:24:38 +0000	[diff] [blame]	114	ThumbDisassembler(const MCSubtargetInfo &STI) :
				115	MCDisassembler(STI) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	116	}
				117
				118	~ThumbDisassembler() {
				119	}
				120
				121	/// getInstruction - See MCDisassembler.
				122	DecodeStatus getInstruction(MCInst &instr,
				123	uint64_t &size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	124	const MemoryObject &region,
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	125	uint64_t address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	126	raw_ostream &vStream,
				127	raw_ostream &cStream) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	128
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	129	private:
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	130	mutable ITStatus ITBlock;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	131	DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	132	void UpdateThumbVFPPredicate(MCInst&) const;
				133	};
				134	}
				135
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	136	static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	137	switch (In) {
				138	case MCDisassembler::Success:
				139	// Out stays the same.
				140	return true;
				141	case MCDisassembler::SoftFail:
				142	Out = In;
				143	return true;
				144	case MCDisassembler::Fail:
				145	Out = In;
				146	return false;
				147	}
David Blaikie	46a9f01	2012-01-20 21:51:11 +0000	[diff] [blame]	148	llvm_unreachable("Invalid DecodeStatus!");
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	149	}
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	150
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	151
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	152	// Forward declare these because the autogenerated code will reference them.
				153	// Definitions are further down.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	154	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	155	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	156	static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	157	unsigned RegNo, uint64_t Address,
				158	const void *Decoder);
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	159	static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
				160	unsigned RegNo, uint64_t Address,
				161	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	162	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	163	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	164	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	165	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	166	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	167	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	168	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	169	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	170	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	171	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	172	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	173	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	174	static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	175	unsigned RegNo,
				176	uint64_t Address,
				177	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	178	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	179	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	180	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	181	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	182	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	183	unsigned RegNo, uint64_t Address,
				184	const void *Decoder);
Johnny Chen	74491bb	2010-08-12 01:40:54 +0000	[diff] [blame]	185
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	186	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	187	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	188	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	189	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	190	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	191	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	192	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	193	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	194	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	195	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	196	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	197	uint64_t Address, const void *Decoder);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	198
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	199	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	200	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	201	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	202	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	203	static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	204	unsigned Insn,
				205	uint64_t Address,
				206	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	207	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	208	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	209	static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	210	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	211	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	212	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	213	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	214	uint64_t Address, const void *Decoder);
				215
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	216	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	217	unsigned Insn,
				218	uint64_t Adddress,
				219	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	220	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	221	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	222	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	223	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	224	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	225	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	226	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	227	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	228	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	229	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	230	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	231	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	232	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	233	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	234	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	235	uint64_t Address, const void *Decoder);
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	236	static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				237	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	238	static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	239	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	240	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	241	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	242	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	243	uint64_t Address, const void *Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	244	static DecodeStatus DecodeVST1Instruction(MCInst &Inst, unsigned Val,
				245	uint64_t Address, const void *Decoder);
				246	static DecodeStatus DecodeVST2Instruction(MCInst &Inst, unsigned Val,
				247	uint64_t Address, const void *Decoder);
				248	static DecodeStatus DecodeVST3Instruction(MCInst &Inst, unsigned Val,
				249	uint64_t Address, const void *Decoder);
				250	static DecodeStatus DecodeVST4Instruction(MCInst &Inst, unsigned Val,
				251	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	252	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	253	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	254	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	255	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	256	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	257	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	258	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	259	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	260	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	261	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	262	static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	263	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	264	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	265	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	266	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	267	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	268	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	269	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	270	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	271	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	272	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	273	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	274	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	275	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	276	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	277	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	278	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	279	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	280	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	281	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame^]	282	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
				283	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	284	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	285	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	286	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	287	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	288	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	289	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	290	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	291	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	292	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	293	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	294	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	295	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	296	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	297	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	298	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	299	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	300	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	301	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	302	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	303	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	304	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	305	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	306	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	307	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	308	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	309	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	310	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	311	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	312	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	313	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	314	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	315	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	316	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	317	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	318	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	319	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	320	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	321	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	322	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	323	uint64_t Address, const void *Decoder);
Quentin Colombet	6f03f62	2013-04-17 18:46:12 +0000	[diff] [blame]	324	static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
				325	const void *Decoder);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	326
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	327
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	328	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	329	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	330	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	331	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	332	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	333	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	334	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	335	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	336	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	337	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	338	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	339	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	340	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	341	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	342	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	343	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	344	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	345	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	346	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	347	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	348	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	349	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	350	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	351	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	352	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	353	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	354	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	355	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	356	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	357	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	358	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	359	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	360	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	361	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	362	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	363	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	364	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				365	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	366	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	367	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	368	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	369	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	370	static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	371	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	372	static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	373	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	374	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	375	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	376	static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	377	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	378	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	379	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	380	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	381	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	382	static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	383	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	384	static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	385	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	386	static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	387	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	388	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	389	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	390	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	391	uint64_t Address, const void *Decoder);
				392
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	393	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	394	uint64_t Address, const void *Decoder);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	395	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				396	uint64_t Address, const void *Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	397	#include "ARMGenDisassemblerTables.inc"
Sean Callanan	814e69b	2010-04-13 21:21:57 +0000	[diff] [blame]	398
James Molloy	4c493e8	2011-09-07 17:24:38 +0000	[diff] [blame]	399	static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				400	return new ARMDisassembler(STI);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	401	}
				402
James Molloy	4c493e8	2011-09-07 17:24:38 +0000	[diff] [blame]	403	static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				404	return new ThumbDisassembler(STI);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	405	}
				406
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	407	DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	408	const MemoryObject &Region,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	409	uint64_t Address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	410	raw_ostream &os,
				411	raw_ostream &cs) const {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	412	CommentStream = &cs;
				413
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	414	uint8_t bytes[4];
				415
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	416	assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
				417	"Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
				418
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	419	// We want to read exactly 4 bytes of data.
Benjamin Kramer	534d3a4	2013-05-24 10:54:58 +0000	[diff] [blame]	420	if (Region.readBytes(Address, 4, bytes) == -1) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	421	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	422	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	423	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	424
				425	// Encoded as a small-endian 32-bit word in the stream.
				426	uint32_t insn = (bytes[3] << 24) \|
				427	(bytes[2] << 16) \|
				428	(bytes[1] << 8) \|
				429	(bytes[0] << 0);
				430
				431	// Calling the auto-generated decoder function.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	432	DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
				433	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	434	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	435	Size = 4;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	436	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	437	}
				438
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	439	// VFP and NEON instructions, similarly, are shared between ARM
				440	// and Thumb modes.
				441	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	442	result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	443	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	444	Size = 4;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	445	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	446	}
				447
				448	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	449	result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
				450	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	451	if (result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	452	Size = 4;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	453	// Add a fake predicate operand, because we share these instruction
				454	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	455	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				456	return MCDisassembler::Fail;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	457	return result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	458	}
				459
				460	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	461	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
				462	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	463	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	464	Size = 4;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	465	// Add a fake predicate operand, because we share these instruction
				466	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	467	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				468	return MCDisassembler::Fail;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	469	return result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	470	}
				471
				472	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	473	result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
				474	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	475	if (result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	476	Size = 4;
				477	// Add a fake predicate operand, because we share these instruction
				478	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	479	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				480	return MCDisassembler::Fail;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	481	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	482	}
				483
				484	MI.clear();
				485
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	486	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	487	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	488	}
				489
				490	namespace llvm {
Benjamin Kramer	0d6d098	2011-10-22 16:50:00 +0000	[diff] [blame]	491	extern const MCInstrDesc ARMInsts[];
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	492	}
				493
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	494	/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
				495	/// immediate Value in the MCInst. The immediate Value has had any PC
				496	/// adjustment made by the caller. If the instruction is a branch instruction
				497	/// then isBranch is true, else false. If the getOpInfo() function was set as
				498	/// part of the setupForSymbolicDisassembly() call then that function is called
				499	/// to get any symbolic information at the Address for this instruction. If
				500	/// that returns non-zero then the symbolic information it returns is used to
				501	/// create an MCExpr and that is added as an operand to the MCInst. If
				502	/// getOpInfo() returns zero and isBranch is true then a symbol look up for
				503	/// Value is done and if a symbol is found an MCExpr is created with that, else
				504	/// an MCExpr with Value is created. This function returns true if it adds an
				505	/// operand to the MCInst and false otherwise.
				506	static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
				507	bool isBranch, uint64_t InstSize,
				508	MCInst &MI, const void *Decoder) {
				509	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	510	// FIXME: Does it make sense for value to be negative?
				511	return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
				512	/* Offset */ 0, InstSize);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	513	}
				514
				515	/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
				516	/// referenced by a load instruction with the base register that is the Pc.
				517	/// These can often be values in a literal pool near the Address of the
				518	/// instruction. The Address of the instruction and its immediate Value are
				519	/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledru	35521e2	2012-07-23 08:51:15 +0000	[diff] [blame]	520	/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	521	/// the referenced address is that of a symbol. Or it will return a pointer to
				522	/// a literal 'C' string if the referenced address of the literal pool's entry
				523	/// is an address into a section with 'C' string literals.
				524	static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	525	const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	526	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	527	Dis->tryAddingPcLoadReferenceComment(Value, Address);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	528	}
				529
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	530	// Thumb1 instructions don't have explicit S bits. Rather, they
				531	// implicitly set CPSR. Since it's not represented in the encoding, the
				532	// auto-generated decoder won't inject the CPSR operand. We need to fix
				533	// that as a post-pass.
				534	static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
				535	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	536	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	537	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	538	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				539	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	540	if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	541	if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	542	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
				543	return;
				544	}
				545	}
				546
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	547	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	548	}
				549
				550	// Most Thumb instructions don't have explicit predicates in the
				551	// encoding, but rather get their predicates from IT context. We need
				552	// to fix up the predicate operands using this context information as a
				553	// post-pass.
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	554	MCDisassembler::DecodeStatus
				555	ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	556	MCDisassembler::DecodeStatus S = Success;
				557
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	558	// A few instructions actually have predicates encoded in them. Don't
				559	// try to overwrite it if we're seeing one of those.
				560	switch (MI.getOpcode()) {
				561	case ARM::tBcc:
				562	case ARM::t2Bcc:
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	563	case ARM::tCBZ:
				564	case ARM::tCBNZ:
Owen Anderson	61e4604	2011-09-19 23:47:10 +0000	[diff] [blame]	565	case ARM::tCPS:
				566	case ARM::t2CPS3p:
				567	case ARM::t2CPS2p:
				568	case ARM::t2CPS1p:
Owen Anderson	163be01	2011-09-19 23:57:20 +0000	[diff] [blame]	569	case ARM::tMOVSr:
Owen Anderson	44f76ea	2011-10-13 17:58:39 +0000	[diff] [blame]	570	case ARM::tSETEND:
Owen Anderson	33d3953	2011-09-08 22:48:37 +0000	[diff] [blame]	571	// Some instructions (mostly conditional branches) are not
				572	// allowed in IT blocks.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	573	if (ITBlock.instrInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	574	S = SoftFail;
				575	else
				576	return Success;
				577	break;
				578	case ARM::tB:
				579	case ARM::t2B:
Owen Anderson	f902d92	2011-09-19 22:34:23 +0000	[diff] [blame]	580	case ARM::t2TBB:
				581	case ARM::t2TBH:
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	582	// Some instructions (mostly unconditional branches) can
				583	// only appears at the end of, or outside of, an IT.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	584	if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	585	S = SoftFail;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	586	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	587	default:
				588	break;
				589	}
				590
				591	// If we're in an IT block, base the predicate on that. Otherwise,
				592	// assume a predicate of AL.
				593	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	594	CC = ITBlock.getITCC();
				595	if (CC == 0xF)
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	596	CC = ARMCC::AL;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	597	if (ITBlock.instrInITBlock())
				598	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	599
				600	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	601	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	602	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	603	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				604	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	605	if (OpInfo[i].isPredicate()) {
				606	I = MI.insert(I, MCOperand::CreateImm(CC));
				607	++I;
				608	if (CC == ARMCC::AL)
				609	MI.insert(I, MCOperand::CreateReg(0));
				610	else
				611	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	612	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	613	}
				614	}
				615
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	616	I = MI.insert(I, MCOperand::CreateImm(CC));
				617	++I;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	618	if (CC == ARMCC::AL)
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	619	MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	620	else
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	621	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	622
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	623	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	624	}
				625
				626	// Thumb VFP instructions are a special case. Because we share their
				627	// encodings between ARM and Thumb modes, and they are predicable in ARM
				628	// mode, the auto-generated decoder will give them an (incorrect)
				629	// predicate operand. We need to rewrite these operands based on the IT
				630	// context as a post-pass.
				631	void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
				632	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	633	CC = ITBlock.getITCC();
				634	if (ITBlock.instrInITBlock())
				635	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	636
				637	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
				638	MCInst::iterator I = MI.begin();
Owen Anderson	216cfaa	2011-08-24 21:35:46 +0000	[diff] [blame]	639	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
				640	for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	641	if (OpInfo[i].isPredicate() ) {
				642	I->setImm(CC);
				643	++I;
				644	if (CC == ARMCC::AL)
				645	I->setReg(0);
				646	else
				647	I->setReg(ARM::CPSR);
				648	return;
				649	}
				650	}
				651	}
				652
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	653	DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	654	const MemoryObject &Region,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	655	uint64_t Address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	656	raw_ostream &os,
				657	raw_ostream &cs) const {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	658	CommentStream = &cs;
				659
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	660	uint8_t bytes[4];
				661
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	662	assert((STI.getFeatureBits() & ARM::ModeThumb) &&
				663	"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
				664
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	665	// We want to read exactly 2 bytes of data.
Benjamin Kramer	534d3a4	2013-05-24 10:54:58 +0000	[diff] [blame]	666	if (Region.readBytes(Address, 2, bytes) == -1) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	667	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	668	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	669	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	670
				671	uint16_t insn16 = (bytes[1] << 8) \| bytes[0];
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	672	DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
				673	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	674	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	675	Size = 2;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	676	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	677	return result;
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	678	}
				679
				680	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	681	result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
				682	Address, this, STI);
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	683	if (result) {
				684	Size = 2;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	685	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	686	Check(result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	687	AddThumb1SBit(MI, InITBlock);
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	688	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	689	}
				690
				691	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	692	result = decodeInstruction(DecoderTableThumb216, MI, insn16,
				693	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	694	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	695	Size = 2;
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	696
				697	// Nested IT blocks are UNPREDICTABLE. Must be checked before we add
				698	// the Thumb predicate.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	699	if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	700	result = MCDisassembler::SoftFail;
				701
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	702	Check(result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	703
				704	// If we find an IT instruction, we need to parse its condition
				705	// code and mask operands so that we can apply them correctly
				706	// to the subsequent instructions.
				707	if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson	f1e3844	2011-09-14 21:06:21 +0000	[diff] [blame]	708
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	709	unsigned Firstcond = MI.getOperand(0).getImm();
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	710	unsigned Mask = MI.getOperand(1).getImm();
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	711	ITBlock.setITState(Firstcond, Mask);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	712	}
				713
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	714	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	715	}
				716
				717	// We want to read exactly 4 bytes of data.
Benjamin Kramer	534d3a4	2013-05-24 10:54:58 +0000	[diff] [blame]	718	if (Region.readBytes(Address, 4, bytes) == -1) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	719	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	720	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	721	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	722
				723	uint32_t insn32 = (bytes[3] << 8) \|
				724	(bytes[2] << 0) \|
				725	(bytes[1] << 24) \|
				726	(bytes[0] << 16);
				727	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	728	result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
				729	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	730	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	731	Size = 4;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	732	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	733	Check(result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	734	AddThumb1SBit(MI, InITBlock);
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	735	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	736	}
				737
				738	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	739	result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
				740	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	741	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	742	Size = 4;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	743	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	744	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	745	}
				746
				747	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	748	result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	749	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	750	Size = 4;
				751	UpdateThumbVFPPredicate(MI);
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	752	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	753	}
				754
				755	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	756	result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
				757	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	758	if (result != MCDisassembler::Fail) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	759	Size = 4;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	760	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	761	return result;
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	762	}
				763
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	764	if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	765	MI.clear();
				766	uint32_t NEONLdStInsn = insn32;
				767	NEONLdStInsn &= 0xF0FFFFFF;
				768	NEONLdStInsn \|= 0x04000000;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	769	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
				770	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	771	if (result != MCDisassembler::Fail) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	772	Size = 4;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	773	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	774	return result;
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	775	}
				776	}
				777
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	778	if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	779	MI.clear();
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	780	uint32_t NEONDataInsn = insn32;
				781	NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
				782	NEONDataInsn \|= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				783	NEONDataInsn \|= 0x12000000; // Set bits 28 and 25
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	784	result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
				785	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	786	if (result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	787	Size = 4;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	788	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	789	return result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	790	}
				791	}
				792
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	793	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	794	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	795	}
				796
				797
				798	extern "C" void LLVMInitializeARMDisassembler() {
				799	TargetRegistry::RegisterMCDisassembler(TheARMTarget,
				800	createARMDisassembler);
				801	TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
				802	createThumbDisassembler);
				803	}
				804
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	805	static const uint16_t GPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	806	ARM::R0, ARM::R1, ARM::R2, ARM::R3,
				807	ARM::R4, ARM::R5, ARM::R6, ARM::R7,
				808	ARM::R8, ARM::R9, ARM::R10, ARM::R11,
				809	ARM::R12, ARM::SP, ARM::LR, ARM::PC
				810	};
				811
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	812	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	813	uint64_t Address, const void *Decoder) {
				814	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	815	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	816
				817	unsigned Register = GPRDecoderTable[RegNo];
				818	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	819	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	820	}
				821
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	822	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	823	DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	824	uint64_t Address, const void *Decoder) {
Silviu Baranga	32a4933	2012-03-20 15:54:56 +0000	[diff] [blame]	825	DecodeStatus S = MCDisassembler::Success;
				826
				827	if (RegNo == 15)
				828	S = MCDisassembler::SoftFail;
				829
				830	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				831
				832	return S;
Owen Anderson	042619f	2011-08-09 22:48:45 +0000	[diff] [blame]	833	}
				834
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	835	static DecodeStatus
				836	DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
				837	uint64_t Address, const void *Decoder) {
				838	DecodeStatus S = MCDisassembler::Success;
				839
				840	if (RegNo == 15)
				841	{
				842	Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
				843	return MCDisassembler::Success;
				844	}
				845
				846	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				847	return S;
				848	}
				849
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	850	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	851	uint64_t Address, const void *Decoder) {
				852	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	853	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	854	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				855	}
				856
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	857	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	858	uint64_t Address, const void *Decoder) {
				859	unsigned Register = 0;
				860	switch (RegNo) {
				861	case 0:
				862	Register = ARM::R0;
				863	break;
				864	case 1:
				865	Register = ARM::R1;
				866	break;
				867	case 2:
				868	Register = ARM::R2;
				869	break;
				870	case 3:
				871	Register = ARM::R3;
				872	break;
				873	case 9:
				874	Register = ARM::R9;
				875	break;
				876	case 12:
				877	Register = ARM::R12;
				878	break;
				879	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	880	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	881	}
				882
				883	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	884	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	885	}
				886
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	887	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	888	uint64_t Address, const void *Decoder) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	889	if (RegNo == 13 \|\| RegNo == 15) return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	890	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				891	}
				892
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	893	static const uint16_t SPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	894	ARM::S0, ARM::S1, ARM::S2, ARM::S3,
				895	ARM::S4, ARM::S5, ARM::S6, ARM::S7,
				896	ARM::S8, ARM::S9, ARM::S10, ARM::S11,
				897	ARM::S12, ARM::S13, ARM::S14, ARM::S15,
				898	ARM::S16, ARM::S17, ARM::S18, ARM::S19,
				899	ARM::S20, ARM::S21, ARM::S22, ARM::S23,
				900	ARM::S24, ARM::S25, ARM::S26, ARM::S27,
				901	ARM::S28, ARM::S29, ARM::S30, ARM::S31
				902	};
				903
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	904	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	905	uint64_t Address, const void *Decoder) {
				906	if (RegNo > 31)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	907	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	908
				909	unsigned Register = SPRDecoderTable[RegNo];
				910	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	911	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	912	}
				913
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	914	static const uint16_t DPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	915	ARM::D0, ARM::D1, ARM::D2, ARM::D3,
				916	ARM::D4, ARM::D5, ARM::D6, ARM::D7,
				917	ARM::D8, ARM::D9, ARM::D10, ARM::D11,
				918	ARM::D12, ARM::D13, ARM::D14, ARM::D15,
				919	ARM::D16, ARM::D17, ARM::D18, ARM::D19,
				920	ARM::D20, ARM::D21, ARM::D22, ARM::D23,
				921	ARM::D24, ARM::D25, ARM::D26, ARM::D27,
				922	ARM::D28, ARM::D29, ARM::D30, ARM::D31
				923	};
				924
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	925	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	926	uint64_t Address, const void *Decoder) {
				927	if (RegNo > 31)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	928	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	929
				930	unsigned Register = DPRDecoderTable[RegNo];
				931	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	932	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	933	}
				934
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	935	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	936	uint64_t Address, const void *Decoder) {
				937	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	938	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	939	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				940	}
				941
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	942	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	943	DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	944	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	945	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	946	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	947	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				948	}
				949
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	950	static const uint16_t QPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	951	ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
				952	ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
				953	ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
				954	ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
				955	};
				956
				957
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	958	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	959	uint64_t Address, const void *Decoder) {
Mihai Popa	dcf0922	2013-05-20 14:42:43 +0000	[diff] [blame]	960	if (RegNo > 31 \|\| (RegNo & 1) != 0)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	961	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	962	RegNo >>= 1;
				963
				964	unsigned Register = QPRDecoderTable[RegNo];
				965	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	966	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	967	}
				968
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	969	static const uint16_t DPairDecoderTable[] = {
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	970	ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
				971	ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
				972	ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
				973	ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
				974	ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
				975	ARM::Q15
				976	};
				977
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	978	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	979	uint64_t Address, const void *Decoder) {
				980	if (RegNo > 30)
				981	return MCDisassembler::Fail;
				982
				983	unsigned Register = DPairDecoderTable[RegNo];
				984	Inst.addOperand(MCOperand::CreateReg(Register));
				985	return MCDisassembler::Success;
				986	}
				987
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	988	static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	989	ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
				990	ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
				991	ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
				992	ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
				993	ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
				994	ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
				995	ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
				996	ARM::D28_D30, ARM::D29_D31
				997	};
				998
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	999	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1000	unsigned RegNo,
				1001	uint64_t Address,
				1002	const void *Decoder) {
				1003	if (RegNo > 29)
				1004	return MCDisassembler::Fail;
				1005
				1006	unsigned Register = DPairSpacedDecoderTable[RegNo];
				1007	Inst.addOperand(MCOperand::CreateReg(Register));
				1008	return MCDisassembler::Success;
				1009	}
				1010
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1011	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1012	uint64_t Address, const void *Decoder) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1013	if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson	7a2401d	2011-08-09 21:07:45 +0000	[diff] [blame]	1014	// AL predicate is not allowed on Thumb1 branches.
				1015	if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1016	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1017	Inst.addOperand(MCOperand::CreateImm(Val));
				1018	if (Val == ARMCC::AL) {
				1019	Inst.addOperand(MCOperand::CreateReg(0));
				1020	} else
				1021	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1022	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1023	}
				1024
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1025	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1026	uint64_t Address, const void *Decoder) {
				1027	if (Val)
				1028	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
				1029	else
				1030	Inst.addOperand(MCOperand::CreateReg(0));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1031	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1032	}
				1033
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1034	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1035	uint64_t Address, const void *Decoder) {
				1036	uint32_t imm = Val & 0xFF;
				1037	uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedman	a7ad9f3	2011-10-13 23:36:06 +0000	[diff] [blame]	1038	uint32_t rot_imm = (imm >> rot) \| (imm << ((32-rot) & 0x1F));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1039	Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1040	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1041	}
				1042
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1043	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1044	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1045	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1046
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1047	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1048	unsigned type = fieldFromInstruction(Val, 5, 2);
				1049	unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1050
				1051	// Register-immediate
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1052	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1053	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1054
				1055	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1056	switch (type) {
				1057	case 0:
				1058	Shift = ARM_AM::lsl;
				1059	break;
				1060	case 1:
				1061	Shift = ARM_AM::lsr;
				1062	break;
				1063	case 2:
				1064	Shift = ARM_AM::asr;
				1065	break;
				1066	case 3:
				1067	Shift = ARM_AM::ror;
				1068	break;
				1069	}
				1070
				1071	if (Shift == ARM_AM::ror && imm == 0)
				1072	Shift = ARM_AM::rrx;
				1073
				1074	unsigned Op = Shift \| (imm << 3);
				1075	Inst.addOperand(MCOperand::CreateImm(Op));
				1076
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1077	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1078	}
				1079
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1080	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1081	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1082	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1083
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1084	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1085	unsigned type = fieldFromInstruction(Val, 5, 2);
				1086	unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1087
				1088	// Register-register
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1089	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1090	return MCDisassembler::Fail;
				1091	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
				1092	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1093
				1094	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1095	switch (type) {
				1096	case 0:
				1097	Shift = ARM_AM::lsl;
				1098	break;
				1099	case 1:
				1100	Shift = ARM_AM::lsr;
				1101	break;
				1102	case 2:
				1103	Shift = ARM_AM::asr;
				1104	break;
				1105	case 3:
				1106	Shift = ARM_AM::ror;
				1107	break;
				1108	}
				1109
				1110	Inst.addOperand(MCOperand::CreateImm(Shift));
				1111
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1112	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1113	}
				1114
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1115	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1116	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1117	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1118
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1119	bool writebackLoad = false;
				1120	unsigned writebackReg = 0;
				1121	switch (Inst.getOpcode()) {
				1122	default:
				1123	break;
				1124	case ARM::LDMIA_UPD:
				1125	case ARM::LDMDB_UPD:
				1126	case ARM::LDMIB_UPD:
				1127	case ARM::LDMDA_UPD:
				1128	case ARM::t2LDMIA_UPD:
				1129	case ARM::t2LDMDB_UPD:
				1130	writebackLoad = true;
				1131	writebackReg = Inst.getOperand(0).getReg();
				1132	break;
				1133	}
				1134
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	1135	// Empty register lists are not allowed.
Benjamin Kramer	8bad66e	2013-05-19 22:01:57 +0000	[diff] [blame]	1136	if (Val == 0) return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1137	for (unsigned i = 0; i < 16; ++i) {
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1138	if (Val & (1 << i)) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1139	if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
				1140	return MCDisassembler::Fail;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1141	// Writeback not allowed if Rn is in the target list.
				1142	if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
				1143	Check(S, MCDisassembler::SoftFail);
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1144	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1145	}
				1146
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1147	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1148	}
				1149
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1150	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1151	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1152	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1153
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1154	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1155	unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1156
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1157	// In case of unpredictable encoding, tweak the operands.
				1158	if (regs == 0 \|\| (Vd + regs) > 32) {
				1159	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1160	regs = std::max( 1u, regs);
				1161	S = MCDisassembler::SoftFail;
				1162	}
				1163
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1164	if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
				1165	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1166	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1167	if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1168	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1169	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1170
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1171	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1172	}
				1173
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1174	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1175	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1176	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1177
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1178	unsigned Vd = fieldFromInstruction(Val, 8, 5);
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1179	unsigned regs = fieldFromInstruction(Val, 1, 7);
Silviu Baranga	9560af8	2012-05-03 16:38:40 +0000	[diff] [blame]	1180
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1181	// In case of unpredictable encoding, tweak the operands.
				1182	if (regs == 0 \|\| regs > 16 \|\| (Vd + regs) > 32) {
				1183	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1184	regs = std::max( 1u, regs);
				1185	regs = std::min(16u, regs);
				1186	S = MCDisassembler::SoftFail;
				1187	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1188
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1189	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				1190	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1191	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1192	if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1193	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1194	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1195
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1196	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1197	}
				1198
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1199	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1200	uint64_t Address, const void *Decoder) {
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1201	// This operand encodes a mask of contiguous zeros between a specified MSB
				1202	// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
				1203	// the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1204	// the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1205	// create the final mask.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1206	unsigned msb = fieldFromInstruction(Val, 5, 5);
				1207	unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1208
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1209	DecodeStatus S = MCDisassembler::Success;
Kevin Enderby	136d674	2012-11-29 23:47:11 +0000	[diff] [blame]	1210	if (lsb > msb) {
				1211	Check(S, MCDisassembler::SoftFail);
				1212	// The check above will cause the warning for the "potentially undefined
				1213	// instruction encoding" but we can't build a bad MCOperand value here
				1214	// with a lsb > msb or else printing the MCInst will cause a crash.
				1215	lsb = msb;
				1216	}
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1217
Owen Anderson	b925e93	2011-09-16 23:04:48 +0000	[diff] [blame]	1218	uint32_t msb_mask = 0xFFFFFFFF;
				1219	if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
				1220	uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1221
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1222	Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1223	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1224	}
				1225
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1226	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1227	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1228	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1229
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1230	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1231	unsigned CRd = fieldFromInstruction(Insn, 12, 4);
				1232	unsigned coproc = fieldFromInstruction(Insn, 8, 4);
				1233	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				1234	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1235	unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1236
				1237	switch (Inst.getOpcode()) {
				1238	case ARM::LDC_OFFSET:
				1239	case ARM::LDC_PRE:
				1240	case ARM::LDC_POST:
				1241	case ARM::LDC_OPTION:
				1242	case ARM::LDCL_OFFSET:
				1243	case ARM::LDCL_PRE:
				1244	case ARM::LDCL_POST:
				1245	case ARM::LDCL_OPTION:
				1246	case ARM::STC_OFFSET:
				1247	case ARM::STC_PRE:
				1248	case ARM::STC_POST:
				1249	case ARM::STC_OPTION:
				1250	case ARM::STCL_OFFSET:
				1251	case ARM::STCL_PRE:
				1252	case ARM::STCL_POST:
				1253	case ARM::STCL_OPTION:
Owen Anderson	18d17aa	2011-09-07 21:10:42 +0000	[diff] [blame]	1254	case ARM::t2LDC_OFFSET:
				1255	case ARM::t2LDC_PRE:
				1256	case ARM::t2LDC_POST:
				1257	case ARM::t2LDC_OPTION:
				1258	case ARM::t2LDCL_OFFSET:
				1259	case ARM::t2LDCL_PRE:
				1260	case ARM::t2LDCL_POST:
				1261	case ARM::t2LDCL_OPTION:
				1262	case ARM::t2STC_OFFSET:
				1263	case ARM::t2STC_PRE:
				1264	case ARM::t2STC_POST:
				1265	case ARM::t2STC_OPTION:
				1266	case ARM::t2STCL_OFFSET:
				1267	case ARM::t2STCL_PRE:
				1268	case ARM::t2STCL_POST:
				1269	case ARM::t2STCL_OPTION:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1270	if (coproc == 0xA \|\| coproc == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1271	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1272	break;
				1273	default:
				1274	break;
				1275	}
				1276
				1277	Inst.addOperand(MCOperand::CreateImm(coproc));
				1278	Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1279	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1280	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1281
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1282	switch (Inst.getOpcode()) {
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1283	case ARM::t2LDC2_OFFSET:
				1284	case ARM::t2LDC2L_OFFSET:
				1285	case ARM::t2LDC2_PRE:
				1286	case ARM::t2LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1287	case ARM::t2STC2_OFFSET:
				1288	case ARM::t2STC2L_OFFSET:
				1289	case ARM::t2STC2_PRE:
				1290	case ARM::t2STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1291	case ARM::LDC2_OFFSET:
				1292	case ARM::LDC2L_OFFSET:
				1293	case ARM::LDC2_PRE:
				1294	case ARM::LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1295	case ARM::STC2_OFFSET:
				1296	case ARM::STC2L_OFFSET:
				1297	case ARM::STC2_PRE:
				1298	case ARM::STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1299	case ARM::t2LDC_OFFSET:
				1300	case ARM::t2LDCL_OFFSET:
				1301	case ARM::t2LDC_PRE:
				1302	case ARM::t2LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1303	case ARM::t2STC_OFFSET:
				1304	case ARM::t2STCL_OFFSET:
				1305	case ARM::t2STC_PRE:
				1306	case ARM::t2STCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1307	case ARM::LDC_OFFSET:
				1308	case ARM::LDCL_OFFSET:
				1309	case ARM::LDC_PRE:
				1310	case ARM::LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1311	case ARM::STC_OFFSET:
				1312	case ARM::STCL_OFFSET:
				1313	case ARM::STC_PRE:
				1314	case ARM::STCL_PRE:
Jim Grosbach	a098a89	2011-10-12 21:59:02 +0000	[diff] [blame]	1315	imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
				1316	Inst.addOperand(MCOperand::CreateImm(imm));
				1317	break;
				1318	case ARM::t2LDC2_POST:
				1319	case ARM::t2LDC2L_POST:
				1320	case ARM::t2STC2_POST:
				1321	case ARM::t2STC2L_POST:
				1322	case ARM::LDC2_POST:
				1323	case ARM::LDC2L_POST:
				1324	case ARM::STC2_POST:
				1325	case ARM::STC2L_POST:
				1326	case ARM::t2LDC_POST:
				1327	case ARM::t2LDCL_POST:
				1328	case ARM::t2STC_POST:
				1329	case ARM::t2STCL_POST:
				1330	case ARM::LDC_POST:
				1331	case ARM::LDCL_POST:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1332	case ARM::STC_POST:
				1333	case ARM::STCL_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1334	imm \|= U << 8;
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1335	// fall through.
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1336	default:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1337	// The 'option' variant doesn't encode 'U' in the immediate since
				1338	// the immediate is unsigned [0,255].
				1339	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1340	break;
				1341	}
				1342
				1343	switch (Inst.getOpcode()) {
				1344	case ARM::LDC_OFFSET:
				1345	case ARM::LDC_PRE:
				1346	case ARM::LDC_POST:
				1347	case ARM::LDC_OPTION:
				1348	case ARM::LDCL_OFFSET:
				1349	case ARM::LDCL_PRE:
				1350	case ARM::LDCL_POST:
				1351	case ARM::LDCL_OPTION:
				1352	case ARM::STC_OFFSET:
				1353	case ARM::STC_PRE:
				1354	case ARM::STC_POST:
				1355	case ARM::STC_OPTION:
				1356	case ARM::STCL_OFFSET:
				1357	case ARM::STCL_PRE:
				1358	case ARM::STCL_POST:
				1359	case ARM::STCL_OPTION:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1360	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1361	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1362	break;
				1363	default:
				1364	break;
				1365	}
				1366
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1367	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1368	}
				1369
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1370	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1371	DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1372	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1373	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1374
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1375	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1376	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1377	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1378	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				1379	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1380	unsigned reg = fieldFromInstruction(Insn, 25, 1);
				1381	unsigned P = fieldFromInstruction(Insn, 24, 1);
				1382	unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1383
				1384	// On stores, the writeback operand precedes Rt.
				1385	switch (Inst.getOpcode()) {
				1386	case ARM::STR_POST_IMM:
				1387	case ARM::STR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1388	case ARM::STRB_POST_IMM:
				1389	case ARM::STRB_POST_REG:
Jim Grosbach	e259421	2011-08-11 22:18:00 +0000	[diff] [blame]	1390	case ARM::STRT_POST_REG:
				1391	case ARM::STRT_POST_IMM:
Jim Grosbach	2a50260	2011-08-11 20:04:56 +0000	[diff] [blame]	1392	case ARM::STRBT_POST_REG:
				1393	case ARM::STRBT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1394	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1395	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1396	break;
				1397	default:
				1398	break;
				1399	}
				1400
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1401	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1402	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1403
				1404	// On loads, the writeback operand comes after Rt.
				1405	switch (Inst.getOpcode()) {
				1406	case ARM::LDR_POST_IMM:
				1407	case ARM::LDR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1408	case ARM::LDRB_POST_IMM:
				1409	case ARM::LDRB_POST_REG:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1410	case ARM::LDRBT_POST_REG:
				1411	case ARM::LDRBT_POST_IMM:
Jim Grosbach	d5d6359	2011-08-10 23:43:54 +0000	[diff] [blame]	1412	case ARM::LDRT_POST_REG:
				1413	case ARM::LDRT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1414	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1415	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1416	break;
				1417	default:
				1418	break;
				1419	}
				1420
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1421	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1422	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1423
				1424	ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1425	if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1426	Op = ARM_AM::sub;
				1427
				1428	bool writeback = (P == 0) \|\| (W == 1);
				1429	unsigned idx_mode = 0;
				1430	if (P && writeback)
				1431	idx_mode = ARMII::IndexModePre;
				1432	else if (!P && writeback)
				1433	idx_mode = ARMII::IndexModePost;
				1434
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1435	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1436	S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson	3477f2c	2011-08-11 19:00:18 +0000	[diff] [blame]	1437
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1438	if (reg) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1439	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1440	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1441	ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1442	switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1443	case 0:
				1444	Opc = ARM_AM::lsl;
				1445	break;
				1446	case 1:
				1447	Opc = ARM_AM::lsr;
				1448	break;
				1449	case 2:
				1450	Opc = ARM_AM::asr;
				1451	break;
				1452	case 3:
				1453	Opc = ARM_AM::ror;
				1454	break;
				1455	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1456	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1457	}
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1458	unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1459	if (Opc == ARM_AM::ror && amt == 0)
				1460	Opc = ARM_AM::rrx;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1461	unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
				1462
				1463	Inst.addOperand(MCOperand::CreateImm(imm));
				1464	} else {
				1465	Inst.addOperand(MCOperand::CreateReg(0));
				1466	unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
				1467	Inst.addOperand(MCOperand::CreateImm(tmp));
				1468	}
				1469
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1470	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1471	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1472
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1473	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1474	}
				1475
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1476	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1477	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1478	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1479
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1480	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				1481	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1482	unsigned type = fieldFromInstruction(Val, 5, 2);
				1483	unsigned imm = fieldFromInstruction(Val, 7, 5);
				1484	unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1485
Owen Anderson	d151b09	2011-08-09 21:38:14 +0000	[diff] [blame]	1486	ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1487	switch (type) {
				1488	case 0:
				1489	ShOp = ARM_AM::lsl;
				1490	break;
				1491	case 1:
				1492	ShOp = ARM_AM::lsr;
				1493	break;
				1494	case 2:
				1495	ShOp = ARM_AM::asr;
				1496	break;
				1497	case 3:
				1498	ShOp = ARM_AM::ror;
				1499	break;
				1500	}
				1501
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1502	if (ShOp == ARM_AM::ror && imm == 0)
				1503	ShOp = ARM_AM::rrx;
				1504
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1505	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1506	return MCDisassembler::Fail;
				1507	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1508	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1509	unsigned shift;
				1510	if (U)
				1511	shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
				1512	else
				1513	shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
				1514	Inst.addOperand(MCOperand::CreateImm(shift));
				1515
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1516	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1517	}
				1518
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1519	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1520	DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1521	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1522	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1523
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1524	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1525	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1526	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1527	unsigned type = fieldFromInstruction(Insn, 22, 1);
				1528	unsigned imm = fieldFromInstruction(Insn, 8, 4);
				1529	unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
				1530	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1531	unsigned W = fieldFromInstruction(Insn, 21, 1);
				1532	unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1533	unsigned Rt2 = Rt + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1534
				1535	bool writeback = (W == 1) \| (P == 0);
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1536
				1537	// For {LD,ST}RD, Rt must be even, else undefined.
				1538	switch (Inst.getOpcode()) {
				1539	case ARM::STRD:
				1540	case ARM::STRD_PRE:
				1541	case ARM::STRD_POST:
				1542	case ARM::LDRD:
				1543	case ARM::LDRD_PRE:
				1544	case ARM::LDRD_POST:
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1545	if (Rt & 0x1) S = MCDisassembler::SoftFail;
				1546	break;
				1547	default:
				1548	break;
				1549	}
				1550	switch (Inst.getOpcode()) {
				1551	case ARM::STRD:
				1552	case ARM::STRD_PRE:
				1553	case ARM::STRD_POST:
				1554	if (P == 0 && W == 1)
				1555	S = MCDisassembler::SoftFail;
				1556
				1557	if (writeback && (Rn == 15 \|\| Rn == Rt \|\| Rn == Rt2))
				1558	S = MCDisassembler::SoftFail;
				1559	if (type && Rm == 15)
				1560	S = MCDisassembler::SoftFail;
				1561	if (Rt2 == 15)
				1562	S = MCDisassembler::SoftFail;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1563	if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1564	S = MCDisassembler::SoftFail;
				1565	break;
				1566	case ARM::STRH:
				1567	case ARM::STRH_PRE:
				1568	case ARM::STRH_POST:
				1569	if (Rt == 15)
				1570	S = MCDisassembler::SoftFail;
				1571	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1572	S = MCDisassembler::SoftFail;
				1573	if (!type && Rm == 15)
				1574	S = MCDisassembler::SoftFail;
				1575	break;
				1576	case ARM::LDRD:
				1577	case ARM::LDRD_PRE:
				1578	case ARM::LDRD_POST:
				1579	if (type && Rn == 15){
				1580	if (Rt2 == 15)
				1581	S = MCDisassembler::SoftFail;
				1582	break;
				1583	}
				1584	if (P == 0 && W == 1)
				1585	S = MCDisassembler::SoftFail;
				1586	if (!type && (Rt2 == 15 \|\| Rm == 15 \|\| Rm == Rt \|\| Rm == Rt2))
				1587	S = MCDisassembler::SoftFail;
				1588	if (!type && writeback && Rn == 15)
				1589	S = MCDisassembler::SoftFail;
				1590	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				1591	S = MCDisassembler::SoftFail;
				1592	break;
				1593	case ARM::LDRH:
				1594	case ARM::LDRH_PRE:
				1595	case ARM::LDRH_POST:
				1596	if (type && Rn == 15){
				1597	if (Rt == 15)
				1598	S = MCDisassembler::SoftFail;
				1599	break;
				1600	}
				1601	if (Rt == 15)
				1602	S = MCDisassembler::SoftFail;
				1603	if (!type && Rm == 15)
				1604	S = MCDisassembler::SoftFail;
				1605	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1606	S = MCDisassembler::SoftFail;
				1607	break;
				1608	case ARM::LDRSH:
				1609	case ARM::LDRSH_PRE:
				1610	case ARM::LDRSH_POST:
				1611	case ARM::LDRSB:
				1612	case ARM::LDRSB_PRE:
				1613	case ARM::LDRSB_POST:
				1614	if (type && Rn == 15){
				1615	if (Rt == 15)
				1616	S = MCDisassembler::SoftFail;
				1617	break;
				1618	}
				1619	if (type && (Rt == 15 \|\| (writeback && Rn == Rt)))
				1620	S = MCDisassembler::SoftFail;
				1621	if (!type && (Rt == 15 \|\| Rm == 15))
				1622	S = MCDisassembler::SoftFail;
				1623	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1624	S = MCDisassembler::SoftFail;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1625	break;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1626	default:
				1627	break;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1628	}
				1629
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1630	if (writeback) { // Writeback
				1631	if (P)
				1632	U \|= ARMII::IndexModePre << 9;
				1633	else
				1634	U \|= ARMII::IndexModePost << 9;
				1635
				1636	// On stores, the writeback operand precedes Rt.
				1637	switch (Inst.getOpcode()) {
				1638	case ARM::STRD:
				1639	case ARM::STRD_PRE:
				1640	case ARM::STRD_POST:
Owen Anderson	60138ea	2011-08-12 20:02:50 +0000	[diff] [blame]	1641	case ARM::STRH:
				1642	case ARM::STRH_PRE:
				1643	case ARM::STRH_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1644	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1645	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1646	break;
				1647	default:
				1648	break;
				1649	}
				1650	}
				1651
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1652	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1653	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1654	switch (Inst.getOpcode()) {
				1655	case ARM::STRD:
				1656	case ARM::STRD_PRE:
				1657	case ARM::STRD_POST:
				1658	case ARM::LDRD:
				1659	case ARM::LDRD_PRE:
				1660	case ARM::LDRD_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1661	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				1662	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1663	break;
				1664	default:
				1665	break;
				1666	}
				1667
				1668	if (writeback) {
				1669	// On loads, the writeback operand comes after Rt.
				1670	switch (Inst.getOpcode()) {
				1671	case ARM::LDRD:
				1672	case ARM::LDRD_PRE:
				1673	case ARM::LDRD_POST:
Owen Anderson	2d1d7a1	2011-08-12 20:36:11 +0000	[diff] [blame]	1674	case ARM::LDRH:
				1675	case ARM::LDRH_PRE:
				1676	case ARM::LDRH_POST:
				1677	case ARM::LDRSH:
				1678	case ARM::LDRSH_PRE:
				1679	case ARM::LDRSH_POST:
				1680	case ARM::LDRSB:
				1681	case ARM::LDRSB_PRE:
				1682	case ARM::LDRSB_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1683	case ARM::LDRHTr:
				1684	case ARM::LDRSBTr:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1685	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1686	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1687	break;
				1688	default:
				1689	break;
				1690	}
				1691	}
				1692
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1693	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1694	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1695
				1696	if (type) {
				1697	Inst.addOperand(MCOperand::CreateReg(0));
				1698	Inst.addOperand(MCOperand::CreateImm(U \| (imm << 4) \| Rm));
				1699	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1700	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1701	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1702	Inst.addOperand(MCOperand::CreateImm(U));
				1703	}
				1704
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1705	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1706	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1707
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1708	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1709	}
				1710
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1711	static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1712	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1713	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1714
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1715	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1716	unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1717
				1718	switch (mode) {
				1719	case 0:
				1720	mode = ARM_AM::da;
				1721	break;
				1722	case 1:
				1723	mode = ARM_AM::ia;
				1724	break;
				1725	case 2:
				1726	mode = ARM_AM::db;
				1727	break;
				1728	case 3:
				1729	mode = ARM_AM::ib;
				1730	break;
				1731	}
				1732
				1733	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1734	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1735	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1736
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1737	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1738	}
				1739
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1740	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				1741	uint64_t Address, const void *Decoder) {
				1742	DecodeStatus S = MCDisassembler::Success;
				1743
				1744	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				1745	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1746	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1747	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1748
				1749	if (pred == 0xF)
				1750	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				1751
				1752	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				1753	return MCDisassembler::Fail;
				1754	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1755	return MCDisassembler::Fail;
				1756	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				1757	return MCDisassembler::Fail;
				1758	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1759	return MCDisassembler::Fail;
				1760	return S;
				1761	}
				1762
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1763	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1764	unsigned Insn,
				1765	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1766	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1767
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1768	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1769	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1770	unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1771
				1772	if (pred == 0xF) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1773	// Ambiguous with RFE and SRS
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1774	switch (Inst.getOpcode()) {
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1775	case ARM::LDMDA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1776	Inst.setOpcode(ARM::RFEDA);
				1777	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1778	case ARM::LDMDA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1779	Inst.setOpcode(ARM::RFEDA_UPD);
				1780	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1781	case ARM::LDMDB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1782	Inst.setOpcode(ARM::RFEDB);
				1783	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1784	case ARM::LDMDB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1785	Inst.setOpcode(ARM::RFEDB_UPD);
				1786	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1787	case ARM::LDMIA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1788	Inst.setOpcode(ARM::RFEIA);
				1789	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1790	case ARM::LDMIA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1791	Inst.setOpcode(ARM::RFEIA_UPD);
				1792	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1793	case ARM::LDMIB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1794	Inst.setOpcode(ARM::RFEIB);
				1795	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1796	case ARM::LDMIB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1797	Inst.setOpcode(ARM::RFEIB_UPD);
				1798	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1799	case ARM::STMDA:
				1800	Inst.setOpcode(ARM::SRSDA);
				1801	break;
				1802	case ARM::STMDA_UPD:
				1803	Inst.setOpcode(ARM::SRSDA_UPD);
				1804	break;
				1805	case ARM::STMDB:
				1806	Inst.setOpcode(ARM::SRSDB);
				1807	break;
				1808	case ARM::STMDB_UPD:
				1809	Inst.setOpcode(ARM::SRSDB_UPD);
				1810	break;
				1811	case ARM::STMIA:
				1812	Inst.setOpcode(ARM::SRSIA);
				1813	break;
				1814	case ARM::STMIA_UPD:
				1815	Inst.setOpcode(ARM::SRSIA_UPD);
				1816	break;
				1817	case ARM::STMIB:
				1818	Inst.setOpcode(ARM::SRSIB);
				1819	break;
				1820	case ARM::STMIB_UPD:
				1821	Inst.setOpcode(ARM::SRSIB_UPD);
				1822	break;
				1823	default:
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1824	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1825	}
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1826
				1827	// For stores (which become SRS's, the only operand is the mode.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1828	if (fieldFromInstruction(Insn, 20, 1) == 0) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1829	// Check SRS encoding constraints
				1830	if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
				1831	fieldFromInstruction(Insn, 20, 1) == 0))
				1832	return MCDisassembler::Fail;
				1833
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1834	Inst.addOperand(
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1835	MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1836	return S;
				1837	}
				1838
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1839	return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
				1840	}
				1841
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1842	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1843	return MCDisassembler::Fail;
				1844	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1845	return MCDisassembler::Fail; // Tied
				1846	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1847	return MCDisassembler::Fail;
				1848	if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
				1849	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1850
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1851	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1852	}
				1853
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1854	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1855	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1856	unsigned imod = fieldFromInstruction(Insn, 18, 2);
				1857	unsigned M = fieldFromInstruction(Insn, 17, 1);
				1858	unsigned iflags = fieldFromInstruction(Insn, 6, 3);
				1859	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1860
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1861	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	1862
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1863	// This decoder is called from multiple location that do not check
				1864	// the full encoding is valid before they do.
				1865	if (fieldFromInstruction(Insn, 5, 1) != 0 \|\|
				1866	fieldFromInstruction(Insn, 16, 1) != 0 \|\|
				1867	fieldFromInstruction(Insn, 20, 8) != 0x10)
				1868	return MCDisassembler::Fail;
				1869
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1870	// imod == '01' --> UNPREDICTABLE
				1871	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1872	// return failure here. The '01' imod value is unprintable, so there's
				1873	// nothing useful we could do even if we returned UNPREDICTABLE.
				1874
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1875	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1876
				1877	if (imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1878	Inst.setOpcode(ARM::CPS3p);
				1879	Inst.addOperand(MCOperand::CreateImm(imod));
				1880	Inst.addOperand(MCOperand::CreateImm(iflags));
				1881	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1882	} else if (imod && !M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1883	Inst.setOpcode(ARM::CPS2p);
				1884	Inst.addOperand(MCOperand::CreateImm(imod));
				1885	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1886	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1887	} else if (!imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1888	Inst.setOpcode(ARM::CPS1p);
				1889	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1890	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1891	} else {
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1892	// imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1893	Inst.setOpcode(ARM::CPS1p);
				1894	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1895	S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1896	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1897
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1898	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1899	}
				1900
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1901	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1902	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1903	unsigned imod = fieldFromInstruction(Insn, 9, 2);
				1904	unsigned M = fieldFromInstruction(Insn, 8, 1);
				1905	unsigned iflags = fieldFromInstruction(Insn, 5, 3);
				1906	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1907
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1908	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1909
				1910	// imod == '01' --> UNPREDICTABLE
				1911	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1912	// return failure here. The '01' imod value is unprintable, so there's
				1913	// nothing useful we could do even if we returned UNPREDICTABLE.
				1914
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1915	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1916
				1917	if (imod && M) {
				1918	Inst.setOpcode(ARM::t2CPS3p);
				1919	Inst.addOperand(MCOperand::CreateImm(imod));
				1920	Inst.addOperand(MCOperand::CreateImm(iflags));
				1921	Inst.addOperand(MCOperand::CreateImm(mode));
				1922	} else if (imod && !M) {
				1923	Inst.setOpcode(ARM::t2CPS2p);
				1924	Inst.addOperand(MCOperand::CreateImm(imod));
				1925	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1926	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1927	} else if (!imod && M) {
				1928	Inst.setOpcode(ARM::t2CPS1p);
				1929	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1930	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1931	} else {
Quentin Colombet	a83d5e9	2013-04-26 17:54:54 +0000	[diff] [blame]	1932	// imod == '00' && M == '0' --> this is a HINT instruction
				1933	int imm = fieldFromInstruction(Insn, 0, 8);
				1934	// HINT are defined only for immediate in [0..4]
				1935	if(imm > 4) return MCDisassembler::Fail;
				1936	Inst.setOpcode(ARM::t2HINT);
				1937	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1938	}
				1939
				1940	return S;
				1941	}
				1942
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1943	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	1944	uint64_t Address, const void *Decoder) {
				1945	DecodeStatus S = MCDisassembler::Success;
				1946
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1947	unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	1948	unsigned imm = 0;
				1949
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1950	imm \|= (fieldFromInstruction(Insn, 0, 8) << 0);
				1951	imm \|= (fieldFromInstruction(Insn, 12, 3) << 8);
				1952	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
				1953	imm \|= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	1954
				1955	if (Inst.getOpcode() == ARM::t2MOVTi16)
				1956	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				1957	return MCDisassembler::Fail;
				1958	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				1959	return MCDisassembler::Fail;
				1960
				1961	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				1962	Inst.addOperand(MCOperand::CreateImm(imm));
				1963
				1964	return S;
				1965	}
				1966
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1967	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	1968	uint64_t Address, const void *Decoder) {
				1969	DecodeStatus S = MCDisassembler::Success;
				1970
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1971	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				1972	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	1973	unsigned imm = 0;
				1974
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1975	imm \|= (fieldFromInstruction(Insn, 0, 12) << 0);
				1976	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	1977
				1978	if (Inst.getOpcode() == ARM::MOVTi16)
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	1979	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	1980	return MCDisassembler::Fail;
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	1981
				1982	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	1983	return MCDisassembler::Fail;
				1984
				1985	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				1986	Inst.addOperand(MCOperand::CreateImm(imm));
				1987
				1988	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1989	return MCDisassembler::Fail;
				1990
				1991	return S;
				1992	}
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1993
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1994	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1995	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1996	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1997
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1998	unsigned Rd = fieldFromInstruction(Insn, 16, 4);
				1999	unsigned Rn = fieldFromInstruction(Insn, 0, 4);
				2000	unsigned Rm = fieldFromInstruction(Insn, 8, 4);
				2001	unsigned Ra = fieldFromInstruction(Insn, 12, 4);
				2002	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2003
				2004	if (pred == 0xF)
				2005	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				2006
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2007	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				2008	return MCDisassembler::Fail;
				2009	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				2010	return MCDisassembler::Fail;
				2011	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				2012	return MCDisassembler::Fail;
				2013	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
				2014	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2015
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2016	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2017	return MCDisassembler::Fail;
Owen Anderson	2f7aa73	2011-08-11 22:05:38 +0000	[diff] [blame]	2018
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2019	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2020	}
				2021
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2022	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2023	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2024	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2025
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2026	unsigned add = fieldFromInstruction(Val, 12, 1);
				2027	unsigned imm = fieldFromInstruction(Val, 0, 12);
				2028	unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2029
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2030	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2031	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2032
				2033	if (!add) imm *= -1;
				2034	if (imm == 0 && !add) imm = INT32_MIN;
				2035	Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2036	if (Rn == 15)
				2037	tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2038
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2039	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2040	}
				2041
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2042	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2043	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2044	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2045
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2046	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				2047	unsigned U = fieldFromInstruction(Val, 8, 1);
				2048	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2049
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2050	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2051	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2052
				2053	if (U)
				2054	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
				2055	else
				2056	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
				2057
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2058	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2059	}
				2060
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2061	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2062	uint64_t Address, const void *Decoder) {
				2063	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
				2064	}
				2065
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2066	static DecodeStatus
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2067	DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				2068	uint64_t Address, const void *Decoder) {
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2069	DecodeStatus Status = MCDisassembler::Success;
				2070
				2071	// Note the J1 and J2 values are from the encoded instruction. So here
				2072	// change them to I1 and I2 values via as documented:
				2073	// I1 = NOT(J1 EOR S);
				2074	// I2 = NOT(J2 EOR S);
				2075	// and build the imm32 with one trailing zero as documented:
				2076	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
				2077	unsigned S = fieldFromInstruction(Insn, 26, 1);
				2078	unsigned J1 = fieldFromInstruction(Insn, 13, 1);
				2079	unsigned J2 = fieldFromInstruction(Insn, 11, 1);
				2080	unsigned I1 = !(J1 ^ S);
				2081	unsigned I2 = !(J2 ^ S);
				2082	unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
				2083	unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
				2084	unsigned tmp = (S << 23) \| (I1 << 22) \| (I2 << 21) \| (imm10 << 11) \| imm11;
				2085	int imm32 = SignExtend32<24>(tmp << 1);
				2086	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2087	true, 4, Inst, Decoder))
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2088	Inst.addOperand(MCOperand::CreateImm(imm32));
				2089
				2090	return Status;
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2091	}
				2092
				2093	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2094	DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	2095	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2096	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2097
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2098	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				2099	unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2100
				2101	if (pred == 0xF) {
				2102	Inst.setOpcode(ARM::BLXi);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2103	imm \|= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2104	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2105	true, 4, Inst, Decoder))
Benjamin Kramer	406dc17	2011-08-09 22:02:50 +0000	[diff] [blame]	2106	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2107	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2108	}
				2109
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2110	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2111	true, 4, Inst, Decoder))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2112	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2113	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2114	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2115
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2116	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2117	}
				2118
				2119
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2120	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2121	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2122	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2123
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2124	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				2125	unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2126
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2127	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2128	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2129	if (!align)
				2130	Inst.addOperand(MCOperand::CreateImm(0));
				2131	else
				2132	Inst.addOperand(MCOperand::CreateImm(4 << align));
				2133
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2134	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2135	}
				2136
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2137	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2138	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2139	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2140
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2141	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2142	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2143	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2144	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2145	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2146	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2147
				2148	// First output register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2149	switch (Inst.getOpcode()) {
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2150	case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
				2151	case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
				2152	case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
				2153	case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
				2154	case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
				2155	case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
				2156	case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
				2157	case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
				2158	case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2159	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2160	return MCDisassembler::Fail;
				2161	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2162	case ARM::VLD2b16:
				2163	case ARM::VLD2b32:
				2164	case ARM::VLD2b8:
				2165	case ARM::VLD2b16wb_fixed:
				2166	case ARM::VLD2b16wb_register:
				2167	case ARM::VLD2b32wb_fixed:
				2168	case ARM::VLD2b32wb_register:
				2169	case ARM::VLD2b8wb_fixed:
				2170	case ARM::VLD2b8wb_register:
				2171	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2172	return MCDisassembler::Fail;
				2173	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2174	default:
				2175	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2176	return MCDisassembler::Fail;
				2177	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2178
				2179	// Second output register
				2180	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2181	case ARM::VLD3d8:
				2182	case ARM::VLD3d16:
				2183	case ARM::VLD3d32:
				2184	case ARM::VLD3d8_UPD:
				2185	case ARM::VLD3d16_UPD:
				2186	case ARM::VLD3d32_UPD:
				2187	case ARM::VLD4d8:
				2188	case ARM::VLD4d16:
				2189	case ARM::VLD4d32:
				2190	case ARM::VLD4d8_UPD:
				2191	case ARM::VLD4d16_UPD:
				2192	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2193	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2194	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2195	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2196	case ARM::VLD3q8:
				2197	case ARM::VLD3q16:
				2198	case ARM::VLD3q32:
				2199	case ARM::VLD3q8_UPD:
				2200	case ARM::VLD3q16_UPD:
				2201	case ARM::VLD3q32_UPD:
				2202	case ARM::VLD4q8:
				2203	case ARM::VLD4q16:
				2204	case ARM::VLD4q32:
				2205	case ARM::VLD4q8_UPD:
				2206	case ARM::VLD4q16_UPD:
				2207	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2208	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2209	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2210	default:
				2211	break;
				2212	}
				2213
				2214	// Third output register
				2215	switch(Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2216	case ARM::VLD3d8:
				2217	case ARM::VLD3d16:
				2218	case ARM::VLD3d32:
				2219	case ARM::VLD3d8_UPD:
				2220	case ARM::VLD3d16_UPD:
				2221	case ARM::VLD3d32_UPD:
				2222	case ARM::VLD4d8:
				2223	case ARM::VLD4d16:
				2224	case ARM::VLD4d32:
				2225	case ARM::VLD4d8_UPD:
				2226	case ARM::VLD4d16_UPD:
				2227	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2228	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2229	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2230	break;
				2231	case ARM::VLD3q8:
				2232	case ARM::VLD3q16:
				2233	case ARM::VLD3q32:
				2234	case ARM::VLD3q8_UPD:
				2235	case ARM::VLD3q16_UPD:
				2236	case ARM::VLD3q32_UPD:
				2237	case ARM::VLD4q8:
				2238	case ARM::VLD4q16:
				2239	case ARM::VLD4q32:
				2240	case ARM::VLD4q8_UPD:
				2241	case ARM::VLD4q16_UPD:
				2242	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2243	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2244	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2245	break;
				2246	default:
				2247	break;
				2248	}
				2249
				2250	// Fourth output register
				2251	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2252	case ARM::VLD4d8:
				2253	case ARM::VLD4d16:
				2254	case ARM::VLD4d32:
				2255	case ARM::VLD4d8_UPD:
				2256	case ARM::VLD4d16_UPD:
				2257	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2258	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2259	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2260	break;
				2261	case ARM::VLD4q8:
				2262	case ARM::VLD4q16:
				2263	case ARM::VLD4q32:
				2264	case ARM::VLD4q8_UPD:
				2265	case ARM::VLD4q16_UPD:
				2266	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2267	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2268	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2269	break;
				2270	default:
				2271	break;
				2272	}
				2273
				2274	// Writeback operand
				2275	switch (Inst.getOpcode()) {
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2276	case ARM::VLD1d8wb_fixed:
				2277	case ARM::VLD1d16wb_fixed:
				2278	case ARM::VLD1d32wb_fixed:
				2279	case ARM::VLD1d64wb_fixed:
				2280	case ARM::VLD1d8wb_register:
				2281	case ARM::VLD1d16wb_register:
				2282	case ARM::VLD1d32wb_register:
				2283	case ARM::VLD1d64wb_register:
				2284	case ARM::VLD1q8wb_fixed:
				2285	case ARM::VLD1q16wb_fixed:
				2286	case ARM::VLD1q32wb_fixed:
				2287	case ARM::VLD1q64wb_fixed:
				2288	case ARM::VLD1q8wb_register:
				2289	case ARM::VLD1q16wb_register:
				2290	case ARM::VLD1q32wb_register:
				2291	case ARM::VLD1q64wb_register:
Jim Grosbach	92fd05e	2011-10-24 23:26:05 +0000	[diff] [blame]	2292	case ARM::VLD1d8Twb_fixed:
				2293	case ARM::VLD1d8Twb_register:
				2294	case ARM::VLD1d16Twb_fixed:
				2295	case ARM::VLD1d16Twb_register:
				2296	case ARM::VLD1d32Twb_fixed:
				2297	case ARM::VLD1d32Twb_register:
				2298	case ARM::VLD1d64Twb_fixed:
				2299	case ARM::VLD1d64Twb_register:
Jim Grosbach	17ec1a1	2011-10-25 00:14:01 +0000	[diff] [blame]	2300	case ARM::VLD1d8Qwb_fixed:
				2301	case ARM::VLD1d8Qwb_register:
				2302	case ARM::VLD1d16Qwb_fixed:
				2303	case ARM::VLD1d16Qwb_register:
				2304	case ARM::VLD1d32Qwb_fixed:
				2305	case ARM::VLD1d32Qwb_register:
				2306	case ARM::VLD1d64Qwb_fixed:
				2307	case ARM::VLD1d64Qwb_register:
Jim Grosbach	d146a02	2011-12-09 21:28:25 +0000	[diff] [blame]	2308	case ARM::VLD2d8wb_fixed:
				2309	case ARM::VLD2d16wb_fixed:
				2310	case ARM::VLD2d32wb_fixed:
				2311	case ARM::VLD2q8wb_fixed:
				2312	case ARM::VLD2q16wb_fixed:
				2313	case ARM::VLD2q32wb_fixed:
				2314	case ARM::VLD2d8wb_register:
				2315	case ARM::VLD2d16wb_register:
				2316	case ARM::VLD2d32wb_register:
				2317	case ARM::VLD2q8wb_register:
				2318	case ARM::VLD2q16wb_register:
				2319	case ARM::VLD2q32wb_register:
				2320	case ARM::VLD2b8wb_fixed:
				2321	case ARM::VLD2b16wb_fixed:
				2322	case ARM::VLD2b32wb_fixed:
				2323	case ARM::VLD2b8wb_register:
				2324	case ARM::VLD2b16wb_register:
				2325	case ARM::VLD2b32wb_register:
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2326	Inst.addOperand(MCOperand::CreateImm(0));
				2327	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2328	case ARM::VLD3d8_UPD:
				2329	case ARM::VLD3d16_UPD:
				2330	case ARM::VLD3d32_UPD:
				2331	case ARM::VLD3q8_UPD:
				2332	case ARM::VLD3q16_UPD:
				2333	case ARM::VLD3q32_UPD:
				2334	case ARM::VLD4d8_UPD:
				2335	case ARM::VLD4d16_UPD:
				2336	case ARM::VLD4d32_UPD:
				2337	case ARM::VLD4q8_UPD:
				2338	case ARM::VLD4q16_UPD:
				2339	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2340	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2341	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2342	break;
				2343	default:
				2344	break;
				2345	}
				2346
				2347	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2348	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2349	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2350
				2351	// AddrMode6 Offset (register)
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2352	switch (Inst.getOpcode()) {
				2353	default:
				2354	// The below have been updated to have explicit am6offset split
				2355	// between fixed and register offset. For those instructions not
				2356	// yet updated, we need to add an additional reg0 operand for the
				2357	// fixed variant.
				2358	//
				2359	// The fixed offset encodes as Rm == 0xd, so we check for that.
				2360	if (Rm == 0xd) {
				2361	Inst.addOperand(MCOperand::CreateReg(0));
				2362	break;
				2363	}
				2364	// Fall through to handle the register offset variant.
				2365	case ARM::VLD1d8wb_fixed:
				2366	case ARM::VLD1d16wb_fixed:
				2367	case ARM::VLD1d32wb_fixed:
				2368	case ARM::VLD1d64wb_fixed:
Owen Anderson	8a6ebd0	2011-10-27 22:53:10 +0000	[diff] [blame]	2369	case ARM::VLD1d8Twb_fixed:
				2370	case ARM::VLD1d16Twb_fixed:
				2371	case ARM::VLD1d32Twb_fixed:
				2372	case ARM::VLD1d64Twb_fixed:
Owen Anderson	40703f4	2011-10-31 17:17:32 +0000	[diff] [blame]	2373	case ARM::VLD1d8Qwb_fixed:
				2374	case ARM::VLD1d16Qwb_fixed:
				2375	case ARM::VLD1d32Qwb_fixed:
				2376	case ARM::VLD1d64Qwb_fixed:
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2377	case ARM::VLD1d8wb_register:
				2378	case ARM::VLD1d16wb_register:
				2379	case ARM::VLD1d32wb_register:
				2380	case ARM::VLD1d64wb_register:
				2381	case ARM::VLD1q8wb_fixed:
				2382	case ARM::VLD1q16wb_fixed:
				2383	case ARM::VLD1q32wb_fixed:
				2384	case ARM::VLD1q64wb_fixed:
				2385	case ARM::VLD1q8wb_register:
				2386	case ARM::VLD1q16wb_register:
				2387	case ARM::VLD1q32wb_register:
				2388	case ARM::VLD1q64wb_register:
				2389	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2390	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2391	// increment and we need to add the register operand to the instruction.
				2392	if (Rm != 0xD && Rm != 0xF &&
				2393	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2394	return MCDisassembler::Fail;
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2395	break;
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2396	case ARM::VLD2d8wb_fixed:
				2397	case ARM::VLD2d16wb_fixed:
				2398	case ARM::VLD2d32wb_fixed:
				2399	case ARM::VLD2b8wb_fixed:
				2400	case ARM::VLD2b16wb_fixed:
				2401	case ARM::VLD2b32wb_fixed:
				2402	case ARM::VLD2q8wb_fixed:
				2403	case ARM::VLD2q16wb_fixed:
				2404	case ARM::VLD2q32wb_fixed:
				2405	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2406	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2407
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2408	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2409	}
				2410
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2411	static DecodeStatus DecodeVST1Instruction(MCInst& Inst, unsigned Insn,
				2412	uint64_t Addr, const void* Decoder) {
				2413	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2414	unsigned align = fieldFromInstruction(Insn, 4, 2);
				2415	if(type == 7 && (align & 2)) return MCDisassembler::Fail;
				2416	if(type == 10 && align == 3) return MCDisassembler::Fail;
				2417	if(type == 6 && (align & 2)) return MCDisassembler::Fail;
				2418
				2419	return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
				2420	}
				2421
				2422	static DecodeStatus DecodeVST2Instruction(MCInst& Inst, unsigned Insn,
				2423	uint64_t Addr, const void* Decoder) {
				2424	unsigned size = fieldFromInstruction(Insn, 6, 2);
				2425	if(size == 3) return MCDisassembler::Fail;
				2426
				2427	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2428	unsigned align = fieldFromInstruction(Insn, 4, 2);
				2429	if(type == 8 && align == 3) return MCDisassembler::Fail;
				2430	if(type == 9 && align == 3) return MCDisassembler::Fail;
				2431
				2432	return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
				2433	}
				2434
				2435	static DecodeStatus DecodeVST3Instruction(MCInst& Inst, unsigned Insn,
				2436	uint64_t Addr, const void* Decoder) {
				2437	unsigned size = fieldFromInstruction(Insn, 6, 2);
				2438	if(size == 3) return MCDisassembler::Fail;
				2439
				2440	unsigned align = fieldFromInstruction(Insn, 4, 2);
				2441	if(align & 2) return MCDisassembler::Fail;
				2442
				2443	return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
				2444	}
				2445
				2446	static DecodeStatus DecodeVST4Instruction(MCInst& Inst, unsigned Insn,
				2447	uint64_t Addr, const void* Decoder) {
				2448	unsigned size = fieldFromInstruction(Insn, 6, 2);
				2449	if(size == 3) return MCDisassembler::Fail;
				2450
				2451	return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
				2452	}
				2453
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2454	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2455	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2456	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2457
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2458	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2459	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2460	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2461	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2462	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2463	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2464
				2465	// Writeback Operand
				2466	switch (Inst.getOpcode()) {
Jim Grosbach	05df460	2011-10-31 21:50:31 +0000	[diff] [blame]	2467	case ARM::VST1d8wb_fixed:
				2468	case ARM::VST1d16wb_fixed:
				2469	case ARM::VST1d32wb_fixed:
				2470	case ARM::VST1d64wb_fixed:
				2471	case ARM::VST1d8wb_register:
				2472	case ARM::VST1d16wb_register:
				2473	case ARM::VST1d32wb_register:
				2474	case ARM::VST1d64wb_register:
				2475	case ARM::VST1q8wb_fixed:
				2476	case ARM::VST1q16wb_fixed:
				2477	case ARM::VST1q32wb_fixed:
				2478	case ARM::VST1q64wb_fixed:
				2479	case ARM::VST1q8wb_register:
				2480	case ARM::VST1q16wb_register:
				2481	case ARM::VST1q32wb_register:
				2482	case ARM::VST1q64wb_register:
Jim Grosbach	98d032f	2011-11-29 22:38:04 +0000	[diff] [blame]	2483	case ARM::VST1d8Twb_fixed:
				2484	case ARM::VST1d16Twb_fixed:
				2485	case ARM::VST1d32Twb_fixed:
				2486	case ARM::VST1d64Twb_fixed:
				2487	case ARM::VST1d8Twb_register:
				2488	case ARM::VST1d16Twb_register:
				2489	case ARM::VST1d32Twb_register:
				2490	case ARM::VST1d64Twb_register:
Jim Grosbach	5ee209c	2011-11-29 22:58:48 +0000	[diff] [blame]	2491	case ARM::VST1d8Qwb_fixed:
				2492	case ARM::VST1d16Qwb_fixed:
				2493	case ARM::VST1d32Qwb_fixed:
				2494	case ARM::VST1d64Qwb_fixed:
				2495	case ARM::VST1d8Qwb_register:
				2496	case ARM::VST1d16Qwb_register:
				2497	case ARM::VST1d32Qwb_register:
				2498	case ARM::VST1d64Qwb_register:
Jim Grosbach	88ac761	2011-12-14 21:32:11 +0000	[diff] [blame]	2499	case ARM::VST2d8wb_fixed:
				2500	case ARM::VST2d16wb_fixed:
				2501	case ARM::VST2d32wb_fixed:
				2502	case ARM::VST2d8wb_register:
				2503	case ARM::VST2d16wb_register:
				2504	case ARM::VST2d32wb_register:
				2505	case ARM::VST2q8wb_fixed:
				2506	case ARM::VST2q16wb_fixed:
				2507	case ARM::VST2q32wb_fixed:
				2508	case ARM::VST2q8wb_register:
				2509	case ARM::VST2q16wb_register:
				2510	case ARM::VST2q32wb_register:
				2511	case ARM::VST2b8wb_fixed:
				2512	case ARM::VST2b16wb_fixed:
				2513	case ARM::VST2b32wb_fixed:
				2514	case ARM::VST2b8wb_register:
				2515	case ARM::VST2b16wb_register:
				2516	case ARM::VST2b32wb_register:
Kevin Enderby	72f18bb	2012-04-11 22:40:17 +0000	[diff] [blame]	2517	if (Rm == 0xF)
				2518	return MCDisassembler::Fail;
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2519	Inst.addOperand(MCOperand::CreateImm(0));
				2520	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2521	case ARM::VST3d8_UPD:
				2522	case ARM::VST3d16_UPD:
				2523	case ARM::VST3d32_UPD:
				2524	case ARM::VST3q8_UPD:
				2525	case ARM::VST3q16_UPD:
				2526	case ARM::VST3q32_UPD:
				2527	case ARM::VST4d8_UPD:
				2528	case ARM::VST4d16_UPD:
				2529	case ARM::VST4d32_UPD:
				2530	case ARM::VST4q8_UPD:
				2531	case ARM::VST4q16_UPD:
				2532	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2533	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2534	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2535	break;
				2536	default:
				2537	break;
				2538	}
				2539
				2540	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2541	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2542	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2543
				2544	// AddrMode6 Offset (register)
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2545	switch (Inst.getOpcode()) {
				2546	default:
				2547	if (Rm == 0xD)
				2548	Inst.addOperand(MCOperand::CreateReg(0));
				2549	else if (Rm != 0xF) {
				2550	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2551	return MCDisassembler::Fail;
				2552	}
				2553	break;
				2554	case ARM::VST1d8wb_fixed:
				2555	case ARM::VST1d16wb_fixed:
				2556	case ARM::VST1d32wb_fixed:
				2557	case ARM::VST1d64wb_fixed:
				2558	case ARM::VST1q8wb_fixed:
				2559	case ARM::VST1q16wb_fixed:
				2560	case ARM::VST1q32wb_fixed:
				2561	case ARM::VST1q64wb_fixed:
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2562	case ARM::VST1d8Twb_fixed:
				2563	case ARM::VST1d16Twb_fixed:
				2564	case ARM::VST1d32Twb_fixed:
				2565	case ARM::VST1d64Twb_fixed:
				2566	case ARM::VST1d8Qwb_fixed:
				2567	case ARM::VST1d16Qwb_fixed:
				2568	case ARM::VST1d32Qwb_fixed:
				2569	case ARM::VST1d64Qwb_fixed:
				2570	case ARM::VST2d8wb_fixed:
				2571	case ARM::VST2d16wb_fixed:
				2572	case ARM::VST2d32wb_fixed:
				2573	case ARM::VST2q8wb_fixed:
				2574	case ARM::VST2q16wb_fixed:
				2575	case ARM::VST2q32wb_fixed:
				2576	case ARM::VST2b8wb_fixed:
				2577	case ARM::VST2b16wb_fixed:
				2578	case ARM::VST2b32wb_fixed:
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2579	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2580	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2581
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2582
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2583	// First input register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2584	switch (Inst.getOpcode()) {
				2585	case ARM::VST1q16:
				2586	case ARM::VST1q32:
				2587	case ARM::VST1q64:
				2588	case ARM::VST1q8:
				2589	case ARM::VST1q16wb_fixed:
				2590	case ARM::VST1q16wb_register:
				2591	case ARM::VST1q32wb_fixed:
				2592	case ARM::VST1q32wb_register:
				2593	case ARM::VST1q64wb_fixed:
				2594	case ARM::VST1q64wb_register:
				2595	case ARM::VST1q8wb_fixed:
				2596	case ARM::VST1q8wb_register:
				2597	case ARM::VST2d16:
				2598	case ARM::VST2d32:
				2599	case ARM::VST2d8:
				2600	case ARM::VST2d16wb_fixed:
				2601	case ARM::VST2d16wb_register:
				2602	case ARM::VST2d32wb_fixed:
				2603	case ARM::VST2d32wb_register:
				2604	case ARM::VST2d8wb_fixed:
				2605	case ARM::VST2d8wb_register:
				2606	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2607	return MCDisassembler::Fail;
				2608	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2609	case ARM::VST2b16:
				2610	case ARM::VST2b32:
				2611	case ARM::VST2b8:
				2612	case ARM::VST2b16wb_fixed:
				2613	case ARM::VST2b16wb_register:
				2614	case ARM::VST2b32wb_fixed:
				2615	case ARM::VST2b32wb_register:
				2616	case ARM::VST2b8wb_fixed:
				2617	case ARM::VST2b8wb_register:
				2618	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2619	return MCDisassembler::Fail;
				2620	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2621	default:
				2622	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2623	return MCDisassembler::Fail;
				2624	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2625
				2626	// Second input register
				2627	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2628	case ARM::VST3d8:
				2629	case ARM::VST3d16:
				2630	case ARM::VST3d32:
				2631	case ARM::VST3d8_UPD:
				2632	case ARM::VST3d16_UPD:
				2633	case ARM::VST3d32_UPD:
				2634	case ARM::VST4d8:
				2635	case ARM::VST4d16:
				2636	case ARM::VST4d32:
				2637	case ARM::VST4d8_UPD:
				2638	case ARM::VST4d16_UPD:
				2639	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2640	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2641	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2642	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2643	case ARM::VST3q8:
				2644	case ARM::VST3q16:
				2645	case ARM::VST3q32:
				2646	case ARM::VST3q8_UPD:
				2647	case ARM::VST3q16_UPD:
				2648	case ARM::VST3q32_UPD:
				2649	case ARM::VST4q8:
				2650	case ARM::VST4q16:
				2651	case ARM::VST4q32:
				2652	case ARM::VST4q8_UPD:
				2653	case ARM::VST4q16_UPD:
				2654	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2655	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2656	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2657	break;
				2658	default:
				2659	break;
				2660	}
				2661
				2662	// Third input register
				2663	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2664	case ARM::VST3d8:
				2665	case ARM::VST3d16:
				2666	case ARM::VST3d32:
				2667	case ARM::VST3d8_UPD:
				2668	case ARM::VST3d16_UPD:
				2669	case ARM::VST3d32_UPD:
				2670	case ARM::VST4d8:
				2671	case ARM::VST4d16:
				2672	case ARM::VST4d32:
				2673	case ARM::VST4d8_UPD:
				2674	case ARM::VST4d16_UPD:
				2675	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2676	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2677	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2678	break;
				2679	case ARM::VST3q8:
				2680	case ARM::VST3q16:
				2681	case ARM::VST3q32:
				2682	case ARM::VST3q8_UPD:
				2683	case ARM::VST3q16_UPD:
				2684	case ARM::VST3q32_UPD:
				2685	case ARM::VST4q8:
				2686	case ARM::VST4q16:
				2687	case ARM::VST4q32:
				2688	case ARM::VST4q8_UPD:
				2689	case ARM::VST4q16_UPD:
				2690	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2691	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2692	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2693	break;
				2694	default:
				2695	break;
				2696	}
				2697
				2698	// Fourth input register
				2699	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2700	case ARM::VST4d8:
				2701	case ARM::VST4d16:
				2702	case ARM::VST4d32:
				2703	case ARM::VST4d8_UPD:
				2704	case ARM::VST4d16_UPD:
				2705	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2706	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2707	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2708	break;
				2709	case ARM::VST4q8:
				2710	case ARM::VST4q16:
				2711	case ARM::VST4q32:
				2712	case ARM::VST4q8_UPD:
				2713	case ARM::VST4q16_UPD:
				2714	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2715	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2716	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2717	break;
				2718	default:
				2719	break;
				2720	}
				2721
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2722	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2723	}
				2724
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2725	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2726	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2727	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2728
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2729	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2730	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2731	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2732	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2733	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2734	unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2735
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	2736	if (size == 0 && align == 1)
				2737	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2738	align *= (1 << size);
				2739
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2740	switch (Inst.getOpcode()) {
				2741	case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
				2742	case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
				2743	case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
				2744	case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
				2745	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2746	return MCDisassembler::Fail;
				2747	break;
				2748	default:
				2749	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2750	return MCDisassembler::Fail;
				2751	break;
				2752	}
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2753	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2754	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2755	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2756	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2757
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2758	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2759	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2760	Inst.addOperand(MCOperand::CreateImm(align));
				2761
Jim Grosbach	a68c9a8	2011-11-30 19:35:44 +0000	[diff] [blame]	2762	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2763	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2764	// increment and we need to add the register operand to the instruction.
				2765	if (Rm != 0xD && Rm != 0xF &&
				2766	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2767	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2768
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2769	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2770	}
				2771
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2772	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2773	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2774	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2775
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2776	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2777	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2778	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2779	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2780	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2781	unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2782	align = 2size;
				2783
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2784	switch (Inst.getOpcode()) {
				2785	case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
				2786	case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
				2787	case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
				2788	case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
				2789	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2790	return MCDisassembler::Fail;
				2791	break;
Jim Grosbach	ed428bc	2012-03-06 23:10:38 +0000	[diff] [blame]	2792	case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
				2793	case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
				2794	case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
				2795	case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
				2796	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2797	return MCDisassembler::Fail;
				2798	break;
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2799	default:
				2800	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2801	return MCDisassembler::Fail;
				2802	break;
				2803	}
Kevin Enderby	520eb3b	2012-03-06 18:33:12 +0000	[diff] [blame]	2804
				2805	if (Rm != 0xF)
				2806	Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2807
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2808	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2809	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2810	Inst.addOperand(MCOperand::CreateImm(align));
				2811
Kevin Enderby	29ae538	2012-04-17 00:49:27 +0000	[diff] [blame]	2812	if (Rm != 0xD && Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2813	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2814	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2815	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2816
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2817	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2818	}
				2819
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2820	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2821	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2822	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2823
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2824	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2825	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2826	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2827	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2828	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2829
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2830	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2831	return MCDisassembler::Fail;
				2832	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2833	return MCDisassembler::Fail;
				2834	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2835	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2836	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2837	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2838	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2839	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2840
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2841	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2842	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2843	Inst.addOperand(MCOperand::CreateImm(0));
				2844
				2845	if (Rm == 0xD)
				2846	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2847	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2848	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2849	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2850	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2851
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2852	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2853	}
				2854
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2855	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2856	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2857	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2858
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2859	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2860	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2861	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2862	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2863	unsigned size = fieldFromInstruction(Insn, 6, 2);
				2864	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
				2865	unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2866
				2867	if (size == 0x3) {
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	2868	if (align == 0)
				2869	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2870	size = 4;
				2871	align = 16;
				2872	} else {
				2873	if (size == 2) {
				2874	size = 1 << size;
				2875	align *= 8;
				2876	} else {
				2877	size = 1 << size;
				2878	align = 4size;
				2879	}
				2880	}
				2881
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2882	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2883	return MCDisassembler::Fail;
				2884	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2885	return MCDisassembler::Fail;
				2886	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2887	return MCDisassembler::Fail;
				2888	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
				2889	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2890	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2891	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2892	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2893	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2894
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2895	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2896	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2897	Inst.addOperand(MCOperand::CreateImm(align));
				2898
				2899	if (Rm == 0xD)
				2900	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2901	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2902	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2903	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2904	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2905
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2906	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2907	}
				2908
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2909	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2910	DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	2911	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2912	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2913
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2914	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2915	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2916	unsigned imm = fieldFromInstruction(Insn, 0, 4);
				2917	imm \|= fieldFromInstruction(Insn, 16, 3) << 4;
				2918	imm \|= fieldFromInstruction(Insn, 24, 1) << 7;
				2919	imm \|= fieldFromInstruction(Insn, 8, 4) << 8;
				2920	imm \|= fieldFromInstruction(Insn, 5, 1) << 12;
				2921	unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2922
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2923	if (Q) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2924	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2925	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2926	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2927	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2928	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2929	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2930
				2931	Inst.addOperand(MCOperand::CreateImm(imm));
				2932
				2933	switch (Inst.getOpcode()) {
				2934	case ARM::VORRiv4i16:
				2935	case ARM::VORRiv2i32:
				2936	case ARM::VBICiv4i16:
				2937	case ARM::VBICiv2i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2938	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2939	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2940	break;
				2941	case ARM::VORRiv8i16:
				2942	case ARM::VORRiv4i32:
				2943	case ARM::VBICiv8i16:
				2944	case ARM::VBICiv4i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2945	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2946	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2947	break;
				2948	default:
				2949	break;
				2950	}
				2951
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2952	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2953	}
				2954
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2955	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2956	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2957	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2958
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2959	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2960	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2961	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2962	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				2963	unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2964
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2965	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2966	return MCDisassembler::Fail;
				2967	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				2968	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2969	Inst.addOperand(MCOperand::CreateImm(8 << size));
				2970
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2971	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2972	}
				2973
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2974	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2975	uint64_t Address, const void *Decoder) {
				2976	Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2977	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2978	}
				2979
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2980	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2981	uint64_t Address, const void *Decoder) {
				2982	Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2983	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2984	}
				2985
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2986	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2987	uint64_t Address, const void *Decoder) {
				2988	Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2989	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2990	}
				2991
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2992	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2993	uint64_t Address, const void *Decoder) {
				2994	Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2995	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2996	}
				2997
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2998	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2999	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3000	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3001
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3002	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3003	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3004	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3005	Rn \|= fieldFromInstruction(Insn, 7, 1) << 4;
				3006	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3007	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3008	unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3009
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3010	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3011	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3012	if (op) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3013	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3014	return MCDisassembler::Fail; // Writeback
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3015	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3016
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	3017	switch (Inst.getOpcode()) {
				3018	case ARM::VTBL2:
				3019	case ARM::VTBX2:
				3020	if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
				3021	return MCDisassembler::Fail;
				3022	break;
				3023	default:
				3024	if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
				3025	return MCDisassembler::Fail;
				3026	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3027
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3028	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3029	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3030
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3031	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3032	}
				3033
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3034	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3035	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3036	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3037
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3038	unsigned dst = fieldFromInstruction(Insn, 8, 3);
				3039	unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3040
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3041	if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
				3042	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3043
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3044	switch(Inst.getOpcode()) {
Owen Anderson	5658b49	2011-08-26 19:39:26 +0000	[diff] [blame]	3045	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3046	return MCDisassembler::Fail;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3047	case ARM::tADR:
Owen Anderson	240d20a	2011-08-26 21:47:57 +0000	[diff] [blame]	3048	break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3049	case ARM::tADDrSPi:
				3050	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3051	break;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3052	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3053
				3054	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3055	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3056	}
				3057
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3058	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3059	uint64_t Address, const void *Decoder) {
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3060	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
				3061	true, 2, Inst, Decoder))
				3062	Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3063	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3064	}
				3065
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3066	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3067	uint64_t Address, const void *Decoder) {
Kevin Enderby	cabbae6	2012-05-04 22:09:52 +0000	[diff] [blame]	3068	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3069	true, 4, Inst, Decoder))
				3070	Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3071	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3072	}
				3073
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3074	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3075	uint64_t Address, const void *Decoder) {
Gordon Keiser	772cf46	2013-03-28 19:22:28 +0000	[diff] [blame]	3076	if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3077	true, 2, Inst, Decoder))
Gordon Keiser	772cf46	2013-03-28 19:22:28 +0000	[diff] [blame]	3078	Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3079	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3080	}
				3081
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3082	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3083	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3084	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3085
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3086	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3087	unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3088
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3089	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3090	return MCDisassembler::Fail;
				3091	if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3092	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3093
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3094	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3095	}
				3096
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3097	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3098	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3099	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3100
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3101	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3102	unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3103
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3104	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3105	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3106	Inst.addOperand(MCOperand::CreateImm(imm));
				3107
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3108	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3109	}
				3110
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3111	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3112	uint64_t Address, const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3113	unsigned imm = Val << 2;
				3114
				3115	Inst.addOperand(MCOperand::CreateImm(imm));
				3116	tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3117
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3118	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3119	}
				3120
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3121	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3122	uint64_t Address, const void *Decoder) {
				3123	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	b498132	2011-08-22 17:56:58 +0000	[diff] [blame]	3124	Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3125
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3126	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3127	}
				3128
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3129	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3130	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3131	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3132
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3133	unsigned Rn = fieldFromInstruction(Val, 6, 4);
				3134	unsigned Rm = fieldFromInstruction(Val, 2, 4);
				3135	unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3136
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3137	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3138	return MCDisassembler::Fail;
				3139	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3140	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3141	Inst.addOperand(MCOperand::CreateImm(imm));
				3142
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3143	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3144	}
				3145
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3146	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3147	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3148	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3149
Owen Anderson	924bcfc	2011-08-23 17:51:38 +0000	[diff] [blame]	3150	switch (Inst.getOpcode()) {
				3151	case ARM::t2PLDs:
				3152	case ARM::t2PLDWs:
				3153	case ARM::t2PLIs:
				3154	break;
				3155	default: {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3156	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Owen Anderson	987a878	2011-09-23 21:07:25 +0000	[diff] [blame]	3157	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3158	return MCDisassembler::Fail;
Owen Anderson	924bcfc	2011-08-23 17:51:38 +0000	[diff] [blame]	3159	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3160	}
				3161
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3162	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3163	if (Rn == 0xF) {
				3164	switch (Inst.getOpcode()) {
				3165	case ARM::t2LDRBs:
				3166	Inst.setOpcode(ARM::t2LDRBpci);
				3167	break;
				3168	case ARM::t2LDRHs:
				3169	Inst.setOpcode(ARM::t2LDRHpci);
				3170	break;
				3171	case ARM::t2LDRSHs:
				3172	Inst.setOpcode(ARM::t2LDRSHpci);
				3173	break;
				3174	case ARM::t2LDRSBs:
				3175	Inst.setOpcode(ARM::t2LDRSBpci);
				3176	break;
				3177	case ARM::t2PLDs:
				3178	Inst.setOpcode(ARM::t2PLDi12);
				3179	Inst.addOperand(MCOperand::CreateReg(ARM::PC));
				3180	break;
				3181	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3182	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3183	}
				3184
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3185	int imm = fieldFromInstruction(Insn, 0, 12);
				3186	if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3187	Inst.addOperand(MCOperand::CreateImm(imm));
				3188
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3189	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3190	}
				3191
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3192	unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
				3193	addrmode \|= fieldFromInstruction(Insn, 0, 4) << 2;
				3194	addrmode \|= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3195	if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
				3196	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3197
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3198	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3199	}
				3200
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3201	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3202	uint64_t Address, const void *Decoder) {
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3203	if (Val == 0)
				3204	Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
				3205	else {
				3206	int imm = Val & 0xFF;
				3207
				3208	if (!(Val & 0x100)) imm *= -1;
Richard Smith	228e6d4	2012-08-24 23:29:28 +0000	[diff] [blame]	3209	Inst.addOperand(MCOperand::CreateImm(imm * 4));
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3210	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3211
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3212	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3213	}
				3214
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3215	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3216	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3217	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3218
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3219	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3220	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3221
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3222	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3223	return MCDisassembler::Fail;
				3224	if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
				3225	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3226
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3227	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3228	}
				3229
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3230	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3231	uint64_t Address, const void *Decoder) {
				3232	DecodeStatus S = MCDisassembler::Success;
				3233
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3234	unsigned Rn = fieldFromInstruction(Val, 8, 4);
				3235	unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3236
				3237	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				3238	return MCDisassembler::Fail;
				3239
				3240	Inst.addOperand(MCOperand::CreateImm(imm));
				3241
				3242	return S;
				3243	}
				3244
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3245	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3246	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3247	int imm = Val & 0xFF;
Owen Anderson	fe82365	2011-09-16 21:08:33 +0000	[diff] [blame]	3248	if (Val == 0)
				3249	imm = INT32_MIN;
				3250	else if (!(Val & 0x100))
				3251	imm *= -1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3252	Inst.addOperand(MCOperand::CreateImm(imm));
				3253
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3254	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3255	}
				3256
				3257
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3258	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3259	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3260	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3261
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3262	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3263	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3264
				3265	// Some instructions always use an additive offset.
				3266	switch (Inst.getOpcode()) {
				3267	case ARM::t2LDRT:
				3268	case ARM::t2LDRBT:
				3269	case ARM::t2LDRHT:
				3270	case ARM::t2LDRSBT:
				3271	case ARM::t2LDRSHT:
Owen Anderson	ddfcec9	2011-09-19 18:07:10 +0000	[diff] [blame]	3272	case ARM::t2STRT:
				3273	case ARM::t2STRBT:
				3274	case ARM::t2STRHT:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3275	imm \|= 0x100;
				3276	break;
				3277	default:
				3278	break;
				3279	}
				3280
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3281	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3282	return MCDisassembler::Fail;
				3283	if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
				3284	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3285
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3286	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3287	}
				3288
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3289	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3290	uint64_t Address, const void *Decoder) {
				3291	DecodeStatus S = MCDisassembler::Success;
				3292
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3293	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3294	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3295	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				3296	addr \|= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3297	addr \|= Rn << 9;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3298	unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3299
				3300	if (!load) {
				3301	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3302	return MCDisassembler::Fail;
				3303	}
				3304
Joe Abbey	f686be4	2013-03-26 13:58:53 +0000	[diff] [blame]	3305	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3306	return MCDisassembler::Fail;
				3307
				3308	if (load) {
				3309	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3310	return MCDisassembler::Fail;
				3311	}
				3312
				3313	if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
				3314	return MCDisassembler::Fail;
				3315
				3316	return S;
				3317	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3318
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3319	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3320	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3321	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3322
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3323	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				3324	unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3325
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3326	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3327	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3328	Inst.addOperand(MCOperand::CreateImm(imm));
				3329
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3330	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3331	}
				3332
				3333
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3334	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3335	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3336	unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3337
				3338	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3339	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3340	Inst.addOperand(MCOperand::CreateImm(imm));
				3341
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3342	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3343	}
				3344
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3345	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3346	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3347	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3348
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3349	if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3350	unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
				3351	Rdm \|= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3352
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3353	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3354	return MCDisassembler::Fail;
Jim Grosbach	9d8f6f3	2012-04-27 23:51:33 +0000	[diff] [blame]	3355	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3356	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3357	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3358	} else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3359	unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3360
				3361	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3362	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3363	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3364	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3365	}
				3366
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3367	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3368	}
				3369
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3370	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3371	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3372	unsigned imod = fieldFromInstruction(Insn, 4, 1) \| 0x2;
				3373	unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3374
				3375	Inst.addOperand(MCOperand::CreateImm(imod));
				3376	Inst.addOperand(MCOperand::CreateImm(flags));
				3377
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3378	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3379	}
				3380
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3381	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3382	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3383	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3384	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3385	unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3386
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	3387	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3388	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3389	Inst.addOperand(MCOperand::CreateImm(add));
				3390
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3391	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3392	}
				3393
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3394	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3395	uint64_t Address, const void *Decoder) {
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3396	// Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3397	// Note only one trailing zero not two. Also the J1 and J2 values are from
				3398	// the encoded instruction. So here change to I1 and I2 values via:
				3399	// I1 = NOT(J1 EOR S);
				3400	// I2 = NOT(J2 EOR S);
				3401	// and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3402	// imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3403	unsigned S = (Val >> 23) & 1;
				3404	unsigned J1 = (Val >> 22) & 1;
				3405	unsigned J2 = (Val >> 21) & 1;
				3406	unsigned I1 = !(J1 ^ S);
				3407	unsigned I2 = !(J2 ^ S);
				3408	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3409	int imm32 = SignExtend32<25>(tmp << 1);
				3410
Jim Grosbach	79ebc51	2011-10-20 17:28:20 +0000	[diff] [blame]	3411	if (!tryAddingSymbolicOperand(Address,
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3412	(Address & ~2u) + imm32 + 4,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3413	true, 4, Inst, Decoder))
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3414	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3415	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3416	}
				3417
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3418	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3419	uint64_t Address, const void *Decoder) {
				3420	if (Val == 0xA \|\| Val == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3421	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3422
				3423	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3424	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3425	}
				3426
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3427	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3428	DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3429	uint64_t Address, const void *Decoder) {
				3430	DecodeStatus S = MCDisassembler::Success;
				3431
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3432	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3433	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3434
				3435	if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
				3436	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3437	return MCDisassembler::Fail;
				3438	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3439	return MCDisassembler::Fail;
				3440	return S;
				3441	}
				3442
				3443	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3444	DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3445	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3446	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3447
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3448	unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3449	if (pred == 0xE \|\| pred == 0xF) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3450	unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3451	switch (opc) {
				3452	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3453	return MCDisassembler::Fail;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3454	case 0xf3bf8f4:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3455	Inst.setOpcode(ARM::t2DSB);
				3456	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3457	case 0xf3bf8f5:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3458	Inst.setOpcode(ARM::t2DMB);
				3459	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3460	case 0xf3bf8f6:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3461	Inst.setOpcode(ARM::t2ISB);
Owen Anderson	cd5612d	2011-09-07 17:55:19 +0000	[diff] [blame]	3462	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3463	}
				3464
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3465	unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3466	return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3467	}
				3468
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3469	unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
				3470	brtarget \|= fieldFromInstruction(Insn, 11, 1) << 19;
				3471	brtarget \|= fieldFromInstruction(Insn, 13, 1) << 18;
				3472	brtarget \|= fieldFromInstruction(Insn, 16, 6) << 12;
				3473	brtarget \|= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3474
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3475	if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
				3476	return MCDisassembler::Fail;
				3477	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3478	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3479
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3480	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3481	}
				3482
				3483	// Decode a shifted immediate operand. These basically consist
				3484	// of an 8-bit value, and a 4-bit directive that specifies either
				3485	// a splat operation or a rotation.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3486	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3487	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3488	unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3489	if (ctrl == 0) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3490	unsigned byte = fieldFromInstruction(Val, 8, 2);
				3491	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3492	switch (byte) {
				3493	case 0:
				3494	Inst.addOperand(MCOperand::CreateImm(imm));
				3495	break;
				3496	case 1:
				3497	Inst.addOperand(MCOperand::CreateImm((imm << 16) \| imm));
				3498	break;
				3499	case 2:
				3500	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 8)));
				3501	break;
				3502	case 3:
				3503	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 16) \|
				3504	(imm << 8) \| imm));
				3505	break;
				3506	}
				3507	} else {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3508	unsigned unrot = fieldFromInstruction(Val, 0, 7) \| 0x80;
				3509	unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3510	unsigned imm = (unrot >> rot) \| (unrot << ((32-rot)&31));
				3511	Inst.addOperand(MCOperand::CreateImm(imm));
				3512	}
				3513
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3514	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3515	}
				3516
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3517	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3518	DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3519	uint64_t Address, const void *Decoder){
Richard Barton	f1ef87d	2012-06-06 09:12:53 +0000	[diff] [blame]	3520	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3521	true, 2, Inst, Decoder))
Richard Barton	f1ef87d	2012-06-06 09:12:53 +0000	[diff] [blame]	3522	Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3523	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3524	}
				3525
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3526	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3527	uint64_t Address, const void *Decoder){
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3528	// Val is passed in as S:J1:J2:imm10:imm11
				3529	// Note no trailing zero after imm11. Also the J1 and J2 values are from
				3530	// the encoded instruction. So here change to I1 and I2 values via:
				3531	// I1 = NOT(J1 EOR S);
				3532	// I2 = NOT(J2 EOR S);
				3533	// and build the imm32 with one trailing zero as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3534	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3535	unsigned S = (Val >> 23) & 1;
				3536	unsigned J1 = (Val >> 22) & 1;
				3537	unsigned J2 = (Val >> 21) & 1;
				3538	unsigned I1 = !(J1 ^ S);
				3539	unsigned I2 = !(J2 ^ S);
				3540	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3541	int imm32 = SignExtend32<25>(tmp << 1);
				3542
				3543	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	3544	true, 4, Inst, Decoder))
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3545	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3546	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3547	}
				3548
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3549	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3550	uint64_t Address, const void *Decoder) {
Jiangning Liu	288e1af	2012-08-02 08:21:27 +0000	[diff] [blame]	3551	if (Val & ~0xf)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3552	return MCDisassembler::Fail;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3553
				3554	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3555	return MCDisassembler::Success;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3556	}
				3557
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame^]	3558	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
				3559	uint64_t Address, const void *Decoder) {
				3560	if (Val & ~0xf)
				3561	return MCDisassembler::Fail;
				3562
				3563	Inst.addOperand(MCOperand::CreateImm(Val));
				3564	return MCDisassembler::Success;
				3565	}
				3566
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3567	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	3568	uint64_t Address, const void *Decoder) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3569	if (!Val) return MCDisassembler::Fail;
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	3570	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3571	return MCDisassembler::Success;
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	3572	}
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	3573
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3574	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3575	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3576	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3577
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3578	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3579	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3580	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	3581
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3582	if ((Rt & 1) \|\| Rt == 0xE \|\| Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	3583
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3584	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3585	return MCDisassembler::Fail;
				3586	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				3587	return MCDisassembler::Fail;
				3588	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3589	return MCDisassembler::Fail;
				3590	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3591	return MCDisassembler::Fail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	3592
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3593	return S;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	3594	}
				3595
				3596
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3597	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3598	uint64_t Address, const void *Decoder){
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3599	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3600
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3601	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3602	unsigned Rt = fieldFromInstruction(Insn, 0, 4);
				3603	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3604	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	3605
Tim Northover	27ff504	2013-04-19 15:44:32 +0000	[diff] [blame]	3606	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3607	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	3608
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3609	if ((Rt & 1) \|\| Rt == 0xE \|\| Rn == 0xF) return MCDisassembler::Fail;
				3610	if (Rd == Rn \|\| Rd == Rt \|\| Rd == Rt+1) return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	3611
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3612	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3613	return MCDisassembler::Fail;
				3614	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				3615	return MCDisassembler::Fail;
				3616	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3617	return MCDisassembler::Fail;
				3618	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3619	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	3620
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3621	return S;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	3622	}
				3623
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3624	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	3625	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3626	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	3627
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3628	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3629	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3630	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3631	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3632	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3633	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	3634
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3635	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	3636
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3637	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3638	return MCDisassembler::Fail;
				3639	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3640	return MCDisassembler::Fail;
				3641	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				3642	return MCDisassembler::Fail;
				3643	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3644	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	3645
				3646	return S;
				3647	}
				3648
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3649	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	3650	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3651	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	3652
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3653	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3654	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3655	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3656	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3657	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3658	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				3659	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	3660
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3661	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
				3662	if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	3663
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3664	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3665	return MCDisassembler::Fail;
				3666	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3667	return MCDisassembler::Fail;
				3668	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				3669	return MCDisassembler::Fail;
				3670	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3671	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	3672
				3673	return S;
				3674	}
				3675
				3676
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3677	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	3678	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3679	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3680
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3681	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3682	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3683	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3684	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3685	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3686	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	3687
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3688	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	3689
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3690	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3691	return MCDisassembler::Fail;
				3692	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3693	return MCDisassembler::Fail;
				3694	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				3695	return MCDisassembler::Fail;
				3696	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3697	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	3698
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3699	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	3700	}
				3701
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3702	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	3703	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3704	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3705
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3706	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3707	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3708	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3709	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3710	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3711	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	3712
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3713	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	3714
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3715	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3716	return MCDisassembler::Fail;
				3717	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3718	return MCDisassembler::Fail;
				3719	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				3720	return MCDisassembler::Fail;
				3721	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3722	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	3723
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3724	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	3725	}
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3726
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3727	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3728	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3729	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3730
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3731	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3732	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3733	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3734	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3735	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3736
				3737	unsigned align = 0;
				3738	unsigned index = 0;
				3739	switch (size) {
				3740	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3741	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3742	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3743	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3744	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3745	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3746	break;
				3747	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3748	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3749	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3750	index = fieldFromInstruction(Insn, 6, 2);
				3751	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3752	align = 2;
				3753	break;
				3754	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3755	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3756	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3757	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	3758
				3759	switch (fieldFromInstruction(Insn, 4, 2)) {
				3760	case 0 :
				3761	align = 0; break;
				3762	case 3:
				3763	align = 4; break;
				3764	default:
				3765	return MCDisassembler::Fail;
				3766	}
				3767	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3768	}
				3769
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3770	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3771	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3772	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3773	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3774	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3775	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3776	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3777	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3778	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	3779	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3780	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3781	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3782	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3783	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	3784	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3785	}
				3786
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3787	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3788	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3789	Inst.addOperand(MCOperand::CreateImm(index));
				3790
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3791	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3792	}
				3793
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3794	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3795	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3796	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3797
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3798	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3799	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3800	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3801	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3802	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3803
				3804	unsigned align = 0;
				3805	unsigned index = 0;
				3806	switch (size) {
				3807	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3808	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3809	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3810	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3811	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3812	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3813	break;
				3814	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3815	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3816	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3817	index = fieldFromInstruction(Insn, 6, 2);
				3818	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3819	align = 2;
				3820	break;
				3821	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3822	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3823	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3824	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	3825
				3826	switch (fieldFromInstruction(Insn, 4, 2)) {
				3827	case 0:
				3828	align = 0; break;
				3829	case 3:
				3830	align = 4; break;
				3831	default:
				3832	return MCDisassembler::Fail;
				3833	}
				3834	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3835	}
				3836
				3837	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3838	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3839	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3840	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3841	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3842	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3843	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	3844	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3845	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3846	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3847	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3848	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	3849	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3850	}
				3851
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3852	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3853	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3854	Inst.addOperand(MCOperand::CreateImm(index));
				3855
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3856	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3857	}
				3858
				3859
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3860	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3861	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3862	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3863
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3864	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3865	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3866	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3867	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3868	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3869
				3870	unsigned align = 0;
				3871	unsigned index = 0;
				3872	unsigned inc = 1;
				3873	switch (size) {
				3874	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3875	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3876	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3877	index = fieldFromInstruction(Insn, 5, 3);
				3878	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3879	align = 2;
				3880	break;
				3881	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3882	index = fieldFromInstruction(Insn, 6, 2);
				3883	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3884	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3885	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3886	inc = 2;
				3887	break;
				3888	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3889	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3890	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3891	index = fieldFromInstruction(Insn, 7, 1);
				3892	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3893	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3894	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3895	inc = 2;
				3896	break;
				3897	}
				3898
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3899	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3900	return MCDisassembler::Fail;
				3901	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3902	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3903	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3904	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3905	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3906	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3907	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3908	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3909	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	3910	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3911	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3912	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3913	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3914	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	3915	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3916	}
				3917
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3918	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3919	return MCDisassembler::Fail;
				3920	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3921	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3922	Inst.addOperand(MCOperand::CreateImm(index));
				3923
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3924	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3925	}
				3926
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3927	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3928	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3929	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3930
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3931	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3932	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3933	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3934	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3935	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3936
				3937	unsigned align = 0;
				3938	unsigned index = 0;
				3939	unsigned inc = 1;
				3940	switch (size) {
				3941	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3942	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3943	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3944	index = fieldFromInstruction(Insn, 5, 3);
				3945	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3946	align = 2;
				3947	break;
				3948	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3949	index = fieldFromInstruction(Insn, 6, 2);
				3950	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3951	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3952	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3953	inc = 2;
				3954	break;
				3955	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3956	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3957	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3958	index = fieldFromInstruction(Insn, 7, 1);
				3959	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3960	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3961	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3962	inc = 2;
				3963	break;
				3964	}
				3965
				3966	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3967	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3968	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3969	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3970	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3971	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3972	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	3973	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3974	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3975	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3976	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3977	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	3978	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3979	}
				3980
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3981	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3982	return MCDisassembler::Fail;
				3983	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3984	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3985	Inst.addOperand(MCOperand::CreateImm(index));
				3986
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3987	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3988	}
				3989
				3990
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3991	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	3992	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3993	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3994
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3995	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3996	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3997	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3998	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3999	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4000
				4001	unsigned align = 0;
				4002	unsigned index = 0;
				4003	unsigned inc = 1;
				4004	switch (size) {
				4005	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4006	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4007	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4008	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4009	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4010	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4011	break;
				4012	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4013	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4014	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4015	index = fieldFromInstruction(Insn, 6, 2);
				4016	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4017	inc = 2;
				4018	break;
				4019	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4020	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4021	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4022	index = fieldFromInstruction(Insn, 7, 1);
				4023	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4024	inc = 2;
				4025	break;
				4026	}
				4027
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4028	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4029	return MCDisassembler::Fail;
				4030	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4031	return MCDisassembler::Fail;
				4032	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4033	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4034
				4035	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4036	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4037	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4038	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4039	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4040	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4041	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4042	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4043	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4044	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4045	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4046	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4047	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4048	}
				4049
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4050	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4051	return MCDisassembler::Fail;
				4052	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4053	return MCDisassembler::Fail;
				4054	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4055	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4056	Inst.addOperand(MCOperand::CreateImm(index));
				4057
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4058	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4059	}
				4060
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4061	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4062	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4063	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4064
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4065	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4066	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4067	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4068	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4069	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4070
				4071	unsigned align = 0;
				4072	unsigned index = 0;
				4073	unsigned inc = 1;
				4074	switch (size) {
				4075	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4076	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4077	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4078	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4079	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4080	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4081	break;
				4082	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4083	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4084	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4085	index = fieldFromInstruction(Insn, 6, 2);
				4086	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4087	inc = 2;
				4088	break;
				4089	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4090	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4091	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4092	index = fieldFromInstruction(Insn, 7, 1);
				4093	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4094	inc = 2;
				4095	break;
				4096	}
				4097
				4098	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4099	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4100	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4101	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4102	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4103	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4104	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4105	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4106	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4107	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4108	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4109	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4110	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4111	}
				4112
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4113	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4114	return MCDisassembler::Fail;
				4115	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4116	return MCDisassembler::Fail;
				4117	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4118	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4119	Inst.addOperand(MCOperand::CreateImm(index));
				4120
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4121	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4122	}
				4123
				4124
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4125	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4126	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4127	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4128
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4129	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4130	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4131	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4132	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4133	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4134
				4135	unsigned align = 0;
				4136	unsigned index = 0;
				4137	unsigned inc = 1;
				4138	switch (size) {
				4139	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4140	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4141	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4142	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4143	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4144	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4145	break;
				4146	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4147	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4148	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4149	index = fieldFromInstruction(Insn, 6, 2);
				4150	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4151	inc = 2;
				4152	break;
				4153	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4154	switch (fieldFromInstruction(Insn, 4, 2)) {
				4155	case 0:
				4156	align = 0; break;
				4157	case 3:
				4158	return MCDisassembler::Fail;
				4159	default:
				4160	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4161	}
				4162
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4163	index = fieldFromInstruction(Insn, 7, 1);
				4164	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4165	inc = 2;
				4166	break;
				4167	}
				4168
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4169	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4170	return MCDisassembler::Fail;
				4171	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4172	return MCDisassembler::Fail;
				4173	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4174	return MCDisassembler::Fail;
				4175	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4176	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4177
				4178	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4179	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4180	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4181	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4182	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4183	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4184	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4185	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4186	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4187	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4188	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4189	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4190	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4191	}
				4192
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4193	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4194	return MCDisassembler::Fail;
				4195	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4196	return MCDisassembler::Fail;
				4197	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4198	return MCDisassembler::Fail;
				4199	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4200	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4201	Inst.addOperand(MCOperand::CreateImm(index));
				4202
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4203	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4204	}
				4205
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4206	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4207	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4208	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4209
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4210	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4211	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4212	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4213	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4214	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4215
				4216	unsigned align = 0;
				4217	unsigned index = 0;
				4218	unsigned inc = 1;
				4219	switch (size) {
				4220	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4221	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4222	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4223	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4224	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4225	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4226	break;
				4227	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4228	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4229	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4230	index = fieldFromInstruction(Insn, 6, 2);
				4231	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4232	inc = 2;
				4233	break;
				4234	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4235	switch (fieldFromInstruction(Insn, 4, 2)) {
				4236	case 0:
				4237	align = 0; break;
				4238	case 3:
				4239	return MCDisassembler::Fail;
				4240	default:
				4241	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4242	}
				4243
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4244	index = fieldFromInstruction(Insn, 7, 1);
				4245	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4246	inc = 2;
				4247	break;
				4248	}
				4249
				4250	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4251	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4252	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4253	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4254	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4255	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4256	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4257	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4258	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4259	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4260	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4261	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4262	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4263	}
				4264
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4265	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4266	return MCDisassembler::Fail;
				4267	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4268	return MCDisassembler::Fail;
				4269	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4270	return MCDisassembler::Fail;
				4271	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4272	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4273	Inst.addOperand(MCOperand::CreateImm(index));
				4274
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4275	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4276	}
				4277
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4278	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4279	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4280	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4281	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4282	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4283	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4284	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4285	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4286
				4287	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4288	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4289
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4290	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4291	return MCDisassembler::Fail;
				4292	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4293	return MCDisassembler::Fail;
				4294	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4295	return MCDisassembler::Fail;
				4296	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4297	return MCDisassembler::Fail;
				4298	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4299	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4300
				4301	return S;
				4302	}
				4303
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4304	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4305	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4306	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4307	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4308	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4309	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4310	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4311	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4312
				4313	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4314	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4315
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4316	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4317	return MCDisassembler::Fail;
				4318	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4319	return MCDisassembler::Fail;
				4320	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4321	return MCDisassembler::Fail;
				4322	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4323	return MCDisassembler::Fail;
				4324	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4325	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4326
				4327	return S;
				4328	}
Owen Anderson	eb1367b	2011-08-22 23:44:04 +0000	[diff] [blame]	4329
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4330	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4331	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4332	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4333	unsigned pred = fieldFromInstruction(Insn, 4, 4);
				4334	unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4335
				4336	if (pred == 0xF) {
				4337	pred = 0xE;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4338	S = MCDisassembler::SoftFail;
Owen Anderson	5230041	2011-08-24 17:21:43 +0000	[diff] [blame]	4339	}
				4340
Richard Barton	f435b09	2012-04-27 08:42:59 +0000	[diff] [blame]	4341	if (mask == 0x0) {
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4342	mask \|= 0x8;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4343	S = MCDisassembler::SoftFail;
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	4344	}
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4345
				4346	Inst.addOperand(MCOperand::CreateImm(pred));
				4347	Inst.addOperand(MCOperand::CreateImm(mask));
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	4348	return S;
				4349	}
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4350
				4351	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4352	DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4353	uint64_t Address, const void *Decoder) {
				4354	DecodeStatus S = MCDisassembler::Success;
				4355
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4356	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4357	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4358	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4359	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4360	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4361	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4362	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4363	bool writeback = (W == 1) \| (P == 0);
				4364
				4365	addr \|= (U << 8) \| (Rn << 9);
				4366
				4367	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4368	Check(S, MCDisassembler::SoftFail);
				4369	if (Rt == Rt2)
				4370	Check(S, MCDisassembler::SoftFail);
				4371
				4372	// Rt
				4373	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4374	return MCDisassembler::Fail;
				4375	// Rt2
				4376	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4377	return MCDisassembler::Fail;
				4378	// Writeback operand
				4379	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4380	return MCDisassembler::Fail;
				4381	// addr
				4382	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4383	return MCDisassembler::Fail;
				4384
				4385	return S;
				4386	}
				4387
				4388	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4389	DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4390	uint64_t Address, const void *Decoder) {
				4391	DecodeStatus S = MCDisassembler::Success;
				4392
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4393	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4394	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4395	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4396	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4397	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4398	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4399	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4400	bool writeback = (W == 1) \| (P == 0);
				4401
				4402	addr \|= (U << 8) \| (Rn << 9);
				4403
				4404	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4405	Check(S, MCDisassembler::SoftFail);
				4406
				4407	// Writeback operand
				4408	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4409	return MCDisassembler::Fail;
				4410	// Rt
				4411	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4412	return MCDisassembler::Fail;
				4413	// Rt2
				4414	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4415	return MCDisassembler::Fail;
				4416	// addr
				4417	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4418	return MCDisassembler::Fail;
				4419
				4420	return S;
				4421	}
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4422
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4423	static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4424	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4425	unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
				4426	unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4427	if (sign1 != sign2) return MCDisassembler::Fail;
				4428
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4429	unsigned Val = fieldFromInstruction(Insn, 0, 8);
				4430	Val \|= fieldFromInstruction(Insn, 12, 3) << 8;
				4431	Val \|= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4432	Val \|= sign1 << 12;
				4433	Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
				4434
				4435	return MCDisassembler::Success;
				4436	}
				4437
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4438	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	4439	uint64_t Address,
				4440	const void *Decoder) {
				4441	DecodeStatus S = MCDisassembler::Success;
				4442
				4443	// Shift of "asr #32" is not allowed in Thumb2 mode.
				4444	if (Val == 0x20) S = MCDisassembler::SoftFail;
				4445	Inst.addOperand(MCOperand::CreateImm(Val));
				4446	return S;
				4447	}
				4448
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4449	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	4450	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4451	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4452	unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
				4453	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4454	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	4455
				4456	if (pred == 0xF)
				4457	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				4458
				4459	DecodeStatus S = MCDisassembler::Success;
Silviu Baranga	ca45af9	2012-04-18 14:18:57 +0000	[diff] [blame]	4460
				4461	if (Rt == Rn \|\| Rn == Rt2)
				4462	S = MCDisassembler::SoftFail;
				4463
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	4464	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4465	return MCDisassembler::Fail;
				4466	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				4467	return MCDisassembler::Fail;
				4468	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				4469	return MCDisassembler::Fail;
				4470	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4471	return MCDisassembler::Fail;
				4472
				4473	return S;
				4474	}
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4475
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4476	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4477	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4478	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4479	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4480	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4481	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4482	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4483	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4484	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4485
				4486	DecodeStatus S = MCDisassembler::Success;
				4487
				4488	// VMOVv2f32 is ambiguous with these decodings.
Owen Anderson	05060f0	2011-11-15 20:30:41 +0000	[diff] [blame]	4489	if (!(imm & 0x38) && cmode == 0xF) {
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4490	if (op == 1) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4491	Inst.setOpcode(ARM::VMOVv2f32);
				4492	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				4493	}
				4494
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	4495	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4496
				4497	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				4498	return MCDisassembler::Fail;
				4499	if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
				4500	return MCDisassembler::Fail;
				4501	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				4502
				4503	return S;
				4504	}
				4505
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4506	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4507	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4508	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4509	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4510	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4511	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4512	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4513	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4514	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4515
				4516	DecodeStatus S = MCDisassembler::Success;
				4517
				4518	// VMOVv4f32 is ambiguous with these decodings.
				4519	if (!(imm & 0x38) && cmode == 0xF) {
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4520	if (op == 1) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4521	Inst.setOpcode(ARM::VMOVv4f32);
				4522	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				4523	}
				4524
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	4525	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4526
				4527	if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
				4528	return MCDisassembler::Fail;
				4529	if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
				4530	return MCDisassembler::Fail;
				4531	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				4532
				4533	return S;
				4534	}
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	4535
Quentin Colombet	6f03f62	2013-04-17 18:46:12 +0000	[diff] [blame]	4536	static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
				4537	const void *Decoder)
				4538	{
				4539	unsigned Imm = fieldFromInstruction(Insn, 0, 3);
				4540	if (Imm > 4) return MCDisassembler::Fail;
				4541	Inst.addOperand(MCOperand::CreateImm(Imm));
				4542	return MCDisassembler::Success;
				4543	}
				4544
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4545	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	4546	uint64_t Address, const void *Decoder) {
				4547	DecodeStatus S = MCDisassembler::Success;
				4548
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4549	unsigned Rn = fieldFromInstruction(Val, 16, 4);
				4550	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				4551	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				4552	Rm \|= (fieldFromInstruction(Val, 23, 1) << 4);
				4553	unsigned Cond = fieldFromInstruction(Val, 28, 4);
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	4554
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4555	if (fieldFromInstruction(Val, 8, 4) != 0 \|\| Rn == Rt)
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	4556	S = MCDisassembler::SoftFail;
				4557
				4558	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4559	return MCDisassembler::Fail;
				4560	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				4561	return MCDisassembler::Fail;
				4562	if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
				4563	return MCDisassembler::Fail;
				4564	if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
				4565	return MCDisassembler::Fail;
				4566	if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
				4567	return MCDisassembler::Fail;
				4568
				4569	return S;
				4570	}
				4571
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	4572	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				4573	uint64_t Address, const void *Decoder) {
				4574
				4575	DecodeStatus S = MCDisassembler::Success;
				4576
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4577	unsigned CRm = fieldFromInstruction(Val, 0, 4);
				4578	unsigned opc1 = fieldFromInstruction(Val, 4, 4);
				4579	unsigned cop = fieldFromInstruction(Val, 8, 4);
				4580	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				4581	unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	4582
				4583	if ((cop & ~0x1) == 0xa)
				4584	return MCDisassembler::Fail;
				4585
				4586	if (Rt == Rt2)
				4587	S = MCDisassembler::SoftFail;
				4588
				4589	Inst.addOperand(MCOperand::CreateImm(cop));
				4590	Inst.addOperand(MCOperand::CreateImm(opc1));
				4591	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4592	return MCDisassembler::Fail;
				4593	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				4594	return MCDisassembler::Fail;
				4595	Inst.addOperand(MCOperand::CreateImm(CRm));
				4596
				4597	return S;
				4598	}
				4599