Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / b81495dccb2977e8861fa40e0b38657b46f148e6 / . / llvm / lib / Target / AMDGPU / DSInstructions.td
blob: e66bf402178b0ad331a824832ef888411b8eea64 [file] [log] [blame]
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]1//===-- DSInstructions.td - DS Instruction Defintions ---------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
11 InstSI <outs, ins, "", pattern>,
12 SIMCInstr <opName, SIEncodingFamily.NONE> {
13
14 let SubtargetPredicate = isGCN;
15
16 let LGKM_CNT = 1;
17 let DS = 1;
Matt Arsenault10c17ca2016-10-06 10:13:23 +0000[diff] [blame]18 let Size = 8;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]19 let UseNamedOperandTable = 1;
20 let Uses = [M0, EXEC];
21
22 // Most instruction load and store data, so set this as the default.
23 let mayLoad = 1;
24 let mayStore = 1;
25
26 let hasSideEffects = 0;
27 let SchedRW = [WriteLDS];
28
29 let isPseudo = 1;
30 let isCodeGenOnly = 1;
31
32 let AsmMatchConverter = "cvtDS";
33
34 string Mnemonic = opName;
35 string AsmOperands = asmOps;
36
37 // Well these bits a kind of hack because it would be more natural
38 // to test "outs" and "ins" dags for the presence of particular operands
39 bits<1> has_vdst = 1;
40 bits<1> has_addr = 1;
41 bits<1> has_data0 = 1;
42 bits<1> has_data1 = 1;
43
44 bits<1> has_offset = 1; // has "offset" that should be split to offset0,1
45 bits<1> has_offset0 = 1;
46 bits<1> has_offset1 = 1;
47
48 bits<1> has_gds = 1;
49 bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
50}
51
52class DS_Real <DS_Pseudo ds> :
53 InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
54 Enc64 {
55
56 let isPseudo = 0;
57 let isCodeGenOnly = 0;
58
59 // copy relevant pseudo op flags
60 let SubtargetPredicate = ds.SubtargetPredicate;
61 let AsmMatchConverter = ds.AsmMatchConverter;
62
63 // encoding fields
64 bits<8> vdst;
65 bits<1> gds;
66 bits<8> addr;
67 bits<8> data0;
68 bits<8> data1;
69 bits<8> offset0;
70 bits<8> offset1;
71
72 bits<16> offset;
73 let offset0 = !if(ds.has_offset, offset{7-0}, ?);
74 let offset1 = !if(ds.has_offset, offset{15-8}, ?);
75}
76
77
78// DS Pseudo instructions
79
80class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
81: DS_Pseudo<opName,
82 (outs),
83 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
84 "$addr, $data0$offset$gds">,
85 AtomicNoRet<opName, 0> {
86
87 let has_data1 = 0;
88 let has_vdst = 0;
89}
90
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]91class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]92: DS_Pseudo<opName,
93 (outs),
94 (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
95 "$addr, $data0, $data1"#"$offset"#"$gds">,
96 AtomicNoRet<opName, 0> {
97
98 let has_vdst = 0;
99}
100
101class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32>
102: DS_Pseudo<opName,
103 (outs),
104 (ins VGPR_32:$addr, rc:$data0, rc:$data1,
105 offset0:$offset0, offset1:$offset1, gds:$gds),
106 "$addr, $data0, $data1$offset0$offset1$gds"> {
107
108 let has_vdst = 0;
109 let has_offset = 0;
110 let AsmMatchConverter = "cvtDSOffset01";
111}
112
113class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
114: DS_Pseudo<opName,
115 (outs rc:$vdst),
116 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
117 "$vdst, $addr, $data0$offset$gds"> {
118
119 let hasPostISelHook = 1;
120 let has_data1 = 0;
121}
122
123class DS_1A2D_RET<string opName,
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]124 RegisterClass rc = VGPR_32,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]125 RegisterClass src = rc>
126: DS_Pseudo<opName,
127 (outs rc:$vdst),
128 (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
129 "$vdst, $addr, $data0, $data1$offset$gds"> {
130
131 let hasPostISelHook = 1;
132}
133
Dmitry Preobrazhensky7184c442017-04-12 14:29:45 +0000[diff] [blame]134class DS_1A2D_Off8_RET<string opName,
135 RegisterClass rc = VGPR_32,
136 RegisterClass src = rc>
137: DS_Pseudo<opName,
138 (outs rc:$vdst),
139 (ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
140 "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
141
142 let has_offset = 0;
143 let AsmMatchConverter = "cvtDSOffset01";
144
145 let hasPostISelHook = 1;
146}
147
Matt Arsenaultb81495d2017-09-20 05:01:53 +0000[diff] [blame^]148class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset>
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]149: DS_Pseudo<opName,
150 (outs rc:$vdst),
Matt Arsenaultb81495d2017-09-20 05:01:53 +0000[diff] [blame^]151 !if(HasTiedOutput,
152 (ins VGPR_32:$addr, ofs:$offset, gds:$gds, rc:$vdst_in),
153 (ins VGPR_32:$addr, ofs:$offset, gds:$gds)),
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]154 "$vdst, $addr$offset$gds"> {
Matt Arsenaultb81495d2017-09-20 05:01:53 +0000[diff] [blame^]155 let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
156 let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]157 let has_data0 = 0;
158 let has_data1 = 0;
159}
160
Matt Arsenaultb81495d2017-09-20 05:01:53 +0000[diff] [blame^]161class DS_1A_RET_Tied<string opName, RegisterClass rc = VGPR_32> :
162 DS_1A_RET<opName, rc, 1>;
163
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]164class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
165: DS_Pseudo<opName,
166 (outs rc:$vdst),
167 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
168 "$vdst, $addr$offset0$offset1$gds"> {
169
170 let has_offset = 0;
171 let has_data0 = 0;
172 let has_data1 = 0;
173 let AsmMatchConverter = "cvtDSOffset01";
174}
175
176class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
177 (outs VGPR_32:$vdst),
178 (ins VGPR_32:$addr, offset:$offset),
179 "$vdst, $addr$offset gds"> {
180
181 let has_data0 = 0;
182 let has_data1 = 0;
183 let has_gds = 0;
184 let gdsValue = 1;
Artem Tamazov43b61562017-02-03 12:47:30 +0000[diff] [blame]185 let AsmMatchConverter = "cvtDSGds";
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]186}
187
188class DS_0A_RET <string opName> : DS_Pseudo<opName,
189 (outs VGPR_32:$vdst),
190 (ins offset:$offset, gds:$gds),
191 "$vdst$offset$gds"> {
192
193 let mayLoad = 1;
194 let mayStore = 1;
195
196 let has_addr = 0;
197 let has_data0 = 0;
198 let has_data1 = 0;
199}
200
201class DS_1A <string opName> : DS_Pseudo<opName,
202 (outs),
203 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
204 "$addr$offset$gds"> {
205
206 let mayLoad = 1;
207 let mayStore = 1;
208
209 let has_vdst = 0;
210 let has_data0 = 0;
211 let has_data1 = 0;
212}
213
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]214class DS_GWS <string opName, dag ins, string asmOps>
215: DS_Pseudo<opName, (outs), ins, asmOps> {
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]216
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]217 let has_vdst = 0;
218 let has_addr = 0;
219 let has_data0 = 0;
220 let has_data1 = 0;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]221
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]222 let has_gds = 0;
223 let gdsValue = 1;
224 let AsmMatchConverter = "cvtDSGds";
225}
226
227class DS_GWS_0D <string opName>
228: DS_GWS<opName,
229 (ins offset:$offset, gds:$gds), "$offset gds">;
230
231class DS_GWS_1D <string opName>
232: DS_GWS<opName,
233 (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
234
235 let has_data0 = 1;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]236}
237
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]238class DS_VOID <string opName> : DS_Pseudo<opName,
239 (outs), (ins), ""> {
240 let mayLoad = 0;
241 let mayStore = 0;
242 let hasSideEffects = 1;
243 let UseNamedOperandTable = 0;
244 let AsmMatchConverter = "";
245
246 let has_vdst = 0;
247 let has_addr = 0;
248 let has_data0 = 0;
249 let has_data1 = 0;
250 let has_offset = 0;
251 let has_offset0 = 0;
252 let has_offset1 = 0;
253 let has_gds = 0;
254}
255
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]256class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag>
257: DS_Pseudo<opName,
258 (outs VGPR_32:$vdst),
259 (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
260 "$vdst, $addr, $data0$offset",
261 [(set i32:$vdst,
262 (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
263
264 let mayLoad = 0;
265 let mayStore = 0;
266 let isConvergent = 1;
267
268 let has_data1 = 0;
269 let has_gds = 0;
270}
271
272def DS_ADD_U32 : DS_1A1D_NORET<"ds_add_u32">;
273def DS_SUB_U32 : DS_1A1D_NORET<"ds_sub_u32">;
274def DS_RSUB_U32 : DS_1A1D_NORET<"ds_rsub_u32">;
275def DS_INC_U32 : DS_1A1D_NORET<"ds_inc_u32">;
276def DS_DEC_U32 : DS_1A1D_NORET<"ds_dec_u32">;
277def DS_MIN_I32 : DS_1A1D_NORET<"ds_min_i32">;
278def DS_MAX_I32 : DS_1A1D_NORET<"ds_max_i32">;
279def DS_MIN_U32 : DS_1A1D_NORET<"ds_min_u32">;
280def DS_MAX_U32 : DS_1A1D_NORET<"ds_max_u32">;
281def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">;
282def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">;
283def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]284def DS_ADD_F32 : DS_1A1D_NORET<"ds_add_f32">;
Artem Tamazov751985a2016-10-21 14:49:22 +0000[diff] [blame]285def DS_MIN_F32 : DS_1A1D_NORET<"ds_min_f32">;
286def DS_MAX_F32 : DS_1A1D_NORET<"ds_max_f32">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]287
288let mayLoad = 0 in {
289def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">;
290def DS_WRITE_B16 : DS_1A1D_NORET<"ds_write_b16">;
291def DS_WRITE_B32 : DS_1A1D_NORET<"ds_write_b32">;
292def DS_WRITE2_B32 : DS_1A2D_Off8_NORET<"ds_write2_b32">;
293def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">;
Matt Arsenaulted6e8f02017-09-01 18:36:06 +0000[diff] [blame]294
295let SubtargetPredicate = HasD16LoadStore in {
296def DS_WRITE_B8_D16_HI : DS_1A1D_NORET<"ds_write_b8_d16_hi">;
297def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">;
298}
299
Matt Arsenaultefa1d652017-09-01 18:38:02 +0000[diff] [blame]300let SubtargetPredicate = HasDSAddTid in {
301def DS_WRITE_ADDTID_B32 : DS_1A1D_NORET<"ds_write_addtid_b32">;
302}
303
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]304}
305
306def DS_MSKOR_B32 : DS_1A2D_NORET<"ds_mskor_b32">;
307def DS_CMPST_B32 : DS_1A2D_NORET<"ds_cmpst_b32">;
308def DS_CMPST_F32 : DS_1A2D_NORET<"ds_cmpst_f32">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]309
310def DS_ADD_U64 : DS_1A1D_NORET<"ds_add_u64", VReg_64>;
311def DS_SUB_U64 : DS_1A1D_NORET<"ds_sub_u64", VReg_64>;
312def DS_RSUB_U64 : DS_1A1D_NORET<"ds_rsub_u64", VReg_64>;
313def DS_INC_U64 : DS_1A1D_NORET<"ds_inc_u64", VReg_64>;
314def DS_DEC_U64 : DS_1A1D_NORET<"ds_dec_u64", VReg_64>;
315def DS_MIN_I64 : DS_1A1D_NORET<"ds_min_i64", VReg_64>;
316def DS_MAX_I64 : DS_1A1D_NORET<"ds_max_i64", VReg_64>;
317def DS_MIN_U64 : DS_1A1D_NORET<"ds_min_u64", VReg_64>;
318def DS_MAX_U64 : DS_1A1D_NORET<"ds_max_u64", VReg_64>;
319def DS_AND_B64 : DS_1A1D_NORET<"ds_and_b64", VReg_64>;
320def DS_OR_B64 : DS_1A1D_NORET<"ds_or_b64", VReg_64>;
321def DS_XOR_B64 : DS_1A1D_NORET<"ds_xor_b64", VReg_64>;
322def DS_MSKOR_B64 : DS_1A2D_NORET<"ds_mskor_b64", VReg_64>;
323let mayLoad = 0 in {
324def DS_WRITE_B64 : DS_1A1D_NORET<"ds_write_b64", VReg_64>;
325def DS_WRITE2_B64 : DS_1A2D_Off8_NORET<"ds_write2_b64", VReg_64>;
326def DS_WRITE2ST64_B64 : DS_1A2D_Off8_NORET<"ds_write2st64_b64", VReg_64>;
327}
328def DS_CMPST_B64 : DS_1A2D_NORET<"ds_cmpst_b64", VReg_64>;
329def DS_CMPST_F64 : DS_1A2D_NORET<"ds_cmpst_f64", VReg_64>;
330def DS_MIN_F64 : DS_1A1D_NORET<"ds_min_f64", VReg_64>;
331def DS_MAX_F64 : DS_1A1D_NORET<"ds_max_f64", VReg_64>;
332
333def DS_ADD_RTN_U32 : DS_1A1D_RET<"ds_add_rtn_u32">,
334 AtomicNoRet<"ds_add_u32", 1>;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]335def DS_ADD_RTN_F32 : DS_1A1D_RET<"ds_add_rtn_f32">,
336 AtomicNoRet<"ds_add_f32", 1>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]337def DS_SUB_RTN_U32 : DS_1A1D_RET<"ds_sub_rtn_u32">,
338 AtomicNoRet<"ds_sub_u32", 1>;
339def DS_RSUB_RTN_U32 : DS_1A1D_RET<"ds_rsub_rtn_u32">,
340 AtomicNoRet<"ds_rsub_u32", 1>;
341def DS_INC_RTN_U32 : DS_1A1D_RET<"ds_inc_rtn_u32">,
342 AtomicNoRet<"ds_inc_u32", 1>;
343def DS_DEC_RTN_U32 : DS_1A1D_RET<"ds_dec_rtn_u32">,
344 AtomicNoRet<"ds_dec_u32", 1>;
345def DS_MIN_RTN_I32 : DS_1A1D_RET<"ds_min_rtn_i32">,
346 AtomicNoRet<"ds_min_i32", 1>;
347def DS_MAX_RTN_I32 : DS_1A1D_RET<"ds_max_rtn_i32">,
348 AtomicNoRet<"ds_max_i32", 1>;
349def DS_MIN_RTN_U32 : DS_1A1D_RET<"ds_min_rtn_u32">,
350 AtomicNoRet<"ds_min_u32", 1>;
351def DS_MAX_RTN_U32 : DS_1A1D_RET<"ds_max_rtn_u32">,
352 AtomicNoRet<"ds_max_u32", 1>;
353def DS_AND_RTN_B32 : DS_1A1D_RET<"ds_and_rtn_b32">,
354 AtomicNoRet<"ds_and_b32", 1>;
355def DS_OR_RTN_B32 : DS_1A1D_RET<"ds_or_rtn_b32">,
356 AtomicNoRet<"ds_or_b32", 1>;
357def DS_XOR_RTN_B32 : DS_1A1D_RET<"ds_xor_rtn_b32">,
358 AtomicNoRet<"ds_xor_b32", 1>;
359def DS_MSKOR_RTN_B32 : DS_1A2D_RET<"ds_mskor_rtn_b32">,
360 AtomicNoRet<"ds_mskor_b32", 1>;
361def DS_CMPST_RTN_B32 : DS_1A2D_RET <"ds_cmpst_rtn_b32">,
362 AtomicNoRet<"ds_cmpst_b32", 1>;
363def DS_CMPST_RTN_F32 : DS_1A2D_RET <"ds_cmpst_rtn_f32">,
364 AtomicNoRet<"ds_cmpst_f32", 1>;
Artem Tamazov751985a2016-10-21 14:49:22 +0000[diff] [blame]365def DS_MIN_RTN_F32 : DS_1A1D_RET <"ds_min_rtn_f32">,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]366 AtomicNoRet<"ds_min_f32", 1>;
Artem Tamazov751985a2016-10-21 14:49:22 +0000[diff] [blame]367def DS_MAX_RTN_F32 : DS_1A1D_RET <"ds_max_rtn_f32">,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]368 AtomicNoRet<"ds_max_f32", 1>;
369
370def DS_WRXCHG_RTN_B32 : DS_1A1D_RET<"ds_wrxchg_rtn_b32">,
371 AtomicNoRet<"", 1>;
Dmitry Preobrazhensky7184c442017-04-12 14:29:45 +0000[diff] [blame]372def DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]373 AtomicNoRet<"", 1>;
Dmitry Preobrazhensky7184c442017-04-12 14:29:45 +0000[diff] [blame]374def DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]375 AtomicNoRet<"", 1>;
376
377def DS_ADD_RTN_U64 : DS_1A1D_RET<"ds_add_rtn_u64", VReg_64>,
378 AtomicNoRet<"ds_add_u64", 1>;
379def DS_SUB_RTN_U64 : DS_1A1D_RET<"ds_sub_rtn_u64", VReg_64>,
380 AtomicNoRet<"ds_sub_u64", 1>;
381def DS_RSUB_RTN_U64 : DS_1A1D_RET<"ds_rsub_rtn_u64", VReg_64>,
382 AtomicNoRet<"ds_rsub_u64", 1>;
383def DS_INC_RTN_U64 : DS_1A1D_RET<"ds_inc_rtn_u64", VReg_64>,
384 AtomicNoRet<"ds_inc_u64", 1>;
385def DS_DEC_RTN_U64 : DS_1A1D_RET<"ds_dec_rtn_u64", VReg_64>,
386 AtomicNoRet<"ds_dec_u64", 1>;
387def DS_MIN_RTN_I64 : DS_1A1D_RET<"ds_min_rtn_i64", VReg_64>,
388 AtomicNoRet<"ds_min_i64", 1>;
389def DS_MAX_RTN_I64 : DS_1A1D_RET<"ds_max_rtn_i64", VReg_64>,
390 AtomicNoRet<"ds_max_i64", 1>;
391def DS_MIN_RTN_U64 : DS_1A1D_RET<"ds_min_rtn_u64", VReg_64>,
392 AtomicNoRet<"ds_min_u64", 1>;
393def DS_MAX_RTN_U64 : DS_1A1D_RET<"ds_max_rtn_u64", VReg_64>,
394 AtomicNoRet<"ds_max_u64", 1>;
395def DS_AND_RTN_B64 : DS_1A1D_RET<"ds_and_rtn_b64", VReg_64>,
396 AtomicNoRet<"ds_and_b64", 1>;
397def DS_OR_RTN_B64 : DS_1A1D_RET<"ds_or_rtn_b64", VReg_64>,
398 AtomicNoRet<"ds_or_b64", 1>;
399def DS_XOR_RTN_B64 : DS_1A1D_RET<"ds_xor_rtn_b64", VReg_64>,
400 AtomicNoRet<"ds_xor_b64", 1>;
401def DS_MSKOR_RTN_B64 : DS_1A2D_RET<"ds_mskor_rtn_b64", VReg_64>,
402 AtomicNoRet<"ds_mskor_b64", 1>;
403def DS_CMPST_RTN_B64 : DS_1A2D_RET<"ds_cmpst_rtn_b64", VReg_64>,
404 AtomicNoRet<"ds_cmpst_b64", 1>;
405def DS_CMPST_RTN_F64 : DS_1A2D_RET<"ds_cmpst_rtn_f64", VReg_64>,
406 AtomicNoRet<"ds_cmpst_f64", 1>;
407def DS_MIN_RTN_F64 : DS_1A1D_RET<"ds_min_rtn_f64", VReg_64>,
408 AtomicNoRet<"ds_min_f64", 1>;
409def DS_MAX_RTN_F64 : DS_1A1D_RET<"ds_max_rtn_f64", VReg_64>,
410 AtomicNoRet<"ds_max_f64", 1>;
411
412def DS_WRXCHG_RTN_B64 : DS_1A1D_RET<"ds_wrxchg_rtn_b64", VReg_64>,
Dmitry Preobrazhensky7184c442017-04-12 14:29:45 +0000[diff] [blame]413 AtomicNoRet<"", 1>;
414def DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>,
415 AtomicNoRet<"", 1>;
416def DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>,
417 AtomicNoRet<"", 1>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]418
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]419def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init">;
420def DS_GWS_SEMA_V : DS_GWS_0D<"ds_gws_sema_v">;
421def DS_GWS_SEMA_BR : DS_GWS_1D<"ds_gws_sema_br">;
422def DS_GWS_SEMA_P : DS_GWS_0D<"ds_gws_sema_p">;
423def DS_GWS_BARRIER : DS_GWS_1D<"ds_gws_barrier">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]424
425def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">;
426def DS_SUB_SRC2_U32 : DS_1A<"ds_sub_src2_u32">;
427def DS_RSUB_SRC2_U32 : DS_1A<"ds_rsub_src2_u32">;
428def DS_INC_SRC2_U32 : DS_1A<"ds_inc_src2_u32">;
429def DS_DEC_SRC2_U32 : DS_1A<"ds_dec_src2_u32">;
430def DS_MIN_SRC2_I32 : DS_1A<"ds_min_src2_i32">;
431def DS_MAX_SRC2_I32 : DS_1A<"ds_max_src2_i32">;
432def DS_MIN_SRC2_U32 : DS_1A<"ds_min_src2_u32">;
433def DS_MAX_SRC2_U32 : DS_1A<"ds_max_src2_u32">;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]434def DS_AND_SRC2_B32 : DS_1A<"ds_and_src2_b32">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]435def DS_OR_SRC2_B32 : DS_1A<"ds_or_src2_b32">;
436def DS_XOR_SRC2_B32 : DS_1A<"ds_xor_src2_b32">;
437def DS_MIN_SRC2_F32 : DS_1A<"ds_min_src2_f32">;
438def DS_MAX_SRC2_F32 : DS_1A<"ds_max_src2_f32">;
439
440def DS_ADD_SRC2_U64 : DS_1A<"ds_add_src2_u64">;
441def DS_SUB_SRC2_U64 : DS_1A<"ds_sub_src2_u64">;
442def DS_RSUB_SRC2_U64 : DS_1A<"ds_rsub_src2_u64">;
443def DS_INC_SRC2_U64 : DS_1A<"ds_inc_src2_u64">;
444def DS_DEC_SRC2_U64 : DS_1A<"ds_dec_src2_u64">;
445def DS_MIN_SRC2_I64 : DS_1A<"ds_min_src2_i64">;
446def DS_MAX_SRC2_I64 : DS_1A<"ds_max_src2_i64">;
447def DS_MIN_SRC2_U64 : DS_1A<"ds_min_src2_u64">;
448def DS_MAX_SRC2_U64 : DS_1A<"ds_max_src2_u64">;
449def DS_AND_SRC2_B64 : DS_1A<"ds_and_src2_b64">;
450def DS_OR_SRC2_B64 : DS_1A<"ds_or_src2_b64">;
451def DS_XOR_SRC2_B64 : DS_1A<"ds_xor_src2_b64">;
452def DS_MIN_SRC2_F64 : DS_1A<"ds_min_src2_f64">;
453def DS_MAX_SRC2_F64 : DS_1A<"ds_max_src2_f64">;
454
Dmitry Preobrazhenskye6ef0992017-04-14 12:28:07 +0000[diff] [blame]455def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">;
456def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]457
458let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
Matt Arsenaultb81495d2017-09-20 05:01:53 +0000[diff] [blame^]459def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, SwizzleImm>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]460}
461
462let mayStore = 0 in {
463def DS_READ_I8 : DS_1A_RET<"ds_read_i8">;
464def DS_READ_U8 : DS_1A_RET<"ds_read_u8">;
465def DS_READ_I16 : DS_1A_RET<"ds_read_i16">;
466def DS_READ_U16 : DS_1A_RET<"ds_read_u16">;
467def DS_READ_B32 : DS_1A_RET<"ds_read_b32">;
468def DS_READ_B64 : DS_1A_RET<"ds_read_b64", VReg_64>;
469
470def DS_READ2_B32 : DS_1A_Off8_RET<"ds_read2_b32", VReg_64>;
471def DS_READ2ST64_B32 : DS_1A_Off8_RET<"ds_read2st64_b32", VReg_64>;
472
473def DS_READ2_B64 : DS_1A_Off8_RET<"ds_read2_b64", VReg_128>;
474def DS_READ2ST64_B64 : DS_1A_Off8_RET<"ds_read2st64_b64", VReg_128>;
Matt Arsenaulted6e8f02017-09-01 18:36:06 +0000[diff] [blame]475
476let SubtargetPredicate = HasD16LoadStore in {
Matt Arsenaultb81495d2017-09-20 05:01:53 +0000[diff] [blame^]477def DS_READ_U8_D16 : DS_1A_RET_Tied<"ds_read_u8_d16">;
478def DS_READ_U8_D16_HI : DS_1A_RET_Tied<"ds_read_u8_d16_hi">;
479def DS_READ_I8_D16 : DS_1A_RET_Tied<"ds_read_i8_d16">;
480def DS_READ_I8_D16_HI : DS_1A_RET_Tied<"ds_read_i8_d16_hi">;
481def DS_READ_U16_D16 : DS_1A_RET_Tied<"ds_read_u16_d16">;
482def DS_READ_U16_D16_HI : DS_1A_RET_Tied<"ds_read_u16_d16_hi">;
Matt Arsenaulted6e8f02017-09-01 18:36:06 +0000[diff] [blame]483}
Matt Arsenaultefa1d652017-09-01 18:38:02 +0000[diff] [blame]484
485let SubtargetPredicate = HasDSAddTid in {
486def DS_READ_ADDTID_B32 : DS_1A_RET<"ds_read_addtid_b32">;
487}
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]488}
489
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]490def DS_CONSUME : DS_0A_RET<"ds_consume">;
491def DS_APPEND : DS_0A_RET<"ds_append">;
492def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]493
494//===----------------------------------------------------------------------===//
495// Instruction definitions for CI and newer.
496//===----------------------------------------------------------------------===//
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]497
498let SubtargetPredicate = isCIVI in {
499
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]500def DS_WRAP_RTN_B32 : DS_1A2D_RET<"ds_wrap_rtn_b32">, AtomicNoRet<"", 1>;
501
502def DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET<"ds_condxchg32_rtn_b64", VReg_64>,
503 AtomicNoRet<"", 1>;
504
505def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]506
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]507let mayStore = 0 in {
508def DS_READ_B96 : DS_1A_RET<"ds_read_b96", VReg_96>;
509def DS_READ_B128: DS_1A_RET<"ds_read_b128", VReg_128>;
510} // End mayStore = 0
511
512let mayLoad = 0 in {
513def DS_WRITE_B96 : DS_1A1D_NORET<"ds_write_b96", VReg_96>;
514def DS_WRITE_B128 : DS_1A1D_NORET<"ds_write_b128", VReg_128>;
515} // End mayLoad = 0
516
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]517def DS_NOP : DS_VOID<"ds_nop">;
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]518
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]519} // let SubtargetPredicate = isCIVI
520
521//===----------------------------------------------------------------------===//
522// Instruction definitions for VI and newer.
523//===----------------------------------------------------------------------===//
524
525let SubtargetPredicate = isVI in {
526
527let Uses = [EXEC] in {
528def DS_PERMUTE_B32 : DS_1A1D_PERMUTE <"ds_permute_b32",
529 int_amdgcn_ds_permute>;
530def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
531 int_amdgcn_ds_bpermute>;
532}
533
534} // let SubtargetPredicate = isVI
535
536//===----------------------------------------------------------------------===//
537// DS Patterns
538//===----------------------------------------------------------------------===//
539
540let Predicates = [isGCN] in {
541
542def : Pat <
543 (int_amdgcn_ds_swizzle i32:$src, imm:$offset16),
544 (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0))
545>;
546
547class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
548 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
549 (inst $ptr, (as_i16imm $offset), (i1 0))
550>;
551
Matt Arsenaultb81495d2017-09-20 05:01:53 +0000[diff] [blame^]552multiclass DSReadPat_Hi16 <DS_Pseudo inst, PatFrag frag, ValueType vt = i16> {
553 def : Pat <
554 (build_vector vt:$lo, (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset)))),
555 (v2i16 (inst $ptr, (as_i16imm $offset), (i1 0), $lo))
556 >;
557
558 def : Pat <
559 (build_vector f16:$lo, (f16 (bitconvert (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset)))))),
560 (v2f16 (inst $ptr, (as_i16imm $offset), (i1 0), $lo))
561 >;
562}
563
Matt Arsenaultbc683832017-09-20 03:43:35 +0000[diff] [blame]564def : DSReadPat <DS_READ_I8, i32, sextloadi8_local_m0>;
565def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local_m0>;
566def : DSReadPat <DS_READ_I8, i16, sextloadi8_local_m0>;
567def : DSReadPat <DS_READ_U8, i16, az_extloadi8_local_m0>;
568def : DSReadPat <DS_READ_I16, i32, sextloadi16_local_m0>;
569def : DSReadPat <DS_READ_I16, i32, sextloadi16_local_m0>;
570def : DSReadPat <DS_READ_U16, i32, az_extloadi16_local_m0>;
571def : DSReadPat <DS_READ_U16, i16, load_local_m0>;
572def : DSReadPat <DS_READ_B32, i32, load_local_m0>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]573
574let AddedComplexity = 100 in {
575
Matt Arsenaultbc683832017-09-20 03:43:35 +0000[diff] [blame]576def : DSReadPat <DS_READ_B64, v2i32, load_align8_local_m0>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]577
578} // End AddedComplexity = 100
579
580def : Pat <
Matt Arsenaultbc683832017-09-20 03:43:35 +0000[diff] [blame]581 (v2i32 (load_local_m0 (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
582 i8:$offset1))),
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]583 (DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0))
584>;
585
Matt Arsenaultb81495d2017-09-20 05:01:53 +0000[diff] [blame^]586
587let Predicates = [HasD16LoadStore] in {
588let AddedComplexity = 100 in {
589defm : DSReadPat_Hi16<DS_READ_U16_D16_HI, load_local>;
590defm : DSReadPat_Hi16<DS_READ_U8_D16_HI, az_extloadi8_local>;
591defm : DSReadPat_Hi16<DS_READ_I8_D16_HI, sextloadi8_local>;
592}
593}
594
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]595class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
596 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
597 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
598>;
599
Matt Arsenaultbc683832017-09-20 03:43:35 +0000[diff] [blame]600def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local_m0>;
601def : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local_m0>;
602def : DSWritePat <DS_WRITE_B8, i16, truncstorei8_local_m0>;
603def : DSWritePat <DS_WRITE_B16, i16, store_local_m0>;
604def : DSWritePat <DS_WRITE_B32, i32, store_local_m0>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]605
Matt Arsenaultfcc213f2017-09-20 03:20:09 +0000[diff] [blame]606let Predicates = [HasD16LoadStore] in {
607def : DSWritePat <DS_WRITE_B16_D16_HI, i32, store_local_hi16>;
608def : DSWritePat <DS_WRITE_B8_D16_HI, i32, truncstorei8_local_hi16>;
609}
610
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]611let AddedComplexity = 100 in {
612
Matt Arsenaultbc683832017-09-20 03:43:35 +0000[diff] [blame]613def : DSWritePat <DS_WRITE_B64, v2i32, store_align8_local_m0>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]614} // End AddedComplexity = 100
615
616def : Pat <
Matt Arsenaultbc683832017-09-20 03:43:35 +0000[diff] [blame]617 (store_local_m0 v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]618 i8:$offset1)),
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]619 (DS_WRITE2_B32 $ptr, (i32 (EXTRACT_SUBREG $value, sub0)),
620 (i32 (EXTRACT_SUBREG $value, sub1)), $offset0, $offset1,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]621 (i1 0))
622>;
623
624class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
625 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
626 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
627>;
628
629class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
630 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
631 (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0))
632>;
633
634
635// 32-bit atomics.
636def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, si_atomic_swap_local>;
637def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, si_atomic_load_add_local>;
638def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, si_atomic_load_sub_local>;
639def : DSAtomicRetPat<DS_INC_RTN_U32, i32, si_atomic_inc_local>;
640def : DSAtomicRetPat<DS_DEC_RTN_U32, i32, si_atomic_dec_local>;
641def : DSAtomicRetPat<DS_AND_RTN_B32, i32, si_atomic_load_and_local>;
642def : DSAtomicRetPat<DS_OR_RTN_B32, i32, si_atomic_load_or_local>;
643def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, si_atomic_load_xor_local>;
644def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, si_atomic_load_min_local>;
645def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, si_atomic_load_max_local>;
646def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, si_atomic_load_umin_local>;
647def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, si_atomic_load_umax_local>;
648def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, si_atomic_cmp_swap_32_local>;
649
650// 64-bit atomics.
651def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, si_atomic_swap_local>;
652def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, si_atomic_load_add_local>;
653def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, si_atomic_load_sub_local>;
654def : DSAtomicRetPat<DS_INC_RTN_U64, i64, si_atomic_inc_local>;
655def : DSAtomicRetPat<DS_DEC_RTN_U64, i64, si_atomic_dec_local>;
656def : DSAtomicRetPat<DS_AND_RTN_B64, i64, si_atomic_load_and_local>;
657def : DSAtomicRetPat<DS_OR_RTN_B64, i64, si_atomic_load_or_local>;
658def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, si_atomic_load_xor_local>;
659def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, si_atomic_load_min_local>;
660def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, si_atomic_load_max_local>;
661def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, si_atomic_load_umin_local>;
662def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, si_atomic_load_umax_local>;
663
664def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, si_atomic_cmp_swap_64_local>;
665
666} // let Predicates = [isGCN]
667
668//===----------------------------------------------------------------------===//
669// Real instructions
670//===----------------------------------------------------------------------===//
671
672//===----------------------------------------------------------------------===//
673// SIInstructions.td
674//===----------------------------------------------------------------------===//
675
676class DS_Real_si <bits<8> op, DS_Pseudo ds> :
677 DS_Real <ds>,
678 SIMCInstr <ds.Mnemonic, SIEncodingFamily.SI> {
679 let AssemblerPredicates=[isSICI];
680 let DecoderNamespace="SICI";
681
682 // encoding
683 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
684 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
685 let Inst{17} = !if(ds.has_gds, gds, ds.gdsValue);
686 let Inst{25-18} = op;
687 let Inst{31-26} = 0x36; // ds prefix
688 let Inst{39-32} = !if(ds.has_addr, addr, 0);
689 let Inst{47-40} = !if(ds.has_data0, data0, 0);
690 let Inst{55-48} = !if(ds.has_data1, data1, 0);
691 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
692}
693
694def DS_ADD_U32_si : DS_Real_si<0x0, DS_ADD_U32>;
695def DS_SUB_U32_si : DS_Real_si<0x1, DS_SUB_U32>;
696def DS_RSUB_U32_si : DS_Real_si<0x2, DS_RSUB_U32>;
697def DS_INC_U32_si : DS_Real_si<0x3, DS_INC_U32>;
698def DS_DEC_U32_si : DS_Real_si<0x4, DS_DEC_U32>;
699def DS_MIN_I32_si : DS_Real_si<0x5, DS_MIN_I32>;
700def DS_MAX_I32_si : DS_Real_si<0x6, DS_MAX_I32>;
701def DS_MIN_U32_si : DS_Real_si<0x7, DS_MIN_U32>;
702def DS_MAX_U32_si : DS_Real_si<0x8, DS_MAX_U32>;
703def DS_AND_B32_si : DS_Real_si<0x9, DS_AND_B32>;
704def DS_OR_B32_si : DS_Real_si<0xa, DS_OR_B32>;
705def DS_XOR_B32_si : DS_Real_si<0xb, DS_XOR_B32>;
706def DS_MSKOR_B32_si : DS_Real_si<0xc, DS_MSKOR_B32>;
707def DS_WRITE_B32_si : DS_Real_si<0xd, DS_WRITE_B32>;
708def DS_WRITE2_B32_si : DS_Real_si<0xe, DS_WRITE2_B32>;
709def DS_WRITE2ST64_B32_si : DS_Real_si<0xf, DS_WRITE2ST64_B32>;
710def DS_CMPST_B32_si : DS_Real_si<0x10, DS_CMPST_B32>;
711def DS_CMPST_F32_si : DS_Real_si<0x11, DS_CMPST_F32>;
712def DS_MIN_F32_si : DS_Real_si<0x12, DS_MIN_F32>;
713def DS_MAX_F32_si : DS_Real_si<0x13, DS_MAX_F32>;
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]714def DS_NOP_si : DS_Real_si<0x14, DS_NOP>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]715def DS_GWS_INIT_si : DS_Real_si<0x19, DS_GWS_INIT>;
716def DS_GWS_SEMA_V_si : DS_Real_si<0x1a, DS_GWS_SEMA_V>;
717def DS_GWS_SEMA_BR_si : DS_Real_si<0x1b, DS_GWS_SEMA_BR>;
718def DS_GWS_SEMA_P_si : DS_Real_si<0x1c, DS_GWS_SEMA_P>;
719def DS_GWS_BARRIER_si : DS_Real_si<0x1d, DS_GWS_BARRIER>;
720def DS_WRITE_B8_si : DS_Real_si<0x1e, DS_WRITE_B8>;
721def DS_WRITE_B16_si : DS_Real_si<0x1f, DS_WRITE_B16>;
722def DS_ADD_RTN_U32_si : DS_Real_si<0x20, DS_ADD_RTN_U32>;
723def DS_SUB_RTN_U32_si : DS_Real_si<0x21, DS_SUB_RTN_U32>;
724def DS_RSUB_RTN_U32_si : DS_Real_si<0x22, DS_RSUB_RTN_U32>;
725def DS_INC_RTN_U32_si : DS_Real_si<0x23, DS_INC_RTN_U32>;
726def DS_DEC_RTN_U32_si : DS_Real_si<0x24, DS_DEC_RTN_U32>;
727def DS_MIN_RTN_I32_si : DS_Real_si<0x25, DS_MIN_RTN_I32>;
728def DS_MAX_RTN_I32_si : DS_Real_si<0x26, DS_MAX_RTN_I32>;
729def DS_MIN_RTN_U32_si : DS_Real_si<0x27, DS_MIN_RTN_U32>;
730def DS_MAX_RTN_U32_si : DS_Real_si<0x28, DS_MAX_RTN_U32>;
731def DS_AND_RTN_B32_si : DS_Real_si<0x29, DS_AND_RTN_B32>;
732def DS_OR_RTN_B32_si : DS_Real_si<0x2a, DS_OR_RTN_B32>;
733def DS_XOR_RTN_B32_si : DS_Real_si<0x2b, DS_XOR_RTN_B32>;
734def DS_MSKOR_RTN_B32_si : DS_Real_si<0x2c, DS_MSKOR_RTN_B32>;
735def DS_WRXCHG_RTN_B32_si : DS_Real_si<0x2d, DS_WRXCHG_RTN_B32>;
736def DS_WRXCHG2_RTN_B32_si : DS_Real_si<0x2e, DS_WRXCHG2_RTN_B32>;
737def DS_WRXCHG2ST64_RTN_B32_si : DS_Real_si<0x2f, DS_WRXCHG2ST64_RTN_B32>;
738def DS_CMPST_RTN_B32_si : DS_Real_si<0x30, DS_CMPST_RTN_B32>;
739def DS_CMPST_RTN_F32_si : DS_Real_si<0x31, DS_CMPST_RTN_F32>;
740def DS_MIN_RTN_F32_si : DS_Real_si<0x32, DS_MIN_RTN_F32>;
741def DS_MAX_RTN_F32_si : DS_Real_si<0x33, DS_MAX_RTN_F32>;
742
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]743// These instruction are CI/VI only
744def DS_WRAP_RTN_B32_si : DS_Real_si<0x34, DS_WRAP_RTN_B32>;
745def DS_CONDXCHG32_RTN_B64_si : DS_Real_si<0x7e, DS_CONDXCHG32_RTN_B64>;
746def DS_GWS_SEMA_RELEASE_ALL_si : DS_Real_si<0x18, DS_GWS_SEMA_RELEASE_ALL>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]747
748def DS_SWIZZLE_B32_si : DS_Real_si<0x35, DS_SWIZZLE_B32>;
749def DS_READ_B32_si : DS_Real_si<0x36, DS_READ_B32>;
750def DS_READ2_B32_si : DS_Real_si<0x37, DS_READ2_B32>;
751def DS_READ2ST64_B32_si : DS_Real_si<0x38, DS_READ2ST64_B32>;
752def DS_READ_I8_si : DS_Real_si<0x39, DS_READ_I8>;
753def DS_READ_U8_si : DS_Real_si<0x3a, DS_READ_U8>;
754def DS_READ_I16_si : DS_Real_si<0x3b, DS_READ_I16>;
755def DS_READ_U16_si : DS_Real_si<0x3c, DS_READ_U16>;
756def DS_CONSUME_si : DS_Real_si<0x3d, DS_CONSUME>;
757def DS_APPEND_si : DS_Real_si<0x3e, DS_APPEND>;
758def DS_ORDERED_COUNT_si : DS_Real_si<0x3f, DS_ORDERED_COUNT>;
759def DS_ADD_U64_si : DS_Real_si<0x40, DS_ADD_U64>;
760def DS_SUB_U64_si : DS_Real_si<0x41, DS_SUB_U64>;
761def DS_RSUB_U64_si : DS_Real_si<0x42, DS_RSUB_U64>;
762def DS_INC_U64_si : DS_Real_si<0x43, DS_INC_U64>;
763def DS_DEC_U64_si : DS_Real_si<0x44, DS_DEC_U64>;
764def DS_MIN_I64_si : DS_Real_si<0x45, DS_MIN_I64>;
765def DS_MAX_I64_si : DS_Real_si<0x46, DS_MAX_I64>;
766def DS_MIN_U64_si : DS_Real_si<0x47, DS_MIN_U64>;
767def DS_MAX_U64_si : DS_Real_si<0x48, DS_MAX_U64>;
768def DS_AND_B64_si : DS_Real_si<0x49, DS_AND_B64>;
769def DS_OR_B64_si : DS_Real_si<0x4a, DS_OR_B64>;
770def DS_XOR_B64_si : DS_Real_si<0x4b, DS_XOR_B64>;
771def DS_MSKOR_B64_si : DS_Real_si<0x4c, DS_MSKOR_B64>;
772def DS_WRITE_B64_si : DS_Real_si<0x4d, DS_WRITE_B64>;
773def DS_WRITE2_B64_si : DS_Real_si<0x4E, DS_WRITE2_B64>;
774def DS_WRITE2ST64_B64_si : DS_Real_si<0x4f, DS_WRITE2ST64_B64>;
775def DS_CMPST_B64_si : DS_Real_si<0x50, DS_CMPST_B64>;
776def DS_CMPST_F64_si : DS_Real_si<0x51, DS_CMPST_F64>;
777def DS_MIN_F64_si : DS_Real_si<0x52, DS_MIN_F64>;
778def DS_MAX_F64_si : DS_Real_si<0x53, DS_MAX_F64>;
779
780def DS_ADD_RTN_U64_si : DS_Real_si<0x60, DS_ADD_RTN_U64>;
781def DS_SUB_RTN_U64_si : DS_Real_si<0x61, DS_SUB_RTN_U64>;
782def DS_RSUB_RTN_U64_si : DS_Real_si<0x62, DS_RSUB_RTN_U64>;
783def DS_INC_RTN_U64_si : DS_Real_si<0x63, DS_INC_RTN_U64>;
784def DS_DEC_RTN_U64_si : DS_Real_si<0x64, DS_DEC_RTN_U64>;
785def DS_MIN_RTN_I64_si : DS_Real_si<0x65, DS_MIN_RTN_I64>;
786def DS_MAX_RTN_I64_si : DS_Real_si<0x66, DS_MAX_RTN_I64>;
787def DS_MIN_RTN_U64_si : DS_Real_si<0x67, DS_MIN_RTN_U64>;
788def DS_MAX_RTN_U64_si : DS_Real_si<0x68, DS_MAX_RTN_U64>;
789def DS_AND_RTN_B64_si : DS_Real_si<0x69, DS_AND_RTN_B64>;
790def DS_OR_RTN_B64_si : DS_Real_si<0x6a, DS_OR_RTN_B64>;
791def DS_XOR_RTN_B64_si : DS_Real_si<0x6b, DS_XOR_RTN_B64>;
792def DS_MSKOR_RTN_B64_si : DS_Real_si<0x6c, DS_MSKOR_RTN_B64>;
793def DS_WRXCHG_RTN_B64_si : DS_Real_si<0x6d, DS_WRXCHG_RTN_B64>;
794def DS_WRXCHG2_RTN_B64_si : DS_Real_si<0x6e, DS_WRXCHG2_RTN_B64>;
795def DS_WRXCHG2ST64_RTN_B64_si : DS_Real_si<0x6f, DS_WRXCHG2ST64_RTN_B64>;
796def DS_CMPST_RTN_B64_si : DS_Real_si<0x70, DS_CMPST_RTN_B64>;
797def DS_CMPST_RTN_F64_si : DS_Real_si<0x71, DS_CMPST_RTN_F64>;
798def DS_MIN_RTN_F64_si : DS_Real_si<0x72, DS_MIN_RTN_F64>;
799def DS_MAX_RTN_F64_si : DS_Real_si<0x73, DS_MAX_RTN_F64>;
800
801def DS_READ_B64_si : DS_Real_si<0x76, DS_READ_B64>;
802def DS_READ2_B64_si : DS_Real_si<0x77, DS_READ2_B64>;
803def DS_READ2ST64_B64_si : DS_Real_si<0x78, DS_READ2ST64_B64>;
804
805def DS_ADD_SRC2_U32_si : DS_Real_si<0x80, DS_ADD_SRC2_U32>;
806def DS_SUB_SRC2_U32_si : DS_Real_si<0x81, DS_SUB_SRC2_U32>;
807def DS_RSUB_SRC2_U32_si : DS_Real_si<0x82, DS_RSUB_SRC2_U32>;
808def DS_INC_SRC2_U32_si : DS_Real_si<0x83, DS_INC_SRC2_U32>;
809def DS_DEC_SRC2_U32_si : DS_Real_si<0x84, DS_DEC_SRC2_U32>;
810def DS_MIN_SRC2_I32_si : DS_Real_si<0x85, DS_MIN_SRC2_I32>;
811def DS_MAX_SRC2_I32_si : DS_Real_si<0x86, DS_MAX_SRC2_I32>;
812def DS_MIN_SRC2_U32_si : DS_Real_si<0x87, DS_MIN_SRC2_U32>;
813def DS_MAX_SRC2_U32_si : DS_Real_si<0x88, DS_MAX_SRC2_U32>;
814def DS_AND_SRC2_B32_si : DS_Real_si<0x89, DS_AND_SRC2_B32>;
815def DS_OR_SRC2_B32_si : DS_Real_si<0x8a, DS_OR_SRC2_B32>;
816def DS_XOR_SRC2_B32_si : DS_Real_si<0x8b, DS_XOR_SRC2_B32>;
817def DS_WRITE_SRC2_B32_si : DS_Real_si<0x8d, DS_WRITE_SRC2_B32>;
818
819def DS_MIN_SRC2_F32_si : DS_Real_si<0x92, DS_MIN_SRC2_F32>;
820def DS_MAX_SRC2_F32_si : DS_Real_si<0x93, DS_MAX_SRC2_F32>;
821
822def DS_ADD_SRC2_U64_si : DS_Real_si<0xc0, DS_ADD_SRC2_U64>;
823def DS_SUB_SRC2_U64_si : DS_Real_si<0xc1, DS_SUB_SRC2_U64>;
824def DS_RSUB_SRC2_U64_si : DS_Real_si<0xc2, DS_RSUB_SRC2_U64>;
825def DS_INC_SRC2_U64_si : DS_Real_si<0xc3, DS_INC_SRC2_U64>;
826def DS_DEC_SRC2_U64_si : DS_Real_si<0xc4, DS_DEC_SRC2_U64>;
827def DS_MIN_SRC2_I64_si : DS_Real_si<0xc5, DS_MIN_SRC2_I64>;
828def DS_MAX_SRC2_I64_si : DS_Real_si<0xc6, DS_MAX_SRC2_I64>;
829def DS_MIN_SRC2_U64_si : DS_Real_si<0xc7, DS_MIN_SRC2_U64>;
830def DS_MAX_SRC2_U64_si : DS_Real_si<0xc8, DS_MAX_SRC2_U64>;
831def DS_AND_SRC2_B64_si : DS_Real_si<0xc9, DS_AND_SRC2_B64>;
832def DS_OR_SRC2_B64_si : DS_Real_si<0xca, DS_OR_SRC2_B64>;
833def DS_XOR_SRC2_B64_si : DS_Real_si<0xcb, DS_XOR_SRC2_B64>;
834def DS_WRITE_SRC2_B64_si : DS_Real_si<0xcd, DS_WRITE_SRC2_B64>;
835
836def DS_MIN_SRC2_F64_si : DS_Real_si<0xd2, DS_MIN_SRC2_F64>;
837def DS_MAX_SRC2_F64_si : DS_Real_si<0xd3, DS_MAX_SRC2_F64>;
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]838def DS_WRITE_B96_si : DS_Real_si<0xde, DS_WRITE_B96>;
839def DS_WRITE_B128_si : DS_Real_si<0xdf, DS_WRITE_B128>;
840def DS_READ_B96_si : DS_Real_si<0xfe, DS_READ_B96>;
841def DS_READ_B128_si : DS_Real_si<0xff, DS_READ_B128>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]842
843//===----------------------------------------------------------------------===//
844// VIInstructions.td
845//===----------------------------------------------------------------------===//
846
847class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
848 DS_Real <ds>,
849 SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
850 let AssemblerPredicates = [isVI];
851 let DecoderNamespace="VI";
852
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]853 // encoding
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]854 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
855 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
856 let Inst{16} = !if(ds.has_gds, gds, ds.gdsValue);
857 let Inst{24-17} = op;
858 let Inst{31-26} = 0x36; // ds prefix
859 let Inst{39-32} = !if(ds.has_addr, addr, 0);
860 let Inst{47-40} = !if(ds.has_data0, data0, 0);
861 let Inst{55-48} = !if(ds.has_data1, data1, 0);
862 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
863}
864
865def DS_ADD_U32_vi : DS_Real_vi<0x0, DS_ADD_U32>;
866def DS_SUB_U32_vi : DS_Real_vi<0x1, DS_SUB_U32>;
867def DS_RSUB_U32_vi : DS_Real_vi<0x2, DS_RSUB_U32>;
868def DS_INC_U32_vi : DS_Real_vi<0x3, DS_INC_U32>;
869def DS_DEC_U32_vi : DS_Real_vi<0x4, DS_DEC_U32>;
870def DS_MIN_I32_vi : DS_Real_vi<0x5, DS_MIN_I32>;
871def DS_MAX_I32_vi : DS_Real_vi<0x6, DS_MAX_I32>;
872def DS_MIN_U32_vi : DS_Real_vi<0x7, DS_MIN_U32>;
873def DS_MAX_U32_vi : DS_Real_vi<0x8, DS_MAX_U32>;
874def DS_AND_B32_vi : DS_Real_vi<0x9, DS_AND_B32>;
875def DS_OR_B32_vi : DS_Real_vi<0xa, DS_OR_B32>;
876def DS_XOR_B32_vi : DS_Real_vi<0xb, DS_XOR_B32>;
877def DS_MSKOR_B32_vi : DS_Real_vi<0xc, DS_MSKOR_B32>;
878def DS_WRITE_B32_vi : DS_Real_vi<0xd, DS_WRITE_B32>;
879def DS_WRITE2_B32_vi : DS_Real_vi<0xe, DS_WRITE2_B32>;
880def DS_WRITE2ST64_B32_vi : DS_Real_vi<0xf, DS_WRITE2ST64_B32>;
881def DS_CMPST_B32_vi : DS_Real_vi<0x10, DS_CMPST_B32>;
882def DS_CMPST_F32_vi : DS_Real_vi<0x11, DS_CMPST_F32>;
883def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>;
884def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>;
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]885def DS_NOP_vi : DS_Real_vi<0x14, DS_NOP>;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]886def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]887def DS_GWS_INIT_vi : DS_Real_vi<0x99, DS_GWS_INIT>;
888def DS_GWS_SEMA_V_vi : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
889def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
890def DS_GWS_SEMA_P_vi : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
891def DS_GWS_BARRIER_vi : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
Matt Arsenaultefa1d652017-09-01 18:38:02 +0000[diff] [blame]892def DS_WRITE_ADDTID_B32_vi : DS_Real_vi<0x1d, DS_WRITE_ADDTID_B32>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]893def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>;
894def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>;
895def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
896def DS_SUB_RTN_U32_vi : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
897def DS_RSUB_RTN_U32_vi : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
898def DS_INC_RTN_U32_vi : DS_Real_vi<0x23, DS_INC_RTN_U32>;
899def DS_DEC_RTN_U32_vi : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
900def DS_MIN_RTN_I32_vi : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
901def DS_MAX_RTN_I32_vi : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
902def DS_MIN_RTN_U32_vi : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
903def DS_MAX_RTN_U32_vi : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
904def DS_AND_RTN_B32_vi : DS_Real_vi<0x29, DS_AND_RTN_B32>;
905def DS_OR_RTN_B32_vi : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
906def DS_XOR_RTN_B32_vi : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
907def DS_MSKOR_RTN_B32_vi : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
908def DS_WRXCHG_RTN_B32_vi : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
909def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
910def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
911def DS_CMPST_RTN_B32_vi : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
912def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
913def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
914def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]915def DS_WRAP_RTN_B32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_B32>;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]916def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]917def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>;
918def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>;
919def DS_READ2ST64_B32_vi : DS_Real_vi<0x38, DS_READ2ST64_B32>;
920def DS_READ_I8_vi : DS_Real_vi<0x39, DS_READ_I8>;
921def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>;
922def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>;
923def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>;
Matt Arsenaultefa1d652017-09-01 18:38:02 +0000[diff] [blame]924def DS_READ_ADDTID_B32_vi : DS_Real_vi<0xb6, DS_READ_ADDTID_B32>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]925def DS_CONSUME_vi : DS_Real_vi<0xbd, DS_CONSUME>;
926def DS_APPEND_vi : DS_Real_vi<0xbe, DS_APPEND>;
927def DS_ORDERED_COUNT_vi : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]928def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
929def DS_PERMUTE_B32_vi : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
930def DS_BPERMUTE_B32_vi : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
931
932def DS_ADD_U64_vi : DS_Real_vi<0x40, DS_ADD_U64>;
933def DS_SUB_U64_vi : DS_Real_vi<0x41, DS_SUB_U64>;
934def DS_RSUB_U64_vi : DS_Real_vi<0x42, DS_RSUB_U64>;
935def DS_INC_U64_vi : DS_Real_vi<0x43, DS_INC_U64>;
936def DS_DEC_U64_vi : DS_Real_vi<0x44, DS_DEC_U64>;
937def DS_MIN_I64_vi : DS_Real_vi<0x45, DS_MIN_I64>;
938def DS_MAX_I64_vi : DS_Real_vi<0x46, DS_MAX_I64>;
939def DS_MIN_U64_vi : DS_Real_vi<0x47, DS_MIN_U64>;
940def DS_MAX_U64_vi : DS_Real_vi<0x48, DS_MAX_U64>;
941def DS_AND_B64_vi : DS_Real_vi<0x49, DS_AND_B64>;
942def DS_OR_B64_vi : DS_Real_vi<0x4a, DS_OR_B64>;
943def DS_XOR_B64_vi : DS_Real_vi<0x4b, DS_XOR_B64>;
944def DS_MSKOR_B64_vi : DS_Real_vi<0x4c, DS_MSKOR_B64>;
945def DS_WRITE_B64_vi : DS_Real_vi<0x4d, DS_WRITE_B64>;
946def DS_WRITE2_B64_vi : DS_Real_vi<0x4E, DS_WRITE2_B64>;
947def DS_WRITE2ST64_B64_vi : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
948def DS_CMPST_B64_vi : DS_Real_vi<0x50, DS_CMPST_B64>;
949def DS_CMPST_F64_vi : DS_Real_vi<0x51, DS_CMPST_F64>;
950def DS_MIN_F64_vi : DS_Real_vi<0x52, DS_MIN_F64>;
951def DS_MAX_F64_vi : DS_Real_vi<0x53, DS_MAX_F64>;
952
Matt Arsenaulted6e8f02017-09-01 18:36:06 +0000[diff] [blame]953def DS_WRITE_B8_D16_HI_vi : DS_Real_vi<0x54, DS_WRITE_B8_D16_HI>;
954def DS_WRITE_B16_D16_HI_vi : DS_Real_vi<0x55, DS_WRITE_B16_D16_HI>;
955
956def DS_READ_U8_D16_vi : DS_Real_vi<0x56, DS_READ_U8_D16>;
957def DS_READ_U8_D16_HI_vi : DS_Real_vi<0x57, DS_READ_U8_D16_HI>;
958def DS_READ_I8_D16_vi : DS_Real_vi<0x58, DS_READ_I8_D16>;
959def DS_READ_I8_D16_HI_vi : DS_Real_vi<0x59, DS_READ_I8_D16_HI>;
960def DS_READ_U16_D16_vi : DS_Real_vi<0x5a, DS_READ_U16_D16>;
961def DS_READ_U16_D16_HI_vi : DS_Real_vi<0x5b, DS_READ_U16_D16_HI>;
962
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]963def DS_ADD_RTN_U64_vi : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
964def DS_SUB_RTN_U64_vi : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
965def DS_RSUB_RTN_U64_vi : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
966def DS_INC_RTN_U64_vi : DS_Real_vi<0x63, DS_INC_RTN_U64>;
967def DS_DEC_RTN_U64_vi : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
968def DS_MIN_RTN_I64_vi : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
969def DS_MAX_RTN_I64_vi : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
970def DS_MIN_RTN_U64_vi : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
971def DS_MAX_RTN_U64_vi : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
972def DS_AND_RTN_B64_vi : DS_Real_vi<0x69, DS_AND_RTN_B64>;
973def DS_OR_RTN_B64_vi : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
974def DS_XOR_RTN_B64_vi : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
975def DS_MSKOR_RTN_B64_vi : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
976def DS_WRXCHG_RTN_B64_vi : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
977def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
978def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]979def DS_CONDXCHG32_RTN_B64_vi : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>;
980def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]981def DS_CMPST_RTN_B64_vi : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
982def DS_CMPST_RTN_F64_vi : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
983def DS_MIN_RTN_F64_vi : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
984def DS_MAX_RTN_F64_vi : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
985
986def DS_READ_B64_vi : DS_Real_vi<0x76, DS_READ_B64>;
987def DS_READ2_B64_vi : DS_Real_vi<0x77, DS_READ2_B64>;
988def DS_READ2ST64_B64_vi : DS_Real_vi<0x78, DS_READ2ST64_B64>;
989
990def DS_ADD_SRC2_U32_vi : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
991def DS_SUB_SRC2_U32_vi : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
992def DS_RSUB_SRC2_U32_vi : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
993def DS_INC_SRC2_U32_vi : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
994def DS_DEC_SRC2_U32_vi : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
995def DS_MIN_SRC2_I32_vi : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
996def DS_MAX_SRC2_I32_vi : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
997def DS_MIN_SRC2_U32_vi : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
998def DS_MAX_SRC2_U32_vi : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
999def DS_AND_SRC2_B32_vi : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
1000def DS_OR_SRC2_B32_vi : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
1001def DS_XOR_SRC2_B32_vi : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
1002def DS_WRITE_SRC2_B32_vi : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
1003def DS_MIN_SRC2_F32_vi : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
1004def DS_MAX_SRC2_F32_vi : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
1005def DS_ADD_SRC2_U64_vi : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
1006def DS_SUB_SRC2_U64_vi : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
1007def DS_RSUB_SRC2_U64_vi : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
1008def DS_INC_SRC2_U64_vi : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
1009def DS_DEC_SRC2_U64_vi : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
1010def DS_MIN_SRC2_I64_vi : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
1011def DS_MAX_SRC2_I64_vi : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
1012def DS_MIN_SRC2_U64_vi : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
1013def DS_MAX_SRC2_U64_vi : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
1014def DS_AND_SRC2_B64_vi : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
1015def DS_OR_SRC2_B64_vi : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
1016def DS_XOR_SRC2_B64_vi : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
1017def DS_WRITE_SRC2_B64_vi : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
1018def DS_MIN_SRC2_F64_vi : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
1019def DS_MAX_SRC2_F64_vi : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]1020def DS_WRITE_B96_vi : DS_Real_vi<0xde, DS_WRITE_B96>;
1021def DS_WRITE_B128_vi : DS_Real_vi<0xdf, DS_WRITE_B128>;
1022def DS_READ_B96_vi : DS_Real_vi<0xfe, DS_READ_B96>;
1023def DS_READ_B128_vi : DS_Real_vi<0xff, DS_READ_B128>;