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gerrit-public.fairphone.software / toolchain / llvm-project / c21deec37b27cf7ab76318e61ab4dd1790573dc7 / . / llvm / lib / Target / X86 / X86SchedBroadwell.td
blob: b575d9848f6696ea5c24526b96fcc9d151e87a9e [file] [log] [blame]
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for Broadwell to support instruction
11// scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14def BroadwellModel : SchedMachineModel {
15 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
16 // instructions per cycle.
17 let IssueWidth = 4;
18 let MicroOpBufferSize = 192; // Based on the reorder buffer.
19 let LoadLatency = 5;
20 let MispredictPenalty = 16;
21
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23 let LoopMicroOpBufferSize = 50;
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]24
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]25 // This flag is set to allow the scheduler to assign a default model to
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]26 // unrecognized opcodes.
27 let CompleteModel = 0;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]28}
29
30let SchedModel = BroadwellModel in {
31
32// Broadwell can issue micro-ops to 8 different ports in one cycle.
33
34// Ports 0, 1, 5, and 6 handle all computation.
35// Port 4 gets the data half of stores. Store data can be available later than
36// the store address, but since we don't model the latency of stores, we can
37// ignore that.
38// Ports 2 and 3 are identical. They handle loads and the address half of
39// stores. Port 7 can handle address calculations.
40def BWPort0 : ProcResource<1>;
41def BWPort1 : ProcResource<1>;
42def BWPort2 : ProcResource<1>;
43def BWPort3 : ProcResource<1>;
44def BWPort4 : ProcResource<1>;
45def BWPort5 : ProcResource<1>;
46def BWPort6 : ProcResource<1>;
47def BWPort7 : ProcResource<1>;
48
49// Many micro-ops are capable of issuing on multiple ports.
50def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>;
51def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>;
52def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;
53def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>;
54def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>;
55def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>;
56def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>;
57def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>;
58def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>;
59def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;
60def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;
61def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;
62
63// 60 Entry Unified Scheduler
64def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,
65 BWPort5, BWPort6, BWPort7]> {
66 let BufferSize=60;
67}
68
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]69// Integer division issued on port 0.
70def BWDivider : ProcResource<1>; // Integer division issued on port 0.
71
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]72// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
73// cycles after the memory operand.
74def : ReadAdvance<ReadAfterLd, 5>;
75
76// Many SchedWrites are defined in pairs with and without a folded load.
77// Instructions with folded loads are usually micro-fused, so they only appear
78// as two micro-ops when queued in the reservation station.
79// This multiclass defines the resource usage for variants with and without
80// folded loads.
81multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]82 list<ProcResourceKind> ExePorts,
83 int Lat, list<int> Res = [1], int UOps = 1> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]84 // Register variant is using a single cycle on ExePort.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]85 def : WriteRes<SchedRW, ExePorts> {
86 let Latency = Lat;
87 let ResourceCycles = Res;
88 let NumMicroOps = UOps;
89 }
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]90
91 // Memory variant also uses a cycle on port 2/3 and adds 5 cycles to the
92 // latency.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]93 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
94 let Latency = !add(Lat, 5);
95 let ResourceCycles = !listconcat([1], Res);
96 let NumMicroOps = UOps;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]97 }
98}
99
100// A folded store needs a cycle on port 4 for the store data, but it does not
101// need an extra port 2/3 cycle to recompute the address.
102def : WriteRes<WriteRMW, [BWPort4]>;
103
104// Arithmetic.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]105defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op.
106defm : BWWriteResPair<WriteIMul, [BWPort1], 3>; // Integer multiplication.
107defm : BWWriteResPair<WriteIDiv, [BWPort0, BWDivider], 25, [1, 10]>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]108def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]109
110def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
111
112// Integer shifts and rotates.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]113defm : BWWriteResPair<WriteShift, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]114
115// Loads, stores, and moves, not folded with other operations.
116def : WriteRes<WriteLoad, [BWPort23]> { let Latency = 5; }
117def : WriteRes<WriteStore, [BWPort237, BWPort4]>;
118def : WriteRes<WriteMove, [BWPort0156]>;
119
120// Idioms that clear a register, like xorps %xmm0, %xmm0.
121// These can often bypass execution ports completely.
122def : WriteRes<WriteZero, []>;
123
Sanjoy Das1074eb22017-12-12 19:11:31 +0000[diff] [blame]124// Treat misc copies as a move.
125def : InstRW<[WriteMove], (instrs COPY)>;
126
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]127// Branches don't produce values, so they have no latency, but they still
128// consume resources. Indirect branches can fold loads.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]129defm : BWWriteResPair<WriteJump, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]130
131// Floating point. This covers both scalar and vector operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]132def : WriteRes<WriteFLoad, [BWPort23]> { let Latency = 5; }
133def : WriteRes<WriteFStore, [BWPort237, BWPort4]>;
134def : WriteRes<WriteFMove, [BWPort5]>;
135
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]136defm : BWWriteResPair<WriteFAdd, [BWPort1], 3>; // Floating point add/sub/compare.
137defm : BWWriteResPair<WriteFMul, [BWPort0], 5>; // Floating point multiplication.
138defm : BWWriteResPair<WriteFDiv, [BWPort0], 12>; // 10-14 cycles. // Floating point division.
139defm : BWWriteResPair<WriteFSqrt, [BWPort0], 15>; // Floating point square root.
140defm : BWWriteResPair<WriteFRcp, [BWPort0], 5>; // Floating point reciprocal estimate.
141defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5>; // Floating point reciprocal square root estimate.
142defm : BWWriteResPair<WriteFMA, [BWPort01], 5>; // Fused Multiply Add.
143defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1>; // Floating point vector shuffles.
144defm : BWWriteResPair<WriteFBlend, [BWPort015], 1>; // Floating point vector blends.
145defm : BWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2]>; // Fp vector variable blends.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]146
147// FMA Scheduling helper class.
148// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
149
150// Vector integer operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]151def : WriteRes<WriteVecLoad, [BWPort23]> { let Latency = 5; }
152def : WriteRes<WriteVecStore, [BWPort237, BWPort4]>;
153def : WriteRes<WriteVecMove, [BWPort015]>;
154
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]155defm : BWWriteResPair<WriteVecALU, [BWPort15], 1>; // Vector integer ALU op, no logicals.
156defm : BWWriteResPair<WriteVecShift, [BWPort0], 1>; // Vector integer shifts.
157defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5>; // Vector integer multiply.
158defm : BWWriteResPair<WriteShuffle, [BWPort5], 1>; // Vector shuffles.
159defm : BWWriteResPair<WriteBlend, [BWPort15], 1>; // Vector blends.
160defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2]>; // Vector variable blends.
161defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 6, [1, 2]>; // Vector MPSAD.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]162
163// Vector bitwise operations.
164// These are often used on both floating point and integer vectors.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]165defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1>; // Vector and/or/xor.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]166
167// Conversion between integer and float.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]168defm : BWWriteResPair<WriteCvtF2I, [BWPort1], 3>; // Float -> Integer.
169defm : BWWriteResPair<WriteCvtI2F, [BWPort1], 4>; // Integer -> Float.
170defm : BWWriteResPair<WriteCvtF2F, [BWPort1], 3>; // Float -> Float size conversion.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]171
172// Strings instructions.
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]173
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]174// Packed Compare Implicit Length Strings, Return Mask
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]175def : WriteRes<WritePCmpIStrM, [BWPort0]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]176 let Latency = 11;
177 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]178 let ResourceCycles = [3];
179}
180def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]181 let Latency = 16;
182 let NumMicroOps = 4;
183 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]184}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]185
186// Packed Compare Explicit Length Strings, Return Mask
187def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
188 let Latency = 19;
189 let NumMicroOps = 9;
190 let ResourceCycles = [4,3,1,1];
191}
192def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
193 let Latency = 24;
194 let NumMicroOps = 10;
195 let ResourceCycles = [4,3,1,1,1];
196}
197
198// Packed Compare Implicit Length Strings, Return Index
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]199def : WriteRes<WritePCmpIStrI, [BWPort0]> {
200 let Latency = 11;
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]201 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]202 let ResourceCycles = [3];
203}
204def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]205 let Latency = 16;
206 let NumMicroOps = 4;
207 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]208}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]209
210// Packed Compare Explicit Length Strings, Return Index
211def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
212 let Latency = 18;
213 let NumMicroOps = 8;
214 let ResourceCycles = [4,3,1];
215}
216def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
217 let Latency = 23;
218 let NumMicroOps = 9;
219 let ResourceCycles = [4,3,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]220}
221
222// AES instructions.
223def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
224 let Latency = 7;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]225 let NumMicroOps = 1;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]226 let ResourceCycles = [1];
227}
228def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]229 let Latency = 12;
230 let NumMicroOps = 2;
231 let ResourceCycles = [1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]232}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]233
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]234def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
235 let Latency = 14;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]236 let NumMicroOps = 2;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]237 let ResourceCycles = [2];
238}
239def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]240 let Latency = 19;
241 let NumMicroOps = 3;
242 let ResourceCycles = [2,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]243}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]244
245def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
246 let Latency = 29;
247 let NumMicroOps = 11;
248 let ResourceCycles = [2,7,2];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]249}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]250def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
251 let Latency = 33;
252 let NumMicroOps = 11;
253 let ResourceCycles = [2,7,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]254}
255
256// Carry-less multiplication instructions.
Simon Pilgrim3b2ff1f2018-03-22 13:37:30 +0000[diff] [blame]257defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]258
259// Catch-all for expensive system instructions.
260def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
261
262// AVX2.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]263defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3>; // Fp 256-bit width vector shuffles.
264defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3>; // 256-bit width vector shuffles.
265defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 2, [2, 1]>; // Variable vector shifts.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]266
267// Old microcoded instructions that nobody use.
268def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
269
270// Fence instructions.
271def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
272
273// Nop, not very useful expect it provides a model for nops!
274def : WriteRes<WriteNop, []>;
275
276////////////////////////////////////////////////////////////////////////////////
277// Horizontal add/sub instructions.
278////////////////////////////////////////////////////////////////////////////////
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]279
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]280defm : BWWriteResPair<WriteFHAdd, [BWPort1], 3>;
281defm : BWWriteResPair<WritePHAdd, [BWPort15], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]282
283// Remaining instrs.
284
285def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
286 let Latency = 1;
287 let NumMicroOps = 1;
288 let ResourceCycles = [1];
289}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]290def: InstRW<[BWWriteResGroup1], (instregex "MMX_MOVD64from64rr",
291 "MMX_MOVD64grr",
292 "MMX_PMOVMSKBrr",
293 "MMX_PSLLDri",
294 "MMX_PSLLDrr",
295 "MMX_PSLLQri",
296 "MMX_PSLLQrr",
297 "MMX_PSLLWri",
298 "MMX_PSLLWrr",
299 "MMX_PSRADri",
300 "MMX_PSRADrr",
301 "MMX_PSRAWri",
302 "MMX_PSRAWrr",
303 "MMX_PSRLDri",
304 "MMX_PSRLDrr",
305 "MMX_PSRLQri",
306 "MMX_PSRLQrr",
307 "MMX_PSRLWri",
308 "MMX_PSRLWrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]309 "(V?)MOVPDI2DIrr",
310 "(V?)MOVPQIto64rr",
311 "(V?)PSLLD(Y?)ri",
312 "(V?)PSLLQ(Y?)ri",
313 "VPSLLVQ(Y?)rr",
314 "(V?)PSLLW(Y?)ri",
315 "(V?)PSRAD(Y?)ri",
316 "(V?)PSRAW(Y?)ri",
317 "(V?)PSRLD(Y?)ri",
318 "(V?)PSRLQ(Y?)ri",
319 "VPSRLVQ(Y?)rr",
320 "(V?)PSRLW(Y?)ri",
321 "VTESTPD(Y?)rr",
322 "VTESTPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]323
324def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
325 let Latency = 1;
326 let NumMicroOps = 1;
327 let ResourceCycles = [1];
328}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]329def: InstRW<[BWWriteResGroup2], (instregex "COMP_FST0r",
330 "COM_FST0r",
331 "UCOM_FPr",
332 "UCOM_Fr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]333
334def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
335 let Latency = 1;
336 let NumMicroOps = 1;
337 let ResourceCycles = [1];
338}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]339def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]340 "MMX_MOVD64to64rr",
341 "MMX_MOVQ2DQrr",
342 "MMX_PALIGNRrri",
343 "MMX_PSHUFBrr",
344 "MMX_PSHUFWri",
345 "MMX_PUNPCKHBWirr",
346 "MMX_PUNPCKHDQirr",
347 "MMX_PUNPCKHWDirr",
348 "MMX_PUNPCKLBWirr",
349 "MMX_PUNPCKLDQirr",
350 "MMX_PUNPCKLWDirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]351 "(V?)ANDNPD(Y?)rr",
352 "(V?)ANDNPS(Y?)rr",
353 "(V?)ANDPD(Y?)rr",
354 "(V?)ANDPS(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]355 "VBROADCASTSSrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]356 "(V?)INSERTPSrr",
357 "(V?)MOV64toPQIrr",
358 "(V?)MOVAPD(Y?)rr",
359 "(V?)MOVAPS(Y?)rr",
360 "(V?)MOVDDUP(Y?)rr",
361 "(V?)MOVDI2PDIrr",
362 "(V?)MOVHLPSrr",
363 "(V?)MOVLHPSrr",
364 "(V?)MOVSDrr",
365 "(V?)MOVSHDUP(Y?)rr",
366 "(V?)MOVSLDUP(Y?)rr",
367 "(V?)MOVSSrr",
368 "(V?)MOVUPD(Y?)rr",
369 "(V?)MOVUPS(Y?)rr",
370 "(V?)ORPD(Y?)rr",
371 "(V?)ORPS(Y?)rr",
372 "(V?)PACKSSDW(Y?)rr",
373 "(V?)PACKSSWB(Y?)rr",
374 "(V?)PACKUSDW(Y?)rr",
375 "(V?)PACKUSWB(Y?)rr",
376 "(V?)PALIGNR(Y?)rri",
377 "(V?)PBLENDW(Y?)rri",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]378 "VPBROADCASTDrr",
379 "VPBROADCASTQrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]380 "VPERMILPD(Y?)ri",
381 "VPERMILPD(Y?)rr",
382 "VPERMILPS(Y?)ri",
383 "VPERMILPS(Y?)rr",
384 "(V?)PMOVSXBDrr",
385 "(V?)PMOVSXBQrr",
386 "(V?)PMOVSXBWrr",
387 "(V?)PMOVSXDQrr",
388 "(V?)PMOVSXWDrr",
389 "(V?)PMOVSXWQrr",
390 "(V?)PMOVZXBDrr",
391 "(V?)PMOVZXBQrr",
392 "(V?)PMOVZXBWrr",
393 "(V?)PMOVZXDQrr",
394 "(V?)PMOVZXWDrr",
395 "(V?)PMOVZXWQrr",
396 "(V?)PSHUFB(Y?)rr",
397 "(V?)PSHUFD(Y?)ri",
398 "(V?)PSHUFHW(Y?)ri",
399 "(V?)PSHUFLW(Y?)ri",
400 "(V?)PSLLDQ(Y?)ri",
401 "(V?)PSRLDQ(Y?)ri",
402 "(V?)PUNPCKHBW(Y?)rr",
403 "(V?)PUNPCKHDQ(Y?)rr",
404 "(V?)PUNPCKHQDQ(Y?)rr",
405 "(V?)PUNPCKHWD(Y?)rr",
406 "(V?)PUNPCKLBW(Y?)rr",
407 "(V?)PUNPCKLDQ(Y?)rr",
408 "(V?)PUNPCKLQDQ(Y?)rr",
409 "(V?)PUNPCKLWD(Y?)rr",
410 "(V?)SHUFPD(Y?)rri",
411 "(V?)SHUFPS(Y?)rri",
412 "(V?)UNPCKHPD(Y?)rr",
413 "(V?)UNPCKHPS(Y?)rr",
414 "(V?)UNPCKLPD(Y?)rr",
415 "(V?)UNPCKLPS(Y?)rr",
416 "(V?)XORPD(Y?)rr",
417 "(V?)XORPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]418
419def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
420 let Latency = 1;
421 let NumMicroOps = 1;
422 let ResourceCycles = [1];
423}
424def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
425
426def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
427 let Latency = 1;
428 let NumMicroOps = 1;
429 let ResourceCycles = [1];
430}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]431def: InstRW<[BWWriteResGroup5], (instregex "FINCSTP",
432 "FNOP")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]433
434def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
435 let Latency = 1;
436 let NumMicroOps = 1;
437 let ResourceCycles = [1];
438}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]439def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
440 "ADC(16|32|64)i",
441 "ADC(8|16|32|64)rr",
442 "ADCX(32|64)rr",
443 "ADOX(32|64)rr",
444 "BT(16|32|64)ri8",
445 "BT(16|32|64)rr",
446 "BTC(16|32|64)ri8",
447 "BTC(16|32|64)rr",
448 "BTR(16|32|64)ri8",
449 "BTR(16|32|64)rr",
450 "BTS(16|32|64)ri8",
451 "BTS(16|32|64)rr",
452 "CDQ",
453 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
454 "CQO",
455 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
456 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
457 "JMP_1",
458 "JMP_4",
459 "RORX(32|64)ri",
460 "SAR(8|16|32|64)r1",
461 "SAR(8|16|32|64)ri",
462 "SARX(32|64)rr",
463 "SBB(16|32|64)ri",
464 "SBB(16|32|64)i",
465 "SBB(8|16|32|64)rr",
466 "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
467 "SHL(8|16|32|64)r1",
468 "SHL(8|16|32|64)ri",
469 "SHLX(32|64)rr",
470 "SHR(8|16|32|64)r1",
471 "SHR(8|16|32|64)ri",
472 "SHRX(32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]473
474def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
475 let Latency = 1;
476 let NumMicroOps = 1;
477 let ResourceCycles = [1];
478}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]479def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr",
480 "BLSI(32|64)rr",
481 "BLSMSK(32|64)rr",
482 "BLSR(32|64)rr",
483 "BZHI(32|64)rr",
484 "LEA(16|32|64)(_32)?r",
485 "MMX_PABSBrr",
486 "MMX_PABSDrr",
487 "MMX_PABSWrr",
488 "MMX_PADDBirr",
489 "MMX_PADDDirr",
490 "MMX_PADDQirr",
491 "MMX_PADDSBirr",
492 "MMX_PADDSWirr",
493 "MMX_PADDUSBirr",
494 "MMX_PADDUSWirr",
495 "MMX_PADDWirr",
496 "MMX_PAVGBirr",
497 "MMX_PAVGWirr",
498 "MMX_PCMPEQBirr",
499 "MMX_PCMPEQDirr",
500 "MMX_PCMPEQWirr",
501 "MMX_PCMPGTBirr",
502 "MMX_PCMPGTDirr",
503 "MMX_PCMPGTWirr",
504 "MMX_PMAXSWirr",
505 "MMX_PMAXUBirr",
506 "MMX_PMINSWirr",
507 "MMX_PMINUBirr",
508 "MMX_PSIGNBrr",
509 "MMX_PSIGNDrr",
510 "MMX_PSIGNWrr",
511 "MMX_PSUBBirr",
512 "MMX_PSUBDirr",
513 "MMX_PSUBQirr",
514 "MMX_PSUBSBirr",
515 "MMX_PSUBSWirr",
516 "MMX_PSUBUSBirr",
517 "MMX_PSUBUSWirr",
518 "MMX_PSUBWirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]519 "(V?)PABSB(Y?)rr",
520 "(V?)PABSD(Y?)rr",
521 "(V?)PABSW(Y?)rr",
522 "(V?)PADDB(Y?)rr",
523 "(V?)PADDD(Y?)rr",
524 "(V?)PADDQ(Y?)rr",
525 "(V?)PADDSB(Y?)rr",
526 "(V?)PADDSW(Y?)rr",
527 "(V?)PADDUSB(Y?)rr",
528 "(V?)PADDUSW(Y?)rr",
529 "(V?)PADDW(Y?)rr",
530 "(V?)PAVGB(Y?)rr",
531 "(V?)PAVGW(Y?)rr",
532 "(V?)PCMPEQB(Y?)rr",
533 "(V?)PCMPEQD(Y?)rr",
534 "(V?)PCMPEQQ(Y?)rr",
535 "(V?)PCMPEQW(Y?)rr",
536 "(V?)PCMPGTB(Y?)rr",
537 "(V?)PCMPGTD(Y?)rr",
538 "(V?)PCMPGTW(Y?)rr",
539 "(V?)PMAXSB(Y?)rr",
540 "(V?)PMAXSD(Y?)rr",
541 "(V?)PMAXSW(Y?)rr",
542 "(V?)PMAXUB(Y?)rr",
543 "(V?)PMAXUD(Y?)rr",
544 "(V?)PMAXUW(Y?)rr",
545 "(V?)PMINSB(Y?)rr",
546 "(V?)PMINSD(Y?)rr",
547 "(V?)PMINSW(Y?)rr",
548 "(V?)PMINUB(Y?)rr",
549 "(V?)PMINUD(Y?)rr",
550 "(V?)PMINUW(Y?)rr",
551 "(V?)PSIGNB(Y?)rr",
552 "(V?)PSIGND(Y?)rr",
553 "(V?)PSIGNW(Y?)rr",
554 "(V?)PSUBB(Y?)rr",
555 "(V?)PSUBD(Y?)rr",
556 "(V?)PSUBQ(Y?)rr",
557 "(V?)PSUBSB(Y?)rr",
558 "(V?)PSUBSW(Y?)rr",
559 "(V?)PSUBUSB(Y?)rr",
560 "(V?)PSUBUSW(Y?)rr",
561 "(V?)PSUBW(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]562
563def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
564 let Latency = 1;
565 let NumMicroOps = 1;
566 let ResourceCycles = [1];
567}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]568def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVQ64rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]569 "MMX_PANDNirr",
570 "MMX_PANDirr",
571 "MMX_PORirr",
572 "MMX_PXORirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]573 "(V?)BLENDPD(Y?)rri",
574 "(V?)BLENDPS(Y?)rri",
575 "(V?)MOVDQA(Y?)rr",
576 "(V?)MOVDQU(Y?)rr",
577 "(V?)MOVPQI2QIrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]578 "VMOVZPQILo2PQIrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]579 "(V?)PANDN(Y?)rr",
580 "(V?)PAND(Y?)rr",
581 "VPBLENDD(Y?)rri",
582 "(V?)POR(Y?)rr",
583 "(V?)PXOR(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]584
585def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
586 let Latency = 1;
587 let NumMicroOps = 1;
588 let ResourceCycles = [1];
589}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]590def: InstRW<[BWWriteResGroup9], (instrs CWDE)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]591def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri",
592 "ADD(8|16|32|64)rr",
593 "ADD(8|16|32|64)i",
594 "AND(8|16|32|64)ri",
595 "AND(8|16|32|64)rr",
596 "AND(8|16|32|64)i",
597 "CBW",
598 "CLC",
599 "CMC",
600 "CMP(8|16|32|64)ri",
601 "CMP(8|16|32|64)rr",
602 "CMP(8|16|32|64)i",
603 "DEC(8|16|32|64)r",
604 "INC(8|16|32|64)r",
605 "LAHF",
606 "MOV(8|16|32|64)rr",
607 "MOV(8|16|32|64)ri",
608 "MOVSX(16|32|64)rr16",
609 "MOVSX(16|32|64)rr32",
610 "MOVSX(16|32|64)rr8",
611 "MOVZX(16|32|64)rr16",
612 "MOVZX(16|32|64)rr8",
613 "NEG(8|16|32|64)r",
614 "NOOP",
615 "NOT(8|16|32|64)r",
616 "OR(8|16|32|64)ri",
617 "OR(8|16|32|64)rr",
618 "OR(8|16|32|64)i",
619 "SAHF",
620 "SGDT64m",
621 "SIDT64m",
622 "SLDT64m",
623 "SMSW16m",
624 "STC",
625 "STRm",
626 "SUB(8|16|32|64)ri",
627 "SUB(8|16|32|64)rr",
628 "SUB(8|16|32|64)i",
629 "SYSCALL",
630 "TEST(8|16|32|64)rr",
631 "TEST(8|16|32|64)i",
632 "TEST(8|16|32|64)ri",
633 "XCHG(16|32|64)rr",
634 "XOR(8|16|32|64)ri",
635 "XOR(8|16|32|64)rr",
636 "XOR(8|16|32|64)i")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]637
638def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
639 let Latency = 1;
640 let NumMicroOps = 2;
641 let ResourceCycles = [1,1];
642}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]643def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
644 "MMX_MOVD64from64rm",
645 "MMX_MOVD64mr",
646 "MMX_MOVNTQmr",
647 "MMX_MOVQ64mr",
648 "MOV(16|32|64)mr",
649 "MOV8mi",
650 "MOV8mr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]651 "MOVNTI_64mr",
652 "MOVNTImr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]653 "ST_FP32m",
654 "ST_FP64m",
655 "ST_FP80m",
656 "VEXTRACTF128mr",
657 "VEXTRACTI128mr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]658 "(V?)MOVAPD(Y?)mr",
659 "(V?)MOVAPS(Y?)mr",
660 "(V?)MOVDQA(Y?)mr",
661 "(V?)MOVDQU(Y?)mr",
662 "(V?)MOVHPDmr",
663 "(V?)MOVHPSmr",
664 "(V?)MOVLPDmr",
665 "(V?)MOVLPSmr",
666 "(V?)MOVNTDQ(V?)mr",
667 "(V?)MOVNTPD(V?)mr",
668 "(V?)MOVNTPS(V?)mr",
669 "(V?)MOVPDI2DImr",
670 "(V?)MOVPQI2QImr",
671 "(V?)MOVPQIto64mr",
672 "(V?)MOVSDmr",
673 "(V?)MOVSSmr",
674 "(V?)MOVUPD(Y?)mr",
675 "(V?)MOVUPS(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]676
677def BWWriteResGroup11 : SchedWriteRes<[BWPort5]> {
678 let Latency = 2;
679 let NumMicroOps = 2;
680 let ResourceCycles = [2];
681}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]682def: InstRW<[BWWriteResGroup11], (instregex "BLENDVPDrr0",
683 "BLENDVPSrr0",
684 "MMX_PINSRWrr",
685 "PBLENDVBrr0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]686 "VBLENDVPD(Y?)rr",
687 "VBLENDVPS(Y?)rr",
688 "VPBLENDVB(Y?)rr",
689 "(V?)PINSRBrr",
690 "(V?)PINSRDrr",
691 "(V?)PINSRQrr",
692 "(V?)PINSRWrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]693
694def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
695 let Latency = 2;
696 let NumMicroOps = 2;
697 let ResourceCycles = [2];
698}
699def: InstRW<[BWWriteResGroup12], (instregex "FDECSTP")>;
700
701def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> {
702 let Latency = 2;
703 let NumMicroOps = 2;
704 let ResourceCycles = [2];
705}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]706def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r1",
707 "ROL(8|16|32|64)ri",
708 "ROR(8|16|32|64)r1",
709 "ROR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]710
711def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
712 let Latency = 2;
713 let NumMicroOps = 2;
714 let ResourceCycles = [2];
715}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]716def: InstRW<[BWWriteResGroup14], (instregex "LFENCE",
717 "MFENCE",
718 "WAIT",
719 "XGETBV")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]720
721def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {
722 let Latency = 2;
723 let NumMicroOps = 2;
724 let ResourceCycles = [1,1];
725}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]726def: InstRW<[BWWriteResGroup15], (instregex "MMX_PEXTRWrr",
727 "VCVTPH2PS(Y?)rr",
728 "(V?)CVTPS2PDrr",
729 "(V?)CVTSS2SDrr",
730 "(V?)EXTRACTPSrr",
731 "(V?)PEXTRBrr",
732 "(V?)PEXTRDrr",
733 "(V?)PEXTRQrr",
734 "(V?)PEXTRWrr",
735 "(V?)PSLLDrr",
736 "(V?)PSLLQrr",
737 "(V?)PSLLWrr",
738 "(V?)PSRADrr",
739 "(V?)PSRAWrr",
740 "(V?)PSRLDrr",
741 "(V?)PSRLQrr",
742 "(V?)PSRLWrr",
743 "(V?)PTESTrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]744
745def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
746 let Latency = 2;
747 let NumMicroOps = 2;
748 let ResourceCycles = [1,1];
749}
750def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
751
752def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
753 let Latency = 2;
754 let NumMicroOps = 2;
755 let ResourceCycles = [1,1];
756}
757def: InstRW<[BWWriteResGroup17], (instregex "MMX_MOVDQ2Qrr")>;
758
759def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
760 let Latency = 2;
761 let NumMicroOps = 2;
762 let ResourceCycles = [1,1];
763}
764def: InstRW<[BWWriteResGroup18], (instregex "SFENCE")>;
765
766def BWWriteResGroup19 : SchedWriteRes<[BWPort06,BWPort15]> {
767 let Latency = 2;
768 let NumMicroOps = 2;
769 let ResourceCycles = [1,1];
770}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]771def: InstRW<[BWWriteResGroup19], (instregex "BEXTR(32|64)rr",
772 "BSWAP(16|32|64)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]773
774def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
775 let Latency = 2;
776 let NumMicroOps = 2;
777 let ResourceCycles = [1,1];
778}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]779def: InstRW<[BWWriteResGroup20], (instrs CWD)>;
Craig Topperb4c78732018-03-19 19:00:32 +0000[diff] [blame]780def: InstRW<[BWWriteResGroup20], (instrs JCXZ, JECXZ, JRCXZ)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]781def: InstRW<[BWWriteResGroup20], (instregex "ADC8i8",
782 "ADC8ri",
783 "CMOV(A|BE)(16|32|64)rr",
784 "SBB8i8",
785 "SBB8ri",
786 "SET(A|BE)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]787
788def BWWriteResGroup21 : SchedWriteRes<[BWPort4,BWPort5,BWPort237]> {
789 let Latency = 2;
790 let NumMicroOps = 3;
791 let ResourceCycles = [1,1,1];
792}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]793def: InstRW<[BWWriteResGroup21], (instregex "(V?)EXTRACTPSmr",
794 "(V?)PEXTRBmr",
795 "(V?)PEXTRDmr",
796 "(V?)PEXTRQmr",
797 "(V?)PEXTRWmr",
798 "(V?)STMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]799
800def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
801 let Latency = 2;
802 let NumMicroOps = 3;
803 let ResourceCycles = [1,1,1];
804}
805def: InstRW<[BWWriteResGroup22], (instregex "FNSTCW16m")>;
806
807def BWWriteResGroup23 : SchedWriteRes<[BWPort4,BWPort237,BWPort06]> {
808 let Latency = 2;
809 let NumMicroOps = 3;
810 let ResourceCycles = [1,1,1];
811}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]812def: InstRW<[BWWriteResGroup23], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]813
814def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
815 let Latency = 2;
816 let NumMicroOps = 3;
817 let ResourceCycles = [1,1,1];
818}
819def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
820
821def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
822 let Latency = 2;
823 let NumMicroOps = 3;
824 let ResourceCycles = [1,1,1];
825}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]826def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]827def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr",
828 "PUSH64i8",
829 "STOSB",
830 "STOSL",
831 "STOSQ",
832 "STOSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]833
834def BWWriteResGroup26 : SchedWriteRes<[BWPort0]> {
835 let Latency = 3;
836 let NumMicroOps = 1;
837 let ResourceCycles = [1];
838}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]839def: InstRW<[BWWriteResGroup26], (instregex "(V?)MOVMSKPD(Y?)rr",
840 "(V?)MOVMSKPS(Y?)rr",
841 "(V?)PMOVMSKB(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]842
843def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
844 let Latency = 3;
845 let NumMicroOps = 1;
846 let ResourceCycles = [1];
847}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]848def: InstRW<[BWWriteResGroup27], (instrs IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]849def: InstRW<[BWWriteResGroup27], (instrs IMUL8r, MUL8r)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]850def: InstRW<[BWWriteResGroup27], (instregex "ADD_FPrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]851 "ADD_FST0r",
852 "ADD_FrST0",
853 "BSF(16|32|64)rr",
854 "BSR(16|32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]855 "LZCNT(16|32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]856 "MMX_CVTPI2PSirr",
857 "PDEP(32|64)rr",
858 "PEXT(32|64)rr",
859 "POPCNT(16|32|64)rr",
860 "SHLD(16|32|64)rri8",
861 "SHRD(16|32|64)rri8",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]862 "SUBR_FPrST0",
863 "SUBR_FST0r",
864 "SUBR_FrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]865 "SUB_FPrST0",
866 "SUB_FST0r",
867 "SUB_FrST0",
868 "TZCNT(16|32|64)rr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]869 "(V?)ADDPD(Y?)rr",
870 "(V?)ADDPS(Y?)rr",
871 "(V?)ADDSDrr",
872 "(V?)ADDSSrr",
873 "(V?)ADDSUBPD(Y?)rr",
874 "(V?)ADDSUBPS(Y?)rr",
875 "(V?)CMPPD(Y?)rri",
876 "(V?)CMPPS(Y?)rri",
877 "(V?)CMPSDrr",
878 "(V?)CMPSSrr",
879 "(V?)COMISDrr",
880 "(V?)COMISSrr",
881 "(V?)CVTDQ2PS(Y?)rr",
882 "(V?)CVTPS2DQ(Y?)rr",
883 "(V?)CVTTPS2DQ(Y?)rr",
884 "(V?)MAX(C?)PD(Y?)rr",
885 "(V?)MAX(C?)PS(Y?)rr",
886 "(V?)MAX(C?)SDrr",
887 "(V?)MAX(C?)SSrr",
888 "(V?)MIN(C?)PD(Y?)rr",
889 "(V?)MIN(C?)PS(Y?)rr",
890 "(V?)MIN(C?)SDrr",
891 "(V?)MIN(C?)SSrr",
892 "(V?)SUBPD(Y?)rr",
893 "(V?)SUBPS(Y?)rr",
894 "(V?)SUBSDrr",
895 "(V?)SUBSSrr",
896 "(V?)UCOMISDrr",
897 "(V?)UCOMISSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]898
899def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> {
900 let Latency = 3;
901 let NumMicroOps = 2;
902 let ResourceCycles = [1,1];
903}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]904def: InstRW<[BWWriteResGroup27_16], (instrs IMUL16rri, IMUL16rri8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]905
906def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
907 let Latency = 3;
908 let NumMicroOps = 1;
909 let ResourceCycles = [1];
910}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]911def: InstRW<[BWWriteResGroup28], (instregex "VBROADCASTSDYrr",
912 "VBROADCASTSSYrr",
913 "VEXTRACTF128rr",
914 "VEXTRACTI128rr",
915 "VINSERTF128rr",
916 "VINSERTI128rr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]917 "VPBROADCASTB(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]918 "VPBROADCASTDYrr",
919 "VPBROADCASTQYrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]920 "VPBROADCASTW(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]921 "VPERM2F128rr",
922 "VPERM2I128rr",
923 "VPERMDYrr",
924 "VPERMPDYri",
925 "VPERMPSYrr",
926 "VPERMQYri",
927 "VPMOVSXBDYrr",
928 "VPMOVSXBQYrr",
929 "VPMOVSXBWYrr",
930 "VPMOVSXDQYrr",
931 "VPMOVSXWDYrr",
932 "VPMOVSXWQYrr",
933 "VPMOVZXBDYrr",
934 "VPMOVZXBQYrr",
935 "VPMOVZXBWYrr",
936 "VPMOVZXDQYrr",
937 "VPMOVZXWDYrr",
938 "VPMOVZXWQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]939
940def BWWriteResGroup29 : SchedWriteRes<[BWPort01]> {
941 let Latency = 3;
942 let NumMicroOps = 1;
943 let ResourceCycles = [1];
944}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]945def: InstRW<[BWWriteResGroup29], (instregex "(V?)MULPD(Y?)rr",
946 "(V?)MULPS(Y?)rr",
947 "(V?)MULSDrr",
948 "(V?)MULSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]949
950def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> {
951 let Latency = 3;
952 let NumMicroOps = 3;
953 let ResourceCycles = [3];
954}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]955def: InstRW<[BWWriteResGroup30], (instregex "XADD(8|16|32|64)rr",
956 "XCHG8rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]957
958def BWWriteResGroup31 : SchedWriteRes<[BWPort0,BWPort5]> {
959 let Latency = 3;
960 let NumMicroOps = 3;
961 let ResourceCycles = [2,1];
962}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]963def: InstRW<[BWWriteResGroup31], (instregex "VPSLLVD(Y?)rr",
964 "VPSRAVD(Y?)rr",
965 "VPSRLVD(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]966
967def BWWriteResGroup32 : SchedWriteRes<[BWPort5,BWPort15]> {
968 let Latency = 3;
969 let NumMicroOps = 3;
970 let ResourceCycles = [2,1];
971}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]972def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDDrr",
973 "MMX_PHADDSWrr",
974 "MMX_PHADDWrr",
975 "MMX_PHSUBDrr",
976 "MMX_PHSUBSWrr",
977 "MMX_PHSUBWrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]978 "(V?)PHADDD(Y?)rr",
979 "(V?)PHADDSW(Y?)rr",
980 "(V?)PHADDW(Y?)rr",
981 "(V?)PHSUBD(Y?)rr",
982 "(V?)PHSUBSW(Y?)rr",
983 "(V?)PHSUBW(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]984
985def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
986 let Latency = 3;
987 let NumMicroOps = 3;
988 let ResourceCycles = [2,1];
989}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]990def: InstRW<[BWWriteResGroup33], (instregex "MMX_PACKSSDWirr",
991 "MMX_PACKSSWBirr",
992 "MMX_PACKUSWBirr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]993
994def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
995 let Latency = 3;
996 let NumMicroOps = 3;
997 let ResourceCycles = [1,2];
998}
999def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
1000
1001def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
1002 let Latency = 3;
1003 let NumMicroOps = 3;
1004 let ResourceCycles = [1,2];
1005}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1006def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r1",
1007 "RCL(8|16|32|64)ri",
1008 "RCR(8|16|32|64)r1",
1009 "RCR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1010
1011def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> {
1012 let Latency = 3;
1013 let NumMicroOps = 3;
1014 let ResourceCycles = [2,1];
1015}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1016def: InstRW<[BWWriteResGroup36], (instregex "ROL(8|16|32|64)rCL",
1017 "ROR(8|16|32|64)rCL",
1018 "SAR(8|16|32|64)rCL",
1019 "SHL(8|16|32|64)rCL",
1020 "SHR(8|16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1021
1022def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
1023 let Latency = 3;
1024 let NumMicroOps = 4;
1025 let ResourceCycles = [1,1,1,1];
1026}
1027def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
1028
1029def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
1030 let Latency = 3;
1031 let NumMicroOps = 4;
1032 let ResourceCycles = [1,1,1,1];
1033}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1034def: InstRW<[BWWriteResGroup38], (instregex "CALL64pcrel32",
1035 "SET(A|BE)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1036
1037def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
1038 let Latency = 4;
1039 let NumMicroOps = 2;
1040 let ResourceCycles = [1,1];
1041}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1042def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVTSD2SI64rr",
1043 "(V?)CVTSD2SIrr",
1044 "(V?)CVTSS2SI64rr",
1045 "(V?)CVTSS2SIrr",
1046 "(V?)CVTTSD2SI64rr",
1047 "(V?)CVTTSD2SIrr",
1048 "(V?)CVTTSS2SI64rr",
1049 "(V?)CVTTSS2SIrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1050
1051def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
1052 let Latency = 4;
1053 let NumMicroOps = 2;
1054 let ResourceCycles = [1,1];
1055}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1056def: InstRW<[BWWriteResGroup40], (instregex "VCVTPS2PDYrr",
1057 "VPSLLDYrr",
1058 "VPSLLQYrr",
1059 "VPSLLWYrr",
1060 "VPSRADYrr",
1061 "VPSRAWYrr",
1062 "VPSRLDYrr",
1063 "VPSRLQYrr",
1064 "VPSRLWYrr",
1065 "VPTESTYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1066
1067def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
1068 let Latency = 4;
1069 let NumMicroOps = 2;
1070 let ResourceCycles = [1,1];
1071}
1072def: InstRW<[BWWriteResGroup41], (instregex "FNSTSW16r")>;
1073
1074def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
1075 let Latency = 4;
1076 let NumMicroOps = 2;
1077 let ResourceCycles = [1,1];
1078}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1079def: InstRW<[BWWriteResGroup42], (instrs IMUL64r, MUL64r, MULX64rr)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1080def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPD2PIirr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1081 "MMX_CVTPI2PDirr",
1082 "MMX_CVTPS2PIirr",
1083 "MMX_CVTTPD2PIirr",
1084 "MMX_CVTTPS2PIirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1085 "(V?)CVTDQ2PDrr",
1086 "(V?)CVTPD2DQrr",
1087 "(V?)CVTPD2PSrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1088 "VCVTPS2PHrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1089 "(V?)CVTSD2SSrr",
1090 "(V?)CVTSI642SDrr",
1091 "(V?)CVTSI2SDrr",
1092 "(V?)CVTSI2SSrr",
1093 "(V?)CVTTPD2DQrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1094
1095def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1096 let Latency = 4;
1097 let NumMicroOps = 4;
1098}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1099def: InstRW<[BWWriteResGroup42_16], (instrs IMUL16r, MUL16r)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1100
1101def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
1102 let Latency = 4;
1103 let NumMicroOps = 3;
1104 let ResourceCycles = [1,1,1];
1105}
1106def: InstRW<[BWWriteResGroup43], (instregex "FNSTSWm")>;
1107
1108def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
1109 let Latency = 4;
1110 let NumMicroOps = 3;
1111 let ResourceCycles = [1,1,1];
1112}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1113def: InstRW<[BWWriteResGroup44], (instregex "ISTT_FP16m",
1114 "ISTT_FP32m",
1115 "ISTT_FP64m",
1116 "IST_F16m",
1117 "IST_F32m",
1118 "IST_FP16m",
1119 "IST_FP32m",
1120 "IST_FP64m",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1121 "VCVTPS2PH(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1122
1123def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
1124 let Latency = 4;
1125 let NumMicroOps = 4;
1126 let ResourceCycles = [4];
1127}
1128def: InstRW<[BWWriteResGroup45], (instregex "FNCLEX")>;
1129
1130def BWWriteResGroup46 : SchedWriteRes<[BWPort015,BWPort0156]> {
1131 let Latency = 4;
1132 let NumMicroOps = 4;
1133 let ResourceCycles = [1,3];
1134}
1135def: InstRW<[BWWriteResGroup46], (instregex "VZEROUPPER")>;
1136
1137def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
1138 let Latency = 5;
1139 let NumMicroOps = 1;
1140 let ResourceCycles = [1];
1141}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1142def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr",
1143 "MMX_PMADDWDirr",
1144 "MMX_PMULHRSWrr",
1145 "MMX_PMULHUWirr",
1146 "MMX_PMULHWirr",
1147 "MMX_PMULLWirr",
1148 "MMX_PMULUDQirr",
1149 "MMX_PSADBWirr",
1150 "MUL_FPrST0",
1151 "MUL_FST0r",
1152 "MUL_FrST0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1153 "(V?)PCMPGTQ(Y?)rr",
1154 "(V?)PHMINPOSUWrr",
1155 "(V?)PMADDUBSW(Y?)rr",
1156 "(V?)PMADDWD(Y?)rr",
1157 "(V?)PMULDQ(Y?)rr",
1158 "(V?)PMULHRSW(Y?)rr",
1159 "(V?)PMULHUW(Y?)rr",
1160 "(V?)PMULHW(Y?)rr",
1161 "(V?)PMULLW(Y?)rr",
1162 "(V?)PMULUDQ(Y?)rr",
1163 "(V?)PSADBW(Y?)rr",
1164 "(V?)RCPPSr",
1165 "(V?)RCPSSr",
1166 "(V?)RSQRTPSr",
1167 "(V?)RSQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1168
1169def BWWriteResGroup48 : SchedWriteRes<[BWPort01]> {
1170 let Latency = 5;
1171 let NumMicroOps = 1;
1172 let ResourceCycles = [1];
1173}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]1174def: InstRW<[BWWriteResGroup48],
1175 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r",
1176 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1177
1178def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
1179 let Latency = 5;
1180 let NumMicroOps = 1;
1181 let ResourceCycles = [1];
1182}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1183def: InstRW<[BWWriteResGroup49], (instregex "MMX_MOVD64rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1184 "MMX_MOVD64to64rm",
1185 "MMX_MOVQ64rm",
1186 "MOV(16|32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1187 "MOVSX(16|32|64)rm16",
1188 "MOVSX(16|32|64)rm32",
1189 "MOVSX(16|32|64)rm8",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1190 "MOVZX(16|32|64)rm16",
1191 "MOVZX(16|32|64)rm8",
1192 "PREFETCHNTA",
1193 "PREFETCHT0",
1194 "PREFETCHT1",
1195 "PREFETCHT2",
1196 "VBROADCASTSSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1197 "(V?)LDDQUrm",
1198 "(V?)MOV64toPQIrm",
1199 "(V?)MOVAPDrm",
1200 "(V?)MOVAPSrm",
1201 "(V?)MOVDDUPrm",
1202 "(V?)MOVDI2PDIrm",
1203 "(V?)MOVDQArm",
1204 "(V?)MOVDQUrm",
1205 "(V?)MOVNTDQArm",
1206 "(V?)MOVQI2PQIrm",
1207 "(V?)MOVSDrm",
1208 "(V?)MOVSHDUPrm",
1209 "(V?)MOVSLDUPrm",
1210 "(V?)MOVSSrm",
1211 "(V?)MOVUPDrm",
1212 "(V?)MOVUPSrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1213 "VPBROADCASTDrm",
1214 "VPBROADCASTQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1215
1216def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
1217 let Latency = 5;
1218 let NumMicroOps = 3;
1219 let ResourceCycles = [1,2];
1220}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1221def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr",
1222 "(V?)HADDPD(Y?)rr",
1223 "(V?)HADDPS(Y?)rr",
1224 "(V?)HSUBPD(Y?)rr",
1225 "(V?)HSUBPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1226
1227def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
1228 let Latency = 5;
1229 let NumMicroOps = 3;
1230 let ResourceCycles = [1,1,1];
1231}
1232def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
1233
1234def BWWriteResGroup52 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1235 let Latency = 4;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1236 let NumMicroOps = 3;
1237 let ResourceCycles = [1,1,1];
1238}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1239def: InstRW<[BWWriteResGroup52], (instrs IMUL32r, MUL32r, MULX32rr)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1240
1241def BWWriteResGroup53 : SchedWriteRes<[BWPort0,BWPort4,BWPort237,BWPort15]> {
1242 let Latency = 5;
1243 let NumMicroOps = 4;
1244 let ResourceCycles = [1,1,1,1];
1245}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1246def: InstRW<[BWWriteResGroup53], (instregex "VMASKMOVPD(Y?)mr",
1247 "VMASKMOVPS(Y?)mr",
1248 "VPMASKMOVD(Y?)mr",
1249 "VPMASKMOVQ(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1250
1251def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
1252 let Latency = 5;
1253 let NumMicroOps = 5;
1254 let ResourceCycles = [1,4];
1255}
1256def: InstRW<[BWWriteResGroup54], (instregex "PAUSE")>;
1257
1258def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
1259 let Latency = 5;
1260 let NumMicroOps = 5;
1261 let ResourceCycles = [1,4];
1262}
1263def: InstRW<[BWWriteResGroup55], (instregex "XSETBV")>;
1264
1265def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> {
1266 let Latency = 5;
1267 let NumMicroOps = 5;
1268 let ResourceCycles = [2,3];
1269}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1270def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(8|16|32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1271
1272def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
1273 let Latency = 5;
1274 let NumMicroOps = 6;
1275 let ResourceCycles = [1,1,4];
1276}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1277def: InstRW<[BWWriteResGroup57], (instregex "PUSHF16", "PUSHF64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1278
1279def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
1280 let Latency = 6;
1281 let NumMicroOps = 1;
1282 let ResourceCycles = [1];
1283}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1284def: InstRW<[BWWriteResGroup58], (instregex "LD_F32m",
1285 "LD_F64m",
1286 "LD_F80m",
1287 "VBROADCASTF128",
1288 "VBROADCASTI128",
1289 "VBROADCASTSDYrm",
1290 "VBROADCASTSSYrm",
1291 "VLDDQUYrm",
1292 "VMOVAPDYrm",
1293 "VMOVAPSYrm",
1294 "VMOVDDUPYrm",
1295 "VMOVDQAYrm",
1296 "VMOVDQUYrm",
1297 "VMOVNTDQAYrm",
1298 "VMOVSHDUPYrm",
1299 "VMOVSLDUPYrm",
1300 "VMOVUPDYrm",
1301 "VMOVUPSYrm",
1302 "VPBROADCASTDYrm",
1303 "VPBROADCASTQYrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1304 "(V?)ROUNDPD(Y?)r",
1305 "(V?)ROUNDPS(Y?)r",
1306 "(V?)ROUNDSDr",
1307 "(V?)ROUNDSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1308
1309def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
1310 let Latency = 6;
1311 let NumMicroOps = 2;
1312 let ResourceCycles = [1,1];
1313}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1314def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSLLDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1315 "MMX_PSLLQrm",
1316 "MMX_PSLLWrm",
1317 "MMX_PSRADrm",
1318 "MMX_PSRAWrm",
1319 "MMX_PSRLDrm",
1320 "MMX_PSRLQrm",
1321 "MMX_PSRLWrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1322 "VCVTPH2PS(Y?)rm",
1323 "(V?)CVTPS2PDrm",
1324 "(V?)CVTSS2SDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1325 "VPSLLVQrm",
1326 "VPSRLVQrm",
1327 "VTESTPDrm",
1328 "VTESTPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1329
1330def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
1331 let Latency = 6;
1332 let NumMicroOps = 2;
1333 let ResourceCycles = [1,1];
1334}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1335def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr",
1336 "VCVTPD2DQYrr",
1337 "VCVTPD2PSYrr",
1338 "VCVTPS2PHYrr",
1339 "VCVTTPD2DQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1340
1341def BWWriteResGroup61 : SchedWriteRes<[BWPort5,BWPort23]> {
1342 let Latency = 6;
1343 let NumMicroOps = 2;
1344 let ResourceCycles = [1,1];
1345}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1346def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNRrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1347 "MMX_PINSRWrm",
1348 "MMX_PSHUFBrm",
1349 "MMX_PSHUFWmi",
1350 "MMX_PUNPCKHBWirm",
1351 "MMX_PUNPCKHDQirm",
1352 "MMX_PUNPCKHWDirm",
1353 "MMX_PUNPCKLBWirm",
1354 "MMX_PUNPCKLDQirm",
1355 "MMX_PUNPCKLWDirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1356 "(V?)ANDNPDrm",
1357 "(V?)ANDNPSrm",
1358 "(V?)ANDPDrm",
1359 "(V?)ANDPSrm",
1360 "(V?)INSERTPSrm",
1361 "(V?)MOVHPDrm",
1362 "(V?)MOVHPSrm",
1363 "(V?)MOVLPDrm",
1364 "(V?)MOVLPSrm",
1365 "(V?)ORPDrm",
1366 "(V?)ORPSrm",
1367 "(V?)PACKSSDWrm",
1368 "(V?)PACKSSWBrm",
1369 "(V?)PACKUSDWrm",
1370 "(V?)PACKUSWBrm",
1371 "(V?)PALIGNRrmi",
1372 "(V?)PBLENDWrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1373 "VPERMILPDmi",
1374 "VPERMILPDrm",
1375 "VPERMILPSmi",
1376 "VPERMILPSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1377 "(V?)PINSRBrm",
1378 "(V?)PINSRDrm",
1379 "(V?)PINSRQrm",
1380 "(V?)PINSRWrm",
1381 "(V?)PMOVSXBDrm",
1382 "(V?)PMOVSXBQrm",
1383 "(V?)PMOVSXBWrm",
1384 "(V?)PMOVSXDQrm",
1385 "(V?)PMOVSXWDrm",
1386 "(V?)PMOVSXWQrm",
1387 "(V?)PMOVZXBDrm",
1388 "(V?)PMOVZXBQrm",
1389 "(V?)PMOVZXBWrm",
1390 "(V?)PMOVZXDQrm",
1391 "(V?)PMOVZXWDrm",
1392 "(V?)PMOVZXWQrm",
1393 "(V?)PSHUFBrm",
1394 "(V?)PSHUFDmi",
1395 "(V?)PSHUFHWmi",
1396 "(V?)PSHUFLWmi",
1397 "(V?)PUNPCKHBWrm",
1398 "(V?)PUNPCKHDQrm",
1399 "(V?)PUNPCKHQDQrm",
1400 "(V?)PUNPCKHWDrm",
1401 "(V?)PUNPCKLBWrm",
1402 "(V?)PUNPCKLDQrm",
1403 "(V?)PUNPCKLQDQrm",
1404 "(V?)PUNPCKLWDrm",
1405 "(V?)SHUFPDrmi",
1406 "(V?)SHUFPSrmi",
1407 "(V?)UNPCKHPDrm",
1408 "(V?)UNPCKHPSrm",
1409 "(V?)UNPCKLPDrm",
1410 "(V?)UNPCKLPSrm",
1411 "(V?)XORPDrm",
1412 "(V?)XORPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1413
1414def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
1415 let Latency = 6;
1416 let NumMicroOps = 2;
1417 let ResourceCycles = [1,1];
1418}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1419def: InstRW<[BWWriteResGroup62], (instregex "FARJMP64",
1420 "JMP(16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1421
1422def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
1423 let Latency = 6;
1424 let NumMicroOps = 2;
1425 let ResourceCycles = [1,1];
1426}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1427def: InstRW<[BWWriteResGroup63], (instregex "ADC(8|16|32|64)rm",
1428 "ADCX(32|64)rm",
1429 "ADOX(32|64)rm",
1430 "BT(16|32|64)mi8",
1431 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
1432 "RORX(32|64)mi",
1433 "SARX(32|64)rm",
1434 "SBB(8|16|32|64)rm",
1435 "SHLX(32|64)rm",
1436 "SHRX(32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1437
1438def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
1439 let Latency = 6;
1440 let NumMicroOps = 2;
1441 let ResourceCycles = [1,1];
1442}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1443def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
1444 "BLSI(32|64)rm",
1445 "BLSMSK(32|64)rm",
1446 "BLSR(32|64)rm",
1447 "BZHI(32|64)rm",
1448 "MMX_PABSBrm",
1449 "MMX_PABSDrm",
1450 "MMX_PABSWrm",
1451 "MMX_PADDBirm",
1452 "MMX_PADDDirm",
1453 "MMX_PADDQirm",
1454 "MMX_PADDSBirm",
1455 "MMX_PADDSWirm",
1456 "MMX_PADDUSBirm",
1457 "MMX_PADDUSWirm",
1458 "MMX_PADDWirm",
1459 "MMX_PAVGBirm",
1460 "MMX_PAVGWirm",
1461 "MMX_PCMPEQBirm",
1462 "MMX_PCMPEQDirm",
1463 "MMX_PCMPEQWirm",
1464 "MMX_PCMPGTBirm",
1465 "MMX_PCMPGTDirm",
1466 "MMX_PCMPGTWirm",
1467 "MMX_PMAXSWirm",
1468 "MMX_PMAXUBirm",
1469 "MMX_PMINSWirm",
1470 "MMX_PMINUBirm",
1471 "MMX_PSIGNBrm",
1472 "MMX_PSIGNDrm",
1473 "MMX_PSIGNWrm",
1474 "MMX_PSUBBirm",
1475 "MMX_PSUBDirm",
1476 "MMX_PSUBQirm",
1477 "MMX_PSUBSBirm",
1478 "MMX_PSUBSWirm",
1479 "MMX_PSUBUSBirm",
1480 "MMX_PSUBUSWirm",
1481 "MMX_PSUBWirm",
1482 "MOVBE(16|32|64)rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1483 "(V?)PABSBrm",
1484 "(V?)PABSDrm",
1485 "(V?)PABSWrm",
1486 "(V?)PADDBrm",
1487 "(V?)PADDDrm",
1488 "(V?)PADDQrm",
1489 "(V?)PADDSBrm",
1490 "(V?)PADDSWrm",
1491 "(V?)PADDUSBrm",
1492 "(V?)PADDUSWrm",
1493 "(V?)PADDWrm",
1494 "(V?)PAVGBrm",
1495 "(V?)PAVGWrm",
1496 "(V?)PCMPEQBrm",
1497 "(V?)PCMPEQDrm",
1498 "(V?)PCMPEQQrm",
1499 "(V?)PCMPEQWrm",
1500 "(V?)PCMPGTBrm",
1501 "(V?)PCMPGTDrm",
1502 "(V?)PCMPGTWrm",
1503 "(V?)PMAXSBrm",
1504 "(V?)PMAXSDrm",
1505 "(V?)PMAXSWrm",
1506 "(V?)PMAXUBrm",
1507 "(V?)PMAXUDrm",
1508 "(V?)PMAXUWrm",
1509 "(V?)PMINSBrm",
1510 "(V?)PMINSDrm",
1511 "(V?)PMINSWrm",
1512 "(V?)PMINUBrm",
1513 "(V?)PMINUDrm",
1514 "(V?)PMINUWrm",
1515 "(V?)PSIGNBrm",
1516 "(V?)PSIGNDrm",
1517 "(V?)PSIGNWrm",
1518 "(V?)PSUBBrm",
1519 "(V?)PSUBDrm",
1520 "(V?)PSUBQrm",
1521 "(V?)PSUBSBrm",
1522 "(V?)PSUBSWrm",
1523 "(V?)PSUBUSBrm",
1524 "(V?)PSUBUSWrm",
1525 "(V?)PSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1526
1527def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
1528 let Latency = 6;
1529 let NumMicroOps = 2;
1530 let ResourceCycles = [1,1];
1531}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1532def: InstRW<[BWWriteResGroup65], (instregex "MMX_PANDNirm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1533 "MMX_PANDirm",
1534 "MMX_PORirm",
1535 "MMX_PXORirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1536 "(V?)BLENDPDrmi",
1537 "(V?)BLENDPSrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1538 "VINSERTF128rm",
1539 "VINSERTI128rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1540 "(V?)PANDNrm",
1541 "(V?)PANDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1542 "VPBLENDDrmi",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1543 "(V?)PORrm",
1544 "(V?)PXORrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1545
1546def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
1547 let Latency = 6;
1548 let NumMicroOps = 2;
1549 let ResourceCycles = [1,1];
1550}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1551def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1552def: InstRW<[BWWriteResGroup66], (instregex "ADD(8|16|32|64)rm",
1553 "AND(8|16|32|64)rm",
1554 "CMP(8|16|32|64)mi",
1555 "CMP(8|16|32|64)mr",
1556 "CMP(8|16|32|64)rm",
1557 "OR(8|16|32|64)rm",
1558 "POP(16|32|64)rmr",
1559 "SUB(8|16|32|64)rm",
1560 "TEST(8|16|32|64)mr",
1561 "TEST(8|16|32|64)mi",
1562 "XOR(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1563
1564def BWWriteResGroup67 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1565 let Latency = 6;
1566 let NumMicroOps = 4;
1567 let ResourceCycles = [1,1,2];
1568}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1569def: InstRW<[BWWriteResGroup67], (instregex "SHLD(16|32|64)rrCL",
1570 "SHRD(16|32|64)rrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1571
1572def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
1573 let Latency = 6;
1574 let NumMicroOps = 4;
1575 let ResourceCycles = [1,1,1,1];
1576}
1577def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
1578
1579def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1580 let Latency = 6;
1581 let NumMicroOps = 4;
1582 let ResourceCycles = [1,1,1,1];
1583}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1584def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8",
1585 "BTR(16|32|64)mi8",
1586 "BTS(16|32|64)mi8",
1587 "SAR(8|16|32|64)m1",
1588 "SAR(8|16|32|64)mi",
1589 "SHL(8|16|32|64)m1",
1590 "SHL(8|16|32|64)mi",
1591 "SHR(8|16|32|64)m1",
1592 "SHR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1593
1594def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1595 let Latency = 6;
1596 let NumMicroOps = 4;
1597 let ResourceCycles = [1,1,1,1];
1598}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1599def: InstRW<[BWWriteResGroup70], (instregex "ADD(8|16|32|64)mi",
1600 "ADD(8|16|32|64)mr",
1601 "AND(8|16|32|64)mi",
1602 "AND(8|16|32|64)mr",
1603 "DEC(8|16|32|64)m",
1604 "INC(8|16|32|64)m",
1605 "NEG(8|16|32|64)m",
1606 "NOT(8|16|32|64)m",
1607 "OR(8|16|32|64)mi",
1608 "OR(8|16|32|64)mr",
1609 "POP(16|32|64)rmm",
1610 "PUSH(16|32|64)rmm",
1611 "SUB(8|16|32|64)mi",
1612 "SUB(8|16|32|64)mr",
1613 "XOR(8|16|32|64)mi",
1614 "XOR(8|16|32|64)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1615
1616def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
1617 let Latency = 6;
1618 let NumMicroOps = 6;
1619 let ResourceCycles = [1,5];
1620}
1621def: InstRW<[BWWriteResGroup71], (instregex "STD")>;
1622
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1623def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
1624 let Latency = 7;
1625 let NumMicroOps = 2;
1626 let ResourceCycles = [1,1];
1627}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1628def: InstRW<[BWWriteResGroup73], (instregex "VPSLLDYrm",
1629 "VPSLLQYrm",
1630 "VPSLLVQYrm",
1631 "VPSLLWYrm",
1632 "VPSRADYrm",
1633 "VPSRAWYrm",
1634 "VPSRLDYrm",
1635 "VPSRLQYrm",
1636 "VPSRLVQYrm",
1637 "VPSRLWYrm",
1638 "VTESTPDYrm",
1639 "VTESTPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1640
1641def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
1642 let Latency = 7;
1643 let NumMicroOps = 2;
1644 let ResourceCycles = [1,1];
1645}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1646def: InstRW<[BWWriteResGroup74], (instregex "FCOM32m",
1647 "FCOM64m",
1648 "FCOMP32m",
1649 "FCOMP64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1650
1651def BWWriteResGroup75 : SchedWriteRes<[BWPort5,BWPort23]> {
1652 let Latency = 7;
1653 let NumMicroOps = 2;
1654 let ResourceCycles = [1,1];
1655}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1656def: InstRW<[BWWriteResGroup75], (instregex "VANDNPDYrm",
1657 "VANDNPSYrm",
1658 "VANDPDYrm",
1659 "VANDPSYrm",
1660 "VORPDYrm",
1661 "VORPSYrm",
1662 "VPACKSSDWYrm",
1663 "VPACKSSWBYrm",
1664 "VPACKUSDWYrm",
1665 "VPACKUSWBYrm",
1666 "VPALIGNRYrmi",
1667 "VPBLENDWYrmi",
1668 "VPERMILPDYmi",
1669 "VPERMILPDYrm",
1670 "VPERMILPSYmi",
1671 "VPERMILPSYrm",
1672 "VPSHUFBYrm",
1673 "VPSHUFDYmi",
1674 "VPSHUFHWYmi",
1675 "VPSHUFLWYmi",
1676 "VPUNPCKHBWYrm",
1677 "VPUNPCKHDQYrm",
1678 "VPUNPCKHQDQYrm",
1679 "VPUNPCKHWDYrm",
1680 "VPUNPCKLBWYrm",
1681 "VPUNPCKLDQYrm",
1682 "VPUNPCKLQDQYrm",
1683 "VPUNPCKLWDYrm",
1684 "VSHUFPDYrmi",
1685 "VSHUFPSYrmi",
1686 "VUNPCKHPDYrm",
1687 "VUNPCKHPSYrm",
1688 "VUNPCKLPDYrm",
1689 "VUNPCKLPSYrm",
1690 "VXORPDYrm",
1691 "VXORPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1692
1693def BWWriteResGroup76 : SchedWriteRes<[BWPort23,BWPort15]> {
1694 let Latency = 7;
1695 let NumMicroOps = 2;
1696 let ResourceCycles = [1,1];
1697}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1698def: InstRW<[BWWriteResGroup76], (instregex "VPABSBYrm",
1699 "VPABSDYrm",
1700 "VPABSWYrm",
1701 "VPADDBYrm",
1702 "VPADDDYrm",
1703 "VPADDQYrm",
1704 "VPADDSBYrm",
1705 "VPADDSWYrm",
1706 "VPADDUSBYrm",
1707 "VPADDUSWYrm",
1708 "VPADDWYrm",
1709 "VPAVGBYrm",
1710 "VPAVGWYrm",
1711 "VPCMPEQBYrm",
1712 "VPCMPEQDYrm",
1713 "VPCMPEQQYrm",
1714 "VPCMPEQWYrm",
1715 "VPCMPGTBYrm",
1716 "VPCMPGTDYrm",
1717 "VPCMPGTWYrm",
1718 "VPMAXSBYrm",
1719 "VPMAXSDYrm",
1720 "VPMAXSWYrm",
1721 "VPMAXUBYrm",
1722 "VPMAXUDYrm",
1723 "VPMAXUWYrm",
1724 "VPMINSBYrm",
1725 "VPMINSDYrm",
1726 "VPMINSWYrm",
1727 "VPMINUBYrm",
1728 "VPMINUDYrm",
1729 "VPMINUWYrm",
1730 "VPSIGNBYrm",
1731 "VPSIGNDYrm",
1732 "VPSIGNWYrm",
1733 "VPSUBBYrm",
1734 "VPSUBDYrm",
1735 "VPSUBQYrm",
1736 "VPSUBSBYrm",
1737 "VPSUBSWYrm",
1738 "VPSUBUSBYrm",
1739 "VPSUBUSWYrm",
1740 "VPSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1741
1742def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
1743 let Latency = 7;
1744 let NumMicroOps = 2;
1745 let ResourceCycles = [1,1];
1746}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1747def: InstRW<[BWWriteResGroup77], (instregex "VBLENDPDYrmi",
1748 "VBLENDPSYrmi",
1749 "VPANDNYrm",
1750 "VPANDYrm",
1751 "VPBLENDDYrmi",
1752 "VPORYrm",
1753 "VPXORYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1754
1755def BWWriteResGroup78 : SchedWriteRes<[BWPort0,BWPort5]> {
1756 let Latency = 7;
1757 let NumMicroOps = 3;
1758 let ResourceCycles = [1,2];
1759}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1760def: InstRW<[BWWriteResGroup78], (instregex "(V?)MPSADBW(Y?)rri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1761
1762def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
1763 let Latency = 7;
1764 let NumMicroOps = 3;
1765 let ResourceCycles = [2,1];
1766}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1767def: InstRW<[BWWriteResGroup79], (instregex "BLENDVPDrm0",
1768 "BLENDVPSrm0",
1769 "MMX_PACKSSDWirm",
1770 "MMX_PACKSSWBirm",
1771 "MMX_PACKUSWBirm",
1772 "PBLENDVBrm0",
1773 "VBLENDVPDrm",
1774 "VBLENDVPSrm",
1775 "VMASKMOVPDrm",
1776 "VMASKMOVPSrm",
1777 "VPBLENDVBrm",
1778 "VPMASKMOVDrm",
1779 "VPMASKMOVQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1780
1781def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
1782 let Latency = 7;
1783 let NumMicroOps = 3;
1784 let ResourceCycles = [1,2];
1785}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1786def: InstRW<[BWWriteResGroup80], (instregex "LEAVE64",
1787 "SCASB",
1788 "SCASL",
1789 "SCASQ",
1790 "SCASW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1791
1792def BWWriteResGroup81 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1793 let Latency = 7;
1794 let NumMicroOps = 3;
1795 let ResourceCycles = [1,1,1];
1796}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1797def: InstRW<[BWWriteResGroup81], (instregex "PSLLDrm",
1798 "PSLLQrm",
1799 "PSLLWrm",
1800 "PSRADrm",
1801 "PSRAWrm",
1802 "PSRLDrm",
1803 "PSRLQrm",
1804 "PSRLWrm",
1805 "PTESTrm",
1806 "VPSLLDrm",
1807 "VPSLLQrm",
1808 "VPSLLWrm",
1809 "VPSRADrm",
1810 "VPSRAWrm",
1811 "VPSRLDrm",
1812 "VPSRLQrm",
1813 "VPSRLWrm",
1814 "VPTESTrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1815
1816def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
1817 let Latency = 7;
1818 let NumMicroOps = 3;
1819 let ResourceCycles = [1,1,1];
1820}
1821def: InstRW<[BWWriteResGroup82], (instregex "FLDCW16m")>;
1822
1823def BWWriteResGroup83 : SchedWriteRes<[BWPort0,BWPort23,BWPort0156]> {
1824 let Latency = 7;
1825 let NumMicroOps = 3;
1826 let ResourceCycles = [1,1,1];
1827}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1828def: InstRW<[BWWriteResGroup83], (instregex "(V?)LDMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1829
1830def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1831 let Latency = 7;
1832 let NumMicroOps = 3;
1833 let ResourceCycles = [1,1,1];
1834}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1835def: InstRW<[BWWriteResGroup84], (instregex "LRETQ",
1836 "RETQ")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1837
1838def BWWriteResGroup85 : SchedWriteRes<[BWPort23,BWPort06,BWPort15]> {
1839 let Latency = 7;
1840 let NumMicroOps = 3;
1841 let ResourceCycles = [1,1,1];
1842}
Craig Toppera42a2ba2017-12-16 18:35:31 +0000[diff] [blame]1843def: InstRW<[BWWriteResGroup85], (instregex "BEXTR(32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1844
1845def BWWriteResGroup86 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1846 let Latency = 7;
1847 let NumMicroOps = 3;
1848 let ResourceCycles = [1,1,1];
1849}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]1850def: InstRW<[BWWriteResGroup86], (instregex "CMOV(A|BE)(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1851
1852def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1853 let Latency = 7;
1854 let NumMicroOps = 5;
1855 let ResourceCycles = [1,1,1,2];
1856}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1857def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m1",
1858 "ROL(8|16|32|64)mi",
1859 "ROR(8|16|32|64)m1",
1860 "ROR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1861
1862def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1863 let Latency = 7;
1864 let NumMicroOps = 5;
1865 let ResourceCycles = [1,1,1,2];
1866}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1867def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1868
1869def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1870 let Latency = 7;
1871 let NumMicroOps = 5;
1872 let ResourceCycles = [1,1,1,1,1];
1873}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1874def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m",
1875 "FARCALL64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1876
1877def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
1878 let Latency = 7;
1879 let NumMicroOps = 7;
1880 let ResourceCycles = [2,2,1,2];
1881}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1882def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1883
1884def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
1885 let Latency = 8;
1886 let NumMicroOps = 2;
1887 let ResourceCycles = [1,1];
1888}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1889def: InstRW<[BWWriteResGroup91], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi8, IMUL64rmi32)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1890def: InstRW<[BWWriteResGroup91], (instrs IMUL8m, MUL8m)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1891def: InstRW<[BWWriteResGroup91], (instregex "BSF(16|32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1892 "BSR(16|32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1893 "LZCNT(16|32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1894 "MMX_CVTPI2PSirm",
1895 "MMX_CVTPS2PIirm",
1896 "MMX_CVTTPS2PIirm",
1897 "PDEP(32|64)rm",
1898 "PEXT(32|64)rm",
1899 "POPCNT(16|32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1900 "TZCNT(16|32|64)rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1901 "(V?)ADDPDrm",
1902 "(V?)ADDPSrm",
1903 "(V?)ADDSDrm",
1904 "(V?)ADDSSrm",
1905 "(V?)ADDSUBPDrm",
1906 "(V?)ADDSUBPSrm",
1907 "(V?)CMPPDrmi",
1908 "(V?)CMPPSrmi",
1909 "(V?)CMPSDrm",
1910 "(V?)CMPSSrm",
1911 "(V?)COMISDrm",
1912 "(V?)COMISSrm",
1913 "(V?)CVTDQ2PSrm",
1914 "(V?)CVTPS2DQrm",
1915 "(V?)CVTTPS2DQrm",
1916 "(V?)MAX(C?)PDrm",
1917 "(V?)MAX(C?)PSrm",
1918 "(V?)MAX(C?)SDrm",
1919 "(V?)MAX(C?)SSrm",
1920 "(V?)MIN(C?)PDrm",
1921 "(V?)MIN(C?)PSrm",
1922 "(V?)MIN(C?)SDrm",
1923 "(V?)MIN(C?)SSrm",
1924 "(V?)SUBPDrm",
1925 "(V?)SUBPSrm",
1926 "(V?)SUBSDrm",
1927 "(V?)SUBSSrm",
1928 "(V?)UCOMISDrm",
1929 "(V?)UCOMISSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1930
1931def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
1932 let Latency = 8;
1933 let NumMicroOps = 3;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1934 let ResourceCycles = [1,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1935}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1936def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1937
1938def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
1939 let Latency = 8;
1940 let NumMicroOps = 5;
1941}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1942def: InstRW<[BWWriteResGroup91_16_2], (instrs IMUL16m, MUL16m)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1943
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1944def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
1945 let Latency = 8;
1946 let NumMicroOps = 2;
1947 let ResourceCycles = [1,1];
1948}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1949def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXBDYrm",
1950 "VPMOVSXBQYrm",
1951 "VPMOVSXBWYrm",
1952 "VPMOVSXDQYrm",
1953 "VPMOVSXWDYrm",
1954 "VPMOVSXWQYrm",
1955 "VPMOVZXWDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1956
1957def BWWriteResGroup93 : SchedWriteRes<[BWPort01,BWPort23]> {
1958 let Latency = 8;
1959 let NumMicroOps = 2;
1960 let ResourceCycles = [1,1];
1961}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]1962def: InstRW<[BWWriteResGroup93], (instregex "(V?)MULPDrm",
1963 "(V?)MULPSrm",
1964 "(V?)MULSDrm",
1965 "(V?)MULSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1966
1967def BWWriteResGroup94 : SchedWriteRes<[BWPort5,BWPort23]> {
1968 let Latency = 8;
1969 let NumMicroOps = 3;
1970 let ResourceCycles = [2,1];
1971}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1972def: InstRW<[BWWriteResGroup94], (instregex "VBLENDVPDYrm",
1973 "VBLENDVPSYrm",
1974 "VMASKMOVPDYrm",
1975 "VMASKMOVPSYrm",
1976 "VPBLENDVBYrm",
1977 "VPMASKMOVDYrm",
1978 "VPMASKMOVQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1979
1980def BWWriteResGroup95 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1981 let Latency = 8;
1982 let NumMicroOps = 4;
1983 let ResourceCycles = [2,1,1];
1984}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1985def: InstRW<[BWWriteResGroup95], (instregex "VPSLLVDrm",
1986 "VPSRAVDrm",
1987 "VPSRLVDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1988
1989def BWWriteResGroup96 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
1990 let Latency = 8;
1991 let NumMicroOps = 4;
1992 let ResourceCycles = [2,1,1];
1993}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1994def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDDrm",
1995 "MMX_PHADDSWrm",
1996 "MMX_PHADDWrm",
1997 "MMX_PHSUBDrm",
1998 "MMX_PHSUBSWrm",
1999 "MMX_PHSUBWrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]2000 "(V?)PHADDDrm",
2001 "(V?)PHADDSWrm",
2002 "(V?)PHADDWrm",
2003 "(V?)PHSUBDrm",
2004 "(V?)PHSUBSWrm",
2005 "(V?)PHSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2006
2007def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
2008 let Latency = 8;
2009 let NumMicroOps = 5;
2010 let ResourceCycles = [1,1,1,2];
2011}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2012def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m1",
2013 "RCL(8|16|32|64)mi",
2014 "RCR(8|16|32|64)m1",
2015 "RCR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2016
2017def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
2018 let Latency = 8;
2019 let NumMicroOps = 5;
2020 let ResourceCycles = [1,1,2,1];
2021}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2022def: InstRW<[BWWriteResGroup98], (instregex "ROR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2023
2024def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
2025 let Latency = 8;
2026 let NumMicroOps = 6;
2027 let ResourceCycles = [1,1,1,3];
2028}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2029def: InstRW<[BWWriteResGroup99], (instregex "ADC(8|16|32|64)mi",
2030 "XCHG(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2031
2032def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2033 let Latency = 8;
2034 let NumMicroOps = 6;
2035 let ResourceCycles = [1,1,1,2,1];
2036}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2037def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mr",
2038 "CMPXCHG(8|16|32|64)rm",
2039 "ROL(8|16|32|64)mCL",
2040 "SAR(8|16|32|64)mCL",
2041 "SBB(8|16|32|64)mi",
2042 "SBB(8|16|32|64)mr",
2043 "SHL(8|16|32|64)mCL",
2044 "SHR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2045
2046def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
2047 let Latency = 9;
2048 let NumMicroOps = 2;
2049 let ResourceCycles = [1,1];
2050}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2051def: InstRW<[BWWriteResGroup101], (instregex "ADD_F32m",
2052 "ADD_F64m",
2053 "ILD_F16m",
2054 "ILD_F32m",
2055 "ILD_F64m",
2056 "SUBR_F32m",
2057 "SUBR_F64m",
2058 "SUB_F32m",
2059 "SUB_F64m",
2060 "VADDPDYrm",
2061 "VADDPSYrm",
2062 "VADDSUBPDYrm",
2063 "VADDSUBPSYrm",
2064 "VCMPPDYrmi",
2065 "VCMPPSYrmi",
2066 "VCVTDQ2PSYrm",
2067 "VCVTPS2DQYrm",
2068 "VCVTTPS2DQYrm",
2069 "VMAX(C?)PDYrm",
2070 "VMAX(C?)PSYrm",
2071 "VMIN(C?)PDYrm",
2072 "VMIN(C?)PSYrm",
2073 "VSUBPDYrm",
2074 "VSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2075
2076def BWWriteResGroup102 : SchedWriteRes<[BWPort5,BWPort23]> {
2077 let Latency = 9;
2078 let NumMicroOps = 2;
2079 let ResourceCycles = [1,1];
2080}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2081def: InstRW<[BWWriteResGroup102], (instregex "VPERM2F128rm",
2082 "VPERM2I128rm",
2083 "VPERMDYrm",
2084 "VPERMPDYmi",
2085 "VPERMPSYrm",
2086 "VPERMQYmi",
2087 "VPMOVZXBDYrm",
2088 "VPMOVZXBQYrm",
2089 "VPMOVZXBWYrm",
2090 "VPMOVZXDQYrm",
2091 "VPMOVZXWQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2092
2093def BWWriteResGroup103 : SchedWriteRes<[BWPort01,BWPort23]> {
2094 let Latency = 9;
2095 let NumMicroOps = 2;
2096 let ResourceCycles = [1,1];
2097}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2098def: InstRW<[BWWriteResGroup103], (instregex "VMULPDYrm",
2099 "VMULPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2100
2101def BWWriteResGroup104 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
2102 let Latency = 9;
2103 let NumMicroOps = 3;
2104 let ResourceCycles = [1,1,1];
2105}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]2106def: InstRW<[BWWriteResGroup104], (instregex "(V?)DPPDrri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2107
2108def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2109 let Latency = 9;
2110 let NumMicroOps = 3;
2111 let ResourceCycles = [1,1,1];
2112}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]2113def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSD2SI64rm",
2114 "(V?)CVTSD2SIrm",
2115 "(V?)CVTSS2SI64rm",
2116 "(V?)CVTSS2SIrm",
2117 "(V?)CVTTSD2SI64rm",
2118 "(V?)CVTTSD2SIrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2119 "VCVTTSS2SI64rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]2120 "(V?)CVTTSS2SIrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2121
2122def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2123 let Latency = 9;
2124 let NumMicroOps = 3;
2125 let ResourceCycles = [1,1,1];
2126}
2127def: InstRW<[BWWriteResGroup106], (instregex "VCVTPS2PDYrm")>;
2128
2129def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2130 let Latency = 9;
2131 let NumMicroOps = 3;
2132 let ResourceCycles = [1,1,1];
2133}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2134def: InstRW<[BWWriteResGroup107], (instrs IMUL64m, MUL64m, MULX64rm)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]2135def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2DQrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2136 "CVTPD2PSrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2137 "CVTTPD2DQrm",
2138 "MMX_CVTPD2PIirm",
2139 "MMX_CVTPI2PDirm",
2140 "MMX_CVTTPD2PIirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]2141 "(V?)CVTDQ2PDrm",
2142 "(V?)CVTSD2SSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2143
2144def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
2145 let Latency = 9;
2146 let NumMicroOps = 3;
2147 let ResourceCycles = [1,1,1];
2148}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]2149def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm",
2150 "VPBROADCASTW(Y?)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2151
2152def BWWriteResGroup109 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2153 let Latency = 9;
2154 let NumMicroOps = 4;
2155 let ResourceCycles = [2,1,1];
2156}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2157def: InstRW<[BWWriteResGroup109], (instregex "VPSLLVDYrm",
2158 "VPSRAVDYrm",
2159 "VPSRLVDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2160
2161def BWWriteResGroup110 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
2162 let Latency = 9;
2163 let NumMicroOps = 4;
2164 let ResourceCycles = [2,1,1];
2165}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2166def: InstRW<[BWWriteResGroup110], (instregex "VPHADDDYrm",
2167 "VPHADDSWYrm",
2168 "VPHADDWYrm",
2169 "VPHSUBDYrm",
2170 "VPHSUBSWYrm",
2171 "VPHSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2172
2173def BWWriteResGroup111 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort0156]> {
2174 let Latency = 9;
2175 let NumMicroOps = 4;
2176 let ResourceCycles = [1,1,1,1];
2177}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2178def: InstRW<[BWWriteResGroup111], (instregex "SHLD(16|32|64)mri8",
2179 "SHRD(16|32|64)mri8")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2180
2181def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
2182 let Latency = 9;
2183 let NumMicroOps = 5;
2184 let ResourceCycles = [1,1,3];
2185}
2186def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>;
2187
2188def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
2189 let Latency = 9;
2190 let NumMicroOps = 5;
2191 let ResourceCycles = [1,2,1,1];
2192}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2193def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
2194 "LSL(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2195
2196def BWWriteResGroup114 : SchedWriteRes<[BWPort0]> {
2197 let Latency = 10;
2198 let NumMicroOps = 2;
2199 let ResourceCycles = [2];
2200}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]2201def: InstRW<[BWWriteResGroup114], (instregex "(V?)PMULLD(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2202
2203def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
2204 let Latency = 10;
2205 let NumMicroOps = 2;
2206 let ResourceCycles = [1,1];
2207}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2208def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm",
2209 "MMX_PMADDWDirm",
2210 "MMX_PMULHRSWrm",
2211 "MMX_PMULHUWirm",
2212 "MMX_PMULHWirm",
2213 "MMX_PMULLWirm",
2214 "MMX_PMULUDQirm",
2215 "MMX_PSADBWirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]2216 "(V?)PCMPGTQrm",
2217 "(V?)PHMINPOSUWrm",
2218 "(V?)PMADDUBSWrm",
2219 "(V?)PMADDWDrm",
2220 "(V?)PMULDQrm",
2221 "(V?)PMULHRSWrm",
2222 "(V?)PMULHUWrm",
2223 "(V?)PMULHWrm",
2224 "(V?)PMULLWrm",
2225 "(V?)PMULUDQrm",
2226 "(V?)PSADBWrm",
2227 "(V?)RCPPSm",
2228 "(V?)RCPSSm",
2229 "(V?)RSQRTPSm",
2230 "(V?)RSQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2231
2232def BWWriteResGroup116 : SchedWriteRes<[BWPort01,BWPort23]> {
2233 let Latency = 10;
2234 let NumMicroOps = 2;
2235 let ResourceCycles = [1,1];
2236}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2237def: InstRW<[BWWriteResGroup116],
2238 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m",
2239 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2240
2241def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
2242 let Latency = 10;
2243 let NumMicroOps = 3;
2244 let ResourceCycles = [2,1];
2245}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2246def: InstRW<[BWWriteResGroup117], (instregex "FICOM16m",
2247 "FICOM32m",
2248 "FICOMP16m",
2249 "FICOMP32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2250
2251def BWWriteResGroup118 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2252 let Latency = 10;
2253 let NumMicroOps = 3;
2254 let ResourceCycles = [1,1,1];
2255}
2256def: InstRW<[BWWriteResGroup118], (instregex "VPTESTYrm")>;
2257
2258def BWWriteResGroup119 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2259 let Latency = 10;
2260 let NumMicroOps = 4;
2261 let ResourceCycles = [1,2,1];
2262}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]2263def: InstRW<[BWWriteResGroup119], (instregex "(V?)HADDPDrm",
2264 "(V?)HADDPSrm",
2265 "(V?)HSUBPDrm",
2266 "(V?)HSUBPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2267
2268def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2269 let Latency = 10;
2270 let NumMicroOps = 4;
2271 let ResourceCycles = [1,1,1,1];
2272}
2273def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
2274
2275def BWWriteResGroup121 : SchedWriteRes<[BWPort1,BWPort23,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2276 let Latency = 9;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2277 let NumMicroOps = 4;
2278 let ResourceCycles = [1,1,1,1];
2279}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2280def: InstRW<[BWWriteResGroup121], (instrs IMUL32m, MUL32m, MULX32rm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2281
2282def BWWriteResGroup122 : SchedWriteRes<[BWPort0]> {
2283 let Latency = 11;
2284 let NumMicroOps = 1;
2285 let ResourceCycles = [1];
2286}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]2287def: InstRW<[BWWriteResGroup122], (instregex "(V?)DIVPSrr",
2288 "(V?)DIVSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2289
2290def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
2291 let Latency = 11;
2292 let NumMicroOps = 2;
2293 let ResourceCycles = [1,1];
2294}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2295def: InstRW<[BWWriteResGroup123], (instregex "MUL_F32m",
2296 "MUL_F64m",
2297 "VPCMPGTQYrm",
2298 "VPMADDUBSWYrm",
2299 "VPMADDWDYrm",
2300 "VPMULDQYrm",
2301 "VPMULHRSWYrm",
2302 "VPMULHUWYrm",
2303 "VPMULHWYrm",
2304 "VPMULLWYrm",
2305 "VPMULUDQYrm",
2306 "VPSADBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2307
2308def BWWriteResGroup124 : SchedWriteRes<[BWPort01,BWPort23]> {
2309 let Latency = 11;
2310 let NumMicroOps = 2;
2311 let ResourceCycles = [1,1];
2312}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2313def: InstRW<[BWWriteResGroup124],
2314 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Ym")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2315
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2316def BWWriteResGroup126 : SchedWriteRes<[BWPort0,BWPort015]> {
2317 let Latency = 11;
2318 let NumMicroOps = 3;
2319 let ResourceCycles = [2,1];
2320}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2321def: InstRW<[BWWriteResGroup126], (instregex "VRCPPSYr",
2322 "VRSQRTPSYr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2323
2324def BWWriteResGroup127 : SchedWriteRes<[BWPort1,BWPort23]> {
2325 let Latency = 11;
2326 let NumMicroOps = 3;
2327 let ResourceCycles = [2,1];
2328}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]2329def: InstRW<[BWWriteResGroup127], (instregex "(V?)ROUNDPDm",
2330 "(V?)ROUNDPSm",
2331 "(V?)ROUNDSDm",
2332 "(V?)ROUNDSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2333
2334def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2335 let Latency = 11;
2336 let NumMicroOps = 3;
2337 let ResourceCycles = [1,1,1];
2338}
2339def: InstRW<[BWWriteResGroup128], (instregex "VCVTDQ2PDYrm")>;
2340
2341def BWWriteResGroup129 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2342 let Latency = 11;
2343 let NumMicroOps = 4;
2344 let ResourceCycles = [1,2,1];
2345}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2346def: InstRW<[BWWriteResGroup129], (instregex "VHADDPDYrm",
2347 "VHADDPSYrm",
2348 "VHSUBPDYrm",
2349 "VHSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2350
2351def BWWriteResGroup130 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2352 let Latency = 11;
2353 let NumMicroOps = 6;
2354 let ResourceCycles = [1,1,1,1,2];
2355}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2356def: InstRW<[BWWriteResGroup130], (instregex "SHLD(16|32|64)mrCL",
2357 "SHRD(16|32|64)mrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2358
2359def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
2360 let Latency = 11;
2361 let NumMicroOps = 7;
2362 let ResourceCycles = [2,2,3];
2363}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2364def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
2365 "RCR(16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2366
2367def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
2368 let Latency = 11;
2369 let NumMicroOps = 9;
2370 let ResourceCycles = [1,4,1,3];
2371}
2372def: InstRW<[BWWriteResGroup132], (instregex "RCL8rCL")>;
2373
2374def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
2375 let Latency = 11;
2376 let NumMicroOps = 11;
2377 let ResourceCycles = [2,9];
2378}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2379def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
2380def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2381
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2382def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
2383 let Latency = 12;
2384 let NumMicroOps = 3;
2385 let ResourceCycles = [2,1];
2386}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2387def: InstRW<[BWWriteResGroup135], (instregex "ADD_FI16m",
2388 "ADD_FI32m",
2389 "SUBR_FI16m",
2390 "SUBR_FI32m",
2391 "SUB_FI16m",
2392 "SUB_FI32m",
Craig Topper40d3b322018-03-22 21:55:20 +0000[diff] [blame]2393 "VROUNDPDYm",
2394 "VROUNDPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2395
2396def BWWriteResGroup136 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2397 let Latency = 12;
2398 let NumMicroOps = 4;
2399 let ResourceCycles = [1,2,1];
2400}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2401def: InstRW<[BWWriteResGroup136], (instregex "(V?)MPSADBWrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2402
2403def BWWriteResGroup137 : SchedWriteRes<[BWPort0]> {
2404 let Latency = 13;
2405 let NumMicroOps = 1;
2406 let ResourceCycles = [1];
2407}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2408def: InstRW<[BWWriteResGroup137], (instregex "SQRTPSr",
2409 "SQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2410
2411def BWWriteResGroup138 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2412 let Latency = 13;
2413 let NumMicroOps = 4;
2414 let ResourceCycles = [1,2,1];
2415}
2416def: InstRW<[BWWriteResGroup138], (instregex "VMPSADBWYrmi")>;
2417
2418def BWWriteResGroup139 : SchedWriteRes<[BWPort0]> {
2419 let Latency = 14;
2420 let NumMicroOps = 1;
2421 let ResourceCycles = [1];
2422}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]2423def: InstRW<[BWWriteResGroup139], (instregex "(V?)DIVPDrr",
2424 "(V?)DIVSDrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2425 "VSQRTPSr",
2426 "VSQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2427
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2428def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2429 let Latency = 14;
2430 let NumMicroOps = 3;
2431 let ResourceCycles = [1,1,1];
2432}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2433def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI16m",
2434 "MUL_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2435
2436def BWWriteResGroup142 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
2437 let Latency = 14;
2438 let NumMicroOps = 4;
2439 let ResourceCycles = [2,1,1];
2440}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]2441def: InstRW<[BWWriteResGroup142], (instregex "(V?)DPPS(Y?)rri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2442
2443def BWWriteResGroup143 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2444 let Latency = 14;
2445 let NumMicroOps = 4;
2446 let ResourceCycles = [1,1,1,1];
2447}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2448def: InstRW<[BWWriteResGroup143], (instregex "(V?)DPPDrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2449
2450def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
2451 let Latency = 14;
2452 let NumMicroOps = 8;
2453 let ResourceCycles = [2,2,1,3];
2454}
2455def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
2456
2457def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
2458 let Latency = 14;
2459 let NumMicroOps = 10;
2460 let ResourceCycles = [2,3,1,4];
2461}
2462def: InstRW<[BWWriteResGroup145], (instregex "RCR8rCL")>;
2463
2464def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
2465 let Latency = 14;
2466 let NumMicroOps = 12;
2467 let ResourceCycles = [2,1,4,5];
2468}
2469def: InstRW<[BWWriteResGroup146], (instregex "XCH_F")>;
2470
2471def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
2472 let Latency = 15;
2473 let NumMicroOps = 1;
2474 let ResourceCycles = [1];
2475}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2476def: InstRW<[BWWriteResGroup147], (instregex "DIVR_FPrST0",
2477 "DIVR_FST0r",
2478 "DIVR_FrST0")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2479
2480def BWWriteResGroup148 : SchedWriteRes<[BWPort0,BWPort23]> {
2481 let Latency = 15;
2482 let NumMicroOps = 3;
2483 let ResourceCycles = [2,1];
2484}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2485def: InstRW<[BWWriteResGroup148], (instregex "(V?)PMULLDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2486
2487def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2488 let Latency = 15;
2489 let NumMicroOps = 10;
2490 let ResourceCycles = [1,1,1,4,1,2];
2491}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2492def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2493
2494def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23]> {
2495 let Latency = 16;
2496 let NumMicroOps = 2;
2497 let ResourceCycles = [1,1];
2498}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2499def: InstRW<[BWWriteResGroup150], (instregex "(V?)DIVPSrm",
2500 "(V?)DIVSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2501
2502def BWWriteResGroup151 : SchedWriteRes<[BWPort0,BWPort23]> {
2503 let Latency = 16;
2504 let NumMicroOps = 3;
2505 let ResourceCycles = [2,1];
2506}
2507def: InstRW<[BWWriteResGroup151], (instregex "VPMULLDYrm")>;
2508
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2509def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2510 let Latency = 16;
2511 let NumMicroOps = 14;
2512 let ResourceCycles = [1,1,1,4,2,5];
2513}
2514def: InstRW<[BWWriteResGroup153], (instregex "CMPXCHG8B")>;
2515
2516def BWWriteResGroup154 : SchedWriteRes<[BWPort5]> {
2517 let Latency = 16;
2518 let NumMicroOps = 16;
2519 let ResourceCycles = [16];
2520}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2521def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2522
2523def BWWriteResGroup155 : SchedWriteRes<[BWPort0,BWPort015]> {
2524 let Latency = 17;
2525 let NumMicroOps = 3;
2526 let ResourceCycles = [2,1];
2527}
2528def: InstRW<[BWWriteResGroup155], (instregex "VDIVPSYrr")>;
2529
2530def BWWriteResGroup156 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2531 let Latency = 17;
2532 let NumMicroOps = 4;
2533 let ResourceCycles = [2,1,1];
2534}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2535def: InstRW<[BWWriteResGroup156], (instregex "VRCPPSYm",
2536 "VRSQRTPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2537
2538def BWWriteResGroup157 : SchedWriteRes<[BWPort0,BWPort23]> {
2539 let Latency = 18;
2540 let NumMicroOps = 2;
2541 let ResourceCycles = [1,1];
2542}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2543def: InstRW<[BWWriteResGroup157], (instregex "SQRTPSm",
2544 "SQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2545
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2546def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
2547 let Latency = 18;
2548 let NumMicroOps = 8;
2549 let ResourceCycles = [1,1,1,5];
2550}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2551def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2552def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2553
2554def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2555 let Latency = 18;
2556 let NumMicroOps = 11;
2557 let ResourceCycles = [2,1,1,3,1,3];
2558}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2559def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2560
2561def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23]> {
2562 let Latency = 19;
2563 let NumMicroOps = 2;
2564 let ResourceCycles = [1,1];
2565}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]2566def: InstRW<[BWWriteResGroup161], (instregex "(V?)DIVPDrm",
2567 "(V?)DIVSDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2568 "VSQRTPSm",
2569 "VSQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2570
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2571def BWWriteResGroup163 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2572 let Latency = 19;
2573 let NumMicroOps = 5;
2574 let ResourceCycles = [2,1,1,1];
2575}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2576def: InstRW<[BWWriteResGroup163], (instregex "(V?)DPPSrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2577
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2578def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
2579 let Latency = 20;
2580 let NumMicroOps = 1;
2581 let ResourceCycles = [1];
2582}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2583def: InstRW<[BWWriteResGroup165], (instregex "DIV_FPrST0",
2584 "DIV_FST0r",
2585 "DIV_FrST0",
2586 "SQRTPDr",
2587 "SQRTSDr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2588
2589def BWWriteResGroup166 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2590 let Latency = 20;
2591 let NumMicroOps = 5;
2592 let ResourceCycles = [2,1,1,1];
2593}
2594def: InstRW<[BWWriteResGroup166], (instregex "VDPPSYrmi")>;
2595
2596def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2597 let Latency = 20;
2598 let NumMicroOps = 8;
2599 let ResourceCycles = [1,1,1,1,1,1,2];
2600}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2601def: InstRW<[BWWriteResGroup167], (instregex "INSB",
2602 "INSL",
2603 "INSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2604
2605def BWWriteResGroup168 : SchedWriteRes<[BWPort0]> {
2606 let Latency = 21;
2607 let NumMicroOps = 1;
2608 let ResourceCycles = [1];
2609}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2610def: InstRW<[BWWriteResGroup168], (instregex "VSQRTPDr",
2611 "VSQRTSDr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2612
2613def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
2614 let Latency = 21;
2615 let NumMicroOps = 2;
2616 let ResourceCycles = [1,1];
2617}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2618def: InstRW<[BWWriteResGroup169], (instregex "DIV_F32m",
2619 "DIV_F64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2620
2621def BWWriteResGroup170 : SchedWriteRes<[BWPort0,BWPort015]> {
2622 let Latency = 21;
2623 let NumMicroOps = 3;
2624 let ResourceCycles = [2,1];
2625}
2626def: InstRW<[BWWriteResGroup170], (instregex "VSQRTPSYr")>;
2627
2628def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2629 let Latency = 21;
2630 let NumMicroOps = 19;
2631 let ResourceCycles = [2,1,4,1,1,4,6];
2632}
2633def: InstRW<[BWWriteResGroup171], (instregex "CMPXCHG16B")>;
2634
2635def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2636 let Latency = 22;
2637 let NumMicroOps = 18;
2638 let ResourceCycles = [1,1,16];
2639}
2640def: InstRW<[BWWriteResGroup172], (instregex "POPF64")>;
2641
2642def BWWriteResGroup173 : SchedWriteRes<[BWPort0,BWPort015]> {
2643 let Latency = 23;
2644 let NumMicroOps = 3;
2645 let ResourceCycles = [2,1];
2646}
2647def: InstRW<[BWWriteResGroup173], (instregex "VDIVPDYrr")>;
2648
2649def BWWriteResGroup174 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2650 let Latency = 23;
2651 let NumMicroOps = 4;
2652 let ResourceCycles = [2,1,1];
2653}
2654def: InstRW<[BWWriteResGroup174], (instregex "VDIVPSYrm")>;
2655
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2656def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2657 let Latency = 23;
2658 let NumMicroOps = 19;
2659 let ResourceCycles = [3,1,15];
2660}
Craig Topper391c6f92017-12-10 01:24:08 +0000[diff] [blame]2661def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2662
2663def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2664 let Latency = 24;
2665 let NumMicroOps = 3;
2666 let ResourceCycles = [1,1,1];
2667}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2668def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI16m",
2669 "DIV_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2670
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2671def BWWriteResGroup179 : SchedWriteRes<[BWPort0,BWPort23]> {
2672 let Latency = 25;
2673 let NumMicroOps = 2;
2674 let ResourceCycles = [1,1];
2675}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2676def: InstRW<[BWWriteResGroup179], (instregex "SQRTPDm",
2677 "SQRTSDm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2678
2679def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
2680 let Latency = 26;
2681 let NumMicroOps = 2;
2682 let ResourceCycles = [1,1];
2683}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2684def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F32m",
2685 "DIVR_F64m",
2686 "VSQRTPDm",
2687 "VSQRTSDm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2688
2689def BWWriteResGroup181 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2690 let Latency = 27;
2691 let NumMicroOps = 4;
2692 let ResourceCycles = [2,1,1];
2693}
2694def: InstRW<[BWWriteResGroup181], (instregex "VSQRTPSYm")>;
2695
2696def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2697 let Latency = 29;
2698 let NumMicroOps = 3;
2699 let ResourceCycles = [1,1,1];
2700}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2701def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI16m",
2702 "DIVR_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2703
2704def BWWriteResGroup183 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2705 let Latency = 29;
2706 let NumMicroOps = 4;
2707 let ResourceCycles = [2,1,1];
2708}
2709def: InstRW<[BWWriteResGroup183], (instregex "VDIVPDYrm")>;
2710
2711def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2712 let Latency = 22;
2713 let NumMicroOps = 7;
2714 let ResourceCycles = [1,3,2,1];
2715}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2716def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2717
2718def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2719 let Latency = 23;
2720 let NumMicroOps = 9;
2721 let ResourceCycles = [1,3,4,1];
2722}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2723def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2724
2725def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2726 let Latency = 24;
2727 let NumMicroOps = 9;
2728 let ResourceCycles = [1,5,2,1];
2729}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2730def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2731
2732def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2733 let Latency = 25;
2734 let NumMicroOps = 7;
2735 let ResourceCycles = [1,3,2,1];
2736}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2737def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm,
2738 VGATHERDPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2739
2740def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2741 let Latency = 26;
2742 let NumMicroOps = 9;
2743 let ResourceCycles = [1,5,2,1];
2744}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2745def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2746
2747def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2748 let Latency = 26;
2749 let NumMicroOps = 14;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame^]2750 let ResourceCycles = [1,4,8,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2751}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2752def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2753
2754def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2755 let Latency = 27;
2756 let NumMicroOps = 9;
2757 let ResourceCycles = [1,5,2,1];
2758}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2759def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2760
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2761def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2762 let Latency = 29;
2763 let NumMicroOps = 27;
2764 let ResourceCycles = [1,5,1,1,19];
2765}
2766def: InstRW<[BWWriteResGroup185], (instregex "XSAVE64")>;
2767
2768def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2769 let Latency = 30;
2770 let NumMicroOps = 28;
2771 let ResourceCycles = [1,6,1,1,19];
2772}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2773def: InstRW<[BWWriteResGroup186], (instregex "^XSAVE$", "XSAVEC", "XSAVES", "XSAVEOPT")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2774
2775def BWWriteResGroup187 : SchedWriteRes<[BWPort01,BWPort15,BWPort015,BWPort0156]> {
2776 let Latency = 31;
2777 let NumMicroOps = 31;
2778 let ResourceCycles = [8,1,21,1];
2779}
2780def: InstRW<[BWWriteResGroup187], (instregex "MMX_EMMS")>;
2781
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2782def BWWriteResGroup189 : SchedWriteRes<[BWPort0,BWPort015]> {
2783 let Latency = 34;
2784 let NumMicroOps = 3;
2785 let ResourceCycles = [2,1];
2786}
2787def: InstRW<[BWWriteResGroup189], (instregex "VSQRTPDYr")>;
2788
2789def BWWriteResGroup190 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
2790 let Latency = 34;
2791 let NumMicroOps = 8;
2792 let ResourceCycles = [2,2,2,1,1];
2793}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2794def: InstRW<[BWWriteResGroup190], (instregex "DIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2795
2796def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
2797 let Latency = 34;
2798 let NumMicroOps = 23;
2799 let ResourceCycles = [1,5,3,4,10];
2800}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2801def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
2802 "IN(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2803
2804def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
2805 let Latency = 35;
2806 let NumMicroOps = 8;
2807 let ResourceCycles = [2,2,2,1,1];
2808}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2809def: InstRW<[BWWriteResGroup193], (instregex "IDIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2810
2811def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2812 let Latency = 35;
2813 let NumMicroOps = 23;
2814 let ResourceCycles = [1,5,2,1,4,10];
2815}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2816def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
2817 "OUT(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2818
2819def BWWriteResGroup195 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2820 let Latency = 40;
2821 let NumMicroOps = 4;
2822 let ResourceCycles = [2,1,1];
2823}
2824def: InstRW<[BWWriteResGroup195], (instregex "VSQRTPDYm")>;
2825
2826def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
2827 let Latency = 42;
2828 let NumMicroOps = 22;
2829 let ResourceCycles = [2,20];
2830}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2831def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2832
2833def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
2834 let Latency = 60;
2835 let NumMicroOps = 64;
2836 let ResourceCycles = [2,2,8,1,10,2,39];
2837}
2838def: InstRW<[BWWriteResGroup197], (instregex "FLDENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2839
2840def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
2841 let Latency = 63;
2842 let NumMicroOps = 88;
2843 let ResourceCycles = [4,4,31,1,2,1,45];
2844}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2845def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2846
2847def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
2848 let Latency = 63;
2849 let NumMicroOps = 90;
2850 let ResourceCycles = [4,2,33,1,2,1,47];
2851}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2852def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2853
2854def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
2855 let Latency = 75;
2856 let NumMicroOps = 15;
2857 let ResourceCycles = [6,3,6];
2858}
2859def: InstRW<[BWWriteResGroup200], (instregex "FNINIT")>;
2860
2861def BWWriteResGroup201 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156]> {
2862 let Latency = 80;
2863 let NumMicroOps = 32;
2864 let ResourceCycles = [7,7,3,3,1,11];
2865}
2866def: InstRW<[BWWriteResGroup201], (instregex "DIV(16|32|64)r")>;
2867
2868def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
2869 let Latency = 115;
2870 let NumMicroOps = 100;
2871 let ResourceCycles = [9,9,11,8,1,11,21,30];
2872}
2873def: InstRW<[BWWriteResGroup202], (instregex "FSTENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2874
2875} // SchedModel
2876