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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000030#include "llvm/ADT/Statistic.h"
31#include "llvm/ADT/STLExtras.h"
Chris Lattner27f29162004-10-26 15:35:58 +000032#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000033using namespace llvm;
34
35namespace {
Chris Lattnerac0b6ae2006-12-06 17:46:33 +000036 static Statistic NumSpills("spiller", "Number of register spills");
37 static Statistic NumStores("spiller", "Number of stores added");
38 static Statistic NumLoads ("spiller", "Number of loads added");
39 static Statistic NumReused("spiller", "Number of values reused");
40 static Statistic NumDSE ("spiller", "Number of dead stores elided");
41 static Statistic NumDCE ("spiller", "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000042
Chris Lattner8c4d88d2004-09-30 01:54:45 +000043 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000044
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000045 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000046 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000047 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000048 cl::Prefix,
49 cl::values(clEnumVal(simple, " simple spiller"),
50 clEnumVal(local, " local spiller"),
51 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000052 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000053}
54
Chris Lattner8c4d88d2004-09-30 01:54:45 +000055//===----------------------------------------------------------------------===//
56// VirtRegMap implementation
57//===----------------------------------------------------------------------===//
58
Chris Lattner29268692006-09-05 02:12:02 +000059VirtRegMap::VirtRegMap(MachineFunction &mf)
60 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
61 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT) {
62 grow();
63}
64
Chris Lattner8c4d88d2004-09-30 01:54:45 +000065void VirtRegMap::grow() {
Chris Lattner7f690e62004-09-30 02:15:18 +000066 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
67 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000068}
69
Chris Lattner8c4d88d2004-09-30 01:54:45 +000070int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
71 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000072 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000073 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000074 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
75 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
76 RC->getAlignment());
77 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000078 ++NumSpills;
79 return frameIndex;
80}
81
82void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
83 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000084 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000085 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000086 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000087}
88
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000089void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +000090 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000091 // Move previous memory references folded to new instruction.
92 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +000093 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000094 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
95 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +000096 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +000097 }
Chris Lattnerdbea9732004-09-30 16:35:08 +000098
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000099 ModRef MRInfo;
Reid Spencerfe463612006-12-07 16:21:19 +0000100 if (TII.getOperandConstraint(OldMI->getOpcode(), OpNo, TOI::TIED_TO)) {
Chris Lattner29268692006-09-05 02:12:02 +0000101 // Folded a two-address operand.
102 MRInfo = isModRef;
103 } else if (OldMI->getOperand(OpNo).isDef()) {
104 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000105 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000106 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000107 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000108
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000109 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000110 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000111}
112
Chris Lattner7f690e62004-09-30 02:15:18 +0000113void VirtRegMap::print(std::ostream &OS) const {
Bill Wendlinge8156192006-12-07 01:30:32 +0000114 OStream LOS(OS);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000115 print(LOS);
116}
117
Bill Wendlinge8156192006-12-07 01:30:32 +0000118void VirtRegMap::print(OStream &OS) const {
Chris Lattner7f690e62004-09-30 02:15:18 +0000119 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000120
Chris Lattner7f690e62004-09-30 02:15:18 +0000121 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000122 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000123 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
124 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
125 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000126
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000127 }
128
129 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000130 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
131 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
132 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
133 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000134}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000135
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000136void VirtRegMap::dump() const {
Bill Wendlinge8156192006-12-07 01:30:32 +0000137 OStream OS = DOUT;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000138 print(OS);
139}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000140
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000141
142//===----------------------------------------------------------------------===//
143// Simple Spiller Implementation
144//===----------------------------------------------------------------------===//
145
146Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000147
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000148namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000149 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000150 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000151 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000152}
153
Chris Lattner35f27052006-05-01 21:16:03 +0000154bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000155 DOUT << "********** REWRITE MACHINE CODE **********\n";
156 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000157 const TargetMachine &TM = MF.getTarget();
158 const MRegisterInfo &MRI = *TM.getRegisterInfo();
159 bool *PhysRegsUsed = MF.getUsedPhysregs();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000160
Chris Lattner4ea1b822004-09-30 02:33:48 +0000161 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
162 // each vreg once (in the case where a spilled vreg is used by multiple
163 // operands). This is always smaller than the number of operands to the
164 // current machine instr, so it should be small.
165 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000166
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000167 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
168 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000169 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000170 MachineBasicBlock &MBB = *MBBI;
171 for (MachineBasicBlock::iterator MII = MBB.begin(),
172 E = MBB.end(); MII != E; ++MII) {
173 MachineInstr &MI = *MII;
174 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000175 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000176 if (MO.isRegister() && MO.getReg())
177 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
178 unsigned VirtReg = MO.getReg();
179 unsigned PhysReg = VRM.getPhys(VirtReg);
180 if (VRM.hasStackSlot(VirtReg)) {
181 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000182 const TargetRegisterClass* RC =
183 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000184
Chris Lattner886dd912005-04-04 21:35:34 +0000185 if (MO.isUse() &&
186 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
187 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000188 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000189 LoadedRegs.push_back(VirtReg);
190 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000191 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000192 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000193
Chris Lattner886dd912005-04-04 21:35:34 +0000194 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000195 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000196 ++NumStores;
197 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000198 }
Chris Lattner886dd912005-04-04 21:35:34 +0000199 PhysRegsUsed[PhysReg] = true;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000200 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000201 } else {
202 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000203 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000204 }
Chris Lattner886dd912005-04-04 21:35:34 +0000205
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000206 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000207 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000208 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000209 }
210 return true;
211}
212
213//===----------------------------------------------------------------------===//
214// Local Spiller Implementation
215//===----------------------------------------------------------------------===//
216
217namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000218 /// LocalSpiller - This spiller does a simple pass over the machine basic
219 /// block to attempt to keep spills in registers as much as possible for
220 /// blocks that have low register pressure (the vreg may be spilled due to
221 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000222 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000223 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000224 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000225 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000226 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000227 MRI = MF.getTarget().getRegisterInfo();
228 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000229 DOUT << "\n**** Local spiller rewriting function '"
230 << MF.getFunction()->getName() << "':\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000231
Chris Lattner7fb64342004-10-01 19:04:51 +0000232 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
233 MBB != E; ++MBB)
234 RewriteMBB(*MBB, VRM);
235 return true;
236 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000237 private:
Chris Lattner35f27052006-05-01 21:16:03 +0000238 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
Chris Lattner7fb64342004-10-01 19:04:51 +0000239 void ClobberPhysReg(unsigned PR, std::map<int, unsigned> &SpillSlots,
Chris Lattner07cf1412006-02-03 00:36:31 +0000240 std::multimap<unsigned, int> &PhysRegs);
Chris Lattner7fb64342004-10-01 19:04:51 +0000241 void ClobberPhysRegOnly(unsigned PR, std::map<int, unsigned> &SpillSlots,
Chris Lattner07cf1412006-02-03 00:36:31 +0000242 std::multimap<unsigned, int> &PhysRegs);
243 void ModifyStackSlot(int Slot, std::map<int, unsigned> &SpillSlots,
244 std::multimap<unsigned, int> &PhysRegs);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000245 };
246}
247
Chris Lattner66cf80f2006-02-03 23:13:58 +0000248/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
249/// top down, keep track of which spills slots are available in each register.
Chris Lattner593c9582006-02-03 23:28:46 +0000250///
251/// Note that not all physregs are created equal here. In particular, some
252/// physregs are reloads that we are allowed to clobber or ignore at any time.
253/// Other physregs are values that the register allocated program is using that
254/// we cannot CHANGE, but we can read if we like. We keep track of this on a
255/// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable
256/// entries. The predicate 'canClobberPhysReg()' checks this bit and
257/// addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000258namespace {
259class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000260 const MRegisterInfo *MRI;
261 const TargetInstrInfo *TII;
262
263 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
264 // register values that are still available, due to being loaded or stored to,
265 // but not invalidated yet.
266 std::map<int, unsigned> SpillSlotsAvailable;
267
268 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
269 // which stack slot values are currently held by a physreg. This is used to
270 // invalidate entries in SpillSlotsAvailable when a physreg is modified.
271 std::multimap<unsigned, int> PhysRegsAvailable;
272
273 void ClobberPhysRegOnly(unsigned PhysReg);
274public:
275 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
276 : MRI(mri), TII(tii) {
277 }
278
279 /// getSpillSlotPhysReg - If the specified stack slot is available in a
280 /// physical register, return that PhysReg, otherwise return 0.
281 unsigned getSpillSlotPhysReg(int Slot) const {
282 std::map<int, unsigned>::const_iterator I = SpillSlotsAvailable.find(Slot);
283 if (I != SpillSlotsAvailable.end())
Chris Lattner593c9582006-02-03 23:28:46 +0000284 return I->second >> 1; // Remove the CanClobber bit.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000285 return 0;
286 }
Chris Lattner540fec62006-02-25 01:51:33 +0000287
288 const MRegisterInfo *getRegInfo() const { return MRI; }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000289
290 /// addAvailable - Mark that the specified stack slot is available in the
Chris Lattner593c9582006-02-03 23:28:46 +0000291 /// specified physreg. If CanClobber is true, the physreg can be modified at
292 /// any time without changing the semantics of the program.
293 void addAvailable(int Slot, unsigned Reg, bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000294 // If this stack slot is thought to be available in some other physreg,
295 // remove its record.
296 ModifyStackSlot(Slot);
297
Chris Lattner66cf80f2006-02-03 23:13:58 +0000298 PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
Jeff Cohen003cecb2006-02-04 03:27:39 +0000299 SpillSlotsAvailable[Slot] = (Reg << 1) | (unsigned)CanClobber;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000300
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000301 DOUT << "Remembering SS#" << Slot << " in physreg "
302 << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000303 }
304
Chris Lattner593c9582006-02-03 23:28:46 +0000305 /// canClobberPhysReg - Return true if the spiller is allowed to change the
306 /// value of the specified stackslot register if it desires. The specified
307 /// stack slot must be available in a physreg for this query to make sense.
308 bool canClobberPhysReg(int Slot) const {
309 assert(SpillSlotsAvailable.count(Slot) && "Slot not available!");
310 return SpillSlotsAvailable.find(Slot)->second & 1;
311 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000312
313 /// ClobberPhysReg - This is called when the specified physreg changes
314 /// value. We use this to invalidate any info about stuff we thing lives in
315 /// it and any of its aliases.
316 void ClobberPhysReg(unsigned PhysReg);
317
318 /// ModifyStackSlot - This method is called when the value in a stack slot
319 /// changes. This removes information about which register the previous value
320 /// for this slot lives in (as the previous value is dead now).
321 void ModifyStackSlot(int Slot);
322};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000323}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000324
325/// ClobberPhysRegOnly - This is called when the specified physreg changes
326/// value. We use this to invalidate any info about stuff we thing lives in it.
327void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
328 std::multimap<unsigned, int>::iterator I =
329 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000330 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000331 int Slot = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000332 PhysRegsAvailable.erase(I++);
Chris Lattner593c9582006-02-03 23:28:46 +0000333 assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000334 "Bidirectional map mismatch!");
335 SpillSlotsAvailable.erase(Slot);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000336 DOUT << "PhysReg " << MRI->getName(PhysReg)
337 << " clobbered, invalidating SS#" << Slot << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000338 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000339}
340
Chris Lattner66cf80f2006-02-03 23:13:58 +0000341/// ClobberPhysReg - This is called when the specified physreg changes
342/// value. We use this to invalidate any info about stuff we thing lives in
343/// it and any of its aliases.
344void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000345 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000346 ClobberPhysRegOnly(*AS);
347 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000348}
349
Chris Lattner07cf1412006-02-03 00:36:31 +0000350/// ModifyStackSlot - This method is called when the value in a stack slot
351/// changes. This removes information about which register the previous value
352/// for this slot lives in (as the previous value is dead now).
Chris Lattner66cf80f2006-02-03 23:13:58 +0000353void AvailableSpills::ModifyStackSlot(int Slot) {
354 std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(Slot);
355 if (It == SpillSlotsAvailable.end()) return;
Chris Lattner593c9582006-02-03 23:28:46 +0000356 unsigned Reg = It->second >> 1;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000357 SpillSlotsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000358
359 // This register may hold the value of multiple stack slots, only remove this
360 // stack slot from the set of values the register contains.
361 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
362 for (; ; ++I) {
363 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
364 "Map inverse broken!");
365 if (I->second == Slot) break;
366 }
367 PhysRegsAvailable.erase(I);
368}
369
370
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000371
Chris Lattner7fb64342004-10-01 19:04:51 +0000372// ReusedOp - For each reused operand, we keep track of a bit of information, in
373// case we need to rollback upon processing a new operand. See comments below.
374namespace {
375 struct ReusedOp {
376 // The MachineInstr operand that reused an available value.
377 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000378
Chris Lattner7fb64342004-10-01 19:04:51 +0000379 // StackSlot - The spill slot of the value being reused.
380 unsigned StackSlot;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000381
Chris Lattner7fb64342004-10-01 19:04:51 +0000382 // PhysRegReused - The physical register the value was available in.
383 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000384
Chris Lattner7fb64342004-10-01 19:04:51 +0000385 // AssignedPhysReg - The physreg that was assigned for use by the reload.
386 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000387
388 // VirtReg - The virtual register itself.
389 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000390
Chris Lattner8a61a752005-10-06 17:19:06 +0000391 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
392 unsigned vreg)
393 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
394 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000395 };
Chris Lattner540fec62006-02-25 01:51:33 +0000396
397 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
398 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000399 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000400 MachineInstr &MI;
401 std::vector<ReusedOp> Reuses;
Evan Chenge077ef62006-11-04 00:21:55 +0000402 bool *PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000403 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000404 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
405 PhysRegsClobbered = new bool[mri->getNumRegs()];
406 std::fill(PhysRegsClobbered, PhysRegsClobbered+mri->getNumRegs(), false);
407 }
408 ~ReuseInfo() {
409 delete[] PhysRegsClobbered;
410 }
Chris Lattner540fec62006-02-25 01:51:33 +0000411
412 bool hasReuses() const {
413 return !Reuses.empty();
414 }
415
416 /// addReuse - If we choose to reuse a virtual register that is already
417 /// available instead of reloading it, remember that we did so.
418 void addReuse(unsigned OpNo, unsigned StackSlot,
419 unsigned PhysRegReused, unsigned AssignedPhysReg,
420 unsigned VirtReg) {
421 // If the reload is to the assigned register anyway, no undo will be
422 // required.
423 if (PhysRegReused == AssignedPhysReg) return;
424
425 // Otherwise, remember this.
426 Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused,
427 AssignedPhysReg, VirtReg));
428 }
Evan Chenge077ef62006-11-04 00:21:55 +0000429
430 void markClobbered(unsigned PhysReg) {
431 PhysRegsClobbered[PhysReg] = true;
432 }
433
434 bool isClobbered(unsigned PhysReg) const {
435 return PhysRegsClobbered[PhysReg];
436 }
Chris Lattner540fec62006-02-25 01:51:33 +0000437
438 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
439 /// is some other operand that is using the specified register, either pick
440 /// a new register to use, or evict the previous reload and use this reg.
441 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
442 AvailableSpills &Spills,
443 std::map<int, MachineInstr*> &MaybeDeadStores) {
444 if (Reuses.empty()) return PhysReg; // This is most often empty.
445
446 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
447 ReusedOp &Op = Reuses[ro];
448 // If we find some other reuse that was supposed to use this register
449 // exactly for its reload, we can change this reload to use ITS reload
450 // register.
451 if (Op.PhysRegReused == PhysReg) {
452 // Yup, use the reload register that we didn't use before.
Evan Chenge077ef62006-11-04 00:21:55 +0000453 unsigned NewReg = Op.AssignedPhysReg;
Chris Lattner47cb7172006-02-25 02:03:40 +0000454 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores);
Chris Lattner540fec62006-02-25 01:51:33 +0000455 } else {
456 // Otherwise, we might also have a problem if a previously reused
457 // value aliases the new register. If so, codegen the previous reload
458 // and use this one.
459 unsigned PRRU = Op.PhysRegReused;
460 const MRegisterInfo *MRI = Spills.getRegInfo();
461 if (MRI->areAliases(PRRU, PhysReg)) {
462 // Okay, we found out that an alias of a reused register
463 // was used. This isn't good because it means we have
464 // to undo a previous reuse.
465 MachineBasicBlock *MBB = MI->getParent();
466 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000467 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
468
469 // Copy Op out of the vector and remove it, we're going to insert an
470 // explicit load for it.
471 ReusedOp NewOp = Op;
472 Reuses.erase(Reuses.begin()+ro);
473
474 // Ok, we're going to try to reload the assigned physreg into the
475 // slot that we were supposed to in the first place. However, that
476 // register could hold a reuse. Check to see if it conflicts or
477 // would prefer us to use a different register.
478 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
479 MI, Spills, MaybeDeadStores);
480
481 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
482 NewOp.StackSlot, AliasRC);
483 Spills.ClobberPhysReg(NewPhysReg);
484 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000485
486 // Any stores to this stack slot are not dead anymore.
Chris Lattner28bad082006-02-25 02:17:31 +0000487 MaybeDeadStores.erase(NewOp.StackSlot);
Chris Lattner540fec62006-02-25 01:51:33 +0000488
Chris Lattnere53f4a02006-05-04 17:52:23 +0000489 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000490
Chris Lattner28bad082006-02-25 02:17:31 +0000491 Spills.addAvailable(NewOp.StackSlot, NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000492 ++NumLoads;
493 DEBUG(MachineBasicBlock::iterator MII = MI;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000494 DOUT << '\t' << *prior(MII));
Chris Lattner540fec62006-02-25 01:51:33 +0000495
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000496 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000497 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000498
499 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000500 return PhysReg;
501 }
502 }
503 }
504 return PhysReg;
505 }
506 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000507}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000508
Chris Lattner7fb64342004-10-01 19:04:51 +0000509
510/// rewriteMBB - Keep track of which spills are available even after the
511/// register allocator is done with them. If possible, avoid reloading vregs.
Chris Lattner35f27052006-05-01 21:16:03 +0000512void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000513
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000514 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000515
Chris Lattner66cf80f2006-02-03 23:13:58 +0000516 // Spills - Keep track of which spilled values are available in physregs so
517 // that we can choose to reuse the physregs instead of emitting reloads.
518 AvailableSpills Spills(MRI, TII);
519
Chris Lattner52b25db2004-10-01 19:47:12 +0000520 // MaybeDeadStores - When we need to write a value back into a stack slot,
521 // keep track of the inserted store. If the stack slot value is never read
522 // (because the value was used from some available register, for example), and
523 // subsequently stored to, the original store is dead. This map keeps track
524 // of inserted stores that are not used. If we see a subsequent store to the
525 // same stack slot, the original store is deleted.
526 std::map<int, MachineInstr*> MaybeDeadStores;
527
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000528 bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
529
Chris Lattner7fb64342004-10-01 19:04:51 +0000530 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
531 MII != E; ) {
532 MachineInstr &MI = *MII;
533 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
534
Chris Lattner540fec62006-02-25 01:51:33 +0000535 /// ReusedOperands - Keep track of operand reuse in case we need to undo
536 /// reuse.
Evan Chenge077ef62006-11-04 00:21:55 +0000537 ReuseInfo ReusedOperands(MI, MRI);
538
539 // Loop over all of the implicit defs, clearing them from our available
540 // sets.
541 const unsigned *ImpDef = TII->getImplicitDefs(MI.getOpcode());
542 if (ImpDef) {
543 for ( ; *ImpDef; ++ImpDef) {
544 PhysRegsUsed[*ImpDef] = true;
545 ReusedOperands.markClobbered(*ImpDef);
546 Spills.ClobberPhysReg(*ImpDef);
547 }
548 }
549
Chris Lattner7fb64342004-10-01 19:04:51 +0000550 // Process all of the spilled uses and all non spilled reg references.
551 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
552 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000553 if (!MO.isRegister() || MO.getReg() == 0)
554 continue; // Ignore non-register operands.
555
556 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
557 // Ignore physregs for spilling, but remember that it is used by this
558 // function.
Chris Lattner886dd912005-04-04 21:35:34 +0000559 PhysRegsUsed[MO.getReg()] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000560 ReusedOperands.markClobbered(MO.getReg());
Chris Lattner50ea01e2005-09-09 20:29:51 +0000561 continue;
562 }
563
564 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
565 "Not a virtual or a physical register?");
566
567 unsigned VirtReg = MO.getReg();
568 if (!VRM.hasStackSlot(VirtReg)) {
569 // This virtual register was assigned a physreg!
570 unsigned Phys = VRM.getPhys(VirtReg);
571 PhysRegsUsed[Phys] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000572 if (MO.isDef())
573 ReusedOperands.markClobbered(Phys);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000574 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000575 continue;
576 }
577
578 // This virtual register is now known to be a spilled value.
579 if (!MO.isUse())
580 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000581
Chris Lattner50ea01e2005-09-09 20:29:51 +0000582 int StackSlot = VRM.getStackSlot(VirtReg);
583 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000584
Chris Lattner50ea01e2005-09-09 20:29:51 +0000585 // Check to see if this stack slot is available.
Chris Lattneraddc55a2006-04-28 01:46:50 +0000586 if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot))) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000587
Chris Lattner29268692006-09-05 02:12:02 +0000588 // This spilled operand might be part of a two-address operand. If this
589 // is the case, then changing it will necessarily require changing the
590 // def part of the instruction as well. However, in some cases, we
591 // aren't allowed to modify the reused register. If none of these cases
592 // apply, reuse it.
593 bool CanReuse = true;
Evan Cheng51cdcd12006-12-07 01:21:59 +0000594 int ti = MI.getInstrDescriptor()->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000595 if (ti != -1 &&
596 MI.getOperand(ti).isReg() &&
597 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000598 // Okay, we have a two address operand. We can reuse this physreg as
Evan Chenge077ef62006-11-04 00:21:55 +0000599 // long as we are allowed to clobber the value and there is an earlier
600 // def that has already clobbered the physreg.
601 CanReuse = Spills.canClobberPhysReg(StackSlot) &&
602 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +0000603 }
604
605 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000606 // If this stack slot value is already available, reuse it!
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000607 DOUT << "Reusing SS#" << StackSlot << " from physreg "
608 << MRI->getName(PhysReg) << " for vreg"
609 << VirtReg <<" instead of reloading into physreg "
610 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000611 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000612
613 // The only technical detail we have is that we don't know that
614 // PhysReg won't be clobbered by a reloaded stack slot that occurs
615 // later in the instruction. In particular, consider 'op V1, V2'.
616 // If V1 is available in physreg R0, we would choose to reuse it
617 // here, instead of reloading it into the register the allocator
618 // indicated (say R1). However, V2 might have to be reloaded
619 // later, and it might indicate that it needs to live in R0. When
620 // this occurs, we need to have information available that
621 // indicates it is safe to use R1 for the reload instead of R0.
622 //
623 // To further complicate matters, we might conflict with an alias,
624 // or R0 and R1 might not be compatible with each other. In this
625 // case, we actually insert a reload for V1 in R1, ensuring that
626 // we can get at R0 or its alias.
627 ReusedOperands.addReuse(i, StackSlot, PhysReg,
628 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000629 if (ti != -1)
630 // Only mark it clobbered if this is a use&def operand.
631 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000632 ++NumReused;
633 continue;
634 }
635
636 // Otherwise we have a situation where we have a two-address instruction
637 // whose mod/ref operand needs to be reloaded. This reload is already
638 // available in some register "PhysReg", but if we used PhysReg as the
639 // operand to our 2-addr instruction, the instruction would modify
640 // PhysReg. This isn't cool if something later uses PhysReg and expects
641 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000642 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000643 // To avoid this problem, and to avoid doing a load right after a store,
644 // we emit a copy from PhysReg into the designated register for this
645 // operand.
646 unsigned DesignatedReg = VRM.getPhys(VirtReg);
647 assert(DesignatedReg && "Must map virtreg to physreg!");
648
649 // Note that, if we reused a register for a previous operand, the
650 // register we want to reload into might not actually be
651 // available. If this occurs, use the register indicated by the
652 // reuser.
653 if (ReusedOperands.hasReuses())
654 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
655 Spills, MaybeDeadStores);
656
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000657 // If the mapped designated register is actually the physreg we have
658 // incoming, we don't need to inserted a dead copy.
659 if (DesignatedReg == PhysReg) {
660 // If this stack slot value is already available, reuse it!
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000661 DOUT << "Reusing SS#" << StackSlot << " from physreg "
662 << MRI->getName(PhysReg) << " for vreg"
663 << VirtReg
664 << " instead of reloading into same physreg.\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000665 MI.getOperand(i).setReg(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000666 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000667 ++NumReused;
668 continue;
669 }
670
Chris Lattneraddc55a2006-04-28 01:46:50 +0000671 const TargetRegisterClass* RC =
672 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
673
674 PhysRegsUsed[DesignatedReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000675 ReusedOperands.markClobbered(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000676 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
677
678 // This invalidates DesignatedReg.
679 Spills.ClobberPhysReg(DesignatedReg);
680
681 Spills.addAvailable(StackSlot, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000682 MI.getOperand(i).setReg(DesignatedReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000683 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000684 ++NumReused;
685 continue;
686 }
687
688 // Otherwise, reload it and remember that we have it.
689 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000690 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000691 const TargetRegisterClass* RC =
692 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000693
Chris Lattner50ea01e2005-09-09 20:29:51 +0000694 // Note that, if we reused a register for a previous operand, the
695 // register we want to reload into might not actually be
696 // available. If this occurs, use the register indicated by the
697 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000698 if (ReusedOperands.hasReuses())
699 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
700 Spills, MaybeDeadStores);
701
Chris Lattner50ea01e2005-09-09 20:29:51 +0000702 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000703 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000704 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000705 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000706 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000707
708 // Any stores to this stack slot are not dead anymore.
709 MaybeDeadStores.erase(StackSlot);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000710 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000711 ++NumLoads;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000712 MI.getOperand(i).setReg(PhysReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000713 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000714 }
715
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000716 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000717
Chris Lattner7fb64342004-10-01 19:04:51 +0000718 // If we have folded references to memory operands, make sure we clear all
719 // physical registers that may contain the value of the spilled virtual
720 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000721 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
722 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000723 DOUT << "Folded vreg: " << I->second.first << " MR: "
724 << I->second.second;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000725 unsigned VirtReg = I->second.first;
726 VirtRegMap::ModRef MR = I->second.second;
Chris Lattnercea86882005-09-19 06:56:21 +0000727 if (!VRM.hasStackSlot(VirtReg)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000728 DOUT << ": No stack slot!\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000729 continue;
730 }
731 int SS = VRM.getStackSlot(VirtReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000732 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000733
734 // If this folded instruction is just a use, check to see if it's a
735 // straight load from the virt reg slot.
736 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
737 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000738 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Chris Lattner6ec36262006-10-12 17:45:38 +0000739 if (FrameIdx == SS) {
740 // If this spill slot is available, turn it into a copy (or nothing)
741 // instead of leaving it as a load!
742 if (unsigned InReg = Spills.getSpillSlotPhysReg(SS)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000743 DOUT << "Promoted Load To Copy: " << MI;
Chris Lattner6ec36262006-10-12 17:45:38 +0000744 MachineFunction &MF = *MBB.getParent();
745 if (DestReg != InReg) {
746 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
747 MF.getSSARegMap()->getRegClass(VirtReg));
748 // Revisit the copy so we make sure to notice the effects of the
749 // operation on the destreg (either needing to RA it if it's
750 // virtual or needing to clobber any values if it's physical).
751 NextMII = &MI;
752 --NextMII; // backtrack to the copy.
753 }
754 VRM.RemoveFromFoldedVirtMap(&MI);
755 MBB.erase(&MI);
756 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +0000757 }
Chris Lattnercea86882005-09-19 06:56:21 +0000758 }
759 }
760 }
761
762 // If this reference is not a use, any previous store is now dead.
763 // Otherwise, the store to this stack slot is not dead anymore.
764 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
765 if (MDSI != MaybeDeadStores.end()) {
766 if (MR & VirtRegMap::isRef) // Previous store is not dead.
767 MaybeDeadStores.erase(MDSI);
768 else {
769 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +0000770 assert(VirtRegMap::isMod && "Can't be modref!");
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000771 DOUT << "Removed dead store:\t" << *MDSI->second;
Chris Lattner35f27052006-05-01 21:16:03 +0000772 MBB.erase(MDSI->second);
Chris Lattner229924a2006-05-01 22:03:24 +0000773 VRM.RemoveFromFoldedVirtMap(MDSI->second);
Chris Lattner35f27052006-05-01 21:16:03 +0000774 MaybeDeadStores.erase(MDSI);
775 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +0000776 }
777 }
778
779 // If the spill slot value is available, and this is a new definition of
780 // the value, the value is not available anymore.
781 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +0000782 // Notice that the value in this stack slot has been modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000783 Spills.ModifyStackSlot(SS);
Chris Lattnercd816392006-02-02 23:29:36 +0000784
785 // If this is *just* a mod of the value, check to see if this is just a
786 // store to the spill slot (i.e. the spill got merged into the copy). If
787 // so, realize that the vreg is available now, and add the store to the
788 // MaybeDeadStore info.
789 int StackSlot;
790 if (!(MR & VirtRegMap::isRef)) {
791 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
792 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
793 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +0000794 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +0000795 // this as a potentially dead store in case there is a subsequent
796 // store into the stack slot without a read from it.
797 MaybeDeadStores[StackSlot] = &MI;
798
Chris Lattnercd816392006-02-02 23:29:36 +0000799 // If the stack slot value was previously available in some other
800 // register, change it now. Otherwise, make the register available,
801 // in PhysReg.
Chris Lattner593c9582006-02-03 23:28:46 +0000802 Spills.addAvailable(StackSlot, SrcReg, false /*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +0000803 }
804 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000805 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000806 }
807
Chris Lattner7fb64342004-10-01 19:04:51 +0000808 // Process all of the spilled defs.
809 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
810 MachineOperand &MO = MI.getOperand(i);
811 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
812 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000813
Chris Lattner7fb64342004-10-01 19:04:51 +0000814 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +0000815 // Check to see if this is a noop copy. If so, eliminate the
816 // instruction before considering the dest reg to be changed.
817 unsigned Src, Dst;
818 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
819 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000820 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner29268692006-09-05 02:12:02 +0000821 MBB.erase(&MI);
822 VRM.RemoveFromFoldedVirtMap(&MI);
823 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +0000824 }
Chris Lattner6ec36262006-10-12 17:45:38 +0000825
826 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +0000827 Spills.ClobberPhysReg(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000828 ReusedOperands.markClobbered(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +0000829
830 // Check to see if this instruction is a load from a stack slot into
831 // a register. If so, this provides the stack slot value in the reg.
832 int FrameIdx;
833 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
834 assert(DestReg == VirtReg && "Unknown load situation!");
835
836 // Otherwise, if it wasn't available, remember that it is now!
837 Spills.addAvailable(FrameIdx, DestReg);
838 goto ProcessNextInst;
839 }
840
Chris Lattner29268692006-09-05 02:12:02 +0000841 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000842 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000843
Chris Lattner84e752a2006-02-03 03:06:49 +0000844 // The only vregs left are stack slot definitions.
845 int StackSlot = VRM.getStackSlot(VirtReg);
846 const TargetRegisterClass *RC =
847 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000848
Chris Lattner29268692006-09-05 02:12:02 +0000849 // If this def is part of a two-address operand, make sure to execute
850 // the store from the correct physical register.
851 unsigned PhysReg;
Evan Chenge6ae14e2006-11-01 23:18:32 +0000852 int TiedOp = TII->findTiedToSrcOperand(MI.getOpcode(), i);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000853 if (TiedOp != -1)
854 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chenge077ef62006-11-04 00:21:55 +0000855 else {
Chris Lattner29268692006-09-05 02:12:02 +0000856 PhysReg = VRM.getPhys(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000857 if (ReusedOperands.isClobbered(PhysReg)) {
858 // Another def has taken the assigned physreg. It must have been a
859 // use&def which got it due to reuse. Undo the reuse!
860 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
861 Spills, MaybeDeadStores);
862 }
863 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000864
Chris Lattner84e752a2006-02-03 03:06:49 +0000865 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000866 ReusedOperands.markClobbered(PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000867 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000868 DOUT << "Store:\t" << *next(MII);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000869 MI.getOperand(i).setReg(PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000870
Chris Lattner109afed2006-02-03 03:16:14 +0000871 // Check to see if this is a noop copy. If so, eliminate the
872 // instruction before considering the dest reg to be changed.
873 {
874 unsigned Src, Dst;
875 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
876 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000877 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner109afed2006-02-03 03:16:14 +0000878 MBB.erase(&MI);
Chris Lattner229924a2006-05-01 22:03:24 +0000879 VRM.RemoveFromFoldedVirtMap(&MI);
Chris Lattner109afed2006-02-03 03:16:14 +0000880 goto ProcessNextInst;
881 }
882 }
883
Chris Lattner84e752a2006-02-03 03:06:49 +0000884 // If there is a dead store to this stack slot, nuke it now.
885 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
886 if (LastStore) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000887 DOUT << "Removed dead store:\t" << *LastStore;
Chris Lattner84e752a2006-02-03 03:06:49 +0000888 ++NumDSE;
889 MBB.erase(LastStore);
Chris Lattner229924a2006-05-01 22:03:24 +0000890 VRM.RemoveFromFoldedVirtMap(LastStore);
Chris Lattner7fb64342004-10-01 19:04:51 +0000891 }
Chris Lattner84e752a2006-02-03 03:06:49 +0000892 LastStore = next(MII);
893
894 // If the stack slot value was previously available in some other
895 // register, change it now. Otherwise, make the register available,
896 // in PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000897 Spills.ModifyStackSlot(StackSlot);
898 Spills.ClobberPhysReg(PhysReg);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000899 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000900 ++NumStores;
Chris Lattner7fb64342004-10-01 19:04:51 +0000901 }
902 }
Chris Lattnercea86882005-09-19 06:56:21 +0000903 ProcessNextInst:
Chris Lattner7fb64342004-10-01 19:04:51 +0000904 MII = NextMII;
905 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000906}
907
Chris Lattnerf7da2c72006-08-24 22:43:55 +0000908
909
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000910llvm::Spiller* llvm::createSpiller() {
911 switch (SpillerOpt) {
912 default: assert(0 && "Unreachable!");
913 case local:
914 return new LocalSpiller();
915 case simple:
916 return new SimpleSpiller();
917 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000918}