Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 1 | //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 10 | // This file implements the VirtRegMap class. |
| 11 | // |
| 12 | // It also contains implementations of the the Spiller interface, which, given a |
| 13 | // virtual register map and a machine function, eliminates all virtual |
| 14 | // references by replacing them with physical register references - adding spill |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 15 | // code as necessary. |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 16 | // |
| 17 | //===----------------------------------------------------------------------===// |
| 18 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 19 | #define DEBUG_TYPE "spiller" |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 20 | #include "VirtRegMap.h" |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 21 | #include "llvm/Function.h" |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 22 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/MachineFunction.h" |
| 24 | #include "llvm/CodeGen/SSARegMap.h" |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 25 | #include "llvm/Target/TargetMachine.h" |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 26 | #include "llvm/Target/TargetInstrInfo.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 27 | #include "llvm/Support/CommandLine.h" |
| 28 | #include "llvm/Support/Debug.h" |
Chris Lattner | a4f0b3a | 2006-08-27 12:54:02 +0000 | [diff] [blame] | 29 | #include "llvm/Support/Compiler.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 30 | #include "llvm/ADT/Statistic.h" |
| 31 | #include "llvm/ADT/STLExtras.h" |
Chris Lattner | 27f2916 | 2004-10-26 15:35:58 +0000 | [diff] [blame] | 32 | #include <algorithm> |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 33 | using namespace llvm; |
| 34 | |
| 35 | namespace { |
Chris Lattner | ac0b6ae | 2006-12-06 17:46:33 +0000 | [diff] [blame] | 36 | static Statistic NumSpills("spiller", "Number of register spills"); |
| 37 | static Statistic NumStores("spiller", "Number of stores added"); |
| 38 | static Statistic NumLoads ("spiller", "Number of loads added"); |
| 39 | static Statistic NumReused("spiller", "Number of values reused"); |
| 40 | static Statistic NumDSE ("spiller", "Number of dead stores elided"); |
| 41 | static Statistic NumDCE ("spiller", "Number of copies elided"); |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 42 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 43 | enum SpillerName { simple, local }; |
Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 44 | |
Andrew Lenharth | ed41f1b | 2006-07-20 17:28:38 +0000 | [diff] [blame] | 45 | static cl::opt<SpillerName> |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 46 | SpillerOpt("spiller", |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 47 | cl::desc("Spiller to use: (default: local)"), |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 48 | cl::Prefix, |
| 49 | cl::values(clEnumVal(simple, " simple spiller"), |
| 50 | clEnumVal(local, " local spiller"), |
| 51 | clEnumValEnd), |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 52 | cl::init(local)); |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 53 | } |
| 54 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 55 | //===----------------------------------------------------------------------===// |
| 56 | // VirtRegMap implementation |
| 57 | //===----------------------------------------------------------------------===// |
| 58 | |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 59 | VirtRegMap::VirtRegMap(MachineFunction &mf) |
| 60 | : TII(*mf.getTarget().getInstrInfo()), MF(mf), |
| 61 | Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT) { |
| 62 | grow(); |
| 63 | } |
| 64 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 65 | void VirtRegMap::grow() { |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 66 | Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg()); |
| 67 | Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg()); |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 68 | } |
| 69 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 70 | int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { |
| 71 | assert(MRegisterInfo::isVirtualRegister(virtReg)); |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 72 | assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 73 | "attempt to assign stack slot to already spilled register"); |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 74 | const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg); |
| 75 | int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(), |
| 76 | RC->getAlignment()); |
| 77 | Virt2StackSlotMap[virtReg] = frameIndex; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 78 | ++NumSpills; |
| 79 | return frameIndex; |
| 80 | } |
| 81 | |
| 82 | void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) { |
| 83 | assert(MRegisterInfo::isVirtualRegister(virtReg)); |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 84 | assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 85 | "attempt to assign stack slot to already spilled register"); |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 86 | Virt2StackSlotMap[virtReg] = frameIndex; |
Alkis Evlogimenos | 38af59a | 2004-05-29 20:38:05 +0000 | [diff] [blame] | 87 | } |
| 88 | |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 89 | void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 90 | unsigned OpNo, MachineInstr *NewMI) { |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 91 | // Move previous memory references folded to new instruction. |
| 92 | MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI); |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 93 | for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI), |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 94 | E = MI2VirtMap.end(); I != E && I->first == OldMI; ) { |
| 95 | MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second)); |
Chris Lattner | dbea973 | 2004-09-30 16:35:08 +0000 | [diff] [blame] | 96 | MI2VirtMap.erase(I++); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 97 | } |
Chris Lattner | dbea973 | 2004-09-30 16:35:08 +0000 | [diff] [blame] | 98 | |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 99 | ModRef MRInfo; |
Evan Cheng | 5c2a460 | 2006-12-08 08:02:34 +0000 | [diff] [blame] | 100 | const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor(); |
| 101 | if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 || |
Evan Cheng | cc22a7a | 2006-12-08 18:45:48 +0000 | [diff] [blame] | 102 | TID->findTiedToSrcOperand(OpNo) != -1) { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 103 | // Folded a two-address operand. |
| 104 | MRInfo = isModRef; |
| 105 | } else if (OldMI->getOperand(OpNo).isDef()) { |
| 106 | MRInfo = isMod; |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 107 | } else { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 108 | MRInfo = isRef; |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 109 | } |
Alkis Evlogimenos | 5f37502 | 2004-03-01 20:05:10 +0000 | [diff] [blame] | 110 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 111 | // add new memory reference |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 112 | MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo))); |
Alkis Evlogimenos | 5f37502 | 2004-03-01 20:05:10 +0000 | [diff] [blame] | 113 | } |
| 114 | |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 115 | void VirtRegMap::print(std::ostream &OS) const { |
Bill Wendling | e815619 | 2006-12-07 01:30:32 +0000 | [diff] [blame] | 116 | OStream LOS(OS); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 117 | print(LOS); |
| 118 | } |
| 119 | |
Bill Wendling | e815619 | 2006-12-07 01:30:32 +0000 | [diff] [blame] | 120 | void VirtRegMap::print(OStream &OS) const { |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 121 | const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo(); |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 122 | |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 123 | OS << "********** REGISTER MAP **********\n"; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 124 | for (unsigned i = MRegisterInfo::FirstVirtualRegister, |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 125 | e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) { |
| 126 | if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) |
| 127 | OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n"; |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 128 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | for (unsigned i = MRegisterInfo::FirstVirtualRegister, |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 132 | e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) |
| 133 | if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) |
| 134 | OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; |
| 135 | OS << '\n'; |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 136 | } |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 137 | |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 138 | void VirtRegMap::dump() const { |
Bill Wendling | e815619 | 2006-12-07 01:30:32 +0000 | [diff] [blame] | 139 | OStream OS = DOUT; |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 140 | print(OS); |
| 141 | } |
Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 142 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 143 | |
| 144 | //===----------------------------------------------------------------------===// |
| 145 | // Simple Spiller Implementation |
| 146 | //===----------------------------------------------------------------------===// |
| 147 | |
| 148 | Spiller::~Spiller() {} |
Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 149 | |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 150 | namespace { |
Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 151 | struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller { |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 152 | bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 153 | }; |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 154 | } |
| 155 | |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 156 | bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 157 | DOUT << "********** REWRITE MACHINE CODE **********\n"; |
| 158 | DOUT << "********** Function: " << MF.getFunction()->getName() << '\n'; |
Chris Lattner | b0f31bf | 2005-01-23 22:45:13 +0000 | [diff] [blame] | 159 | const TargetMachine &TM = MF.getTarget(); |
| 160 | const MRegisterInfo &MRI = *TM.getRegisterInfo(); |
| 161 | bool *PhysRegsUsed = MF.getUsedPhysregs(); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 162 | |
Chris Lattner | 4ea1b82 | 2004-09-30 02:33:48 +0000 | [diff] [blame] | 163 | // LoadedRegs - Keep track of which vregs are loaded, so that we only load |
| 164 | // each vreg once (in the case where a spilled vreg is used by multiple |
| 165 | // operands). This is always smaller than the number of operands to the |
| 166 | // current machine instr, so it should be small. |
| 167 | std::vector<unsigned> LoadedRegs; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 168 | |
Chris Lattner | 0fc27cc | 2004-09-30 02:59:33 +0000 | [diff] [blame] | 169 | for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); |
| 170 | MBBI != E; ++MBBI) { |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 171 | DOUT << MBBI->getBasicBlock()->getName() << ":\n"; |
Chris Lattner | 0fc27cc | 2004-09-30 02:59:33 +0000 | [diff] [blame] | 172 | MachineBasicBlock &MBB = *MBBI; |
| 173 | for (MachineBasicBlock::iterator MII = MBB.begin(), |
| 174 | E = MBB.end(); MII != E; ++MII) { |
| 175 | MachineInstr &MI = *MII; |
| 176 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 177 | MachineOperand &MO = MI.getOperand(i); |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 178 | if (MO.isRegister() && MO.getReg()) |
| 179 | if (MRegisterInfo::isVirtualRegister(MO.getReg())) { |
| 180 | unsigned VirtReg = MO.getReg(); |
| 181 | unsigned PhysReg = VRM.getPhys(VirtReg); |
| 182 | if (VRM.hasStackSlot(VirtReg)) { |
| 183 | int StackSlot = VRM.getStackSlot(VirtReg); |
Chris Lattner | bf9716b | 2005-09-30 01:29:00 +0000 | [diff] [blame] | 184 | const TargetRegisterClass* RC = |
| 185 | MF.getSSARegMap()->getRegClass(VirtReg); |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 186 | |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 187 | if (MO.isUse() && |
| 188 | std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg) |
| 189 | == LoadedRegs.end()) { |
Chris Lattner | bf9716b | 2005-09-30 01:29:00 +0000 | [diff] [blame] | 190 | MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 191 | LoadedRegs.push_back(VirtReg); |
| 192 | ++NumLoads; |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 193 | DOUT << '\t' << *prior(MII); |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 194 | } |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 195 | |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 196 | if (MO.isDef()) { |
Chris Lattner | bf9716b | 2005-09-30 01:29:00 +0000 | [diff] [blame] | 197 | MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 198 | ++NumStores; |
| 199 | } |
Chris Lattner | 0fc27cc | 2004-09-30 02:59:33 +0000 | [diff] [blame] | 200 | } |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 201 | PhysRegsUsed[PhysReg] = true; |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 202 | MI.getOperand(i).setReg(PhysReg); |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 203 | } else { |
| 204 | PhysRegsUsed[MO.getReg()] = true; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 205 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 206 | } |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 207 | |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 208 | DOUT << '\t' << MI; |
Chris Lattner | 4ea1b82 | 2004-09-30 02:33:48 +0000 | [diff] [blame] | 209 | LoadedRegs.clear(); |
Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 210 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 211 | } |
| 212 | return true; |
| 213 | } |
| 214 | |
| 215 | //===----------------------------------------------------------------------===// |
| 216 | // Local Spiller Implementation |
| 217 | //===----------------------------------------------------------------------===// |
| 218 | |
| 219 | namespace { |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 220 | /// LocalSpiller - This spiller does a simple pass over the machine basic |
| 221 | /// block to attempt to keep spills in registers as much as possible for |
| 222 | /// blocks that have low register pressure (the vreg may be spilled due to |
| 223 | /// register pressure in other blocks). |
Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 224 | class VISIBILITY_HIDDEN LocalSpiller : public Spiller { |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 225 | const MRegisterInfo *MRI; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 226 | const TargetInstrInfo *TII; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 227 | public: |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 228 | bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 229 | MRI = MF.getTarget().getRegisterInfo(); |
| 230 | TII = MF.getTarget().getInstrInfo(); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 231 | DOUT << "\n**** Local spiller rewriting function '" |
| 232 | << MF.getFunction()->getName() << "':\n"; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 233 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 234 | for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); |
| 235 | MBB != E; ++MBB) |
| 236 | RewriteMBB(*MBB, VRM); |
| 237 | return true; |
| 238 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 239 | private: |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 240 | void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM); |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 241 | void ClobberPhysReg(unsigned PR, std::map<int, unsigned> &SpillSlots, |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 242 | std::multimap<unsigned, int> &PhysRegs); |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 243 | void ClobberPhysRegOnly(unsigned PR, std::map<int, unsigned> &SpillSlots, |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 244 | std::multimap<unsigned, int> &PhysRegs); |
| 245 | void ModifyStackSlot(int Slot, std::map<int, unsigned> &SpillSlots, |
| 246 | std::multimap<unsigned, int> &PhysRegs); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 247 | }; |
| 248 | } |
| 249 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 250 | /// AvailableSpills - As the local spiller is scanning and rewriting an MBB from |
| 251 | /// top down, keep track of which spills slots are available in each register. |
Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 252 | /// |
| 253 | /// Note that not all physregs are created equal here. In particular, some |
| 254 | /// physregs are reloads that we are allowed to clobber or ignore at any time. |
| 255 | /// Other physregs are values that the register allocated program is using that |
| 256 | /// we cannot CHANGE, but we can read if we like. We keep track of this on a |
| 257 | /// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable |
| 258 | /// entries. The predicate 'canClobberPhysReg()' checks this bit and |
| 259 | /// addAvailable sets it if. |
Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 260 | namespace { |
| 261 | class VISIBILITY_HIDDEN AvailableSpills { |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 262 | const MRegisterInfo *MRI; |
| 263 | const TargetInstrInfo *TII; |
| 264 | |
| 265 | // SpillSlotsAvailable - This map keeps track of all of the spilled virtual |
| 266 | // register values that are still available, due to being loaded or stored to, |
| 267 | // but not invalidated yet. |
| 268 | std::map<int, unsigned> SpillSlotsAvailable; |
| 269 | |
| 270 | // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating |
| 271 | // which stack slot values are currently held by a physreg. This is used to |
| 272 | // invalidate entries in SpillSlotsAvailable when a physreg is modified. |
| 273 | std::multimap<unsigned, int> PhysRegsAvailable; |
| 274 | |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 275 | void disallowClobberPhysRegOnly(unsigned PhysReg); |
| 276 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 277 | void ClobberPhysRegOnly(unsigned PhysReg); |
| 278 | public: |
| 279 | AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii) |
| 280 | : MRI(mri), TII(tii) { |
| 281 | } |
| 282 | |
| 283 | /// getSpillSlotPhysReg - If the specified stack slot is available in a |
| 284 | /// physical register, return that PhysReg, otherwise return 0. |
| 285 | unsigned getSpillSlotPhysReg(int Slot) const { |
| 286 | std::map<int, unsigned>::const_iterator I = SpillSlotsAvailable.find(Slot); |
| 287 | if (I != SpillSlotsAvailable.end()) |
Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 288 | return I->second >> 1; // Remove the CanClobber bit. |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 289 | return 0; |
| 290 | } |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 291 | |
| 292 | const MRegisterInfo *getRegInfo() const { return MRI; } |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 293 | |
| 294 | /// addAvailable - Mark that the specified stack slot is available in the |
Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 295 | /// specified physreg. If CanClobber is true, the physreg can be modified at |
| 296 | /// any time without changing the semantics of the program. |
| 297 | void addAvailable(int Slot, unsigned Reg, bool CanClobber = true) { |
Chris Lattner | 8666249 | 2006-02-03 23:50:46 +0000 | [diff] [blame] | 298 | // If this stack slot is thought to be available in some other physreg, |
| 299 | // remove its record. |
| 300 | ModifyStackSlot(Slot); |
| 301 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 302 | PhysRegsAvailable.insert(std::make_pair(Reg, Slot)); |
Jeff Cohen | 003cecb | 2006-02-04 03:27:39 +0000 | [diff] [blame] | 303 | SpillSlotsAvailable[Slot] = (Reg << 1) | (unsigned)CanClobber; |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 304 | |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 305 | DOUT << "Remembering SS#" << Slot << " in physreg " |
| 306 | << MRI->getName(Reg) << "\n"; |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 307 | } |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 308 | |
Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 309 | /// canClobberPhysReg - Return true if the spiller is allowed to change the |
| 310 | /// value of the specified stackslot register if it desires. The specified |
| 311 | /// stack slot must be available in a physreg for this query to make sense. |
| 312 | bool canClobberPhysReg(int Slot) const { |
| 313 | assert(SpillSlotsAvailable.count(Slot) && "Slot not available!"); |
| 314 | return SpillSlotsAvailable.find(Slot)->second & 1; |
| 315 | } |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 316 | |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 317 | /// disallowClobberPhysReg - Unset the CanClobber bit of the specified |
| 318 | /// stackslot register. The register is still available but is no longer |
| 319 | /// allowed to be modifed. |
| 320 | void disallowClobberPhysReg(unsigned PhysReg); |
| 321 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 322 | /// ClobberPhysReg - This is called when the specified physreg changes |
| 323 | /// value. We use this to invalidate any info about stuff we thing lives in |
| 324 | /// it and any of its aliases. |
| 325 | void ClobberPhysReg(unsigned PhysReg); |
| 326 | |
| 327 | /// ModifyStackSlot - This method is called when the value in a stack slot |
| 328 | /// changes. This removes information about which register the previous value |
| 329 | /// for this slot lives in (as the previous value is dead now). |
| 330 | void ModifyStackSlot(int Slot); |
| 331 | }; |
Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 332 | } |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 333 | |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 334 | /// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified |
| 335 | /// stackslot register. The register is still available but is no longer |
| 336 | /// allowed to be modifed. |
| 337 | void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) { |
| 338 | std::multimap<unsigned, int>::iterator I = |
| 339 | PhysRegsAvailable.lower_bound(PhysReg); |
| 340 | while (I != PhysRegsAvailable.end() && I->first == PhysReg) { |
| 341 | int Slot = I->second; |
| 342 | I++; |
| 343 | assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg && |
| 344 | "Bidirectional map mismatch!"); |
| 345 | SpillSlotsAvailable[Slot] &= ~1; |
| 346 | DOUT << "PhysReg " << MRI->getName(PhysReg) |
| 347 | << " copied, it is available for use but can no longer be modified\n"; |
| 348 | } |
| 349 | } |
| 350 | |
| 351 | /// disallowClobberPhysReg - Unset the CanClobber bit of the specified |
| 352 | /// stackslot register and its aliases. The register and its aliases may |
| 353 | /// still available but is no longer allowed to be modifed. |
| 354 | void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) { |
| 355 | for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) |
| 356 | disallowClobberPhysRegOnly(*AS); |
| 357 | disallowClobberPhysRegOnly(PhysReg); |
| 358 | } |
| 359 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 360 | /// ClobberPhysRegOnly - This is called when the specified physreg changes |
| 361 | /// value. We use this to invalidate any info about stuff we thing lives in it. |
| 362 | void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) { |
| 363 | std::multimap<unsigned, int>::iterator I = |
| 364 | PhysRegsAvailable.lower_bound(PhysReg); |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 365 | while (I != PhysRegsAvailable.end() && I->first == PhysReg) { |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 366 | int Slot = I->second; |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 367 | PhysRegsAvailable.erase(I++); |
Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 368 | assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg && |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 369 | "Bidirectional map mismatch!"); |
| 370 | SpillSlotsAvailable.erase(Slot); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 371 | DOUT << "PhysReg " << MRI->getName(PhysReg) |
| 372 | << " clobbered, invalidating SS#" << Slot << "\n"; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 373 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 374 | } |
| 375 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 376 | /// ClobberPhysReg - This is called when the specified physreg changes |
| 377 | /// value. We use this to invalidate any info about stuff we thing lives in |
| 378 | /// it and any of its aliases. |
| 379 | void AvailableSpills::ClobberPhysReg(unsigned PhysReg) { |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 380 | for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 381 | ClobberPhysRegOnly(*AS); |
| 382 | ClobberPhysRegOnly(PhysReg); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 383 | } |
| 384 | |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 385 | /// ModifyStackSlot - This method is called when the value in a stack slot |
| 386 | /// changes. This removes information about which register the previous value |
| 387 | /// for this slot lives in (as the previous value is dead now). |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 388 | void AvailableSpills::ModifyStackSlot(int Slot) { |
| 389 | std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(Slot); |
| 390 | if (It == SpillSlotsAvailable.end()) return; |
Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 391 | unsigned Reg = It->second >> 1; |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 392 | SpillSlotsAvailable.erase(It); |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 393 | |
| 394 | // This register may hold the value of multiple stack slots, only remove this |
| 395 | // stack slot from the set of values the register contains. |
| 396 | std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg); |
| 397 | for (; ; ++I) { |
| 398 | assert(I != PhysRegsAvailable.end() && I->first == Reg && |
| 399 | "Map inverse broken!"); |
| 400 | if (I->second == Slot) break; |
| 401 | } |
| 402 | PhysRegsAvailable.erase(I); |
| 403 | } |
| 404 | |
| 405 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 406 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 407 | // ReusedOp - For each reused operand, we keep track of a bit of information, in |
| 408 | // case we need to rollback upon processing a new operand. See comments below. |
| 409 | namespace { |
| 410 | struct ReusedOp { |
| 411 | // The MachineInstr operand that reused an available value. |
| 412 | unsigned Operand; |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 413 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 414 | // StackSlot - The spill slot of the value being reused. |
| 415 | unsigned StackSlot; |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 416 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 417 | // PhysRegReused - The physical register the value was available in. |
| 418 | unsigned PhysRegReused; |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 419 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 420 | // AssignedPhysReg - The physreg that was assigned for use by the reload. |
| 421 | unsigned AssignedPhysReg; |
Chris Lattner | 8a61a75 | 2005-10-06 17:19:06 +0000 | [diff] [blame] | 422 | |
| 423 | // VirtReg - The virtual register itself. |
| 424 | unsigned VirtReg; |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 425 | |
Chris Lattner | 8a61a75 | 2005-10-06 17:19:06 +0000 | [diff] [blame] | 426 | ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr, |
| 427 | unsigned vreg) |
| 428 | : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr), |
| 429 | VirtReg(vreg) {} |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 430 | }; |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 431 | |
| 432 | /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that |
| 433 | /// is reused instead of reloaded. |
Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 434 | class VISIBILITY_HIDDEN ReuseInfo { |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 435 | MachineInstr &MI; |
| 436 | std::vector<ReusedOp> Reuses; |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 437 | bool *PhysRegsClobbered; |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 438 | public: |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 439 | ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) { |
| 440 | PhysRegsClobbered = new bool[mri->getNumRegs()]; |
| 441 | std::fill(PhysRegsClobbered, PhysRegsClobbered+mri->getNumRegs(), false); |
| 442 | } |
| 443 | ~ReuseInfo() { |
| 444 | delete[] PhysRegsClobbered; |
| 445 | } |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 446 | |
| 447 | bool hasReuses() const { |
| 448 | return !Reuses.empty(); |
| 449 | } |
| 450 | |
| 451 | /// addReuse - If we choose to reuse a virtual register that is already |
| 452 | /// available instead of reloading it, remember that we did so. |
| 453 | void addReuse(unsigned OpNo, unsigned StackSlot, |
| 454 | unsigned PhysRegReused, unsigned AssignedPhysReg, |
| 455 | unsigned VirtReg) { |
| 456 | // If the reload is to the assigned register anyway, no undo will be |
| 457 | // required. |
| 458 | if (PhysRegReused == AssignedPhysReg) return; |
| 459 | |
| 460 | // Otherwise, remember this. |
| 461 | Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused, |
| 462 | AssignedPhysReg, VirtReg)); |
| 463 | } |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 464 | |
| 465 | void markClobbered(unsigned PhysReg) { |
| 466 | PhysRegsClobbered[PhysReg] = true; |
| 467 | } |
| 468 | |
| 469 | bool isClobbered(unsigned PhysReg) const { |
| 470 | return PhysRegsClobbered[PhysReg]; |
| 471 | } |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 472 | |
| 473 | /// GetRegForReload - We are about to emit a reload into PhysReg. If there |
| 474 | /// is some other operand that is using the specified register, either pick |
| 475 | /// a new register to use, or evict the previous reload and use this reg. |
| 476 | unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, |
| 477 | AvailableSpills &Spills, |
| 478 | std::map<int, MachineInstr*> &MaybeDeadStores) { |
| 479 | if (Reuses.empty()) return PhysReg; // This is most often empty. |
| 480 | |
| 481 | for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) { |
| 482 | ReusedOp &Op = Reuses[ro]; |
| 483 | // If we find some other reuse that was supposed to use this register |
| 484 | // exactly for its reload, we can change this reload to use ITS reload |
| 485 | // register. |
| 486 | if (Op.PhysRegReused == PhysReg) { |
| 487 | // Yup, use the reload register that we didn't use before. |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 488 | unsigned NewReg = Op.AssignedPhysReg; |
Chris Lattner | 47cb717 | 2006-02-25 02:03:40 +0000 | [diff] [blame] | 489 | return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores); |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 490 | } else { |
| 491 | // Otherwise, we might also have a problem if a previously reused |
| 492 | // value aliases the new register. If so, codegen the previous reload |
| 493 | // and use this one. |
| 494 | unsigned PRRU = Op.PhysRegReused; |
| 495 | const MRegisterInfo *MRI = Spills.getRegInfo(); |
| 496 | if (MRI->areAliases(PRRU, PhysReg)) { |
| 497 | // Okay, we found out that an alias of a reused register |
| 498 | // was used. This isn't good because it means we have |
| 499 | // to undo a previous reuse. |
| 500 | MachineBasicBlock *MBB = MI->getParent(); |
| 501 | const TargetRegisterClass *AliasRC = |
Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 502 | MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg); |
| 503 | |
| 504 | // Copy Op out of the vector and remove it, we're going to insert an |
| 505 | // explicit load for it. |
| 506 | ReusedOp NewOp = Op; |
| 507 | Reuses.erase(Reuses.begin()+ro); |
| 508 | |
| 509 | // Ok, we're going to try to reload the assigned physreg into the |
| 510 | // slot that we were supposed to in the first place. However, that |
| 511 | // register could hold a reuse. Check to see if it conflicts or |
| 512 | // would prefer us to use a different register. |
| 513 | unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg, |
| 514 | MI, Spills, MaybeDeadStores); |
| 515 | |
| 516 | MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg, |
| 517 | NewOp.StackSlot, AliasRC); |
| 518 | Spills.ClobberPhysReg(NewPhysReg); |
| 519 | Spills.ClobberPhysReg(NewOp.PhysRegReused); |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 520 | |
| 521 | // Any stores to this stack slot are not dead anymore. |
Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 522 | MaybeDeadStores.erase(NewOp.StackSlot); |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 523 | |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 524 | MI->getOperand(NewOp.Operand).setReg(NewPhysReg); |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 525 | |
Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 526 | Spills.addAvailable(NewOp.StackSlot, NewPhysReg); |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 527 | ++NumLoads; |
| 528 | DEBUG(MachineBasicBlock::iterator MII = MI; |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 529 | DOUT << '\t' << *prior(MII)); |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 530 | |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 531 | DOUT << "Reuse undone!\n"; |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 532 | --NumReused; |
Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 533 | |
| 534 | // Finally, PhysReg is now available, go ahead and use it. |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 535 | return PhysReg; |
| 536 | } |
| 537 | } |
| 538 | } |
| 539 | return PhysReg; |
| 540 | } |
| 541 | }; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 542 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 543 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 544 | |
| 545 | /// rewriteMBB - Keep track of which spills are available even after the |
| 546 | /// register allocator is done with them. If possible, avoid reloading vregs. |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 547 | void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 548 | |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 549 | DOUT << MBB.getBasicBlock()->getName() << ":\n"; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 550 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 551 | // Spills - Keep track of which spilled values are available in physregs so |
| 552 | // that we can choose to reuse the physregs instead of emitting reloads. |
| 553 | AvailableSpills Spills(MRI, TII); |
| 554 | |
Chris Lattner | 52b25db | 2004-10-01 19:47:12 +0000 | [diff] [blame] | 555 | // MaybeDeadStores - When we need to write a value back into a stack slot, |
| 556 | // keep track of the inserted store. If the stack slot value is never read |
| 557 | // (because the value was used from some available register, for example), and |
| 558 | // subsequently stored to, the original store is dead. This map keeps track |
| 559 | // of inserted stores that are not used. If we see a subsequent store to the |
| 560 | // same stack slot, the original store is deleted. |
| 561 | std::map<int, MachineInstr*> MaybeDeadStores; |
| 562 | |
Chris Lattner | b0f31bf | 2005-01-23 22:45:13 +0000 | [diff] [blame] | 563 | bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs(); |
| 564 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 565 | for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); |
| 566 | MII != E; ) { |
| 567 | MachineInstr &MI = *MII; |
| 568 | MachineBasicBlock::iterator NextMII = MII; ++NextMII; |
| 569 | |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 570 | /// ReusedOperands - Keep track of operand reuse in case we need to undo |
| 571 | /// reuse. |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 572 | ReuseInfo ReusedOperands(MI, MRI); |
| 573 | |
| 574 | // Loop over all of the implicit defs, clearing them from our available |
| 575 | // sets. |
Evan Cheng | 86facc2 | 2006-12-15 06:41:01 +0000 | [diff] [blame] | 576 | const TargetInstrDescriptor *TID = MI.getInstrDescriptor(); |
| 577 | const unsigned *ImpDef = TID->ImplicitDefs; |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 578 | if (ImpDef) { |
| 579 | for ( ; *ImpDef; ++ImpDef) { |
| 580 | PhysRegsUsed[*ImpDef] = true; |
| 581 | ReusedOperands.markClobbered(*ImpDef); |
| 582 | Spills.ClobberPhysReg(*ImpDef); |
| 583 | } |
| 584 | } |
| 585 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 586 | // Process all of the spilled uses and all non spilled reg references. |
| 587 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
| 588 | MachineOperand &MO = MI.getOperand(i); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 589 | if (!MO.isRegister() || MO.getReg() == 0) |
| 590 | continue; // Ignore non-register operands. |
| 591 | |
| 592 | if (MRegisterInfo::isPhysicalRegister(MO.getReg())) { |
| 593 | // Ignore physregs for spilling, but remember that it is used by this |
| 594 | // function. |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 595 | PhysRegsUsed[MO.getReg()] = true; |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 596 | ReusedOperands.markClobbered(MO.getReg()); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 597 | continue; |
| 598 | } |
| 599 | |
| 600 | assert(MRegisterInfo::isVirtualRegister(MO.getReg()) && |
| 601 | "Not a virtual or a physical register?"); |
| 602 | |
| 603 | unsigned VirtReg = MO.getReg(); |
| 604 | if (!VRM.hasStackSlot(VirtReg)) { |
| 605 | // This virtual register was assigned a physreg! |
| 606 | unsigned Phys = VRM.getPhys(VirtReg); |
| 607 | PhysRegsUsed[Phys] = true; |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 608 | if (MO.isDef()) |
| 609 | ReusedOperands.markClobbered(Phys); |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 610 | MI.getOperand(i).setReg(Phys); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 611 | continue; |
| 612 | } |
| 613 | |
| 614 | // This virtual register is now known to be a spilled value. |
| 615 | if (!MO.isUse()) |
| 616 | continue; // Handle defs in the loop below (handle use&def here though) |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 617 | |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 618 | int StackSlot = VRM.getStackSlot(VirtReg); |
| 619 | unsigned PhysReg; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 620 | |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 621 | // Check to see if this stack slot is available. |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 622 | if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot))) { |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 623 | |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 624 | // This spilled operand might be part of a two-address operand. If this |
| 625 | // is the case, then changing it will necessarily require changing the |
| 626 | // def part of the instruction as well. However, in some cases, we |
| 627 | // aren't allowed to modify the reused register. If none of these cases |
| 628 | // apply, reuse it. |
| 629 | bool CanReuse = true; |
Evan Cheng | 86facc2 | 2006-12-15 06:41:01 +0000 | [diff] [blame] | 630 | int ti = TID->getOperandConstraint(i, TOI::TIED_TO); |
Evan Cheng | 360c2dd | 2006-11-01 23:06:55 +0000 | [diff] [blame] | 631 | if (ti != -1 && |
| 632 | MI.getOperand(ti).isReg() && |
| 633 | MI.getOperand(ti).getReg() == VirtReg) { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 634 | // Okay, we have a two address operand. We can reuse this physreg as |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 635 | // long as we are allowed to clobber the value and there is an earlier |
| 636 | // def that has already clobbered the physreg. |
| 637 | CanReuse = Spills.canClobberPhysReg(StackSlot) && |
| 638 | !ReusedOperands.isClobbered(PhysReg); |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 639 | } |
| 640 | |
| 641 | if (CanReuse) { |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 642 | // If this stack slot value is already available, reuse it! |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 643 | DOUT << "Reusing SS#" << StackSlot << " from physreg " |
| 644 | << MRI->getName(PhysReg) << " for vreg" |
| 645 | << VirtReg <<" instead of reloading into physreg " |
| 646 | << MRI->getName(VRM.getPhys(VirtReg)) << "\n"; |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 647 | MI.getOperand(i).setReg(PhysReg); |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 648 | |
| 649 | // The only technical detail we have is that we don't know that |
| 650 | // PhysReg won't be clobbered by a reloaded stack slot that occurs |
| 651 | // later in the instruction. In particular, consider 'op V1, V2'. |
| 652 | // If V1 is available in physreg R0, we would choose to reuse it |
| 653 | // here, instead of reloading it into the register the allocator |
| 654 | // indicated (say R1). However, V2 might have to be reloaded |
| 655 | // later, and it might indicate that it needs to live in R0. When |
| 656 | // this occurs, we need to have information available that |
| 657 | // indicates it is safe to use R1 for the reload instead of R0. |
| 658 | // |
| 659 | // To further complicate matters, we might conflict with an alias, |
| 660 | // or R0 and R1 might not be compatible with each other. In this |
| 661 | // case, we actually insert a reload for V1 in R1, ensuring that |
| 662 | // we can get at R0 or its alias. |
| 663 | ReusedOperands.addReuse(i, StackSlot, PhysReg, |
| 664 | VRM.getPhys(VirtReg), VirtReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 665 | if (ti != -1) |
| 666 | // Only mark it clobbered if this is a use&def operand. |
| 667 | ReusedOperands.markClobbered(PhysReg); |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 668 | ++NumReused; |
| 669 | continue; |
| 670 | } |
| 671 | |
| 672 | // Otherwise we have a situation where we have a two-address instruction |
| 673 | // whose mod/ref operand needs to be reloaded. This reload is already |
| 674 | // available in some register "PhysReg", but if we used PhysReg as the |
| 675 | // operand to our 2-addr instruction, the instruction would modify |
| 676 | // PhysReg. This isn't cool if something later uses PhysReg and expects |
| 677 | // to get its initial value. |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 678 | // |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 679 | // To avoid this problem, and to avoid doing a load right after a store, |
| 680 | // we emit a copy from PhysReg into the designated register for this |
| 681 | // operand. |
| 682 | unsigned DesignatedReg = VRM.getPhys(VirtReg); |
| 683 | assert(DesignatedReg && "Must map virtreg to physreg!"); |
| 684 | |
| 685 | // Note that, if we reused a register for a previous operand, the |
| 686 | // register we want to reload into might not actually be |
| 687 | // available. If this occurs, use the register indicated by the |
| 688 | // reuser. |
| 689 | if (ReusedOperands.hasReuses()) |
| 690 | DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI, |
| 691 | Spills, MaybeDeadStores); |
| 692 | |
Chris Lattner | ba1fc3d | 2006-04-28 04:43:18 +0000 | [diff] [blame] | 693 | // If the mapped designated register is actually the physreg we have |
| 694 | // incoming, we don't need to inserted a dead copy. |
| 695 | if (DesignatedReg == PhysReg) { |
| 696 | // If this stack slot value is already available, reuse it! |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 697 | DOUT << "Reusing SS#" << StackSlot << " from physreg " |
| 698 | << MRI->getName(PhysReg) << " for vreg" |
| 699 | << VirtReg |
| 700 | << " instead of reloading into same physreg.\n"; |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 701 | MI.getOperand(i).setReg(PhysReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 702 | ReusedOperands.markClobbered(PhysReg); |
Chris Lattner | ba1fc3d | 2006-04-28 04:43:18 +0000 | [diff] [blame] | 703 | ++NumReused; |
| 704 | continue; |
| 705 | } |
| 706 | |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 707 | const TargetRegisterClass* RC = |
| 708 | MBB.getParent()->getSSARegMap()->getRegClass(VirtReg); |
| 709 | |
| 710 | PhysRegsUsed[DesignatedReg] = true; |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 711 | ReusedOperands.markClobbered(DesignatedReg); |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 712 | MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC); |
| 713 | |
| 714 | // This invalidates DesignatedReg. |
| 715 | Spills.ClobberPhysReg(DesignatedReg); |
| 716 | |
| 717 | Spills.addAvailable(StackSlot, DesignatedReg); |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 718 | MI.getOperand(i).setReg(DesignatedReg); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 719 | DOUT << '\t' << *prior(MII); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 720 | ++NumReused; |
| 721 | continue; |
| 722 | } |
| 723 | |
| 724 | // Otherwise, reload it and remember that we have it. |
| 725 | PhysReg = VRM.getPhys(VirtReg); |
Chris Lattner | 172c362 | 2006-01-04 06:47:48 +0000 | [diff] [blame] | 726 | assert(PhysReg && "Must map virtreg to physreg!"); |
Chris Lattner | bf9716b | 2005-09-30 01:29:00 +0000 | [diff] [blame] | 727 | const TargetRegisterClass* RC = |
| 728 | MBB.getParent()->getSSARegMap()->getRegClass(VirtReg); |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 729 | |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 730 | // Note that, if we reused a register for a previous operand, the |
| 731 | // register we want to reload into might not actually be |
| 732 | // available. If this occurs, use the register indicated by the |
| 733 | // reuser. |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 734 | if (ReusedOperands.hasReuses()) |
| 735 | PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, |
| 736 | Spills, MaybeDeadStores); |
| 737 | |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 738 | PhysRegsUsed[PhysReg] = true; |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 739 | ReusedOperands.markClobbered(PhysReg); |
Chris Lattner | bf9716b | 2005-09-30 01:29:00 +0000 | [diff] [blame] | 740 | MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 741 | // This invalidates PhysReg. |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 742 | Spills.ClobberPhysReg(PhysReg); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 743 | |
| 744 | // Any stores to this stack slot are not dead anymore. |
| 745 | MaybeDeadStores.erase(StackSlot); |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 746 | Spills.addAvailable(StackSlot, PhysReg); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 747 | ++NumLoads; |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 748 | MI.getOperand(i).setReg(PhysReg); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 749 | DOUT << '\t' << *prior(MII); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 750 | } |
| 751 | |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 752 | DOUT << '\t' << MI; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 753 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 754 | // If we have folded references to memory operands, make sure we clear all |
| 755 | // physical registers that may contain the value of the spilled virtual |
| 756 | // register |
Chris Lattner | 8f1d640 | 2005-01-14 15:54:24 +0000 | [diff] [blame] | 757 | VirtRegMap::MI2VirtMapTy::const_iterator I, End; |
| 758 | for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) { |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 759 | DOUT << "Folded vreg: " << I->second.first << " MR: " |
| 760 | << I->second.second; |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 761 | unsigned VirtReg = I->second.first; |
| 762 | VirtRegMap::ModRef MR = I->second.second; |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 763 | if (!VRM.hasStackSlot(VirtReg)) { |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 764 | DOUT << ": No stack slot!\n"; |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 765 | continue; |
| 766 | } |
| 767 | int SS = VRM.getStackSlot(VirtReg); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 768 | DOUT << " - StackSlot: " << SS << "\n"; |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 769 | |
| 770 | // If this folded instruction is just a use, check to see if it's a |
| 771 | // straight load from the virt reg slot. |
| 772 | if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) { |
| 773 | int FrameIdx; |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 774 | if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) { |
Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 775 | if (FrameIdx == SS) { |
| 776 | // If this spill slot is available, turn it into a copy (or nothing) |
| 777 | // instead of leaving it as a load! |
| 778 | if (unsigned InReg = Spills.getSpillSlotPhysReg(SS)) { |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 779 | DOUT << "Promoted Load To Copy: " << MI; |
Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 780 | MachineFunction &MF = *MBB.getParent(); |
| 781 | if (DestReg != InReg) { |
| 782 | MRI->copyRegToReg(MBB, &MI, DestReg, InReg, |
| 783 | MF.getSSARegMap()->getRegClass(VirtReg)); |
| 784 | // Revisit the copy so we make sure to notice the effects of the |
| 785 | // operation on the destreg (either needing to RA it if it's |
| 786 | // virtual or needing to clobber any values if it's physical). |
| 787 | NextMII = &MI; |
| 788 | --NextMII; // backtrack to the copy. |
| 789 | } |
| 790 | VRM.RemoveFromFoldedVirtMap(&MI); |
| 791 | MBB.erase(&MI); |
| 792 | goto ProcessNextInst; |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 793 | } |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 794 | } |
| 795 | } |
| 796 | } |
| 797 | |
| 798 | // If this reference is not a use, any previous store is now dead. |
| 799 | // Otherwise, the store to this stack slot is not dead anymore. |
| 800 | std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS); |
| 801 | if (MDSI != MaybeDeadStores.end()) { |
| 802 | if (MR & VirtRegMap::isRef) // Previous store is not dead. |
| 803 | MaybeDeadStores.erase(MDSI); |
| 804 | else { |
| 805 | // If we get here, the store is dead, nuke it now. |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 806 | assert(VirtRegMap::isMod && "Can't be modref!"); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 807 | DOUT << "Removed dead store:\t" << *MDSI->second; |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 808 | MBB.erase(MDSI->second); |
Chris Lattner | 229924a | 2006-05-01 22:03:24 +0000 | [diff] [blame] | 809 | VRM.RemoveFromFoldedVirtMap(MDSI->second); |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 810 | MaybeDeadStores.erase(MDSI); |
| 811 | ++NumDSE; |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 812 | } |
| 813 | } |
| 814 | |
| 815 | // If the spill slot value is available, and this is a new definition of |
| 816 | // the value, the value is not available anymore. |
| 817 | if (MR & VirtRegMap::isMod) { |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 818 | // Notice that the value in this stack slot has been modified. |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 819 | Spills.ModifyStackSlot(SS); |
Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 820 | |
| 821 | // If this is *just* a mod of the value, check to see if this is just a |
| 822 | // store to the spill slot (i.e. the spill got merged into the copy). If |
| 823 | // so, realize that the vreg is available now, and add the store to the |
| 824 | // MaybeDeadStore info. |
| 825 | int StackSlot; |
| 826 | if (!(MR & VirtRegMap::isRef)) { |
| 827 | if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) { |
| 828 | assert(MRegisterInfo::isPhysicalRegister(SrcReg) && |
| 829 | "Src hasn't been allocated yet?"); |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 830 | // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark |
Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 831 | // this as a potentially dead store in case there is a subsequent |
| 832 | // store into the stack slot without a read from it. |
| 833 | MaybeDeadStores[StackSlot] = &MI; |
| 834 | |
Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 835 | // If the stack slot value was previously available in some other |
| 836 | // register, change it now. Otherwise, make the register available, |
| 837 | // in PhysReg. |
Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 838 | Spills.addAvailable(StackSlot, SrcReg, false /*don't clobber*/); |
Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 839 | } |
| 840 | } |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 841 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 842 | } |
| 843 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 844 | // Process all of the spilled defs. |
| 845 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
| 846 | MachineOperand &MO = MI.getOperand(i); |
| 847 | if (MO.isRegister() && MO.getReg() && MO.isDef()) { |
| 848 | unsigned VirtReg = MO.getReg(); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 849 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 850 | if (!MRegisterInfo::isVirtualRegister(VirtReg)) { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 851 | // Check to see if this is a noop copy. If so, eliminate the |
| 852 | // instruction before considering the dest reg to be changed. |
| 853 | unsigned Src, Dst; |
| 854 | if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { |
| 855 | ++NumDCE; |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 856 | DOUT << "Removing now-noop copy: " << MI; |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 857 | MBB.erase(&MI); |
| 858 | VRM.RemoveFromFoldedVirtMap(&MI); |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 859 | Spills.disallowClobberPhysReg(VirtReg); |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 860 | goto ProcessNextInst; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 861 | } |
Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 862 | |
| 863 | // If it's not a no-op copy, it clobbers the value in the destreg. |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 864 | Spills.ClobberPhysReg(VirtReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 865 | ReusedOperands.markClobbered(VirtReg); |
Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 866 | |
| 867 | // Check to see if this instruction is a load from a stack slot into |
| 868 | // a register. If so, this provides the stack slot value in the reg. |
| 869 | int FrameIdx; |
| 870 | if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) { |
| 871 | assert(DestReg == VirtReg && "Unknown load situation!"); |
| 872 | |
| 873 | // Otherwise, if it wasn't available, remember that it is now! |
| 874 | Spills.addAvailable(FrameIdx, DestReg); |
| 875 | goto ProcessNextInst; |
| 876 | } |
| 877 | |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 878 | continue; |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 879 | } |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 880 | |
Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 881 | // The only vregs left are stack slot definitions. |
| 882 | int StackSlot = VRM.getStackSlot(VirtReg); |
| 883 | const TargetRegisterClass *RC = |
| 884 | MBB.getParent()->getSSARegMap()->getRegClass(VirtReg); |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 885 | |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 886 | // If this def is part of a two-address operand, make sure to execute |
| 887 | // the store from the correct physical register. |
| 888 | unsigned PhysReg; |
Evan Cheng | cc22a7a | 2006-12-08 18:45:48 +0000 | [diff] [blame] | 889 | int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i); |
Evan Cheng | 360c2dd | 2006-11-01 23:06:55 +0000 | [diff] [blame] | 890 | if (TiedOp != -1) |
| 891 | PhysReg = MI.getOperand(TiedOp).getReg(); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 892 | else { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 893 | PhysReg = VRM.getPhys(VirtReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 894 | if (ReusedOperands.isClobbered(PhysReg)) { |
| 895 | // Another def has taken the assigned physreg. It must have been a |
| 896 | // use&def which got it due to reuse. Undo the reuse! |
| 897 | PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, |
| 898 | Spills, MaybeDeadStores); |
| 899 | } |
| 900 | } |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 901 | |
Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 902 | PhysRegsUsed[PhysReg] = true; |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 903 | ReusedOperands.markClobbered(PhysReg); |
Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 904 | MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 905 | DOUT << "Store:\t" << *next(MII); |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 906 | MI.getOperand(i).setReg(PhysReg); |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 907 | |
Chris Lattner | 109afed | 2006-02-03 03:16:14 +0000 | [diff] [blame] | 908 | // Check to see if this is a noop copy. If so, eliminate the |
| 909 | // instruction before considering the dest reg to be changed. |
| 910 | { |
| 911 | unsigned Src, Dst; |
| 912 | if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { |
| 913 | ++NumDCE; |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 914 | DOUT << "Removing now-noop copy: " << MI; |
Chris Lattner | 109afed | 2006-02-03 03:16:14 +0000 | [diff] [blame] | 915 | MBB.erase(&MI); |
Chris Lattner | 229924a | 2006-05-01 22:03:24 +0000 | [diff] [blame] | 916 | VRM.RemoveFromFoldedVirtMap(&MI); |
Chris Lattner | 109afed | 2006-02-03 03:16:14 +0000 | [diff] [blame] | 917 | goto ProcessNextInst; |
| 918 | } |
| 919 | } |
| 920 | |
Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 921 | // If there is a dead store to this stack slot, nuke it now. |
| 922 | MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; |
| 923 | if (LastStore) { |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 924 | DOUT << "Removed dead store:\t" << *LastStore; |
Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 925 | ++NumDSE; |
| 926 | MBB.erase(LastStore); |
Chris Lattner | 229924a | 2006-05-01 22:03:24 +0000 | [diff] [blame] | 927 | VRM.RemoveFromFoldedVirtMap(LastStore); |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 928 | } |
Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 929 | LastStore = next(MII); |
| 930 | |
| 931 | // If the stack slot value was previously available in some other |
| 932 | // register, change it now. Otherwise, make the register available, |
| 933 | // in PhysReg. |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 934 | Spills.ModifyStackSlot(StackSlot); |
| 935 | Spills.ClobberPhysReg(PhysReg); |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 936 | Spills.addAvailable(StackSlot, PhysReg); |
Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 937 | ++NumStores; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 938 | } |
| 939 | } |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 940 | ProcessNextInst: |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 941 | MII = NextMII; |
| 942 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 943 | } |
| 944 | |
Chris Lattner | f7da2c7 | 2006-08-24 22:43:55 +0000 | [diff] [blame] | 945 | |
| 946 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 947 | llvm::Spiller* llvm::createSpiller() { |
| 948 | switch (SpillerOpt) { |
| 949 | default: assert(0 && "Unreachable!"); |
| 950 | case local: |
| 951 | return new LocalSpiller(); |
| 952 | case simple: |
| 953 | return new SimpleSpiller(); |
| 954 | } |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 955 | } |