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Arnold Schwaighofer373e8652007-10-12 21:30:57 +00001//===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner081ce942007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Dan Gohmanf17a25c2007-07-18 16:29:46 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 instruction set, defining the instructions, and
11// properties of the instructions which are needed for code generation, machine
12// code emission, and analysis.
13//
14//===----------------------------------------------------------------------===//
15
16//===----------------------------------------------------------------------===//
17// X86 specific DAG Nodes.
18//
19
20def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
23
24def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
25
Evan Cheng621216e2007-09-29 00:00:36 +000026def SDTX86Cmov : SDTypeProfile<1, 4,
Evan Cheng950aac02007-09-25 01:57:46 +000027 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000029
Dan Gohman99a12192009-03-04 19:44:21 +000030// Unary and binary operator instructions that set EFLAGS as a side-effect.
31def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
32 [SDTCisInt<0>]>;
33def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
34 [SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>,
36 SDTCisInt<0>]>;
Evan Cheng621216e2007-09-29 00:00:36 +000037def SDTX86BrCond : SDTypeProfile<0, 3,
Evan Cheng950aac02007-09-25 01:57:46 +000038 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000040
Evan Cheng621216e2007-09-29 00:00:36 +000041def SDTX86SetCC : SDTypeProfile<1, 2,
Evan Cheng950aac02007-09-25 01:57:46 +000042 [SDTCisVT<0, i8>,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000044
Andrew Lenharth7dfe23f2008-03-01 21:52:34 +000045def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
46 SDTCisVT<2, i8>]>;
Andrew Lenharth81580822008-03-05 01:15:49 +000047def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
Andrew Lenharth7dfe23f2008-03-01 21:52:34 +000048
Dale Johannesenf160d802008-10-02 18:53:47 +000049def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
50 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
Chris Lattnerb56cc342008-03-11 03:23:40 +000051def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000052
Sean Callanan2c8a2592009-06-23 23:25:37 +000053def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
54def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
55 SDTCisVT<1, i32>]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000056
Dan Gohman3329ffe2008-05-29 19:57:41 +000057def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000058
59def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
60
61def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
62
63def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
64
Rafael Espindolaaf759ab2009-04-17 14:35:58 +000065def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000066
Rafael Espindolabca99f72009-04-08 21:14:34 +000067def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000068
69def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
70
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +000071def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
72
Evan Cheng48679f42007-12-14 02:13:44 +000073def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
74def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000075def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
76def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
77
Evan Cheng621216e2007-09-29 00:00:36 +000078def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000079
Dan Gohman7fe9b7f2008-12-23 22:45:23 +000080def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
81
Evan Cheng621216e2007-09-29 00:00:36 +000082def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000083def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
Evan Cheng950aac02007-09-25 01:57:46 +000084 [SDNPHasChain]>;
Evan Cheng621216e2007-09-29 00:00:36 +000085def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000086
Andrew Lenharth7dfe23f2008-03-01 21:52:34 +000087def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
88 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
89 SDNPMayLoad]>;
Andrew Lenharth81580822008-03-05 01:15:49 +000090def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
91 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
92 SDNPMayLoad]>;
Dale Johannesenf160d802008-10-02 18:53:47 +000093def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
94 [SDNPHasChain, SDNPMayStore,
95 SDNPMayLoad, SDNPMemOperand]>;
96def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
97 [SDNPHasChain, SDNPMayStore,
98 SDNPMayLoad, SDNPMemOperand]>;
99def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
100 [SDNPHasChain, SDNPMayStore,
101 SDNPMayLoad, SDNPMemOperand]>;
102def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
103 [SDNPHasChain, SDNPMayStore,
104 SDNPMayLoad, SDNPMemOperand]>;
105def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
106 [SDNPHasChain, SDNPMayStore,
107 SDNPMayLoad, SDNPMemOperand]>;
108def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
109 [SDNPHasChain, SDNPMayStore,
110 SDNPMayLoad, SDNPMemOperand]>;
Dale Johannesen51c58ee2008-10-03 22:25:52 +0000111def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
112 [SDNPHasChain, SDNPMayStore,
113 SDNPMayLoad, SDNPMemOperand]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000114def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
115 [SDNPHasChain, SDNPOptInFlag]>;
116
117def X86callseq_start :
118 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
119 [SDNPHasChain, SDNPOutFlag]>;
120def X86callseq_end :
121 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +0000122 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000123
124def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
125 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
126
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000127def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
Chris Lattnerca4e0fe2008-01-10 05:12:37 +0000128 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000129def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
Chris Lattnerca4e0fe2008-01-10 05:12:37 +0000130 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
131 SDNPMayLoad]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000132
133def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000134 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000135
136def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
137def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
138
139def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
Anton Korobeynikov4fbf00b2008-05-04 21:36:32 +0000140 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Rafael Espindolabca99f72009-04-08 21:14:34 +0000141def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
142 SDT_X86SegmentBaseAddress, []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000143
144def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
145 [SDNPHasChain]>;
146
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +0000147def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
148 [SDNPHasChain, SDNPOptInFlag]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000149
Dan Gohman99a12192009-03-04 19:44:21 +0000150def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>;
151def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
152def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
153def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
154def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
155def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
Bill Wendlingae034ed2008-12-12 00:56:36 +0000156
Evan Chengc3495762009-03-30 21:36:47 +0000157def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
158
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000159//===----------------------------------------------------------------------===//
160// X86 Operand Definitions.
161//
162
Chris Lattner357a0ca2009-06-20 19:34:09 +0000163def i32imm_pcrel : Operand<i32> {
164 let PrintMethod = "print_pcrel_imm";
165}
166
Dan Gohmanfe606822009-07-30 01:56:29 +0000167// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
168// the index operand of an address, to conform to x86 encoding restrictions.
169def ptr_rc_nosp : PointerLikeRegClass<1>;
Chris Lattner357a0ca2009-06-20 19:34:09 +0000170
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000171// *mem - Operand definitions for the funky X86 addressing mode operands.
172//
Daniel Dunbar0f10cbf2009-08-10 18:41:10 +0000173def X86MemAsmOperand : AsmOperandClass {
174 let Name = "Mem";
Daniel Dunbar6e9ee792009-08-10 19:08:02 +0000175 let SuperClass = ?;
Daniel Dunbar0f10cbf2009-08-10 18:41:10 +0000176}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000177class X86MemOperand<string printMethod> : Operand<iPTR> {
178 let PrintMethod = printMethod;
Dan Gohmanfe606822009-07-30 01:56:29 +0000179 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
Daniel Dunbar0f10cbf2009-08-10 18:41:10 +0000180 let ParserMatchClass = X86MemAsmOperand;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000181}
182
183def i8mem : X86MemOperand<"printi8mem">;
184def i16mem : X86MemOperand<"printi16mem">;
185def i32mem : X86MemOperand<"printi32mem">;
186def i64mem : X86MemOperand<"printi64mem">;
187def i128mem : X86MemOperand<"printi128mem">;
David Greene6b75fca2009-06-30 19:24:59 +0000188def i256mem : X86MemOperand<"printi256mem">;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000189def f32mem : X86MemOperand<"printf32mem">;
190def f64mem : X86MemOperand<"printf64mem">;
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000191def f80mem : X86MemOperand<"printf80mem">;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000192def f128mem : X86MemOperand<"printf128mem">;
David Greene6b75fca2009-06-30 19:24:59 +0000193def f256mem : X86MemOperand<"printf256mem">;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000194
Dan Gohman744d4622009-04-13 16:09:41 +0000195// A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
196// plain GR64, so that it doesn't potentially require a REX prefix.
197def i8mem_NOREX : Operand<i64> {
198 let PrintMethod = "printi8mem";
Dan Gohmanfe606822009-07-30 01:56:29 +0000199 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
Daniel Dunbar0f10cbf2009-08-10 18:41:10 +0000200 let ParserMatchClass = X86MemAsmOperand;
Dan Gohman744d4622009-04-13 16:09:41 +0000201}
202
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000203def lea32mem : Operand<i32> {
Rafael Espindolabca99f72009-04-08 21:14:34 +0000204 let PrintMethod = "printlea32mem";
Dan Gohmanefbd3bc2009-08-05 17:40:24 +0000205 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
Daniel Dunbar0f10cbf2009-08-10 18:41:10 +0000206 let ParserMatchClass = X86MemAsmOperand;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000207}
208
209def SSECC : Operand<i8> {
210 let PrintMethod = "printSSECC";
211}
212
213def piclabel: Operand<i32> {
214 let PrintMethod = "printPICLabel";
215}
216
Daniel Dunbar0f10cbf2009-08-10 18:41:10 +0000217def ImmSExt8AsmOperand : AsmOperandClass {
218 let Name = "ImmSExt8";
219 let SuperClass = ImmAsmOperand;
220}
221
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000222// A couple of more descriptive operand definitions.
223// 16-bits but only 8 bits are significant.
Daniel Dunbar06d5cb62009-08-09 07:20:21 +0000224def i16i8imm : Operand<i16> {
Daniel Dunbar0f10cbf2009-08-10 18:41:10 +0000225 let ParserMatchClass = ImmSExt8AsmOperand;
Daniel Dunbar06d5cb62009-08-09 07:20:21 +0000226}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000227// 32-bits but only 8 bits are significant.
Daniel Dunbar06d5cb62009-08-09 07:20:21 +0000228def i32i8imm : Operand<i32> {
Daniel Dunbar0f10cbf2009-08-10 18:41:10 +0000229 let ParserMatchClass = ImmSExt8AsmOperand;
Daniel Dunbar06d5cb62009-08-09 07:20:21 +0000230}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000231
Chris Lattner357a0ca2009-06-20 19:34:09 +0000232// Branch targets have OtherVT type and print as pc-relative values.
233def brtarget : Operand<OtherVT> {
234 let PrintMethod = "print_pcrel_imm";
235}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000236
Evan Chengd11052b2009-07-21 06:00:18 +0000237def brtarget8 : Operand<OtherVT> {
238 let PrintMethod = "print_pcrel_imm";
239}
240
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000241//===----------------------------------------------------------------------===//
242// X86 Complex Pattern Definitions.
243//
244
245// Define X86 specific addressing mode.
Rafael Espindolabca99f72009-04-08 21:14:34 +0000246def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000247def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
Dan Gohman0c0d7412009-08-02 16:09:17 +0000248 [add, sub, mul, X86mul_imm, shl, or, frameindex],
249 []>;
Chris Lattnerf1940742009-06-20 20:38:48 +0000250def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
251 [tglobaltlsaddr], []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000252
253//===----------------------------------------------------------------------===//
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000254// X86 Instruction Predicate Definitions.
255def HasMMX : Predicate<"Subtarget->hasMMX()">;
256def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
257def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
258def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
259def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
Nate Begemanb2975562008-02-03 07:18:54 +0000260def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
261def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
David Greene8bf22bc2009-06-26 22:46:54 +0000262def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
263def HasAVX : Predicate<"Subtarget->hasAVX()">;
264def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
265def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
Dale Johannesene0e0fd02007-09-23 14:52:20 +0000266def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
267def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000268def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
269def In64BitMode : Predicate<"Subtarget->is64Bit()">;
Anton Korobeynikov2cbcdb72009-08-03 08:12:53 +0000270def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
271def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
Anton Korobeynikov68d4eca2009-08-06 11:23:24 +0000272def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
273def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
274def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
Anton Korobeynikov7e1178f2009-08-06 09:11:19 +0000275 "TM.getCodeModel() != CodeModel::Kernel">;
Anton Korobeynikov68d4eca2009-08-06 11:23:24 +0000276def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
277 "TM.getCodeModel() == CodeModel::Kernel">;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000278def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
Evan Cheng13559d62008-09-26 23:41:32 +0000279def OptForSpeed : Predicate<"!OptForSize">;
Evan Cheng95a77fd2009-01-02 05:35:45 +0000280def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
Evan Cheng6d35a4d2009-05-20 04:53:57 +0000281def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000282
283//===----------------------------------------------------------------------===//
Evan Cheng86ab7d32007-07-31 08:04:03 +0000284// X86 Instruction Format Definitions.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000285//
286
Evan Cheng86ab7d32007-07-31 08:04:03 +0000287include "X86InstrFormats.td"
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000288
289//===----------------------------------------------------------------------===//
290// Pattern fragments...
291//
292
293// X86 specific condition code. These correspond to CondCode in
294// X86InstrInfo.h. They must be kept in synch.
Dan Gohman0fc9ed62009-01-07 00:15:08 +0000295def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
296def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
297def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
298def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
299def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
300def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
301def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
302def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
303def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
304def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000305def X86_COND_NO : PatLeaf<(i8 10)>;
Dan Gohman0fc9ed62009-01-07 00:15:08 +0000306def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000307def X86_COND_NS : PatLeaf<(i8 12)>;
Dan Gohman0fc9ed62009-01-07 00:15:08 +0000308def X86_COND_O : PatLeaf<(i8 13)>;
309def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
310def X86_COND_S : PatLeaf<(i8 15)>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000311
312def i16immSExt8 : PatLeaf<(i16 imm), [{
313 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
314 // sign extended field.
Dan Gohmanfaeb4a32008-09-12 16:56:44 +0000315 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000316}]>;
317
318def i32immSExt8 : PatLeaf<(i32 imm), [{
319 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
320 // sign extended field.
Dan Gohmanfaeb4a32008-09-12 16:56:44 +0000321 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000322}]>;
323
324// Helper fragments for loads.
Evan Chengb3e25ea2008-05-13 18:59:59 +0000325// It's always safe to treat a anyext i16 load as a i32 load if the i16 is
326// known to be 32-bit aligned or better. Ditto for i8 to i16.
Dan Gohman2a174122008-10-15 06:50:19 +0000327def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
Dan Gohman8335c412008-08-20 15:24:22 +0000328 LoadSDNode *LD = cast<LoadSDNode>(N);
Chris Lattner12208612009-04-10 00:16:23 +0000329 if (const Value *Src = LD->getSrcValue())
330 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wangdc97d5a2009-04-27 07:22:10 +0000331 if (PT->getAddressSpace() > 255)
Chris Lattner12208612009-04-10 00:16:23 +0000332 return false;
Dan Gohman8335c412008-08-20 15:24:22 +0000333 ISD::LoadExtType ExtType = LD->getExtensionType();
334 if (ExtType == ISD::NON_EXTLOAD)
335 return true;
336 if (ExtType == ISD::EXTLOAD)
337 return LD->getAlignment() >= 2 && !LD->isVolatile();
Evan Cheng8b765e92008-05-13 00:54:02 +0000338 return false;
339}]>;
340
Dan Gohman2a174122008-10-15 06:50:19 +0000341def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
Evan Cheng56ec77b2008-09-24 23:27:55 +0000342 LoadSDNode *LD = cast<LoadSDNode>(N);
Chris Lattner12208612009-04-10 00:16:23 +0000343 if (const Value *Src = LD->getSrcValue())
344 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wangdc97d5a2009-04-27 07:22:10 +0000345 if (PT->getAddressSpace() > 255)
Chris Lattner12208612009-04-10 00:16:23 +0000346 return false;
Evan Cheng56ec77b2008-09-24 23:27:55 +0000347 ISD::LoadExtType ExtType = LD->getExtensionType();
348 if (ExtType == ISD::EXTLOAD)
349 return LD->getAlignment() >= 2 && !LD->isVolatile();
350 return false;
351}]>;
352
Dan Gohman2a174122008-10-15 06:50:19 +0000353def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
Dan Gohman8335c412008-08-20 15:24:22 +0000354 LoadSDNode *LD = cast<LoadSDNode>(N);
Chris Lattner12208612009-04-10 00:16:23 +0000355 if (const Value *Src = LD->getSrcValue())
356 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wangdc97d5a2009-04-27 07:22:10 +0000357 if (PT->getAddressSpace() > 255)
Chris Lattner12208612009-04-10 00:16:23 +0000358 return false;
Dan Gohman8335c412008-08-20 15:24:22 +0000359 ISD::LoadExtType ExtType = LD->getExtensionType();
360 if (ExtType == ISD::NON_EXTLOAD)
361 return true;
362 if (ExtType == ISD::EXTLOAD)
363 return LD->getAlignment() >= 4 && !LD->isVolatile();
Evan Cheng8b765e92008-05-13 00:54:02 +0000364 return false;
365}]>;
366
Dan Gohman2a174122008-10-15 06:50:19 +0000367def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
Evan Cheng1e5e5452008-09-29 17:26:18 +0000368 LoadSDNode *LD = cast<LoadSDNode>(N);
Chris Lattner12208612009-04-10 00:16:23 +0000369 if (const Value *Src = LD->getSrcValue())
370 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wangdc97d5a2009-04-27 07:22:10 +0000371 if (PT->getAddressSpace() > 255)
Chris Lattner12208612009-04-10 00:16:23 +0000372 return false;
Evan Cheng1e5e5452008-09-29 17:26:18 +0000373 if (LD->isVolatile())
374 return false;
Evan Cheng1e5e5452008-09-29 17:26:18 +0000375 ISD::LoadExtType ExtType = LD->getExtensionType();
376 if (ExtType == ISD::NON_EXTLOAD)
377 return true;
378 if (ExtType == ISD::EXTLOAD)
379 return LD->getAlignment() >= 4;
380 return false;
381}]>;
382
sampo9cc09a32009-01-26 01:24:32 +0000383def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
Chris Lattner12208612009-04-10 00:16:23 +0000384 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
385 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
386 return PT->getAddressSpace() == 256;
sampo9cc09a32009-01-26 01:24:32 +0000387 return false;
388}]>;
389
Chris Lattnera7c2d8a2009-05-05 18:52:19 +0000390def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
391 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
392 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
393 return PT->getAddressSpace() == 257;
394 return false;
395}]>;
396
Chris Lattner12208612009-04-10 00:16:23 +0000397def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
398 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
399 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wangdc97d5a2009-04-27 07:22:10 +0000400 if (PT->getAddressSpace() > 255)
Chris Lattner12208612009-04-10 00:16:23 +0000401 return false;
402 return true;
403}]>;
404def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
405 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
406 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wangdc97d5a2009-04-27 07:22:10 +0000407 if (PT->getAddressSpace() > 255)
Chris Lattner12208612009-04-10 00:16:23 +0000408 return false;
409 return true;
410}]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000411
Chris Lattner12208612009-04-10 00:16:23 +0000412def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
413 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
414 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wangdc97d5a2009-04-27 07:22:10 +0000415 if (PT->getAddressSpace() > 255)
Chris Lattner12208612009-04-10 00:16:23 +0000416 return false;
417 return true;
418}]>;
419def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
420 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
421 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wangdc97d5a2009-04-27 07:22:10 +0000422 if (PT->getAddressSpace() > 255)
Chris Lattner12208612009-04-10 00:16:23 +0000423 return false;
424 return true;
425}]>;
426def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
427 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
428 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wangdc97d5a2009-04-27 07:22:10 +0000429 if (PT->getAddressSpace() > 255)
Chris Lattner12208612009-04-10 00:16:23 +0000430 return false;
431 return true;
432}]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000433
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000434def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
435def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
436def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
437
438def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
439def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
440def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
441def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
442def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
443def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
444
445def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
446def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
447def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
448def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
449def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
450def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
451
Chris Lattner21da6382008-02-19 17:37:35 +0000452
453// An 'and' node with a single use.
454def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
Evan Cheng9123cfa2008-03-04 00:40:35 +0000455 return N->hasOneUse();
Chris Lattner21da6382008-02-19 17:37:35 +0000456}]>;
Dan Gohman744d4622009-04-13 16:09:41 +0000457// An 'srl' node with a single use.
458def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
459 return N->hasOneUse();
460}]>;
461// An 'trunc' node with a single use.
462def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
463 return N->hasOneUse();
464}]>;
Chris Lattner21da6382008-02-19 17:37:35 +0000465
Dan Gohman921581d2008-10-17 01:23:35 +0000466// 'shld' and 'shrd' instruction patterns. Note that even though these have
467// the srl and shl in their patterns, the C++ code must still check for them,
468// because predicates are tested before children nodes are explored.
469
470def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
471 (or (srl node:$src1, node:$amt1),
472 (shl node:$src2, node:$amt2)), [{
473 assert(N->getOpcode() == ISD::OR);
474 return N->getOperand(0).getOpcode() == ISD::SRL &&
475 N->getOperand(1).getOpcode() == ISD::SHL &&
476 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
477 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
478 N->getOperand(0).getConstantOperandVal(1) ==
479 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
480}]>;
481
482def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
483 (or (shl node:$src1, node:$amt1),
484 (srl node:$src2, node:$amt2)), [{
485 assert(N->getOpcode() == ISD::OR);
486 return N->getOperand(0).getOpcode() == ISD::SHL &&
487 N->getOperand(1).getOpcode() == ISD::SRL &&
488 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
489 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
490 N->getOperand(0).getConstantOperandVal(1) ==
491 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
492}]>;
493
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000494//===----------------------------------------------------------------------===//
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000495// Instruction list...
496//
497
498// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
499// a stack adjustment and the codegen must know that they may modify the stack
500// pointer before prolog-epilog rewriting occurs.
Chris Lattnerb56cc342008-03-11 03:23:40 +0000501// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
502// sub / add which can clobber EFLAGS.
Evan Cheng037364a2007-09-28 01:19:48 +0000503let Defs = [ESP, EFLAGS], Uses = [ESP] in {
Dan Gohman01c9f772008-10-01 18:28:06 +0000504def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
505 "#ADJCALLSTACKDOWN",
Chris Lattnerfe5d4022008-10-11 22:08:30 +0000506 [(X86callseq_start timm:$amt)]>,
Dan Gohman01c9f772008-10-01 18:28:06 +0000507 Requires<[In32BitMode]>;
508def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
509 "#ADJCALLSTACKUP",
Chris Lattnerfe5d4022008-10-11 22:08:30 +0000510 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
Dan Gohman01c9f772008-10-01 18:28:06 +0000511 Requires<[In32BitMode]>;
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000512}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000513
514// Nop
Sean Callananf94a0542009-07-23 23:39:34 +0000515let neverHasSideEffects = 1 in {
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000516 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
Sean Callananf94a0542009-07-23 23:39:34 +0000517 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
518 "nopl\t$zero", []>, TB;
519}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000520
Evan Cheng0729ccf2008-01-05 00:41:47 +0000521// PIC base
Dan Gohman9499cfe2008-10-01 04:14:30 +0000522let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000523 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
Dan Gohman70a8a112009-04-27 15:13:28 +0000524 "call\t$label\n\t"
525 "pop{l}\t$reg", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000526
527//===----------------------------------------------------------------------===//
528// Control Flow Instructions...
529//
530
531// Return instructions.
532let isTerminator = 1, isReturn = 1, isBarrier = 1,
Chris Lattnerb56cc342008-03-11 03:23:40 +0000533 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
Dan Gohman2c4be2a2008-05-31 02:11:25 +0000534 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
Chris Lattnerb56cc342008-03-11 03:23:40 +0000535 "ret",
Dan Gohman2c4be2a2008-05-31 02:11:25 +0000536 [(X86retflag 0)]>;
Chris Lattnerb56cc342008-03-11 03:23:40 +0000537 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
538 "ret\t$amt",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000539 [(X86retflag imm:$amt)]>;
540}
541
542// All branches are RawFrm, Void, Branch, and Terminators
Evan Cheng37e7c752007-07-21 00:34:19 +0000543let isBranch = 1, isTerminator = 1 in
Evan Chengb783fa32007-07-19 01:14:50 +0000544 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
545 I<opcode, RawFrm, (outs), ins, asm, pattern>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000546
Sean Callananc0608152009-07-22 01:05:20 +0000547let isBranch = 1, isBarrier = 1 in {
Dan Gohman91888f02007-07-31 20:11:57 +0000548 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
Sean Callananc0608152009-07-22 01:05:20 +0000549 def JMP8 : IBr<0xEB, (ins brtarget8:$dst), "jmp\t$dst", []>;
550}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000551
Owen Andersonf8053082007-11-12 07:39:39 +0000552// Indirect branches
553let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
Dan Gohman91888f02007-07-31 20:11:57 +0000554 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000555 [(brind GR32:$dst)]>;
Dan Gohman91888f02007-07-31 20:11:57 +0000556 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000557 [(brind (loadi32 addr:$dst))]>;
558}
559
560// Conditional branches
Evan Cheng950aac02007-09-25 01:57:46 +0000561let Uses = [EFLAGS] in {
Evan Chengd11052b2009-07-21 06:00:18 +0000562// Short conditional jumps
563def JO8 : IBr<0x70, (ins brtarget8:$dst), "jo\t$dst", []>;
564def JNO8 : IBr<0x71, (ins brtarget8:$dst), "jno\t$dst", []>;
565def JB8 : IBr<0x72, (ins brtarget8:$dst), "jb\t$dst", []>;
566def JAE8 : IBr<0x73, (ins brtarget8:$dst), "jae\t$dst", []>;
567def JE8 : IBr<0x74, (ins brtarget8:$dst), "je\t$dst", []>;
568def JNE8 : IBr<0x75, (ins brtarget8:$dst), "jne\t$dst", []>;
569def JBE8 : IBr<0x76, (ins brtarget8:$dst), "jbe\t$dst", []>;
570def JA8 : IBr<0x77, (ins brtarget8:$dst), "ja\t$dst", []>;
571def JS8 : IBr<0x78, (ins brtarget8:$dst), "js\t$dst", []>;
572def JNS8 : IBr<0x79, (ins brtarget8:$dst), "jns\t$dst", []>;
573def JP8 : IBr<0x7A, (ins brtarget8:$dst), "jp\t$dst", []>;
574def JNP8 : IBr<0x7B, (ins brtarget8:$dst), "jnp\t$dst", []>;
575def JL8 : IBr<0x7C, (ins brtarget8:$dst), "jl\t$dst", []>;
576def JGE8 : IBr<0x7D, (ins brtarget8:$dst), "jge\t$dst", []>;
577def JLE8 : IBr<0x7E, (ins brtarget8:$dst), "jle\t$dst", []>;
578def JG8 : IBr<0x7F, (ins brtarget8:$dst), "jg\t$dst", []>;
579
580def JCXZ8 : IBr<0xE3, (ins brtarget8:$dst), "jcxz\t$dst", []>;
581
Dan Gohman91888f02007-07-31 20:11:57 +0000582def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000583 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000584def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000585 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000586def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000587 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000588def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000589 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000590def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000591 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000592def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000593 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000594
Dan Gohman91888f02007-07-31 20:11:57 +0000595def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000596 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000597def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000598 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000599def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000600 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000601def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000602 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000603
Dan Gohman91888f02007-07-31 20:11:57 +0000604def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000605 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000606def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000607 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000608def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000609 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000610def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000611 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000612def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000613 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000614def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000615 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
Evan Cheng950aac02007-09-25 01:57:46 +0000616} // Uses = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000617
618//===----------------------------------------------------------------------===//
619// Call Instructions...
620//
Evan Cheng37e7c752007-07-21 00:34:19 +0000621let isCall = 1 in
Dan Gohman01c9f772008-10-01 18:28:06 +0000622 // All calls clobber the non-callee saved registers. ESP is marked as
623 // a use to prevent stack-pointer assignments that appear immediately
624 // before calls from potentially appearing dead. Uses for argument
625 // registers are added manually.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000626 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
627 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
Evan Cheng2293b252008-10-17 21:02:22 +0000628 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
629 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
Dan Gohman9499cfe2008-10-01 04:14:30 +0000630 Uses = [ESP] in {
Chris Lattner357a0ca2009-06-20 19:34:09 +0000631 def CALLpcrel32 : Ii32<0xE8, RawFrm,
632 (outs), (ins i32imm_pcrel:$dst,variable_ops),
633 "call\t$dst", []>;
Evan Chengb783fa32007-07-19 01:14:50 +0000634 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
Dan Gohman91888f02007-07-31 20:11:57 +0000635 "call\t{*}$dst", [(X86call GR32:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +0000636 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
Dan Gohmanea4faba2008-05-29 21:50:34 +0000637 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000638 }
639
640// Tail call stuff.
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +0000641
Evan Cheng37e7c752007-07-21 00:34:19 +0000642let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
Arnold Schwaighofer6fd37ac2008-03-19 16:39:45 +0000643def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +0000644 "#TC_RETURN $dst $offset",
645 []>;
646
647let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
Arnold Schwaighofer6fd37ac2008-03-19 16:39:45 +0000648def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +0000649 "#TC_RETURN $dst $offset",
650 []>;
651
652let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
Arnold Schwaighofera0032722008-04-30 09:16:33 +0000653
Chris Lattner357a0ca2009-06-20 19:34:09 +0000654 def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst), "jmp\t$dst # TAILCALL",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000655 []>;
Evan Cheng37e7c752007-07-21 00:34:19 +0000656let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +0000657 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
658 []>;
Evan Cheng37e7c752007-07-21 00:34:19 +0000659let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
Evan Chengb783fa32007-07-19 01:14:50 +0000660 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +0000661 "jmp\t{*}$dst # TAILCALL", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000662
663//===----------------------------------------------------------------------===//
664// Miscellaneous Instructions...
665//
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000666let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000667def LEAVE : I<0xC9, RawFrm,
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000668 (outs), (ins), "leave", []>;
669
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000670let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
671let mayLoad = 1 in
Evan Chengd8434332007-09-26 01:29:06 +0000672def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000673
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000674let mayStore = 1 in
Evan Chengd8434332007-09-26 01:29:06 +0000675def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000676}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000677
Bill Wendling4c2638c2009-06-15 19:39:04 +0000678let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
679def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
Bill Wendling0b0437f2009-06-15 20:59:31 +0000680 "push{l}\t$imm", []>;
Bill Wendling4c2638c2009-06-15 19:39:04 +0000681def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
Bill Wendling0b0437f2009-06-15 20:59:31 +0000682 "push{l}\t$imm", []>;
Bill Wendling4c2638c2009-06-15 19:39:04 +0000683def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
Bill Wendling0b0437f2009-06-15 20:59:31 +0000684 "push{l}\t$imm", []>;
Bill Wendling4c2638c2009-06-15 19:39:04 +0000685}
686
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000687let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
Evan Chengf1341312007-09-26 21:28:00 +0000688def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000689let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
Evan Chengf1341312007-09-26 21:28:00 +0000690def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
Evan Chengd8434332007-09-26 01:29:06 +0000691
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000692let isTwoAddress = 1 in // GR32 = bswap GR32
693 def BSWAP32r : I<0xC8, AddRegFrm,
Evan Chengb783fa32007-07-19 01:14:50 +0000694 (outs GR32:$dst), (ins GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000695 "bswap{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000696 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
697
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000698
Evan Cheng48679f42007-12-14 02:13:44 +0000699// Bit scan instructions.
700let Defs = [EFLAGS] in {
Evan Cheng4e33de92007-12-14 18:49:43 +0000701def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
Dan Gohmancdb54c62007-12-14 15:10:00 +0000702 "bsf{w}\t{$src, $dst|$dst, $src}",
Evan Cheng7cfbfe32007-12-14 08:30:15 +0000703 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
Evan Cheng48679f42007-12-14 02:13:44 +0000704def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
Dan Gohmancdb54c62007-12-14 15:10:00 +0000705 "bsf{w}\t{$src, $dst|$dst, $src}",
Evan Cheng7cfbfe32007-12-14 08:30:15 +0000706 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
707 (implicit EFLAGS)]>, TB;
Evan Cheng4e33de92007-12-14 18:49:43 +0000708def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
Dan Gohmancdb54c62007-12-14 15:10:00 +0000709 "bsf{l}\t{$src, $dst|$dst, $src}",
Evan Cheng7cfbfe32007-12-14 08:30:15 +0000710 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
Evan Cheng48679f42007-12-14 02:13:44 +0000711def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
Dan Gohmancdb54c62007-12-14 15:10:00 +0000712 "bsf{l}\t{$src, $dst|$dst, $src}",
Evan Cheng7cfbfe32007-12-14 08:30:15 +0000713 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
714 (implicit EFLAGS)]>, TB;
Evan Cheng48679f42007-12-14 02:13:44 +0000715
Evan Cheng4e33de92007-12-14 18:49:43 +0000716def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
Dan Gohmancdb54c62007-12-14 15:10:00 +0000717 "bsr{w}\t{$src, $dst|$dst, $src}",
Evan Cheng7cfbfe32007-12-14 08:30:15 +0000718 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
Evan Cheng48679f42007-12-14 02:13:44 +0000719def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
Dan Gohmancdb54c62007-12-14 15:10:00 +0000720 "bsr{w}\t{$src, $dst|$dst, $src}",
Evan Cheng7cfbfe32007-12-14 08:30:15 +0000721 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
722 (implicit EFLAGS)]>, TB;
Evan Cheng4e33de92007-12-14 18:49:43 +0000723def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
Dan Gohmancdb54c62007-12-14 15:10:00 +0000724 "bsr{l}\t{$src, $dst|$dst, $src}",
Evan Cheng7cfbfe32007-12-14 08:30:15 +0000725 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
Evan Cheng48679f42007-12-14 02:13:44 +0000726def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
Dan Gohmancdb54c62007-12-14 15:10:00 +0000727 "bsr{l}\t{$src, $dst|$dst, $src}",
Evan Cheng7cfbfe32007-12-14 08:30:15 +0000728 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
729 (implicit EFLAGS)]>, TB;
Evan Cheng48679f42007-12-14 02:13:44 +0000730} // Defs = [EFLAGS]
731
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000732let neverHasSideEffects = 1 in
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000733def LEA16r : I<0x8D, MRMSrcMem,
Evan Chengb783fa32007-07-19 01:14:50 +0000734 (outs GR16:$dst), (ins i32mem:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000735 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
Evan Cheng1ea8e6b2008-03-27 01:41:09 +0000736let isReMaterializable = 1 in
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000737def LEA32r : I<0x8D, MRMSrcMem,
Evan Chengb783fa32007-07-19 01:14:50 +0000738 (outs GR32:$dst), (ins lea32mem:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000739 "lea{l}\t{$src|$dst}, {$dst|$src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000740 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
741
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000742let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
Evan Chengb783fa32007-07-19 01:14:50 +0000743def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000744 [(X86rep_movs i8)]>, REP;
Evan Chengb783fa32007-07-19 01:14:50 +0000745def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000746 [(X86rep_movs i16)]>, REP, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +0000747def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000748 [(X86rep_movs i32)]>, REP;
749}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000750
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000751let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
Evan Chengb783fa32007-07-19 01:14:50 +0000752def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000753 [(X86rep_stos i8)]>, REP;
754let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
Evan Chengb783fa32007-07-19 01:14:50 +0000755def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000756 [(X86rep_stos i16)]>, REP, OpSize;
757let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
Evan Chengb783fa32007-07-19 01:14:50 +0000758def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000759 [(X86rep_stos i32)]>, REP;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000760
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000761let Defs = [RAX, RDX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000762def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000763 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000764
Anton Korobeynikov39d40ba2008-01-15 07:02:33 +0000765let isBarrier = 1, hasCtrlDep = 1 in {
Chris Lattner56b941f2008-01-15 21:58:22 +0000766def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
Anton Korobeynikov39d40ba2008-01-15 07:02:33 +0000767}
768
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000769//===----------------------------------------------------------------------===//
770// Input/Output Instructions...
771//
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000772let Defs = [AL], Uses = [DX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000773def IN8rr : I<0xEC, RawFrm, (outs), (ins),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000774 "in{b}\t{%dx, %al|%AL, %DX}", []>;
775let Defs = [AX], Uses = [DX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000776def IN16rr : I<0xED, RawFrm, (outs), (ins),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000777 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
778let Defs = [EAX], Uses = [DX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000779def IN32rr : I<0xED, RawFrm, (outs), (ins),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000780 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000781
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000782let Defs = [AL] in
Evan Chengb783fa32007-07-19 01:14:50 +0000783def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000784 "in{b}\t{$port, %al|%AL, $port}", []>;
785let Defs = [AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000786def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000787 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
788let Defs = [EAX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000789def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000790 "in{l}\t{$port, %eax|%EAX, $port}", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000791
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000792let Uses = [DX, AL] in
Evan Chengb783fa32007-07-19 01:14:50 +0000793def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000794 "out{b}\t{%al, %dx|%DX, %AL}", []>;
795let Uses = [DX, AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000796def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000797 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
798let Uses = [DX, EAX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000799def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000800 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000801
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000802let Uses = [AL] in
Evan Chengb783fa32007-07-19 01:14:50 +0000803def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000804 "out{b}\t{%al, $port|$port, %AL}", []>;
805let Uses = [AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000806def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000807 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
808let Uses = [EAX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000809def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000810 "out{l}\t{%eax, $port|$port, %EAX}", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000811
812//===----------------------------------------------------------------------===//
813// Move Instructions...
814//
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000815let neverHasSideEffects = 1 in {
Evan Chengb783fa32007-07-19 01:14:50 +0000816def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000817 "mov{b}\t{$src, $dst|$dst, $src}", []>;
Evan Chengb783fa32007-07-19 01:14:50 +0000818def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000819 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +0000820def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000821 "mov{l}\t{$src, $dst|$dst, $src}", []>;
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000822}
Evan Cheng6f26e8b2008-06-18 08:13:07 +0000823let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
Evan Chengb783fa32007-07-19 01:14:50 +0000824def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000825 "mov{b}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000826 [(set GR8:$dst, imm:$src)]>;
Evan Chengb783fa32007-07-19 01:14:50 +0000827def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000828 "mov{w}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000829 [(set GR16:$dst, imm:$src)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +0000830def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000831 "mov{l}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000832 [(set GR32:$dst, imm:$src)]>;
833}
Evan Chengb783fa32007-07-19 01:14:50 +0000834def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000835 "mov{b}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000836 [(store (i8 imm:$src), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +0000837def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000838 "mov{w}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000839 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +0000840def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000841 "mov{l}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000842 [(store (i32 imm:$src), addr:$dst)]>;
843
Dan Gohman5574cc72008-12-03 18:15:48 +0000844let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
Evan Chengb783fa32007-07-19 01:14:50 +0000845def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000846 "mov{b}\t{$src, $dst|$dst, $src}",
Chris Lattner12208612009-04-10 00:16:23 +0000847 [(set GR8:$dst, (loadi8 addr:$src))]>;
Evan Chengb783fa32007-07-19 01:14:50 +0000848def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000849 "mov{w}\t{$src, $dst|$dst, $src}",
Chris Lattner12208612009-04-10 00:16:23 +0000850 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +0000851def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000852 "mov{l}\t{$src, $dst|$dst, $src}",
Chris Lattner12208612009-04-10 00:16:23 +0000853 [(set GR32:$dst, (loadi32 addr:$src))]>;
Evan Cheng4e84e452007-08-30 05:49:43 +0000854}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000855
Evan Chengb783fa32007-07-19 01:14:50 +0000856def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000857 "mov{b}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000858 [(store GR8:$src, addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +0000859def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000860 "mov{w}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000861 [(store GR16:$src, addr:$dst)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +0000862def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000863 "mov{l}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000864 [(store GR32:$src, addr:$dst)]>;
Dan Gohman744d4622009-04-13 16:09:41 +0000865
Dan Gohman1d8ce9c2009-04-27 16:41:36 +0000866// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
867// that they can be used for copying and storing h registers, which can't be
868// encoded when a REX prefix is present.
Dan Gohman2da0db32009-04-15 00:04:23 +0000869let neverHasSideEffects = 1 in
Dan Gohman40ddc362009-04-15 19:48:57 +0000870def MOV8rr_NOREX : I<0x88, MRMDestReg,
871 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
Dan Gohman2da0db32009-04-15 00:04:23 +0000872 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
Evan Chengebc49402009-04-30 00:58:57 +0000873let mayStore = 1 in
Dan Gohman2da0db32009-04-15 00:04:23 +0000874def MOV8mr_NOREX : I<0x88, MRMDestMem,
875 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
876 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
Evan Chengebc49402009-04-30 00:58:57 +0000877let mayLoad = 1,
878 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
Dan Gohman1d8ce9c2009-04-27 16:41:36 +0000879def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
880 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
881 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
Dan Gohman744d4622009-04-13 16:09:41 +0000882
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000883//===----------------------------------------------------------------------===//
884// Fixed-Register Multiplication and Division Instructions...
885//
886
887// Extra precision multiplication
Evan Cheng55687072007-09-14 21:48:26 +0000888let Defs = [AL,AH,EFLAGS], Uses = [AL] in
Dan Gohman91888f02007-07-31 20:11:57 +0000889def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000890 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
891 // This probably ought to be moved to a def : Pat<> if the
892 // syntax can be accepted.
Bill Wendlingf5399032008-12-12 21:15:41 +0000893 [(set AL, (mul AL, GR8:$src)),
894 (implicit EFLAGS)]>; // AL,AH = AL*GR8
895
Chris Lattnerc7e96e72008-01-11 07:18:17 +0000896let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
Bill Wendlingf5399032008-12-12 21:15:41 +0000897def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
898 "mul{w}\t$src",
899 []>, OpSize; // AX,DX = AX*GR16
900
Chris Lattnerc7e96e72008-01-11 07:18:17 +0000901let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
Bill Wendlingf5399032008-12-12 21:15:41 +0000902def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
903 "mul{l}\t$src",
904 []>; // EAX,EDX = EAX*GR32
905
Evan Cheng55687072007-09-14 21:48:26 +0000906let Defs = [AL,AH,EFLAGS], Uses = [AL] in
Evan Chengb783fa32007-07-19 01:14:50 +0000907def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000908 "mul{b}\t$src",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000909 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
910 // This probably ought to be moved to a def : Pat<> if the
911 // syntax can be accepted.
Bill Wendlingf5399032008-12-12 21:15:41 +0000912 [(set AL, (mul AL, (loadi8 addr:$src))),
913 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
914
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000915let mayLoad = 1, neverHasSideEffects = 1 in {
Evan Cheng55687072007-09-14 21:48:26 +0000916let Defs = [AX,DX,EFLAGS], Uses = [AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000917def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
Bill Wendlingf5399032008-12-12 21:15:41 +0000918 "mul{w}\t$src",
919 []>, OpSize; // AX,DX = AX*[mem16]
920
Evan Cheng55687072007-09-14 21:48:26 +0000921let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000922def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
Bill Wendlingf5399032008-12-12 21:15:41 +0000923 "mul{l}\t$src",
924 []>; // EAX,EDX = EAX*[mem32]
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000925}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000926
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000927let neverHasSideEffects = 1 in {
Evan Cheng55687072007-09-14 21:48:26 +0000928let Defs = [AL,AH,EFLAGS], Uses = [AL] in
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000929def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
930 // AL,AH = AL*GR8
Evan Cheng55687072007-09-14 21:48:26 +0000931let Defs = [AX,DX,EFLAGS], Uses = [AX] in
Dan Gohman91888f02007-07-31 20:11:57 +0000932def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000933 OpSize; // AX,DX = AX*GR16
Evan Cheng55687072007-09-14 21:48:26 +0000934let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000935def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
936 // EAX,EDX = EAX*GR32
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000937let mayLoad = 1 in {
Evan Cheng55687072007-09-14 21:48:26 +0000938let Defs = [AL,AH,EFLAGS], Uses = [AL] in
Evan Chengb783fa32007-07-19 01:14:50 +0000939def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000940 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
Evan Cheng55687072007-09-14 21:48:26 +0000941let Defs = [AX,DX,EFLAGS], Uses = [AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000942def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000943 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
944let Defs = [EAX,EDX], Uses = [EAX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000945def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000946 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000947}
Dan Gohmand44572d2008-11-18 21:29:14 +0000948} // neverHasSideEffects
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000949
950// unsigned division/remainder
Dale Johannesend8fd3562008-10-07 18:54:28 +0000951let Defs = [AL,AH,EFLAGS], Uses = [AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000952def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000953 "div{b}\t$src", []>;
Evan Cheng55687072007-09-14 21:48:26 +0000954let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000955def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000956 "div{w}\t$src", []>, OpSize;
Evan Cheng55687072007-09-14 21:48:26 +0000957let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000958def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000959 "div{l}\t$src", []>;
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000960let mayLoad = 1 in {
Dale Johannesend8fd3562008-10-07 18:54:28 +0000961let Defs = [AL,AH,EFLAGS], Uses = [AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000962def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000963 "div{b}\t$src", []>;
Evan Cheng55687072007-09-14 21:48:26 +0000964let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000965def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000966 "div{w}\t$src", []>, OpSize;
Evan Cheng55687072007-09-14 21:48:26 +0000967let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000968def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000969 "div{l}\t$src", []>;
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000970}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000971
972// Signed division/remainder.
Dale Johannesend8fd3562008-10-07 18:54:28 +0000973let Defs = [AL,AH,EFLAGS], Uses = [AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000974def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000975 "idiv{b}\t$src", []>;
Evan Cheng55687072007-09-14 21:48:26 +0000976let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000977def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000978 "idiv{w}\t$src", []>, OpSize;
Evan Cheng55687072007-09-14 21:48:26 +0000979let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000980def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000981 "idiv{l}\t$src", []>;
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000982let mayLoad = 1, mayLoad = 1 in {
Dale Johannesend8fd3562008-10-07 18:54:28 +0000983let Defs = [AL,AH,EFLAGS], Uses = [AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000984def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000985 "idiv{b}\t$src", []>;
Evan Cheng55687072007-09-14 21:48:26 +0000986let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000987def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000988 "idiv{w}\t$src", []>, OpSize;
Evan Cheng55687072007-09-14 21:48:26 +0000989let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000990def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000991 "idiv{l}\t$src", []>;
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000992}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000993
994//===----------------------------------------------------------------------===//
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000995// Two address Instructions.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000996//
997let isTwoAddress = 1 in {
998
999// Conditional moves
Evan Cheng950aac02007-09-25 01:57:46 +00001000let Uses = [EFLAGS] in {
Evan Cheng926658c2007-10-05 23:13:21 +00001001let isCommutable = 1 in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001002def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +00001003 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001004 "cmovb\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001005 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001006 X86_COND_B, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001007 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001008def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +00001009 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001010 "cmovb\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001011 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001012 X86_COND_B, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001013 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001014def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +00001015 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001016 "cmovae\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001017 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001018 X86_COND_AE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001019 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001020def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +00001021 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001022 "cmovae\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001023 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001024 X86_COND_AE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001025 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001026def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +00001027 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001028 "cmove\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001029 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001030 X86_COND_E, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001031 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001032def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +00001033 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001034 "cmove\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001035 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001036 X86_COND_E, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001037 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001038def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +00001039 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001040 "cmovne\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001041 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001042 X86_COND_NE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001043 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001044def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +00001045 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001046 "cmovne\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001047 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001048 X86_COND_NE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001049 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001050def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +00001051 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001052 "cmovbe\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001053 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001054 X86_COND_BE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001055 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001056def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +00001057 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001058 "cmovbe\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001059 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001060 X86_COND_BE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001061 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001062def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +00001063 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001064 "cmova\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001065 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001066 X86_COND_A, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001067 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001068def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +00001069 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001070 "cmova\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001071 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001072 X86_COND_A, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001073 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001074def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +00001075 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001076 "cmovl\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001077 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001078 X86_COND_L, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001079 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001080def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +00001081 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001082 "cmovl\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001083 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001084 X86_COND_L, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001085 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001086def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +00001087 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001088 "cmovge\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001089 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001090 X86_COND_GE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001091 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001092def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +00001093 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001094 "cmovge\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001095 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001096 X86_COND_GE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001097 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001098def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +00001099 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001100 "cmovle\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001101 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001102 X86_COND_LE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001103 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001104def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +00001105 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001106 "cmovle\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001107 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001108 X86_COND_LE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001109 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001110def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +00001111 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001112 "cmovg\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001113 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001114 X86_COND_G, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001115 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001116def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +00001117 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001118 "cmovg\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001119 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001120 X86_COND_G, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001121 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001122def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +00001123 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001124 "cmovs\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001125 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001126 X86_COND_S, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001127 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001128def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +00001129 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001130 "cmovs\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001131 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001132 X86_COND_S, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001133 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001134def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +00001135 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001136 "cmovns\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001137 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001138 X86_COND_NS, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001139 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001140def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +00001141 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001142 "cmovns\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001143 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001144 X86_COND_NS, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001145 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001146def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +00001147 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001148 "cmovp\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001149 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001150 X86_COND_P, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001151 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001152def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +00001153 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001154 "cmovp\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001155 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001156 X86_COND_P, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001157 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001158def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +00001159 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001160 "cmovnp\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001161 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001162 X86_COND_NP, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001163 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001164def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +00001165 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001166 "cmovnp\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001167 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001168 X86_COND_NP, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001169 TB;
Dan Gohman12fd4d72009-01-07 00:35:10 +00001170def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1171 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1172 "cmovo\t{$src2, $dst|$dst, $src2}",
1173 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1174 X86_COND_O, EFLAGS))]>,
1175 TB, OpSize;
1176def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1177 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1178 "cmovo\t{$src2, $dst|$dst, $src2}",
1179 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1180 X86_COND_O, EFLAGS))]>,
Evan Cheng950aac02007-09-25 01:57:46 +00001181 TB;
Dan Gohman12fd4d72009-01-07 00:35:10 +00001182def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1183 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1184 "cmovno\t{$src2, $dst|$dst, $src2}",
1185 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1186 X86_COND_NO, EFLAGS))]>,
1187 TB, OpSize;
1188def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1189 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1190 "cmovno\t{$src2, $dst|$dst, $src2}",
1191 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1192 X86_COND_NO, EFLAGS))]>,
1193 TB;
1194} // isCommutable = 1
Evan Cheng926658c2007-10-05 23:13:21 +00001195
1196def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1197 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1198 "cmovb\t{$src2, $dst|$dst, $src2}",
1199 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1200 X86_COND_B, EFLAGS))]>,
1201 TB, OpSize;
1202def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1203 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1204 "cmovb\t{$src2, $dst|$dst, $src2}",
1205 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1206 X86_COND_B, EFLAGS))]>,
1207 TB;
1208def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1209 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1210 "cmovae\t{$src2, $dst|$dst, $src2}",
1211 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1212 X86_COND_AE, EFLAGS))]>,
1213 TB, OpSize;
1214def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1215 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1216 "cmovae\t{$src2, $dst|$dst, $src2}",
1217 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1218 X86_COND_AE, EFLAGS))]>,
1219 TB;
1220def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1221 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1222 "cmove\t{$src2, $dst|$dst, $src2}",
1223 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1224 X86_COND_E, EFLAGS))]>,
1225 TB, OpSize;
1226def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1227 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1228 "cmove\t{$src2, $dst|$dst, $src2}",
1229 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1230 X86_COND_E, EFLAGS))]>,
1231 TB;
1232def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1233 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1234 "cmovne\t{$src2, $dst|$dst, $src2}",
1235 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1236 X86_COND_NE, EFLAGS))]>,
1237 TB, OpSize;
1238def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1239 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1240 "cmovne\t{$src2, $dst|$dst, $src2}",
1241 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1242 X86_COND_NE, EFLAGS))]>,
1243 TB;
1244def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1245 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1246 "cmovbe\t{$src2, $dst|$dst, $src2}",
1247 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1248 X86_COND_BE, EFLAGS))]>,
1249 TB, OpSize;
1250def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1251 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1252 "cmovbe\t{$src2, $dst|$dst, $src2}",
1253 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1254 X86_COND_BE, EFLAGS))]>,
1255 TB;
1256def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1257 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1258 "cmova\t{$src2, $dst|$dst, $src2}",
1259 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1260 X86_COND_A, EFLAGS))]>,
1261 TB, OpSize;
1262def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1263 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1264 "cmova\t{$src2, $dst|$dst, $src2}",
1265 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1266 X86_COND_A, EFLAGS))]>,
1267 TB;
1268def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1269 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1270 "cmovl\t{$src2, $dst|$dst, $src2}",
1271 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1272 X86_COND_L, EFLAGS))]>,
1273 TB, OpSize;
1274def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1275 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1276 "cmovl\t{$src2, $dst|$dst, $src2}",
1277 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1278 X86_COND_L, EFLAGS))]>,
1279 TB;
1280def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1281 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1282 "cmovge\t{$src2, $dst|$dst, $src2}",
1283 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1284 X86_COND_GE, EFLAGS))]>,
1285 TB, OpSize;
1286def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1287 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1288 "cmovge\t{$src2, $dst|$dst, $src2}",
1289 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1290 X86_COND_GE, EFLAGS))]>,
1291 TB;
1292def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1293 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1294 "cmovle\t{$src2, $dst|$dst, $src2}",
1295 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1296 X86_COND_LE, EFLAGS))]>,
1297 TB, OpSize;
1298def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1299 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1300 "cmovle\t{$src2, $dst|$dst, $src2}",
1301 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1302 X86_COND_LE, EFLAGS))]>,
1303 TB;
1304def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1305 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1306 "cmovg\t{$src2, $dst|$dst, $src2}",
1307 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1308 X86_COND_G, EFLAGS))]>,
1309 TB, OpSize;
1310def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1311 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1312 "cmovg\t{$src2, $dst|$dst, $src2}",
1313 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1314 X86_COND_G, EFLAGS))]>,
1315 TB;
1316def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1317 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1318 "cmovs\t{$src2, $dst|$dst, $src2}",
1319 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1320 X86_COND_S, EFLAGS))]>,
1321 TB, OpSize;
1322def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1323 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1324 "cmovs\t{$src2, $dst|$dst, $src2}",
1325 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1326 X86_COND_S, EFLAGS))]>,
1327 TB;
1328def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1329 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1330 "cmovns\t{$src2, $dst|$dst, $src2}",
1331 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1332 X86_COND_NS, EFLAGS))]>,
1333 TB, OpSize;
1334def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1335 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1336 "cmovns\t{$src2, $dst|$dst, $src2}",
1337 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1338 X86_COND_NS, EFLAGS))]>,
1339 TB;
1340def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1341 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1342 "cmovp\t{$src2, $dst|$dst, $src2}",
1343 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1344 X86_COND_P, EFLAGS))]>,
1345 TB, OpSize;
1346def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1347 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1348 "cmovp\t{$src2, $dst|$dst, $src2}",
1349 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1350 X86_COND_P, EFLAGS))]>,
1351 TB;
1352def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1353 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1354 "cmovnp\t{$src2, $dst|$dst, $src2}",
1355 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1356 X86_COND_NP, EFLAGS))]>,
1357 TB, OpSize;
Dan Gohman12fd4d72009-01-07 00:35:10 +00001358def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1359 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1360 "cmovnp\t{$src2, $dst|$dst, $src2}",
1361 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1362 X86_COND_NP, EFLAGS))]>,
1363 TB;
1364def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1365 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1366 "cmovo\t{$src2, $dst|$dst, $src2}",
1367 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1368 X86_COND_O, EFLAGS))]>,
1369 TB, OpSize;
1370def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1371 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1372 "cmovo\t{$src2, $dst|$dst, $src2}",
1373 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1374 X86_COND_O, EFLAGS))]>,
1375 TB;
1376def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1377 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1378 "cmovno\t{$src2, $dst|$dst, $src2}",
1379 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1380 X86_COND_NO, EFLAGS))]>,
1381 TB, OpSize;
1382def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1383 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1384 "cmovno\t{$src2, $dst|$dst, $src2}",
1385 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1386 X86_COND_NO, EFLAGS))]>,
1387 TB;
Evan Cheng950aac02007-09-25 01:57:46 +00001388} // Uses = [EFLAGS]
1389
1390
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001391// unary instructions
1392let CodeSize = 2 in {
Evan Cheng55687072007-09-14 21:48:26 +00001393let Defs = [EFLAGS] in {
Dan Gohman91888f02007-07-31 20:11:57 +00001394def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001395 [(set GR8:$dst, (ineg GR8:$src)),
1396 (implicit EFLAGS)]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001397def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001398 [(set GR16:$dst, (ineg GR16:$src)),
1399 (implicit EFLAGS)]>, OpSize;
Dan Gohman91888f02007-07-31 20:11:57 +00001400def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001401 [(set GR32:$dst, (ineg GR32:$src)),
1402 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001403let isTwoAddress = 0 in {
Dan Gohman91888f02007-07-31 20:11:57 +00001404 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001405 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1406 (implicit EFLAGS)]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001407 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001408 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1409 (implicit EFLAGS)]>, OpSize;
Dan Gohman91888f02007-07-31 20:11:57 +00001410 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001411 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1412 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001413}
Evan Cheng55687072007-09-14 21:48:26 +00001414} // Defs = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001415
Evan Chengc6cee682009-01-21 02:09:05 +00001416// Match xor -1 to not. Favors these over a move imm + xor to save code size.
1417let AddedComplexity = 15 in {
Dan Gohman91888f02007-07-31 20:11:57 +00001418def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001419 [(set GR8:$dst, (not GR8:$src))]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001420def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001421 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
Dan Gohman91888f02007-07-31 20:11:57 +00001422def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001423 [(set GR32:$dst, (not GR32:$src))]>;
Evan Chengc6cee682009-01-21 02:09:05 +00001424}
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001425let isTwoAddress = 0 in {
Dan Gohman91888f02007-07-31 20:11:57 +00001426 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001427 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001428 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001429 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
Dan Gohman91888f02007-07-31 20:11:57 +00001430 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001431 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1432}
1433} // CodeSize
1434
1435// TODO: inc/dec is slow for P4, but fast for Pentium-M.
Evan Cheng55687072007-09-14 21:48:26 +00001436let Defs = [EFLAGS] in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001437let CodeSize = 2 in
Dan Gohman91888f02007-07-31 20:11:57 +00001438def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001439 [(set GR8:$dst, (add GR8:$src, 1)),
1440 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001441let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
Dan Gohman91888f02007-07-31 20:11:57 +00001442def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001443 [(set GR16:$dst, (add GR16:$src, 1)),
1444 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001445 OpSize, Requires<[In32BitMode]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001446def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001447 [(set GR32:$dst, (add GR32:$src, 1)),
1448 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001449}
1450let isTwoAddress = 0, CodeSize = 2 in {
Dan Gohman91888f02007-07-31 20:11:57 +00001451 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001452 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1453 (implicit EFLAGS)]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001454 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001455 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1456 (implicit EFLAGS)]>,
Evan Cheng4a7e72f2007-10-19 21:23:22 +00001457 OpSize, Requires<[In32BitMode]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001458 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001459 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1460 (implicit EFLAGS)]>,
Evan Cheng4a7e72f2007-10-19 21:23:22 +00001461 Requires<[In32BitMode]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001462}
1463
1464let CodeSize = 2 in
Dan Gohman91888f02007-07-31 20:11:57 +00001465def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001466 [(set GR8:$dst, (add GR8:$src, -1)),
1467 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001468let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
Dan Gohman91888f02007-07-31 20:11:57 +00001469def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001470 [(set GR16:$dst, (add GR16:$src, -1)),
1471 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001472 OpSize, Requires<[In32BitMode]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001473def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001474 [(set GR32:$dst, (add GR32:$src, -1)),
1475 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001476}
1477
1478let isTwoAddress = 0, CodeSize = 2 in {
Dan Gohman91888f02007-07-31 20:11:57 +00001479 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001480 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1481 (implicit EFLAGS)]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001482 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001483 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1484 (implicit EFLAGS)]>,
Evan Cheng4a7e72f2007-10-19 21:23:22 +00001485 OpSize, Requires<[In32BitMode]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001486 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001487 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1488 (implicit EFLAGS)]>,
Evan Cheng4a7e72f2007-10-19 21:23:22 +00001489 Requires<[In32BitMode]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001490}
Evan Cheng55687072007-09-14 21:48:26 +00001491} // Defs = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001492
1493// Logical operators...
Evan Cheng55687072007-09-14 21:48:26 +00001494let Defs = [EFLAGS] in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001495let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1496def AND8rr : I<0x20, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00001497 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001498 "and{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001499 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1500 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001501def AND16rr : I<0x21, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00001502 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001503 "and{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001504 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1505 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001506def AND32rr : I<0x21, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00001507 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001508 "and{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001509 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1510 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001511}
1512
1513def AND8rm : I<0x22, MRMSrcMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001514 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001515 "and{b}\t{$src2, $dst|$dst, $src2}",
Chris Lattner12208612009-04-10 00:16:23 +00001516 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001517 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001518def AND16rm : I<0x23, MRMSrcMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001519 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001520 "and{w}\t{$src2, $dst|$dst, $src2}",
Chris Lattner12208612009-04-10 00:16:23 +00001521 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001522 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001523def AND32rm : I<0x23, MRMSrcMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001524 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001525 "and{l}\t{$src2, $dst|$dst, $src2}",
Chris Lattner12208612009-04-10 00:16:23 +00001526 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001527 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001528
1529def AND8ri : Ii8<0x80, MRM4r,
Evan Chengb783fa32007-07-19 01:14:50 +00001530 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001531 "and{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001532 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1533 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001534def AND16ri : Ii16<0x81, MRM4r,
Evan Chengb783fa32007-07-19 01:14:50 +00001535 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001536 "and{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001537 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1538 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001539def AND32ri : Ii32<0x81, MRM4r,
Evan Chengb783fa32007-07-19 01:14:50 +00001540 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001541 "and{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001542 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1543 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001544def AND16ri8 : Ii8<0x83, MRM4r,
Evan Chengb783fa32007-07-19 01:14:50 +00001545 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001546 "and{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001547 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1548 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001549 OpSize;
1550def AND32ri8 : Ii8<0x83, MRM4r,
Evan Chengb783fa32007-07-19 01:14:50 +00001551 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001552 "and{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001553 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1554 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001555
1556let isTwoAddress = 0 in {
1557 def AND8mr : I<0x20, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001558 (outs), (ins i8mem :$dst, GR8 :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001559 "and{b}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001560 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1561 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001562 def AND16mr : I<0x21, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001563 (outs), (ins i16mem:$dst, GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001564 "and{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001565 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1566 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001567 OpSize;
1568 def AND32mr : I<0x21, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001569 (outs), (ins i32mem:$dst, GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001570 "and{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001571 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1572 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001573 def AND8mi : Ii8<0x80, MRM4m,
Evan Chengb783fa32007-07-19 01:14:50 +00001574 (outs), (ins i8mem :$dst, i8imm :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001575 "and{b}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001576 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1577 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001578 def AND16mi : Ii16<0x81, MRM4m,
Evan Chengb783fa32007-07-19 01:14:50 +00001579 (outs), (ins i16mem:$dst, i16imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001580 "and{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001581 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1582 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001583 OpSize;
1584 def AND32mi : Ii32<0x81, MRM4m,
Evan Chengb783fa32007-07-19 01:14:50 +00001585 (outs), (ins i32mem:$dst, i32imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001586 "and{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001587 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1588 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001589 def AND16mi8 : Ii8<0x83, MRM4m,
Evan Chengb783fa32007-07-19 01:14:50 +00001590 (outs), (ins i16mem:$dst, i16i8imm :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001591 "and{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001592 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1593 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001594 OpSize;
1595 def AND32mi8 : Ii8<0x83, MRM4m,
Evan Chengb783fa32007-07-19 01:14:50 +00001596 (outs), (ins i32mem:$dst, i32i8imm :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001597 "and{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001598 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1599 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001600}
1601
1602
1603let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
Evan Chengb783fa32007-07-19 01:14:50 +00001604def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001605 "or{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001606 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1607 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001608def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001609 "or{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001610 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1611 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001612def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001613 "or{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001614 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1615 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001616}
Evan Chengb783fa32007-07-19 01:14:50 +00001617def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001618 "or{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001619 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1620 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001621def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001622 "or{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001623 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1624 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001625def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001626 "or{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001627 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1628 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001629
Evan Chengb783fa32007-07-19 01:14:50 +00001630def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001631 "or{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001632 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1633 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001634def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001635 "or{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001636 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1637 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001638def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001639 "or{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001640 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1641 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001642
Evan Chengb783fa32007-07-19 01:14:50 +00001643def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001644 "or{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001645 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1646 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001647def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001648 "or{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001649 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1650 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001651let isTwoAddress = 0 in {
Evan Chengb783fa32007-07-19 01:14:50 +00001652 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001653 "or{b}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001654 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1655 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001656 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001657 "or{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001658 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1659 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001660 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001661 "or{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001662 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1663 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001664 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001665 "or{b}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001666 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1667 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001668 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001669 "or{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001670 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1671 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001672 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001673 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001674 "or{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001675 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1676 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001677 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001678 "or{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001679 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1680 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001681 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001682 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001683 "or{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001684 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1685 (implicit EFLAGS)]>;
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001686} // isTwoAddress = 0
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001687
1688
Evan Cheng6f26e8b2008-06-18 08:13:07 +00001689let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001690 def XOR8rr : I<0x30, MRMDestReg,
1691 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1692 "xor{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001693 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1694 (implicit EFLAGS)]>;
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001695 def XOR16rr : I<0x31, MRMDestReg,
1696 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1697 "xor{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001698 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1699 (implicit EFLAGS)]>, OpSize;
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001700 def XOR32rr : I<0x31, MRMDestReg,
1701 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1702 "xor{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001703 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1704 (implicit EFLAGS)]>;
Evan Cheng6f26e8b2008-06-18 08:13:07 +00001705} // isCommutable = 1
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001706
1707def XOR8rm : I<0x32, MRMSrcMem ,
Evan Chengb783fa32007-07-19 01:14:50 +00001708 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001709 "xor{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001710 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1711 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001712def XOR16rm : I<0x33, MRMSrcMem ,
Evan Chengb783fa32007-07-19 01:14:50 +00001713 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001714 "xor{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001715 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1716 (implicit EFLAGS)]>,
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001717 OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001718def XOR32rm : I<0x33, MRMSrcMem ,
Evan Chengb783fa32007-07-19 01:14:50 +00001719 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001720 "xor{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001721 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1722 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001723
Bill Wendlingbac38eb2008-05-29 03:46:36 +00001724def XOR8ri : Ii8<0x80, MRM6r,
1725 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1726 "xor{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001727 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1728 (implicit EFLAGS)]>;
Bill Wendlingbac38eb2008-05-29 03:46:36 +00001729def XOR16ri : Ii16<0x81, MRM6r,
1730 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1731 "xor{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001732 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
1733 (implicit EFLAGS)]>, OpSize;
Bill Wendlingbac38eb2008-05-29 03:46:36 +00001734def XOR32ri : Ii32<0x81, MRM6r,
1735 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1736 "xor{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001737 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
1738 (implicit EFLAGS)]>;
Bill Wendlingbac38eb2008-05-29 03:46:36 +00001739def XOR16ri8 : Ii8<0x83, MRM6r,
1740 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1741 "xor{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001742 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
1743 (implicit EFLAGS)]>,
Bill Wendlingbac38eb2008-05-29 03:46:36 +00001744 OpSize;
1745def XOR32ri8 : Ii8<0x83, MRM6r,
1746 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1747 "xor{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001748 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
1749 (implicit EFLAGS)]>;
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001750
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001751let isTwoAddress = 0 in {
1752 def XOR8mr : I<0x30, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001753 (outs), (ins i8mem :$dst, GR8 :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001754 "xor{b}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001755 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1756 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001757 def XOR16mr : I<0x31, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001758 (outs), (ins i16mem:$dst, GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001759 "xor{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001760 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1761 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001762 OpSize;
1763 def XOR32mr : I<0x31, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001764 (outs), (ins i32mem:$dst, GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001765 "xor{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001766 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1767 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001768 def XOR8mi : Ii8<0x80, MRM6m,
Evan Chengb783fa32007-07-19 01:14:50 +00001769 (outs), (ins i8mem :$dst, i8imm :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001770 "xor{b}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001771 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1772 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001773 def XOR16mi : Ii16<0x81, MRM6m,
Evan Chengb783fa32007-07-19 01:14:50 +00001774 (outs), (ins i16mem:$dst, i16imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001775 "xor{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001776 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1777 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001778 OpSize;
1779 def XOR32mi : Ii32<0x81, MRM6m,
Evan Chengb783fa32007-07-19 01:14:50 +00001780 (outs), (ins i32mem:$dst, i32imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001781 "xor{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001782 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1783 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001784 def XOR16mi8 : Ii8<0x83, MRM6m,
Evan Chengb783fa32007-07-19 01:14:50 +00001785 (outs), (ins i16mem:$dst, i16i8imm :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001786 "xor{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001787 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1788 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001789 OpSize;
1790 def XOR32mi8 : Ii8<0x83, MRM6m,
Evan Chengb783fa32007-07-19 01:14:50 +00001791 (outs), (ins i32mem:$dst, i32i8imm :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001792 "xor{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001793 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1794 (implicit EFLAGS)]>;
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001795} // isTwoAddress = 0
Evan Cheng55687072007-09-14 21:48:26 +00001796} // Defs = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001797
1798// Shift instructions
Evan Cheng55687072007-09-14 21:48:26 +00001799let Defs = [EFLAGS] in {
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001800let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00001801def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
Eli Friedman378ea832009-06-19 04:48:38 +00001802 "shl{b}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001803 [(set GR8:$dst, (shl GR8:$src, CL))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001804def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
Eli Friedman378ea832009-06-19 04:48:38 +00001805 "shl{w}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001806 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001807def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
Eli Friedman378ea832009-06-19 04:48:38 +00001808 "shl{l}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001809 [(set GR32:$dst, (shl GR32:$src, CL))]>;
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001810} // Uses = [CL]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001811
Evan Chengb783fa32007-07-19 01:14:50 +00001812def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001813 "shl{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001814 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1815let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
Evan Chengb783fa32007-07-19 01:14:50 +00001816def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001817 "shl{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001818 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001819def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001820 "shl{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001821 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
Chris Lattnerf4005a82008-01-11 18:00:50 +00001822// NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1823// cheaper.
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001824} // isConvertibleToThreeAddress = 1
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001825
1826let isTwoAddress = 0 in {
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001827 let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00001828 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
Eli Friedman378ea832009-06-19 04:48:38 +00001829 "shl{b}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001830 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001831 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
Eli Friedman378ea832009-06-19 04:48:38 +00001832 "shl{w}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001833 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001834 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
Eli Friedman378ea832009-06-19 04:48:38 +00001835 "shl{l}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001836 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1837 }
Evan Chengb783fa32007-07-19 01:14:50 +00001838 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001839 "shl{b}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001840 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001841 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001842 "shl{w}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001843 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1844 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001845 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001846 "shl{l}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001847 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1848
1849 // Shift by 1
Evan Chengb783fa32007-07-19 01:14:50 +00001850 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001851 "shl{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001852 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001853 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001854 "shl{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001855 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1856 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001857 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001858 "shl{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001859 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1860}
1861
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001862let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00001863def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
Eli Friedman378ea832009-06-19 04:48:38 +00001864 "shr{b}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001865 [(set GR8:$dst, (srl GR8:$src, CL))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001866def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
Eli Friedman378ea832009-06-19 04:48:38 +00001867 "shr{w}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001868 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001869def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
Eli Friedman378ea832009-06-19 04:48:38 +00001870 "shr{l}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001871 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1872}
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001873
Evan Chengb783fa32007-07-19 01:14:50 +00001874def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001875 "shr{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001876 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001877def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001878 "shr{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001879 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001880def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001881 "shr{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001882 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1883
1884// Shift by 1
Evan Chengb783fa32007-07-19 01:14:50 +00001885def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001886 "shr{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001887 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001888def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001889 "shr{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001890 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001891def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001892 "shr{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001893 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1894
1895let isTwoAddress = 0 in {
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001896 let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00001897 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
Eli Friedman378ea832009-06-19 04:48:38 +00001898 "shr{b}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001899 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001900 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
Eli Friedman378ea832009-06-19 04:48:38 +00001901 "shr{w}\t{%cl, $dst|$dst, CL}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001902 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001903 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001904 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
Eli Friedman378ea832009-06-19 04:48:38 +00001905 "shr{l}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001906 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1907 }
Evan Chengb783fa32007-07-19 01:14:50 +00001908 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001909 "shr{b}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001910 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001911 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001912 "shr{w}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001913 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1914 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001915 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001916 "shr{l}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001917 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1918
1919 // Shift by 1
Evan Chengb783fa32007-07-19 01:14:50 +00001920 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001921 "shr{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001922 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001923 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001924 "shr{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001925 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001926 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001927 "shr{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001928 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1929}
1930
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001931let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00001932def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
Eli Friedman378ea832009-06-19 04:48:38 +00001933 "sar{b}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001934 [(set GR8:$dst, (sra GR8:$src, CL))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001935def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
Eli Friedman378ea832009-06-19 04:48:38 +00001936 "sar{w}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001937 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001938def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
Eli Friedman378ea832009-06-19 04:48:38 +00001939 "sar{l}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001940 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1941}
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001942
Evan Chengb783fa32007-07-19 01:14:50 +00001943def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001944 "sar{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001945 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001946def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001947 "sar{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001948 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1949 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001950def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001951 "sar{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001952 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1953
1954// Shift by 1
Evan Chengb783fa32007-07-19 01:14:50 +00001955def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001956 "sar{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001957 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001958def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001959 "sar{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001960 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001961def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001962 "sar{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001963 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1964
1965let isTwoAddress = 0 in {
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001966 let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00001967 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
Eli Friedman378ea832009-06-19 04:48:38 +00001968 "sar{b}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001969 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001970 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
Eli Friedman378ea832009-06-19 04:48:38 +00001971 "sar{w}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001972 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001973 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
Eli Friedman378ea832009-06-19 04:48:38 +00001974 "sar{l}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001975 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1976 }
Evan Chengb783fa32007-07-19 01:14:50 +00001977 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001978 "sar{b}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001979 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001980 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001981 "sar{w}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001982 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1983 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001984 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001985 "sar{l}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001986 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1987
1988 // Shift by 1
Evan Chengb783fa32007-07-19 01:14:50 +00001989 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001990 "sar{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001991 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001992 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001993 "sar{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001994 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1995 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001996 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001997 "sar{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001998 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1999}
2000
2001// Rotate instructions
2002// FIXME: provide shorter instructions when imm8 == 1
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002003let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00002004def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
Eli Friedman378ea832009-06-19 04:48:38 +00002005 "rol{b}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002006 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002007def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
Eli Friedman378ea832009-06-19 04:48:38 +00002008 "rol{w}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002009 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002010def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
Eli Friedman378ea832009-06-19 04:48:38 +00002011 "rol{l}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002012 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2013}
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002014
Evan Chengb783fa32007-07-19 01:14:50 +00002015def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002016 "rol{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002017 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002018def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002019 "rol{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002020 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002021def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002022 "rol{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002023 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2024
2025// Rotate by 1
Evan Chengb783fa32007-07-19 01:14:50 +00002026def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00002027 "rol{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002028 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002029def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00002030 "rol{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002031 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002032def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00002033 "rol{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002034 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2035
2036let isTwoAddress = 0 in {
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002037 let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00002038 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
Eli Friedman378ea832009-06-19 04:48:38 +00002039 "rol{b}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002040 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002041 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
Eli Friedman378ea832009-06-19 04:48:38 +00002042 "rol{w}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002043 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002044 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
Eli Friedman378ea832009-06-19 04:48:38 +00002045 "rol{l}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002046 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2047 }
Evan Chengb783fa32007-07-19 01:14:50 +00002048 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002049 "rol{b}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002050 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002051 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002052 "rol{w}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002053 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2054 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002055 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002056 "rol{l}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002057 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2058
2059 // Rotate by 1
Evan Chengb783fa32007-07-19 01:14:50 +00002060 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002061 "rol{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002062 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002063 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002064 "rol{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002065 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2066 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002067 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002068 "rol{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002069 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2070}
2071
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002072let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00002073def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
Eli Friedman378ea832009-06-19 04:48:38 +00002074 "ror{b}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002075 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002076def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
Eli Friedman378ea832009-06-19 04:48:38 +00002077 "ror{w}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002078 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002079def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
Eli Friedman378ea832009-06-19 04:48:38 +00002080 "ror{l}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002081 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2082}
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002083
Evan Chengb783fa32007-07-19 01:14:50 +00002084def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002085 "ror{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002086 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002087def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002088 "ror{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002089 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002090def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002091 "ror{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002092 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2093
2094// Rotate by 1
Evan Chengb783fa32007-07-19 01:14:50 +00002095def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00002096 "ror{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002097 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002098def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00002099 "ror{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002100 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002101def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00002102 "ror{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002103 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2104
2105let isTwoAddress = 0 in {
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002106 let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00002107 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
Eli Friedman378ea832009-06-19 04:48:38 +00002108 "ror{b}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002109 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002110 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
Eli Friedman378ea832009-06-19 04:48:38 +00002111 "ror{w}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002112 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002113 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
Eli Friedman378ea832009-06-19 04:48:38 +00002114 "ror{l}\t{%cl, $dst|$dst, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002115 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2116 }
Evan Chengb783fa32007-07-19 01:14:50 +00002117 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002118 "ror{b}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002119 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002120 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002121 "ror{w}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002122 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2123 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002124 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002125 "ror{l}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002126 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2127
2128 // Rotate by 1
Evan Chengb783fa32007-07-19 01:14:50 +00002129 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002130 "ror{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002131 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002132 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002133 "ror{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002134 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2135 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002136 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002137 "ror{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002138 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2139}
2140
2141
2142
2143// Double shift instructions (generalizations of rotate)
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002144let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00002145def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Eli Friedman378ea832009-06-19 04:48:38 +00002146 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002147 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00002148def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Eli Friedman378ea832009-06-19 04:48:38 +00002149 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002150 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00002151def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Eli Friedman378ea832009-06-19 04:48:38 +00002152 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002153 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002154 TB, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002155def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Eli Friedman378ea832009-06-19 04:48:38 +00002156 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002157 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002158 TB, OpSize;
2159}
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002160
2161let isCommutable = 1 in { // These instructions commute to each other.
2162def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00002163 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
Dan Gohman91888f02007-07-31 20:11:57 +00002164 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002165 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2166 (i8 imm:$src3)))]>,
2167 TB;
2168def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00002169 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
Dan Gohman91888f02007-07-31 20:11:57 +00002170 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002171 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2172 (i8 imm:$src3)))]>,
2173 TB;
2174def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00002175 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
Dan Gohman91888f02007-07-31 20:11:57 +00002176 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002177 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2178 (i8 imm:$src3)))]>,
2179 TB, OpSize;
2180def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00002181 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
Dan Gohman91888f02007-07-31 20:11:57 +00002182 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002183 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2184 (i8 imm:$src3)))]>,
2185 TB, OpSize;
2186}
2187
2188let isTwoAddress = 0 in {
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002189 let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00002190 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Eli Friedman378ea832009-06-19 04:48:38 +00002191 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002192 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002193 addr:$dst)]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00002194 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Eli Friedman378ea832009-06-19 04:48:38 +00002195 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002196 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002197 addr:$dst)]>, TB;
2198 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002199 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002200 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
Dan Gohman91888f02007-07-31 20:11:57 +00002201 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002202 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2203 (i8 imm:$src3)), addr:$dst)]>,
2204 TB;
2205 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002206 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
Dan Gohman91888f02007-07-31 20:11:57 +00002207 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002208 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2209 (i8 imm:$src3)), addr:$dst)]>,
2210 TB;
2211
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002212 let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00002213 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
Eli Friedman378ea832009-06-19 04:48:38 +00002214 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002215 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002216 addr:$dst)]>, TB, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002217 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
Eli Friedman378ea832009-06-19 04:48:38 +00002218 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002219 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002220 addr:$dst)]>, TB, OpSize;
2221 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002222 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002223 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
Dan Gohman91888f02007-07-31 20:11:57 +00002224 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002225 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2226 (i8 imm:$src3)), addr:$dst)]>,
2227 TB, OpSize;
2228 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002229 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
Dan Gohman91888f02007-07-31 20:11:57 +00002230 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002231 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2232 (i8 imm:$src3)), addr:$dst)]>,
2233 TB, OpSize;
2234}
Evan Cheng55687072007-09-14 21:48:26 +00002235} // Defs = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002236
2237
2238// Arithmetic.
Evan Cheng55687072007-09-14 21:48:26 +00002239let Defs = [EFLAGS] in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002240let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
Bill Wendlingae034ed2008-12-12 00:56:36 +00002241// Register-Register Addition
2242def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2243 (ins GR8 :$src1, GR8 :$src2),
2244 "add{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002245 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
Bill Wendlingae034ed2008-12-12 00:56:36 +00002246 (implicit EFLAGS)]>;
2247
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002248let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
Bill Wendlingae034ed2008-12-12 00:56:36 +00002249// Register-Register Addition
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002250def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2251 (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002252 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002253 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2254 (implicit EFLAGS)]>, OpSize;
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002255def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2256 (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002257 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002258 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2259 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002260} // end isConvertibleToThreeAddress
2261} // end isCommutable
Bill Wendlingae034ed2008-12-12 00:56:36 +00002262
2263// Register-Memory Addition
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002264def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2265 (ins GR8 :$src1, i8mem :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002266 "add{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002267 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2268 (implicit EFLAGS)]>;
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002269def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2270 (ins GR16:$src1, i16mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002271 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002272 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2273 (implicit EFLAGS)]>, OpSize;
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002274def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2275 (ins GR32:$src1, i32mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002276 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002277 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2278 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002279
Bill Wendlingae034ed2008-12-12 00:56:36 +00002280// Register-Integer Addition
2281def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2282 "add{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002283 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2284 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002285
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002286let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
Bill Wendlingae034ed2008-12-12 00:56:36 +00002287// Register-Integer Addition
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002288def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2289 (ins GR16:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002290 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002291 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2292 (implicit EFLAGS)]>, OpSize;
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002293def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2294 (ins GR32:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002295 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002296 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2297 (implicit EFLAGS)]>;
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002298def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2299 (ins GR16:$src1, i16i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002300 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002301 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2302 (implicit EFLAGS)]>, OpSize;
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002303def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2304 (ins GR32:$src1, i32i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002305 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002306 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2307 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002308}
2309
2310let isTwoAddress = 0 in {
Bill Wendlingae034ed2008-12-12 00:56:36 +00002311 // Memory-Register Addition
Bill Wendlingf5399032008-12-12 21:15:41 +00002312 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002313 "add{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002314 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2315 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002316 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002317 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002318 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2319 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002320 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002321 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002322 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2323 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002324 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002325 "add{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002326 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2327 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002328 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002329 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002330 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2331 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002332 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002333 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002334 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2335 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002336 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002337 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002338 [(store (add (load addr:$dst), i16immSExt8:$src2),
2339 addr:$dst),
2340 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002341 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002342 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingae034ed2008-12-12 00:56:36 +00002343 [(store (add (load addr:$dst), i32immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00002344 addr:$dst),
2345 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002346}
2347
Evan Cheng259471d2007-10-05 17:59:57 +00002348let Uses = [EFLAGS] in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002349let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
Dale Johannesen747fe522009-06-02 03:12:52 +00002350def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
Dale Johannesen06b83f12009-05-18 17:44:15 +00002351 "adc{b}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002352 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002353def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2354 (ins GR16:$src1, GR16:$src2),
2355 "adc{w}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002356 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002357def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2358 (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002359 "adc{l}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002360 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002361}
Dale Johannesen06b83f12009-05-18 17:44:15 +00002362def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2363 (ins GR8:$src1, i8mem:$src2),
2364 "adc{b}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002365 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002366def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2367 (ins GR16:$src1, i16mem:$src2),
2368 "adc{w}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002369 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
Dale Johannesen067cfb22009-05-18 21:41:59 +00002370 OpSize;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002371def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2372 (ins GR32:$src1, i32mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002373 "adc{l}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002374 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2375def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
Dale Johannesen06b83f12009-05-18 17:44:15 +00002376 "adc{b}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002377 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002378def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2379 (ins GR16:$src1, i16imm:$src2),
2380 "adc{w}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002381 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002382def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2383 (ins GR16:$src1, i16i8imm:$src2),
2384 "adc{w}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002385 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2386 OpSize;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002387def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2388 (ins GR32:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002389 "adc{l}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002390 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002391def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2392 (ins GR32:$src1, i32i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002393 "adc{l}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002394 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002395
2396let isTwoAddress = 0 in {
Dale Johannesen747fe522009-06-02 03:12:52 +00002397 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
Dale Johannesen06b83f12009-05-18 17:44:15 +00002398 "adc{b}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002399 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2400 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
Dale Johannesen06b83f12009-05-18 17:44:15 +00002401 "adc{w}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002402 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2403 OpSize;
2404 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002405 "adc{l}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002406 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2407 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
Dale Johannesen06b83f12009-05-18 17:44:15 +00002408 "adc{b}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002409 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2410 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
Dale Johannesen06b83f12009-05-18 17:44:15 +00002411 "adc{w}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002412 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2413 OpSize;
2414 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
Dale Johannesen06b83f12009-05-18 17:44:15 +00002415 "adc{w}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002416 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2417 OpSize;
2418 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002419 "adc{l}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002420 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2421 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002422 "adc{l}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002423 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2424}
Evan Cheng259471d2007-10-05 17:59:57 +00002425} // Uses = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002426
Bill Wendlingae034ed2008-12-12 00:56:36 +00002427// Register-Register Subtraction
2428def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2429 "sub{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002430 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2431 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002432def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2433 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002434 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2435 (implicit EFLAGS)]>, OpSize;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002436def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2437 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002438 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2439 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002440
2441// Register-Memory Subtraction
2442def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2443 (ins GR8 :$src1, i8mem :$src2),
2444 "sub{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002445 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2446 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002447def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2448 (ins GR16:$src1, i16mem:$src2),
2449 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002450 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2451 (implicit EFLAGS)]>, OpSize;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002452def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2453 (ins GR32:$src1, i32mem:$src2),
2454 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002455 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2456 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002457
2458// Register-Integer Subtraction
2459def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2460 (ins GR8:$src1, i8imm:$src2),
2461 "sub{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002462 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2463 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002464def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2465 (ins GR16:$src1, i16imm:$src2),
2466 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002467 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2468 (implicit EFLAGS)]>, OpSize;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002469def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2470 (ins GR32:$src1, i32imm:$src2),
2471 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002472 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2473 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002474def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2475 (ins GR16:$src1, i16i8imm:$src2),
2476 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002477 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2478 (implicit EFLAGS)]>, OpSize;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002479def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2480 (ins GR32:$src1, i32i8imm:$src2),
2481 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002482 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2483 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002484
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002485let isTwoAddress = 0 in {
Bill Wendlingae034ed2008-12-12 00:56:36 +00002486 // Memory-Register Subtraction
Evan Chengb783fa32007-07-19 01:14:50 +00002487 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002488 "sub{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002489 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2490 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002491 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002492 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002493 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2494 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002495 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002496 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002497 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2498 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002499
2500 // Memory-Integer Subtraction
Evan Chengb783fa32007-07-19 01:14:50 +00002501 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002502 "sub{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002503 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2504 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002505 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002506 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002507 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2508 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002509 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002510 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002511 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2512 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002513 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002514 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingae034ed2008-12-12 00:56:36 +00002515 [(store (sub (load addr:$dst), i16immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00002516 addr:$dst),
2517 (implicit EFLAGS)]>, OpSize;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002518 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002519 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingae034ed2008-12-12 00:56:36 +00002520 [(store (sub (load addr:$dst), i32immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00002521 addr:$dst),
2522 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002523}
2524
Evan Cheng259471d2007-10-05 17:59:57 +00002525let Uses = [EFLAGS] in {
Dale Johannesen06b83f12009-05-18 17:44:15 +00002526def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2527 (ins GR8:$src1, GR8:$src2),
2528 "sbb{b}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002529 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002530def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2531 (ins GR16:$src1, GR16:$src2),
2532 "sbb{w}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002533 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002534def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2535 (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002536 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002537 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002538
2539let isTwoAddress = 0 in {
Dale Johannesen06b83f12009-05-18 17:44:15 +00002540 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2541 "sbb{b}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002542 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002543 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2544 "sbb{w}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002545 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
Dale Johannesen067cfb22009-05-18 21:41:59 +00002546 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002547 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002548 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002549 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002550 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002551 "sbb{b}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002552 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002553 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2554 "sbb{w}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002555 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
Dale Johannesen067cfb22009-05-18 21:41:59 +00002556 OpSize;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002557 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2558 "sbb{w}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002559 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
Dale Johannesen067cfb22009-05-18 21:41:59 +00002560 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002561 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002562 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002563 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002564 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002565 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002566 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002567}
Dale Johannesen06b83f12009-05-18 17:44:15 +00002568def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
2569 "sbb{b}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002570 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002571def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
2572 (ins GR16:$src1, i16mem:$src2),
2573 "sbb{w}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002574 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
Dale Johannesen067cfb22009-05-18 21:41:59 +00002575 OpSize;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002576def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
2577 (ins GR32:$src1, i32mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002578 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002579 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002580def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2581 "sbb{b}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002582 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002583def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
2584 (ins GR16:$src1, i16imm:$src2),
2585 "sbb{w}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002586 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002587def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
2588 (ins GR16:$src1, i16i8imm:$src2),
2589 "sbb{w}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002590 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
2591 OpSize;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002592def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
2593 (ins GR32:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002594 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002595 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
Dale Johannesen06b83f12009-05-18 17:44:15 +00002596def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
2597 (ins GR32:$src1, i32i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002598 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Dale Johannesen747fe522009-06-02 03:12:52 +00002599 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
Evan Cheng259471d2007-10-05 17:59:57 +00002600} // Uses = [EFLAGS]
Evan Cheng55687072007-09-14 21:48:26 +00002601} // Defs = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002602
Evan Cheng55687072007-09-14 21:48:26 +00002603let Defs = [EFLAGS] in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002604let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
Bill Wendlingf5399032008-12-12 21:15:41 +00002605// Register-Register Signed Integer Multiply
Bill Wendlingae034ed2008-12-12 00:56:36 +00002606def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002607 "imul{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002608 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2609 (implicit EFLAGS)]>, TB, OpSize;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002610def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002611 "imul{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002612 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2613 (implicit EFLAGS)]>, TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002614}
Bill Wendlingae034ed2008-12-12 00:56:36 +00002615
Bill Wendlingf5399032008-12-12 21:15:41 +00002616// Register-Memory Signed Integer Multiply
Bill Wendlingae034ed2008-12-12 00:56:36 +00002617def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2618 (ins GR16:$src1, i16mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002619 "imul{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002620 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2621 (implicit EFLAGS)]>, TB, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002622def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002623 "imul{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002624 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2625 (implicit EFLAGS)]>, TB;
Evan Cheng55687072007-09-14 21:48:26 +00002626} // Defs = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002627} // end Two Address instructions
2628
2629// Suprisingly enough, these are not two address instructions!
Evan Cheng55687072007-09-14 21:48:26 +00002630let Defs = [EFLAGS] in {
Bill Wendlingf5399032008-12-12 21:15:41 +00002631// Register-Integer Signed Integer Multiply
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002632def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
Evan Chengb783fa32007-07-19 01:14:50 +00002633 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002634 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002635 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2636 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002637def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
Evan Chengb783fa32007-07-19 01:14:50 +00002638 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002639 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002640 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2641 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002642def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
Evan Chengb783fa32007-07-19 01:14:50 +00002643 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002644 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002645 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2646 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002647def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
Evan Chengb783fa32007-07-19 01:14:50 +00002648 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002649 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002650 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2651 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002652
Bill Wendlingf5399032008-12-12 21:15:41 +00002653// Memory-Integer Signed Integer Multiply
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002654def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
Evan Chengb783fa32007-07-19 01:14:50 +00002655 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002656 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002657 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2658 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002659def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
Evan Chengb783fa32007-07-19 01:14:50 +00002660 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002661 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002662 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2663 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002664def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
Evan Chengb783fa32007-07-19 01:14:50 +00002665 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002666 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingae034ed2008-12-12 00:56:36 +00002667 [(set GR16:$dst, (mul (load addr:$src1),
Bill Wendlingf5399032008-12-12 21:15:41 +00002668 i16immSExt8:$src2)),
2669 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002670def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
Evan Chengb783fa32007-07-19 01:14:50 +00002671 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002672 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingae034ed2008-12-12 00:56:36 +00002673 [(set GR32:$dst, (mul (load addr:$src1),
Bill Wendlingf5399032008-12-12 21:15:41 +00002674 i32immSExt8:$src2)),
2675 (implicit EFLAGS)]>;
Evan Cheng55687072007-09-14 21:48:26 +00002676} // Defs = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002677
2678//===----------------------------------------------------------------------===//
2679// Test instructions are just like AND, except they don't generate a result.
2680//
Evan Cheng950aac02007-09-25 01:57:46 +00002681let Defs = [EFLAGS] in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002682let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
Evan Chengb783fa32007-07-19 01:14:50 +00002683def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
Evan Cheng621216e2007-09-29 00:00:36 +00002684 "test{b}\t{$src2, $src1|$src1, $src2}",
Chris Lattner21da6382008-02-19 17:37:35 +00002685 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
Evan Cheng621216e2007-09-29 00:00:36 +00002686 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002687def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
Evan Cheng621216e2007-09-29 00:00:36 +00002688 "test{w}\t{$src2, $src1|$src1, $src2}",
Chris Lattner21da6382008-02-19 17:37:35 +00002689 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
Evan Cheng621216e2007-09-29 00:00:36 +00002690 (implicit EFLAGS)]>,
2691 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002692def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
Evan Cheng621216e2007-09-29 00:00:36 +00002693 "test{l}\t{$src2, $src1|$src1, $src2}",
Chris Lattner21da6382008-02-19 17:37:35 +00002694 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
Evan Cheng621216e2007-09-29 00:00:36 +00002695 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002696}
2697
Evan Chengb783fa32007-07-19 01:14:50 +00002698def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
Evan Cheng621216e2007-09-29 00:00:36 +00002699 "test{b}\t{$src2, $src1|$src1, $src2}",
2700 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2701 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002702def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
Evan Cheng621216e2007-09-29 00:00:36 +00002703 "test{w}\t{$src2, $src1|$src1, $src2}",
2704 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2705 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002706def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
Evan Cheng621216e2007-09-29 00:00:36 +00002707 "test{l}\t{$src2, $src1|$src1, $src2}",
2708 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2709 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002710
2711def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
Evan Chengb783fa32007-07-19 01:14:50 +00002712 (outs), (ins GR8:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002713 "test{b}\t{$src2, $src1|$src1, $src2}",
Chris Lattner21da6382008-02-19 17:37:35 +00002714 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
Evan Cheng621216e2007-09-29 00:00:36 +00002715 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002716def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
Evan Chengb783fa32007-07-19 01:14:50 +00002717 (outs), (ins GR16:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002718 "test{w}\t{$src2, $src1|$src1, $src2}",
Chris Lattner21da6382008-02-19 17:37:35 +00002719 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
Evan Cheng621216e2007-09-29 00:00:36 +00002720 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002721def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
Evan Chengb783fa32007-07-19 01:14:50 +00002722 (outs), (ins GR32:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002723 "test{l}\t{$src2, $src1|$src1, $src2}",
Chris Lattner21da6382008-02-19 17:37:35 +00002724 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
Evan Cheng621216e2007-09-29 00:00:36 +00002725 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002726
Evan Cheng621216e2007-09-29 00:00:36 +00002727def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
Evan Chengb783fa32007-07-19 01:14:50 +00002728 (outs), (ins i8mem:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002729 "test{b}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002730 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2731 (implicit EFLAGS)]>;
2732def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
Evan Chengb783fa32007-07-19 01:14:50 +00002733 (outs), (ins i16mem:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002734 "test{w}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002735 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2736 (implicit EFLAGS)]>, OpSize;
2737def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
Evan Chengb783fa32007-07-19 01:14:50 +00002738 (outs), (ins i32mem:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002739 "test{l}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002740 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
Evan Cheng950aac02007-09-25 01:57:46 +00002741 (implicit EFLAGS)]>;
2742} // Defs = [EFLAGS]
2743
2744
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002745// Condition code ops, incl. set if equal/not equal/...
Chris Lattnerc90ee9c2008-01-10 07:59:24 +00002746let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002747def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
Chris Lattnerc90ee9c2008-01-10 07:59:24 +00002748let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002749def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002750
Evan Cheng950aac02007-09-25 01:57:46 +00002751let Uses = [EFLAGS] in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002752def SETEr : I<0x94, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002753 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002754 "sete\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002755 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002756 TB; // GR8 = ==
2757def SETEm : I<0x94, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002758 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002759 "sete\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002760 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002761 TB; // [mem8] = ==
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002762
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002763def SETNEr : I<0x95, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002764 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002765 "setne\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002766 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002767 TB; // GR8 = !=
2768def SETNEm : I<0x95, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002769 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002770 "setne\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002771 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002772 TB; // [mem8] = !=
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002773
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002774def SETLr : I<0x9C, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002775 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002776 "setl\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002777 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002778 TB; // GR8 = < signed
2779def SETLm : I<0x9C, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002780 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002781 "setl\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002782 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002783 TB; // [mem8] = < signed
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002784
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002785def SETGEr : I<0x9D, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002786 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002787 "setge\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002788 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002789 TB; // GR8 = >= signed
2790def SETGEm : I<0x9D, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002791 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002792 "setge\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002793 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002794 TB; // [mem8] = >= signed
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002795
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002796def SETLEr : I<0x9E, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002797 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002798 "setle\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002799 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002800 TB; // GR8 = <= signed
2801def SETLEm : I<0x9E, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002802 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002803 "setle\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002804 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002805 TB; // [mem8] = <= signed
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002806
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002807def SETGr : I<0x9F, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002808 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002809 "setg\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002810 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002811 TB; // GR8 = > signed
2812def SETGm : I<0x9F, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002813 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002814 "setg\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002815 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002816 TB; // [mem8] = > signed
2817
2818def SETBr : I<0x92, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002819 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002820 "setb\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002821 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002822 TB; // GR8 = < unsign
2823def SETBm : I<0x92, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002824 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002825 "setb\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002826 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002827 TB; // [mem8] = < unsign
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002828
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002829def SETAEr : I<0x93, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002830 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002831 "setae\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002832 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002833 TB; // GR8 = >= unsign
2834def SETAEm : I<0x93, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002835 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002836 "setae\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002837 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002838 TB; // [mem8] = >= unsign
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002839
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002840def SETBEr : I<0x96, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002841 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002842 "setbe\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002843 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002844 TB; // GR8 = <= unsign
2845def SETBEm : I<0x96, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002846 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002847 "setbe\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002848 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002849 TB; // [mem8] = <= unsign
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002850
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002851def SETAr : I<0x97, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002852 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002853 "seta\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002854 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002855 TB; // GR8 = > signed
2856def SETAm : I<0x97, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002857 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002858 "seta\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002859 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002860 TB; // [mem8] = > signed
2861
2862def SETSr : I<0x98, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002863 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002864 "sets\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002865 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002866 TB; // GR8 = <sign bit>
2867def SETSm : I<0x98, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002868 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002869 "sets\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002870 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002871 TB; // [mem8] = <sign bit>
2872def SETNSr : I<0x99, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002873 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002874 "setns\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002875 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002876 TB; // GR8 = !<sign bit>
2877def SETNSm : I<0x99, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002878 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002879 "setns\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002880 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002881 TB; // [mem8] = !<sign bit>
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002882
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002883def SETPr : I<0x9A, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002884 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002885 "setp\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002886 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002887 TB; // GR8 = parity
2888def SETPm : I<0x9A, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002889 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002890 "setp\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002891 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002892 TB; // [mem8] = parity
2893def SETNPr : I<0x9B, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002894 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002895 "setnp\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002896 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002897 TB; // GR8 = not parity
2898def SETNPm : I<0x9B, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002899 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002900 "setnp\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002901 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002902 TB; // [mem8] = not parity
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002903
2904def SETOr : I<0x90, MRM0r,
2905 (outs GR8 :$dst), (ins),
2906 "seto\t$dst",
2907 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
2908 TB; // GR8 = overflow
2909def SETOm : I<0x90, MRM0m,
2910 (outs), (ins i8mem:$dst),
2911 "seto\t$dst",
2912 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
2913 TB; // [mem8] = overflow
2914def SETNOr : I<0x91, MRM0r,
2915 (outs GR8 :$dst), (ins),
2916 "setno\t$dst",
2917 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
2918 TB; // GR8 = not overflow
2919def SETNOm : I<0x91, MRM0m,
2920 (outs), (ins i8mem:$dst),
2921 "setno\t$dst",
2922 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
2923 TB; // [mem8] = not overflow
Evan Cheng950aac02007-09-25 01:57:46 +00002924} // Uses = [EFLAGS]
2925
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002926
2927// Integer comparisons
Evan Cheng55687072007-09-14 21:48:26 +00002928let Defs = [EFLAGS] in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002929def CMP8rr : I<0x38, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00002930 (outs), (ins GR8 :$src1, GR8 :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002931 "cmp{b}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002932 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002933def CMP16rr : I<0x39, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00002934 (outs), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002935 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002936 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002937def CMP32rr : I<0x39, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00002938 (outs), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002939 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002940 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002941def CMP8mr : I<0x38, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002942 (outs), (ins i8mem :$src1, GR8 :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002943 "cmp{b}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002944 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2945 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002946def CMP16mr : I<0x39, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002947 (outs), (ins i16mem:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002948 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002949 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2950 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002951def CMP32mr : I<0x39, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002952 (outs), (ins i32mem:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002953 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002954 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2955 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002956def CMP8rm : I<0x3A, MRMSrcMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002957 (outs), (ins GR8 :$src1, i8mem :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002958 "cmp{b}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002959 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2960 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002961def CMP16rm : I<0x3B, MRMSrcMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002962 (outs), (ins GR16:$src1, i16mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002963 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002964 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2965 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002966def CMP32rm : I<0x3B, MRMSrcMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002967 (outs), (ins GR32:$src1, i32mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002968 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002969 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2970 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002971def CMP8ri : Ii8<0x80, MRM7r,
Evan Chengb783fa32007-07-19 01:14:50 +00002972 (outs), (ins GR8:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002973 "cmp{b}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002974 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002975def CMP16ri : Ii16<0x81, MRM7r,
Evan Chengb783fa32007-07-19 01:14:50 +00002976 (outs), (ins GR16:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002977 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002978 [(X86cmp GR16:$src1, imm:$src2),
2979 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002980def CMP32ri : Ii32<0x81, MRM7r,
Evan Chengb783fa32007-07-19 01:14:50 +00002981 (outs), (ins GR32:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002982 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002983 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002984def CMP8mi : Ii8 <0x80, MRM7m,
Evan Chengb783fa32007-07-19 01:14:50 +00002985 (outs), (ins i8mem :$src1, i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002986 "cmp{b}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002987 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2988 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002989def CMP16mi : Ii16<0x81, MRM7m,
Evan Chengb783fa32007-07-19 01:14:50 +00002990 (outs), (ins i16mem:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002991 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002992 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2993 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002994def CMP32mi : Ii32<0x81, MRM7m,
Evan Chengb783fa32007-07-19 01:14:50 +00002995 (outs), (ins i32mem:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002996 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002997 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2998 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002999def CMP16ri8 : Ii8<0x83, MRM7r,
Evan Chengb783fa32007-07-19 01:14:50 +00003000 (outs), (ins GR16:$src1, i16i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00003001 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00003002 [(X86cmp GR16:$src1, i16immSExt8:$src2),
3003 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003004def CMP16mi8 : Ii8<0x83, MRM7m,
Evan Chengb783fa32007-07-19 01:14:50 +00003005 (outs), (ins i16mem:$src1, i16i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00003006 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00003007 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
3008 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003009def CMP32mi8 : Ii8<0x83, MRM7m,
Evan Chengb783fa32007-07-19 01:14:50 +00003010 (outs), (ins i32mem:$src1, i32i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00003011 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00003012 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
3013 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003014def CMP32ri8 : Ii8<0x83, MRM7r,
Evan Chengb783fa32007-07-19 01:14:50 +00003015 (outs), (ins GR32:$src1, i32i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00003016 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00003017 [(X86cmp GR32:$src1, i32immSExt8:$src2),
Evan Cheng950aac02007-09-25 01:57:46 +00003018 (implicit EFLAGS)]>;
3019} // Defs = [EFLAGS]
3020
Dan Gohman7fe9b7f2008-12-23 22:45:23 +00003021// Bit tests.
Dan Gohman7fe9b7f2008-12-23 22:45:23 +00003022// TODO: BTC, BTR, and BTS
3023let Defs = [EFLAGS] in {
Dan Gohmanfc4eddb2009-01-13 20:32:45 +00003024def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
Dan Gohman7fe9b7f2008-12-23 22:45:23 +00003025 "bt{w}\t{$src2, $src1|$src1, $src2}",
3026 [(X86bt GR16:$src1, GR16:$src2),
Chris Lattner5a95cde2008-12-25 01:32:49 +00003027 (implicit EFLAGS)]>, OpSize, TB;
Dan Gohmanfc4eddb2009-01-13 20:32:45 +00003028def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
Dan Gohman7fe9b7f2008-12-23 22:45:23 +00003029 "bt{l}\t{$src2, $src1|$src1, $src2}",
3030 [(X86bt GR32:$src1, GR32:$src2),
Chris Lattner5a95cde2008-12-25 01:32:49 +00003031 (implicit EFLAGS)]>, TB;
Dan Gohman85a228c2009-01-13 23:23:30 +00003032
3033// Unlike with the register+register form, the memory+register form of the
3034// bt instruction does not ignore the high bits of the index. From ISel's
3035// perspective, this is pretty bizarre. Disable these instructions for now.
3036//def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3037// "bt{w}\t{$src2, $src1|$src1, $src2}",
3038// [(X86bt (loadi16 addr:$src1), GR16:$src2),
3039// (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
3040//def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3041// "bt{l}\t{$src2, $src1|$src1, $src2}",
3042// [(X86bt (loadi32 addr:$src1), GR32:$src2),
3043// (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
Dan Gohman46fb1cf2009-01-13 20:33:23 +00003044
3045def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3046 "bt{w}\t{$src2, $src1|$src1, $src2}",
3047 [(X86bt GR16:$src1, i16immSExt8:$src2),
3048 (implicit EFLAGS)]>, OpSize, TB;
3049def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3050 "bt{l}\t{$src2, $src1|$src1, $src2}",
3051 [(X86bt GR32:$src1, i32immSExt8:$src2),
3052 (implicit EFLAGS)]>, TB;
3053// Note that these instructions don't need FastBTMem because that
3054// only applies when the other operand is in a register. When it's
3055// an immediate, bt is still fast.
3056def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3057 "bt{w}\t{$src2, $src1|$src1, $src2}",
3058 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3059 (implicit EFLAGS)]>, OpSize, TB;
3060def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3061 "bt{l}\t{$src2, $src1|$src1, $src2}",
3062 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3063 (implicit EFLAGS)]>, TB;
Dan Gohman7fe9b7f2008-12-23 22:45:23 +00003064} // Defs = [EFLAGS]
3065
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003066// Sign/Zero extenders
Dan Gohman9203ab42008-07-30 18:09:17 +00003067// Use movsbl intead of movsbw; we don't care about the high 16 bits
3068// of the register here. This has a smaller encoding and avoids a
3069// partial-register update.
Evan Chengb783fa32007-07-19 01:14:50 +00003070def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
Dan Gohman9203ab42008-07-30 18:09:17 +00003071 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3072 [(set GR16:$dst, (sext GR8:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00003073def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
Dan Gohman9203ab42008-07-30 18:09:17 +00003074 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3075 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00003076def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00003077 "movs{bl|x}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003078 [(set GR32:$dst, (sext GR8:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00003079def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00003080 "movs{bl|x}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003081 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00003082def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00003083 "movs{wl|x}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003084 [(set GR32:$dst, (sext GR16:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00003085def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00003086 "movs{wl|x}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003087 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3088
Dan Gohman9203ab42008-07-30 18:09:17 +00003089// Use movzbl intead of movzbw; we don't care about the high 16 bits
3090// of the register here. This has a smaller encoding and avoids a
3091// partial-register update.
Evan Chengb783fa32007-07-19 01:14:50 +00003092def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
Dan Gohman9203ab42008-07-30 18:09:17 +00003093 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3094 [(set GR16:$dst, (zext GR8:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00003095def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
Dan Gohman9203ab42008-07-30 18:09:17 +00003096 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3097 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00003098def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00003099 "movz{bl|x}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003100 [(set GR32:$dst, (zext GR8:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00003101def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00003102 "movz{bl|x}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003103 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00003104def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00003105 "movz{wl|x}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003106 [(set GR32:$dst, (zext GR16:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00003107def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00003108 "movz{wl|x}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003109 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3110
Dan Gohman744d4622009-04-13 16:09:41 +00003111// These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
3112// except that they use GR32_NOREX for the output operand register class
3113// instead of GR32. This allows them to operate on h registers on x86-64.
3114def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3115 (outs GR32_NOREX:$dst), (ins GR8:$src),
3116 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3117 []>, TB;
Dan Gohman89f4cda2009-04-30 03:11:48 +00003118let mayLoad = 1 in
Dan Gohman744d4622009-04-13 16:09:41 +00003119def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3120 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3121 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3122 []>, TB;
3123
Chris Lattnerc90ee9c2008-01-10 07:59:24 +00003124let neverHasSideEffects = 1 in {
3125 let Defs = [AX], Uses = [AL] in
3126 def CBW : I<0x98, RawFrm, (outs), (ins),
3127 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3128 let Defs = [EAX], Uses = [AX] in
3129 def CWDE : I<0x98, RawFrm, (outs), (ins),
3130 "{cwtl|cwde}", []>; // EAX = signext(AX)
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003131
Chris Lattnerc90ee9c2008-01-10 07:59:24 +00003132 let Defs = [AX,DX], Uses = [AX] in
3133 def CWD : I<0x99, RawFrm, (outs), (ins),
3134 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3135 let Defs = [EAX,EDX], Uses = [EAX] in
3136 def CDQ : I<0x99, RawFrm, (outs), (ins),
3137 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3138}
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003139
3140//===----------------------------------------------------------------------===//
3141// Alias Instructions
3142//===----------------------------------------------------------------------===//
3143
3144// Alias instructions that map movr0 to xor.
3145// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
Bill Wendlingba5d5b02008-05-29 01:02:09 +00003146let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in {
Evan Chengb783fa32007-07-19 01:14:50 +00003147def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00003148 "xor{b}\t$dst, $dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003149 [(set GR8:$dst, 0)]>;
Dan Gohman9203ab42008-07-30 18:09:17 +00003150// Use xorl instead of xorw since we don't care about the high 16 bits,
3151// it's smaller, and it avoids a partial-register update.
Evan Chengb783fa32007-07-19 01:14:50 +00003152def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
Dan Gohman9203ab42008-07-30 18:09:17 +00003153 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
3154 [(set GR16:$dst, 0)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00003155def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00003156 "xor{l}\t$dst, $dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003157 [(set GR32:$dst, 0)]>;
Dan Gohman8aef09b2007-09-07 21:32:51 +00003158}
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003159
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003160//===----------------------------------------------------------------------===//
3161// Thread Local Storage Instructions
3162//
3163
Rafael Espindola7fc4b8d2009-04-24 12:59:40 +00003164// All calls clobber the non-callee saved registers. ESP is marked as
3165// a use to prevent stack-pointer assignments that appear immediately
3166// before calls from potentially appearing dead.
3167let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3168 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3169 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3170 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
Chris Lattnerf1940742009-06-20 20:38:48 +00003171 Uses = [ESP] in
3172def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3173 "leal\t$sym, %eax; "
Dan Gohman70a8a112009-04-27 15:13:28 +00003174 "call\t___tls_get_addr@PLT",
Chris Lattnerf1940742009-06-20 20:38:48 +00003175 [(X86tlsaddr tls32addr:$sym)]>,
Rafael Espindolaaf759ab2009-04-17 14:35:58 +00003176 Requires<[In32BitMode]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003177
sampo9cc09a32009-01-26 01:24:32 +00003178let AddedComplexity = 5 in
3179def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3180 "movl\t%gs:$src, $dst",
3181 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3182
Chris Lattnera7c2d8a2009-05-05 18:52:19 +00003183let AddedComplexity = 5 in
3184def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3185 "movl\t%fs:$src, $dst",
3186 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3187
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003188//===----------------------------------------------------------------------===//
3189// DWARF Pseudo Instructions
3190//
3191
Evan Chengb783fa32007-07-19 01:14:50 +00003192def DWARF_LOC : I<0, Pseudo, (outs),
3193 (ins i32imm:$line, i32imm:$col, i32imm:$file),
Chris Lattner64b54552009-07-10 22:34:11 +00003194 ".loc\t$file $line $col",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003195 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
3196 (i32 imm:$file))]>;
3197
3198//===----------------------------------------------------------------------===//
3199// EH Pseudo Instructions
3200//
3201let isTerminator = 1, isReturn = 1, isBarrier = 1,
Evan Cheng37e7c752007-07-21 00:34:19 +00003202 hasCtrlDep = 1 in {
Evan Chengb783fa32007-07-19 01:14:50 +00003203def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
Dan Gohman91888f02007-07-31 20:11:57 +00003204 "ret\t#eh_return, addr: $addr",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003205 [(X86ehret GR32:$addr)]>;
3206
3207}
3208
3209//===----------------------------------------------------------------------===//
Andrew Lenharthe44f3902008-02-21 06:45:13 +00003210// Atomic support
3211//
Andrew Lenharth7a5a4b22008-03-01 13:37:02 +00003212
Evan Cheng3e171562008-04-19 01:20:30 +00003213// Atomic swap. These are just normal xchg instructions. But since a memory
3214// operand is referenced, the atomicity is ensured.
Dan Gohmana41a1c092008-08-06 15:52:50 +00003215let Constraints = "$val = $dst" in {
Evan Cheng3e171562008-04-19 01:20:30 +00003216def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3217 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3218 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3219def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3220 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3221 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3222 OpSize;
3223def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3224 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3225 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3226}
3227
Evan Chengd49dbb82008-04-18 20:55:36 +00003228// Atomic compare and swap.
Andrew Lenharth7dfe23f2008-03-01 21:52:34 +00003229let Defs = [EAX, EFLAGS], Uses = [EAX] in {
Evan Chengd49dbb82008-04-18 20:55:36 +00003230def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
Dan Gohman70a8a112009-04-27 15:13:28 +00003231 "lock\n\t"
3232 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
Evan Cheng09fbdee2008-03-04 03:20:06 +00003233 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
Andrew Lenharth7a5a4b22008-03-01 13:37:02 +00003234}
Dale Johannesenf160d802008-10-02 18:53:47 +00003235let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
Anton Korobeynikovc4067392008-07-22 16:22:48 +00003236def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
Dan Gohman70a8a112009-04-27 15:13:28 +00003237 "lock\n\t"
3238 "cmpxchg8b\t$ptr",
Andrew Lenharth81580822008-03-05 01:15:49 +00003239 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3240}
Andrew Lenharth7dfe23f2008-03-01 21:52:34 +00003241
3242let Defs = [AX, EFLAGS], Uses = [AX] in {
Evan Chengd49dbb82008-04-18 20:55:36 +00003243def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
Dan Gohman70a8a112009-04-27 15:13:28 +00003244 "lock\n\t"
3245 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
Evan Cheng09fbdee2008-03-04 03:20:06 +00003246 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
Andrew Lenharth7a5a4b22008-03-01 13:37:02 +00003247}
Andrew Lenharth7dfe23f2008-03-01 21:52:34 +00003248let Defs = [AL, EFLAGS], Uses = [AL] in {
Evan Chengd49dbb82008-04-18 20:55:36 +00003249def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
Dan Gohman70a8a112009-04-27 15:13:28 +00003250 "lock\n\t"
3251 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
Evan Cheng09fbdee2008-03-04 03:20:06 +00003252 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
Andrew Lenharth7a5a4b22008-03-01 13:37:02 +00003253}
3254
Evan Chengd49dbb82008-04-18 20:55:36 +00003255// Atomic exchange and add
3256let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3257def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
Dan Gohman70a8a112009-04-27 15:13:28 +00003258 "lock\n\t"
3259 "xadd{l}\t{$val, $ptr|$ptr, $val}",
Mon P Wang6bde9ec2008-06-25 08:15:39 +00003260 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
Evan Chengd49dbb82008-04-18 20:55:36 +00003261 TB, LOCK;
3262def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
Dan Gohman70a8a112009-04-27 15:13:28 +00003263 "lock\n\t"
3264 "xadd{w}\t{$val, $ptr|$ptr, $val}",
Mon P Wang6bde9ec2008-06-25 08:15:39 +00003265 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
Evan Chengd49dbb82008-04-18 20:55:36 +00003266 TB, OpSize, LOCK;
3267def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
Dan Gohman70a8a112009-04-27 15:13:28 +00003268 "lock\n\t"
3269 "xadd{b}\t{$val, $ptr|$ptr, $val}",
Mon P Wang6bde9ec2008-06-25 08:15:39 +00003270 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
Evan Chengd49dbb82008-04-18 20:55:36 +00003271 TB, LOCK;
Andrew Lenharth7a5a4b22008-03-01 13:37:02 +00003272}
3273
Evan Chengb723fb52009-07-30 08:33:02 +00003274// Optimized codegen when the non-memory output is not used.
3275// FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3276def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3277 "lock\n\t"
3278 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3279def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3280 "lock\n\t"
3281 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3282def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3283 "lock\n\t"
3284 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3285def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3286 "lock\n\t"
3287 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3288def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3289 "lock\n\t"
3290 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3291def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3292 "lock\n\t"
3293 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3294def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3295 "lock\n\t"
3296 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3297def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3298 "lock\n\t"
3299 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3300
3301def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3302 "lock\n\t"
3303 "inc{b}\t$dst", []>, LOCK;
3304def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3305 "lock\n\t"
3306 "inc{w}\t$dst", []>, OpSize, LOCK;
3307def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3308 "lock\n\t"
3309 "inc{l}\t$dst", []>, LOCK;
3310
3311def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3312 "lock\n\t"
3313 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3314def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3315 "lock\n\t"
3316 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3317def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3318 "lock\n\t"
3319 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3320def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3321 "lock\n\t"
3322 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3323def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3324 "lock\n\t"
3325 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3326def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3327 "lock\n\t"
3328 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3329def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3330 "lock\n\t"
3331 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3332def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3333 "lock\n\t"
3334 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3335
3336def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3337 "lock\n\t"
3338 "dec{b}\t$dst", []>, LOCK;
3339def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3340 "lock\n\t"
3341 "dec{w}\t$dst", []>, OpSize, LOCK;
3342def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3343 "lock\n\t"
3344 "dec{l}\t$dst", []>, LOCK;
3345
Mon P Wang6bde9ec2008-06-25 08:15:39 +00003346// Atomic exchange, and, or, xor
Mon P Wang078a62d2008-05-05 19:05:59 +00003347let Constraints = "$val = $dst", Defs = [EFLAGS],
3348 usesCustomDAGSchedInserter = 1 in {
Dan Gohman8aeb61f2008-05-12 20:22:45 +00003349def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003350 "#ATOMAND32 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003351 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
Dan Gohman8aeb61f2008-05-12 20:22:45 +00003352def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003353 "#ATOMOR32 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003354 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
Dan Gohman8aeb61f2008-05-12 20:22:45 +00003355def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003356 "#ATOMXOR32 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003357 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
Andrew Lenharthaf02d592008-06-14 05:48:15 +00003358def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003359 "#ATOMNAND32 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003360 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
Dan Gohman8aeb61f2008-05-12 20:22:45 +00003361def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003362 "#ATOMMIN32 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003363 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
Dan Gohman8aeb61f2008-05-12 20:22:45 +00003364def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003365 "#ATOMMAX32 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003366 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
Dan Gohman8aeb61f2008-05-12 20:22:45 +00003367def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003368 "#ATOMUMIN32 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003369 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
Dan Gohman8aeb61f2008-05-12 20:22:45 +00003370def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003371 "#ATOMUMAX32 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003372 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003373
3374def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003375 "#ATOMAND16 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003376 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003377def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003378 "#ATOMOR16 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003379 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003380def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003381 "#ATOMXOR16 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003382 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003383def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003384 "#ATOMNAND16 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003385 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003386def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003387 "#ATOMMIN16 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003388 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003389def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003390 "#ATOMMAX16 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003391 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003392def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003393 "#ATOMUMIN16 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003394 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003395def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003396 "#ATOMUMAX16 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003397 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003398
3399def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003400 "#ATOMAND8 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003401 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003402def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003403 "#ATOMOR8 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003404 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003405def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003406 "#ATOMXOR8 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003407 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003408def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003409 "#ATOMNAND8 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003410 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
Mon P Wang078a62d2008-05-05 19:05:59 +00003411}
3412
Dale Johannesenf160d802008-10-02 18:53:47 +00003413let Constraints = "$val1 = $dst1, $val2 = $dst2",
3414 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3415 Uses = [EAX, EBX, ECX, EDX],
Dale Johannesen44eb5372008-10-03 19:41:08 +00003416 mayLoad = 1, mayStore = 1,
Dale Johannesenf160d802008-10-02 18:53:47 +00003417 usesCustomDAGSchedInserter = 1 in {
3418def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3419 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003420 "#ATOMAND6432 PSEUDO!", []>;
Dale Johannesenf160d802008-10-02 18:53:47 +00003421def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3422 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003423 "#ATOMOR6432 PSEUDO!", []>;
Dale Johannesenf160d802008-10-02 18:53:47 +00003424def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3425 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003426 "#ATOMXOR6432 PSEUDO!", []>;
Dale Johannesenf160d802008-10-02 18:53:47 +00003427def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3428 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003429 "#ATOMNAND6432 PSEUDO!", []>;
Dale Johannesenf160d802008-10-02 18:53:47 +00003430def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3431 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003432 "#ATOMADD6432 PSEUDO!", []>;
Dale Johannesenf160d802008-10-02 18:53:47 +00003433def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3434 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003435 "#ATOMSUB6432 PSEUDO!", []>;
Dale Johannesen51c58ee2008-10-03 22:25:52 +00003436def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3437 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003438 "#ATOMSWAP6432 PSEUDO!", []>;
Dale Johannesenf160d802008-10-02 18:53:47 +00003439}
3440
Andrew Lenharthe44f3902008-02-21 06:45:13 +00003441//===----------------------------------------------------------------------===//
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003442// Non-Instruction Patterns
3443//===----------------------------------------------------------------------===//
3444
Bill Wendlingfef06052008-09-16 21:48:12 +00003445// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003446def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3447def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
Nate Begemanb52948972008-04-12 00:47:57 +00003448def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003449def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3450def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3451
3452def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3453 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3454def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3455 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3456def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3457 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3458def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3459 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3460
3461def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3462 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3463def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3464 (MOV32mi addr:$dst, texternalsym:$src)>;
3465
3466// Calls
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +00003467// tailcall stuff
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +00003468def : Pat<(X86tcret GR32:$dst, imm:$off),
3469 (TCRETURNri GR32:$dst, imm:$off)>;
3470
3471def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3472 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3473
3474def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3475 (TCRETURNdi texternalsym:$dst, imm:$off)>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003476
Dan Gohmance5dbff2009-08-02 16:10:01 +00003477// Normal calls, with various flavors of addresses.
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003478def : Pat<(X86call (i32 tglobaladdr:$dst)),
3479 (CALLpcrel32 tglobaladdr:$dst)>;
3480def : Pat<(X86call (i32 texternalsym:$dst)),
3481 (CALLpcrel32 texternalsym:$dst)>;
Evan Cheng6d35a4d2009-05-20 04:53:57 +00003482def : Pat<(X86call (i32 imm:$dst)),
3483 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003484
3485// X86 specific add which produces a flag.
3486def : Pat<(addc GR32:$src1, GR32:$src2),
3487 (ADD32rr GR32:$src1, GR32:$src2)>;
3488def : Pat<(addc GR32:$src1, (load addr:$src2)),
3489 (ADD32rm GR32:$src1, addr:$src2)>;
3490def : Pat<(addc GR32:$src1, imm:$src2),
3491 (ADD32ri GR32:$src1, imm:$src2)>;
3492def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3493 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3494
3495def : Pat<(subc GR32:$src1, GR32:$src2),
3496 (SUB32rr GR32:$src1, GR32:$src2)>;
3497def : Pat<(subc GR32:$src1, (load addr:$src2)),
3498 (SUB32rm GR32:$src1, addr:$src2)>;
3499def : Pat<(subc GR32:$src1, imm:$src2),
3500 (SUB32ri GR32:$src1, imm:$src2)>;
3501def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3502 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3503
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003504// Comparisons.
3505
3506// TEST R,R is smaller than CMP R,0
Evan Cheng621216e2007-09-29 00:00:36 +00003507def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003508 (TEST8rr GR8:$src1, GR8:$src1)>;
Evan Cheng621216e2007-09-29 00:00:36 +00003509def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003510 (TEST16rr GR16:$src1, GR16:$src1)>;
Evan Cheng621216e2007-09-29 00:00:36 +00003511def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003512 (TEST32rr GR32:$src1, GR32:$src1)>;
3513
Dan Gohman0a3c5222009-01-07 01:00:24 +00003514// Conditional moves with folded loads with operands swapped and conditions
3515// inverted.
3516def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
3517 (CMOVAE16rm GR16:$src2, addr:$src1)>;
3518def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
3519 (CMOVAE32rm GR32:$src2, addr:$src1)>;
3520def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
3521 (CMOVB16rm GR16:$src2, addr:$src1)>;
3522def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
3523 (CMOVB32rm GR32:$src2, addr:$src1)>;
3524def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
3525 (CMOVNE16rm GR16:$src2, addr:$src1)>;
3526def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
3527 (CMOVNE32rm GR32:$src2, addr:$src1)>;
3528def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
3529 (CMOVE16rm GR16:$src2, addr:$src1)>;
3530def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
3531 (CMOVE32rm GR32:$src2, addr:$src1)>;
3532def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
3533 (CMOVA16rm GR16:$src2, addr:$src1)>;
3534def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
3535 (CMOVA32rm GR32:$src2, addr:$src1)>;
3536def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
3537 (CMOVBE16rm GR16:$src2, addr:$src1)>;
3538def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
3539 (CMOVBE32rm GR32:$src2, addr:$src1)>;
3540def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
3541 (CMOVGE16rm GR16:$src2, addr:$src1)>;
3542def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
3543 (CMOVGE32rm GR32:$src2, addr:$src1)>;
3544def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
3545 (CMOVL16rm GR16:$src2, addr:$src1)>;
3546def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
3547 (CMOVL32rm GR32:$src2, addr:$src1)>;
3548def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
3549 (CMOVG16rm GR16:$src2, addr:$src1)>;
3550def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
3551 (CMOVG32rm GR32:$src2, addr:$src1)>;
3552def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
3553 (CMOVLE16rm GR16:$src2, addr:$src1)>;
3554def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
3555 (CMOVLE32rm GR32:$src2, addr:$src1)>;
3556def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
3557 (CMOVNP16rm GR16:$src2, addr:$src1)>;
3558def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
3559 (CMOVNP32rm GR32:$src2, addr:$src1)>;
3560def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
3561 (CMOVP16rm GR16:$src2, addr:$src1)>;
3562def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
3563 (CMOVP32rm GR32:$src2, addr:$src1)>;
3564def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
3565 (CMOVNS16rm GR16:$src2, addr:$src1)>;
3566def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
3567 (CMOVNS32rm GR32:$src2, addr:$src1)>;
3568def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
3569 (CMOVS16rm GR16:$src2, addr:$src1)>;
3570def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
3571 (CMOVS32rm GR32:$src2, addr:$src1)>;
3572def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
3573 (CMOVNO16rm GR16:$src2, addr:$src1)>;
3574def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
3575 (CMOVNO32rm GR32:$src2, addr:$src1)>;
3576def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
3577 (CMOVO16rm GR16:$src2, addr:$src1)>;
3578def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
3579 (CMOVO32rm GR32:$src2, addr:$src1)>;
3580
Duncan Sands082524c2008-01-23 20:39:46 +00003581// zextload bool -> zextload byte
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003582def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3583def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3584def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3585
3586// extload bool -> extload byte
3587def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
Bill Wendlingce1c5c12008-08-22 20:51:05 +00003588def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
3589 Requires<[In32BitMode]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003590def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
Bill Wendlingce1c5c12008-08-22 20:51:05 +00003591def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
3592 Requires<[In32BitMode]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003593def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3594def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3595
Dan Gohmandd612bb2008-08-20 21:27:32 +00003596// anyext
Bill Wendlingce1c5c12008-08-22 20:51:05 +00003597def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
3598 Requires<[In32BitMode]>;
3599def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
3600 Requires<[In32BitMode]>;
Dan Gohmandd612bb2008-08-20 21:27:32 +00003601def : Pat<(i32 (anyext GR16:$src)),
3602 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003603
Evan Chengf2abee72007-12-13 00:43:27 +00003604// (and (i32 load), 255) -> (zextload i8)
Evan Cheng1e5e5452008-09-29 17:26:18 +00003605def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3606 (MOVZX32rm8 addr:$src)>;
3607def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3608 (MOVZX32rm16 addr:$src)>;
Evan Chengf2abee72007-12-13 00:43:27 +00003609
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003610//===----------------------------------------------------------------------===//
3611// Some peepholes
3612//===----------------------------------------------------------------------===//
3613
Dan Gohman5a5e6e92008-10-17 01:33:43 +00003614// Odd encoding trick: -128 fits into an 8-bit immediate field while
3615// +128 doesn't, so in this special case use a sub instead of an add.
3616def : Pat<(add GR16:$src1, 128),
3617 (SUB16ri8 GR16:$src1, -128)>;
3618def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3619 (SUB16mi8 addr:$dst, -128)>;
3620def : Pat<(add GR32:$src1, 128),
3621 (SUB32ri8 GR32:$src1, -128)>;
3622def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3623 (SUB32mi8 addr:$dst, -128)>;
3624
Dan Gohman9203ab42008-07-30 18:09:17 +00003625// r & (2^16-1) ==> movz
3626def : Pat<(and GR32:$src1, 0xffff),
Dan Gohman744d4622009-04-13 16:09:41 +00003627 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
Dan Gohman5beb1ff2008-08-06 18:27:21 +00003628// r & (2^8-1) ==> movz
3629def : Pat<(and GR32:$src1, 0xff),
Dan Gohman6e438702009-04-27 16:33:14 +00003630 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_ABCD),
Dan Gohman744d4622009-04-13 16:09:41 +00003631 x86_subreg_8bit))>,
Dan Gohman5beb1ff2008-08-06 18:27:21 +00003632 Requires<[In32BitMode]>;
3633// r & (2^8-1) ==> movz
3634def : Pat<(and GR16:$src1, 0xff),
Dan Gohman6e438702009-04-27 16:33:14 +00003635 (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD),
Dan Gohman744d4622009-04-13 16:09:41 +00003636 x86_subreg_8bit))>,
Dan Gohmandd612bb2008-08-20 21:27:32 +00003637 Requires<[In32BitMode]>;
3638
3639// sext_inreg patterns
3640def : Pat<(sext_inreg GR32:$src, i16),
Dan Gohman744d4622009-04-13 16:09:41 +00003641 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
Dan Gohmandd612bb2008-08-20 21:27:32 +00003642def : Pat<(sext_inreg GR32:$src, i8),
Dan Gohman6e438702009-04-27 16:33:14 +00003643 (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
Dan Gohman744d4622009-04-13 16:09:41 +00003644 x86_subreg_8bit))>,
Dan Gohmandd612bb2008-08-20 21:27:32 +00003645 Requires<[In32BitMode]>;
3646def : Pat<(sext_inreg GR16:$src, i8),
Dan Gohman6e438702009-04-27 16:33:14 +00003647 (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
Dan Gohman744d4622009-04-13 16:09:41 +00003648 x86_subreg_8bit))>,
Dan Gohmandd612bb2008-08-20 21:27:32 +00003649 Requires<[In32BitMode]>;
3650
3651// trunc patterns
3652def : Pat<(i16 (trunc GR32:$src)),
Dan Gohman744d4622009-04-13 16:09:41 +00003653 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
Dan Gohmandd612bb2008-08-20 21:27:32 +00003654def : Pat<(i8 (trunc GR32:$src)),
Dan Gohman6e438702009-04-27 16:33:14 +00003655 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
Dan Gohman744d4622009-04-13 16:09:41 +00003656 x86_subreg_8bit)>,
Dan Gohmandd612bb2008-08-20 21:27:32 +00003657 Requires<[In32BitMode]>;
3658def : Pat<(i8 (trunc GR16:$src)),
Dan Gohman6e438702009-04-27 16:33:14 +00003659 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
Dan Gohman744d4622009-04-13 16:09:41 +00003660 x86_subreg_8bit)>,
3661 Requires<[In32BitMode]>;
3662
3663// h-register tricks
3664def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
Dan Gohman6e438702009-04-27 16:33:14 +00003665 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
Dan Gohman744d4622009-04-13 16:09:41 +00003666 x86_subreg_8bit_hi)>,
3667 Requires<[In32BitMode]>;
3668def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
Dan Gohman6e438702009-04-27 16:33:14 +00003669 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
Dan Gohman744d4622009-04-13 16:09:41 +00003670 x86_subreg_8bit_hi)>,
3671 Requires<[In32BitMode]>;
3672def : Pat<(srl_su GR16:$src, (i8 8)),
3673 (EXTRACT_SUBREG
3674 (MOVZX32rr8
Dan Gohman6e438702009-04-27 16:33:14 +00003675 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
Dan Gohman744d4622009-04-13 16:09:41 +00003676 x86_subreg_8bit_hi)),
3677 x86_subreg_16bit)>,
3678 Requires<[In32BitMode]>;
Evan Cheng957ca282009-05-29 01:44:43 +00003679def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
3680 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3681 x86_subreg_8bit_hi))>,
3682 Requires<[In32BitMode]>;
Dan Gohman744d4622009-04-13 16:09:41 +00003683def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
Dan Gohman6e438702009-04-27 16:33:14 +00003684 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
Dan Gohman744d4622009-04-13 16:09:41 +00003685 x86_subreg_8bit_hi))>,
Dan Gohman5beb1ff2008-08-06 18:27:21 +00003686 Requires<[In32BitMode]>;
Dan Gohman9203ab42008-07-30 18:09:17 +00003687
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003688// (shl x, 1) ==> (add x, x)
3689def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3690def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3691def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3692
Evan Cheng76a64c72008-08-30 02:03:58 +00003693// (shl x (and y, 31)) ==> (shl x, y)
3694def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3695 (SHL8rCL GR8:$src1)>;
3696def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3697 (SHL16rCL GR16:$src1)>;
3698def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3699 (SHL32rCL GR32:$src1)>;
3700def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3701 (SHL8mCL addr:$dst)>;
3702def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3703 (SHL16mCL addr:$dst)>;
3704def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3705 (SHL32mCL addr:$dst)>;
3706
3707def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3708 (SHR8rCL GR8:$src1)>;
3709def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3710 (SHR16rCL GR16:$src1)>;
3711def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3712 (SHR32rCL GR32:$src1)>;
3713def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3714 (SHR8mCL addr:$dst)>;
3715def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3716 (SHR16mCL addr:$dst)>;
3717def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3718 (SHR32mCL addr:$dst)>;
3719
3720def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3721 (SAR8rCL GR8:$src1)>;
3722def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3723 (SAR16rCL GR16:$src1)>;
3724def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3725 (SAR32rCL GR32:$src1)>;
3726def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3727 (SAR8mCL addr:$dst)>;
3728def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3729 (SAR16mCL addr:$dst)>;
3730def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3731 (SAR32mCL addr:$dst)>;
3732
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003733// (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3734def : Pat<(or (srl GR32:$src1, CL:$amt),
3735 (shl GR32:$src2, (sub 32, CL:$amt))),
3736 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3737
3738def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3739 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3740 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3741
Dan Gohman921581d2008-10-17 01:23:35 +00003742def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3743 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3744 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3745
3746def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3747 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3748 addr:$dst),
3749 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3750
3751def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3752 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3753
3754def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3755 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3756 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3757
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003758// (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3759def : Pat<(or (shl GR32:$src1, CL:$amt),
3760 (srl GR32:$src2, (sub 32, CL:$amt))),
3761 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3762
3763def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3764 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3765 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3766
Dan Gohman921581d2008-10-17 01:23:35 +00003767def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3768 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3769 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3770
3771def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3772 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3773 addr:$dst),
3774 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3775
3776def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3777 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3778
3779def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3780 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3781 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3782
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003783// (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3784def : Pat<(or (srl GR16:$src1, CL:$amt),
3785 (shl GR16:$src2, (sub 16, CL:$amt))),
3786 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3787
3788def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3789 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3790 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3791
Dan Gohman921581d2008-10-17 01:23:35 +00003792def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3793 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3794 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3795
3796def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3797 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3798 addr:$dst),
3799 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3800
3801def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3802 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3803
3804def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3805 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3806 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3807
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003808// (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3809def : Pat<(or (shl GR16:$src1, CL:$amt),
3810 (srl GR16:$src2, (sub 16, CL:$amt))),
3811 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3812
3813def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3814 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3815 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3816
Dan Gohman921581d2008-10-17 01:23:35 +00003817def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3818 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3819 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3820
3821def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3822 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3823 addr:$dst),
3824 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3825
3826def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3827 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3828
3829def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3830 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3831 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3832
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003833//===----------------------------------------------------------------------===//
Dan Gohman99a12192009-03-04 19:44:21 +00003834// EFLAGS-defining Patterns
Bill Wendlingf5399032008-12-12 21:15:41 +00003835//===----------------------------------------------------------------------===//
3836
Dan Gohman99a12192009-03-04 19:44:21 +00003837// Register-Register Addition with EFLAGS result
3838def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003839 (implicit EFLAGS)),
3840 (ADD8rr GR8:$src1, GR8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003841def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003842 (implicit EFLAGS)),
3843 (ADD16rr GR16:$src1, GR16:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003844def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003845 (implicit EFLAGS)),
3846 (ADD32rr GR32:$src1, GR32:$src2)>;
3847
Dan Gohman99a12192009-03-04 19:44:21 +00003848// Register-Memory Addition with EFLAGS result
3849def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
Bill Wendlingf5399032008-12-12 21:15:41 +00003850 (implicit EFLAGS)),
3851 (ADD8rm GR8:$src1, addr:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003852def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
Bill Wendlingf5399032008-12-12 21:15:41 +00003853 (implicit EFLAGS)),
3854 (ADD16rm GR16:$src1, addr:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003855def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
Bill Wendlingf5399032008-12-12 21:15:41 +00003856 (implicit EFLAGS)),
3857 (ADD32rm GR32:$src1, addr:$src2)>;
3858
Dan Gohman99a12192009-03-04 19:44:21 +00003859// Register-Integer Addition with EFLAGS result
3860def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003861 (implicit EFLAGS)),
3862 (ADD8ri GR8:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003863def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003864 (implicit EFLAGS)),
3865 (ADD16ri GR16:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003866def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003867 (implicit EFLAGS)),
3868 (ADD32ri GR32:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003869def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003870 (implicit EFLAGS)),
3871 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003872def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003873 (implicit EFLAGS)),
3874 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3875
Dan Gohman99a12192009-03-04 19:44:21 +00003876// Memory-Register Addition with EFLAGS result
3877def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003878 addr:$dst),
3879 (implicit EFLAGS)),
3880 (ADD8mr addr:$dst, GR8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003881def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003882 addr:$dst),
3883 (implicit EFLAGS)),
3884 (ADD16mr addr:$dst, GR16:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003885def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003886 addr:$dst),
3887 (implicit EFLAGS)),
3888 (ADD32mr addr:$dst, GR32:$src2)>;
Dale Johannesen06b83f12009-05-18 17:44:15 +00003889
3890// Memory-Integer Addition with EFLAGS result
Dan Gohman99a12192009-03-04 19:44:21 +00003891def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003892 addr:$dst),
3893 (implicit EFLAGS)),
3894 (ADD8mi addr:$dst, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003895def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003896 addr:$dst),
3897 (implicit EFLAGS)),
3898 (ADD16mi addr:$dst, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003899def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003900 addr:$dst),
3901 (implicit EFLAGS)),
3902 (ADD32mi addr:$dst, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003903def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003904 addr:$dst),
3905 (implicit EFLAGS)),
3906 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003907def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003908 addr:$dst),
3909 (implicit EFLAGS)),
3910 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
3911
Dan Gohman99a12192009-03-04 19:44:21 +00003912// Register-Register Subtraction with EFLAGS result
3913def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003914 (implicit EFLAGS)),
3915 (SUB8rr GR8:$src1, GR8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003916def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003917 (implicit EFLAGS)),
3918 (SUB16rr GR16:$src1, GR16:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003919def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003920 (implicit EFLAGS)),
3921 (SUB32rr GR32:$src1, GR32:$src2)>;
3922
Dan Gohman99a12192009-03-04 19:44:21 +00003923// Register-Memory Subtraction with EFLAGS result
3924def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
Bill Wendlingf5399032008-12-12 21:15:41 +00003925 (implicit EFLAGS)),
3926 (SUB8rm GR8:$src1, addr:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003927def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
Bill Wendlingf5399032008-12-12 21:15:41 +00003928 (implicit EFLAGS)),
3929 (SUB16rm GR16:$src1, addr:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003930def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
Bill Wendlingf5399032008-12-12 21:15:41 +00003931 (implicit EFLAGS)),
3932 (SUB32rm GR32:$src1, addr:$src2)>;
3933
Dan Gohman99a12192009-03-04 19:44:21 +00003934// Register-Integer Subtraction with EFLAGS result
3935def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003936 (implicit EFLAGS)),
3937 (SUB8ri GR8:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003938def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003939 (implicit EFLAGS)),
3940 (SUB16ri GR16:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003941def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003942 (implicit EFLAGS)),
3943 (SUB32ri GR32:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003944def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003945 (implicit EFLAGS)),
3946 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003947def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003948 (implicit EFLAGS)),
3949 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3950
Dan Gohman99a12192009-03-04 19:44:21 +00003951// Memory-Register Subtraction with EFLAGS result
3952def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003953 addr:$dst),
3954 (implicit EFLAGS)),
3955 (SUB8mr addr:$dst, GR8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003956def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003957 addr:$dst),
3958 (implicit EFLAGS)),
3959 (SUB16mr addr:$dst, GR16:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003960def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003961 addr:$dst),
3962 (implicit EFLAGS)),
3963 (SUB32mr addr:$dst, GR32:$src2)>;
3964
Dan Gohman99a12192009-03-04 19:44:21 +00003965// Memory-Integer Subtraction with EFLAGS result
3966def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003967 addr:$dst),
3968 (implicit EFLAGS)),
3969 (SUB8mi addr:$dst, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003970def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003971 addr:$dst),
3972 (implicit EFLAGS)),
3973 (SUB16mi addr:$dst, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003974def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003975 addr:$dst),
3976 (implicit EFLAGS)),
3977 (SUB32mi addr:$dst, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003978def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003979 addr:$dst),
3980 (implicit EFLAGS)),
3981 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003982def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003983 addr:$dst),
3984 (implicit EFLAGS)),
3985 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
3986
3987
Dan Gohman99a12192009-03-04 19:44:21 +00003988// Register-Register Signed Integer Multiply with EFLAGS result
3989def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003990 (implicit EFLAGS)),
3991 (IMUL16rr GR16:$src1, GR16:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003992def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003993 (implicit EFLAGS)),
3994 (IMUL32rr GR32:$src1, GR32:$src2)>;
3995
Dan Gohman99a12192009-03-04 19:44:21 +00003996// Register-Memory Signed Integer Multiply with EFLAGS result
3997def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
Bill Wendlingf5399032008-12-12 21:15:41 +00003998 (implicit EFLAGS)),
3999 (IMUL16rm GR16:$src1, addr:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00004000def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
Bill Wendlingf5399032008-12-12 21:15:41 +00004001 (implicit EFLAGS)),
4002 (IMUL32rm GR32:$src1, addr:$src2)>;
4003
Dan Gohman99a12192009-03-04 19:44:21 +00004004// Register-Integer Signed Integer Multiply with EFLAGS result
4005def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00004006 (implicit EFLAGS)),
4007 (IMUL16rri GR16:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00004008def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00004009 (implicit EFLAGS)),
4010 (IMUL32rri GR32:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00004011def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00004012 (implicit EFLAGS)),
4013 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00004014def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00004015 (implicit EFLAGS)),
4016 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4017
Dan Gohman99a12192009-03-04 19:44:21 +00004018// Memory-Integer Signed Integer Multiply with EFLAGS result
4019def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00004020 (implicit EFLAGS)),
4021 (IMUL16rmi addr:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00004022def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00004023 (implicit EFLAGS)),
4024 (IMUL32rmi addr:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00004025def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00004026 (implicit EFLAGS)),
4027 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00004028def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00004029 (implicit EFLAGS)),
4030 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4031
Dan Gohman99a12192009-03-04 19:44:21 +00004032// Optimize multiply by 2 with EFLAGS result.
Evan Cheng00cf7932009-01-27 03:30:42 +00004033let AddedComplexity = 2 in {
Dan Gohman99a12192009-03-04 19:44:21 +00004034def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
Evan Cheng00cf7932009-01-27 03:30:42 +00004035 (implicit EFLAGS)),
4036 (ADD16rr GR16:$src1, GR16:$src1)>;
4037
Dan Gohman99a12192009-03-04 19:44:21 +00004038def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
Evan Cheng00cf7932009-01-27 03:30:42 +00004039 (implicit EFLAGS)),
4040 (ADD32rr GR32:$src1, GR32:$src1)>;
4041}
4042
Dan Gohman99a12192009-03-04 19:44:21 +00004043// INC and DEC with EFLAGS result. Note that these do not set CF.
4044def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4045 (INC8r GR8:$src)>;
4046def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4047 (implicit EFLAGS)),
4048 (INC8m addr:$dst)>;
4049def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4050 (DEC8r GR8:$src)>;
4051def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4052 (implicit EFLAGS)),
4053 (DEC8m addr:$dst)>;
4054
4055def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
Dan Gohmaneebcac72009-03-05 21:32:23 +00004056 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
Dan Gohman99a12192009-03-04 19:44:21 +00004057def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4058 (implicit EFLAGS)),
Dan Gohmaneebcac72009-03-05 21:32:23 +00004059 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
Dan Gohman99a12192009-03-04 19:44:21 +00004060def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
Dan Gohmaneebcac72009-03-05 21:32:23 +00004061 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
Dan Gohman99a12192009-03-04 19:44:21 +00004062def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4063 (implicit EFLAGS)),
Dan Gohmaneebcac72009-03-05 21:32:23 +00004064 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
Dan Gohman99a12192009-03-04 19:44:21 +00004065
4066def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
Dan Gohmaneebcac72009-03-05 21:32:23 +00004067 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
Dan Gohman99a12192009-03-04 19:44:21 +00004068def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4069 (implicit EFLAGS)),
Dan Gohmaneebcac72009-03-05 21:32:23 +00004070 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
Dan Gohman99a12192009-03-04 19:44:21 +00004071def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
Dan Gohmaneebcac72009-03-05 21:32:23 +00004072 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
Dan Gohman99a12192009-03-04 19:44:21 +00004073def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4074 (implicit EFLAGS)),
Dan Gohmaneebcac72009-03-05 21:32:23 +00004075 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
Dan Gohman99a12192009-03-04 19:44:21 +00004076
Bill Wendlingf5399032008-12-12 21:15:41 +00004077//===----------------------------------------------------------------------===//
Dan Gohmanf17a25c2007-07-18 16:29:46 +00004078// Floating Point Stack Support
4079//===----------------------------------------------------------------------===//
4080
4081include "X86InstrFPStack.td"
4082
4083//===----------------------------------------------------------------------===//
Evan Cheng86ab7d32007-07-31 08:04:03 +00004084// X86-64 Support
4085//===----------------------------------------------------------------------===//
4086
Chris Lattner2de8d2b2008-01-10 05:50:42 +00004087include "X86Instr64bit.td"
Evan Cheng86ab7d32007-07-31 08:04:03 +00004088
4089//===----------------------------------------------------------------------===//
Dan Gohmanf17a25c2007-07-18 16:29:46 +00004090// XMM Floating point support (requires SSE / SSE2)
4091//===----------------------------------------------------------------------===//
4092
4093include "X86InstrSSE.td"
Evan Cheng5e4d1e72008-04-25 18:19:54 +00004094
4095//===----------------------------------------------------------------------===//
4096// MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4097//===----------------------------------------------------------------------===//
4098
4099include "X86InstrMMX.td"