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Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]5 <meta http-equiv="content-type" content="text/html; charset=utf-8">
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]6 <title>The LLVM Target-Independent Code Generator</title>
7 <link rel="stylesheet" href="llvm.css" type="text/css">
8</head>
9<body>
10
11<div class="doc_title">
12 The LLVM Target-Independent Code Generator
13</div>
14
15<ol>
16 <li><a href="#introduction">Introduction</a>
17 <ul>
18 <li><a href="#required">Required components in the code generator</a></li>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]19 <li><a href="#high-level-design">The high-level design of the code
20 generator</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]21 <li><a href="#tablegen">Using TableGen for target description</a></li>
22 </ul>
23 </li>
24 <li><a href="#targetdesc">Target description classes</a>
25 <ul>
26 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
27 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]28 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]29 <li><a href="#targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]30 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
31 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]32 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]33 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
34 </ul>
35 </li>
36 <li><a href="#codegendesc">Machine code description classes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]37 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]38 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]39 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
40 class</a></li>
41 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]42 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]43 </li>
44 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]45 <ul>
46 <li><a href="#instselect">Instruction Selection</a>
47 <ul>
48 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
49 <li><a href="#selectiondag_process">SelectionDAG Code Generation
50 Process</a></li>
51 <li><a href="#selectiondag_build">Initial SelectionDAG
52 Construction</a></li>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]53 <li><a href="#selectiondag_legalize_types">SelectionDAG LegalizeTypes Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]54 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
55 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]56 Phase: the DAG Combiner</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]57 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]58 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]59 Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]60 <li><a href="#selectiondag_future">Future directions for the
61 SelectionDAG</a></li>
62 </ul></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]63 <li><a href="#liveintervals">Live Intervals</a>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]64 <ul>
65 <li><a href="#livevariable_analysis">Live Variable Analysis</a></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]66 <li><a href="#liveintervals_analysis">Live Intervals Analysis</a></li>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]67 </ul></li>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]68 <li><a href="#regalloc">Register Allocation</a>
69 <ul>
70 <li><a href="#regAlloc_represent">How registers are represented in
71 LLVM</a></li>
72 <li><a href="#regAlloc_howTo">Mapping virtual registers to physical
73 registers</a></li>
74 <li><a href="#regAlloc_twoAddr">Handling two address instructions</a></li>
75 <li><a href="#regAlloc_ssaDecon">The SSA deconstruction phase</a></li>
76 <li><a href="#regAlloc_fold">Instruction folding</a></li>
77 <li><a href="#regAlloc_builtIn">Built in register allocators</a></li>
78 </ul></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]79 <li><a href="#codeemit">Code Emission</a>
80 <ul>
81 <li><a href="#codeemit_asm">Generating Assembly Code</a></li>
82 <li><a href="#codeemit_bin">Generating Binary Machine Code</a></li>
83 </ul></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]84 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]85 </li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]86 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]87 <ul>
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]88 <li><a href="#tailcallopt">Tail call optimization</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]89 <li><a href="#x86">The X86 backend</a></li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]90 <li><a href="#ppc">The PowerPC backend</a>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]91 <ul>
92 <li><a href="#ppc_abi">LLVM PowerPC ABI</a></li>
93 <li><a href="#ppc_frame">Frame Layout</a></li>
94 <li><a href="#ppc_prolog">Prolog/Epilog</a></li>
95 <li><a href="#ppc_dynamic">Dynamic Allocation</a></li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]96 </ul></li>
97 </ul></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]98
99</ol>
100
101<div class="doc_author">
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]102 <p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a>,
Jim Laskeyd201f4e2007-03-14 19:30:33 +0000[diff] [blame]103 <a href="mailto:isanbard@gmail.com">Bill Wendling</a>,
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]104 <a href="mailto:pronesto@gmail.com">Fernando Magno Quintao
Jim Laskeyd201f4e2007-03-14 19:30:33 +0000[diff] [blame]105 Pereira</a> and
106 <a href="mailto:jlaskey@mac.com">Jim Laskey</a></p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]107</div>
108
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]109<div class="doc_warning">
110 <p>Warning: This is a work in progress.</p>
111</div>
112
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]113<!-- *********************************************************************** -->
114<div class="doc_section">
115 <a name="introduction">Introduction</a>
116</div>
117<!-- *********************************************************************** -->
118
119<div class="doc_text">
120
121<p>The LLVM target-independent code generator is a framework that provides a
122suite of reusable components for translating the LLVM internal representation to
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]123the machine code for a specified target&mdash;either in assembly form (suitable
124for a static compiler) or in binary machine code format (usable for a JIT
125compiler). The LLVM target-independent code generator consists of five main
126components:</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]127
128<ol>
129<li><a href="#targetdesc">Abstract target description</a> interfaces which
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]130capture important properties about various aspects of the machine, independently
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]131of how they will be used. These interfaces are defined in
132<tt>include/llvm/Target/</tt>.</li>
133
134<li>Classes used to represent the <a href="#codegendesc">machine code</a> being
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]135generated for a target. These classes are intended to be abstract enough to
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]136represent the machine code for <i>any</i> target machine. These classes are
137defined in <tt>include/llvm/CodeGen/</tt>.</li>
138
139<li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
140various phases of native code generation (register allocation, scheduling, stack
141frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
142
143<li><a href="#targetimpls">Implementations of the abstract target description
144interfaces</a> for particular targets. These machine descriptions make use of
145the components provided by LLVM, and can optionally provide custom
146target-specific passes, to build complete code generators for a specific target.
147Target descriptions live in <tt>lib/Target/</tt>.</li>
148
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]149<li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
150completely target independent (it uses the <tt>TargetJITInfo</tt> structure to
151interface for target-specific issues. The code for the target-independent
152JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
153
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]154</ol>
155
156<p>
157Depending on which part of the code generator you are interested in working on,
158different pieces of this will be useful to you. In any case, you should be
159familiar with the <a href="#targetdesc">target description</a> and <a
160href="#codegendesc">machine code representation</a> classes. If you want to add
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]161a backend for a new target, you will need to <a href="#targetimpls">implement the
162target description</a> classes for your new target and understand the <a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]163href="LangRef.html">LLVM code representation</a>. If you are interested in
164implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
165should only depend on the target-description and machine code representation
166classes, ensuring that it is portable.
167</p>
168
169</div>
170
171<!-- ======================================================================= -->
172<div class="doc_subsection">
173 <a name="required">Required components in the code generator</a>
174</div>
175
176<div class="doc_text">
177
178<p>The two pieces of the LLVM code generator are the high-level interface to the
179code generator and the set of reusable components that can be used to build
180target-specific backends. The two most important interfaces (<a
181href="#targetmachine"><tt>TargetMachine</tt></a> and <a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]182href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]183required to be defined for a backend to fit into the LLVM system, but the others
184must be defined if the reusable code generator components are going to be
185used.</p>
186
187<p>This design has two important implications. The first is that LLVM can
188support completely non-traditional code generation targets. For example, the C
189backend does not require register allocation, instruction selection, or any of
190the other standard components provided by the system. As such, it only
191implements these two interfaces, and does its own thing. Another example of a
192code generator like this is a (purely hypothetical) backend that converts LLVM
193to the GCC RTL form and uses GCC to emit machine code for a target.</p>
194
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]195<p>This design also implies that it is possible to design and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]196implement radically different code generators in the LLVM system that do not
197make use of any of the built-in components. Doing so is not recommended at all,
198but could be required for radically different targets that do not fit into the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]199LLVM machine description model: FPGAs for example.</p>
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]200
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]201</div>
202
203<!-- ======================================================================= -->
204<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]205 <a name="high-level-design">The high-level design of the code generator</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]206</div>
207
208<div class="doc_text">
209
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]210<p>The LLVM target-independent code generator is designed to support efficient and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]211quality code generation for standard register-based microprocessors. Code
212generation in this model is divided into the following stages:</p>
213
214<ol>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]215<li><b><a href="#instselect">Instruction Selection</a></b> - This phase
216determines an efficient way to express the input LLVM code in the target
217instruction set.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]218This stage produces the initial code for the program in the target instruction
219set, then makes use of virtual registers in SSA form and physical registers that
220represent any required register assignments due to target constraints or calling
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]221conventions. This step turns the LLVM code into a DAG of target
222instructions.</li>
223
224<li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> - This
225phase takes the DAG of target instructions produced by the instruction selection
226phase, determines an ordering of the instructions, then emits the instructions
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]227as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering. Note
228that we describe this in the <a href="#instselect">instruction selection
229section</a> because it operates on a <a
230href="#selectiondag_intro">SelectionDAG</a>.
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]231</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]232
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]233<li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
234optional stage consists of a series of machine-code optimizations that
235operate on the SSA-form produced by the instruction selector. Optimizations
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]236like modulo-scheduling or peephole optimization work here.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]237</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]238
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]239<li><b><a href="#regalloc">Register Allocation</a></b> - The
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]240target code is transformed from an infinite virtual register file in SSA form
241to the concrete register file used by the target. This phase introduces spill
242code and eliminates all virtual register references from the program.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]243
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]244<li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]245machine code has been generated for the function and the amount of stack space
246required is known (used for LLVM alloca's and spill slots), the prolog and
247epilog code for the function can be inserted and "abstract stack location
248references" can be eliminated. This stage is responsible for implementing
249optimizations like frame-pointer elimination and stack packing.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]250
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]251<li><b><a href="#latemco">Late Machine Code Optimizations</a></b> - Optimizations
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]252that operate on "final" machine code can go here, such as spill code scheduling
253and peephole optimizations.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]254
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]255<li><b><a href="#codeemit">Code Emission</a></b> - The final stage actually
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]256puts out the code for the current function, either in the target assembler
257format or in machine code.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]258
259</ol>
260
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]261<p>The code generator is based on the assumption that the instruction selector
262will use an optimal pattern matching selector to create high-quality sequences of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]263native instructions. Alternative code generator designs based on pattern
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]264expansion and aggressive iterative peephole optimization are much slower. This
265design permits efficient compilation (important for JIT environments) and
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]266aggressive optimization (used when generating code offline) by allowing
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]267components of varying levels of sophistication to be used for any step of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]268compilation.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]269
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]270<p>In addition to these stages, target implementations can insert arbitrary
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]271target-specific passes into the flow. For example, the X86 target uses a
272special pass to handle the 80x87 floating point stack architecture. Other
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]273targets with unusual requirements can be supported with custom passes as
274needed.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]275
276</div>
277
278
279<!-- ======================================================================= -->
280<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]281 <a name="tablegen">Using TableGen for target description</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]282</div>
283
284<div class="doc_text">
285
Chris Lattner5489e932004-06-01 18:35:00 +0000[diff] [blame]286<p>The target description classes require a detailed description of the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]287architecture. These target descriptions often have a large amount of common
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]288information (e.g., an <tt>add</tt> instruction is almost identical to a
289<tt>sub</tt> instruction).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]290In order to allow the maximum amount of commonality to be factored out, the LLVM
291code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]292describe big chunks of the target machine, which allows the use of
293domain-specific and target-specific abstractions to reduce the amount of
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]294repetition.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]295
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]296<p>As LLVM continues to be developed and refined, we plan to move more and more
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]297of the target description to the <tt>.td</tt> form. Doing so gives us a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]298number of advantages. The most important is that it makes it easier to port
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]299LLVM because it reduces the amount of C++ code that has to be written, and the
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]300surface area of the code generator that needs to be understood before someone
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]301can get something working. Second, it makes it easier to change things. In
302particular, if tables and other things are all emitted by <tt>tblgen</tt>, we
303only need a change in one place (<tt>tblgen</tt>) to update all of the targets
304to a new interface.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]305
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]306</div>
307
308<!-- *********************************************************************** -->
309<div class="doc_section">
310 <a name="targetdesc">Target description classes</a>
311</div>
312<!-- *********************************************************************** -->
313
314<div class="doc_text">
315
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]316<p>The LLVM target description classes (located in the
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]317<tt>include/llvm/Target</tt> directory) provide an abstract description of the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]318target machine independent of any particular client. These classes are
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]319designed to capture the <i>abstract</i> properties of the target (such as the
320instructions and registers it has), and do not incorporate any particular pieces
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]321of code generation algorithms.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]322
323<p>All of the target description classes (except the <tt><a
324href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
325the concrete target implementation, and have virtual methods implemented. To
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]326get to these implementations, the <tt><a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]327href="#targetmachine">TargetMachine</a></tt> class provides accessors that
328should be implemented by the target.</p>
329
330</div>
331
332<!-- ======================================================================= -->
333<div class="doc_subsection">
334 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
335</div>
336
337<div class="doc_text">
338
339<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
340access the target-specific implementations of the various target description
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]341classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
342<tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
343designed to be specialized by
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]344a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
345implements the various virtual methods. The only required target description
346class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
347code generator components are to be used, the other interfaces should be
348implemented as well.</p>
349
350</div>
351
352
353<!-- ======================================================================= -->
354<div class="doc_subsection">
355 <a name="targetdata">The <tt>TargetData</tt> class</a>
356</div>
357
358<div class="doc_text">
359
360<p>The <tt>TargetData</tt> class is the only required target description class,
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]361and it is the only class that is not extensible (you cannot derived a new
362class from it). <tt>TargetData</tt> specifies information about how the target
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]363lays out memory for structures, the alignment requirements for various data
364types, the size of pointers in the target, and whether the target is
365little-endian or big-endian.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]366
367</div>
368
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]369<!-- ======================================================================= -->
370<div class="doc_subsection">
371 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
372</div>
373
374<div class="doc_text">
375
376<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
377selectors primarily to describe how LLVM code should be lowered to SelectionDAG
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]378operations. Among other things, this class indicates:</p>
379
380<ul>
381 <li>an initial register class to use for various <tt>ValueType</tt>s</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]382 <li>which operations are natively supported by the target machine</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]383 <li>the return type of <tt>setcc</tt> operations</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]384 <li>the type to use for shift amounts</li>
385 <li>various high-level characteristics, like whether it is profitable to turn
386 division by a constant into a multiplication sequence</li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]387</ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]388
389</div>
390
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]391<!-- ======================================================================= -->
392<div class="doc_subsection">
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]393 <a name="targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]394</div>
395
396<div class="doc_text">
397
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]398<p>The <tt>TargetRegisterInfo</tt> class is used to describe the register
399file of the target and any interactions between the registers.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]400
401<p>Registers in the code generator are represented in the code generator by
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]402unsigned integers. Physical registers (those that actually exist in the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]403description) are unique small numbers, and virtual registers are generally
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]404large. Note that register #0 is reserved as a flag value.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]405
406<p>Each register in the processor description has an associated
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]407<tt>TargetRegisterDesc</tt> entry, which provides a textual name for the
408register (used for assembly output and debugging dumps) and a set of aliases
409(used to indicate whether one register overlaps with another).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]410</p>
411
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]412<p>In addition to the per-register description, the <tt>TargetRegisterInfo</tt>
413class exposes a set of processor specific register classes (instances of the
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]414<tt>TargetRegisterClass</tt> class). Each register class contains sets of
415registers that have the same properties (for example, they are all 32-bit
416integer registers). Each SSA virtual register created by the instruction
417selector has an associated register class. When the register allocator runs, it
418replaces virtual registers with a physical register in the set.</p>
419
420<p>
421The target-specific implementations of these classes is auto-generated from a <a
422href="TableGenFundamentals.html">TableGen</a> description of the register file.
423</p>
424
425</div>
426
427<!-- ======================================================================= -->
428<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]429 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]430</div>
431
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]432<div class="doc_text">
433 <p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
434 instructions supported by the target. It is essentially an array of
435 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
436 instruction the target supports. Descriptors define things like the mnemonic
Chris Lattnera3079782005-07-19 03:37:48 +0000[diff] [blame]437 for the opcode, the number of operands, the list of implicit register uses
438 and defs, whether the instruction has certain target-independent properties
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]439 (accesses memory, is commutable, etc), and holds any target-specific
440 flags.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]441</div>
442
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]443<!-- ======================================================================= -->
444<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]445 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]446</div>
447
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]448<div class="doc_text">
449 <p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
450 stack frame layout of the target. It holds the direction of stack growth,
451 the known stack alignment on entry to each function, and the offset to the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]452 local area. The offset to the local area is the offset from the stack
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]453 pointer on function entry to the first location where function data (local
454 variables, spill locations) can be stored.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]455</div>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]456
457<!-- ======================================================================= -->
458<div class="doc_subsection">
459 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
460</div>
461
462<div class="doc_text">
Jim Laskey82d61a12005-10-17 12:19:10 +0000[diff] [blame]463 <p>The <tt>TargetSubtarget</tt> class is used to provide information about the
464 specific chip set being targeted. A sub-target informs code generation of
465 which instructions are supported, instruction latencies and instruction
466 execution itinerary; i.e., which processing units are used, in what order, and
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]467 for how long.</p>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]468</div>
469
470
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]471<!-- ======================================================================= -->
472<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]473 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]474</div>
475
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]476<div class="doc_text">
477 <p>The <tt>TargetJITInfo</tt> class exposes an abstract interface used by the
478 Just-In-Time code generator to perform target-specific activities, such as
479 emitting stubs. If a <tt>TargetMachine</tt> supports JIT code generation, it
480 should provide one of these objects through the <tt>getJITInfo</tt>
481 method.</p>
482</div>
483
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]484<!-- *********************************************************************** -->
485<div class="doc_section">
486 <a name="codegendesc">Machine code description classes</a>
487</div>
488<!-- *********************************************************************** -->
489
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]490<div class="doc_text">
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]491
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]492<p>At the high-level, LLVM code is translated to a machine specific
493representation formed out of
494<a href="#machinefunction"><tt>MachineFunction</tt></a>,
495<a href="#machinebasicblock"><tt>MachineBasicBlock</tt></a>, and <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]496href="#machineinstr"><tt>MachineInstr</tt></a> instances
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]497(defined in <tt>include/llvm/CodeGen</tt>). This representation is completely
498target agnostic, representing instructions in their most abstract form: an
499opcode and a series of operands. This representation is designed to support
500both an SSA representation for machine code, as well as a register allocated,
501non-SSA form.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]502
503</div>
504
505<!-- ======================================================================= -->
506<div class="doc_subsection">
507 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
508</div>
509
510<div class="doc_text">
511
512<p>Target machine instructions are represented as instances of the
513<tt>MachineInstr</tt> class. This class is an extremely abstract way of
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]514representing machine instructions. In particular, it only keeps track of
515an opcode number and a set of operands.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]516
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]517<p>The opcode number is a simple unsigned integer that only has meaning to a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]518specific backend. All of the instructions for a target should be defined in
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]519the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]520are auto-generated from this description. The <tt>MachineInstr</tt> class does
521not have any information about how to interpret the instruction (i.e., what the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]522semantics of the instruction are); for that you must refer to the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]523<tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
524
525<p>The operands of a machine instruction can be of several different types:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]526a register reference, a constant integer, a basic block reference, etc. In
527addition, a machine operand should be marked as a def or a use of the value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]528(though only registers are allowed to be defs).</p>
529
530<p>By convention, the LLVM code generator orders instruction operands so that
531all register definitions come before the register uses, even on architectures
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]532that are normally printed in other orders. For example, the SPARC add
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]533instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
534and stores the result into the "%i3" register. In the LLVM code generator,
535the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
536first.</p>
537
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]538<p>Keeping destination (definition) operands at the beginning of the operand
539list has several advantages. In particular, the debugging printer will print
540the instruction like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]541
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]542<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]543<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]544%r3 = add %i1, %i2
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]545</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]546</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]547
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]548<p>Also if the first operand is a def, it is easier to <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]549href="#buildmi">create instructions</a> whose only def is the first
550operand.</p>
551
552</div>
553
554<!-- _______________________________________________________________________ -->
555<div class="doc_subsubsection">
556 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
557</div>
558
559<div class="doc_text">
560
561<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
562located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
563<tt>BuildMI</tt> functions make it easy to build arbitrary machine
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]564instructions. Usage of the <tt>BuildMI</tt> functions look like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]565
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]566<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]567<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]568// Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
569// instruction. The '1' specifies how many operands will be added.
570MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]571
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]572// Create the same instr, but insert it at the end of a basic block.
573MachineBasicBlock &amp;MBB = ...
574BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]575
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]576// Create the same instr, but insert it before a specified iterator point.
577MachineBasicBlock::iterator MBBI = ...
578BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]579
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]580// Create a 'cmp Reg, 0' instruction, no destination reg.
581MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
582// Create an 'sahf' instruction which takes no operands and stores nothing.
583MI = BuildMI(X86::SAHF, 0);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]584
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]585// Create a self looping branch instruction.
586BuildMI(MBB, X86::JNE, 1).addMBB(&amp;MBB);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]587</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]588</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]589
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]590<p>The key thing to remember with the <tt>BuildMI</tt> functions is that you
591have to specify the number of operands that the machine instruction will take.
592This allows for efficient memory allocation. You also need to specify if
593operands default to be uses of values, not definitions. If you need to add a
594definition operand (other than the optional destination register), you must
595explicitly mark it as such:</p>
596
597<div class="doc_code">
598<pre>
599MI.addReg(Reg, MachineOperand::Def);
600</pre>
601</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]602
603</div>
604
605<!-- _______________________________________________________________________ -->
606<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]607 <a name="fixedregs">Fixed (preassigned) registers</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]608</div>
609
610<div class="doc_text">
611
612<p>One important issue that the code generator needs to be aware of is the
613presence of fixed registers. In particular, there are often places in the
614instruction stream where the register allocator <em>must</em> arrange for a
615particular value to be in a particular register. This can occur due to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]616limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]617with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
618conventions. In any case, the instruction selector should emit code that
619copies a virtual register into or out of a physical register when needed.</p>
620
621<p>For example, consider this simple LLVM example:</p>
622
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]623<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]624<pre>
Matthijs Kooijman61399af2008-06-04 15:46:35 +0000[diff] [blame]625define i32 @test(i32 %X, i32 %Y) {
626 %Z = udiv i32 %X, %Y
627 ret i32 %Z
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]628}
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]629</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]630</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]631
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]632<p>The X86 instruction selector produces this machine code for the <tt>div</tt>
633and <tt>ret</tt> (use
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]634"<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to get this):</p>
635
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]636<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]637<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]638;; Start of div
639%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
640%reg1027 = sar %reg1024, 31
641%EDX = mov %reg1027 ;; Sign extend X into EDX
642idiv %reg1025 ;; Divide by Y (in reg1025)
643%reg1026 = mov %EAX ;; Read the result (Z) out of EAX
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]644
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]645;; Start of ret
646%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
647ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]648</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]649</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]650
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]651<p>By the end of code generation, the register allocator has coalesced
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]652the registers and deleted the resultant identity moves producing the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]653following code:</p>
654
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]655<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]656<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]657;; X is in EAX, Y is in ECX
658mov %EAX, %EDX
659sar %EDX, 31
660idiv %ECX
661ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]662</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]663</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]664
665<p>This approach is extremely general (if it can handle the X86 architecture,
666it can handle anything!) and allows all of the target specific
667knowledge about the instruction stream to be isolated in the instruction
668selector. Note that physical registers should have a short lifetime for good
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]669code generation, and all physical registers are assumed dead on entry to and
670exit from basic blocks (before register allocation). Thus, if you need a value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]671to be live across basic block boundaries, it <em>must</em> live in a virtual
672register.</p>
673
674</div>
675
676<!-- _______________________________________________________________________ -->
677<div class="doc_subsubsection">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]678 <a name="ssa">Machine code in SSA form</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]679</div>
680
681<div class="doc_text">
682
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]683<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]684are maintained in SSA-form until register allocation happens. For the most
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]685part, this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]686become machine code PHI nodes, and virtual registers are only allowed to have a
687single definition.</p>
688
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]689<p>After register allocation, machine code is no longer in SSA-form because there
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]690are no virtual registers left in the code.</p>
691
692</div>
693
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]694<!-- ======================================================================= -->
695<div class="doc_subsection">
696 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
697</div>
698
699<div class="doc_text">
700
701<p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]702(<tt><a href="#machineinstr">MachineInstr</a></tt> instances). It roughly
703corresponds to the LLVM code input to the instruction selector, but there can be
704a one-to-many mapping (i.e. one LLVM basic block can map to multiple machine
705basic blocks). The <tt>MachineBasicBlock</tt> class has a
706"<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
707comes from.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]708
709</div>
710
711<!-- ======================================================================= -->
712<div class="doc_subsection">
713 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
714</div>
715
716<div class="doc_text">
717
718<p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]719(<tt><a href="#machinebasicblock">MachineBasicBlock</a></tt> instances). It
720corresponds one-to-one with the LLVM function input to the instruction selector.
721In addition to a list of basic blocks, the <tt>MachineFunction</tt> contains a
722a <tt>MachineConstantPool</tt>, a <tt>MachineFrameInfo</tt>, a
Chris Lattner534bcfb2007-12-31 04:16:08 +0000[diff] [blame]723<tt>MachineFunctionInfo</tt>, and a <tt>MachineRegisterInfo</tt>. See
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]724<tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]725
726</div>
727
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]728<!-- *********************************************************************** -->
729<div class="doc_section">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]730 <a name="codegenalgs">Target-independent code generation algorithms</a>
731</div>
732<!-- *********************************************************************** -->
733
734<div class="doc_text">
735
736<p>This section documents the phases described in the <a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]737href="#high-level-design">high-level design of the code generator</a>. It
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]738explains how they work and some of the rationale behind their design.</p>
739
740</div>
741
742<!-- ======================================================================= -->
743<div class="doc_subsection">
744 <a name="instselect">Instruction Selection</a>
745</div>
746
747<div class="doc_text">
748<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]749Instruction Selection is the process of translating LLVM code presented to the
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]750code generator into target-specific machine instructions. There are several
Evan Cheng77949352007-10-08 17:54:24 +0000[diff] [blame]751well-known ways to do this in the literature. LLVM uses a SelectionDAG based
752instruction selector.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]753</p>
754
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]755<p>Portions of the DAG instruction selector are generated from the target
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]756description (<tt>*.td</tt>) files. Our goal is for the entire instruction
Dan Gohmanfd800722007-12-13 20:43:47 +0000[diff] [blame]757selector to be generated from these <tt>.td</tt> files, though currently
758there are still things that require custom C++ code.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]759</div>
760
761<!-- _______________________________________________________________________ -->
762<div class="doc_subsubsection">
763 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
764</div>
765
766<div class="doc_text">
767
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]768<p>The SelectionDAG provides an abstraction for code representation in a way
769that is amenable to instruction selection using automatic techniques
770(e.g. dynamic-programming based optimal pattern matching selectors). It is also
771well-suited to other phases of code generation; in particular,
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]772instruction scheduling (SelectionDAG's are very close to scheduling DAGs
773post-selection). Additionally, the SelectionDAG provides a host representation
774where a large variety of very-low-level (but target-independent)
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]775<a href="#selectiondag_optimize">optimizations</a> may be
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]776performed; ones which require extensive information about the instructions
777efficiently supported by the target.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]778
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]779<p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]780<tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]781operation code (Opcode) that indicates what operation the node performs and
782the operands to the operation.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]783The various operation node types are described at the top of the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]784<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]785
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]786<p>Although most operations define a single value, each node in the graph may
787define multiple values. For example, a combined div/rem operation will define
788both the dividend and the remainder. Many other situations require multiple
789values as well. Each node also has some number of operands, which are edges
790to the node defining the used value. Because nodes may define multiple values,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]791edges are represented by instances of the <tt>SDValue</tt> class, which is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]792a <tt>&lt;SDNode, unsigned&gt;</tt> pair, indicating the node and result
793value being used, respectively. Each value produced by an <tt>SDNode</tt> has
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]794an associated <tt>MVT</tt> (Machine Value Type) indicating what the type of the
795value is.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]796
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]797<p>SelectionDAGs contain two different kinds of values: those that represent
798data flow and those that represent control flow dependencies. Data values are
799simple edges with an integer or floating point value type. Control edges are
800represented as "chain" edges which are of type <tt>MVT::Other</tt>. These edges
801provide an ordering between nodes that have side effects (such as
802loads, stores, calls, returns, etc). All nodes that have side effects should
803take a token chain as input and produce a new one as output. By convention,
804token chain inputs are always operand #0, and chain results are always the last
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]805value produced by an operation.</p>
806
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]807<p>A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
808always a marker node with an Opcode of <tt>ISD::EntryToken</tt>. The Root node
809is the final side-effecting node in the token chain. For example, in a single
810basic block function it would be the return node.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]811
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]812<p>One important concept for SelectionDAGs is the notion of a "legal" vs.
813"illegal" DAG. A legal DAG for a target is one that only uses supported
814operations and supported types. On a 32-bit PowerPC, for example, a DAG with
815a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that uses a
816SREM or UREM operation. The
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]817<a href="#selectinodag_legalize_types">legalize types</a> and
818<a href="#selectiondag_legalize">legalize operations</a> phases are
819responsible for turning an illegal DAG into a legal DAG.</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]820
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]821</div>
822
823<!-- _______________________________________________________________________ -->
824<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]825 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]826</div>
827
828<div class="doc_text">
829
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]830<p>SelectionDAG-based instruction selection consists of the following steps:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]831
832<ol>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]833<li><a href="#selectiondag_build">Build initial DAG</a> - This stage
834 performs a simple translation from the input LLVM code to an illegal
835 SelectionDAG.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]836<li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> - This stage
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]837 performs simple optimizations on the SelectionDAG to simplify it, and
838 recognize meta instructions (like rotates and <tt>div</tt>/<tt>rem</tt>
839 pairs) for targets that support these meta operations. This makes the
840 resultant code more efficient and the <a href="#selectiondag_select">select
841 instructions from DAG</a> phase (below) simpler.</li>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]842<li><a href="#selectiondag_legalize_types">Legalize SelectionDAG Types</a> - This
843 stage transforms SelectionDAG nodes to eliminate any types that are
844 unsupported on the target.</li>
845<li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> - The
846 SelectionDAG optimizer is run to clean up redundancies exposed
847 by type legalization.</li>
848<li><a href="#selectiondag_legalize">Legalize SelectionDAG Types</a> - This
849 stage transforms SelectionDAG nodes to eliminate any types that are
850 unsupported on the target.</li>
851<li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> - The
852 SelectionDAG optimizer is run to eliminate inefficiencies introduced
853 by operation legalization.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]854<li><a href="#selectiondag_select">Select instructions from DAG</a> - Finally,
855 the target instruction selector matches the DAG operations to target
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]856 instructions. This process translates the target-independent input DAG into
857 another DAG of target instructions.</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]858<li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]859 - The last phase assigns a linear order to the instructions in the
860 target-instruction DAG and emits them into the MachineFunction being
861 compiled. This step uses traditional prepass scheduling techniques.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]862</ol>
863
864<p>After all of these steps are complete, the SelectionDAG is destroyed and the
865rest of the code generation passes are run.</p>
866
Chris Lattnerdf921f02005-10-17 01:40:33 +0000[diff] [blame]867<p>One great way to visualize what is going on here is to take advantage of a
Dan Gohman8c9c55f2008-09-10 22:23:41 +0000[diff] [blame]868few LLC command line options. The following options pop up a window displaying
869the SelectionDAG at specific times (if you only get errors printed to the console
870while using this, you probably
871<a href="ProgrammersManual.html#ViewGraph">need to configure your system</a> to
872add support for it).</p>
873
874<ul>
875<li><tt>-view-dag-combine1-dags</tt> displays the DAG after being built, before
876 the first optimization pass.</li>
877<li><tt>-view-legalize-dags</tt> displays the DAG before Legalization.</li>
878<li><tt>-view-dag-combine2-dags</tt> displays the DAG before the second
879 optimization pass.</li>
880<li><tt>-view-isel-dags</tt> displays the DAG before the Select phase.</li>
881<li><tt>-view-sched-dags</tt> displays the DAG before Scheduling.</li>
882</ul>
883
884<p>The <tt>-view-sunit-dags</tt> displays the Scheduler's dependency graph.
885This graph is based on the final SelectionDAG, with nodes that must be
886scheduled together bundled into a single scheduling-unit node, and with
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]887immediate operands and other nodes that aren't relevant for scheduling
Dan Gohman8c9c55f2008-09-10 22:23:41 +0000[diff] [blame]888omitted.
Dan Gohmane9bb13d2007-10-15 21:07:59 +0000[diff] [blame]889</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]890
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]891</div>
892
893<!-- _______________________________________________________________________ -->
894<div class="doc_subsubsection">
895 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
896</div>
897
898<div class="doc_text">
899
Bill Wendling16448772006-08-28 03:04:05 +0000[diff] [blame]900<p>The initial SelectionDAG is na&iuml;vely peephole expanded from the LLVM
901input by the <tt>SelectionDAGLowering</tt> class in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]902<tt>lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp</tt> file. The intent of this
903pass is to expose as much low-level, target-specific details to the SelectionDAG
904as possible. This pass is mostly hard-coded (e.g. an LLVM <tt>add</tt> turns
Dan Gohman24585cb2008-10-03 00:07:11 +0000[diff] [blame]905into an <tt>SDNode add</tt> while a <tt>getelementptr</tt> is expanded into the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]906obvious arithmetic). This pass requires target-specific hooks to lower calls,
907returns, varargs, etc. For these features, the
908<tt><a href="#targetlowering">TargetLowering</a></tt> interface is used.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]909
910</div>
911
912<!-- _______________________________________________________________________ -->
913<div class="doc_subsubsection">
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]914 <a name="selectiondag_legalize_types">SelectionDAG LegalizeTypes Phase</a>
915</div>
916
917<div class="doc_text">
918
919<p>The Legalize phase is in charge of converting a DAG to only use the types
920that are natively supported by the target.</p>
921
922<p>There are two main ways of converting values of unsupported scalar types
923 to values of supported types: converting small types to
924 larger types ("promoting"), and breaking up large integer types
925 into smaller ones ("expanding"). For example, a target might require
926 that all f32 values are promoted to f64 and that all i1/i8/i16 values
927 are promoted to i32. The same target might require that all i64 values
928 be expanded into pairs of i32 values. These changes can insert sign and
929 zero extensions as needed to make sure that the final code has the same
930 behavior as the input.</p>
931
932<p>There are two main ways of converting values of unsupported vector types
933 to value of supported types: splitting vector types, multiple times if
934 necessary, until a legal type is found, and extending vector types by
935 adding elements to the end to round them out to legal types ("widening").
936 If a vector gets split all the way down to single-element parts with
937 no supported vector type being found, the elements are converted to
938 scalars ("scalarizing").</p>
939
940<p>A target implementation tells the legalizer which types are supported
941 (and which register class to use for them) by calling the
942 <tt>addRegisterClass</tt> method in its TargetLowering constructor.</p>
943
944</div>
945
946<!-- _______________________________________________________________________ -->
947<div class="doc_subsubsection">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]948 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
949</div>
950
951<div class="doc_text">
952
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]953<p>The Legalize phase is in charge of converting a DAG to only use the
954operations that are natively supported by the target.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]955
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]956<p>Targets often have weird constraints, such as not supporting every
957 operation on every supported datatype (e.g. X86 does not support byte
958 conditional moves and PowerPC does not support sign-extending loads from
959 a 16-bit memory location). Legalize takes care of this by open-coding
960 another sequence of operations to emulate the operation ("expansion"), by
961 promoting one type to a larger type that supports the operation
962 ("promotion"), or by using a target-specific hook to implement the
963 legalization ("custom").</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]964
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]965<p>A target implementation tells the legalizer which operations are not
966 supported (and which of the above three actions to take) by calling the
967 <tt>setOperationAction</tt> method in its <tt>TargetLowering</tt>
968 constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]969
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]970<p>Prior to the existence of the Legalize passes, we required that every target
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]971<a href="#selectiondag_optimize">selector</a> supported and handled every
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]972operator and type even if they are not natively supported. The introduction of
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]973the Legalize phases allows all of the canonicalization patterns to be shared
974across targets, and makes it very easy to optimize the canonicalized code
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]975because it is still in the form of a DAG.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]976
977</div>
978
979<!-- _______________________________________________________________________ -->
980<div class="doc_subsubsection">
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]981 <a name="selectiondag_optimize">SelectionDAG Optimization Phase: the DAG
982 Combiner</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]983</div>
984
985<div class="doc_text">
986
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]987<p>The SelectionDAG optimization phase is run multiple times for code generation,
988immediately after the DAG is built and once after each legalization. The first
989run of the pass allows the initial code to be cleaned up (e.g. performing
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]990optimizations that depend on knowing that the operators have restricted type
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]991inputs). Subsequent runs of the pass clean up the messy code generated by the
992Legalize passes, which allows Legalize to be very simple (it can focus on making
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]993code legal instead of focusing on generating <em>good</em> and legal code).</p>
994
995<p>One important class of optimizations performed is optimizing inserted sign
996and zero extension instructions. We currently use ad-hoc techniques, but could
997move to more rigorous techniques in the future. Here are some good papers on
998the subject:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]999
1000<p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1001 "<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
1002 integer arithmetic</a>"<br>
1003 Kevin Redwine and Norman Ramsey<br>
1004 International Conference on Compiler Construction (CC) 2004
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1005</p>
1006
1007
1008<p>
1009 "<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
1010 sign extension elimination</a>"<br>
1011 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
1012 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
1013 and Implementation.
1014</p>
1015
1016</div>
1017
1018<!-- _______________________________________________________________________ -->
1019<div class="doc_subsubsection">
1020 <a name="selectiondag_select">SelectionDAG Select Phase</a>
1021</div>
1022
1023<div class="doc_text">
1024
1025<p>The Select phase is the bulk of the target-specific code for instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1026selection. This phase takes a legal SelectionDAG as input, pattern matches the
1027instructions supported by the target to this DAG, and produces a new DAG of
1028target code. For example, consider the following LLVM fragment:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1029
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1030<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1031<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1032%t1 = add float %W, %X
1033%t2 = mul float %t1, %Y
1034%t3 = add float %t2, %Z
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1035</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1036</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1037
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1038<p>This LLVM code corresponds to a SelectionDAG that looks basically like
1039this:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1040
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1041<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1042<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1043(fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1044</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1045</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1046
Chris Lattnera1ff9312005-10-17 15:19:24 +0000[diff] [blame]1047<p>If a target supports floating point multiply-and-add (FMA) operations, one
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1048of the adds can be merged with the multiply. On the PowerPC, for example, the
1049output of the instruction selector might look like this DAG:</p>
1050
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1051<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1052<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1053(FMADDS (FADDS W, X), Y, Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1054</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1055</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1056
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1057<p>The <tt>FMADDS</tt> instruction is a ternary instruction that multiplies its
1058first two operands and adds the third (as single-precision floating-point
1059numbers). The <tt>FADDS</tt> instruction is a simple binary single-precision
1060add instruction. To perform this pattern match, the PowerPC backend includes
1061the following instruction definitions:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1062
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1063<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1064<pre>
1065def FMADDS : AForm_1&lt;59, 29,
1066 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1067 "fmadds $FRT, $FRA, $FRC, $FRB",
1068 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1069 F4RC:$FRB))</b>]&gt;;
1070def FADDS : AForm_2&lt;59, 21,
1071 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1072 "fadds $FRT, $FRA, $FRB",
1073 [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]&gt;;
1074</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1075</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1076
1077<p>The portion of the instruction definition in bold indicates the pattern used
1078to match the instruction. The DAG operators (like <tt>fmul</tt>/<tt>fadd</tt>)
1079are defined in the <tt>lib/Target/TargetSelectionDAG.td</tt> file.
Dan Gohmana7ab2bf2008-11-24 16:35:31 +0000[diff] [blame]1080"<tt>F4RC</tt>" is the register class of the input and result values.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1081
1082<p>The TableGen DAG instruction selector generator reads the instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1083patterns in the <tt>.td</tt> file and automatically builds parts of the pattern
1084matching code for your target. It has the following strengths:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1085
1086<ul>
1087<li>At compiler-compiler time, it analyzes your instruction patterns and tells
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1088 you if your patterns make sense or not.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1089<li>It can handle arbitrary constraints on operands for the pattern match. In
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1090 particular, it is straight-forward to say things like "match any immediate
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1091 that is a 13-bit sign-extended value". For examples, see the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1092 <tt>immSExt16</tt> and related <tt>tblgen</tt> classes in the PowerPC
1093 backend.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1094<li>It knows several important identities for the patterns defined. For
1095 example, it knows that addition is commutative, so it allows the
1096 <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
1097 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1098 to specially handle this case.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1099<li>It has a full-featured type-inferencing system. In particular, you should
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1100 rarely have to explicitly tell the system what type parts of your patterns
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1101 are. In the <tt>FMADDS</tt> case above, we didn't have to tell
1102 <tt>tblgen</tt> that all of the nodes in the pattern are of type 'f32'. It
1103 was able to infer and propagate this knowledge from the fact that
1104 <tt>F4RC</tt> has type 'f32'.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1105<li>Targets can define their own (and rely on built-in) "pattern fragments".
1106 Pattern fragments are chunks of reusable patterns that get inlined into your
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1107 patterns during compiler-compiler time. For example, the integer
1108 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment that
1109 expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not have a
1110 native '<tt>not</tt>' operation. Targets can define their own short-hand
1111 fragments as they see fit. See the definition of '<tt>not</tt>' and
1112 '<tt>ineg</tt>' for examples.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1113<li>In addition to instructions, targets can specify arbitrary patterns that
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1114 map to one or more instructions using the 'Pat' class. For example,
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1115 the PowerPC has no way to load an arbitrary integer immediate into a
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1116 register in one instruction. To tell tblgen how to do this, it defines:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1117 <br>
1118 <br>
1119 <div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1120 <pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1121// Arbitrary immediate support. Implement in terms of LIS/ORI.
1122def : Pat&lt;(i32 imm:$imm),
1123 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))&gt;;
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1124 </pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1125 </div>
1126 <br>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1127 If none of the single-instruction patterns for loading an immediate into a
1128 register match, this will be used. This rule says "match an arbitrary i32
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1129 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and an
1130 <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to the
1131 left 16 bits') instruction". To make this work, the
1132 <tt>LO16</tt>/<tt>HI16</tt> node transformations are used to manipulate the
1133 input immediate (in this case, take the high or low 16-bits of the
1134 immediate).</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1135<li>While the system does automate a lot, it still allows you to write custom
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1136 C++ code to match special cases if there is something that is hard to
1137 express.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1138</ul>
1139
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1140<p>While it has many strengths, the system currently has some limitations,
1141primarily because it is a work in progress and is not yet finished:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1142
1143<ul>
1144<li>Overall, there is no way to define or match SelectionDAG nodes that define
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1145 multiple values (e.g. <tt>ADD_PARTS</tt>, <tt>LOAD</tt>, <tt>CALL</tt>,
1146 etc). This is the biggest reason that you currently still <em>have to</em>
1147 write custom C++ code for your instruction selector.</li>
1148<li>There is no great way to support matching complex addressing modes yet. In
1149 the future, we will extend pattern fragments to allow them to define
1150 multiple values (e.g. the four operands of the <a href="#x86_memory">X86
Dan Gohmanfd800722007-12-13 20:43:47 +0000[diff] [blame]1151 addressing mode</a>, which are currently matched with custom C++ code).
1152 In addition, we'll extend fragments so that a
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1153 fragment can match multiple different patterns.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1154<li>We don't automatically infer flags like isStore/isLoad yet.</li>
1155<li>We don't automatically generate the set of supported registers and
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1156 operations for the <a href="#selectiondag_legalize">Legalizer</a> yet.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1157<li>We don't have a way of tying in custom legalized nodes yet.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1158</ul>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1159
1160<p>Despite these limitations, the instruction selector generator is still quite
1161useful for most of the binary and logical operations in typical instruction
1162sets. If you run into any problems or can't figure out how to do something,
1163please let Chris know!</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1164
1165</div>
1166
1167<!-- _______________________________________________________________________ -->
1168<div class="doc_subsubsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1169 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1170</div>
1171
1172<div class="doc_text">
1173
1174<p>The scheduling phase takes the DAG of target instructions from the selection
1175phase and assigns an order. The scheduler can pick an order depending on
1176various constraints of the machines (i.e. order for minimal register pressure or
1177try to cover instruction latencies). Once an order is established, the DAG is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1178converted to a list of <tt><a href="#machineinstr">MachineInstr</a></tt>s and
1179the SelectionDAG is destroyed.</p>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1180
Jeff Cohen0b81cda2005-10-24 16:54:55 +0000[diff] [blame]1181<p>Note that this phase is logically separate from the instruction selection
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]1182phase, but is tied to it closely in the code because it operates on
1183SelectionDAGs.</p>
1184
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1185</div>
1186
1187<!-- _______________________________________________________________________ -->
1188<div class="doc_subsubsection">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1189 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
1190</div>
1191
1192<div class="doc_text">
1193
1194<ol>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1195<li>Optional function-at-a-time selection.</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1196<li>Auto-generate entire selector from <tt>.td</tt> file.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1197</ol>
1198
1199</div>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1200
1201<!-- ======================================================================= -->
1202<div class="doc_subsection">
1203 <a name="ssamco">SSA-based Machine Code Optimizations</a>
1204</div>
1205<div class="doc_text"><p>To Be Written</p></div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1206
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1207<!-- ======================================================================= -->
1208<div class="doc_subsection">
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1209 <a name="liveintervals">Live Intervals</a>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1210</div>
1211
1212<div class="doc_text">
1213
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1214<p>Live Intervals are the ranges (intervals) where a variable is <i>live</i>.
1215They are used by some <a href="#regalloc">register allocator</a> passes to
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1216determine if two or more virtual registers which require the same physical
Bill Wendling41b32522006-09-07 08:39:35 +0000[diff] [blame]1217register are live at the same point in the program (i.e., they conflict). When
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1218this situation occurs, one virtual register must be <i>spilled</i>.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1219
1220</div>
1221
1222<!-- _______________________________________________________________________ -->
1223<div class="doc_subsubsection">
1224 <a name="livevariable_analysis">Live Variable Analysis</a>
1225</div>
1226
1227<div class="doc_text">
1228
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1229<p>The first step in determining the live intervals of variables is to
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1230calculate the set of registers that are immediately dead after the
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1231instruction (i.e., the instruction calculates the value, but it is
1232never used) and the set of registers that are used by the instruction,
1233but are never used after the instruction (i.e., they are killed). Live
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1234variable information is computed for each <i>virtual</i> register and
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1235<i>register allocatable</i> physical register in the function. This
1236is done in a very efficient manner because it uses SSA to sparsely
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1237compute lifetime information for virtual registers (which are in SSA
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1238form) and only has to track physical registers within a block. Before
1239register allocation, LLVM can assume that physical registers are only
1240live within a single basic block. This allows it to do a single,
1241local analysis to resolve physical register lifetimes within each
1242basic block. If a physical register is not register allocatable (e.g.,
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1243a stack pointer or condition codes), it is not tracked.</p>
1244
1245<p>Physical registers may be live in to or out of a function. Live in values
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1246are typically arguments in registers. Live out values are typically return
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1247values in registers. Live in values are marked as such, and are given a dummy
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1248"defining" instruction during live intervals analysis. If the last basic block
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1249of a function is a <tt>return</tt>, then it's marked as using all live out
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1250values in the function.</p>
1251
1252<p><tt>PHI</tt> nodes need to be handled specially, because the calculation
1253of the live variable information from a depth first traversal of the CFG of
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1254the function won't guarantee that a virtual register used by the <tt>PHI</tt>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1255node is defined before it's used. When a <tt>PHI</tt> node is encountered, only
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1256the definition is handled, because the uses will be handled in other basic
1257blocks.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1258
1259<p>For each <tt>PHI</tt> node of the current basic block, we simulate an
1260assignment at the end of the current basic block and traverse the successor
1261basic blocks. If a successor basic block has a <tt>PHI</tt> node and one of
1262the <tt>PHI</tt> node's operands is coming from the current basic block,
1263then the variable is marked as <i>alive</i> within the current basic block
1264and all of its predecessor basic blocks, until the basic block with the
1265defining instruction is encountered.</p>
1266
1267</div>
1268
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1269<!-- _______________________________________________________________________ -->
1270<div class="doc_subsubsection">
1271 <a name="liveintervals_analysis">Live Intervals Analysis</a>
1272</div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1273
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1274<div class="doc_text">
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1275
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1276<p>We now have the information available to perform the live intervals analysis
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1277and build the live intervals themselves. We start off by numbering the basic
1278blocks and machine instructions. We then handle the "live-in" values. These
1279are in physical registers, so the physical register is assumed to be killed by
1280the end of the basic block. Live intervals for virtual registers are computed
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1281for some ordering of the machine instructions <tt>[1, N]</tt>. A live interval
Dan Gohman364a39f2008-10-14 17:00:38 +0000[diff] [blame]1282is an interval <tt>[i, j)</tt>, where <tt>1 &lt;= i &lt;= j &lt; N</tt>, for which a
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1283variable is live.</p>
1284
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1285<p><i><b>More to come...</b></i></p>
1286
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1287</div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1288
1289<!-- ======================================================================= -->
1290<div class="doc_subsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1291 <a name="regalloc">Register Allocation</a>
1292</div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1293
1294<div class="doc_text">
1295
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1296<p>The <i>Register Allocation problem</i> consists in mapping a program
1297<i>P<sub>v</sub></i>, that can use an unbounded number of virtual
1298registers, to a program <i>P<sub>p</sub></i> that contains a finite
1299(possibly small) number of physical registers. Each target architecture has
1300a different number of physical registers. If the number of physical
1301registers is not enough to accommodate all the virtual registers, some of
1302them will have to be mapped into memory. These virtuals are called
1303<i>spilled virtuals</i>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1304
1305</div>
1306
1307<!-- _______________________________________________________________________ -->
1308
1309<div class="doc_subsubsection">
1310 <a name="regAlloc_represent">How registers are represented in LLVM</a>
1311</div>
1312
1313<div class="doc_text">
1314
1315<p>In LLVM, physical registers are denoted by integer numbers that
1316normally range from 1 to 1023. To see how this numbering is defined
1317for a particular architecture, you can read the
1318<tt>GenRegisterNames.inc</tt> file for that architecture. For
1319instance, by inspecting
1320<tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the 32-bit
1321register <tt>EAX</tt> is denoted by 15, and the MMX register
1322<tt>MM0</tt> is mapped to 48.</p>
1323
1324<p>Some architectures contain registers that share the same physical
1325location. A notable example is the X86 platform. For instance, in the
1326X86 architecture, the registers <tt>EAX</tt>, <tt>AX</tt> and
1327<tt>AL</tt> share the first eight bits. These physical registers are
1328marked as <i>aliased</i> in LLVM. Given a particular architecture, you
1329can check which registers are aliased by inspecting its
1330<tt>RegisterInfo.td</tt> file. Moreover, the method
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1331<tt>TargetRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1332all the physical registers aliased to the register <tt>p_reg</tt>.</p>
1333
1334<p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>.
1335Elements in the same register class are functionally equivalent, and can
1336be interchangeably used. Each virtual register can only be mapped to
1337physical registers of a particular class. For instance, in the X86
1338architecture, some virtuals can only be allocated to 8 bit registers.
1339A register class is described by <tt>TargetRegisterClass</tt> objects.
1340To discover if a virtual register is compatible with a given physical,
1341this code can be used:
1342</p>
1343
1344<div class="doc_code">
1345<pre>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1346bool RegMapping_Fer::compatible_class(MachineFunction &amp;mf,
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1347 unsigned v_reg,
1348 unsigned p_reg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1349 assert(TargetRegisterInfo::isPhysicalRegister(p_reg) &amp;&amp;
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1350 "Target register must be physical");
Chris Lattner534bcfb2007-12-31 04:16:08 +0000[diff] [blame]1351 const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
1352 return trc-&gt;contains(p_reg);
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1353}
1354</pre>
1355</div>
1356
1357<p>Sometimes, mostly for debugging purposes, it is useful to change
1358the number of physical registers available in the target
1359architecture. This must be done statically, inside the
1360<tt>TargetRegsterInfo.td</tt> file. Just <tt>grep</tt> for
1361<tt>RegisterClass</tt>, the last parameter of which is a list of
1362registers. Just commenting some out is one simple way to avoid them
1363being used. A more polite way is to explicitly exclude some registers
1364from the <i>allocation order</i>. See the definition of the
1365<tt>GR</tt> register class in
1366<tt>lib/Target/IA64/IA64RegisterInfo.td</tt> for an example of this
1367(e.g., <tt>numReservedRegs</tt> registers are hidden.)</p>
1368
1369<p>Virtual registers are also denoted by integer numbers. Contrary to
1370physical registers, different virtual registers never share the same
1371number. The smallest virtual register is normally assigned the number
13721024. This may change, so, in order to know which is the first virtual
1373register, you should access
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1374<tt>TargetRegisterInfo::FirstVirtualRegister</tt>. Any register whose
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1375number is greater than or equal to
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1376<tt>TargetRegisterInfo::FirstVirtualRegister</tt> is considered a virtual
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1377register. Whereas physical registers are statically defined in a
1378<tt>TargetRegisterInfo.td</tt> file and cannot be created by the
1379application developer, that is not the case with virtual registers.
1380In order to create new virtual registers, use the method
Chris Lattner534bcfb2007-12-31 04:16:08 +0000[diff] [blame]1381<tt>MachineRegisterInfo::createVirtualRegister()</tt>. This method will return a
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1382virtual register with the highest code.
1383</p>
1384
1385<p>Before register allocation, the operands of an instruction are
1386mostly virtual registers, although physical registers may also be
1387used. In order to check if a given machine operand is a register, use
1388the boolean function <tt>MachineOperand::isRegister()</tt>. To obtain
1389the integer code of a register, use
1390<tt>MachineOperand::getReg()</tt>. An instruction may define or use a
1391register. For instance, <tt>ADD reg:1026 := reg:1025 reg:1024</tt>
1392defines the registers 1024, and uses registers 1025 and 1026. Given a
1393register operand, the method <tt>MachineOperand::isUse()</tt> informs
1394if that register is being used by the instruction. The method
1395<tt>MachineOperand::isDef()</tt> informs if that registers is being
1396defined.</p>
1397
Gabor Greif04367bf2007-07-06 22:07:22 +0000[diff] [blame]1398<p>We will call physical registers present in the LLVM bitcode before
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1399register allocation <i>pre-colored registers</i>. Pre-colored
1400registers are used in many different situations, for instance, to pass
1401parameters of functions calls, and to store results of particular
1402instructions. There are two types of pre-colored registers: the ones
1403<i>implicitly</i> defined, and those <i>explicitly</i>
1404defined. Explicitly defined registers are normal operands, and can be
1405accessed with <tt>MachineInstr::getOperand(int)::getReg()</tt>. In
1406order to check which registers are implicitly defined by an
1407instruction, use the
1408<tt>TargetInstrInfo::get(opcode)::ImplicitDefs</tt>, where
1409<tt>opcode</tt> is the opcode of the target instruction. One important
1410difference between explicit and implicit physical registers is that
1411the latter are defined statically for each instruction, whereas the
1412former may vary depending on the program being compiled. For example,
1413an instruction that represents a function call will always implicitly
1414define or use the same set of physical registers. To read the
1415registers implicitly used by an instruction, use
1416<tt>TargetInstrInfo::get(opcode)::ImplicitUses</tt>. Pre-colored
1417registers impose constraints on any register allocation algorithm. The
1418register allocator must make sure that none of them is been
1419overwritten by the values of virtual registers while still alive.</p>
1420
1421</div>
1422
1423<!-- _______________________________________________________________________ -->
1424
1425<div class="doc_subsubsection">
1426 <a name="regAlloc_howTo">Mapping virtual registers to physical registers</a>
1427</div>
1428
1429<div class="doc_text">
1430
1431<p>There are two ways to map virtual registers to physical registers (or to
1432memory slots). The first way, that we will call <i>direct mapping</i>,
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1433is based on the use of methods of the classes <tt>TargetRegisterInfo</tt>,
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1434and <tt>MachineOperand</tt>. The second way, that we will call
1435<i>indirect mapping</i>, relies on the <tt>VirtRegMap</tt> class in
1436order to insert loads and stores sending and getting values to and from
1437memory.</p>
1438
1439<p>The direct mapping provides more flexibility to the developer of
1440the register allocator; however, it is more error prone, and demands
1441more implementation work. Basically, the programmer will have to
1442specify where load and store instructions should be inserted in the
1443target function being compiled in order to get and store values in
1444memory. To assign a physical register to a virtual register present in
1445a given operand, use <tt>MachineOperand::setReg(p_reg)</tt>. To insert
1446a store instruction, use
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1447<tt>TargetRegisterInfo::storeRegToStackSlot(...)</tt>, and to insert a load
1448instruction, use <tt>TargetRegisterInfo::loadRegFromStackSlot</tt>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1449
1450<p>The indirect mapping shields the application developer from the
1451complexities of inserting load and store instructions. In order to map
1452a virtual register to a physical one, use
1453<tt>VirtRegMap::assignVirt2Phys(vreg, preg)</tt>. In order to map a
1454certain virtual register to memory, use
1455<tt>VirtRegMap::assignVirt2StackSlot(vreg)</tt>. This method will
1456return the stack slot where <tt>vreg</tt>'s value will be located. If
1457it is necessary to map another virtual register to the same stack
1458slot, use <tt>VirtRegMap::assignVirt2StackSlot(vreg,
1459stack_location)</tt>. One important point to consider when using the
1460indirect mapping, is that even if a virtual register is mapped to
1461memory, it still needs to be mapped to a physical register. This
1462physical register is the location where the virtual register is
1463supposed to be found before being stored or after being reloaded.</p>
1464
1465<p>If the indirect strategy is used, after all the virtual registers
1466have been mapped to physical registers or stack slots, it is necessary
1467to use a spiller object to place load and store instructions in the
1468code. Every virtual that has been mapped to a stack slot will be
1469stored to memory after been defined and will be loaded before being
1470used. The implementation of the spiller tries to recycle load/store
1471instructions, avoiding unnecessary instructions. For an example of how
1472to invoke the spiller, see
1473<tt>RegAllocLinearScan::runOnMachineFunction</tt> in
1474<tt>lib/CodeGen/RegAllocLinearScan.cpp</tt>.</p>
1475
1476</div>
1477
1478<!-- _______________________________________________________________________ -->
1479<div class="doc_subsubsection">
1480 <a name="regAlloc_twoAddr">Handling two address instructions</a>
1481</div>
1482
1483<div class="doc_text">
1484
1485<p>With very rare exceptions (e.g., function calls), the LLVM machine
1486code instructions are three address instructions. That is, each
1487instruction is expected to define at most one register, and to use at
1488most two registers. However, some architectures use two address
1489instructions. In this case, the defined register is also one of the
1490used register. For instance, an instruction such as <tt>ADD %EAX,
1491%EBX</tt>, in X86 is actually equivalent to <tt>%EAX = %EAX +
1492%EBX</tt>.</p>
1493
1494<p>In order to produce correct code, LLVM must convert three address
1495instructions that represent two address instructions into true two
1496address instructions. LLVM provides the pass
1497<tt>TwoAddressInstructionPass</tt> for this specific purpose. It must
1498be run before register allocation takes place. After its execution,
1499the resulting code may no longer be in SSA form. This happens, for
1500instance, in situations where an instruction such as <tt>%a = ADD %b
1501%c</tt> is converted to two instructions such as:</p>
1502
1503<div class="doc_code">
1504<pre>
1505%a = MOVE %b
Dan Gohman03e58572008-06-13 17:55:57 +0000[diff] [blame]1506%a = ADD %a %c
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1507</pre>
1508</div>
1509
1510<p>Notice that, internally, the second instruction is represented as
Dan Gohman03e58572008-06-13 17:55:57 +0000[diff] [blame]1511<tt>ADD %a[def/use] %c</tt>. I.e., the register operand <tt>%a</tt> is
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1512both used and defined by the instruction.</p>
1513
1514</div>
1515
1516<!-- _______________________________________________________________________ -->
1517<div class="doc_subsubsection">
1518 <a name="regAlloc_ssaDecon">The SSA deconstruction phase</a>
1519</div>
1520
1521<div class="doc_text">
1522
1523<p>An important transformation that happens during register allocation is called
1524the <i>SSA Deconstruction Phase</i>. The SSA form simplifies many
1525analyses that are performed on the control flow graph of
1526programs. However, traditional instruction sets do not implement
1527PHI instructions. Thus, in order to generate executable code, compilers
1528must replace PHI instructions with other instructions that preserve their
1529semantics.</p>
1530
1531<p>There are many ways in which PHI instructions can safely be removed
1532from the target code. The most traditional PHI deconstruction
1533algorithm replaces PHI instructions with copy instructions. That is
1534the strategy adopted by LLVM. The SSA deconstruction algorithm is
Dan Gohmanfd9ddc02008-11-24 16:45:15 +0000[diff] [blame]1535implemented in <tt>lib/CodeGen/PHIElimination.cpp</tt>. In order to
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1536invoke this pass, the identifier <tt>PHIEliminationID</tt> must be
1537marked as required in the code of the register allocator.</p>
1538
1539</div>
1540
1541<!-- _______________________________________________________________________ -->
1542<div class="doc_subsubsection">
1543 <a name="regAlloc_fold">Instruction folding</a>
1544</div>
1545
1546<div class="doc_text">
1547
1548<p><i>Instruction folding</i> is an optimization performed during
1549register allocation that removes unnecessary copy instructions. For
1550instance, a sequence of instructions such as:</p>
1551
1552<div class="doc_code">
1553<pre>
1554%EBX = LOAD %mem_address
1555%EAX = COPY %EBX
1556</pre>
1557</div>
1558
Dan Gohmana7ab2bf2008-11-24 16:35:31 +0000[diff] [blame]1559<p>can be safely substituted by the single instruction:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1560
1561<div class="doc_code">
1562<pre>
1563%EAX = LOAD %mem_address
1564</pre>
1565</div>
1566
1567<p>Instructions can be folded with the
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1568<tt>TargetRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1569taken when folding instructions; a folded instruction can be quite
1570different from the original instruction. See
1571<tt>LiveIntervals::addIntervalsForSpills</tt> in
1572<tt>lib/CodeGen/LiveIntervalAnalysis.cpp</tt> for an example of its use.</p>
1573
1574</div>
1575
1576<!-- _______________________________________________________________________ -->
1577
1578<div class="doc_subsubsection">
1579 <a name="regAlloc_builtIn">Built in register allocators</a>
1580</div>
1581
1582<div class="doc_text">
1583
1584<p>The LLVM infrastructure provides the application developer with
1585three different register allocators:</p>
1586
1587<ul>
1588 <li><i>Simple</i> - This is a very simple implementation that does
1589 not keep values in registers across instructions. This register
1590 allocator immediately spills every value right after it is
1591 computed, and reloads all used operands from memory to temporary
1592 registers before each instruction.</li>
1593 <li><i>Local</i> - This register allocator is an improvement on the
1594 <i>Simple</i> implementation. It allocates registers on a basic
1595 block level, attempting to keep values in registers and reusing
1596 registers as appropriate.</li>
1597 <li><i>Linear Scan</i> - <i>The default allocator</i>. This is the
1598 well-know linear scan register allocator. Whereas the
1599 <i>Simple</i> and <i>Local</i> algorithms use a direct mapping
1600 implementation technique, the <i>Linear Scan</i> implementation
1601 uses a spiller in order to place load and stores.</li>
1602</ul>
1603
1604<p>The type of register allocator used in <tt>llc</tt> can be chosen with the
1605command line option <tt>-regalloc=...</tt>:</p>
1606
1607<div class="doc_code">
1608<pre>
1609$ llc -f -regalloc=simple file.bc -o sp.s;
1610$ llc -f -regalloc=local file.bc -o lc.s;
1611$ llc -f -regalloc=linearscan file.bc -o ln.s;
1612</pre>
1613</div>
1614
1615</div>
1616
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1617<!-- ======================================================================= -->
1618<div class="doc_subsection">
1619 <a name="proepicode">Prolog/Epilog Code Insertion</a>
1620</div>
1621<div class="doc_text"><p>To Be Written</p></div>
1622<!-- ======================================================================= -->
1623<div class="doc_subsection">
1624 <a name="latemco">Late Machine Code Optimizations</a>
1625</div>
1626<div class="doc_text"><p>To Be Written</p></div>
1627<!-- ======================================================================= -->
1628<div class="doc_subsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1629 <a name="codeemit">Code Emission</a>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1630</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1631<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1632<!-- _______________________________________________________________________ -->
1633<div class="doc_subsubsection">
1634 <a name="codeemit_asm">Generating Assembly Code</a>
1635</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1636<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1637<!-- _______________________________________________________________________ -->
1638<div class="doc_subsubsection">
1639 <a name="codeemit_bin">Generating Binary Machine Code</a>
1640</div>
1641
1642<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1643 <p>For the JIT or <tt>.o</tt> file writer</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1644</div>
1645
1646
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1647<!-- *********************************************************************** -->
1648<div class="doc_section">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1649 <a name="targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1650</div>
1651<!-- *********************************************************************** -->
1652
1653<div class="doc_text">
1654
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1655<p>This section of the document explains features or design decisions that
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1656are specific to the code generator for a particular target.</p>
1657
1658</div>
1659
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]1660<!-- ======================================================================= -->
1661<div class="doc_subsection">
1662 <a name="tailcallopt">Tail call optimization</a>
1663</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1664
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]1665<div class="doc_text">
1666 <p>Tail call optimization, callee reusing the stack of the caller, is currently supported on x86/x86-64 and PowerPC. It is performed if:
1667 <ul>
1668 <li>Caller and callee have the calling convention <tt>fastcc</tt>.</li>
1669 <li>The call is a tail call - in tail position (ret immediately follows call and ret uses value of call or is void).</li>
1670 <li>Option <tt>-tailcallopt</tt> is enabled.</li>
1671 <li>Platform specific constraints are met.</li>
1672 </ul>
1673 </p>
1674
1675 <p>x86/x86-64 constraints:
1676 <ul>
1677 <li>No variable argument lists are used.</li>
1678 <li>On x86-64 when generating GOT/PIC code only module-local calls (visibility = hidden or protected) are supported.</li>
1679 </ul>
1680 </p>
1681 <p>PowerPC constraints:
1682 <ul>
1683 <li>No variable argument lists are used.</li>
1684 <li>No byval parameters are used.</li>
1685 <li>On ppc32/64 GOT/PIC only module-local calls (visibility = hidden or protected) are supported.</li>
1686 </ul>
1687 </p>
1688 <p>Example:</p>
1689 <p>Call as <tt>llc -tailcallopt test.ll</tt>.
1690 <div class="doc_code">
1691 <pre>
1692declare fastcc i32 @tailcallee(i32 inreg %a1, i32 inreg %a2, i32 %a3, i32 %a4)
1693
1694define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
1695 %l1 = add i32 %in1, %in2
1696 %tmp = tail call fastcc i32 @tailcallee(i32 %in1 inreg, i32 %in2 inreg, i32 %in1, i32 %l1)
1697 ret i32 %tmp
1698}</pre>
1699 </div>
1700 </p>
1701 <p>Implications of <tt>-tailcallopt</tt>:</p>
1702 <p>To support tail call optimization in situations where the callee has more arguments than the caller a 'callee pops arguments' convention is used. This currently causes each <tt>fastcc</tt> call that is not tail call optimized (because one or more of above constraints are not met) to be followed by a readjustment of the stack. So performance might be worse in such cases.</p>
1703 <p>On x86 and x86-64 one register is reserved for indirect tail calls (e.g via a function pointer). So there is one less register for integer argument passing. For x86 this means 2 registers (if <tt>inreg</tt> parameter attribute is used) and for x86-64 this means 5 register are used.</p>
1704</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1705<!-- ======================================================================= -->
1706<div class="doc_subsection">
1707 <a name="x86">The X86 backend</a>
1708</div>
1709
1710<div class="doc_text">
1711
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1712<p>The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
Dan Gohmanfd800722007-12-13 20:43:47 +0000[diff] [blame]1713code generator is capable of targeting a variety of x86-32 and x86-64
1714processors, and includes support for ISA extensions such as MMX and SSE.
1715</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1716
1717</div>
1718
1719<!-- _______________________________________________________________________ -->
1720<div class="doc_subsubsection">
Nate Begeman34509842009-01-26 02:54:45 +0000[diff] [blame]1721 <a name="x86_tt">X86 Target Triples supported</a>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1722</div>
1723
1724<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1725
1726<p>The following are the known target triples that are supported by the X86
1727backend. This is not an exhaustive list, and it would be useful to add those
1728that people test.</p>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1729
1730<ul>
1731<li><b>i686-pc-linux-gnu</b> - Linux</li>
1732<li><b>i386-unknown-freebsd5.3</b> - FreeBSD 5.3</li>
1733<li><b>i686-pc-cygwin</b> - Cygwin on Win32</li>
1734<li><b>i686-pc-mingw32</b> - MingW on Win32</li>
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]1735<li><b>i386-pc-mingw32msvc</b> - MingW crosscompiler on Linux</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1736<li><b>i686-apple-darwin*</b> - Apple Darwin on X86</li>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1737</ul>
1738
1739</div>
1740
1741<!-- _______________________________________________________________________ -->
1742<div class="doc_subsubsection">
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]1743 <a name="x86_cc">X86 Calling Conventions supported</a>
1744</div>
1745
1746
1747<div class="doc_text">
1748
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1749<p>The following target-specific calling conventions are known to backend:</p>
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]1750
1751<ul>
1752<li><b>x86_StdCall</b> - stdcall calling convention seen on Microsoft Windows
1753platform (CC ID = 64).</li>
1754<li><b>x86_FastCall</b> - fastcall calling convention seen on Microsoft Windows
1755platform (CC ID = 65).</li>
1756</ul>
1757
1758</div>
1759
1760<!-- _______________________________________________________________________ -->
1761<div class="doc_subsubsection">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1762 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
1763</div>
1764
1765<div class="doc_text">
1766
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1767<p>The x86 has a very flexible way of accessing memory. It is capable of
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1768forming memory addresses of the following expression directly in integer
1769instructions (which use ModR/M addressing):</p>
1770
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1771<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1772<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1773Base + [1,2,4,8] * IndexReg + Disp32
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1774</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1775</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1776
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1777<p>In order to represent this, LLVM tracks no less than 4 operands for each
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1778memory operand of this form. This means that the "load" form of '<tt>mov</tt>'
1779has the following <tt>MachineOperand</tt>s in this order:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1780
1781<pre>
1782Index: 0 | 1 2 3 4
1783Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
1784OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
1785</pre>
1786
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1787<p>Stores, and all other instructions, treat the four memory operands in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1788same way and in the same order.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1789
1790</div>
1791
1792<!-- _______________________________________________________________________ -->
1793<div class="doc_subsubsection">
Nate Begeman34509842009-01-26 02:54:45 +0000[diff] [blame]1794 <a name="x86_memory">X86 address spaces supported</a>
1795</div>
1796
1797<div class="doc_text">
1798
1799<p>x86 has the ability to perform loads and stores to different address spaces
1800via the x86 segment registers. A segment override prefix byte on an instruction
1801causes the instruction's memory access to go to the specified segment. LLVM
1802address space 0 is the default address space, which includes the stack, and
1803any unqualified memory accesses in a program. Address spaces 1-255 are
1804currently reserved for user-defined code. The GS-segment is represented by
1805address space 256. Other x86 segments have yet to be allocated address space
1806numbers.
1807
1808<p>Some operating systems use the GS-segment to implement TLS, so care should be
1809taken when reading and writing to address space 256 on these platforms.
1810
1811</div>
1812
1813<!-- _______________________________________________________________________ -->
1814<div class="doc_subsubsection">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1815 <a name="x86_names">Instruction naming</a>
1816</div>
1817
1818<div class="doc_text">
1819
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1820<p>An instruction name consists of the base name, a default operand size, and a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1821a character per operand with an optional special size. For example:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1822
1823<p>
1824<tt>ADD8rr</tt> -&gt; add, 8-bit register, 8-bit register<br>
1825<tt>IMUL16rmi</tt> -&gt; imul, 16-bit register, 16-bit memory, 16-bit immediate<br>
1826<tt>IMUL16rmi8</tt> -&gt; imul, 16-bit register, 16-bit memory, 8-bit immediate<br>
1827<tt>MOVSX32rm16</tt> -&gt; movsx, 32-bit register, 16-bit memory
1828</p>
1829
1830</div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1831
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1832<!-- ======================================================================= -->
1833<div class="doc_subsection">
1834 <a name="ppc">The PowerPC backend</a>
1835</div>
1836
1837<div class="doc_text">
1838<p>The PowerPC code generator lives in the lib/Target/PowerPC directory. The
1839code generation is retargetable to several variations or <i>subtargets</i> of
1840the PowerPC ISA; including ppc32, ppc64 and altivec.
1841</p>
1842</div>
1843
1844<!-- _______________________________________________________________________ -->
1845<div class="doc_subsubsection">
1846 <a name="ppc_abi">LLVM PowerPC ABI</a>
1847</div>
1848
1849<div class="doc_text">
1850<p>LLVM follows the AIX PowerPC ABI, with two deviations. LLVM uses a PC
1851relative (PIC) or static addressing for accessing global values, so no TOC (r2)
1852is used. Second, r31 is used as a frame pointer to allow dynamic growth of a
1853stack frame. LLVM takes advantage of having no TOC to provide space to save
1854the frame pointer in the PowerPC linkage area of the caller frame. Other
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1855details of PowerPC ABI can be found at <a href=
1856"http://developer.apple.com/documentation/DeveloperTools/Conceptual/LowLevelABI/Articles/32bitPowerPC.html"
1857>PowerPC ABI.</a> Note: This link describes the 32 bit ABI. The
185864 bit ABI is similar except space for GPRs are 8 bytes wide (not 4) and r13 is
1859reserved for system use.</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1860</div>
1861
1862<!-- _______________________________________________________________________ -->
1863<div class="doc_subsubsection">
1864 <a name="ppc_frame">Frame Layout</a>
1865</div>
1866
1867<div class="doc_text">
1868<p>The size of a PowerPC frame is usually fixed for the duration of a
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1869function&rsquo;s invocation. Since the frame is fixed size, all references into
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1870the frame can be accessed via fixed offsets from the stack pointer. The
1871exception to this is when dynamic alloca or variable sized arrays are present,
1872then a base pointer (r31) is used as a proxy for the stack pointer and stack
1873pointer is free to grow or shrink. A base pointer is also used if llvm-gcc is
1874not passed the -fomit-frame-pointer flag. The stack pointer is always aligned to
187516 bytes, so that space allocated for altivec vectors will be properly
1876aligned.</p>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1877<p>An invocation frame is laid out as follows (low memory at top);</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1878</div>
1879
1880<div class="doc_text">
1881<table class="layout">
1882 <tr>
1883 <td>Linkage<br><br></td>
1884 </tr>
1885 <tr>
1886 <td>Parameter area<br><br></td>
1887 </tr>
1888 <tr>
1889 <td>Dynamic area<br><br></td>
1890 </tr>
1891 <tr>
1892 <td>Locals area<br><br></td>
1893 </tr>
1894 <tr>
1895 <td>Saved registers area<br><br></td>
1896 </tr>
1897 <tr style="border-style: none hidden none hidden;">
1898 <td><br></td>
1899 </tr>
1900 <tr>
1901 <td>Previous Frame<br><br></td>
1902 </tr>
1903</table>
1904</div>
1905
1906<div class="doc_text">
1907<p>The <i>linkage</i> area is used by a callee to save special registers prior
1908to allocating its own frame. Only three entries are relevant to LLVM. The
1909first entry is the previous stack pointer (sp), aka link. This allows probing
1910tools like gdb or exception handlers to quickly scan the frames in the stack. A
1911function epilog can also use the link to pop the frame from the stack. The
1912third entry in the linkage area is used to save the return address from the lr
1913register. Finally, as mentioned above, the last entry is used to save the
1914previous frame pointer (r31.) The entries in the linkage area are the size of a
1915GPR, thus the linkage area is 24 bytes long in 32 bit mode and 48 bytes in 64
1916bit mode.</p>
1917</div>
1918
1919<div class="doc_text">
1920<p>32 bit linkage area</p>
1921<table class="layout">
1922 <tr>
1923 <td>0</td>
1924 <td>Saved SP (r1)</td>
1925 </tr>
1926 <tr>
1927 <td>4</td>
1928 <td>Saved CR</td>
1929 </tr>
1930 <tr>
1931 <td>8</td>
1932 <td>Saved LR</td>
1933 </tr>
1934 <tr>
1935 <td>12</td>
1936 <td>Reserved</td>
1937 </tr>
1938 <tr>
1939 <td>16</td>
1940 <td>Reserved</td>
1941 </tr>
1942 <tr>
1943 <td>20</td>
1944 <td>Saved FP (r31)</td>
1945 </tr>
1946</table>
1947</div>
1948
1949<div class="doc_text">
1950<p>64 bit linkage area</p>
1951<table class="layout">
1952 <tr>
1953 <td>0</td>
1954 <td>Saved SP (r1)</td>
1955 </tr>
1956 <tr>
1957 <td>8</td>
1958 <td>Saved CR</td>
1959 </tr>
1960 <tr>
1961 <td>16</td>
1962 <td>Saved LR</td>
1963 </tr>
1964 <tr>
1965 <td>24</td>
1966 <td>Reserved</td>
1967 </tr>
1968 <tr>
1969 <td>32</td>
1970 <td>Reserved</td>
1971 </tr>
1972 <tr>
1973 <td>40</td>
1974 <td>Saved FP (r31)</td>
1975 </tr>
1976</table>
1977</div>
1978
1979<div class="doc_text">
1980<p>The <i>parameter area</i> is used to store arguments being passed to a callee
1981function. Following the PowerPC ABI, the first few arguments are actually
1982passed in registers, with the space in the parameter area unused. However, if
1983there are not enough registers or the callee is a thunk or vararg function,
1984these register arguments can be spilled into the parameter area. Thus, the
1985parameter area must be large enough to store all the parameters for the largest
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1986call sequence made by the caller. The size must also be minimally large enough
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1987to spill registers r3-r10. This allows callees blind to the call signature,
1988such as thunks and vararg functions, enough space to cache the argument
1989registers. Therefore, the parameter area is minimally 32 bytes (64 bytes in 64
1990bit mode.) Also note that since the parameter area is a fixed offset from the
1991top of the frame, that a callee can access its spilt arguments using fixed
1992offsets from the stack pointer (or base pointer.)</p>
1993</div>
1994
1995<div class="doc_text">
1996<p>Combining the information about the linkage, parameter areas and alignment. A
1997stack frame is minimally 64 bytes in 32 bit mode and 128 bytes in 64 bit
1998mode.</p>
1999</div>
2000
2001<div class="doc_text">
2002<p>The <i>dynamic area</i> starts out as size zero. If a function uses dynamic
2003alloca then space is added to the stack, the linkage and parameter areas are
2004shifted to top of stack, and the new space is available immediately below the
2005linkage and parameter areas. The cost of shifting the linkage and parameter
2006areas is minor since only the link value needs to be copied. The link value can
2007be easily fetched by adding the original frame size to the base pointer. Note
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]2008that allocations in the dynamic space need to observe 16 byte alignment.</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2009</div>
2010
2011<div class="doc_text">
2012<p>The <i>locals area</i> is where the llvm compiler reserves space for local
2013variables.</p>
2014</div>
2015
2016<div class="doc_text">
2017<p>The <i>saved registers area</i> is where the llvm compiler spills callee saved
2018registers on entry to the callee.</p>
2019</div>
2020
2021<!-- _______________________________________________________________________ -->
2022<div class="doc_subsubsection">
2023 <a name="ppc_prolog">Prolog/Epilog</a>
2024</div>
2025
2026<div class="doc_text">
2027<p>The llvm prolog and epilog are the same as described in the PowerPC ABI, with
2028the following exceptions. Callee saved registers are spilled after the frame is
2029created. This allows the llvm epilog/prolog support to be common with other
2030targets. The base pointer callee saved register r31 is saved in the TOC slot of
2031linkage area. This simplifies allocation of space for the base pointer and
2032makes it convenient to locate programatically and during debugging.</p>
2033</div>
2034
2035<!-- _______________________________________________________________________ -->
2036<div class="doc_subsubsection">
2037 <a name="ppc_dynamic">Dynamic Allocation</a>
2038</div>
2039
2040<div class="doc_text">
2041<p></p>
2042</div>
2043
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]2044<div class="doc_text">
2045<p><i>TODO - More to come.</i></p>
2046</div>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2047
2048
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]2049<!-- *********************************************************************** -->
2050<hr>
2051<address>
2052 <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
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Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]2056
2057 <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
Reid Spencer05fe4b02006-03-14 05:39:39 +0000[diff] [blame]2058 <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
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