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Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]6 <title>The LLVM Target-Independent Code Generator</title>
7 <link rel="stylesheet" href="llvm.css" type="text/css">
8</head>
9<body>
10
11<div class="doc_title">
12 The LLVM Target-Independent Code Generator
13</div>
14
15<ol>
16 <li><a href="#introduction">Introduction</a>
17 <ul>
18 <li><a href="#required">Required components in the code generator</a></li>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]19 <li><a href="#high-level-design">The high-level design of the code
20 generator</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]21 <li><a href="#tablegen">Using TableGen for target description</a></li>
22 </ul>
23 </li>
24 <li><a href="#targetdesc">Target description classes</a>
25 <ul>
26 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
27 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]28 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]29 <li><a href="#targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]30 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
31 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]32 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]33 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
34 </ul>
35 </li>
36 <li><a href="#codegendesc">Machine code description classes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]37 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]38 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]39 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
40 class</a></li>
41 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]42 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]43 </li>
44 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]45 <ul>
46 <li><a href="#instselect">Instruction Selection</a>
47 <ul>
48 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
49 <li><a href="#selectiondag_process">SelectionDAG Code Generation
50 Process</a></li>
51 <li><a href="#selectiondag_build">Initial SelectionDAG
52 Construction</a></li>
53 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
54 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]55 Phase: the DAG Combiner</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]56 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]57 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]58 Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]59 <li><a href="#selectiondag_future">Future directions for the
60 SelectionDAG</a></li>
61 </ul></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]62 <li><a href="#liveintervals">Live Intervals</a>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]63 <ul>
64 <li><a href="#livevariable_analysis">Live Variable Analysis</a></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]65 <li><a href="#liveintervals_analysis">Live Intervals Analysis</a></li>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]66 </ul></li>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]67 <li><a href="#regalloc">Register Allocation</a>
68 <ul>
69 <li><a href="#regAlloc_represent">How registers are represented in
70 LLVM</a></li>
71 <li><a href="#regAlloc_howTo">Mapping virtual registers to physical
72 registers</a></li>
73 <li><a href="#regAlloc_twoAddr">Handling two address instructions</a></li>
74 <li><a href="#regAlloc_ssaDecon">The SSA deconstruction phase</a></li>
75 <li><a href="#regAlloc_fold">Instruction folding</a></li>
76 <li><a href="#regAlloc_builtIn">Built in register allocators</a></li>
77 </ul></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]78 <li><a href="#codeemit">Code Emission</a>
79 <ul>
80 <li><a href="#codeemit_asm">Generating Assembly Code</a></li>
81 <li><a href="#codeemit_bin">Generating Binary Machine Code</a></li>
82 </ul></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]83 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]84 </li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]85 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]86 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]87 <li><a href="#x86">The X86 backend</a></li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]88 <li><a href="#ppc">The PowerPC backend</a>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]89 <ul>
90 <li><a href="#ppc_abi">LLVM PowerPC ABI</a></li>
91 <li><a href="#ppc_frame">Frame Layout</a></li>
92 <li><a href="#ppc_prolog">Prolog/Epilog</a></li>
93 <li><a href="#ppc_dynamic">Dynamic Allocation</a></li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]94 </ul></li>
95 </ul></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]96
97</ol>
98
99<div class="doc_author">
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]100 <p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a>,
Jim Laskeyd201f4e2007-03-14 19:30:33 +0000[diff] [blame]101 <a href="mailto:isanbard@gmail.com">Bill Wendling</a>,
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]102 <a href="mailto:pronesto@gmail.com">Fernando Magno Quintao
Jim Laskeyd201f4e2007-03-14 19:30:33 +0000[diff] [blame]103 Pereira</a> and
104 <a href="mailto:jlaskey@mac.com">Jim Laskey</a></p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]105</div>
106
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]107<div class="doc_warning">
108 <p>Warning: This is a work in progress.</p>
109</div>
110
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]111<!-- *********************************************************************** -->
112<div class="doc_section">
113 <a name="introduction">Introduction</a>
114</div>
115<!-- *********************************************************************** -->
116
117<div class="doc_text">
118
119<p>The LLVM target-independent code generator is a framework that provides a
120suite of reusable components for translating the LLVM internal representation to
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]121the machine code for a specified target&mdash;either in assembly form (suitable
122for a static compiler) or in binary machine code format (usable for a JIT
123compiler). The LLVM target-independent code generator consists of five main
124components:</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]125
126<ol>
127<li><a href="#targetdesc">Abstract target description</a> interfaces which
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]128capture important properties about various aspects of the machine, independently
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]129of how they will be used. These interfaces are defined in
130<tt>include/llvm/Target/</tt>.</li>
131
132<li>Classes used to represent the <a href="#codegendesc">machine code</a> being
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]133generated for a target. These classes are intended to be abstract enough to
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]134represent the machine code for <i>any</i> target machine. These classes are
135defined in <tt>include/llvm/CodeGen/</tt>.</li>
136
137<li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
138various phases of native code generation (register allocation, scheduling, stack
139frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
140
141<li><a href="#targetimpls">Implementations of the abstract target description
142interfaces</a> for particular targets. These machine descriptions make use of
143the components provided by LLVM, and can optionally provide custom
144target-specific passes, to build complete code generators for a specific target.
145Target descriptions live in <tt>lib/Target/</tt>.</li>
146
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]147<li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
148completely target independent (it uses the <tt>TargetJITInfo</tt> structure to
149interface for target-specific issues. The code for the target-independent
150JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
151
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]152</ol>
153
154<p>
155Depending on which part of the code generator you are interested in working on,
156different pieces of this will be useful to you. In any case, you should be
157familiar with the <a href="#targetdesc">target description</a> and <a
158href="#codegendesc">machine code representation</a> classes. If you want to add
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]159a backend for a new target, you will need to <a href="#targetimpls">implement the
160target description</a> classes for your new target and understand the <a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]161href="LangRef.html">LLVM code representation</a>. If you are interested in
162implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
163should only depend on the target-description and machine code representation
164classes, ensuring that it is portable.
165</p>
166
167</div>
168
169<!-- ======================================================================= -->
170<div class="doc_subsection">
171 <a name="required">Required components in the code generator</a>
172</div>
173
174<div class="doc_text">
175
176<p>The two pieces of the LLVM code generator are the high-level interface to the
177code generator and the set of reusable components that can be used to build
178target-specific backends. The two most important interfaces (<a
179href="#targetmachine"><tt>TargetMachine</tt></a> and <a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]180href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]181required to be defined for a backend to fit into the LLVM system, but the others
182must be defined if the reusable code generator components are going to be
183used.</p>
184
185<p>This design has two important implications. The first is that LLVM can
186support completely non-traditional code generation targets. For example, the C
187backend does not require register allocation, instruction selection, or any of
188the other standard components provided by the system. As such, it only
189implements these two interfaces, and does its own thing. Another example of a
190code generator like this is a (purely hypothetical) backend that converts LLVM
191to the GCC RTL form and uses GCC to emit machine code for a target.</p>
192
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]193<p>This design also implies that it is possible to design and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]194implement radically different code generators in the LLVM system that do not
195make use of any of the built-in components. Doing so is not recommended at all,
196but could be required for radically different targets that do not fit into the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]197LLVM machine description model: FPGAs for example.</p>
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]198
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]199</div>
200
201<!-- ======================================================================= -->
202<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]203 <a name="high-level-design">The high-level design of the code generator</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]204</div>
205
206<div class="doc_text">
207
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]208<p>The LLVM target-independent code generator is designed to support efficient and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]209quality code generation for standard register-based microprocessors. Code
210generation in this model is divided into the following stages:</p>
211
212<ol>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]213<li><b><a href="#instselect">Instruction Selection</a></b> - This phase
214determines an efficient way to express the input LLVM code in the target
215instruction set.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]216This stage produces the initial code for the program in the target instruction
217set, then makes use of virtual registers in SSA form and physical registers that
218represent any required register assignments due to target constraints or calling
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]219conventions. This step turns the LLVM code into a DAG of target
220instructions.</li>
221
222<li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> - This
223phase takes the DAG of target instructions produced by the instruction selection
224phase, determines an ordering of the instructions, then emits the instructions
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]225as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering. Note
226that we describe this in the <a href="#instselect">instruction selection
227section</a> because it operates on a <a
228href="#selectiondag_intro">SelectionDAG</a>.
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]229</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]230
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]231<li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
232optional stage consists of a series of machine-code optimizations that
233operate on the SSA-form produced by the instruction selector. Optimizations
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]234like modulo-scheduling or peephole optimization work here.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]235</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]236
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]237<li><b><a href="#regalloc">Register Allocation</a></b> - The
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]238target code is transformed from an infinite virtual register file in SSA form
239to the concrete register file used by the target. This phase introduces spill
240code and eliminates all virtual register references from the program.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]241
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]242<li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]243machine code has been generated for the function and the amount of stack space
244required is known (used for LLVM alloca's and spill slots), the prolog and
245epilog code for the function can be inserted and "abstract stack location
246references" can be eliminated. This stage is responsible for implementing
247optimizations like frame-pointer elimination and stack packing.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]248
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]249<li><b><a href="#latemco">Late Machine Code Optimizations</a></b> - Optimizations
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]250that operate on "final" machine code can go here, such as spill code scheduling
251and peephole optimizations.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]252
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]253<li><b><a href="#codeemit">Code Emission</a></b> - The final stage actually
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]254puts out the code for the current function, either in the target assembler
255format or in machine code.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]256
257</ol>
258
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]259<p>The code generator is based on the assumption that the instruction selector
260will use an optimal pattern matching selector to create high-quality sequences of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]261native instructions. Alternative code generator designs based on pattern
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]262expansion and aggressive iterative peephole optimization are much slower. This
263design permits efficient compilation (important for JIT environments) and
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]264aggressive optimization (used when generating code offline) by allowing
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]265components of varying levels of sophistication to be used for any step of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]266compilation.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]267
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]268<p>In addition to these stages, target implementations can insert arbitrary
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]269target-specific passes into the flow. For example, the X86 target uses a
270special pass to handle the 80x87 floating point stack architecture. Other
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]271targets with unusual requirements can be supported with custom passes as
272needed.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]273
274</div>
275
276
277<!-- ======================================================================= -->
278<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]279 <a name="tablegen">Using TableGen for target description</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]280</div>
281
282<div class="doc_text">
283
Chris Lattner5489e932004-06-01 18:35:00 +0000[diff] [blame]284<p>The target description classes require a detailed description of the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]285architecture. These target descriptions often have a large amount of common
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]286information (e.g., an <tt>add</tt> instruction is almost identical to a
287<tt>sub</tt> instruction).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]288In order to allow the maximum amount of commonality to be factored out, the LLVM
289code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]290describe big chunks of the target machine, which allows the use of
291domain-specific and target-specific abstractions to reduce the amount of
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]292repetition.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]293
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]294<p>As LLVM continues to be developed and refined, we plan to move more and more
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]295of the target description to the <tt>.td</tt> form. Doing so gives us a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]296number of advantages. The most important is that it makes it easier to port
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]297LLVM because it reduces the amount of C++ code that has to be written, and the
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]298surface area of the code generator that needs to be understood before someone
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]299can get something working. Second, it makes it easier to change things. In
300particular, if tables and other things are all emitted by <tt>tblgen</tt>, we
301only need a change in one place (<tt>tblgen</tt>) to update all of the targets
302to a new interface.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]303
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]304</div>
305
306<!-- *********************************************************************** -->
307<div class="doc_section">
308 <a name="targetdesc">Target description classes</a>
309</div>
310<!-- *********************************************************************** -->
311
312<div class="doc_text">
313
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]314<p>The LLVM target description classes (located in the
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]315<tt>include/llvm/Target</tt> directory) provide an abstract description of the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]316target machine independent of any particular client. These classes are
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]317designed to capture the <i>abstract</i> properties of the target (such as the
318instructions and registers it has), and do not incorporate any particular pieces
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]319of code generation algorithms.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]320
321<p>All of the target description classes (except the <tt><a
322href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
323the concrete target implementation, and have virtual methods implemented. To
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]324get to these implementations, the <tt><a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]325href="#targetmachine">TargetMachine</a></tt> class provides accessors that
326should be implemented by the target.</p>
327
328</div>
329
330<!-- ======================================================================= -->
331<div class="doc_subsection">
332 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
333</div>
334
335<div class="doc_text">
336
337<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
338access the target-specific implementations of the various target description
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]339classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
340<tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
341designed to be specialized by
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]342a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
343implements the various virtual methods. The only required target description
344class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
345code generator components are to be used, the other interfaces should be
346implemented as well.</p>
347
348</div>
349
350
351<!-- ======================================================================= -->
352<div class="doc_subsection">
353 <a name="targetdata">The <tt>TargetData</tt> class</a>
354</div>
355
356<div class="doc_text">
357
358<p>The <tt>TargetData</tt> class is the only required target description class,
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]359and it is the only class that is not extensible (you cannot derived a new
360class from it). <tt>TargetData</tt> specifies information about how the target
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]361lays out memory for structures, the alignment requirements for various data
362types, the size of pointers in the target, and whether the target is
363little-endian or big-endian.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]364
365</div>
366
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]367<!-- ======================================================================= -->
368<div class="doc_subsection">
369 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
370</div>
371
372<div class="doc_text">
373
374<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
375selectors primarily to describe how LLVM code should be lowered to SelectionDAG
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]376operations. Among other things, this class indicates:</p>
377
378<ul>
379 <li>an initial register class to use for various <tt>ValueType</tt>s</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]380 <li>which operations are natively supported by the target machine</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]381 <li>the return type of <tt>setcc</tt> operations</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]382 <li>the type to use for shift amounts</li>
383 <li>various high-level characteristics, like whether it is profitable to turn
384 division by a constant into a multiplication sequence</li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]385</ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]386
387</div>
388
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]389<!-- ======================================================================= -->
390<div class="doc_subsection">
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]391 <a name="targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]392</div>
393
394<div class="doc_text">
395
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]396<p>The <tt>TargetRegisterInfo</tt> class is used to describe the register
397file of the target and any interactions between the registers.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]398
399<p>Registers in the code generator are represented in the code generator by
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]400unsigned integers. Physical registers (those that actually exist in the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]401description) are unique small numbers, and virtual registers are generally
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]402large. Note that register #0 is reserved as a flag value.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]403
404<p>Each register in the processor description has an associated
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]405<tt>TargetRegisterDesc</tt> entry, which provides a textual name for the
406register (used for assembly output and debugging dumps) and a set of aliases
407(used to indicate whether one register overlaps with another).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]408</p>
409
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]410<p>In addition to the per-register description, the <tt>TargetRegisterInfo</tt>
411class exposes a set of processor specific register classes (instances of the
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]412<tt>TargetRegisterClass</tt> class). Each register class contains sets of
413registers that have the same properties (for example, they are all 32-bit
414integer registers). Each SSA virtual register created by the instruction
415selector has an associated register class. When the register allocator runs, it
416replaces virtual registers with a physical register in the set.</p>
417
418<p>
419The target-specific implementations of these classes is auto-generated from a <a
420href="TableGenFundamentals.html">TableGen</a> description of the register file.
421</p>
422
423</div>
424
425<!-- ======================================================================= -->
426<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]427 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]428</div>
429
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]430<div class="doc_text">
431 <p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
432 instructions supported by the target. It is essentially an array of
433 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
434 instruction the target supports. Descriptors define things like the mnemonic
Chris Lattnera3079782005-07-19 03:37:48 +0000[diff] [blame]435 for the opcode, the number of operands, the list of implicit register uses
436 and defs, whether the instruction has certain target-independent properties
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]437 (accesses memory, is commutable, etc), and holds any target-specific
438 flags.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]439</div>
440
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]441<!-- ======================================================================= -->
442<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]443 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]444</div>
445
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]446<div class="doc_text">
447 <p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
448 stack frame layout of the target. It holds the direction of stack growth,
449 the known stack alignment on entry to each function, and the offset to the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]450 local area. The offset to the local area is the offset from the stack
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]451 pointer on function entry to the first location where function data (local
452 variables, spill locations) can be stored.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]453</div>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]454
455<!-- ======================================================================= -->
456<div class="doc_subsection">
457 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
458</div>
459
460<div class="doc_text">
Jim Laskey82d61a12005-10-17 12:19:10 +0000[diff] [blame]461 <p>The <tt>TargetSubtarget</tt> class is used to provide information about the
462 specific chip set being targeted. A sub-target informs code generation of
463 which instructions are supported, instruction latencies and instruction
464 execution itinerary; i.e., which processing units are used, in what order, and
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]465 for how long.</p>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]466</div>
467
468
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]469<!-- ======================================================================= -->
470<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]471 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]472</div>
473
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]474<div class="doc_text">
475 <p>The <tt>TargetJITInfo</tt> class exposes an abstract interface used by the
476 Just-In-Time code generator to perform target-specific activities, such as
477 emitting stubs. If a <tt>TargetMachine</tt> supports JIT code generation, it
478 should provide one of these objects through the <tt>getJITInfo</tt>
479 method.</p>
480</div>
481
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]482<!-- *********************************************************************** -->
483<div class="doc_section">
484 <a name="codegendesc">Machine code description classes</a>
485</div>
486<!-- *********************************************************************** -->
487
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]488<div class="doc_text">
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]489
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]490<p>At the high-level, LLVM code is translated to a machine specific
491representation formed out of
492<a href="#machinefunction"><tt>MachineFunction</tt></a>,
493<a href="#machinebasicblock"><tt>MachineBasicBlock</tt></a>, and <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]494href="#machineinstr"><tt>MachineInstr</tt></a> instances
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]495(defined in <tt>include/llvm/CodeGen</tt>). This representation is completely
496target agnostic, representing instructions in their most abstract form: an
497opcode and a series of operands. This representation is designed to support
498both an SSA representation for machine code, as well as a register allocated,
499non-SSA form.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]500
501</div>
502
503<!-- ======================================================================= -->
504<div class="doc_subsection">
505 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
506</div>
507
508<div class="doc_text">
509
510<p>Target machine instructions are represented as instances of the
511<tt>MachineInstr</tt> class. This class is an extremely abstract way of
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]512representing machine instructions. In particular, it only keeps track of
513an opcode number and a set of operands.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]514
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]515<p>The opcode number is a simple unsigned integer that only has meaning to a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]516specific backend. All of the instructions for a target should be defined in
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]517the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]518are auto-generated from this description. The <tt>MachineInstr</tt> class does
519not have any information about how to interpret the instruction (i.e., what the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]520semantics of the instruction are); for that you must refer to the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]521<tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
522
523<p>The operands of a machine instruction can be of several different types:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]524a register reference, a constant integer, a basic block reference, etc. In
525addition, a machine operand should be marked as a def or a use of the value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]526(though only registers are allowed to be defs).</p>
527
528<p>By convention, the LLVM code generator orders instruction operands so that
529all register definitions come before the register uses, even on architectures
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]530that are normally printed in other orders. For example, the SPARC add
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]531instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
532and stores the result into the "%i3" register. In the LLVM code generator,
533the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
534first.</p>
535
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]536<p>Keeping destination (definition) operands at the beginning of the operand
537list has several advantages. In particular, the debugging printer will print
538the instruction like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]539
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]540<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]541<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]542%r3 = add %i1, %i2
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]543</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]544</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]545
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]546<p>Also if the first operand is a def, it is easier to <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]547href="#buildmi">create instructions</a> whose only def is the first
548operand.</p>
549
550</div>
551
552<!-- _______________________________________________________________________ -->
553<div class="doc_subsubsection">
554 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
555</div>
556
557<div class="doc_text">
558
559<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
560located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
561<tt>BuildMI</tt> functions make it easy to build arbitrary machine
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]562instructions. Usage of the <tt>BuildMI</tt> functions look like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]563
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]564<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]565<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]566// Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
567// instruction. The '1' specifies how many operands will be added.
568MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]569
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]570// Create the same instr, but insert it at the end of a basic block.
571MachineBasicBlock &amp;MBB = ...
572BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]573
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]574// Create the same instr, but insert it before a specified iterator point.
575MachineBasicBlock::iterator MBBI = ...
576BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]577
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]578// Create a 'cmp Reg, 0' instruction, no destination reg.
579MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
580// Create an 'sahf' instruction which takes no operands and stores nothing.
581MI = BuildMI(X86::SAHF, 0);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]582
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]583// Create a self looping branch instruction.
584BuildMI(MBB, X86::JNE, 1).addMBB(&amp;MBB);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]585</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]586</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]587
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]588<p>The key thing to remember with the <tt>BuildMI</tt> functions is that you
589have to specify the number of operands that the machine instruction will take.
590This allows for efficient memory allocation. You also need to specify if
591operands default to be uses of values, not definitions. If you need to add a
592definition operand (other than the optional destination register), you must
593explicitly mark it as such:</p>
594
595<div class="doc_code">
596<pre>
597MI.addReg(Reg, MachineOperand::Def);
598</pre>
599</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]600
601</div>
602
603<!-- _______________________________________________________________________ -->
604<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]605 <a name="fixedregs">Fixed (preassigned) registers</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]606</div>
607
608<div class="doc_text">
609
610<p>One important issue that the code generator needs to be aware of is the
611presence of fixed registers. In particular, there are often places in the
612instruction stream where the register allocator <em>must</em> arrange for a
613particular value to be in a particular register. This can occur due to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]614limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]615with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
616conventions. In any case, the instruction selector should emit code that
617copies a virtual register into or out of a physical register when needed.</p>
618
619<p>For example, consider this simple LLVM example:</p>
620
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]621<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]622<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]623int %test(int %X, int %Y) {
624 %Z = div int %X, %Y
625 ret int %Z
626}
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]627</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]628</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]629
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]630<p>The X86 instruction selector produces this machine code for the <tt>div</tt>
631and <tt>ret</tt> (use
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]632"<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to get this):</p>
633
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]634<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]635<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]636;; Start of div
637%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
638%reg1027 = sar %reg1024, 31
639%EDX = mov %reg1027 ;; Sign extend X into EDX
640idiv %reg1025 ;; Divide by Y (in reg1025)
641%reg1026 = mov %EAX ;; Read the result (Z) out of EAX
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]642
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]643;; Start of ret
644%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
645ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]646</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]647</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]648
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]649<p>By the end of code generation, the register allocator has coalesced
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]650the registers and deleted the resultant identity moves producing the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]651following code:</p>
652
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]653<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]654<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]655;; X is in EAX, Y is in ECX
656mov %EAX, %EDX
657sar %EDX, 31
658idiv %ECX
659ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]660</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]661</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]662
663<p>This approach is extremely general (if it can handle the X86 architecture,
664it can handle anything!) and allows all of the target specific
665knowledge about the instruction stream to be isolated in the instruction
666selector. Note that physical registers should have a short lifetime for good
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]667code generation, and all physical registers are assumed dead on entry to and
668exit from basic blocks (before register allocation). Thus, if you need a value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]669to be live across basic block boundaries, it <em>must</em> live in a virtual
670register.</p>
671
672</div>
673
674<!-- _______________________________________________________________________ -->
675<div class="doc_subsubsection">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]676 <a name="ssa">Machine code in SSA form</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]677</div>
678
679<div class="doc_text">
680
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]681<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]682are maintained in SSA-form until register allocation happens. For the most
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]683part, this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]684become machine code PHI nodes, and virtual registers are only allowed to have a
685single definition.</p>
686
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]687<p>After register allocation, machine code is no longer in SSA-form because there
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]688are no virtual registers left in the code.</p>
689
690</div>
691
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]692<!-- ======================================================================= -->
693<div class="doc_subsection">
694 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
695</div>
696
697<div class="doc_text">
698
699<p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]700(<tt><a href="#machineinstr">MachineInstr</a></tt> instances). It roughly
701corresponds to the LLVM code input to the instruction selector, but there can be
702a one-to-many mapping (i.e. one LLVM basic block can map to multiple machine
703basic blocks). The <tt>MachineBasicBlock</tt> class has a
704"<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
705comes from.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]706
707</div>
708
709<!-- ======================================================================= -->
710<div class="doc_subsection">
711 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
712</div>
713
714<div class="doc_text">
715
716<p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]717(<tt><a href="#machinebasicblock">MachineBasicBlock</a></tt> instances). It
718corresponds one-to-one with the LLVM function input to the instruction selector.
719In addition to a list of basic blocks, the <tt>MachineFunction</tt> contains a
720a <tt>MachineConstantPool</tt>, a <tt>MachineFrameInfo</tt>, a
Chris Lattner534bcfb2007-12-31 04:16:08 +0000[diff] [blame]721<tt>MachineFunctionInfo</tt>, and a <tt>MachineRegisterInfo</tt>. See
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]722<tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]723
724</div>
725
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]726<!-- *********************************************************************** -->
727<div class="doc_section">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]728 <a name="codegenalgs">Target-independent code generation algorithms</a>
729</div>
730<!-- *********************************************************************** -->
731
732<div class="doc_text">
733
734<p>This section documents the phases described in the <a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]735href="#high-level-design">high-level design of the code generator</a>. It
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]736explains how they work and some of the rationale behind their design.</p>
737
738</div>
739
740<!-- ======================================================================= -->
741<div class="doc_subsection">
742 <a name="instselect">Instruction Selection</a>
743</div>
744
745<div class="doc_text">
746<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]747Instruction Selection is the process of translating LLVM code presented to the
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]748code generator into target-specific machine instructions. There are several
Evan Cheng77949352007-10-08 17:54:24 +0000[diff] [blame]749well-known ways to do this in the literature. LLVM uses a SelectionDAG based
750instruction selector.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]751</p>
752
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]753<p>Portions of the DAG instruction selector are generated from the target
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]754description (<tt>*.td</tt>) files. Our goal is for the entire instruction
Dan Gohmanfd800722007-12-13 20:43:47 +0000[diff] [blame]755selector to be generated from these <tt>.td</tt> files, though currently
756there are still things that require custom C++ code.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]757</div>
758
759<!-- _______________________________________________________________________ -->
760<div class="doc_subsubsection">
761 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
762</div>
763
764<div class="doc_text">
765
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]766<p>The SelectionDAG provides an abstraction for code representation in a way
767that is amenable to instruction selection using automatic techniques
768(e.g. dynamic-programming based optimal pattern matching selectors). It is also
769well-suited to other phases of code generation; in particular,
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]770instruction scheduling (SelectionDAG's are very close to scheduling DAGs
771post-selection). Additionally, the SelectionDAG provides a host representation
772where a large variety of very-low-level (but target-independent)
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]773<a href="#selectiondag_optimize">optimizations</a> may be
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]774performed; ones which require extensive information about the instructions
775efficiently supported by the target.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]776
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]777<p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]778<tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]779operation code (Opcode) that indicates what operation the node performs and
780the operands to the operation.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]781The various operation node types are described at the top of the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]782<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]783
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]784<p>Although most operations define a single value, each node in the graph may
785define multiple values. For example, a combined div/rem operation will define
786both the dividend and the remainder. Many other situations require multiple
787values as well. Each node also has some number of operands, which are edges
788to the node defining the used value. Because nodes may define multiple values,
789edges are represented by instances of the <tt>SDOperand</tt> class, which is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]790a <tt>&lt;SDNode, unsigned&gt;</tt> pair, indicating the node and result
791value being used, respectively. Each value produced by an <tt>SDNode</tt> has
792an associated <tt>MVT::ValueType</tt> indicating what type the value is.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]793
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]794<p>SelectionDAGs contain two different kinds of values: those that represent
795data flow and those that represent control flow dependencies. Data values are
796simple edges with an integer or floating point value type. Control edges are
797represented as "chain" edges which are of type <tt>MVT::Other</tt>. These edges
798provide an ordering between nodes that have side effects (such as
799loads, stores, calls, returns, etc). All nodes that have side effects should
800take a token chain as input and produce a new one as output. By convention,
801token chain inputs are always operand #0, and chain results are always the last
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]802value produced by an operation.</p>
803
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]804<p>A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
805always a marker node with an Opcode of <tt>ISD::EntryToken</tt>. The Root node
806is the final side-effecting node in the token chain. For example, in a single
807basic block function it would be the return node.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]808
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]809<p>One important concept for SelectionDAGs is the notion of a "legal" vs.
810"illegal" DAG. A legal DAG for a target is one that only uses supported
811operations and supported types. On a 32-bit PowerPC, for example, a DAG with
812a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that uses a
813SREM or UREM operation. The
814<a href="#selectiondag_legalize">legalize</a> phase is responsible for turning
815an illegal DAG into a legal DAG.</p>
816
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]817</div>
818
819<!-- _______________________________________________________________________ -->
820<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]821 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]822</div>
823
824<div class="doc_text">
825
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]826<p>SelectionDAG-based instruction selection consists of the following steps:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]827
828<ol>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]829<li><a href="#selectiondag_build">Build initial DAG</a> - This stage
830 performs a simple translation from the input LLVM code to an illegal
831 SelectionDAG.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]832<li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> - This stage
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]833 performs simple optimizations on the SelectionDAG to simplify it, and
834 recognize meta instructions (like rotates and <tt>div</tt>/<tt>rem</tt>
835 pairs) for targets that support these meta operations. This makes the
836 resultant code more efficient and the <a href="#selectiondag_select">select
837 instructions from DAG</a> phase (below) simpler.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]838<li><a href="#selectiondag_legalize">Legalize SelectionDAG</a> - This stage
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]839 converts the illegal SelectionDAG to a legal SelectionDAG by eliminating
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]840 unsupported operations and data types.</li>
841<li><a href="#selectiondag_optimize">Optimize SelectionDAG (#2)</a> - This
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]842 second run of the SelectionDAG optimizes the newly legalized DAG to
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]843 eliminate inefficiencies introduced by legalization.</li>
844<li><a href="#selectiondag_select">Select instructions from DAG</a> - Finally,
845 the target instruction selector matches the DAG operations to target
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]846 instructions. This process translates the target-independent input DAG into
847 another DAG of target instructions.</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]848<li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]849 - The last phase assigns a linear order to the instructions in the
850 target-instruction DAG and emits them into the MachineFunction being
851 compiled. This step uses traditional prepass scheduling techniques.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]852</ol>
853
854<p>After all of these steps are complete, the SelectionDAG is destroyed and the
855rest of the code generation passes are run.</p>
856
Chris Lattnerdf921f02005-10-17 01:40:33 +0000[diff] [blame]857<p>One great way to visualize what is going on here is to take advantage of a
858few LLC command line options. In particular, the <tt>-view-isel-dags</tt>
859option pops up a window with the SelectionDAG input to the Select phase for all
860of the code compiled (if you only get errors printed to the console while using
861this, you probably <a href="ProgrammersManual.html#ViewGraph">need to configure
862your system</a> to add support for it). The <tt>-view-sched-dags</tt> option
863views the SelectionDAG output from the Select phase and input to the Scheduler
Dan Gohmane9bb13d2007-10-15 21:07:59 +0000[diff] [blame]864phase. The <tt>-view-sunit-dags</tt> option views the ScheduleDAG, which is
865based on the final SelectionDAG, with nodes that must be scheduled as a unit
866bundled together into a single node, and with immediate operands and other
867nodes that aren't relevent for scheduling omitted.
868</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]869
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]870</div>
871
872<!-- _______________________________________________________________________ -->
873<div class="doc_subsubsection">
874 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
875</div>
876
877<div class="doc_text">
878
Bill Wendling16448772006-08-28 03:04:05 +0000[diff] [blame]879<p>The initial SelectionDAG is na&iuml;vely peephole expanded from the LLVM
880input by the <tt>SelectionDAGLowering</tt> class in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]881<tt>lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp</tt> file. The intent of this
882pass is to expose as much low-level, target-specific details to the SelectionDAG
883as possible. This pass is mostly hard-coded (e.g. an LLVM <tt>add</tt> turns
884into an <tt>SDNode add</tt> while a <tt>geteelementptr</tt> is expanded into the
885obvious arithmetic). This pass requires target-specific hooks to lower calls,
886returns, varargs, etc. For these features, the
887<tt><a href="#targetlowering">TargetLowering</a></tt> interface is used.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]888
889</div>
890
891<!-- _______________________________________________________________________ -->
892<div class="doc_subsubsection">
893 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
894</div>
895
896<div class="doc_text">
897
898<p>The Legalize phase is in charge of converting a DAG to only use the types and
899operations that are natively supported by the target. This involves two major
900tasks:</p>
901
902<ol>
903<li><p>Convert values of unsupported types to values of supported types.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]904 <p>There are two main ways of doing this: converting small types to
905 larger types ("promoting"), and breaking up large integer types
906 into smaller ones ("expanding"). For example, a target might require
907 that all f32 values are promoted to f64 and that all i1/i8/i16 values
908 are promoted to i32. The same target might require that all i64 values
909 be expanded into i32 values. These changes can insert sign and zero
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]910 extensions as needed to make sure that the final code has the same
911 behavior as the input.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]912 <p>A target implementation tells the legalizer which types are supported
913 (and which register class to use for them) by calling the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]914 <tt>addRegisterClass</tt> method in its TargetLowering constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]915</li>
916
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]917<li><p>Eliminate operations that are not supported by the target.</p>
918 <p>Targets often have weird constraints, such as not supporting every
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]919 operation on every supported datatype (e.g. X86 does not support byte
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]920 conditional moves and PowerPC does not support sign-extending loads from
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]921 a 16-bit memory location). Legalize takes care of this by open-coding
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]922 another sequence of operations to emulate the operation ("expansion"), by
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]923 promoting one type to a larger type that supports the operation
924 ("promotion"), or by using a target-specific hook to implement the
925 legalization ("custom").</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]926 <p>A target implementation tells the legalizer which operations are not
927 supported (and which of the above three actions to take) by calling the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]928 <tt>setOperationAction</tt> method in its <tt>TargetLowering</tt>
929 constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]930</li>
931</ol>
932
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]933<p>Prior to the existance of the Legalize pass, we required that every target
934<a href="#selectiondag_optimize">selector</a> supported and handled every
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]935operator and type even if they are not natively supported. The introduction of
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]936the Legalize phase allows all of the cannonicalization patterns to be shared
937across targets, and makes it very easy to optimize the cannonicalized code
938because it is still in the form of a DAG.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]939
940</div>
941
942<!-- _______________________________________________________________________ -->
943<div class="doc_subsubsection">
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]944 <a name="selectiondag_optimize">SelectionDAG Optimization Phase: the DAG
945 Combiner</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]946</div>
947
948<div class="doc_text">
949
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]950<p>The SelectionDAG optimization phase is run twice for code generation: once
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]951immediately after the DAG is built and once after legalization. The first run
952of the pass allows the initial code to be cleaned up (e.g. performing
953optimizations that depend on knowing that the operators have restricted type
954inputs). The second run of the pass cleans up the messy code generated by the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]955Legalize pass, which allows Legalize to be very simple (it can focus on making
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]956code legal instead of focusing on generating <em>good</em> and legal code).</p>
957
958<p>One important class of optimizations performed is optimizing inserted sign
959and zero extension instructions. We currently use ad-hoc techniques, but could
960move to more rigorous techniques in the future. Here are some good papers on
961the subject:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]962
963<p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]964 "<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
965 integer arithmetic</a>"<br>
966 Kevin Redwine and Norman Ramsey<br>
967 International Conference on Compiler Construction (CC) 2004
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]968</p>
969
970
971<p>
972 "<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
973 sign extension elimination</a>"<br>
974 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
975 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
976 and Implementation.
977</p>
978
979</div>
980
981<!-- _______________________________________________________________________ -->
982<div class="doc_subsubsection">
983 <a name="selectiondag_select">SelectionDAG Select Phase</a>
984</div>
985
986<div class="doc_text">
987
988<p>The Select phase is the bulk of the target-specific code for instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]989selection. This phase takes a legal SelectionDAG as input, pattern matches the
990instructions supported by the target to this DAG, and produces a new DAG of
991target code. For example, consider the following LLVM fragment:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]992
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]993<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]994<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]995%t1 = add float %W, %X
996%t2 = mul float %t1, %Y
997%t3 = add float %t2, %Z
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]998</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]999</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1000
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1001<p>This LLVM code corresponds to a SelectionDAG that looks basically like
1002this:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1003
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1004<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1005<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1006(fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1007</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1008</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1009
Chris Lattnera1ff9312005-10-17 15:19:24 +0000[diff] [blame]1010<p>If a target supports floating point multiply-and-add (FMA) operations, one
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1011of the adds can be merged with the multiply. On the PowerPC, for example, the
1012output of the instruction selector might look like this DAG:</p>
1013
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1014<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1015<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1016(FMADDS (FADDS W, X), Y, Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1017</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1018</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1019
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1020<p>The <tt>FMADDS</tt> instruction is a ternary instruction that multiplies its
1021first two operands and adds the third (as single-precision floating-point
1022numbers). The <tt>FADDS</tt> instruction is a simple binary single-precision
1023add instruction. To perform this pattern match, the PowerPC backend includes
1024the following instruction definitions:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1025
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1026<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1027<pre>
1028def FMADDS : AForm_1&lt;59, 29,
1029 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1030 "fmadds $FRT, $FRA, $FRC, $FRB",
1031 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1032 F4RC:$FRB))</b>]&gt;;
1033def FADDS : AForm_2&lt;59, 21,
1034 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1035 "fadds $FRT, $FRA, $FRB",
1036 [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]&gt;;
1037</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1038</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1039
1040<p>The portion of the instruction definition in bold indicates the pattern used
1041to match the instruction. The DAG operators (like <tt>fmul</tt>/<tt>fadd</tt>)
1042are defined in the <tt>lib/Target/TargetSelectionDAG.td</tt> file.
1043"<tt>F4RC</tt>" is the register class of the input and result values.<p>
1044
1045<p>The TableGen DAG instruction selector generator reads the instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1046patterns in the <tt>.td</tt> file and automatically builds parts of the pattern
1047matching code for your target. It has the following strengths:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1048
1049<ul>
1050<li>At compiler-compiler time, it analyzes your instruction patterns and tells
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1051 you if your patterns make sense or not.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1052<li>It can handle arbitrary constraints on operands for the pattern match. In
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1053 particular, it is straight-forward to say things like "match any immediate
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1054 that is a 13-bit sign-extended value". For examples, see the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1055 <tt>immSExt16</tt> and related <tt>tblgen</tt> classes in the PowerPC
1056 backend.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1057<li>It knows several important identities for the patterns defined. For
1058 example, it knows that addition is commutative, so it allows the
1059 <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
1060 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1061 to specially handle this case.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1062<li>It has a full-featured type-inferencing system. In particular, you should
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1063 rarely have to explicitly tell the system what type parts of your patterns
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1064 are. In the <tt>FMADDS</tt> case above, we didn't have to tell
1065 <tt>tblgen</tt> that all of the nodes in the pattern are of type 'f32'. It
1066 was able to infer and propagate this knowledge from the fact that
1067 <tt>F4RC</tt> has type 'f32'.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1068<li>Targets can define their own (and rely on built-in) "pattern fragments".
1069 Pattern fragments are chunks of reusable patterns that get inlined into your
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1070 patterns during compiler-compiler time. For example, the integer
1071 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment that
1072 expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not have a
1073 native '<tt>not</tt>' operation. Targets can define their own short-hand
1074 fragments as they see fit. See the definition of '<tt>not</tt>' and
1075 '<tt>ineg</tt>' for examples.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1076<li>In addition to instructions, targets can specify arbitrary patterns that
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1077 map to one or more instructions using the 'Pat' class. For example,
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1078 the PowerPC has no way to load an arbitrary integer immediate into a
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1079 register in one instruction. To tell tblgen how to do this, it defines:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1080 <br>
1081 <br>
1082 <div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1083 <pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1084// Arbitrary immediate support. Implement in terms of LIS/ORI.
1085def : Pat&lt;(i32 imm:$imm),
1086 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))&gt;;
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1087 </pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1088 </div>
1089 <br>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1090 If none of the single-instruction patterns for loading an immediate into a
1091 register match, this will be used. This rule says "match an arbitrary i32
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1092 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and an
1093 <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to the
1094 left 16 bits') instruction". To make this work, the
1095 <tt>LO16</tt>/<tt>HI16</tt> node transformations are used to manipulate the
1096 input immediate (in this case, take the high or low 16-bits of the
1097 immediate).</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1098<li>While the system does automate a lot, it still allows you to write custom
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1099 C++ code to match special cases if there is something that is hard to
1100 express.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1101</ul>
1102
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1103<p>While it has many strengths, the system currently has some limitations,
1104primarily because it is a work in progress and is not yet finished:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1105
1106<ul>
1107<li>Overall, there is no way to define or match SelectionDAG nodes that define
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1108 multiple values (e.g. <tt>ADD_PARTS</tt>, <tt>LOAD</tt>, <tt>CALL</tt>,
1109 etc). This is the biggest reason that you currently still <em>have to</em>
1110 write custom C++ code for your instruction selector.</li>
1111<li>There is no great way to support matching complex addressing modes yet. In
1112 the future, we will extend pattern fragments to allow them to define
1113 multiple values (e.g. the four operands of the <a href="#x86_memory">X86
Dan Gohmanfd800722007-12-13 20:43:47 +0000[diff] [blame]1114 addressing mode</a>, which are currently matched with custom C++ code).
1115 In addition, we'll extend fragments so that a
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1116 fragment can match multiple different patterns.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1117<li>We don't automatically infer flags like isStore/isLoad yet.</li>
1118<li>We don't automatically generate the set of supported registers and
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1119 operations for the <a href="#selectiondag_legalize">Legalizer</a> yet.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1120<li>We don't have a way of tying in custom legalized nodes yet.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1121</ul>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1122
1123<p>Despite these limitations, the instruction selector generator is still quite
1124useful for most of the binary and logical operations in typical instruction
1125sets. If you run into any problems or can't figure out how to do something,
1126please let Chris know!</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1127
1128</div>
1129
1130<!-- _______________________________________________________________________ -->
1131<div class="doc_subsubsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1132 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1133</div>
1134
1135<div class="doc_text">
1136
1137<p>The scheduling phase takes the DAG of target instructions from the selection
1138phase and assigns an order. The scheduler can pick an order depending on
1139various constraints of the machines (i.e. order for minimal register pressure or
1140try to cover instruction latencies). Once an order is established, the DAG is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1141converted to a list of <tt><a href="#machineinstr">MachineInstr</a></tt>s and
1142the SelectionDAG is destroyed.</p>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1143
Jeff Cohen0b81cda2005-10-24 16:54:55 +0000[diff] [blame]1144<p>Note that this phase is logically separate from the instruction selection
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]1145phase, but is tied to it closely in the code because it operates on
1146SelectionDAGs.</p>
1147
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1148</div>
1149
1150<!-- _______________________________________________________________________ -->
1151<div class="doc_subsubsection">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1152 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
1153</div>
1154
1155<div class="doc_text">
1156
1157<ol>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1158<li>Optional function-at-a-time selection.</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1159<li>Auto-generate entire selector from <tt>.td</tt> file.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1160</ol>
1161
1162</div>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1163
1164<!-- ======================================================================= -->
1165<div class="doc_subsection">
1166 <a name="ssamco">SSA-based Machine Code Optimizations</a>
1167</div>
1168<div class="doc_text"><p>To Be Written</p></div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1169
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1170<!-- ======================================================================= -->
1171<div class="doc_subsection">
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1172 <a name="liveintervals">Live Intervals</a>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1173</div>
1174
1175<div class="doc_text">
1176
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1177<p>Live Intervals are the ranges (intervals) where a variable is <i>live</i>.
1178They are used by some <a href="#regalloc">register allocator</a> passes to
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1179determine if two or more virtual registers which require the same physical
Bill Wendling41b32522006-09-07 08:39:35 +0000[diff] [blame]1180register are live at the same point in the program (i.e., they conflict). When
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1181this situation occurs, one virtual register must be <i>spilled</i>.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1182
1183</div>
1184
1185<!-- _______________________________________________________________________ -->
1186<div class="doc_subsubsection">
1187 <a name="livevariable_analysis">Live Variable Analysis</a>
1188</div>
1189
1190<div class="doc_text">
1191
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1192<p>The first step in determining the live intervals of variables is to
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1193calculate the set of registers that are immediately dead after the
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1194instruction (i.e., the instruction calculates the value, but it is
1195never used) and the set of registers that are used by the instruction,
1196but are never used after the instruction (i.e., they are killed). Live
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1197variable information is computed for each <i>virtual</i> register and
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1198<i>register allocatable</i> physical register in the function. This
1199is done in a very efficient manner because it uses SSA to sparsely
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1200compute lifetime information for virtual registers (which are in SSA
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1201form) and only has to track physical registers within a block. Before
1202register allocation, LLVM can assume that physical registers are only
1203live within a single basic block. This allows it to do a single,
1204local analysis to resolve physical register lifetimes within each
1205basic block. If a physical register is not register allocatable (e.g.,
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1206a stack pointer or condition codes), it is not tracked.</p>
1207
1208<p>Physical registers may be live in to or out of a function. Live in values
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1209are typically arguments in registers. Live out values are typically return
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1210values in registers. Live in values are marked as such, and are given a dummy
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1211"defining" instruction during live intervals analysis. If the last basic block
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1212of a function is a <tt>return</tt>, then it's marked as using all live out
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1213values in the function.</p>
1214
1215<p><tt>PHI</tt> nodes need to be handled specially, because the calculation
1216of the live variable information from a depth first traversal of the CFG of
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1217the function won't guarantee that a virtual register used by the <tt>PHI</tt>
1218node is defined before it's used. When a <tt>PHI</tt> node is encounted, only
1219the definition is handled, because the uses will be handled in other basic
1220blocks.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1221
1222<p>For each <tt>PHI</tt> node of the current basic block, we simulate an
1223assignment at the end of the current basic block and traverse the successor
1224basic blocks. If a successor basic block has a <tt>PHI</tt> node and one of
1225the <tt>PHI</tt> node's operands is coming from the current basic block,
1226then the variable is marked as <i>alive</i> within the current basic block
1227and all of its predecessor basic blocks, until the basic block with the
1228defining instruction is encountered.</p>
1229
1230</div>
1231
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1232<!-- _______________________________________________________________________ -->
1233<div class="doc_subsubsection">
1234 <a name="liveintervals_analysis">Live Intervals Analysis</a>
1235</div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1236
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1237<div class="doc_text">
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1238
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1239<p>We now have the information available to perform the live intervals analysis
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1240and build the live intervals themselves. We start off by numbering the basic
1241blocks and machine instructions. We then handle the "live-in" values. These
1242are in physical registers, so the physical register is assumed to be killed by
1243the end of the basic block. Live intervals for virtual registers are computed
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1244for some ordering of the machine instructions <tt>[1, N]</tt>. A live interval
1245is an interval <tt>[i, j)</tt>, where <tt>1 <= i <= j < N</tt>, for which a
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1246variable is live.</p>
1247
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1248<p><i><b>More to come...</b></i></p>
1249
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1250</div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1251
1252<!-- ======================================================================= -->
1253<div class="doc_subsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1254 <a name="regalloc">Register Allocation</a>
1255</div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1256
1257<div class="doc_text">
1258
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1259<p>The <i>Register Allocation problem</i> consists in mapping a program
1260<i>P<sub>v</sub></i>, that can use an unbounded number of virtual
1261registers, to a program <i>P<sub>p</sub></i> that contains a finite
1262(possibly small) number of physical registers. Each target architecture has
1263a different number of physical registers. If the number of physical
1264registers is not enough to accommodate all the virtual registers, some of
1265them will have to be mapped into memory. These virtuals are called
1266<i>spilled virtuals</i>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1267
1268</div>
1269
1270<!-- _______________________________________________________________________ -->
1271
1272<div class="doc_subsubsection">
1273 <a name="regAlloc_represent">How registers are represented in LLVM</a>
1274</div>
1275
1276<div class="doc_text">
1277
1278<p>In LLVM, physical registers are denoted by integer numbers that
1279normally range from 1 to 1023. To see how this numbering is defined
1280for a particular architecture, you can read the
1281<tt>GenRegisterNames.inc</tt> file for that architecture. For
1282instance, by inspecting
1283<tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the 32-bit
1284register <tt>EAX</tt> is denoted by 15, and the MMX register
1285<tt>MM0</tt> is mapped to 48.</p>
1286
1287<p>Some architectures contain registers that share the same physical
1288location. A notable example is the X86 platform. For instance, in the
1289X86 architecture, the registers <tt>EAX</tt>, <tt>AX</tt> and
1290<tt>AL</tt> share the first eight bits. These physical registers are
1291marked as <i>aliased</i> in LLVM. Given a particular architecture, you
1292can check which registers are aliased by inspecting its
1293<tt>RegisterInfo.td</tt> file. Moreover, the method
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1294<tt>TargetRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1295all the physical registers aliased to the register <tt>p_reg</tt>.</p>
1296
1297<p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>.
1298Elements in the same register class are functionally equivalent, and can
1299be interchangeably used. Each virtual register can only be mapped to
1300physical registers of a particular class. For instance, in the X86
1301architecture, some virtuals can only be allocated to 8 bit registers.
1302A register class is described by <tt>TargetRegisterClass</tt> objects.
1303To discover if a virtual register is compatible with a given physical,
1304this code can be used:
1305</p>
1306
1307<div class="doc_code">
1308<pre>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1309bool RegMapping_Fer::compatible_class(MachineFunction &amp;mf,
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1310 unsigned v_reg,
1311 unsigned p_reg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1312 assert(TargetRegisterInfo::isPhysicalRegister(p_reg) &amp;&amp;
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1313 "Target register must be physical");
Chris Lattner534bcfb2007-12-31 04:16:08 +0000[diff] [blame]1314 const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
1315 return trc-&gt;contains(p_reg);
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1316}
1317</pre>
1318</div>
1319
1320<p>Sometimes, mostly for debugging purposes, it is useful to change
1321the number of physical registers available in the target
1322architecture. This must be done statically, inside the
1323<tt>TargetRegsterInfo.td</tt> file. Just <tt>grep</tt> for
1324<tt>RegisterClass</tt>, the last parameter of which is a list of
1325registers. Just commenting some out is one simple way to avoid them
1326being used. A more polite way is to explicitly exclude some registers
1327from the <i>allocation order</i>. See the definition of the
1328<tt>GR</tt> register class in
1329<tt>lib/Target/IA64/IA64RegisterInfo.td</tt> for an example of this
1330(e.g., <tt>numReservedRegs</tt> registers are hidden.)</p>
1331
1332<p>Virtual registers are also denoted by integer numbers. Contrary to
1333physical registers, different virtual registers never share the same
1334number. The smallest virtual register is normally assigned the number
13351024. This may change, so, in order to know which is the first virtual
1336register, you should access
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1337<tt>TargetRegisterInfo::FirstVirtualRegister</tt>. Any register whose
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1338number is greater than or equal to
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1339<tt>TargetRegisterInfo::FirstVirtualRegister</tt> is considered a virtual
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1340register. Whereas physical registers are statically defined in a
1341<tt>TargetRegisterInfo.td</tt> file and cannot be created by the
1342application developer, that is not the case with virtual registers.
1343In order to create new virtual registers, use the method
Chris Lattner534bcfb2007-12-31 04:16:08 +0000[diff] [blame]1344<tt>MachineRegisterInfo::createVirtualRegister()</tt>. This method will return a
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1345virtual register with the highest code.
1346</p>
1347
1348<p>Before register allocation, the operands of an instruction are
1349mostly virtual registers, although physical registers may also be
1350used. In order to check if a given machine operand is a register, use
1351the boolean function <tt>MachineOperand::isRegister()</tt>. To obtain
1352the integer code of a register, use
1353<tt>MachineOperand::getReg()</tt>. An instruction may define or use a
1354register. For instance, <tt>ADD reg:1026 := reg:1025 reg:1024</tt>
1355defines the registers 1024, and uses registers 1025 and 1026. Given a
1356register operand, the method <tt>MachineOperand::isUse()</tt> informs
1357if that register is being used by the instruction. The method
1358<tt>MachineOperand::isDef()</tt> informs if that registers is being
1359defined.</p>
1360
Gabor Greif04367bf2007-07-06 22:07:22 +0000[diff] [blame]1361<p>We will call physical registers present in the LLVM bitcode before
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1362register allocation <i>pre-colored registers</i>. Pre-colored
1363registers are used in many different situations, for instance, to pass
1364parameters of functions calls, and to store results of particular
1365instructions. There are two types of pre-colored registers: the ones
1366<i>implicitly</i> defined, and those <i>explicitly</i>
1367defined. Explicitly defined registers are normal operands, and can be
1368accessed with <tt>MachineInstr::getOperand(int)::getReg()</tt>. In
1369order to check which registers are implicitly defined by an
1370instruction, use the
1371<tt>TargetInstrInfo::get(opcode)::ImplicitDefs</tt>, where
1372<tt>opcode</tt> is the opcode of the target instruction. One important
1373difference between explicit and implicit physical registers is that
1374the latter are defined statically for each instruction, whereas the
1375former may vary depending on the program being compiled. For example,
1376an instruction that represents a function call will always implicitly
1377define or use the same set of physical registers. To read the
1378registers implicitly used by an instruction, use
1379<tt>TargetInstrInfo::get(opcode)::ImplicitUses</tt>. Pre-colored
1380registers impose constraints on any register allocation algorithm. The
1381register allocator must make sure that none of them is been
1382overwritten by the values of virtual registers while still alive.</p>
1383
1384</div>
1385
1386<!-- _______________________________________________________________________ -->
1387
1388<div class="doc_subsubsection">
1389 <a name="regAlloc_howTo">Mapping virtual registers to physical registers</a>
1390</div>
1391
1392<div class="doc_text">
1393
1394<p>There are two ways to map virtual registers to physical registers (or to
1395memory slots). The first way, that we will call <i>direct mapping</i>,
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1396is based on the use of methods of the classes <tt>TargetRegisterInfo</tt>,
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1397and <tt>MachineOperand</tt>. The second way, that we will call
1398<i>indirect mapping</i>, relies on the <tt>VirtRegMap</tt> class in
1399order to insert loads and stores sending and getting values to and from
1400memory.</p>
1401
1402<p>The direct mapping provides more flexibility to the developer of
1403the register allocator; however, it is more error prone, and demands
1404more implementation work. Basically, the programmer will have to
1405specify where load and store instructions should be inserted in the
1406target function being compiled in order to get and store values in
1407memory. To assign a physical register to a virtual register present in
1408a given operand, use <tt>MachineOperand::setReg(p_reg)</tt>. To insert
1409a store instruction, use
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1410<tt>TargetRegisterInfo::storeRegToStackSlot(...)</tt>, and to insert a load
1411instruction, use <tt>TargetRegisterInfo::loadRegFromStackSlot</tt>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1412
1413<p>The indirect mapping shields the application developer from the
1414complexities of inserting load and store instructions. In order to map
1415a virtual register to a physical one, use
1416<tt>VirtRegMap::assignVirt2Phys(vreg, preg)</tt>. In order to map a
1417certain virtual register to memory, use
1418<tt>VirtRegMap::assignVirt2StackSlot(vreg)</tt>. This method will
1419return the stack slot where <tt>vreg</tt>'s value will be located. If
1420it is necessary to map another virtual register to the same stack
1421slot, use <tt>VirtRegMap::assignVirt2StackSlot(vreg,
1422stack_location)</tt>. One important point to consider when using the
1423indirect mapping, is that even if a virtual register is mapped to
1424memory, it still needs to be mapped to a physical register. This
1425physical register is the location where the virtual register is
1426supposed to be found before being stored or after being reloaded.</p>
1427
1428<p>If the indirect strategy is used, after all the virtual registers
1429have been mapped to physical registers or stack slots, it is necessary
1430to use a spiller object to place load and store instructions in the
1431code. Every virtual that has been mapped to a stack slot will be
1432stored to memory after been defined and will be loaded before being
1433used. The implementation of the spiller tries to recycle load/store
1434instructions, avoiding unnecessary instructions. For an example of how
1435to invoke the spiller, see
1436<tt>RegAllocLinearScan::runOnMachineFunction</tt> in
1437<tt>lib/CodeGen/RegAllocLinearScan.cpp</tt>.</p>
1438
1439</div>
1440
1441<!-- _______________________________________________________________________ -->
1442<div class="doc_subsubsection">
1443 <a name="regAlloc_twoAddr">Handling two address instructions</a>
1444</div>
1445
1446<div class="doc_text">
1447
1448<p>With very rare exceptions (e.g., function calls), the LLVM machine
1449code instructions are three address instructions. That is, each
1450instruction is expected to define at most one register, and to use at
1451most two registers. However, some architectures use two address
1452instructions. In this case, the defined register is also one of the
1453used register. For instance, an instruction such as <tt>ADD %EAX,
1454%EBX</tt>, in X86 is actually equivalent to <tt>%EAX = %EAX +
1455%EBX</tt>.</p>
1456
1457<p>In order to produce correct code, LLVM must convert three address
1458instructions that represent two address instructions into true two
1459address instructions. LLVM provides the pass
1460<tt>TwoAddressInstructionPass</tt> for this specific purpose. It must
1461be run before register allocation takes place. After its execution,
1462the resulting code may no longer be in SSA form. This happens, for
1463instance, in situations where an instruction such as <tt>%a = ADD %b
1464%c</tt> is converted to two instructions such as:</p>
1465
1466<div class="doc_code">
1467<pre>
1468%a = MOVE %b
1469%a = ADD %a %b
1470</pre>
1471</div>
1472
1473<p>Notice that, internally, the second instruction is represented as
1474<tt>ADD %a[def/use] %b</tt>. I.e., the register operand <tt>%a</tt> is
1475both used and defined by the instruction.</p>
1476
1477</div>
1478
1479<!-- _______________________________________________________________________ -->
1480<div class="doc_subsubsection">
1481 <a name="regAlloc_ssaDecon">The SSA deconstruction phase</a>
1482</div>
1483
1484<div class="doc_text">
1485
1486<p>An important transformation that happens during register allocation is called
1487the <i>SSA Deconstruction Phase</i>. The SSA form simplifies many
1488analyses that are performed on the control flow graph of
1489programs. However, traditional instruction sets do not implement
1490PHI instructions. Thus, in order to generate executable code, compilers
1491must replace PHI instructions with other instructions that preserve their
1492semantics.</p>
1493
1494<p>There are many ways in which PHI instructions can safely be removed
1495from the target code. The most traditional PHI deconstruction
1496algorithm replaces PHI instructions with copy instructions. That is
1497the strategy adopted by LLVM. The SSA deconstruction algorithm is
1498implemented in n<tt>lib/CodeGen/>PHIElimination.cpp</tt>. In order to
1499invoke this pass, the identifier <tt>PHIEliminationID</tt> must be
1500marked as required in the code of the register allocator.</p>
1501
1502</div>
1503
1504<!-- _______________________________________________________________________ -->
1505<div class="doc_subsubsection">
1506 <a name="regAlloc_fold">Instruction folding</a>
1507</div>
1508
1509<div class="doc_text">
1510
1511<p><i>Instruction folding</i> is an optimization performed during
1512register allocation that removes unnecessary copy instructions. For
1513instance, a sequence of instructions such as:</p>
1514
1515<div class="doc_code">
1516<pre>
1517%EBX = LOAD %mem_address
1518%EAX = COPY %EBX
1519</pre>
1520</div>
1521
1522<p>can be safely substituted by the single instruction:
1523
1524<div class="doc_code">
1525<pre>
1526%EAX = LOAD %mem_address
1527</pre>
1528</div>
1529
1530<p>Instructions can be folded with the
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1531<tt>TargetRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1532taken when folding instructions; a folded instruction can be quite
1533different from the original instruction. See
1534<tt>LiveIntervals::addIntervalsForSpills</tt> in
1535<tt>lib/CodeGen/LiveIntervalAnalysis.cpp</tt> for an example of its use.</p>
1536
1537</div>
1538
1539<!-- _______________________________________________________________________ -->
1540
1541<div class="doc_subsubsection">
1542 <a name="regAlloc_builtIn">Built in register allocators</a>
1543</div>
1544
1545<div class="doc_text">
1546
1547<p>The LLVM infrastructure provides the application developer with
1548three different register allocators:</p>
1549
1550<ul>
1551 <li><i>Simple</i> - This is a very simple implementation that does
1552 not keep values in registers across instructions. This register
1553 allocator immediately spills every value right after it is
1554 computed, and reloads all used operands from memory to temporary
1555 registers before each instruction.</li>
1556 <li><i>Local</i> - This register allocator is an improvement on the
1557 <i>Simple</i> implementation. It allocates registers on a basic
1558 block level, attempting to keep values in registers and reusing
1559 registers as appropriate.</li>
1560 <li><i>Linear Scan</i> - <i>The default allocator</i>. This is the
1561 well-know linear scan register allocator. Whereas the
1562 <i>Simple</i> and <i>Local</i> algorithms use a direct mapping
1563 implementation technique, the <i>Linear Scan</i> implementation
1564 uses a spiller in order to place load and stores.</li>
1565</ul>
1566
1567<p>The type of register allocator used in <tt>llc</tt> can be chosen with the
1568command line option <tt>-regalloc=...</tt>:</p>
1569
1570<div class="doc_code">
1571<pre>
1572$ llc -f -regalloc=simple file.bc -o sp.s;
1573$ llc -f -regalloc=local file.bc -o lc.s;
1574$ llc -f -regalloc=linearscan file.bc -o ln.s;
1575</pre>
1576</div>
1577
1578</div>
1579
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1580<!-- ======================================================================= -->
1581<div class="doc_subsection">
1582 <a name="proepicode">Prolog/Epilog Code Insertion</a>
1583</div>
1584<div class="doc_text"><p>To Be Written</p></div>
1585<!-- ======================================================================= -->
1586<div class="doc_subsection">
1587 <a name="latemco">Late Machine Code Optimizations</a>
1588</div>
1589<div class="doc_text"><p>To Be Written</p></div>
1590<!-- ======================================================================= -->
1591<div class="doc_subsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1592 <a name="codeemit">Code Emission</a>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1593</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1594<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1595<!-- _______________________________________________________________________ -->
1596<div class="doc_subsubsection">
1597 <a name="codeemit_asm">Generating Assembly Code</a>
1598</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1599<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1600<!-- _______________________________________________________________________ -->
1601<div class="doc_subsubsection">
1602 <a name="codeemit_bin">Generating Binary Machine Code</a>
1603</div>
1604
1605<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1606 <p>For the JIT or <tt>.o</tt> file writer</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1607</div>
1608
1609
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1610<!-- *********************************************************************** -->
1611<div class="doc_section">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1612 <a name="targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1613</div>
1614<!-- *********************************************************************** -->
1615
1616<div class="doc_text">
1617
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1618<p>This section of the document explains features or design decisions that
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1619are specific to the code generator for a particular target.</p>
1620
1621</div>
1622
1623
1624<!-- ======================================================================= -->
1625<div class="doc_subsection">
1626 <a name="x86">The X86 backend</a>
1627</div>
1628
1629<div class="doc_text">
1630
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1631<p>The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
Dan Gohmanfd800722007-12-13 20:43:47 +0000[diff] [blame]1632code generator is capable of targeting a variety of x86-32 and x86-64
1633processors, and includes support for ISA extensions such as MMX and SSE.
1634</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1635
1636</div>
1637
1638<!-- _______________________________________________________________________ -->
1639<div class="doc_subsubsection">
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1640 <a name="x86_tt">X86 Target Triples Supported</a>
1641</div>
1642
1643<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1644
1645<p>The following are the known target triples that are supported by the X86
1646backend. This is not an exhaustive list, and it would be useful to add those
1647that people test.</p>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1648
1649<ul>
1650<li><b>i686-pc-linux-gnu</b> - Linux</li>
1651<li><b>i386-unknown-freebsd5.3</b> - FreeBSD 5.3</li>
1652<li><b>i686-pc-cygwin</b> - Cygwin on Win32</li>
1653<li><b>i686-pc-mingw32</b> - MingW on Win32</li>
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]1654<li><b>i386-pc-mingw32msvc</b> - MingW crosscompiler on Linux</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1655<li><b>i686-apple-darwin*</b> - Apple Darwin on X86</li>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1656</ul>
1657
1658</div>
1659
1660<!-- _______________________________________________________________________ -->
1661<div class="doc_subsubsection">
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]1662 <a name="x86_cc">X86 Calling Conventions supported</a>
1663</div>
1664
1665
1666<div class="doc_text">
1667
1668<p>The folowing target-specific calling conventions are known to backend:</p>
1669
1670<ul>
1671<li><b>x86_StdCall</b> - stdcall calling convention seen on Microsoft Windows
1672platform (CC ID = 64).</li>
1673<li><b>x86_FastCall</b> - fastcall calling convention seen on Microsoft Windows
1674platform (CC ID = 65).</li>
1675</ul>
1676
1677</div>
1678
1679<!-- _______________________________________________________________________ -->
1680<div class="doc_subsubsection">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1681 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
1682</div>
1683
1684<div class="doc_text">
1685
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1686<p>The x86 has a very flexible way of accessing memory. It is capable of
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1687forming memory addresses of the following expression directly in integer
1688instructions (which use ModR/M addressing):</p>
1689
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1690<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1691<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1692Base + [1,2,4,8] * IndexReg + Disp32
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1693</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1694</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1695
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1696<p>In order to represent this, LLVM tracks no less than 4 operands for each
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1697memory operand of this form. This means that the "load" form of '<tt>mov</tt>'
1698has the following <tt>MachineOperand</tt>s in this order:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1699
1700<pre>
1701Index: 0 | 1 2 3 4
1702Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
1703OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
1704</pre>
1705
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1706<p>Stores, and all other instructions, treat the four memory operands in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1707same way and in the same order.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1708
1709</div>
1710
1711<!-- _______________________________________________________________________ -->
1712<div class="doc_subsubsection">
1713 <a name="x86_names">Instruction naming</a>
1714</div>
1715
1716<div class="doc_text">
1717
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1718<p>An instruction name consists of the base name, a default operand size, and a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1719a character per operand with an optional special size. For example:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1720
1721<p>
1722<tt>ADD8rr</tt> -&gt; add, 8-bit register, 8-bit register<br>
1723<tt>IMUL16rmi</tt> -&gt; imul, 16-bit register, 16-bit memory, 16-bit immediate<br>
1724<tt>IMUL16rmi8</tt> -&gt; imul, 16-bit register, 16-bit memory, 8-bit immediate<br>
1725<tt>MOVSX32rm16</tt> -&gt; movsx, 32-bit register, 16-bit memory
1726</p>
1727
1728</div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1729
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1730<!-- ======================================================================= -->
1731<div class="doc_subsection">
1732 <a name="ppc">The PowerPC backend</a>
1733</div>
1734
1735<div class="doc_text">
1736<p>The PowerPC code generator lives in the lib/Target/PowerPC directory. The
1737code generation is retargetable to several variations or <i>subtargets</i> of
1738the PowerPC ISA; including ppc32, ppc64 and altivec.
1739</p>
1740</div>
1741
1742<!-- _______________________________________________________________________ -->
1743<div class="doc_subsubsection">
1744 <a name="ppc_abi">LLVM PowerPC ABI</a>
1745</div>
1746
1747<div class="doc_text">
1748<p>LLVM follows the AIX PowerPC ABI, with two deviations. LLVM uses a PC
1749relative (PIC) or static addressing for accessing global values, so no TOC (r2)
1750is used. Second, r31 is used as a frame pointer to allow dynamic growth of a
1751stack frame. LLVM takes advantage of having no TOC to provide space to save
1752the frame pointer in the PowerPC linkage area of the caller frame. Other
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1753details of PowerPC ABI can be found at <a href=
1754"http://developer.apple.com/documentation/DeveloperTools/Conceptual/LowLevelABI/Articles/32bitPowerPC.html"
1755>PowerPC ABI.</a> Note: This link describes the 32 bit ABI. The
175664 bit ABI is similar except space for GPRs are 8 bytes wide (not 4) and r13 is
1757reserved for system use.</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1758</div>
1759
1760<!-- _______________________________________________________________________ -->
1761<div class="doc_subsubsection">
1762 <a name="ppc_frame">Frame Layout</a>
1763</div>
1764
1765<div class="doc_text">
1766<p>The size of a PowerPC frame is usually fixed for the duration of a
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1767function&rsquo;s invocation. Since the frame is fixed size, all references into
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1768the frame can be accessed via fixed offsets from the stack pointer. The
1769exception to this is when dynamic alloca or variable sized arrays are present,
1770then a base pointer (r31) is used as a proxy for the stack pointer and stack
1771pointer is free to grow or shrink. A base pointer is also used if llvm-gcc is
1772not passed the -fomit-frame-pointer flag. The stack pointer is always aligned to
177316 bytes, so that space allocated for altivec vectors will be properly
1774aligned.</p>
1775<p>An invocation frame is layed out as follows (low memory at top);</p>
1776</div>
1777
1778<div class="doc_text">
1779<table class="layout">
1780 <tr>
1781 <td>Linkage<br><br></td>
1782 </tr>
1783 <tr>
1784 <td>Parameter area<br><br></td>
1785 </tr>
1786 <tr>
1787 <td>Dynamic area<br><br></td>
1788 </tr>
1789 <tr>
1790 <td>Locals area<br><br></td>
1791 </tr>
1792 <tr>
1793 <td>Saved registers area<br><br></td>
1794 </tr>
1795 <tr style="border-style: none hidden none hidden;">
1796 <td><br></td>
1797 </tr>
1798 <tr>
1799 <td>Previous Frame<br><br></td>
1800 </tr>
1801</table>
1802</div>
1803
1804<div class="doc_text">
1805<p>The <i>linkage</i> area is used by a callee to save special registers prior
1806to allocating its own frame. Only three entries are relevant to LLVM. The
1807first entry is the previous stack pointer (sp), aka link. This allows probing
1808tools like gdb or exception handlers to quickly scan the frames in the stack. A
1809function epilog can also use the link to pop the frame from the stack. The
1810third entry in the linkage area is used to save the return address from the lr
1811register. Finally, as mentioned above, the last entry is used to save the
1812previous frame pointer (r31.) The entries in the linkage area are the size of a
1813GPR, thus the linkage area is 24 bytes long in 32 bit mode and 48 bytes in 64
1814bit mode.</p>
1815</div>
1816
1817<div class="doc_text">
1818<p>32 bit linkage area</p>
1819<table class="layout">
1820 <tr>
1821 <td>0</td>
1822 <td>Saved SP (r1)</td>
1823 </tr>
1824 <tr>
1825 <td>4</td>
1826 <td>Saved CR</td>
1827 </tr>
1828 <tr>
1829 <td>8</td>
1830 <td>Saved LR</td>
1831 </tr>
1832 <tr>
1833 <td>12</td>
1834 <td>Reserved</td>
1835 </tr>
1836 <tr>
1837 <td>16</td>
1838 <td>Reserved</td>
1839 </tr>
1840 <tr>
1841 <td>20</td>
1842 <td>Saved FP (r31)</td>
1843 </tr>
1844</table>
1845</div>
1846
1847<div class="doc_text">
1848<p>64 bit linkage area</p>
1849<table class="layout">
1850 <tr>
1851 <td>0</td>
1852 <td>Saved SP (r1)</td>
1853 </tr>
1854 <tr>
1855 <td>8</td>
1856 <td>Saved CR</td>
1857 </tr>
1858 <tr>
1859 <td>16</td>
1860 <td>Saved LR</td>
1861 </tr>
1862 <tr>
1863 <td>24</td>
1864 <td>Reserved</td>
1865 </tr>
1866 <tr>
1867 <td>32</td>
1868 <td>Reserved</td>
1869 </tr>
1870 <tr>
1871 <td>40</td>
1872 <td>Saved FP (r31)</td>
1873 </tr>
1874</table>
1875</div>
1876
1877<div class="doc_text">
1878<p>The <i>parameter area</i> is used to store arguments being passed to a callee
1879function. Following the PowerPC ABI, the first few arguments are actually
1880passed in registers, with the space in the parameter area unused. However, if
1881there are not enough registers or the callee is a thunk or vararg function,
1882these register arguments can be spilled into the parameter area. Thus, the
1883parameter area must be large enough to store all the parameters for the largest
1884call sequence made by the caller. The size must also be mimimally large enough
1885to spill registers r3-r10. This allows callees blind to the call signature,
1886such as thunks and vararg functions, enough space to cache the argument
1887registers. Therefore, the parameter area is minimally 32 bytes (64 bytes in 64
1888bit mode.) Also note that since the parameter area is a fixed offset from the
1889top of the frame, that a callee can access its spilt arguments using fixed
1890offsets from the stack pointer (or base pointer.)</p>
1891</div>
1892
1893<div class="doc_text">
1894<p>Combining the information about the linkage, parameter areas and alignment. A
1895stack frame is minimally 64 bytes in 32 bit mode and 128 bytes in 64 bit
1896mode.</p>
1897</div>
1898
1899<div class="doc_text">
1900<p>The <i>dynamic area</i> starts out as size zero. If a function uses dynamic
1901alloca then space is added to the stack, the linkage and parameter areas are
1902shifted to top of stack, and the new space is available immediately below the
1903linkage and parameter areas. The cost of shifting the linkage and parameter
1904areas is minor since only the link value needs to be copied. The link value can
1905be easily fetched by adding the original frame size to the base pointer. Note
1906that allocations in the dynamic space need to observe 16 byte aligment.</p>
1907</div>
1908
1909<div class="doc_text">
1910<p>The <i>locals area</i> is where the llvm compiler reserves space for local
1911variables.</p>
1912</div>
1913
1914<div class="doc_text">
1915<p>The <i>saved registers area</i> is where the llvm compiler spills callee saved
1916registers on entry to the callee.</p>
1917</div>
1918
1919<!-- _______________________________________________________________________ -->
1920<div class="doc_subsubsection">
1921 <a name="ppc_prolog">Prolog/Epilog</a>
1922</div>
1923
1924<div class="doc_text">
1925<p>The llvm prolog and epilog are the same as described in the PowerPC ABI, with
1926the following exceptions. Callee saved registers are spilled after the frame is
1927created. This allows the llvm epilog/prolog support to be common with other
1928targets. The base pointer callee saved register r31 is saved in the TOC slot of
1929linkage area. This simplifies allocation of space for the base pointer and
1930makes it convenient to locate programatically and during debugging.</p>
1931</div>
1932
1933<!-- _______________________________________________________________________ -->
1934<div class="doc_subsubsection">
1935 <a name="ppc_dynamic">Dynamic Allocation</a>
1936</div>
1937
1938<div class="doc_text">
1939<p></p>
1940</div>
1941
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1942<div class="doc_text">
1943<p><i>TODO - More to come.</i></p>
1944</div>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1945
1946
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1947<!-- *********************************************************************** -->
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1955 <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
Reid Spencer05fe4b02006-03-14 05:39:39 +0000[diff] [blame]1956 <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1957 Last modified: $Date$
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