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Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that X86 uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef X86ISELLOWERING_H
16#define X86ISELLOWERING_H
17
Evan Cheng559806f2006-01-27 08:10:46 +000018#include "X86Subtarget.h"
Anton Korobeynikov2365f512007-07-14 14:06:15 +000019#include "X86RegisterInfo.h"
Gordon Henriksen86737662008-01-05 16:56:59 +000020#include "X86MachineFunctionInfo.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000021#include "llvm/Target/TargetLowering.h"
Evan Chengddc419c2010-01-26 19:04:47 +000022#include "llvm/Target/TargetOptions.h"
Ted Kremenekb388eb82008-09-03 02:54:11 +000023#include "llvm/CodeGen/FastISel.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000024#include "llvm/CodeGen/SelectionDAG.h"
Rafael Espindola1b5dcc32007-08-31 15:06:30 +000025#include "llvm/CodeGen/CallingConvLower.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000026
27namespace llvm {
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000028 namespace X86ISD {
Evan Chengd9558e02006-01-06 00:43:03 +000029 // X86 Specific DAG Nodes
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000030 enum NodeType {
31 // Start the numbering where the builtin ops leave off.
Dan Gohman0ba2bcf2008-09-23 18:42:32 +000032 FIRST_NUMBER = ISD::BUILTIN_OP_END,
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000033
Evan Cheng18efe262007-12-14 02:13:44 +000034 /// BSF - Bit scan forward.
35 /// BSR - Bit scan reverse.
36 BSF,
37 BSR,
38
Evan Chenge3413162006-01-09 18:33:28 +000039 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
41 SHLD,
42 SHRD,
43
Evan Chengef6ffb12006-01-31 03:14:29 +000044 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
46 FAND,
47
Evan Cheng68c47cb2007-01-05 07:55:56 +000048 /// FOR - Bitwise logical OR of floating point values. This corresponds
49 /// to X86::ORPS or X86::ORPD.
50 FOR,
51
Evan Cheng223547a2006-01-31 22:28:30 +000052 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53 /// to X86::XORPS or X86::XORPD.
54 FXOR,
55
Evan Cheng73d6cf12007-01-05 21:37:56 +000056 /// FSRL - Bitwise logical right shift of floating point values. These
57 /// corresponds to X86::PSRLDQ.
Evan Cheng68c47cb2007-01-05 07:55:56 +000058 FSRL,
59
Evan Chenge3de85b2006-02-04 02:20:30 +000060 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
61 /// integer source in memory and FP reg result. This corresponds to the
62 /// X86::FILD*m instructions. It has three inputs (token chain, address,
63 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
64 /// also produces a flag).
Evan Chenga3195e82006-01-12 22:54:21 +000065 FILD,
Evan Chenge3de85b2006-02-04 02:20:30 +000066 FILD_FLAG,
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000067
68 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
69 /// integer destination in memory and a FP reg source. This corresponds
70 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
Chris Lattner91897772006-10-18 18:26:48 +000071 /// has two inputs (token chain and address) and two outputs (int value
72 /// and token chain).
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000073 FP_TO_INT16_IN_MEM,
74 FP_TO_INT32_IN_MEM,
75 FP_TO_INT64_IN_MEM,
76
Evan Chengb077b842005-12-21 02:39:21 +000077 /// FLD - This instruction implements an extending load to FP stack slots.
78 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
Evan Cheng38bcbaf2005-12-23 07:31:11 +000079 /// operand, ptr to load from, and a ValueType node indicating the type
80 /// to load to.
Evan Chengb077b842005-12-21 02:39:21 +000081 FLD,
82
Evan Chengd90eb7f2006-01-05 00:27:02 +000083 /// FST - This instruction implements a truncating store to FP stack
84 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
85 /// chain operand, value to store, address, and a ValueType to store it
86 /// as.
87 FST,
88
Dan Gohman98ca4f22009-08-05 01:29:28 +000089 /// CALL - These operations represent an abstract X86 call
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000090 /// instruction, which includes a bunch of information. In particular the
91 /// operands of these node are:
92 ///
93 /// #0 - The incoming token chain
94 /// #1 - The callee
95 /// #2 - The number of arg bytes the caller pushes on the stack.
96 /// #3 - The number of arg bytes the callee pops off the stack.
97 /// #4 - The value to pass in AL/AX/EAX (optional)
98 /// #5 - The value to pass in DL/DX/EDX (optional)
99 ///
100 /// The result values of these nodes are:
101 ///
102 /// #0 - The outgoing token chain
103 /// #1 - The first register result value (optional)
104 /// #2 - The second register result value (optional)
105 ///
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000106 CALL,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000107
Andrew Lenharthb873ff32005-11-20 21:41:10 +0000108 /// RDTSC_DAG - This operation implements the lowering for
109 /// readcyclecounter
110 RDTSC_DAG,
Evan Cheng7df96d62005-12-17 01:21:05 +0000111
112 /// X86 compare and logical compare instructions.
Evan Cheng7d6ff3a2007-09-17 17:42:53 +0000113 CMP, COMI, UCOMI,
Evan Cheng7df96d62005-12-17 01:21:05 +0000114
Dan Gohmanc7a37d42008-12-23 22:45:23 +0000115 /// X86 bit-test instructions.
116 BT,
117
Dan Gohman2004eb62009-03-23 15:40:10 +0000118 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the flag
Evan Chengd5781fc2005-12-21 20:21:51 +0000119 /// operand produced by a CMP instruction.
120 SETCC,
121
Evan Chengad9c0a32009-12-15 00:53:42 +0000122 // Same as SETCC except it's materialized with a sbb and the value is all
123 // one's or all zero's.
124 SETCC_CARRY,
125
Chris Lattner2b9f4342009-03-12 06:46:02 +0000126 /// X86 conditional moves. Operand 0 and operand 1 are the two values
127 /// to select from. Operand 2 is the condition code, and operand 3 is the
128 /// flag operand produced by a CMP or TEST instruction. It also writes a
129 /// flag result.
Evan Cheng7df96d62005-12-17 01:21:05 +0000130 CMOV,
Evan Cheng898101c2005-12-19 23:12:38 +0000131
Dan Gohman2004eb62009-03-23 15:40:10 +0000132 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
133 /// is the block to branch if condition is true, operand 2 is the
134 /// condition code, and operand 3 is the flag operand produced by a CMP
Evan Chengd5781fc2005-12-21 20:21:51 +0000135 /// or TEST instruction.
Evan Cheng898101c2005-12-19 23:12:38 +0000136 BRCOND,
Evan Chengb077b842005-12-21 02:39:21 +0000137
Dan Gohman2004eb62009-03-23 15:40:10 +0000138 /// Return with a flag operand. Operand 0 is the chain operand, operand
139 /// 1 is the number of bytes of stack to pop.
Evan Chengb077b842005-12-21 02:39:21 +0000140 RET_FLAG,
Evan Cheng67f92a72006-01-11 22:15:48 +0000141
142 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
143 REP_STOS,
144
145 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
146 REP_MOVS,
Evan Cheng223547a2006-01-31 22:28:30 +0000147
Evan Cheng7ccced62006-02-18 00:15:05 +0000148 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
149 /// at function entry, used for PIC code.
150 GlobalBaseReg,
Evan Chenga0ea0532006-02-23 02:43:52 +0000151
Bill Wendling056292f2008-09-16 21:48:12 +0000152 /// Wrapper - A wrapper node for TargetConstantPool,
153 /// TargetExternalSymbol, and TargetGlobalAddress.
Evan Cheng020d2e82006-02-23 20:41:18 +0000154 Wrapper,
Evan Cheng48090aa2006-03-21 23:01:21 +0000155
Evan Cheng0085a282006-11-30 21:55:46 +0000156 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
157 /// relative displacements.
158 WrapperRIP,
159
Mon P Wangeb38ebf2010-01-24 00:05:03 +0000160 /// MOVQ2DQ - Copies a 64-bit value from a vector to another vector.
161 /// Can be used to move a vector value from a MMX register to a XMM
162 /// register.
163 MOVQ2DQ,
164
Nate Begeman14d12ca2008-02-11 04:19:36 +0000165 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
166 /// i32, corresponds to X86::PEXTRB.
167 PEXTRB,
168
Evan Chengb067a1e2006-03-31 19:22:53 +0000169 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
Evan Cheng653159f2006-03-31 21:55:24 +0000170 /// i32, corresponds to X86::PEXTRW.
Evan Chengb067a1e2006-03-31 19:22:53 +0000171 PEXTRW,
Evan Cheng653159f2006-03-31 21:55:24 +0000172
Nate Begeman14d12ca2008-02-11 04:19:36 +0000173 /// INSERTPS - Insert any element of a 4 x float vector into any element
174 /// of a destination 4 x floatvector.
175 INSERTPS,
176
177 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
178 /// corresponds to X86::PINSRB.
179 PINSRB,
180
Evan Cheng653159f2006-03-31 21:55:24 +0000181 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
182 /// corresponds to X86::PINSRW.
Evan Cheng8ca29322006-11-10 21:43:37 +0000183 PINSRW,
184
Nate Begemanb9a47b82009-02-23 08:49:38 +0000185 /// PSHUFB - Shuffle 16 8-bit values within a vector.
186 PSHUFB,
187
Evan Cheng8ca29322006-11-10 21:43:37 +0000188 /// FMAX, FMIN - Floating point max and min.
189 ///
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +0000190 FMAX, FMIN,
Dan Gohman20382522007-07-10 00:05:58 +0000191
192 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
193 /// approximation. Note that these typically require refinement
194 /// in order to obtain suitable precision.
195 FRSQRT, FRCP,
196
Rafael Espindola094fad32009-04-08 21:14:34 +0000197 // TLSADDR - Thread Local Storage.
198 TLSADDR,
199
200 // SegmentBaseAddress - The address segment:0
201 SegmentBaseAddress,
Anton Korobeynikov2365f512007-07-14 14:06:15 +0000202
Evan Cheng7e2ff772008-05-08 00:57:18 +0000203 // EH_RETURN - Exception Handling helpers.
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000204 EH_RETURN,
205
Arnold Schwaighofer4fe30732008-03-19 16:39:45 +0000206 /// TC_RETURN - Tail call return.
207 /// operand #0 chain
208 /// operand #1 callee (register or absolute)
209 /// operand #2 stack adjustment
210 /// operand #3 optional in flag
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +0000211 TC_RETURN,
212
Evan Cheng7e2ff772008-05-08 00:57:18 +0000213 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
Andrew Lenharth26ed8692008-03-01 21:52:34 +0000214 LCMPXCHG_DAG,
Andrew Lenharthd19189e2008-03-05 01:15:49 +0000215 LCMPXCHG8_DAG,
Andrew Lenharth26ed8692008-03-01 21:52:34 +0000216
Evan Cheng7e2ff772008-05-08 00:57:18 +0000217 // FNSTCW16m - Store FP control world into i16 memory.
218 FNSTCW16m,
219
Evan Chengd880b972008-05-09 21:53:03 +0000220 // VZEXT_MOVL - Vector move low and zero extend.
221 VZEXT_MOVL,
222
223 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
Evan Chengf26ffe92008-05-29 08:22:04 +0000224 VZEXT_LOAD,
225
226 // VSHL, VSRL - Vector logical left / right shift.
Nate Begeman30a0de92008-07-17 16:51:19 +0000227 VSHL, VSRL,
Nate Begeman9008ca62009-04-27 18:41:29 +0000228
229 // CMPPD, CMPPS - Vector double/float comparison.
Nate Begeman30a0de92008-07-17 16:51:19 +0000230 // CMPPD, CMPPS - Vector double/float comparison.
231 CMPPD, CMPPS,
232
233 // PCMP* - Vector integer comparisons.
234 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
Bill Wendlingab55ebd2008-12-12 00:56:36 +0000235 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
236
Dan Gohman076aee32009-03-04 19:44:21 +0000237 // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results.
238 ADD, SUB, SMUL, UMUL,
Dan Gohmane220c4b2009-09-18 19:59:53 +0000239 INC, DEC, OR, XOR, AND,
Evan Cheng73f24c92009-03-30 21:36:47 +0000240
241 // MUL_IMM - X86 specific multiply by immediate.
Eric Christopher71c67532009-07-29 00:28:05 +0000242 MUL_IMM,
243
244 // PTEST - Vector bitwise comparisons
Dan Gohmand6708ea2009-08-15 01:38:56 +0000245 PTEST,
246
247 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
248 // according to %al. An operator is needed so that this can be expanded
249 // with control flow.
Dan Gohmanc76909a2009-09-25 20:36:54 +0000250 VASTART_SAVE_XMM_REGS,
251
252 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
253 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
254 // Atomic 64-bit binary operations.
255 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
256 ATOMSUB64_DAG,
257 ATOMOR64_DAG,
258 ATOMXOR64_DAG,
259 ATOMAND64_DAG,
260 ATOMNAND64_DAG,
261 ATOMSWAP64_DAG
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000262 };
263 }
264
Evan Cheng0d9e9762008-01-29 19:34:22 +0000265 /// Define some predicates that are used for node matching.
266 namespace X86 {
267 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
268 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
Nate Begeman9008ca62009-04-27 18:41:29 +0000269 bool isPSHUFDMask(ShuffleVectorSDNode *N);
Evan Cheng0188ecb2006-03-22 18:59:22 +0000270
Evan Cheng0d9e9762008-01-29 19:34:22 +0000271 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
272 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
Nate Begeman9008ca62009-04-27 18:41:29 +0000273 bool isPSHUFHWMask(ShuffleVectorSDNode *N);
Evan Cheng506d3df2006-03-29 23:07:14 +0000274
Evan Cheng0d9e9762008-01-29 19:34:22 +0000275 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
276 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
Nate Begeman9008ca62009-04-27 18:41:29 +0000277 bool isPSHUFLWMask(ShuffleVectorSDNode *N);
Evan Cheng506d3df2006-03-29 23:07:14 +0000278
Evan Cheng0d9e9762008-01-29 19:34:22 +0000279 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
280 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
Nate Begeman9008ca62009-04-27 18:41:29 +0000281 bool isSHUFPMask(ShuffleVectorSDNode *N);
Evan Cheng14aed5e2006-03-24 01:18:28 +0000282
Evan Cheng0d9e9762008-01-29 19:34:22 +0000283 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
284 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
Nate Begeman9008ca62009-04-27 18:41:29 +0000285 bool isMOVHLPSMask(ShuffleVectorSDNode *N);
Evan Cheng2c0dbd02006-03-24 02:58:06 +0000286
Evan Cheng0d9e9762008-01-29 19:34:22 +0000287 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
288 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
289 /// <2, 3, 2, 3>
Nate Begeman9008ca62009-04-27 18:41:29 +0000290 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
Evan Cheng6e56e2c2006-11-07 22:14:24 +0000291
Evan Cheng0d9e9762008-01-29 19:34:22 +0000292 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
Nate Begeman9008ca62009-04-27 18:41:29 +0000293 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
294 bool isMOVLPMask(ShuffleVectorSDNode *N);
Evan Cheng5ced1d82006-04-06 23:23:56 +0000295
Evan Cheng0d9e9762008-01-29 19:34:22 +0000296 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
Nate Begeman9008ca62009-04-27 18:41:29 +0000297 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
Evan Cheng0d9e9762008-01-29 19:34:22 +0000298 /// as well as MOVLHPS.
Nate Begeman0b10b912009-11-07 23:17:15 +0000299 bool isMOVLHPSMask(ShuffleVectorSDNode *N);
Evan Cheng5ced1d82006-04-06 23:23:56 +0000300
Evan Cheng0d9e9762008-01-29 19:34:22 +0000301 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
302 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
Nate Begeman9008ca62009-04-27 18:41:29 +0000303 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
Evan Cheng0038e592006-03-28 00:39:58 +0000304
Evan Cheng0d9e9762008-01-29 19:34:22 +0000305 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
306 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
Nate Begeman9008ca62009-04-27 18:41:29 +0000307 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
Evan Cheng4fcb9222006-03-28 02:43:26 +0000308
Evan Cheng0d9e9762008-01-29 19:34:22 +0000309 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
310 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
311 /// <0, 0, 1, 1>
Nate Begeman9008ca62009-04-27 18:41:29 +0000312 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N);
Evan Cheng1d5a8cc2006-04-05 07:20:06 +0000313
Evan Cheng0d9e9762008-01-29 19:34:22 +0000314 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
315 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
316 /// <2, 2, 3, 3>
Nate Begeman9008ca62009-04-27 18:41:29 +0000317 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N);
Bill Wendling2f9bb1a2007-04-24 21:16:55 +0000318
Evan Cheng0d9e9762008-01-29 19:34:22 +0000319 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
320 /// specifies a shuffle of elements that is suitable for input to MOVSS,
321 /// MOVSD, and MOVD, i.e. setting the lowest element.
Nate Begeman9008ca62009-04-27 18:41:29 +0000322 bool isMOVLMask(ShuffleVectorSDNode *N);
Evan Chengd6d1cbd2006-04-11 00:19:04 +0000323
Evan Cheng0d9e9762008-01-29 19:34:22 +0000324 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
325 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
Nate Begeman9008ca62009-04-27 18:41:29 +0000326 bool isMOVSHDUPMask(ShuffleVectorSDNode *N);
Evan Chengd9539472006-04-14 21:59:03 +0000327
Evan Cheng0d9e9762008-01-29 19:34:22 +0000328 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
329 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
Nate Begeman9008ca62009-04-27 18:41:29 +0000330 bool isMOVSLDUPMask(ShuffleVectorSDNode *N);
Evan Chengf686d9b2006-10-27 21:08:32 +0000331
Evan Cheng0b457f02008-09-25 20:50:48 +0000332 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
333 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
Nate Begeman9008ca62009-04-27 18:41:29 +0000334 bool isMOVDDUPMask(ShuffleVectorSDNode *N);
Evan Cheng0b457f02008-09-25 20:50:48 +0000335
Nate Begemana09008b2009-10-19 02:17:23 +0000336 /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand
337 /// specifies a shuffle of elements that is suitable for input to PALIGNR.
338 bool isPALIGNRMask(ShuffleVectorSDNode *N);
339
Evan Cheng0d9e9762008-01-29 19:34:22 +0000340 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
341 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
342 /// instructions.
343 unsigned getShuffleSHUFImmediate(SDNode *N);
Evan Cheng506d3df2006-03-29 23:07:14 +0000344
Evan Cheng0d9e9762008-01-29 19:34:22 +0000345 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
Nate Begemana09008b2009-10-19 02:17:23 +0000346 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction.
Evan Cheng0d9e9762008-01-29 19:34:22 +0000347 unsigned getShufflePSHUFHWImmediate(SDNode *N);
Evan Cheng506d3df2006-03-29 23:07:14 +0000348
Nate Begemana09008b2009-10-19 02:17:23 +0000349 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
350 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction.
Evan Cheng0d9e9762008-01-29 19:34:22 +0000351 unsigned getShufflePSHUFLWImmediate(SDNode *N);
Evan Cheng37b73872009-07-30 08:33:02 +0000352
Nate Begemana09008b2009-10-19 02:17:23 +0000353 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
354 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
355 unsigned getShufflePALIGNRImmediate(SDNode *N);
356
Evan Cheng37b73872009-07-30 08:33:02 +0000357 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
358 /// constant +0.0.
359 bool isZeroNode(SDValue Elt);
Anton Korobeynikovb5e01722009-08-05 23:01:26 +0000360
361 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
362 /// fit into displacement field of the instruction.
363 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
364 bool hasSymbolicDisplacement = true);
Evan Chengddc419c2010-01-26 19:04:47 +0000365
366 /// IsEligibleForTailCallOpt - Return true if it's legal to perform tail call
367 /// optimization for the given calling convention.
368 bool IsEligibleForTailCallOpt(CallingConv::ID CC);
Evan Cheng0d9e9762008-01-29 19:34:22 +0000369 }
370
Chris Lattner91897772006-10-18 18:26:48 +0000371 //===--------------------------------------------------------------------===//
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000372 // X86TargetLowering - X86 Implementation of the TargetLowering interface
373 class X86TargetLowering : public TargetLowering {
374 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
Evan Cheng25ab6902006-09-08 06:48:29 +0000375 int RegSaveFrameIndex; // X86-64 vararg func register save area.
376 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
377 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000378 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
379 int BytesCallerReserves; // Number of arg bytes caller makes.
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000380
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000381 public:
Dan Gohmanc9f5f3f2008-05-14 01:58:56 +0000382 explicit X86TargetLowering(X86TargetMachine &TM);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000383
Chris Lattner589c6f62010-01-26 06:28:43 +0000384 /// getPICBaseSymbol - Return the X86-32 PIC base.
385 MCSymbol *getPICBaseSymbol(const MachineFunction *MF, MCContext &Ctx) const;
386
Chris Lattnerc64daab2010-01-26 05:02:42 +0000387 virtual unsigned getJumpTableEncoding() const;
Chris Lattner5e1df8d2010-01-25 23:38:14 +0000388
Chris Lattnerc64daab2010-01-26 05:02:42 +0000389 virtual const MCExpr *
390 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
391 const MachineBasicBlock *MBB, unsigned uid,
392 MCContext &Ctx) const;
393
Evan Chengcc415862007-11-09 01:32:10 +0000394 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
395 /// jumptable.
Chris Lattnerc64daab2010-01-26 05:02:42 +0000396 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
397 SelectionDAG &DAG) const;
Chris Lattner589c6f62010-01-26 06:28:43 +0000398 virtual const MCExpr *
399 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
400 unsigned JTI, MCContext &Ctx) const;
401
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000402 // Return the number of bytes that a function should pop when it returns (in
403 // addition to the space used by the return address).
404 //
405 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
406
407 // Return the number of bytes that the caller reserves for arguments passed
408 // to this function.
409 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
410
Chris Lattner54e3efd2007-02-26 04:01:25 +0000411 /// getStackPtrReg - Return the stack pointer register we are using: either
412 /// ESP or RSP.
413 unsigned getStackPtrReg() const { return X86StackPtr; }
Evan Cheng29286502008-01-23 23:17:41 +0000414
415 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
416 /// function arguments in the caller parameter area. For X86, aggregates
417 /// that contains are placed at 16-byte boundaries while the rest are at
418 /// 4-byte boundaries.
419 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
Evan Chengf0df0312008-05-15 08:39:06 +0000420
421 /// getOptimalMemOpType - Returns the target specific optimal type for load
Evan Cheng0ef8de32008-05-15 22:13:02 +0000422 /// and store operations as a result of memset, memcpy, and memmove
Owen Andersone50ed302009-08-10 22:56:29 +0000423 /// lowering. It returns EVT::iAny if SelectionDAG should be responsible for
Evan Chengf0df0312008-05-15 08:39:06 +0000424 /// determining it.
Bill Wendlingaf566342009-08-15 21:21:19 +0000425 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
426 bool isSrcConst, bool isSrcStr,
427 SelectionDAG &DAG) const;
428
429 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
430 /// unaligned memory accesses. of the specified type.
431 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
432 return true;
433 }
Bill Wendling20c568f2009-06-30 22:38:32 +0000434
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000435 /// LowerOperation - Provide custom lowering hooks for some operations.
436 ///
Dan Gohman475871a2008-07-27 21:46:04 +0000437 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000438
Duncan Sands1607f052008-12-01 11:39:25 +0000439 /// ReplaceNodeResults - Replace the results of node with an illegal result
440 /// type with new values built out of custom code.
Chris Lattner27a6c732007-11-24 07:07:01 +0000441 ///
Duncan Sands1607f052008-12-01 11:39:25 +0000442 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
443 SelectionDAG &DAG);
Chris Lattner27a6c732007-11-24 07:07:01 +0000444
445
Dan Gohman475871a2008-07-27 21:46:04 +0000446 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
Evan Cheng206ee9d2006-07-07 08:33:52 +0000447
Evan Chengff9b3732008-01-30 18:18:23 +0000448 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
Evan Chengfb2e7522009-09-18 21:02:19 +0000449 MachineBasicBlock *MBB,
450 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
Evan Cheng4a460802006-01-11 00:33:36 +0000451
Mon P Wang63307c32008-05-05 19:05:59 +0000452
Evan Cheng72261582005-12-20 06:22:03 +0000453 /// getTargetNodeName - This method returns the name of a target specific
454 /// DAG node.
455 virtual const char *getTargetNodeName(unsigned Opcode) const;
456
Scott Michel5b8f82e2008-03-10 15:42:14 +0000457 /// getSetCCResultType - Return the ISD::SETCC ValueType
Owen Anderson825b72b2009-08-11 20:47:22 +0000458 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000459
Nate Begeman368e18d2006-02-16 21:11:51 +0000460 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
461 /// in Mask are known to be either zero or one and return them in the
462 /// KnownZero/KnownOne bitsets.
Dan Gohman475871a2008-07-27 21:46:04 +0000463 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman977a76f2008-02-13 22:28:48 +0000464 const APInt &Mask,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000465 APInt &KnownZero,
466 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000467 const SelectionDAG &DAG,
Nate Begeman368e18d2006-02-16 21:11:51 +0000468 unsigned Depth = 0) const;
Evan Chengad4196b2008-05-12 19:56:52 +0000469
470 virtual bool
471 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
Nate Begeman368e18d2006-02-16 21:11:51 +0000472
Dan Gohman475871a2008-07-27 21:46:04 +0000473 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000474
Chris Lattnerb8105652009-07-20 17:51:36 +0000475 virtual bool ExpandInlineAsm(CallInst *CI) const;
476
Chris Lattner4234f572007-03-25 02:14:49 +0000477 ConstraintType getConstraintType(const std::string &Constraint) const;
Chris Lattnerf4dff842006-07-11 02:54:03 +0000478
Chris Lattner259e97c2006-01-31 19:43:35 +0000479 std::vector<unsigned>
Chris Lattner1efa40f2006-02-22 00:56:39 +0000480 getRegClassForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000481 EVT VT) const;
Chris Lattner48884cd2007-08-25 00:47:38 +0000482
Owen Andersone50ed302009-08-10 22:56:29 +0000483 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000484
Chris Lattner48884cd2007-08-25 00:47:38 +0000485 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
Evan Chengda43bcf2008-09-24 00:05:32 +0000486 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
487 /// true it means one of the asm constraint of the inline asm instruction
488 /// being processed is 'm'.
Dan Gohman475871a2008-07-27 21:46:04 +0000489 virtual void LowerAsmOperandForConstraint(SDValue Op,
Chris Lattner48884cd2007-08-25 00:47:38 +0000490 char ConstraintLetter,
Evan Chengda43bcf2008-09-24 00:05:32 +0000491 bool hasMemory,
Dan Gohman475871a2008-07-27 21:46:04 +0000492 std::vector<SDValue> &Ops,
Chris Lattner5e764232008-04-26 23:02:14 +0000493 SelectionDAG &DAG) const;
Chris Lattner22aaf1d2006-10-31 20:13:11 +0000494
Chris Lattner91897772006-10-18 18:26:48 +0000495 /// getRegForInlineAsmConstraint - Given a physical register constraint
496 /// (e.g. {edx}), return the register number and the register class for the
497 /// register. This should only be used for C_Register constraints. On
498 /// error, this returns a register number of 0.
Chris Lattnerf76d1802006-07-31 23:26:50 +0000499 std::pair<unsigned, const TargetRegisterClass*>
500 getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000501 EVT VT) const;
Chris Lattnerf76d1802006-07-31 23:26:50 +0000502
Chris Lattnerc9addb72007-03-30 23:15:24 +0000503 /// isLegalAddressingMode - Return true if the addressing mode represented
504 /// by AM is legal for this target, for a load/store of the specified type.
505 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
506
Evan Cheng2bd122c2007-10-26 01:56:11 +0000507 /// isTruncateFree - Return true if it's free to truncate a value of
508 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
509 /// register EAX to i16 by referencing its sub-register AX.
510 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
Owen Andersone50ed302009-08-10 22:56:29 +0000511 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
Dan Gohman97121ba2009-04-08 00:15:30 +0000512
513 /// isZExtFree - Return true if any actual instruction that defines a
514 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
515 /// register. This does not necessarily include registers defined in
516 /// unknown ways, such as incoming arguments, or copies from unknown
517 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
518 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
519 /// all instructions that define 32-bit values implicit zero-extend the
520 /// result out to 64 bits.
521 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const;
Owen Andersone50ed302009-08-10 22:56:29 +0000522 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
Dan Gohman97121ba2009-04-08 00:15:30 +0000523
Evan Cheng8b944d32009-05-28 00:35:15 +0000524 /// isNarrowingProfitable - Return true if it's profitable to narrow
525 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
526 /// from i32 to i8 but not from i32 to i16.
Owen Andersone50ed302009-08-10 22:56:29 +0000527 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
Evan Cheng8b944d32009-05-28 00:35:15 +0000528
Evan Chengeb2f9692009-10-27 19:56:55 +0000529 /// isFPImmLegal - Returns true if the target can instruction select the
530 /// specified FP immediate natively. If false, the legalizer will
531 /// materialize the FP immediate as a load from a constant pool.
Evan Chenga1eaa3c2009-10-28 01:43:28 +0000532 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
Evan Chengeb2f9692009-10-27 19:56:55 +0000533
Evan Cheng0188ecb2006-03-22 18:59:22 +0000534 /// isShuffleMaskLegal - Targets can use this to indicate that they only
535 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
Chris Lattner91897772006-10-18 18:26:48 +0000536 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
537 /// values are assumed to be legal.
Nate Begeman5a5ca152009-04-29 05:20:52 +0000538 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
Owen Andersone50ed302009-08-10 22:56:29 +0000539 EVT VT) const;
Evan Cheng39623da2006-04-20 08:58:49 +0000540
541 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
542 /// used by Targets can use this to indicate if there is a suitable
543 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
544 /// pool entry.
Nate Begeman5a5ca152009-04-29 05:20:52 +0000545 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
Owen Andersone50ed302009-08-10 22:56:29 +0000546 EVT VT) const;
Evan Cheng6fd599f2008-03-05 01:30:59 +0000547
548 /// ShouldShrinkFPConstant - If true, then instruction selection should
549 /// seek to shrink the FP constant of the specified type to a smaller type
550 /// in order to save space and / or reduce runtime.
Owen Andersone50ed302009-08-10 22:56:29 +0000551 virtual bool ShouldShrinkFPConstant(EVT VT) const {
Evan Cheng6fd599f2008-03-05 01:30:59 +0000552 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
553 // expensive than a straight movsd. On the other hand, it's important to
554 // shrink long double fp constant since fldt is very slow.
Owen Anderson825b72b2009-08-11 20:47:22 +0000555 return !X86ScalarSSEf64 || VT == MVT::f80;
Evan Cheng6fd599f2008-03-05 01:30:59 +0000556 }
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000557
558 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
Dan Gohmana9c1dd72009-08-01 21:25:00 +0000559 /// for tail call optimization. Targets which want to do tail call
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000560 /// optimization should implement this function.
Dan Gohman98ca4f22009-08-05 01:29:28 +0000561 virtual bool
562 IsEligibleForTailCallOptimization(SDValue Callee,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000563 CallingConv::ID CalleeCC,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000564 bool isVarArg,
565 const SmallVectorImpl<ISD::InputArg> &Ins,
566 SelectionDAG& DAG) const;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000567
Dan Gohman707e0182008-04-12 04:36:06 +0000568 virtual const X86Subtarget* getSubtarget() {
569 return Subtarget;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000570 }
571
Chris Lattner3d661852008-01-18 06:52:41 +0000572 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
573 /// computed in an SSE register, not on the X87 floating point stack.
Owen Andersone50ed302009-08-10 22:56:29 +0000574 bool isScalarFPTypeInSSEReg(EVT VT) const {
Owen Anderson825b72b2009-08-11 20:47:22 +0000575 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
576 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
Chris Lattner3d661852008-01-18 06:52:41 +0000577 }
Dan Gohmand9f3c482008-08-19 21:32:53 +0000578
Mon P Wang0c397192008-10-30 08:01:45 +0000579 /// getWidenVectorType: given a vector type, returns the type to widen
580 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
Owen Andersone50ed302009-08-10 22:56:29 +0000581 /// If there is no vector type that we want to widen to, returns EVT::Other
Mon P Wang0c397192008-10-30 08:01:45 +0000582 /// When and were to widen is target dependent based on the cost of
583 /// scalarizing vs using the wider vector type.
Owen Andersone50ed302009-08-10 22:56:29 +0000584 virtual EVT getWidenVectorType(EVT VT) const;
Mon P Wang0c397192008-10-30 08:01:45 +0000585
Dan Gohmand9f3c482008-08-19 21:32:53 +0000586 /// createFastISel - This method returns a target specific FastISel object,
587 /// or null if the target does not support "fast" ISel.
Dan Gohman3df24e62008-09-03 23:12:08 +0000588 virtual FastISel *
589 createFastISel(MachineFunction &mf,
Devang Patel83489bb2009-01-13 00:35:13 +0000590 MachineModuleInfo *mmi, DwarfWriter *dw,
Dan Gohman3df24e62008-09-03 23:12:08 +0000591 DenseMap<const Value *, unsigned> &,
Dan Gohman0586d912008-09-10 20:11:02 +0000592 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
Dan Gohmandd5b58a2008-10-14 23:54:11 +0000593 DenseMap<const AllocaInst *, int> &
594#ifndef NDEBUG
595 , SmallSet<Instruction*, 8> &
596#endif
597 );
Bill Wendling20c568f2009-06-30 22:38:32 +0000598
Bill Wendlingb4202b82009-07-01 18:50:55 +0000599 /// getFunctionAlignment - Return the Log2 alignment of this function.
Bill Wendling20c568f2009-06-30 22:38:32 +0000600 virtual unsigned getFunctionAlignment(const Function *F) const;
601
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000602 private:
Evan Cheng0db9fe62006-04-25 20:13:52 +0000603 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
604 /// make the right decision when generating code for different targets.
605 const X86Subtarget *Subtarget;
Dan Gohmanc9f5f3f2008-05-14 01:58:56 +0000606 const X86RegisterInfo *RegInfo;
Anton Korobeynikovbff66b02008-09-09 18:22:57 +0000607 const TargetData *TD;
Evan Cheng0db9fe62006-04-25 20:13:52 +0000608
Evan Cheng25ab6902006-09-08 06:48:29 +0000609 /// X86StackPtr - X86 physical register used as stack ptr.
610 unsigned X86StackPtr;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000611
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000612 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
613 /// floating point ops.
614 /// When SSE is available, use it for f32 operations.
615 /// When SSE2 is available, use it for f64 operations.
616 bool X86ScalarSSEf32;
617 bool X86ScalarSSEf64;
Evan Cheng0d9e9762008-01-29 19:34:22 +0000618
Evan Chengeb2f9692009-10-27 19:56:55 +0000619 /// LegalFPImmediates - A list of legal fp immediates.
620 std::vector<APFloat> LegalFPImmediates;
621
622 /// addLegalFPImmediate - Indicate that this x86 target can instruction
623 /// select the specified FP immediate natively.
624 void addLegalFPImmediate(const APFloat& Imm) {
625 LegalFPImmediates.push_back(Imm);
626 }
627
Dan Gohman98ca4f22009-08-05 01:29:28 +0000628 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000629 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000630 const SmallVectorImpl<ISD::InputArg> &Ins,
631 DebugLoc dl, SelectionDAG &DAG,
632 SmallVectorImpl<SDValue> &InVals);
633 SDValue LowerMemArgument(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000634 CallingConv::ID CallConv,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000635 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
636 DebugLoc dl, SelectionDAG &DAG,
637 const CCValAssign &VA, MachineFrameInfo *MFI,
638 unsigned i);
639 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
640 DebugLoc dl, SelectionDAG &DAG,
641 const CCValAssign &VA,
642 ISD::ArgFlagsTy Flags);
Rafael Espindola1b5dcc32007-08-31 15:06:30 +0000643
Gordon Henriksen86737662008-01-05 16:56:59 +0000644 // Call lowering helpers.
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000645 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv);
Dan Gohman475871a2008-07-27 21:46:04 +0000646 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
647 SDValue Chain, bool IsTailCall, bool Is64Bit,
Dale Johannesenace16102009-02-03 19:33:06 +0000648 int FPDiff, DebugLoc dl);
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +0000649
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000650 CCAssignFn *CCAssignFnForNode(CallingConv::ID CallConv) const;
651 NameDecorationStyle NameDecorationForCallConv(CallingConv::ID CallConv);
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000652 unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG);
Evan Cheng559806f2006-01-27 08:10:46 +0000653
Eli Friedman948e95a2009-05-23 09:59:16 +0000654 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
655 bool isSigned);
Evan Chengc3630942009-12-09 21:00:30 +0000656
657 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
658 SelectionDAG &DAG);
Dan Gohman475871a2008-07-27 21:46:04 +0000659 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG);
Mon P Wangeb38ebf2010-01-24 00:05:03 +0000660 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG);
Dan Gohman475871a2008-07-27 21:46:04 +0000661 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG);
662 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG);
663 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
664 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG);
665 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
666 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
667 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
Dan Gohmanf705adb2009-10-30 01:28:02 +0000668 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG);
Dale Johannesen33c960f2009-02-04 20:06:27 +0000669 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
670 int64_t Offset, SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000671 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
672 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
673 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG);
674 SDValue LowerShift(SDValue Op, SelectionDAG &DAG);
Owen Andersone50ed302009-08-10 22:56:29 +0000675 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
Eli Friedman948e95a2009-05-23 09:59:16 +0000676 SelectionDAG &DAG);
Dan Gohman475871a2008-07-27 21:46:04 +0000677 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
Dale Johannesen1c15bf52008-10-21 20:50:01 +0000678 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG);
Bill Wendling8b8a6362009-01-17 03:56:04 +0000679 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG);
680 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG);
Dan Gohman475871a2008-07-27 21:46:04 +0000681 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG);
Eli Friedman948e95a2009-05-23 09:59:16 +0000682 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG);
Dan Gohman475871a2008-07-27 21:46:04 +0000683 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG);
684 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG);
685 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG);
686 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
687 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG);
688 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG);
689 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG);
690 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG);
691 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
Dan Gohman475871a2008-07-27 21:46:04 +0000692 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
Dan Gohman475871a2008-07-27 21:46:04 +0000693 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG);
694 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG);
695 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG);
696 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
697 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
698 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
699 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG);
700 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG);
701 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG);
702 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
703 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG);
704 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG);
Mon P Wangaf9b9522008-12-18 21:42:19 +0000705 SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG);
Bill Wendling74c37652008-12-09 22:08:41 +0000706 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG);
Bill Wendling41ea7e72008-11-24 19:21:46 +0000707
Dan Gohman475871a2008-07-27 21:46:04 +0000708 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG);
Dale Johannesen71d1bf52008-09-29 22:25:26 +0000709 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG);
Duncan Sands1607f052008-12-01 11:39:25 +0000710 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG);
711
Dan Gohman98ca4f22009-08-05 01:29:28 +0000712 virtual SDValue
713 LowerFormalArguments(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000714 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000715 const SmallVectorImpl<ISD::InputArg> &Ins,
716 DebugLoc dl, SelectionDAG &DAG,
717 SmallVectorImpl<SDValue> &InVals);
718 virtual SDValue
719 LowerCall(SDValue Chain, SDValue Callee,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000720 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000721 const SmallVectorImpl<ISD::OutputArg> &Outs,
722 const SmallVectorImpl<ISD::InputArg> &Ins,
723 DebugLoc dl, SelectionDAG &DAG,
724 SmallVectorImpl<SDValue> &InVals);
725
726 virtual SDValue
727 LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000728 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000729 const SmallVectorImpl<ISD::OutputArg> &Outs,
730 DebugLoc dl, SelectionDAG &DAG);
731
Kenneth Uildriksb4997ae2009-11-07 02:11:54 +0000732 virtual bool
733 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
734 const SmallVectorImpl<EVT> &OutTys,
735 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
736 SelectionDAG &DAG);
737
Duncan Sands1607f052008-12-01 11:39:25 +0000738 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
739 SelectionDAG &DAG, unsigned NewOp);
740
Dale Johanneseneacf2dc2009-02-03 22:26:34 +0000741 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
Bill Wendling6f287b22008-09-30 21:22:07 +0000742 SDValue Chain,
743 SDValue Dst, SDValue Src,
744 SDValue Size, unsigned Align,
Bill Wendling6158d842008-10-01 00:59:58 +0000745 const Value *DstSV, uint64_t DstSVOff);
Dale Johanneseneacf2dc2009-02-03 22:26:34 +0000746 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
Bill Wendling6f287b22008-09-30 21:22:07 +0000747 SDValue Chain,
748 SDValue Dst, SDValue Src,
749 SDValue Size, unsigned Align,
750 bool AlwaysInline,
751 const Value *DstSV, uint64_t DstSVOff,
752 const Value *SrcSV, uint64_t SrcSVOff);
Mon P Wang63307c32008-05-05 19:05:59 +0000753
Eric Christopherb120ab42009-08-18 22:50:32 +0000754 /// Utility function to emit string processing sse4.2 instructions
755 /// that return in xmm0.
Evan Cheng431f7752009-09-19 10:09:15 +0000756 /// This takes the instruction to expand, the associated machine basic
757 /// block, the number of args, and whether or not the second arg is
758 /// in memory or not.
Eric Christopherb120ab42009-08-18 22:50:32 +0000759 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
760 unsigned argNum, bool inMem) const;
761
Mon P Wang63307c32008-05-05 19:05:59 +0000762 /// Utility function to emit atomic bitwise operations (and, or, xor).
Evan Cheng431f7752009-09-19 10:09:15 +0000763 /// It takes the bitwise instruction to expand, the associated machine basic
764 /// block, and the associated X86 opcodes for reg/reg and reg/imm.
Mon P Wang63307c32008-05-05 19:05:59 +0000765 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
766 MachineInstr *BInstr,
767 MachineBasicBlock *BB,
768 unsigned regOpc,
Andrew Lenharth507a58a2008-06-14 05:48:15 +0000769 unsigned immOpc,
Dale Johannesen140be2d2008-08-19 18:47:28 +0000770 unsigned loadOpc,
771 unsigned cxchgOpc,
772 unsigned copyOpc,
773 unsigned notOpc,
774 unsigned EAXreg,
775 TargetRegisterClass *RC,
Dan Gohman1fdbc1d2009-02-07 16:15:20 +0000776 bool invSrc = false) const;
Dale Johannesen48c1bc22008-10-02 18:53:47 +0000777
778 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
779 MachineInstr *BInstr,
780 MachineBasicBlock *BB,
781 unsigned regOpcL,
782 unsigned regOpcH,
783 unsigned immOpcL,
784 unsigned immOpcH,
Dan Gohman1fdbc1d2009-02-07 16:15:20 +0000785 bool invSrc = false) const;
Mon P Wang63307c32008-05-05 19:05:59 +0000786
787 /// Utility function to emit atomic min and max. It takes the min/max
Bill Wendlingbddc4422009-03-26 01:46:56 +0000788 /// instruction to expand, the associated basic block, and the associated
789 /// cmov opcode for moving the min or max value.
Mon P Wang63307c32008-05-05 19:05:59 +0000790 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
791 MachineBasicBlock *BB,
Dan Gohman1fdbc1d2009-02-07 16:15:20 +0000792 unsigned cmovOpc) const;
Dan Gohman076aee32009-03-04 19:44:21 +0000793
Dan Gohmand6708ea2009-08-15 01:38:56 +0000794 /// Utility function to emit the xmm reg save portion of va_start.
795 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
796 MachineInstr *BInstr,
797 MachineBasicBlock *BB) const;
798
Chris Lattner52600972009-09-02 05:57:00 +0000799 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
Evan Chengce319102009-09-19 09:51:03 +0000800 MachineBasicBlock *BB,
801 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
Chris Lattner52600972009-09-02 05:57:00 +0000802
Dan Gohman076aee32009-03-04 19:44:21 +0000803 /// Emit nodes that will be selected as "test Op0,Op0", or something
Dan Gohman31125812009-03-07 01:58:32 +0000804 /// equivalent, for use with the given x86 condition code.
805 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG);
Dan Gohman076aee32009-03-04 19:44:21 +0000806
807 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
Dan Gohman31125812009-03-07 01:58:32 +0000808 /// equivalent, for use with the given x86 condition code.
809 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
810 SelectionDAG &DAG);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000811 };
Evan Chengc3f44b02008-09-03 00:03:49 +0000812
813 namespace X86 {
Dan Gohman3df24e62008-09-03 23:12:08 +0000814 FastISel *createFastISel(MachineFunction &mf,
Devang Patel83489bb2009-01-13 00:35:13 +0000815 MachineModuleInfo *mmi, DwarfWriter *dw,
Dan Gohman3df24e62008-09-03 23:12:08 +0000816 DenseMap<const Value *, unsigned> &,
Dan Gohman0586d912008-09-10 20:11:02 +0000817 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
Dan Gohmandd5b58a2008-10-14 23:54:11 +0000818 DenseMap<const AllocaInst *, int> &
819#ifndef NDEBUG
820 , SmallSet<Instruction*, 8> &
821#endif
822 );
Evan Chengc3f44b02008-09-03 00:03:49 +0000823 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000824}
825
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000826#endif // X86ISELLOWERING_H