Rishabh Bhatnagar | e9a05bb | 2018-12-10 11:09:45 -0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 2 | /* |
Amir Samuelov | f52db41 | 2019-01-08 09:30:58 +0200 | [diff] [blame] | 3 | * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include "skeleton64.dtsi" |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 7 | |
| 8 | #include <dt-bindings/clock/qcom,aop-qmp.h> |
| 9 | #include <dt-bindings/clock/qcom,camcc-kona.h> |
| 10 | #include <dt-bindings/clock/qcom,cpucc-kona.h> |
| 11 | #include <dt-bindings/clock/qcom,dispcc-kona.h> |
| 12 | #include <dt-bindings/clock/qcom,gcc-kona.h> |
| 13 | #include <dt-bindings/clock/qcom,gpucc-kona.h> |
| 14 | #include <dt-bindings/clock/qcom,npucc-kona.h> |
| 15 | #include <dt-bindings/clock/qcom,rpmh.h> |
| 16 | #include <dt-bindings/clock/qcom,videocc-kona.h> |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 17 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
David Dai | b1d6848 | 2018-10-01 19:40:35 -0700 | [diff] [blame] | 18 | #include <dt-bindings/msm/msm-bus-ids.h> |
David Collins | 61d237d | 2019-01-03 16:01:15 -0800 | [diff] [blame] | 19 | #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h> |
Raghavendra Rao Ananta | 0295796 | 2018-08-06 15:28:34 -0700 | [diff] [blame] | 20 | #include <dt-bindings/soc/qcom,ipcc.h> |
Lina Iyer | ea91c72 | 2018-06-20 14:58:05 -0600 | [diff] [blame] | 21 | #include <dt-bindings/soc/qcom,rpmh-rsc.h> |
Rishabh Bhatnagar | 2b66dc1 | 2018-10-18 10:36:27 -0700 | [diff] [blame] | 22 | #include <dt-bindings/gpio/gpio.h> |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 23 | |
Rama Aparna Mallavarapu | 5a7daf4 | 2019-01-14 22:08:20 -0800 | [diff] [blame] | 24 | #define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) |
| 25 | #define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;} |
| 26 | |
| 27 | |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 28 | / { |
| 29 | model = "Qualcomm Technologies, Inc. kona"; |
| 30 | compatible = "qcom,kona"; |
| 31 | qcom,msm-id = <356 0x10000>; |
| 32 | interrupt-parent = <&intc>; |
| 33 | |
Swathi Sridhar | 869198a | 2019-01-22 14:52:07 -0800 | [diff] [blame] | 34 | mem-offline { |
| 35 | compatible = "qcom,mem-offline"; |
| 36 | offline-sizes = <0x1 0x40000000 0x0 0x40000000>, |
| 37 | <0x1 0xc0000000 0x0 0x80000000>; |
| 38 | granule = <512>; |
| 39 | mboxes = <&qmp_aop 0>; |
| 40 | }; |
| 41 | |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 42 | aliases { |
| 43 | ufshc1 = &ufshc_mem; /* Embedded UFS slot */ |
Bao D. Nguyen | bd2335b | 2019-01-17 13:32:42 -0800 | [diff] [blame] | 44 | sdhc2 = &sdhc_2; /* SDC2 SD card slot */ |
Tony Truong | 576c9bf | 2019-01-31 17:38:11 -0800 | [diff] [blame] | 45 | pci-domain0 = &pcie0; /* PCIe0 domain */ |
| 46 | pci-domain1 = &pcie1; /* PCIe1 domain */ |
Tony Truong | c972c64 | 2018-09-12 10:03:51 -0700 | [diff] [blame] | 47 | pci-domain2 = &pcie2; /* PCIe2 domain */ |
Vipin Deep Kaur | 9a2c13d | 2018-12-19 18:38:46 +0530 | [diff] [blame] | 48 | serial0 = &qupv3_se2_2uart; /* RUMI */ |
Karthikeyan Mani | 4b26426 | 2019-02-12 19:49:50 -0800 | [diff] [blame] | 49 | swr0 = &swr0; |
| 50 | swr1 = &swr1; |
| 51 | swr2 = &swr2; |
Sujeev Dias | 4e5ff1f | 2019-01-18 19:03:14 -0800 | [diff] [blame] | 52 | mhi-netdev0 = &mhi_netdev_0; |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 53 | }; |
| 54 | |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 55 | cpus { |
| 56 | #address-cells = <2>; |
| 57 | #size-cells = <0>; |
| 58 | |
| 59 | CPU0: cpu@0 { |
| 60 | device_type = "cpu"; |
| 61 | compatible = "qcom,kryo"; |
| 62 | reg = <0x0 0x0>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 63 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 64 | cache-size = <0x8000>; |
| 65 | cpu-release-addr = <0x0 0x90000000>; |
| 66 | next-level-cache = <&L2_0>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 67 | qcom,freq-domain = <&cpufreq_hw 0 4>; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 68 | capacity-dmips-mhz = <1024>; |
Satya Durga Srinivasu Prabhala | 50812f7 | 2018-12-13 12:50:08 -0800 | [diff] [blame] | 69 | dynamic-power-coefficient = <100>; |
Ram Chandrasekar | 38f02e2 | 2019-02-25 15:59:34 -0700 | [diff] [blame] | 70 | #cooling-cells = <2>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 71 | L2_0: l2-cache { |
| 72 | compatible = "arm,arch-cache"; |
| 73 | cache-size = <0x20000>; |
| 74 | cache-level = <2>; |
| 75 | next-level-cache = <&L3_0>; |
| 76 | |
| 77 | L3_0: l3-cache { |
| 78 | compatible = "arm,arch-cache"; |
| 79 | cache-size = <0x400000>; |
| 80 | cache-level = <3>; |
| 81 | }; |
| 82 | }; |
Venkata Narendra Kumar Gutta | b0205a9 | 2018-09-11 13:40:34 -0700 | [diff] [blame] | 83 | |
| 84 | L1_I_0: l1-icache { |
| 85 | compatible = "arm,arch-cache"; |
| 86 | qcom,dump-size = <0x8800>; |
| 87 | }; |
| 88 | |
| 89 | L1_D_0: l1-dcache { |
| 90 | compatible = "arm,arch-cache"; |
| 91 | qcom,dump-size = <0x9000>; |
| 92 | }; |
| 93 | |
| 94 | L2_TLB_0: l2-tlb { |
| 95 | qcom,dump-size = <0x5000>; |
| 96 | }; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 97 | }; |
| 98 | |
| 99 | CPU1: cpu@100 { |
| 100 | device_type = "cpu"; |
| 101 | compatible = "qcom,kryo"; |
| 102 | reg = <0x0 0x100>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 103 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 104 | cache-size = <0x8000>; |
| 105 | cpu-release-addr = <0x0 0x90000000>; |
| 106 | next-level-cache = <&L2_1>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 107 | qcom,freq-domain = <&cpufreq_hw 0 4>; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 108 | capacity-dmips-mhz = <1024>; |
Satya Durga Srinivasu Prabhala | 50812f7 | 2018-12-13 12:50:08 -0800 | [diff] [blame] | 109 | dynamic-power-coefficient = <100>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 110 | L2_1: l2-cache { |
| 111 | compatible = "arm,arch-cache"; |
| 112 | cache-size = <0x20000>; |
| 113 | cache-level = <2>; |
| 114 | next-level-cache = <&L3_0>; |
| 115 | }; |
Venkata Narendra Kumar Gutta | b0205a9 | 2018-09-11 13:40:34 -0700 | [diff] [blame] | 116 | |
| 117 | L1_I_100: l1-icache { |
| 118 | compatible = "arm,arch-cache"; |
| 119 | qcom,dump-size = <0x8800>; |
| 120 | }; |
| 121 | |
| 122 | L1_D_100: l1-dcache { |
| 123 | compatible = "arm,arch-cache"; |
| 124 | qcom,dump-size = <0x9000>; |
| 125 | }; |
| 126 | |
| 127 | L2_TLB_100: l2-tlb { |
| 128 | qcom,dump-size = <0x5000>; |
| 129 | }; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 130 | }; |
| 131 | |
| 132 | CPU2: cpu@200 { |
| 133 | device_type = "cpu"; |
| 134 | compatible = "qcom,kryo"; |
| 135 | reg = <0x0 0x200>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 136 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 137 | cache-size = <0x8000>; |
| 138 | cpu-release-addr = <0x0 0x90000000>; |
| 139 | next-level-cache = <&L2_2>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 140 | qcom,freq-domain = <&cpufreq_hw 0 4>; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 141 | capacity-dmips-mhz = <1024>; |
Satya Durga Srinivasu Prabhala | 50812f7 | 2018-12-13 12:50:08 -0800 | [diff] [blame] | 142 | dynamic-power-coefficient = <100>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 143 | L2_2: l2-cache { |
| 144 | compatible = "arm,arch-cache"; |
| 145 | cache-size = <0x20000>; |
| 146 | cache-level = <2>; |
| 147 | next-level-cache = <&L3_0>; |
| 148 | }; |
Venkata Narendra Kumar Gutta | b0205a9 | 2018-09-11 13:40:34 -0700 | [diff] [blame] | 149 | |
| 150 | L1_I_200: l1-icache { |
| 151 | compatible = "arm,arch-cache"; |
| 152 | qcom,dump-size = <0x8800>; |
| 153 | }; |
| 154 | |
| 155 | L1_D_200: l1-dcache { |
| 156 | compatible = "arm,arch-cache"; |
| 157 | qcom,dump-size = <0x9000>; |
| 158 | }; |
| 159 | |
| 160 | L2_TLB_200: l2-tlb { |
| 161 | qcom,dump-size = <0x5000>; |
| 162 | }; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 163 | }; |
| 164 | |
| 165 | CPU3: cpu@300 { |
| 166 | device_type = "cpu"; |
| 167 | compatible = "qcom,kryo"; |
| 168 | reg = <0x0 0x300>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 169 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 170 | cache-size = <0x8000>; |
| 171 | cpu-release-addr = <0x0 0x90000000>; |
| 172 | next-level-cache = <&L2_3>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 173 | qcom,freq-domain = <&cpufreq_hw 0 4>; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 174 | capacity-dmips-mhz = <1024>; |
Satya Durga Srinivasu Prabhala | 50812f7 | 2018-12-13 12:50:08 -0800 | [diff] [blame] | 175 | dynamic-power-coefficient = <100>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 176 | L2_3: l2-cache { |
| 177 | compatible = "arm,arch-cache"; |
| 178 | cache-size = <0x20000>; |
| 179 | cache-level = <2>; |
| 180 | next-level-cache = <&L3_0>; |
| 181 | }; |
Venkata Narendra Kumar Gutta | b0205a9 | 2018-09-11 13:40:34 -0700 | [diff] [blame] | 182 | |
| 183 | L1_I_300: l1-icache { |
| 184 | compatible = "arm,arch-cache"; |
| 185 | qcom,dump-size = <0x8800>; |
| 186 | }; |
| 187 | |
| 188 | L1_D_300: l1-dcache { |
| 189 | compatible = "arm,arch-cache"; |
| 190 | qcom,dump-size = <0x9000>; |
| 191 | }; |
| 192 | |
| 193 | L2_TLB_300: l2-tlb { |
| 194 | qcom,dump-size = <0x5000>; |
| 195 | }; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 196 | }; |
| 197 | |
| 198 | CPU4: cpu@400 { |
| 199 | device_type = "cpu"; |
| 200 | compatible = "qcom,kryo"; |
| 201 | reg = <0x0 0x400>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 202 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 203 | cache-size = <0x10000>; |
| 204 | cpu-release-addr = <0x0 0x90000000>; |
| 205 | next-level-cache = <&L2_4>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 206 | qcom,freq-domain = <&cpufreq_hw 1 4>; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 207 | capacity-dmips-mhz = <1894>; |
Satya Durga Srinivasu Prabhala | db98c3e | 2019-01-25 10:26:46 -0800 | [diff] [blame] | 208 | dynamic-power-coefficient = <514>; |
Ram Chandrasekar | 38f02e2 | 2019-02-25 15:59:34 -0700 | [diff] [blame] | 209 | #cooling-cells = <2>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 210 | L2_4: l2-cache { |
| 211 | compatible = "arm,arch-cache"; |
Venkata Narendra Kumar Gutta | b0205a9 | 2018-09-11 13:40:34 -0700 | [diff] [blame] | 212 | cache-size = <0x40000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 213 | cache-level = <2>; |
| 214 | next-level-cache = <&L3_0>; |
Venkata Narendra Kumar Gutta | b0205a9 | 2018-09-11 13:40:34 -0700 | [diff] [blame] | 215 | qcom,dump-size = <0x48000>; |
| 216 | }; |
| 217 | |
| 218 | L1_I_400: l1-icache { |
| 219 | compatible = "arm,arch-cache"; |
| 220 | qcom,dump-size = <0x11000>; |
| 221 | }; |
| 222 | |
| 223 | L1_D_400: l1-dcache { |
| 224 | compatible = "arm,arch-cache"; |
| 225 | qcom,dump-size = <0x12000>; |
| 226 | }; |
| 227 | |
| 228 | L1_ITLB_400: l1-itlb { |
| 229 | qcom,dump-size = <0x300>; |
| 230 | }; |
| 231 | |
| 232 | L1_DTLB_400: l1-dtlb { |
| 233 | qcom,dump-size = <0x480>; |
| 234 | }; |
| 235 | |
| 236 | L2_TLB_400: l2-tlb { |
| 237 | qcom,dump-size = <0x7800>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 238 | }; |
| 239 | }; |
| 240 | |
| 241 | CPU5: cpu@500 { |
| 242 | device_type = "cpu"; |
| 243 | compatible = "qcom,kryo"; |
| 244 | reg = <0x0 0x500>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 245 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 246 | cache-size = <0x10000>; |
| 247 | cpu-release-addr = <0x0 0x90000000>; |
| 248 | next-level-cache = <&L2_5>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 249 | qcom,freq-domain = <&cpufreq_hw 1 4>; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 250 | capacity-dmips-mhz = <1894>; |
Satya Durga Srinivasu Prabhala | db98c3e | 2019-01-25 10:26:46 -0800 | [diff] [blame] | 251 | dynamic-power-coefficient = <514>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 252 | L2_5: l2-cache { |
| 253 | compatible = "arm,arch-cache"; |
Venkata Narendra Kumar Gutta | b0205a9 | 2018-09-11 13:40:34 -0700 | [diff] [blame] | 254 | cache-size = <0x40000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 255 | cache-level = <2>; |
| 256 | next-level-cache = <&L3_0>; |
Venkata Narendra Kumar Gutta | b0205a9 | 2018-09-11 13:40:34 -0700 | [diff] [blame] | 257 | qcom,dump-size = <0x48000>; |
| 258 | }; |
| 259 | |
| 260 | L1_I_500: l1-icache { |
| 261 | compatible = "arm,arch-cache"; |
| 262 | qcom,dump-size = <0x11000>; |
| 263 | }; |
| 264 | |
| 265 | L1_D_500: l1-dcache { |
| 266 | compatible = "arm,arch-cache"; |
| 267 | qcom,dump-size = <0x12000>; |
| 268 | }; |
| 269 | |
| 270 | L1_ITLB_500: l1-itlb { |
| 271 | qcom,dump-size = <0x300>; |
| 272 | }; |
| 273 | |
| 274 | L1_DTLB_500: l1-dtlb { |
| 275 | qcom,dump-size = <0x480>; |
| 276 | }; |
| 277 | |
| 278 | L2_TLB_500: l2-tlb { |
| 279 | qcom,dump-size = <0x7800>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 280 | }; |
| 281 | }; |
| 282 | |
| 283 | CPU6: cpu@600 { |
| 284 | device_type = "cpu"; |
| 285 | compatible = "qcom,kryo"; |
| 286 | reg = <0x0 0x600>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 287 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 288 | cache-size = <0x10000>; |
| 289 | cpu-release-addr = <0x0 0x90000000>; |
| 290 | next-level-cache = <&L2_6>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 291 | qcom,freq-domain = <&cpufreq_hw 1 4>; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 292 | capacity-dmips-mhz = <1894>; |
Satya Durga Srinivasu Prabhala | db98c3e | 2019-01-25 10:26:46 -0800 | [diff] [blame] | 293 | dynamic-power-coefficient = <514>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 294 | L2_6: l2-cache { |
| 295 | compatible = "arm,arch-cache"; |
Venkata Narendra Kumar Gutta | b0205a9 | 2018-09-11 13:40:34 -0700 | [diff] [blame] | 296 | cache-size = <0x40000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 297 | cache-level = <2>; |
| 298 | next-level-cache = <&L3_0>; |
Venkata Narendra Kumar Gutta | b0205a9 | 2018-09-11 13:40:34 -0700 | [diff] [blame] | 299 | qcom,dump-size = <0x48000>; |
| 300 | }; |
| 301 | |
| 302 | L1_I_600: l1-icache { |
| 303 | compatible = "arm,arch-cache"; |
| 304 | qcom,dump-size = <0x11000>; |
| 305 | }; |
| 306 | |
| 307 | L1_D_600: l1-dcache { |
| 308 | compatible = "arm,arch-cache"; |
| 309 | qcom,dump-size = <0x12000>; |
| 310 | }; |
| 311 | |
| 312 | L1_ITLB_600: l1-itlb { |
| 313 | qcom,dump-size = <0x300>; |
| 314 | }; |
| 315 | |
| 316 | L1_DTLB_600: l1-dtlb { |
| 317 | qcom,dump-size = <0x480>; |
| 318 | }; |
| 319 | |
| 320 | L2_TLB_600: l2-tlb { |
| 321 | qcom,dump-size = <0x7800>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 322 | }; |
| 323 | }; |
| 324 | |
| 325 | CPU7: cpu@700 { |
| 326 | device_type = "cpu"; |
| 327 | compatible = "qcom,kryo"; |
| 328 | reg = <0x0 0x700>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 329 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 330 | cache-size = <0x10000>; |
| 331 | cpu-release-addr = <0x0 0x90000000>; |
| 332 | next-level-cache = <&L2_7>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 333 | qcom,freq-domain = <&cpufreq_hw 2 4>; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 334 | capacity-dmips-mhz = <1894>; |
Satya Durga Srinivasu Prabhala | db98c3e | 2019-01-25 10:26:46 -0800 | [diff] [blame] | 335 | dynamic-power-coefficient = <598>; |
Ram Chandrasekar | 38f02e2 | 2019-02-25 15:59:34 -0700 | [diff] [blame] | 336 | #cooling-cells = <2>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 337 | L2_7: l2-cache { |
| 338 | compatible = "arm,arch-cache"; |
| 339 | cache-size = <0x80000>; |
| 340 | cache-level = <2>; |
| 341 | next-level-cache = <&L3_0>; |
Venkata Narendra Kumar Gutta | b0205a9 | 2018-09-11 13:40:34 -0700 | [diff] [blame] | 342 | qcom,dump-size = <0x90000>; |
| 343 | }; |
| 344 | |
| 345 | L1_I_700: l1-icache { |
| 346 | compatible = "arm,arch-cache"; |
| 347 | qcom,dump-size = <0x11000>; |
| 348 | }; |
| 349 | |
| 350 | L1_D_700: l1-dcache { |
| 351 | compatible = "arm,arch-cache"; |
| 352 | qcom,dump-size = <0x12000>; |
| 353 | }; |
| 354 | |
| 355 | L1_ITLB_700: l1-itlb { |
| 356 | qcom,dump-size = <0x300>; |
| 357 | }; |
| 358 | |
| 359 | L1_DTLB_700: l1-dtlb { |
| 360 | qcom,dump-size = <0x480>; |
| 361 | }; |
| 362 | |
| 363 | L2_TLB_700: l2-tlb { |
| 364 | qcom,dump-size = <0x7800>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 365 | }; |
| 366 | }; |
| 367 | |
| 368 | cpu-map { |
| 369 | cluster0 { |
| 370 | core0 { |
| 371 | cpu = <&CPU0>; |
| 372 | }; |
| 373 | |
| 374 | core1 { |
| 375 | cpu = <&CPU1>; |
| 376 | }; |
| 377 | |
| 378 | core2 { |
| 379 | cpu = <&CPU2>; |
| 380 | }; |
| 381 | |
| 382 | core3 { |
| 383 | cpu = <&CPU3>; |
| 384 | }; |
| 385 | }; |
| 386 | |
| 387 | cluster1 { |
| 388 | core0 { |
| 389 | cpu = <&CPU4>; |
| 390 | }; |
| 391 | |
| 392 | core1 { |
| 393 | cpu = <&CPU5>; |
| 394 | }; |
| 395 | |
| 396 | core2 { |
| 397 | cpu = <&CPU6>; |
| 398 | }; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 399 | }; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 400 | |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 401 | cluster2 { |
| 402 | core0 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 403 | cpu = <&CPU7>; |
| 404 | }; |
| 405 | }; |
| 406 | }; |
| 407 | }; |
| 408 | |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 409 | |
Channagoud Kadabi | cdd72a0 | 2018-09-21 14:46:21 -0700 | [diff] [blame] | 410 | cpu_pmu: cpu-pmu { |
| 411 | compatible = "arm,armv8-pmuv3"; |
| 412 | qcom,irq-is-percpu; |
| 413 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 414 | }; |
| 415 | |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 416 | soc: soc { |
| 417 | cpufreq_hw: qcom,cpufreq-hw { |
| 418 | compatible = "qcom,cpufreq-hw"; |
| 419 | reg = <0x18591000 0x1000>, <0x18592000 0x1000>, |
| 420 | <0x18593000 0x1000>; |
| 421 | reg-names = "freq-domain0", "freq-domain1", |
| 422 | "freq-domain2"; |
| 423 | |
David Dai | ee6a9d6 | 2019-01-10 17:14:04 -0800 | [diff] [blame] | 424 | clocks = <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GPLL0>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 425 | clock-names = "xo", "cpu_clk"; |
| 426 | |
| 427 | #freq-domain-cells = <2>; |
| 428 | }; |
| 429 | }; |
| 430 | |
Arjun Bagla | 76f02ef | 2018-09-19 10:00:29 -0700 | [diff] [blame] | 431 | psci { |
| 432 | compatible = "arm,psci-1.0"; |
| 433 | method = "smc"; |
| 434 | }; |
| 435 | |
Venkata Narendra Kumar Gutta | 07fdd26 | 2019-02-11 21:12:04 -0800 | [diff] [blame] | 436 | chosen { |
| 437 | bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; |
| 438 | }; |
| 439 | |
Bruce Levy | 3bd8d1b | 2018-09-11 11:31:13 -0700 | [diff] [blame] | 440 | firmware: firmware { |
| 441 | android { |
| 442 | compatible = "android,firmware"; |
Zhen Kong | b8fe407 | 2019-01-15 17:58:27 -0800 | [diff] [blame] | 443 | vbmeta { |
| 444 | compatible = "android,vbmeta"; |
| 445 | parts = "vbmeta,boot,system,vendor,dtbo"; |
| 446 | }; |
| 447 | |
Bruce Levy | 3bd8d1b | 2018-09-11 11:31:13 -0700 | [diff] [blame] | 448 | fstab { |
| 449 | compatible = "android,fstab"; |
| 450 | vendor { |
| 451 | compatible = "android,vendor"; |
| 452 | dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; |
| 453 | type = "ext4"; |
| 454 | mnt_flags = "ro,barrier=1,discard"; |
| 455 | fsmgr_flags = "wait,slotselect,avb"; |
| 456 | status = "ok"; |
| 457 | }; |
| 458 | }; |
| 459 | }; |
| 460 | }; |
| 461 | |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 462 | psci { |
| 463 | compatible = "arm,psci-1.0"; |
| 464 | method = "smc"; |
| 465 | }; |
| 466 | |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 467 | reserved-memory { |
| 468 | #address-cells = <2>; |
| 469 | #size-cells = <2>; |
| 470 | ranges; |
| 471 | |
| 472 | hyp_mem: hyp_region@80000000 { |
| 473 | no-map; |
| 474 | reg = <0x0 0x80000000 0x0 0x600000>; |
| 475 | }; |
| 476 | |
| 477 | xbl_aop_mem: xbl_aop_region@80700000 { |
| 478 | no-map; |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 479 | reg = <0x0 0x80700000 0x0 0x160000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 480 | }; |
| 481 | |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 482 | cmd_db: reserved-memory@80860000 { |
| 483 | reg = <0x0 0x80860000 0x0 0x20000>; |
Lina Iyer | 5d609fa | 2018-10-03 14:26:55 -0600 | [diff] [blame] | 484 | compatible = "qcom,cmd-db"; |
| 485 | no-map; |
| 486 | }; |
| 487 | |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 488 | smem_mem: smem_region@80900000 { |
| 489 | no-map; |
| 490 | reg = <0x0 0x80900000 0x0 0x200000>; |
| 491 | }; |
| 492 | |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 493 | lpass_pcie_mem: lpass_pcie_region@80b00000 { |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 494 | no-map; |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 495 | reg = <0x0 0x80b00000 0x0 0x100000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 496 | }; |
| 497 | |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 498 | ssc_pcie_mem: ssc_pcie_region@80c00000 { |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 499 | no-map; |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 500 | reg = <0x0 0x80c00000 0x0 0x100000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 501 | }; |
| 502 | |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 503 | removed_mem: removed_region@80d00000 { |
| 504 | no-map; |
| 505 | reg = <0x0 0x80d00000 0x0 0x1300000>; |
| 506 | }; |
| 507 | |
| 508 | qtee_apps_mem: qtee_apps_region@82000000 { |
| 509 | no-map; |
| 510 | reg = <0x0 0x82000000 0x0 0x2600000>; |
| 511 | }; |
| 512 | |
| 513 | pil_camera_mem: pil_camera_region@86200000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 514 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 515 | no-map; |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 516 | reg = <0x0 0x86200000 0x0 0x500000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 517 | }; |
| 518 | |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 519 | pil_wlan_fw_mem: pil_wlan_fw_region@86700000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 520 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 521 | no-map; |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 522 | reg = <0x0 0x86700000 0x0 0x100000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 523 | }; |
| 524 | |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 525 | pil_ipa_fw_mem: pil_ipa_fw_region@86800000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 526 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 527 | no-map; |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 528 | reg = <0x0 0x86800000 0x0 0x10000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 529 | }; |
| 530 | |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 531 | pil_ipa_gsi_mem: pil_ipa_gsi_region@86810000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 532 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 533 | no-map; |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 534 | reg = <0x0 0x86810000 0x0 0xa000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 535 | }; |
| 536 | |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 537 | pil_gpu_mem: pil_gpu_region@8681a000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 538 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 539 | no-map; |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 540 | reg = <0x0 0x8681a000 0x0 0x2000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 541 | }; |
| 542 | |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 543 | pil_npu_mem: pil_npu_region@86900000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 544 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 545 | no-map; |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 546 | reg = <0x0 0x86900000 0x0 0x500000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 547 | }; |
| 548 | |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 549 | pil_video_mem: pil_video_region@86e00000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 550 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 551 | no-map; |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 552 | reg = <0x0 0x86e00000 0x0 0x500000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 553 | }; |
| 554 | |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 555 | pil_cvp_mem: pil_cvp_region@87300000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 556 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 557 | no-map; |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 558 | reg = <0x0 0x87300000 0x0 0x500000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 559 | }; |
| 560 | |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 561 | pil_cdsp_mem: pil_cdsp_region@87800000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 562 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 563 | no-map; |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 564 | reg = <0x0 0x87800000 0x0 0x800000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 565 | }; |
| 566 | |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 567 | pil_slpi_mem: pil_slpi_region@88000000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 568 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 569 | no-map; |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 570 | reg = <0x0 0x88000000 0x0 0x1500000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 571 | }; |
| 572 | |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 573 | pil_adsp_mem: pil_adsp_region@89500000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 574 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 575 | no-map; |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 576 | reg = <0x0 0x89500000 0x0 0x1c00000>; |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 577 | }; |
| 578 | |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 579 | pil_spss_mem: pil_spss_region@8b100000 { |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 580 | compatible = "removed-dma-pool"; |
| 581 | no-map; |
Swathi Sridhar | e084268 | 2019-02-07 17:42:01 -0800 | [diff] [blame] | 582 | reg = <0x0 0x8b100000 0x0 0x100000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 583 | }; |
| 584 | |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 585 | adsp_mem: adsp_region { |
| 586 | compatible = "shared-dma-pool"; |
| 587 | alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| 588 | reusable; |
| 589 | alignment = <0x0 0x400000>; |
Tharun Kumar Merugu | 9bf49d7 | 2018-12-21 02:33:10 +0530 | [diff] [blame] | 590 | size = <0x0 0xC00000>; |
| 591 | }; |
| 592 | |
| 593 | sdsp_mem: sdsp_region { |
| 594 | compatible = "shared-dma-pool"; |
| 595 | alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| 596 | reusable; |
| 597 | alignment = <0x0 0x400000>; |
| 598 | size = <0x0 0x800000>; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 599 | }; |
| 600 | |
George Shen | 9c54c66 | 2018-12-26 15:50:11 -0800 | [diff] [blame] | 601 | cdsp_mem: cdsp_region { |
| 602 | compatible = "shared-dma-pool"; |
| 603 | alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| 604 | reusable; |
| 605 | alignment = <0x0 0x400000>; |
| 606 | size = <0x0 0x400000>; |
| 607 | }; |
| 608 | |
Veera Sundaram Sankaran | bc490f6 | 2019-02-15 13:25:23 -0800 | [diff] [blame] | 609 | cont_splash_memory: cont_splash_region@9c000000 { |
| 610 | reg = <0x0 0x9c000000 0x0 0x02400000>; |
| 611 | label = "cont_splash_region"; |
| 612 | }; |
| 613 | |
Veera Sundaram Sankaran | 9503882 | 2019-02-22 10:26:13 -0800 | [diff] [blame] | 614 | disp_rdump_memory: disp_rdump_region@9c000000 { |
| 615 | reg = <0x0 0x9c000000 0x0 0x00800000>; |
| 616 | label = "disp_rdump_region"; |
| 617 | }; |
| 618 | |
Tingwei Zhang | d9b535f | 2018-12-03 19:14:06 -0800 | [diff] [blame] | 619 | dump_mem: mem_dump_region { |
| 620 | compatible = "shared-dma-pool"; |
Swathi Sridhar | 08b670b | 2019-01-16 17:05:24 -0800 | [diff] [blame] | 621 | alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
Tingwei Zhang | d9b535f | 2018-12-03 19:14:06 -0800 | [diff] [blame] | 622 | reusable; |
| 623 | size = <0 0x2400000>; |
| 624 | }; |
Konstantin Dorfman | 13fe543 | 2019-02-06 16:03:13 +0200 | [diff] [blame] | 625 | sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ |
| 626 | compatible = "shared-dma-pool"; |
| 627 | alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| 628 | reusable; |
| 629 | alignment = <0x0 0x400000>; |
Konstantin Dorfman | a22248e | 2019-03-19 15:44:58 +0200 | [diff] [blame] | 630 | size = <0x0 0xc00000>; |
Konstantin Dorfman | 13fe543 | 2019-02-06 16:03:13 +0200 | [diff] [blame] | 631 | }; |
Tingwei Zhang | d9b535f | 2018-12-03 19:14:06 -0800 | [diff] [blame] | 632 | |
Zhen Kong | 284c9f0 | 2018-11-06 12:00:30 -0800 | [diff] [blame] | 633 | qseecom_mem: qseecom_region { |
| 634 | compatible = "shared-dma-pool"; |
| 635 | alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| 636 | reusable; |
| 637 | alignment = <0x0 0x400000>; |
| 638 | size = <0x0 0x1400000>; |
| 639 | }; |
| 640 | |
| 641 | qseecom_ta_mem: qseecom_ta_region { |
| 642 | compatible = "shared-dma-pool"; |
| 643 | alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| 644 | reusable; |
| 645 | alignment = <0x0 0x400000>; |
| 646 | size = <0x0 0x1000000>; |
| 647 | }; |
| 648 | |
Akshay Chandrashekhar Kalghatgi | ae0539a | 2019-02-27 19:08:55 -0800 | [diff] [blame] | 649 | secure_display_memory: secure_display_region { /* Secure UI */ |
| 650 | compatible = "shared-dma-pool"; |
| 651 | alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| 652 | reusable; |
| 653 | alignment = <0x0 0x400000>; |
| 654 | size = <0x0 0xA000000>; |
| 655 | }; |
| 656 | |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 657 | /* global autoconfigured region for contiguous allocations */ |
| 658 | linux,cma { |
| 659 | compatible = "shared-dma-pool"; |
| 660 | alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| 661 | reusable; |
| 662 | alignment = <0x0 0x400000>; |
| 663 | size = <0x0 0x2000000>; |
| 664 | linux,cma-default; |
| 665 | }; |
Vikram Panduranga | 5bbf75a | 2019-01-17 19:26:52 -0800 | [diff] [blame] | 666 | |
| 667 | mailbox_mem: mailbox_region { |
| 668 | compatible = "shared-dma-pool"; |
| 669 | no-map; |
| 670 | alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| 671 | alignment = <0x0 0x400000>; |
| 672 | size = <0x0 0x20000>; |
| 673 | }; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 674 | }; |
Bruce Levy | c5eb199 | 2019-01-11 12:09:18 -0800 | [diff] [blame] | 675 | |
| 676 | vendor: vendor { |
| 677 | #address-cells = <1>; |
| 678 | #size-cells = <1>; |
| 679 | ranges = <0 0 0 0xffffffff>; |
| 680 | compatible = "simple-bus"; |
| 681 | }; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 682 | }; |
| 683 | |
| 684 | &soc { |
| 685 | #address-cells = <1>; |
| 686 | #size-cells = <1>; |
| 687 | ranges = <0 0 0 0xffffffff>; |
| 688 | compatible = "simple-bus"; |
| 689 | |
David Collins | 692dff7 | 2018-11-12 17:09:49 -0800 | [diff] [blame] | 690 | thermal_zones: thermal-zones { |
| 691 | }; |
| 692 | |
Dilip Kota | ab8bf96 | 2018-12-26 12:12:22 +0530 | [diff] [blame] | 693 | slim_aud: slim@3ac0000 { |
| 694 | cell-index = <1>; |
| 695 | compatible = "qcom,slim-ngd"; |
| 696 | reg = <0x3ac0000 0x2c000>, |
| 697 | <0x3a84000 0x2c000>; |
| 698 | reg-names = "slimbus_physical", "slimbus_bam_physical"; |
Rishabh Bhatnagar | 7ef1588 | 2019-01-22 11:02:09 -0800 | [diff] [blame] | 699 | interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, |
| 700 | <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; |
Dilip Kota | ab8bf96 | 2018-12-26 12:12:22 +0530 | [diff] [blame] | 701 | interrupt-names = "slimbus_irq", "slimbus_bam_irq"; |
| 702 | qcom,apps-ch-pipes = <0x700000>; |
| 703 | qcom,ea-pc = <0x2d0>; |
Dilip Kota | 8b36d60 | 2019-02-06 12:07:34 +0530 | [diff] [blame] | 704 | iommus = <&apps_smmu 0x1826 0x0>, |
| 705 | <&apps_smmu 0x182f 0x0>, |
| 706 | <&apps_smmu 0x1830 0x1>; |
| 707 | qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; |
| 708 | qcom,iommu-dma = "bypass"; |
Mahesh Kumar Sharma | b8e6266 | 2019-01-17 16:16:22 -0800 | [diff] [blame] | 709 | status = "ok"; |
Mahesh Kumar Sharma | b8e6266 | 2019-01-17 16:16:22 -0800 | [diff] [blame] | 710 | |
| 711 | /* Slimbus Slave DT for QCA6390 */ |
| 712 | btfmslim_codec: qca6390 { |
| 713 | compatible = "qcom,btfmslim_slave"; |
| 714 | elemental-addr = [00 01 20 02 17 02]; |
| 715 | qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; |
| 716 | qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; |
| 717 | }; |
Dilip Kota | ab8bf96 | 2018-12-26 12:12:22 +0530 | [diff] [blame] | 718 | }; |
| 719 | |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 720 | intc: interrupt-controller@17a00000 { |
| 721 | compatible = "arm,gic-v3"; |
| 722 | #interrupt-cells = <3>; |
| 723 | interrupt-controller; |
| 724 | #redistributor-regions = <1>; |
| 725 | redistributor-stride = <0x0 0x20000>; |
| 726 | reg = <0x17a00000 0x10000>, /* GICD */ |
| 727 | <0x17a60000 0x100000>; /* GICR * 8 */ |
| 728 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 729 | }; |
| 730 | |
Rishabh Bhatnagar | fd73eb1 | 2018-09-04 15:00:46 -0700 | [diff] [blame] | 731 | qcom,chd_silver { |
| 732 | compatible = "qcom,core-hang-detect"; |
| 733 | label = "silver"; |
| 734 | qcom,threshold-arr = <0x18000058 0x18010058 |
| 735 | 0x18020058 0x18030058>; |
| 736 | qcom,config-arr = <0x18000060 0x18010060 |
| 737 | 0x18020060 0x18030060>; |
| 738 | }; |
| 739 | |
| 740 | qcom,chd_gold { |
| 741 | compatible = "qcom,core-hang-detect"; |
| 742 | label = "gold"; |
| 743 | qcom,threshold-arr = <0x18040058 0x18050058 |
| 744 | 0x18060058 0x18070058>; |
| 745 | qcom,config-arr = <0x18040060 0x18050060 |
| 746 | 0x18060060 0x18070060>; |
| 747 | }; |
| 748 | |
Rishabh Bhatnagar | 8f0dd4b | 2018-08-07 11:07:40 -0700 | [diff] [blame] | 749 | cache-controller@9200000 { |
Rishabh Bhatnagar | 83765df | 2019-02-19 15:01:49 -0800 | [diff] [blame] | 750 | compatible = "qcom,llcc-v2"; |
Rishabh Bhatnagar | 8f0dd4b | 2018-08-07 11:07:40 -0700 | [diff] [blame] | 751 | reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>; |
| 752 | reg-names = "llcc_base", "llcc_broadcast_base"; |
Rishabh Bhatnagar | 2e49cd3a | 2019-01-16 12:03:36 -0800 | [diff] [blame] | 753 | cap-based-alloc-and-pwr-collapse; |
Rishabh Bhatnagar | 8f0dd4b | 2018-08-07 11:07:40 -0700 | [diff] [blame] | 754 | }; |
| 755 | |
Rishabh Bhatnagar | c6970a0 | 2018-09-04 16:43:43 -0700 | [diff] [blame] | 756 | wdog: qcom,wdt@17c10000 { |
| 757 | compatible = "qcom,msm-watchdog"; |
| 758 | reg = <0x17c10000 0x1000>; |
| 759 | reg-names = "wdt-base"; |
| 760 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
| 761 | <0 1 IRQ_TYPE_LEVEL_HIGH>; |
| 762 | qcom,bark-time = <11000>; |
| 763 | qcom,pet-time = <9360>; |
| 764 | qcom,wakeup-enable; |
Rishabh Bhatnagar | 1265dc5 | 2019-02-08 13:40:59 -0800 | [diff] [blame] | 765 | qcom,ipi-ping; |
Rishabh Bhatnagar | c6970a0 | 2018-09-04 16:43:43 -0700 | [diff] [blame] | 766 | qcom,scandump-sizes = <0x10100 0x10100 0x10100 0x10100 |
| 767 | 0x18100 0x18100 0x18100 0x18100>; |
Rishabh Bhatnagar | c6970a0 | 2018-09-04 16:43:43 -0700 | [diff] [blame] | 768 | }; |
| 769 | |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 770 | arch_timer: timer { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 771 | compatible = "arm,armv8-timer"; |
| 772 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| 773 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| 774 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| 775 | <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; |
| 776 | clock-frequency = <19200000>; |
| 777 | }; |
| 778 | |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 779 | memtimer: timer@17c20000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 780 | #address-cells = <1>; |
| 781 | #size-cells = <1>; |
| 782 | ranges; |
| 783 | compatible = "arm,armv7-timer-mem"; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 784 | reg = <0x17c20000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 785 | clock-frequency = <19200000>; |
| 786 | |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 787 | frame@17c21000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 788 | frame-number = <0>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 789 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 790 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 791 | reg = <0x17c21000 0x1000>, |
| 792 | <0x17c22000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 793 | }; |
| 794 | |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 795 | frame@17c23000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 796 | frame-number = <1>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 797 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 798 | reg = <0x17c23000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 799 | status = "disabled"; |
| 800 | }; |
| 801 | |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 802 | frame@17c25000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 803 | frame-number = <2>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 804 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| 805 | reg = <0x17c25000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 806 | status = "disabled"; |
| 807 | }; |
| 808 | |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 809 | frame@17c27000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 810 | frame-number = <3>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 811 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| 812 | reg = <0x17c27000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 813 | status = "disabled"; |
| 814 | }; |
| 815 | |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 816 | frame@17c29000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 817 | frame-number = <4>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 818 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| 819 | reg = <0x17c29000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 820 | status = "disabled"; |
| 821 | }; |
| 822 | |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 823 | frame@17c2b000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 824 | frame-number = <5>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 825 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| 826 | reg = <0x17c2b000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 827 | status = "disabled"; |
| 828 | }; |
| 829 | |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 830 | frame@17c2d000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 831 | frame-number = <6>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 832 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 833 | reg = <0x17c2d000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 834 | status = "disabled"; |
| 835 | }; |
| 836 | }; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 837 | |
Tingwei Zhang | 020594a | 2018-11-27 21:58:09 -0800 | [diff] [blame] | 838 | jtag_mm0: jtagmm@7040000 { |
| 839 | compatible = "qcom,jtagv8-mm"; |
| 840 | reg = <0x7040000 0x1000>; |
| 841 | reg-names = "etm-base"; |
| 842 | |
| 843 | clocks = <&clock_aop QDSS_CLK>; |
| 844 | clock-names = "core_clk"; |
| 845 | |
| 846 | qcom,coresight-jtagmm-cpu = <&CPU0>; |
| 847 | }; |
| 848 | |
| 849 | jtag_mm1: jtagmm@7140000 { |
| 850 | compatible = "qcom,jtagv8-mm"; |
| 851 | reg = <0x7140000 0x1000>; |
| 852 | reg-names = "etm-base"; |
| 853 | |
| 854 | clocks = <&clock_aop QDSS_CLK>; |
| 855 | clock-names = "core_clk"; |
| 856 | |
| 857 | qcom,coresight-jtagmm-cpu = <&CPU1>; |
| 858 | }; |
| 859 | |
| 860 | jtag_mm2: jtagmm@7240000 { |
| 861 | compatible = "qcom,jtagv8-mm"; |
| 862 | reg = <0x7240000 0x1000>; |
| 863 | reg-names = "etm-base"; |
| 864 | |
| 865 | clocks = <&clock_aop QDSS_CLK>; |
| 866 | clock-names = "core_clk"; |
| 867 | |
| 868 | qcom,coresight-jtagmm-cpu = <&CPU2>; |
| 869 | }; |
| 870 | |
| 871 | jtag_mm3: jtagmm@7340000 { |
| 872 | compatible = "qcom,jtagv8-mm"; |
| 873 | reg = <0x7340000 0x1000>; |
| 874 | reg-names = "etm-base"; |
| 875 | |
| 876 | clocks = <&clock_aop QDSS_CLK>; |
| 877 | clock-names = "core_clk"; |
| 878 | |
| 879 | qcom,coresight-jtagmm-cpu = <&CPU3>; |
| 880 | }; |
| 881 | |
| 882 | jtag_mm4: jtagmm@7440000 { |
| 883 | compatible = "qcom,jtagv8-mm"; |
| 884 | reg = <0x7440000 0x1000>; |
| 885 | reg-names = "etm-base"; |
| 886 | |
| 887 | clocks = <&clock_aop QDSS_CLK>; |
| 888 | clock-names = "core_clk"; |
| 889 | |
| 890 | qcom,coresight-jtagmm-cpu = <&CPU4>; |
| 891 | }; |
| 892 | |
| 893 | jtag_mm5: jtagmm@7540000 { |
| 894 | compatible = "qcom,jtagv8-mm"; |
| 895 | reg = <0x7540000 0x1000>; |
| 896 | reg-names = "etm-base"; |
| 897 | |
| 898 | clocks = <&clock_aop QDSS_CLK>; |
| 899 | clock-names = "core_clk"; |
| 900 | |
| 901 | qcom,coresight-jtagmm-cpu = <&CPU5>; |
| 902 | }; |
| 903 | |
| 904 | jtag_mm6: jtagmm@7640000 { |
| 905 | compatible = "qcom,jtagv8-mm"; |
| 906 | reg = <0x7640000 0x1000>; |
| 907 | reg-names = "etm-base"; |
| 908 | |
| 909 | clocks = <&clock_aop QDSS_CLK>; |
| 910 | clock-names = "core_clk"; |
| 911 | |
| 912 | qcom,coresight-jtagmm-cpu = <&CPU6>; |
| 913 | }; |
| 914 | |
| 915 | jtag_mm7: jtagmm@7740000 { |
| 916 | compatible = "qcom,jtagv8-mm"; |
| 917 | reg = <0x7740000 0x1000>; |
| 918 | reg-names = "etm-base"; |
| 919 | |
| 920 | clocks = <&clock_aop QDSS_CLK>; |
| 921 | clock-names = "core_clk"; |
| 922 | |
| 923 | qcom,coresight-jtagmm-cpu = <&CPU7>; |
| 924 | }; |
| 925 | |
David Dai | 3c42780 | 2018-10-17 14:40:08 -0700 | [diff] [blame] | 926 | qcom,devfreq-l3 { |
| 927 | compatible = "qcom,devfreq-fw"; |
| 928 | reg = <0x18590000 0x4>, <0x18590100 0xa0>, <0x18590320 0x4>; |
| 929 | reg-names = "en-base", "ftbl-base", "perf-base"; |
| 930 | |
Rama Aparna Mallavarapu | de6608e | 2019-01-07 15:41:32 -0800 | [diff] [blame] | 931 | cpu0_l3: qcom,cpu0-cpu-l3-lat { |
David Dai | 3c42780 | 2018-10-17 14:40:08 -0700 | [diff] [blame] | 932 | compatible = "qcom,devfreq-fw-voter"; |
| 933 | }; |
| 934 | |
Rama Aparna Mallavarapu | de6608e | 2019-01-07 15:41:32 -0800 | [diff] [blame] | 935 | cpu4_l3: qcom,cpu4-cpu-l3-lat { |
| 936 | compatible = "qcom,devfreq-fw-voter"; |
| 937 | }; |
| 938 | |
| 939 | cpu7_l3: qcom,cpu7-cpu-l3-lat { |
| 940 | compatible = "qcom,devfreq-fw-voter"; |
| 941 | }; |
| 942 | |
| 943 | cdsp_l3: qcom,cdsp-cdsp-l3-lat { |
David Dai | 3c42780 | 2018-10-17 14:40:08 -0700 | [diff] [blame] | 944 | compatible = "qcom,devfreq-fw-voter"; |
| 945 | }; |
| 946 | }; |
| 947 | |
Dhaval Patel | 6982325 | 2019-03-20 10:37:06 -0700 | [diff] [blame] | 948 | bus_proxy_client: qcom,bus_proxy_client { |
| 949 | compatible = "qcom,bus-proxy-client"; |
| 950 | qcom,msm-bus,name = "bus-proxy-client"; |
| 951 | qcom,msm-bus,num-cases = <2>; |
| 952 | qcom,msm-bus,num-paths = <2>; |
| 953 | qcom,msm-bus,vectors-KBps = |
| 954 | <22 512 0 0>, <23 512 0 0>, |
| 955 | <22 512 1500000 1500000>, <23 512 1500000 1500000>; |
| 956 | qcom,msm-bus,active-only; |
| 957 | status = "ok"; |
| 958 | }; |
| 959 | |
David Dai | 95d5bfba | 2019-01-31 13:59:58 -0800 | [diff] [blame] | 960 | keepalive_opp_table: keepalive-opp-table { |
| 961 | compatible = "operating-points-v2"; |
| 962 | opp-1 { |
| 963 | opp-hz = /bits/ 64 < 1 >; |
| 964 | }; |
| 965 | }; |
| 966 | |
| 967 | snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive { |
| 968 | compatible = "qcom,devbw"; |
| 969 | governor = "powersave"; |
| 970 | qcom,src-dst-ports = <MSM_BUS_MASTER_AMPSS_M0 |
| 971 | MSM_BUS_SLAVE_IMEM_CFG>; |
| 972 | qcom,active-only; |
| 973 | status = "ok"; |
| 974 | operating-points-v2 = <&keepalive_opp_table>; |
| 975 | }; |
| 976 | |
Chinmay Sawarkar | e5d4b86 | 2019-01-07 15:54:39 -0800 | [diff] [blame] | 977 | venus_bus_cnoc_bw_table: bus-cnoc-bw-table { |
| 978 | compatible = "operating-points-v2"; |
| 979 | BW_OPP_ENTRY( 200, 4); |
| 980 | }; |
| 981 | |
Rama Aparna Mallavarapu | 5a7daf4 | 2019-01-14 22:08:20 -0800 | [diff] [blame] | 982 | llcc_bw_opp_table: llcc-bw-opp-table { |
| 983 | compatible = "operating-points-v2"; |
| 984 | BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ |
| 985 | BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */ |
| 986 | BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */ |
| 987 | BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */ |
| 988 | BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */ |
| 989 | BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */ |
| 990 | BW_OPP_ENTRY( 1000, 16); /* 15258 MB/s */ |
| 991 | }; |
| 992 | |
Rama Aparna Mallavarapu | 033ff62 | 2019-03-15 13:12:22 -0700 | [diff] [blame] | 993 | suspendable_llcc_bw_opp_table: suspendable-llcc-bw-opp-table { |
| 994 | compatible = "operating-points-v2"; |
| 995 | BW_OPP_ENTRY( 0, 16); /* 0 MB/s */ |
| 996 | BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ |
| 997 | BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */ |
| 998 | BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */ |
| 999 | BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */ |
| 1000 | BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */ |
| 1001 | BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */ |
| 1002 | BW_OPP_ENTRY( 1000, 16); /* 15258 MB/s */ |
| 1003 | }; |
| 1004 | |
Rama Aparna Mallavarapu | 5a7daf4 | 2019-01-14 22:08:20 -0800 | [diff] [blame] | 1005 | ddr_bw_opp_table: ddr-bw-opp-table { |
| 1006 | compatible = "operating-points-v2"; |
| 1007 | BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ |
| 1008 | BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ |
| 1009 | BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ |
| 1010 | BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ |
| 1011 | BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ |
| 1012 | BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ |
| 1013 | BW_OPP_ENTRY( 1017, 4); /* 3879 MB/s */ |
| 1014 | BW_OPP_ENTRY( 1353, 4); /* 5161 MB/s */ |
| 1015 | BW_OPP_ENTRY( 1555, 4); /* 5931 MB/s */ |
Rama Aparna Mallavarapu | de6608e | 2019-01-07 15:41:32 -0800 | [diff] [blame] | 1016 | BW_OPP_ENTRY( 1804, 4); /* 6881 MB/s */ |
Rama Aparna Mallavarapu | 5a7daf4 | 2019-01-14 22:08:20 -0800 | [diff] [blame] | 1017 | BW_OPP_ENTRY( 2092, 4); /* 7980 MB/s */ |
| 1018 | BW_OPP_ENTRY( 2736, 4); /* 10437 MB/s */ |
| 1019 | }; |
| 1020 | |
| 1021 | suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table { |
| 1022 | compatible = "operating-points-v2"; |
| 1023 | BW_OPP_ENTRY( 0, 4); /* 0 MB/s */ |
| 1024 | BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ |
| 1025 | BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ |
| 1026 | BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ |
| 1027 | BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ |
| 1028 | BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ |
| 1029 | BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ |
| 1030 | BW_OPP_ENTRY( 1017, 4); /* 3879 MB/s */ |
| 1031 | BW_OPP_ENTRY( 1353, 4); /* 5161 MB/s */ |
| 1032 | BW_OPP_ENTRY( 1555, 4); /* 5931 MB/s */ |
Rama Aparna Mallavarapu | de6608e | 2019-01-07 15:41:32 -0800 | [diff] [blame] | 1033 | BW_OPP_ENTRY( 1804, 4); /* 6881 MB/s */ |
Rama Aparna Mallavarapu | 5a7daf4 | 2019-01-14 22:08:20 -0800 | [diff] [blame] | 1034 | BW_OPP_ENTRY( 2092, 4); /* 7980 MB/s */ |
| 1035 | BW_OPP_ENTRY( 2736, 4); /* 10437 MB/s */ |
| 1036 | }; |
| 1037 | |
Rama Aparna Mallavarapu | 230fb2a | 2019-01-31 12:56:01 -0800 | [diff] [blame] | 1038 | llcc_pmu: llcc-pmu@9095000 { |
| 1039 | compatible = "qcom,llcc-pmu-ver2"; |
| 1040 | reg = <0x09095000 0x300>; |
Rama Aparna Mallavarapu | de6608e | 2019-01-07 15:41:32 -0800 | [diff] [blame] | 1041 | reg-names = "lagg-base"; |
| 1042 | }; |
| 1043 | |
| 1044 | cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw { |
| 1045 | compatible = "qcom,devbw"; |
| 1046 | governor = "performance"; |
| 1047 | qcom,src-dst-ports = |
| 1048 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>; |
| 1049 | qcom,active-only; |
| 1050 | operating-points-v2 = <&llcc_bw_opp_table>; |
| 1051 | }; |
| 1052 | |
| 1053 | cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 { |
| 1054 | compatible = "qcom,bimc-bwmon4"; |
| 1055 | reg = <0x90b6400 0x300>, <0x90b6300 0x200>; |
| 1056 | reg-names = "base", "global_base"; |
| 1057 | interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; |
| 1058 | qcom,mport = <0>; |
| 1059 | qcom,hw-timer-hz = <19200000>; |
| 1060 | qcom,target-dev = <&cpu_cpu_llcc_bw>; |
| 1061 | qcom,count-unit = <0x10000>; |
| 1062 | }; |
| 1063 | |
| 1064 | cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw { |
| 1065 | compatible = "qcom,devbw"; |
| 1066 | governor = "performance"; |
| 1067 | qcom,src-dst-ports = |
| 1068 | <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>; |
| 1069 | qcom,active-only; |
| 1070 | operating-points-v2 = <&ddr_bw_opp_table>; |
| 1071 | }; |
| 1072 | |
| 1073 | cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@9091000 { |
| 1074 | compatible = "qcom,bimc-bwmon5"; |
| 1075 | reg = <0x9091000 0x1000>; |
| 1076 | reg-names = "base"; |
| 1077 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| 1078 | qcom,hw-timer-hz = <19200000>; |
| 1079 | qcom,target-dev = <&cpu_llcc_ddr_bw>; |
| 1080 | qcom,count-unit = <0x10000>; |
| 1081 | }; |
| 1082 | |
| 1083 | npu_npu_ddr_bw: qcom,npu-npu-ddr-bw { |
| 1084 | compatible = "qcom,devbw"; |
| 1085 | governor = "performance"; |
| 1086 | qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>; |
| 1087 | operating-points-v2 = <&suspendable_ddr_bw_opp_table>; |
| 1088 | }; |
| 1089 | |
| 1090 | npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@60300 { |
| 1091 | compatible = "qcom,bimc-bwmon4"; |
Rama Aparna Mallavarapu | ca523db | 2019-03-11 14:41:49 -0700 | [diff] [blame] | 1092 | reg = <0x00060400 0x300>, <0x00060300 0x200>; |
Rama Aparna Mallavarapu | de6608e | 2019-01-07 15:41:32 -0800 | [diff] [blame] | 1093 | reg-names = "base", "global_base"; |
Rama Aparna Mallavarapu | ca523db | 2019-03-11 14:41:49 -0700 | [diff] [blame] | 1094 | interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; |
Rama Aparna Mallavarapu | de6608e | 2019-01-07 15:41:32 -0800 | [diff] [blame] | 1095 | qcom,mport = <0>; |
| 1096 | qcom,hw-timer-hz = <19200000>; |
| 1097 | qcom,target-dev = <&npu_npu_ddr_bw>; |
| 1098 | qcom,count-unit = <0x10000>; |
| 1099 | }; |
| 1100 | |
Rama Aparna Mallavarapu | ca523db | 2019-03-11 14:41:49 -0700 | [diff] [blame] | 1101 | npudsp_npu_ddr_bw: qcom,npudsp-npu-ddr-bw { |
| 1102 | compatible = "qcom,devbw"; |
| 1103 | governor = "performance"; |
| 1104 | qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>; |
| 1105 | operating-points-v2 = <&suspendable_ddr_bw_opp_table>; |
| 1106 | }; |
| 1107 | |
| 1108 | npudsp_npu_ddr_bwmon: qcom,npudsp-npu-ddr-bwmon@70200 { |
Rama Aparna Mallavarapu | de6608e | 2019-01-07 15:41:32 -0800 | [diff] [blame] | 1109 | compatible = "qcom,bimc-bwmon4"; |
Rama Aparna Mallavarapu | ca523db | 2019-03-11 14:41:49 -0700 | [diff] [blame] | 1110 | reg = <0x00070300 0x300>, <0x00070200 0x200>; |
Rama Aparna Mallavarapu | de6608e | 2019-01-07 15:41:32 -0800 | [diff] [blame] | 1111 | reg-names = "base", "global_base"; |
| 1112 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
| 1113 | qcom,mport = <0>; |
| 1114 | qcom,hw-timer-hz = <19200000>; |
Rama Aparna Mallavarapu | ca523db | 2019-03-11 14:41:49 -0700 | [diff] [blame] | 1115 | qcom,target-dev = <&npudsp_npu_ddr_bw>; |
Rama Aparna Mallavarapu | de6608e | 2019-01-07 15:41:32 -0800 | [diff] [blame] | 1116 | qcom,count-unit = <0x10000>; |
| 1117 | }; |
| 1118 | |
| 1119 | cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { |
| 1120 | compatible = "qcom,arm-memlat-mon"; |
| 1121 | qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; |
| 1122 | qcom,target-dev = <&cpu0_l3>; |
| 1123 | qcom,cachemiss-ev = <0x17>; |
| 1124 | qcom,core-dev-table = |
| 1125 | < 300000 300000000 >, |
| 1126 | < 403200 403200000 >, |
| 1127 | < 518400 518400000 >, |
| 1128 | < 633600 614400000 >, |
| 1129 | < 825600 729600000 >, |
| 1130 | < 921600 825600000 >, |
| 1131 | < 1036800 921600000 >, |
| 1132 | < 1132800 1036800000 >, |
| 1133 | < 1228800 1132800000 >, |
| 1134 | < 1401600 1228800000 >, |
| 1135 | < 1497600 1305600000 >, |
| 1136 | < 1670400 1382400000 >; |
| 1137 | }; |
| 1138 | |
| 1139 | cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { |
| 1140 | compatible = "qcom,arm-memlat-mon"; |
| 1141 | qcom,cpulist = <&CPU4 &CPU5 &CPU6>; |
| 1142 | qcom,target-dev = <&cpu4_l3>; |
| 1143 | qcom,cachemiss-ev = <0x17>; |
| 1144 | qcom,core-dev-table = |
| 1145 | < 300000 300000000 >, |
| 1146 | < 806400 614400000 >, |
| 1147 | < 1017600 729600000 >, |
| 1148 | < 1228800 921600000 >, |
| 1149 | < 1689600 1228800000 >, |
| 1150 | < 1804800 1305600000 >, |
| 1151 | < 2227200 1382400000 >; |
| 1152 | }; |
| 1153 | |
| 1154 | cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon { |
| 1155 | compatible = "qcom,arm-memlat-mon"; |
| 1156 | qcom,cpulist = <&CPU7>; |
| 1157 | qcom,target-dev = <&cpu7_l3>; |
| 1158 | qcom,cachemiss-ev = <0x17>; |
| 1159 | qcom,core-dev-table = |
| 1160 | < 300000 300000000 >, |
| 1161 | < 806400 614400000 >, |
| 1162 | < 1017600 729600000 >, |
| 1163 | < 1228800 921600000 >, |
| 1164 | < 1689600 1228800000 >, |
| 1165 | < 1804800 1305600000 >, |
| 1166 | < 2227200 1382400000 >; |
| 1167 | }; |
| 1168 | |
| 1169 | cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { |
| 1170 | compatible = "qcom,devbw"; |
| 1171 | governor = "performance"; |
| 1172 | qcom,src-dst-ports = |
| 1173 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>; |
| 1174 | qcom,active-only; |
| 1175 | operating-points-v2 = <&llcc_bw_opp_table>; |
| 1176 | }; |
| 1177 | |
| 1178 | cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { |
| 1179 | compatible = "qcom,arm-memlat-mon"; |
| 1180 | qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; |
| 1181 | qcom,target-dev = <&cpu0_cpu_llcc_lat>; |
| 1182 | qcom,cachemiss-ev = <0x2A>; |
| 1183 | qcom,core-dev-table = |
| 1184 | < 300000 MHZ_TO_MBPS( 150, 16) >, |
| 1185 | < 729600 MHZ_TO_MBPS( 300, 16) >, |
| 1186 | < 1497600 MHZ_TO_MBPS( 466, 16) >, |
| 1187 | < 1670400 MHZ_TO_MBPS( 600, 16) >; |
| 1188 | }; |
| 1189 | |
| 1190 | cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat { |
| 1191 | compatible = "qcom,devbw"; |
| 1192 | governor = "performance"; |
| 1193 | qcom,src-dst-ports = |
| 1194 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>; |
| 1195 | qcom,active-only; |
| 1196 | operating-points-v2 = <&llcc_bw_opp_table>; |
| 1197 | }; |
| 1198 | |
| 1199 | cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon { |
| 1200 | compatible = "qcom,arm-memlat-mon"; |
| 1201 | qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; |
| 1202 | qcom,target-dev = <&cpu4_cpu_llcc_lat>; |
| 1203 | qcom,cachemiss-ev = <0x2A>; |
| 1204 | qcom,core-dev-table = |
| 1205 | < 300000 MHZ_TO_MBPS( 150, 16) >, |
| 1206 | < 691200 MHZ_TO_MBPS( 300, 16) >, |
| 1207 | < 1017600 MHZ_TO_MBPS( 466, 16) >, |
| 1208 | < 1228800 MHZ_TO_MBPS( 600, 16) >, |
| 1209 | < 1804800 MHZ_TO_MBPS( 806, 16) >, |
| 1210 | < 2227200 MHZ_TO_MBPS( 933, 16) >, |
| 1211 | < 2476800 MHZ_TO_MBPS( 1000, 16) >; |
| 1212 | }; |
| 1213 | |
| 1214 | cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat { |
| 1215 | compatible = "qcom,devbw"; |
| 1216 | governor = "performance"; |
| 1217 | qcom,src-dst-ports = |
| 1218 | <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>; |
| 1219 | qcom,active-only; |
| 1220 | operating-points-v2 = <&ddr_bw_opp_table>; |
| 1221 | }; |
| 1222 | |
| 1223 | cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon { |
| 1224 | compatible = "qcom,arm-memlat-mon"; |
| 1225 | qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; |
| 1226 | qcom,target-dev = <&cpu0_llcc_ddr_lat>; |
Rama Aparna Mallavarapu | f81d55d | 2019-03-11 12:22:23 -0700 | [diff] [blame] | 1227 | qcom,cachemiss-ev = <0x2A>; |
Rama Aparna Mallavarapu | de6608e | 2019-01-07 15:41:32 -0800 | [diff] [blame] | 1228 | qcom,core-dev-table = |
| 1229 | < 300000 MHZ_TO_MBPS( 200, 4) >, |
| 1230 | < 729600 MHZ_TO_MBPS( 451, 4) >, |
| 1231 | < 1132800 MHZ_TO_MBPS( 547, 4) >, |
| 1232 | < 1497600 MHZ_TO_MBPS( 768, 4) >, |
| 1233 | < 1670400 MHZ_TO_MBPS( 1017, 4) >; |
| 1234 | }; |
| 1235 | |
| 1236 | cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat { |
| 1237 | compatible = "qcom,devbw"; |
| 1238 | governor = "performance"; |
| 1239 | qcom,src-dst-ports = |
| 1240 | <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>; |
| 1241 | qcom,active-only; |
| 1242 | operating-points-v2 = <&ddr_bw_opp_table>; |
| 1243 | }; |
| 1244 | |
| 1245 | cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon { |
| 1246 | compatible = "qcom,arm-memlat-mon"; |
| 1247 | qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; |
| 1248 | qcom,target-dev = <&cpu4_llcc_ddr_lat>; |
Rama Aparna Mallavarapu | f81d55d | 2019-03-11 12:22:23 -0700 | [diff] [blame] | 1249 | qcom,cachemiss-ev = <0x2A>; |
Rama Aparna Mallavarapu | de6608e | 2019-01-07 15:41:32 -0800 | [diff] [blame] | 1250 | qcom,core-dev-table = |
| 1251 | < 300000 MHZ_TO_MBPS( 200, 4) >, |
| 1252 | < 691200 MHZ_TO_MBPS( 451, 4) >, |
| 1253 | < 806400 MHZ_TO_MBPS( 547, 4) >, |
| 1254 | < 1017600 MHZ_TO_MBPS( 768, 4) >, |
| 1255 | < 1228800 MHZ_TO_MBPS(1017, 4) >, |
| 1256 | < 1574400 MHZ_TO_MBPS(1353, 4) >, |
| 1257 | < 1804800 MHZ_TO_MBPS(1555, 4) >, |
| 1258 | < 2227200 MHZ_TO_MBPS(1804, 4) >, |
| 1259 | < 2380800 MHZ_TO_MBPS(2092, 4) >, |
| 1260 | < 2476800 MHZ_TO_MBPS(2736, 4) >; |
| 1261 | }; |
| 1262 | |
| 1263 | cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor { |
| 1264 | compatible = "qcom,devbw"; |
| 1265 | governor = "performance"; |
| 1266 | qcom,src-dst-ports = |
| 1267 | <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>; |
| 1268 | qcom,active-only; |
| 1269 | operating-points-v2 = <&ddr_bw_opp_table>; |
| 1270 | }; |
| 1271 | |
| 1272 | cpu4_computemon: qcom,cpu4-computemon { |
| 1273 | compatible = "qcom,arm-cpu-mon"; |
| 1274 | qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; |
| 1275 | qcom,target-dev = <&cpu4_cpu_ddr_latfloor>; |
| 1276 | qcom,core-dev-table = |
| 1277 | < 1804800 MHZ_TO_MBPS( 200, 4) >, |
| 1278 | < 2380800 MHZ_TO_MBPS(1017, 4) >, |
| 1279 | < 2500000 MHZ_TO_MBPS(2736, 4) >; |
| 1280 | }; |
| 1281 | |
| 1282 | keepalive_opp_table: keepalive-opp-table { |
| 1283 | compatible = "operating-points-v2"; |
| 1284 | opp-1 { |
| 1285 | opp-hz = /bits/ 64 < 1 >; |
| 1286 | }; |
| 1287 | }; |
| 1288 | |
| 1289 | snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive { |
| 1290 | compatible = "qcom,devbw"; |
| 1291 | governor = "powersave"; |
| 1292 | qcom,src-dst-ports = <1 627>; |
| 1293 | qcom,active-only; |
| 1294 | status = "ok"; |
| 1295 | operating-points-v2 = <&keepalive_opp_table>; |
| 1296 | }; |
| 1297 | |
| 1298 | cdsp_keepalive: qcom,cdsp_keepalive { |
| 1299 | compatible = "qcom,devbw"; |
| 1300 | governor = "powersave"; |
| 1301 | qcom,src-dst-ports = <154 10070>; |
| 1302 | qcom,active-only; |
| 1303 | status = "ok"; |
| 1304 | operating-points-v2 = <&keepalive_opp_table>; |
| 1305 | }; |
| 1306 | |
Rishabh Bhatnagar | f35ba02 | 2018-09-18 15:17:22 -0700 | [diff] [blame] | 1307 | qcom,msm-imem@146bf000 { |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 1308 | compatible = "qcom,msm-imem"; |
| 1309 | reg = <0x146bf000 0x1000>; |
| 1310 | ranges = <0x0 0x146bf000 0x1000>; |
| 1311 | #address-cells = <1>; |
| 1312 | #size-cells = <1>; |
| 1313 | |
Tingwei Zhang | d9b535f | 2018-12-03 19:14:06 -0800 | [diff] [blame] | 1314 | mem_dump_table@10 { |
| 1315 | compatible = "qcom,msm-imem-mem_dump_table"; |
| 1316 | reg = <0x10 0x8>; |
| 1317 | }; |
| 1318 | |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 1319 | restart_reason@65c { |
| 1320 | compatible = "qcom,msm-imem-restart_reason"; |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 1321 | reg = <0x65c 0x4>; |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 1322 | }; |
| 1323 | |
| 1324 | dload_type@1c { |
| 1325 | compatible = "qcom,msm-imem-dload-type"; |
| 1326 | reg = <0x1c 0x4>; |
| 1327 | }; |
| 1328 | |
| 1329 | boot_stats@6b0 { |
| 1330 | compatible = "qcom,msm-imem-boot_stats"; |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 1331 | reg = <0x6b0 0x20>; |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 1332 | }; |
| 1333 | |
| 1334 | kaslr_offset@6d0 { |
| 1335 | compatible = "qcom,msm-imem-kaslr_offset"; |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 1336 | reg = <0x6d0 0xc>; |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 1337 | }; |
| 1338 | |
| 1339 | pil@94c { |
| 1340 | compatible = "qcom,msm-imem-pil"; |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 1341 | reg = <0x94c 0xc8>; |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 1342 | }; |
Hemant Kumar | ca39968 | 2019-01-25 14:51:13 -0800 | [diff] [blame] | 1343 | |
| 1344 | diag_dload@c8 { |
| 1345 | compatible = "qcom,msm-imem-diag-dload"; |
| 1346 | reg = <0xc8 0xc8>; |
| 1347 | }; |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 1348 | }; |
| 1349 | |
Rishabh Bhatnagar | 811170f | 2018-11-09 13:44:32 -0800 | [diff] [blame] | 1350 | restart@c264000 { |
| 1351 | compatible = "qcom,pshold"; |
| 1352 | reg = <0xc264000 0x4>, |
| 1353 | <0x1fd3000 0x4>; |
| 1354 | reg-names = "pshold-base", "tcsr-boot-misc-detect"; |
| 1355 | }; |
| 1356 | |
Zhen Kong | 284c9f0 | 2018-11-06 12:00:30 -0800 | [diff] [blame] | 1357 | dcc: dcc_v2@1023000 { |
| 1358 | compatible = "qcom,dcc-v2"; |
| 1359 | reg = <0x1023000 0x1000>, |
| 1360 | <0x103a000 0x6000>; |
| 1361 | reg-names = "dcc-base", "dcc-ram-base"; |
| 1362 | |
| 1363 | dcc-ram-offset = <0x1a000>; |
| 1364 | }; |
| 1365 | |
| 1366 | qcom_seecom: qseecom@82200000 { |
| 1367 | compatible = "qcom,qseecom"; |
| 1368 | reg = <0x82200000 0x2200000>; |
| 1369 | reg-names = "secapp-region"; |
| 1370 | memory-region = <&qseecom_mem>; |
| 1371 | qcom,hlos-num-ce-hw-instances = <1>; |
| 1372 | qcom,hlos-ce-hw-instance = <0>; |
| 1373 | qcom,qsee-ce-hw-instance = <0>; |
| 1374 | qcom,disk-encrypt-pipe-pair = <2>; |
| 1375 | qcom,support-fde; |
| 1376 | qcom,no-clock-support; |
| 1377 | qcom,fde-key-size; |
Zhen Kong | 8499702 | 2019-01-29 12:52:21 -0800 | [diff] [blame] | 1378 | qcom,appsbl-qseecom-support; |
Zhen Kong | 284c9f0 | 2018-11-06 12:00:30 -0800 | [diff] [blame] | 1379 | qcom,commonlib64-loaded-by-uefi; |
| 1380 | qcom,qsee-reentrancy-support = <2>; |
| 1381 | }; |
| 1382 | |
Zhen Kong | 24ab1cf | 2019-02-20 11:59:15 -0800 | [diff] [blame] | 1383 | qcom_rng: qrng@793000 { |
| 1384 | compatible = "qcom,msm-rng"; |
| 1385 | reg = <0x793000 0x1000>; |
| 1386 | qcom,msm-rng-iface-clk; |
| 1387 | qcom,no-qrng-config; |
| 1388 | qcom,msm-bus,name = "msm-rng-noc"; |
| 1389 | qcom,msm-bus,num-cases = <2>; |
| 1390 | qcom,msm-bus,num-paths = <1>; |
| 1391 | qcom,msm-bus,vectors-KBps = |
| 1392 | <1 618 0 0>, /* No vote */ |
| 1393 | <1 618 0 300000>; /* 75 MHz */ |
| 1394 | clocks = <&clock_gcc GCC_PRNG_AHB_CLK>; |
| 1395 | clock-names = "iface_clk"; |
| 1396 | }; |
| 1397 | |
Rishabh Bhatnagar | 19ddb35e | 2018-09-18 15:53:03 -0700 | [diff] [blame] | 1398 | mdm0: qcom,mdm0 { |
Rishabh Bhatnagar | 134ede8 | 2018-10-16 10:54:12 -0700 | [diff] [blame] | 1399 | compatible = "qcom,ext-sdx55m"; |
Rishabh Bhatnagar | 19ddb35e | 2018-09-18 15:53:03 -0700 | [diff] [blame] | 1400 | cell-index = <0>; |
| 1401 | #address-cells = <0>; |
| 1402 | interrupt-parent = <&mdm0>; |
| 1403 | #interrupt-cells = <1>; |
| 1404 | interrupt-map-mask = <0xffffffff>; |
| 1405 | interrupt-names = |
| 1406 | "err_fatal_irq", |
| 1407 | "status_irq", |
| 1408 | "mdm2ap_vddmin_irq"; |
| 1409 | /* modem attributes */ |
| 1410 | qcom,ramdump-delay-ms = <3000>; |
| 1411 | qcom,ramdump-timeout-ms = <120000>; |
| 1412 | qcom,vddmin-modes = "normal"; |
| 1413 | qcom,vddmin-drive-strength = <8>; |
| 1414 | qcom,sfr-query; |
| 1415 | qcom,sysmon-id = <20>; |
| 1416 | qcom,ssctl-instance-id = <0x10>; |
| 1417 | qcom,support-shutdown; |
| 1418 | qcom,pil-force-shutdown; |
| 1419 | qcom,esoc-skip-restart-for-mdm-crash; |
Rishabh Bhatnagar | 632f326 | 2019-01-25 10:30:36 -0800 | [diff] [blame] | 1420 | qcom,esoc-spmi-soft-reset; |
Rishabh Bhatnagar | 19ddb35e | 2018-09-18 15:53:03 -0700 | [diff] [blame] | 1421 | pinctrl-names = "default", "mdm_active", "mdm_suspend"; |
| 1422 | pinctrl-0 = <&ap2mdm_pon_reset_default>; |
| 1423 | pinctrl-1 = <&ap2mdm_active &mdm2ap_active>; |
| 1424 | pinctrl-2 = <&ap2mdm_sleep &mdm2ap_sleep>; |
| 1425 | interrupt-map = <0 &tlmm 1 0x3 |
| 1426 | 1 &tlmm 3 0x3>; |
| 1427 | qcom,mdm2ap-errfatal-gpio = <&tlmm 1 0x00>; |
| 1428 | qcom,ap2mdm-errfatal-gpio = <&tlmm 57 0x00>; |
| 1429 | qcom,mdm2ap-status-gpio = <&tlmm 3 0x00>; |
| 1430 | qcom,ap2mdm-status-gpio = <&tlmm 56 0x00>; |
Rishabh Bhatnagar | 2b66dc1 | 2018-10-18 10:36:27 -0700 | [diff] [blame] | 1431 | qcom,ap2mdm-soft-reset-gpio = <&tlmm 145 GPIO_ACTIVE_LOW>; |
Rishabh Bhatnagar | 19ddb35e | 2018-09-18 15:53:03 -0700 | [diff] [blame] | 1432 | qcom,mdm-link-info = "0306_02.01.00"; |
| 1433 | status = "ok"; |
| 1434 | }; |
| 1435 | |
Lina Iyer | 8551c79 | 2018-06-21 16:06:53 -0600 | [diff] [blame] | 1436 | pdc: interrupt-controller@b220000 { |
| 1437 | compatible = "qcom,kona-pdc"; |
| 1438 | reg = <0xb220000 0x30000>; |
Lina Iyer | 20cebbc | 2019-02-06 09:06:52 -0700 | [diff] [blame] | 1439 | qcom,pdc-ranges = <0 480 30>, <42 522 52>, <94 609 30>; |
Lina Iyer | 8551c79 | 2018-06-21 16:06:53 -0600 | [diff] [blame] | 1440 | #interrupt-cells = <2>; |
| 1441 | interrupt-parent = <&intc>; |
| 1442 | interrupt-controller; |
| 1443 | }; |
| 1444 | |
Vivek Aknurwar | 65bafd9 | 2018-11-01 17:27:53 -0700 | [diff] [blame] | 1445 | clocks { |
David Dai | ee6a9d6 | 2019-01-10 17:14:04 -0800 | [diff] [blame] | 1446 | xo_board: xo-board { |
| 1447 | compatible = "fixed-clock"; |
| 1448 | #clock-cells = <0>; |
| 1449 | clock-frequency = <38400000>; |
| 1450 | clock-output-names = "xo_board"; |
| 1451 | }; |
| 1452 | |
Vivek Aknurwar | 65bafd9 | 2018-11-01 17:27:53 -0700 | [diff] [blame] | 1453 | sleep_clk: sleep-clk { |
| 1454 | compatible = "fixed-clock"; |
| 1455 | clock-frequency = <32000>; |
| 1456 | clock-output-names = "chip_sleep_clk"; |
| 1457 | #clock-cells = <1>; |
| 1458 | }; |
| 1459 | }; |
| 1460 | |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 1461 | clock_aop: qcom,aopclk { |
David Collins | b8a46bb | 2019-01-07 18:03:13 -0800 | [diff] [blame] | 1462 | compatible = "qcom,aop-qmp-clk"; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 1463 | #clock-cells = <1>; |
David Collins | b8a46bb | 2019-01-07 18:03:13 -0800 | [diff] [blame] | 1464 | mboxes = <&qmp_aop 0>; |
| 1465 | mbox-names = "qdss_clk"; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 1466 | }; |
| 1467 | |
Vivek Aknurwar | 7e9ecb9 | 2018-09-07 14:27:58 -0700 | [diff] [blame] | 1468 | clock_gcc: qcom,gcc@100000 { |
David Dai | 7e431ad | 2018-12-05 15:37:39 -0800 | [diff] [blame] | 1469 | compatible = "qcom,gcc-kona", "syscon"; |
Vivek Aknurwar | 7e9ecb9 | 2018-09-07 14:27:58 -0700 | [diff] [blame] | 1470 | reg = <0x100000 0x1f0000>; |
| 1471 | reg-names = "cc_base"; |
| 1472 | vdd_cx-supply = <&VDD_CX_LEVEL>; |
| 1473 | vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; |
| 1474 | vdd_mm-supply = <&VDD_MMCX_LEVEL>; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 1475 | #clock-cells = <1>; |
| 1476 | #reset-cells = <1>; |
| 1477 | }; |
| 1478 | |
David Collins | 4eb34f3 | 2018-12-06 11:51:01 -0800 | [diff] [blame] | 1479 | clock_npucc: qcom,npucc@9980000 { |
| 1480 | compatible = "qcom,npucc-kona", "syscon"; |
| 1481 | reg = <0x9980000 0x10000>, |
| 1482 | <0x9800000 0x10000>, |
| 1483 | <0x9810000 0x10000>; |
| 1484 | reg-names = "cc", "qdsp6ss", "qdsp6ss_pll"; |
| 1485 | vdd_cx-supply = <&VDD_CX_LEVEL>; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 1486 | #clock-cells = <1>; |
| 1487 | #reset-cells = <1>; |
| 1488 | }; |
| 1489 | |
Vivek Aknurwar | 65bafd9 | 2018-11-01 17:27:53 -0700 | [diff] [blame] | 1490 | clock_videocc: qcom,videocc@abf0000 { |
| 1491 | compatible = "qcom,videocc-kona", "syscon"; |
| 1492 | reg = <0xabf0000 0x10000>; |
| 1493 | reg-names = "cc_base"; |
| 1494 | vdd_mx-supply = <&VDD_MX_LEVEL>; |
| 1495 | vdd_mm-supply = <&VDD_MMCX_LEVEL>; |
| 1496 | clock-names = "cfg_ahb_clk"; |
| 1497 | clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 1498 | #clock-cells = <1>; |
| 1499 | #reset-cells = <1>; |
| 1500 | }; |
| 1501 | |
Vivek Aknurwar | 86452c0 | 2018-11-05 15:20:31 -0800 | [diff] [blame] | 1502 | clock_camcc: qcom,camcc@ad00000 { |
| 1503 | compatible = "qcom,camcc-kona", "syscon"; |
| 1504 | reg = <0xad00000 0x10000>; |
| 1505 | reg-names = "cc_base"; |
| 1506 | vdd_mx-supply = <&VDD_MX_LEVEL>; |
| 1507 | vdd_mm-supply = <&VDD_MMCX_LEVEL>; |
| 1508 | clock-names = "cfg_ahb_clk"; |
| 1509 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 1510 | #clock-cells = <1>; |
| 1511 | #reset-cells = <1>; |
| 1512 | }; |
| 1513 | |
David Dai | dc93e48 | 2018-11-27 17:32:50 -0800 | [diff] [blame] | 1514 | clock_dispcc: qcom,dispcc@af00000 { |
David Dai | 7e431ad | 2018-12-05 15:37:39 -0800 | [diff] [blame] | 1515 | compatible = "qcom,kona-dispcc", "syscon"; |
David Dai | dc93e48 | 2018-11-27 17:32:50 -0800 | [diff] [blame] | 1516 | reg = <0xaf00000 0x20000>; |
| 1517 | reg-names = "cc_base"; |
| 1518 | vdd_mm-supply = <&VDD_MMCX_LEVEL>; |
| 1519 | clock-names = "cfg_ahb_clk"; |
| 1520 | clocks = <&clock_gcc GCC_DISP_AHB_CLK>; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 1521 | #clock-cells = <1>; |
| 1522 | #reset-cells = <1>; |
| 1523 | }; |
| 1524 | |
Vivek Aknurwar | 31c2e0f2 | 2018-11-16 17:10:12 -0800 | [diff] [blame] | 1525 | clock_gpucc: qcom,gpucc@3d90000 { |
| 1526 | compatible = "qcom,gpucc-kona", "syscon"; |
| 1527 | reg = <0x3d90000 0x9000>; |
| 1528 | reg-names = "cc_base"; |
| 1529 | vdd_cx-supply = <&VDD_CX_LEVEL>; |
| 1530 | vdd_mx-supply = <&VDD_MX_LEVEL>; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 1531 | #clock-cells = <1>; |
| 1532 | #reset-cells = <1>; |
| 1533 | }; |
| 1534 | |
| 1535 | clock_cpucc: qcom,cpucc { |
| 1536 | compatible = "qcom,dummycc"; |
| 1537 | clock-output-names = "cpucc_clocks"; |
| 1538 | #clock-cells = <1>; |
| 1539 | }; |
Raghavendra Rao Ananta | 0295796 | 2018-08-06 15:28:34 -0700 | [diff] [blame] | 1540 | |
David Dai | 7e431ad | 2018-12-05 15:37:39 -0800 | [diff] [blame] | 1541 | clock_debugcc: qcom,cc-debug { |
| 1542 | compatible = "qcom,kona-debugcc"; |
| 1543 | qcom,gcc = <&clock_gcc>; |
| 1544 | qcom,videocc = <&clock_videocc>; |
| 1545 | qcom,dispcc = <&clock_dispcc>; |
| 1546 | qcom,camcc = <&clock_camcc>; |
| 1547 | qcom,gpucc = <&clock_gpucc>; |
David Collins | 4eb34f3 | 2018-12-06 11:51:01 -0800 | [diff] [blame] | 1548 | qcom,npucc = <&clock_npucc>; |
David Dai | 7e431ad | 2018-12-05 15:37:39 -0800 | [diff] [blame] | 1549 | clock-names = "xo_clk_src"; |
David Dai | ee6a9d6 | 2019-01-10 17:14:04 -0800 | [diff] [blame] | 1550 | clocks = <&clock_rpmh RPMH_CXO_CLK>; |
David Dai | 7e431ad | 2018-12-05 15:37:39 -0800 | [diff] [blame] | 1551 | #clock-cells = <1>; |
| 1552 | }; |
| 1553 | |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1554 | /* GCC GDSCs */ |
| 1555 | pcie_0_gdsc: qcom,gdsc@16b004 { |
| 1556 | compatible = "qcom,gdsc"; |
| 1557 | reg = <0x16b004 0x4>; |
| 1558 | regulator-name = "pcie_0_gdsc"; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1559 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1560 | }; |
| 1561 | |
| 1562 | pcie_1_gdsc: qcom,gdsc@18d004 { |
| 1563 | compatible = "qcom,gdsc"; |
| 1564 | reg = <0x18d004 0x4>; |
| 1565 | regulator-name = "pcie_1_gdsc"; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1566 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1567 | }; |
| 1568 | |
| 1569 | pcie_2_gdsc: qcom,gdsc@106004 { |
| 1570 | compatible = "qcom,gdsc"; |
| 1571 | reg = <0x106004 0x4>; |
| 1572 | regulator-name = "pcie_2_gdsc"; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1573 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1574 | }; |
| 1575 | |
| 1576 | ufs_card_gdsc: qcom,gdsc@175004 { |
| 1577 | compatible = "qcom,gdsc"; |
| 1578 | reg = <0x175004 0x4>; |
| 1579 | regulator-name = "ufs_card_gdsc"; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1580 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1581 | }; |
| 1582 | |
| 1583 | ufs_phy_gdsc: qcom,gdsc@177004 { |
| 1584 | compatible = "qcom,gdsc"; |
| 1585 | reg = <0x177004 0x4>; |
| 1586 | regulator-name = "ufs_phy_gdsc"; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1587 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1588 | }; |
| 1589 | |
| 1590 | usb30_prim_gdsc: qcom,gdsc@10f004 { |
| 1591 | compatible = "qcom,gdsc"; |
| 1592 | reg = <0x10f004 0x4>; |
| 1593 | regulator-name = "usb30_prim_gdsc"; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1594 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1595 | }; |
| 1596 | |
| 1597 | usb30_sec_gdsc: qcom,gdsc@110004 { |
| 1598 | compatible = "qcom,gdsc"; |
| 1599 | reg = <0x110004 0x4>; |
| 1600 | regulator-name = "usb30_sec_gdsc"; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1601 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1602 | }; |
| 1603 | |
| 1604 | hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 { |
| 1605 | compatible = "qcom,gdsc"; |
| 1606 | reg = <0x17d050 0x4>; |
| 1607 | regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; |
| 1608 | qcom,no-status-check-on-disable; |
| 1609 | qcom,gds-timeout = <500>; |
| 1610 | }; |
| 1611 | |
| 1612 | hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 { |
| 1613 | compatible = "qcom,gdsc"; |
| 1614 | reg = <0x17d058 0x4>; |
| 1615 | regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; |
| 1616 | qcom,no-status-check-on-disable; |
| 1617 | qcom,gds-timeout = <500>; |
| 1618 | }; |
| 1619 | |
| 1620 | hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 { |
| 1621 | compatible = "qcom,gdsc"; |
| 1622 | reg = <0x17d054 0x4>; |
| 1623 | regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc"; |
| 1624 | qcom,no-status-check-on-disable; |
| 1625 | qcom,gds-timeout = <500>; |
| 1626 | }; |
| 1627 | |
| 1628 | hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@17d06c { |
| 1629 | compatible = "qcom,gdsc"; |
| 1630 | reg = <0x17d06c 0x4>; |
| 1631 | regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc"; |
| 1632 | qcom,no-status-check-on-disable; |
| 1633 | qcom,gds-timeout = <500>; |
| 1634 | }; |
| 1635 | |
| 1636 | /* CAM_CC GDSCs */ |
| 1637 | bps_gdsc: qcom,gdsc@ad07004 { |
| 1638 | compatible = "qcom,gdsc"; |
| 1639 | reg = <0xad07004 0x4>; |
| 1640 | regulator-name = "bps_gdsc"; |
| 1641 | clock-names = "ahb_clk"; |
| 1642 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 1643 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1644 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 1645 | qcom,support-hw-trigger; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1646 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1647 | }; |
| 1648 | |
| 1649 | ife_0_gdsc: qcom,gdsc@ad0a004 { |
| 1650 | compatible = "qcom,gdsc"; |
| 1651 | reg = <0xad0a004 0x4>; |
| 1652 | regulator-name = "ife_0_gdsc"; |
| 1653 | clock-names = "ahb_clk"; |
| 1654 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 1655 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1656 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1657 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1658 | }; |
| 1659 | |
| 1660 | ife_1_gdsc: qcom,gdsc@ad0b004 { |
| 1661 | compatible = "qcom,gdsc"; |
| 1662 | reg = <0xad0b004 0x4>; |
| 1663 | regulator-name = "ife_1_gdsc"; |
| 1664 | clock-names = "ahb_clk"; |
| 1665 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 1666 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1667 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1668 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1669 | }; |
| 1670 | |
| 1671 | ipe_0_gdsc: qcom,gdsc@ad08004 { |
| 1672 | compatible = "qcom,gdsc"; |
| 1673 | reg = <0xad08004 0x4>; |
| 1674 | regulator-name = "ipe_0_gdsc"; |
| 1675 | clock-names = "ahb_clk"; |
| 1676 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 1677 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1678 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 1679 | qcom,support-hw-trigger; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1680 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1681 | }; |
| 1682 | |
| 1683 | sbi_gdsc: qcom,gdsc@ad09004 { |
| 1684 | compatible = "qcom,gdsc"; |
| 1685 | reg = <0xad09004 0x4>; |
| 1686 | regulator-name = "sbi_gdsc"; |
| 1687 | clock-names = "ahb_clk"; |
| 1688 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 1689 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1690 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1691 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1692 | }; |
| 1693 | |
| 1694 | titan_top_gdsc: qcom,gdsc@ad0c144 { |
| 1695 | compatible = "qcom,gdsc"; |
| 1696 | reg = <0xad0c144 0x4>; |
| 1697 | regulator-name = "titan_top_gdsc"; |
| 1698 | clock-names = "ahb_clk"; |
| 1699 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 1700 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1701 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1702 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1703 | }; |
| 1704 | |
| 1705 | /* DISP_CC GDSC */ |
| 1706 | mdss_core_gdsc: qcom,gdsc@af03000 { |
| 1707 | compatible = "qcom,gdsc"; |
| 1708 | reg = <0xaf03000 0x4>; |
| 1709 | regulator-name = "mdss_core_gdsc"; |
| 1710 | clock-names = "ahb_clk"; |
| 1711 | clocks = <&clock_gcc GCC_DISP_AHB_CLK>; |
| 1712 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1713 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 1714 | qcom,support-hw-trigger; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1715 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1716 | }; |
| 1717 | |
| 1718 | /* GPU_CC GDSCs */ |
| 1719 | gpu_cx_hw_ctrl: syscon@3d91540 { |
| 1720 | compatible = "syscon"; |
| 1721 | reg = <0x3d91540 0x4>; |
| 1722 | }; |
| 1723 | |
| 1724 | gpu_cx_gdsc: qcom,gdsc@3d9106c { |
| 1725 | compatible = "qcom,gdsc"; |
| 1726 | reg = <0x3d9106c 0x4>; |
| 1727 | regulator-name = "gpu_cx_gdsc"; |
| 1728 | hw-ctrl-addr = <&gpu_cx_hw_ctrl>; |
| 1729 | parent-supply = <&VDD_CX_LEVEL>; |
| 1730 | qcom,no-status-check-on-disable; |
| 1731 | qcom,clk-dis-wait-val = <8>; |
| 1732 | qcom,gds-timeout = <500>; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1733 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1734 | }; |
| 1735 | |
David Collins | d7eea14 | 2018-10-08 17:32:48 -0700 | [diff] [blame] | 1736 | gpu_gx_domain_addr: syscon@3d91508 { |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1737 | compatible = "syscon"; |
| 1738 | reg = <0x3d91508 0x4>; |
| 1739 | }; |
| 1740 | |
David Collins | d7eea14 | 2018-10-08 17:32:48 -0700 | [diff] [blame] | 1741 | gpu_gx_sw_reset: syscon@3d91008 { |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1742 | compatible = "syscon"; |
| 1743 | reg = <0x3d91008 0x4>; |
| 1744 | }; |
| 1745 | |
| 1746 | gpu_gx_gdsc: qcom,gdsc@3d9100c { |
| 1747 | compatible = "qcom,gdsc"; |
| 1748 | reg = <0x3d9100c 0x4>; |
| 1749 | regulator-name = "gpu_gx_gdsc"; |
| 1750 | domain-addr = <&gpu_gx_domain_addr>; |
| 1751 | sw-reset = <&gpu_gx_sw_reset>; |
| 1752 | parent-supply = <&VDD_GFX_LEVEL>; |
| 1753 | vdd_parent-supply = <&VDD_GFX_LEVEL>; |
| 1754 | qcom,reset-aon-logic; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1755 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1756 | }; |
| 1757 | |
| 1758 | /* NPU GDSC */ |
| 1759 | npu_core_gdsc: qcom,gdsc@9981004 { |
| 1760 | compatible = "qcom,gdsc"; |
| 1761 | reg = <0x9981004 0x4>; |
| 1762 | regulator-name = "npu_core_gdsc"; |
| 1763 | clock-names = "ahb_clk"; |
| 1764 | clocks = <&clock_gcc GCC_NPU_CFG_AHB_CLK>; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1765 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1766 | }; |
| 1767 | |
Jishnu Prakash | 793bf5b | 2018-11-09 16:28:55 +0530 | [diff] [blame] | 1768 | qcom,sps { |
| 1769 | compatible = "qcom,msm-sps-4k"; |
| 1770 | qcom,pipe-attr-ee; |
| 1771 | }; |
| 1772 | |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1773 | /* VIDEO_CC GDSCs */ |
| 1774 | mvs0_gdsc: qcom,gdsc@abf0d18 { |
| 1775 | compatible = "qcom,gdsc"; |
| 1776 | reg = <0xabf0d18 0x4>; |
| 1777 | regulator-name = "mvs0_gdsc"; |
| 1778 | clock-names = "ahb_clk"; |
| 1779 | clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
| 1780 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1781 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1782 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1783 | }; |
| 1784 | |
| 1785 | mvs0c_gdsc: qcom,gdsc@abf0bf8 { |
| 1786 | compatible = "qcom,gdsc"; |
| 1787 | reg = <0xabf0bf8 0x4>; |
| 1788 | regulator-name = "mvs0c_gdsc"; |
| 1789 | clock-names = "ahb_clk"; |
| 1790 | clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
| 1791 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1792 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1793 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1794 | }; |
| 1795 | |
| 1796 | mvs1_gdsc: qcom,gdsc@abf0d98 { |
| 1797 | compatible = "qcom,gdsc"; |
| 1798 | reg = <0xabf0d98 0x4>; |
| 1799 | regulator-name = "mvs1_gdsc"; |
| 1800 | clock-names = "ahb_clk"; |
| 1801 | clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
| 1802 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1803 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
David Collins | 2da7dc9 | 2019-02-14 17:38:00 -0800 | [diff] [blame] | 1804 | qcom,support-hw-trigger; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1805 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1806 | }; |
| 1807 | |
| 1808 | mvs1c_gdsc: qcom,gdsc@abf0c98 { |
| 1809 | compatible = "qcom,gdsc"; |
| 1810 | reg = <0xabf0c98 0x4>; |
| 1811 | regulator-name = "mvs1c_gdsc"; |
| 1812 | clock-names = "ahb_clk"; |
| 1813 | clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
| 1814 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1815 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
David Collins | 48f6131 | 2019-02-08 15:52:55 -0800 | [diff] [blame] | 1816 | qcom,retain-regs; |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1817 | }; |
| 1818 | |
David Collins | c2c02f6 | 2018-11-05 16:23:24 -0800 | [diff] [blame] | 1819 | spmi_bus: qcom,spmi@c440000 { |
| 1820 | compatible = "qcom,spmi-pmic-arb"; |
| 1821 | reg = <0xc440000 0x1100>, |
| 1822 | <0xc600000 0x2000000>, |
| 1823 | <0xe600000 0x100000>, |
| 1824 | <0xe700000 0xa0000>, |
| 1825 | <0xc40a000 0x26000>; |
| 1826 | reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| 1827 | interrupt-names = "periph_irq"; |
Lina Iyer | 55c2249 | 2019-02-27 14:04:27 -0700 | [diff] [blame] | 1828 | interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; |
David Collins | c2c02f6 | 2018-11-05 16:23:24 -0800 | [diff] [blame] | 1829 | qcom,ee = <0>; |
| 1830 | qcom,channel = <0>; |
| 1831 | #address-cells = <2>; |
| 1832 | #size-cells = <0>; |
| 1833 | interrupt-controller; |
| 1834 | #interrupt-cells = <4>; |
| 1835 | cell-index = <0>; |
| 1836 | }; |
| 1837 | |
Zhen Kong | 833f534 | 2019-03-04 14:39:40 -0800 | [diff] [blame] | 1838 | ufs_ice: ufsice@1d90000 { |
| 1839 | compatible = "qcom,ice"; |
| 1840 | reg = <0x1d90000 0x8000>; |
| 1841 | qcom,enable-ice-clk; |
| 1842 | clock-names = "ufs_core_clk", "bus_clk", |
| 1843 | "iface_clk", "ice_core_clk"; |
| 1844 | clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, |
| 1845 | <&clock_gcc GCC_UFS_1X_CLKREF_EN>, |
| 1846 | <&clock_gcc GCC_UFS_PHY_AHB_CLK>, |
| 1847 | <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>; |
| 1848 | qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; |
| 1849 | vdd-hba-supply = <&ufs_phy_gdsc>; |
| 1850 | qcom,msm-bus,name = "ufs_ice_noc"; |
| 1851 | qcom,msm-bus,num-cases = <2>; |
| 1852 | qcom,msm-bus,num-paths = <1>; |
| 1853 | qcom,msm-bus,vectors-KBps = |
| 1854 | <1 650 0 0>, /* No vote */ |
| 1855 | <1 650 1000 0>; /* Max. bandwidth */ |
| 1856 | qcom,bus-vector-names = "MIN", |
| 1857 | "MAX"; |
| 1858 | qcom,instance-type = "ufs"; |
| 1859 | }; |
| 1860 | |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1861 | ufsphy_mem: ufsphy_mem@1d87000 { |
| 1862 | reg = <0x1d87000 0xe00>; /* PHY regs */ |
| 1863 | reg-names = "phy_mem"; |
| 1864 | #phy-cells = <0>; |
Zhen Kong | 833f534 | 2019-03-04 14:39:40 -0800 | [diff] [blame] | 1865 | ufs-qcom-crypto = <&ufs_ice>; |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1866 | |
| 1867 | lanes-per-direction = <2>; |
| 1868 | |
| 1869 | clock-names = "ref_clk_src", |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1870 | "ref_aux_clk"; |
| 1871 | clocks = <&clock_rpmh RPMH_CXO_CLK>, |
Can Guo | a176c21 | 2019-02-18 14:47:19 +0800 | [diff] [blame] | 1872 | <&clock_gcc GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK>; |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1873 | |
| 1874 | status = "disabled"; |
| 1875 | }; |
| 1876 | |
| 1877 | ufshc_mem: ufshc@1d84000 { |
| 1878 | compatible = "qcom,ufshc"; |
| 1879 | reg = <0x1d84000 0x3000>; |
| 1880 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; |
| 1881 | phys = <&ufsphy_mem>; |
| 1882 | phy-names = "ufsphy"; |
Zhen Kong | 833f534 | 2019-03-04 14:39:40 -0800 | [diff] [blame] | 1883 | ufs-qcom-crypto = <&ufs_ice>; |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1884 | |
| 1885 | lanes-per-direction = <2>; |
| 1886 | dev-ref-clk-freq = <0>; /* 19.2 MHz */ |
| 1887 | |
| 1888 | clock-names = |
| 1889 | "core_clk", |
| 1890 | "bus_aggr_clk", |
| 1891 | "iface_clk", |
| 1892 | "core_clk_unipro", |
| 1893 | "core_clk_ice", |
| 1894 | "ref_clk", |
| 1895 | "tx_lane0_sync_clk", |
| 1896 | "rx_lane0_sync_clk", |
| 1897 | "rx_lane1_sync_clk"; |
| 1898 | clocks = |
Can Guo | a176c21 | 2019-02-18 14:47:19 +0800 | [diff] [blame] | 1899 | <&clock_gcc GCC_UFS_PHY_AXI_HW_CTL_CLK>, |
| 1900 | <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK>, |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1901 | <&clock_gcc GCC_UFS_PHY_AHB_CLK>, |
Can Guo | a176c21 | 2019-02-18 14:47:19 +0800 | [diff] [blame] | 1902 | <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK>, |
| 1903 | <&clock_gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>, |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1904 | <&clock_rpmh RPMH_CXO_CLK>, |
| 1905 | <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, |
| 1906 | <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, |
| 1907 | <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; |
| 1908 | freq-table-hz = |
| 1909 | <37500000 300000000>, |
| 1910 | <0 0>, |
| 1911 | <0 0>, |
| 1912 | <37500000 300000000>, |
Can Guo | a176c21 | 2019-02-18 14:47:19 +0800 | [diff] [blame] | 1913 | <37500000 300000000>, |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1914 | <0 0>, |
| 1915 | <0 0>, |
| 1916 | <0 0>, |
| 1917 | <0 0>; |
| 1918 | |
| 1919 | qcom,msm-bus,name = "ufshc_mem"; |
Bao D. Nguyen | 5c20872 | 2019-02-01 11:03:41 -0800 | [diff] [blame] | 1920 | qcom,msm-bus,num-cases = <26>; |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1921 | qcom,msm-bus,num-paths = <2>; |
| 1922 | qcom,msm-bus,vectors-KBps = |
| 1923 | /* |
| 1924 | * During HS G3 UFS runs at nominal voltage corner, vote |
| 1925 | * higher bandwidth to push other buses in the data path |
| 1926 | * to run at nominal to achieve max throughput. |
| 1927 | * 4GBps pushes BIMC to run at nominal. |
| 1928 | * 200MBps pushes CNOC to run at nominal. |
| 1929 | * Vote for half of this bandwidth for HS G3 1-lane. |
| 1930 | * For max bandwidth, vote high enough to push the buses |
| 1931 | * to run in turbo voltage corner. |
| 1932 | */ |
| 1933 | <123 512 0 0>, <1 757 0 0>, /* No vote */ |
| 1934 | <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */ |
| 1935 | <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */ |
| 1936 | <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */ |
| 1937 | <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */ |
| 1938 | <123 512 1844 0>, <1 757 1000 0>, /* PWM G1 L2 */ |
| 1939 | <123 512 3688 0>, <1 757 1000 0>, /* PWM G2 L2 */ |
| 1940 | <123 512 7376 0>, <1 757 1000 0>, /* PWM G3 L2 */ |
| 1941 | <123 512 14752 0>, <1 757 1000 0>, /* PWM G4 L2 */ |
| 1942 | <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */ |
| 1943 | <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */ |
| 1944 | <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */ |
Bao D. Nguyen | 5c20872 | 2019-02-01 11:03:41 -0800 | [diff] [blame] | 1945 | <123 512 4194304 0>, <1 757 204800 0>, /* HS G4 RA */ |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1946 | <123 512 255591 0>, <1 757 1000 0>, /* HS G1 RA L2 */ |
| 1947 | <123 512 511181 0>, <1 757 1000 0>, /* HS G2 RA L2 */ |
| 1948 | <123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */ |
Bao D. Nguyen | 5c20872 | 2019-02-01 11:03:41 -0800 | [diff] [blame] | 1949 | <123 512 8388608 0>, <1 757 409600 0>, /* HS G4 RA L2 */ |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1950 | <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */ |
| 1951 | <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */ |
| 1952 | <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */ |
Bao D. Nguyen | 5c20872 | 2019-02-01 11:03:41 -0800 | [diff] [blame] | 1953 | <123 512 4194304 0>, <1 757 204800 0>, /* HS G4 RB */ |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1954 | <123 512 298189 0>, <1 757 1000 0>, /* HS G1 RB L2 */ |
| 1955 | <123 512 596378 0>, <1 757 1000 0>, /* HS G2 RB L2 */ |
| 1956 | /* As UFS working in HS G3 RB L2 mode, aggregated |
| 1957 | * bandwidth (AB) should take care of providing |
| 1958 | * optimum throughput requested. However, as tested, |
| 1959 | * in order to scale up CNOC clock, instantaneous |
| 1960 | * bindwidth (IB) needs to be given a proper value too. |
| 1961 | */ |
| 1962 | <123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */ |
Bao D. Nguyen | 5c20872 | 2019-02-01 11:03:41 -0800 | [diff] [blame] | 1963 | <123 512 8388608 0>, <1 757 409600 409600>, /* HS G4 RB L2 */ |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1964 | <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */ |
| 1965 | |
| 1966 | qcom,bus-vector-names = "MIN", |
| 1967 | "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", |
| 1968 | "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", |
Bao D. Nguyen | 5c20872 | 2019-02-01 11:03:41 -0800 | [diff] [blame] | 1969 | "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", |
| 1970 | "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", |
| 1971 | "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", |
| 1972 | "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", |
| 1973 | |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1974 | "MAX"; |
| 1975 | |
| 1976 | /* PM QoS */ |
| 1977 | qcom,pm-qos-cpu-groups = <0x0f 0xf0>; |
| 1978 | qcom,pm-qos-cpu-group-latency-us = <44 44>; |
| 1979 | qcom,pm-qos-default-cpu = <0>; |
| 1980 | |
| 1981 | pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; |
| 1982 | pinctrl-0 = <&ufs_dev_reset_assert>; |
| 1983 | pinctrl-1 = <&ufs_dev_reset_deassert>; |
| 1984 | |
| 1985 | resets = <&clock_gcc GCC_UFS_PHY_BCR>; |
| 1986 | reset-names = "core_reset"; |
| 1987 | |
| 1988 | status = "disabled"; |
| 1989 | }; |
| 1990 | |
Bao D. Nguyen | bd2335b | 2019-01-17 13:32:42 -0800 | [diff] [blame] | 1991 | sdhc_2: sdhci@8804000 { |
| 1992 | compatible = "qcom,sdhci-msm-v5"; |
| 1993 | reg = <0x8804000 0x1000>; |
| 1994 | reg-names = "hc_mem"; |
| 1995 | |
| 1996 | interrupts = <0 204 0>, <0 222 0>; |
| 1997 | interrupt-names = "hc_irq", "pwr_irq"; |
| 1998 | |
| 1999 | qcom,bus-width = <4>; |
| 2000 | qcom,large-address-bus; |
| 2001 | |
| 2002 | qcom,msm-bus,name = "sdhc2"; |
| 2003 | qcom,msm-bus,num-cases = <8>; |
| 2004 | qcom,msm-bus,num-paths = <2>; |
| 2005 | qcom,msm-bus,vectors-KBps = |
| 2006 | /* No vote */ |
| 2007 | <81 512 0 0>, <1 608 0 0>, |
| 2008 | /* 400 KB/s*/ |
| 2009 | <81 512 1046 1600>, |
| 2010 | <1 608 1600 1600>, |
| 2011 | /* 20 MB/s */ |
| 2012 | <81 512 52286 80000>, |
| 2013 | <1 608 80000 80000>, |
| 2014 | /* 25 MB/s */ |
| 2015 | <81 512 65360 100000>, |
| 2016 | <1 608 100000 100000>, |
| 2017 | /* 50 MB/s */ |
| 2018 | <81 512 130718 200000>, |
| 2019 | <1 608 133320 133320>, |
| 2020 | /* 100 MB/s */ |
| 2021 | <81 512 261438 200000>, |
| 2022 | <1 608 150000 150000>, |
| 2023 | /* 200 MB/s */ |
| 2024 | <81 512 261438 400000>, |
| 2025 | <1 608 300000 300000>, |
| 2026 | /* Max. bandwidth */ |
| 2027 | <81 512 1338562 4096000>, |
| 2028 | <1 608 1338562 4096000>; |
| 2029 | qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 |
| 2030 | 100750000 200000000 4294967295>; |
| 2031 | |
| 2032 | qcom,restore-after-cx-collapse; |
| 2033 | |
| 2034 | qcom,clk-rates = <400000 20000000 25000000 |
| 2035 | 50000000 100000000 201500000>; |
| 2036 | qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", |
| 2037 | "SDR104"; |
| 2038 | |
| 2039 | qcom,devfreq,freq-table = <50000000 201500000>; |
| 2040 | clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>, |
| 2041 | <&clock_gcc GCC_SDCC2_APPS_CLK>; |
| 2042 | clock-names = "iface_clk", "core_clk"; |
| 2043 | |
| 2044 | /* PM QoS */ |
| 2045 | qcom,pm-qos-irq-type = "affine_irq"; |
| 2046 | qcom,pm-qos-irq-latency = <44 44>; |
| 2047 | qcom,pm-qos-cpu-groups = <0x3f 0xc0>; |
| 2048 | qcom,pm-qos-legacy-latency-us = <44 44>, <44 44>; |
| 2049 | |
| 2050 | status = "disabled"; |
| 2051 | }; |
| 2052 | |
Raghavendra Rao Ananta | 0295796 | 2018-08-06 15:28:34 -0700 | [diff] [blame] | 2053 | ipcc_mproc: qcom,ipcc@408000 { |
Neeraj Upadhyay | 5d7531f | 2019-01-16 10:25:24 -0800 | [diff] [blame] | 2054 | compatible = "qcom,ipcc"; |
Raghavendra Rao Ananta | 0295796 | 2018-08-06 15:28:34 -0700 | [diff] [blame] | 2055 | reg = <0x408000 0x1000>; |
| 2056 | interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; |
| 2057 | interrupt-controller; |
| 2058 | #interrupt-cells = <3>; |
| 2059 | #mbox-cells = <2>; |
| 2060 | }; |
Lina Iyer | ea91c72 | 2018-06-20 14:58:05 -0600 | [diff] [blame] | 2061 | |
Raghavendra Rao Ananta | 5da54b3 | 2018-08-09 10:04:50 -0700 | [diff] [blame] | 2062 | ipcc_self_ping: ipcc-self-ping { |
| 2063 | compatible = "qcom,ipcc-self-ping"; |
| 2064 | interrupts-extended = <&ipcc_mproc IPCC_CLIENT_APSS |
| 2065 | IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_LEVEL_HIGH>; |
| 2066 | mboxes = <&ipcc_mproc IPCC_CLIENT_APSS IPCC_MPROC_SIGNAL_SMP2P>; |
| 2067 | }; |
| 2068 | |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 2069 | apps_rsc: rsc@18200000 { |
Lina Iyer | ea91c72 | 2018-06-20 14:58:05 -0600 | [diff] [blame] | 2070 | label = "apps_rsc"; |
| 2071 | compatible = "qcom,rpmh-rsc"; |
| 2072 | reg = <0x18200000 0x10000>, |
| 2073 | <0x18210000 0x10000>, |
| 2074 | <0x18220000 0x10000>; |
| 2075 | reg-names = "drv-0", "drv-1", "drv-2"; |
| 2076 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
| 2077 | <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| 2078 | <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| 2079 | qcom,tcs-offset = <0xd00>; |
| 2080 | qcom,drv-id = <2>; |
| 2081 | qcom,tcs-config = <ACTIVE_TCS 2>, |
| 2082 | <SLEEP_TCS 3>, |
| 2083 | <WAKE_TCS 3>, |
| 2084 | <CONTROL_TCS 1>; |
David Dai | 07c8d4e | 2018-10-09 14:22:06 -0700 | [diff] [blame] | 2085 | |
| 2086 | msm_bus_apps_rsc { |
| 2087 | compatible = "qcom,msm-bus-rsc"; |
| 2088 | qcom,msm-bus-id = <MSM_BUS_RSC_APPS>; |
| 2089 | }; |
Arjun Bagla | 76f02ef | 2018-09-19 10:00:29 -0700 | [diff] [blame] | 2090 | |
| 2091 | system_pm { |
| 2092 | compatible = "qcom,system-pm"; |
| 2093 | }; |
David Dai | ee6a9d6 | 2019-01-10 17:14:04 -0800 | [diff] [blame] | 2094 | |
| 2095 | clock_rpmh: qcom,rpmhclk { |
| 2096 | compatible = "qcom,kona-rpmh-clk"; |
| 2097 | #clock-cells = <1>; |
| 2098 | }; |
Lina Iyer | ea91c72 | 2018-06-20 14:58:05 -0600 | [diff] [blame] | 2099 | }; |
| 2100 | |
| 2101 | disp_rsc: rsc@af20000 { |
| 2102 | label = "disp_rsc"; |
| 2103 | compatible = "qcom,rpmh-rsc"; |
| 2104 | reg = <0xaf20000 0x10000>; |
| 2105 | reg-names = "drv-0"; |
| 2106 | interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; |
| 2107 | qcom,tcs-offset = <0x1c00>; |
| 2108 | qcom,drv-id = <0>; |
| 2109 | qcom,tcs-config = <ACTIVE_TCS 0>, |
| 2110 | <SLEEP_TCS 1>, |
| 2111 | <WAKE_TCS 1>, |
| 2112 | <CONTROL_TCS 0>; |
| 2113 | status = "disabled"; |
Dhaval Patel | f92536a | 2018-10-24 13:19:15 -0700 | [diff] [blame] | 2114 | |
David Dai | aa2197d | 2019-02-12 10:32:43 -0800 | [diff] [blame] | 2115 | msm_bus_disp_rsc { |
| 2116 | compatible = "qcom,msm-bus-rsc"; |
| 2117 | qcom,msm-bus-id = <MSM_BUS_RSC_DISP>; |
| 2118 | status = "disabled"; |
| 2119 | }; |
| 2120 | |
Dhaval Patel | f92536a | 2018-10-24 13:19:15 -0700 | [diff] [blame] | 2121 | sde_rsc_rpmh { |
| 2122 | compatible = "qcom,sde-rsc-rpmh"; |
| 2123 | cell-index = <0>; |
| 2124 | status = "disabled"; |
| 2125 | }; |
Lina Iyer | ea91c72 | 2018-06-20 14:58:05 -0600 | [diff] [blame] | 2126 | }; |
Chris Lew | 86f6bde | 2018-09-06 16:40:39 -0700 | [diff] [blame] | 2127 | |
| 2128 | tcsr_mutex_block: syscon@1f40000 { |
| 2129 | compatible = "syscon"; |
| 2130 | reg = <0x1f40000 0x20000>; |
| 2131 | }; |
| 2132 | |
| 2133 | tcsr_mutex: hwlock { |
| 2134 | compatible = "qcom,tcsr-mutex"; |
| 2135 | syscon = <&tcsr_mutex_block 0 0x1000>; |
| 2136 | #hwlock-cells = <1>; |
| 2137 | }; |
| 2138 | |
| 2139 | smem: qcom,smem { |
| 2140 | compatible = "qcom,smem"; |
| 2141 | memory-region = <&smem_mem>; |
| 2142 | hwlocks = <&tcsr_mutex 3>; |
| 2143 | }; |
Venkata Narendra Kumar Gutta | 1781e56 | 2018-10-09 14:44:10 -0700 | [diff] [blame] | 2144 | |
| 2145 | kryo-erp { |
| 2146 | compatible = "arm,arm64-kryo-cpu-erp"; |
| 2147 | interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 2148 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| 2149 | interrupt-names = "l1-l2-faultirq", |
| 2150 | "l3-scu-faultirq"; |
| 2151 | }; |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 2152 | |
Chris Lew | 3b1f098 | 2018-10-05 17:28:21 -0700 | [diff] [blame] | 2153 | sp_scsr: mailbox@188501c { |
| 2154 | compatible = "qcom,kona-spcs-global"; |
| 2155 | reg = <0x188501c 0x4>; |
| 2156 | |
| 2157 | #mbox-cells = <1>; |
| 2158 | }; |
| 2159 | |
| 2160 | sp_scsr_block: syscon@1880000 { |
| 2161 | compatible = "syscon"; |
| 2162 | reg = <0x1880000 0x10000>; |
| 2163 | }; |
| 2164 | |
| 2165 | intsp: qcom,qsee_irq { |
| 2166 | compatible = "qcom,kona-qsee-irq"; |
| 2167 | |
| 2168 | syscon = <&sp_scsr_block>; |
| 2169 | interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>, |
| 2170 | <0 349 IRQ_TYPE_LEVEL_HIGH>; |
| 2171 | |
| 2172 | interrupt-names = "sp_ipc0", |
| 2173 | "sp_ipc1"; |
| 2174 | |
| 2175 | interrupt-controller; |
| 2176 | #interrupt-cells = <3>; |
| 2177 | }; |
| 2178 | |
| 2179 | qcom,qsee_irq_bridge { |
| 2180 | compatible = "qcom,qsee-ipc-irq-bridge"; |
| 2181 | |
| 2182 | qcom,qsee-ipc-irq-spss { |
| 2183 | qcom,dev-name = "qsee_ipc_irq_spss"; |
| 2184 | label = "spss"; |
| 2185 | interrupt-parent = <&intsp>; |
| 2186 | interrupts = <1 0 IRQ_TYPE_LEVEL_HIGH>; |
| 2187 | }; |
| 2188 | }; |
| 2189 | |
Amir Samuelov | e4c0434 | 2019-01-17 13:25:02 +0200 | [diff] [blame] | 2190 | spss_utils: qcom,spss_utils { |
| 2191 | compatible = "qcom,spss-utils"; |
| 2192 | /* spss fuses physical address */ |
Mor Ohana | 7af12db | 2019-02-20 09:33:12 +0200 | [diff] [blame] | 2193 | qcom,spss-fuse1-addr = <0x00780234>; |
Amir Samuelov | e4c0434 | 2019-01-17 13:25:02 +0200 | [diff] [blame] | 2194 | qcom,spss-fuse1-bit = <27>; |
Mor Ohana | 7af12db | 2019-02-20 09:33:12 +0200 | [diff] [blame] | 2195 | qcom,spss-fuse2-addr = <0x00780234>; |
Amir Samuelov | e4c0434 | 2019-01-17 13:25:02 +0200 | [diff] [blame] | 2196 | qcom,spss-fuse2-bit = <26>; |
| 2197 | qcom,spss-dev-firmware-name = "spss1d"; /* 8 chars max */ |
| 2198 | qcom,spss-test-firmware-name = "spss1t"; /* 8 chars max */ |
| 2199 | qcom,spss-prod-firmware-name = "spss1p"; /* 8 chars max */ |
| 2200 | qcom,spss-debug-reg-addr = <0x01886020>; |
| 2201 | qcom,spss-emul-type-reg-addr = <0x01fc8004>; |
| 2202 | status = "ok"; |
| 2203 | }; |
| 2204 | |
| 2205 | qcom,spcom { |
| 2206 | compatible = "qcom,spcom"; |
| 2207 | |
| 2208 | /* predefined channels, remote side is server */ |
| 2209 | qcom,spcom-ch-names = "sp_kernel", "sp_ssr"; |
| 2210 | status = "ok"; |
| 2211 | }; |
| 2212 | |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2213 | qcom,msm_gsi { |
| 2214 | compatible = "qcom,msm_gsi"; |
| 2215 | }; |
| 2216 | |
| 2217 | qcom,rmnet-ipa { |
| 2218 | compatible = "qcom,rmnet-ipa3"; |
| 2219 | qcom,rmnet-ipa-ssr; |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2220 | qcom,ipa-advertise-sg-support; |
| 2221 | qcom,ipa-napi-enable; |
| 2222 | }; |
| 2223 | |
| 2224 | qcom,ipa_fws { |
| 2225 | compatible = "qcom,pil-tz-generic"; |
| 2226 | qcom,pas-id = <0xf>; |
| 2227 | qcom,firmware-name = "ipa_fws"; |
| 2228 | qcom,pil-force-shutdown; |
Amir Levy | 69bdbc4 | 2019-01-31 15:40:18 +0200 | [diff] [blame] | 2229 | memory-region = <&pil_ipa_gsi_mem>; |
| 2230 | }; |
| 2231 | |
| 2232 | qcom,ipa_uc { |
| 2233 | compatible = "qcom,pil-tz-generic"; |
| 2234 | qcom,pas-id = <0x1B>; |
| 2235 | qcom,firmware-name = "ipa_uc"; |
| 2236 | qcom,pil-force-shutdown; |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2237 | memory-region = <&pil_ipa_fw_mem>; |
| 2238 | }; |
| 2239 | |
| 2240 | ipa_hw: qcom,ipa@1e00000 { |
| 2241 | compatible = "qcom,ipa"; |
Michael Adisumarta | 33e334f | 2019-03-20 11:57:29 -0700 | [diff] [blame] | 2242 | mboxes = <&qmp_aop 0>; |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2243 | reg = |
| 2244 | <0x1e00000 0x84000>, |
| 2245 | <0x1e04000 0x23000>; |
| 2246 | reg-names = "ipa-base", "gsi-base"; |
| 2247 | interrupts = |
| 2248 | <0 311 IRQ_TYPE_LEVEL_HIGH>, |
| 2249 | <0 432 IRQ_TYPE_LEVEL_HIGH>; |
| 2250 | interrupt-names = "ipa-irq", "gsi-irq"; |
| 2251 | qcom,ipa-hw-ver = <17>; /* IPA core version = IPAv4.5 */ |
| 2252 | qcom,ipa-hw-mode = <0>; |
Ghanim Fodi | f8dcdbf | 2018-11-04 17:58:22 +0200 | [diff] [blame] | 2253 | qcom,platform-type = <2>; /* APQ platform */ |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2254 | qcom,ee = <0>; |
| 2255 | qcom,use-ipa-tethering-bridge; |
| 2256 | qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */ |
| 2257 | qcom,modem-cfg-emb-pipe-flt; |
Ghanim Fodi | 03a999c | 2019-02-18 18:43:31 +0200 | [diff] [blame] | 2258 | qcom,ipa-wdi3-over-gsi; |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2259 | qcom,use-ipa-pm; |
Michael Adisumarta | 039e292 | 2019-02-19 20:18:40 -0800 | [diff] [blame] | 2260 | qcom,arm-smmu; |
| 2261 | qcom,smmu-fast-map; |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2262 | qcom,bandwidth-vote-for-ipa; |
| 2263 | qcom,use-64-bit-dma-mask; |
| 2264 | qcom,msm-bus,name = "ipa"; |
| 2265 | qcom,msm-bus,num-cases = <5>; |
Michael Adisumarta | 039e292 | 2019-02-19 20:18:40 -0800 | [diff] [blame] | 2266 | qcom,msm-bus,num-paths = <5>; |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2267 | qcom,msm-bus,vectors-KBps = |
| 2268 | /* No vote */ |
Michael Adisumarta | 039e292 | 2019-02-19 20:18:40 -0800 | [diff] [blame] | 2269 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 0 0>, |
| 2270 | <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 0 0>, |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2271 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>, |
| 2272 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>, |
| 2273 | <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 0>, |
| 2274 | |
| 2275 | /* SVS2 */ |
Michael Adisumarta | 039e292 | 2019-02-19 20:18:40 -0800 | [diff] [blame] | 2276 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 150000 600000>, |
| 2277 | <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 150000 1804000>, |
| 2278 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 75000 300000>, |
| 2279 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 76800>, |
| 2280 | <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 150>, |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2281 | |
| 2282 | /* SVS */ |
Michael Adisumarta | 039e292 | 2019-02-19 20:18:40 -0800 | [diff] [blame] | 2283 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 625000 1200000>, |
| 2284 | <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 625000 3072000>, |
| 2285 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 312500 700000>, |
| 2286 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 150000>, |
| 2287 | <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 240>, |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2288 | |
| 2289 | /* NOMINAL */ |
Michael Adisumarta | 039e292 | 2019-02-19 20:18:40 -0800 | [diff] [blame] | 2290 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 1250000 2400000>, |
| 2291 | <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 1250000 6220800>, |
| 2292 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 625000 1500000>, |
| 2293 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 400000>, |
| 2294 | <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 466>, |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2295 | |
| 2296 | /* TURBO */ |
Michael Adisumarta | 039e292 | 2019-02-19 20:18:40 -0800 | [diff] [blame] | 2297 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 2000000 3500000>, |
| 2298 | <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 2000000 7219200>, |
| 2299 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 1000000 1920000>, |
| 2300 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 400000>, |
| 2301 | <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 533>; |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2302 | |
| 2303 | qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", |
| 2304 | "TURBO"; |
Michael Adisumarta | 039e292 | 2019-02-19 20:18:40 -0800 | [diff] [blame] | 2305 | qcom,throughput-threshold = <600 2500 5000>; |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2306 | qcom,scaling-exceptions = <>; |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2307 | |
Jennifer L. Zenner | 718a8ca | 2019-01-31 12:24:21 -0500 | [diff] [blame] | 2308 | qcom,entire-ipa-block-size = <0x100000>; |
| 2309 | qcom,register-collection-on-crash; |
| 2310 | qcom,testbus-collection-on-crash; |
| 2311 | qcom,non-tn-collection-on-crash; |
Perry Randise | f912c79 | 2019-02-27 11:10:24 -0500 | [diff] [blame] | 2312 | qcom,secure-debug-check-action = <0>; |
Jennifer L. Zenner | 718a8ca | 2019-01-31 12:24:21 -0500 | [diff] [blame] | 2313 | |
Michael Adisumarta | 039e292 | 2019-02-19 20:18:40 -0800 | [diff] [blame] | 2314 | ipa_smmu_ap: ipa_smmu_ap { |
| 2315 | compatible = "qcom,ipa-smmu-ap-cb"; |
| 2316 | iommus = <&apps_smmu 0x5C0 0x0>; |
| 2317 | qcom,iova-mapping = <0x20000000 0x40000000>; |
| 2318 | qcom,additional-mapping = |
| 2319 | /* modem tables in IMEM */ |
| 2320 | <0x146BD000 0x146BD000 0x2000>; |
| 2321 | dma-coherent; |
| 2322 | qcom,iommu-dma = "disabled"; |
| 2323 | }; |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2324 | |
Michael Adisumarta | 039e292 | 2019-02-19 20:18:40 -0800 | [diff] [blame] | 2325 | ipa_smmu_wlan: ipa_smmu_wlan { |
| 2326 | compatible = "qcom,ipa-smmu-wlan-cb"; |
| 2327 | iommus = <&apps_smmu 0x5C1 0x0>; |
| 2328 | qcom,iommu-dma = "disabled"; |
| 2329 | }; |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2330 | |
Michael Adisumarta | 039e292 | 2019-02-19 20:18:40 -0800 | [diff] [blame] | 2331 | ipa_smmu_uc: ipa_smmu_uc { |
| 2332 | compatible = "qcom,ipa-smmu-uc-cb"; |
| 2333 | iommus = <&apps_smmu 0x5C2 0x0>; |
| 2334 | qcom,iova-mapping = <0x40000000 0x20000000>; |
| 2335 | qcom,iommu-dma = "disabled"; |
| 2336 | }; |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 2337 | }; |
| 2338 | |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 2339 | qcom,glink { |
| 2340 | compatible = "qcom,glink"; |
| 2341 | #address-cells = <1>; |
| 2342 | #size-cells = <1>; |
| 2343 | ranges; |
| 2344 | |
Chris Lew | b2da048 | 2018-11-16 14:50:31 -0800 | [diff] [blame] | 2345 | glink_npu: npu { |
| 2346 | qcom,remote-pid = <10>; |
| 2347 | transport = "smem"; |
| 2348 | mboxes = <&ipcc_mproc IPCC_CLIENT_NPU |
| 2349 | IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| 2350 | mbox-names = "npu_smem"; |
| 2351 | interrupt-parent = <&ipcc_mproc>; |
| 2352 | interrupts = <IPCC_CLIENT_NPU |
| 2353 | IPCC_MPROC_SIGNAL_GLINK_QMP |
| 2354 | IRQ_TYPE_EDGE_RISING>; |
| 2355 | |
| 2356 | label = "npu"; |
| 2357 | qcom,glink-label = "npu"; |
| 2358 | |
| 2359 | qcom,npu_qrtr { |
Chris Lew | c386112 | 2018-12-14 18:26:01 -0800 | [diff] [blame] | 2360 | qcom,net-id = <1>; |
Chris Lew | b2da048 | 2018-11-16 14:50:31 -0800 | [diff] [blame] | 2361 | qcom,glink-channels = "IPCRTR"; |
| 2362 | qcom,intents = <0x800 5 |
| 2363 | 0x2000 3 |
| 2364 | 0x4400 2>; |
| 2365 | }; |
| 2366 | |
| 2367 | qcom,npu_glink_ssr { |
| 2368 | qcom,glink-channels = "glink_ssr"; |
| 2369 | qcom,notify-edges = <&glink_cdsp>; |
| 2370 | }; |
| 2371 | }; |
| 2372 | |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 2373 | glink_adsp: adsp { |
| 2374 | qcom,remote-pid = <2>; |
| 2375 | transport = "smem"; |
| 2376 | mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS |
| 2377 | IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| 2378 | mbox-names = "adsp_smem"; |
| 2379 | interrupt-parent = <&ipcc_mproc>; |
| 2380 | interrupts = <IPCC_CLIENT_LPASS |
| 2381 | IPCC_MPROC_SIGNAL_GLINK_QMP |
| 2382 | IRQ_TYPE_EDGE_RISING>; |
| 2383 | |
| 2384 | label = "adsp"; |
| 2385 | qcom,glink-label = "lpass"; |
| 2386 | |
| 2387 | qcom,adsp_qrtr { |
Chris Lew | c386112 | 2018-12-14 18:26:01 -0800 | [diff] [blame] | 2388 | qcom,net-id = <2>; |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 2389 | qcom,glink-channels = "IPCRTR"; |
| 2390 | qcom,intents = <0x800 5 |
| 2391 | 0x2000 3 |
| 2392 | 0x4400 2>; |
| 2393 | }; |
| 2394 | |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2395 | qcom,msm_fastrpc_rpmsg { |
| 2396 | compatible = "qcom,msm-fastrpc-rpmsg"; |
| 2397 | qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| 2398 | qcom,intents = <0x64 64>; |
| 2399 | }; |
| 2400 | |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 2401 | qcom,adsp_glink_ssr { |
| 2402 | qcom,glink-channels = "glink_ssr"; |
| 2403 | qcom,notify-edges = <&glink_slpi>, |
| 2404 | <&glink_cdsp>; |
| 2405 | }; |
| 2406 | }; |
| 2407 | |
| 2408 | glink_slpi: dsps { |
| 2409 | qcom,remote-pid = <3>; |
| 2410 | transport = "smem"; |
| 2411 | mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI |
| 2412 | IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| 2413 | mbox-names = "dsps_smem"; |
| 2414 | interrupt-parent = <&ipcc_mproc>; |
| 2415 | interrupts = <IPCC_CLIENT_SLPI |
| 2416 | IPCC_MPROC_SIGNAL_GLINK_QMP |
| 2417 | IRQ_TYPE_EDGE_RISING>; |
| 2418 | |
| 2419 | label = "slpi"; |
| 2420 | qcom,glink-label = "dsps"; |
| 2421 | |
| 2422 | qcom,slpi_qrtr { |
Chris Lew | c386112 | 2018-12-14 18:26:01 -0800 | [diff] [blame] | 2423 | qcom,net-id = <2>; |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 2424 | qcom,glink-channels = "IPCRTR"; |
| 2425 | qcom,intents = <0x800 5 |
| 2426 | 0x2000 3 |
| 2427 | 0x4400 2>; |
| 2428 | }; |
| 2429 | |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2430 | qcom,msm_fastrpc_rpmsg { |
| 2431 | compatible = "qcom,msm-fastrpc-rpmsg"; |
| 2432 | qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| 2433 | qcom,intents = <0x64 64>; |
| 2434 | }; |
| 2435 | |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 2436 | qcom,slpi_glink_ssr { |
| 2437 | qcom,glink-channels = "glink_ssr"; |
| 2438 | qcom,notify-edges = <&glink_adsp>, |
| 2439 | <&glink_cdsp>; |
| 2440 | }; |
| 2441 | }; |
| 2442 | |
| 2443 | glink_cdsp: cdsp { |
| 2444 | qcom,remote-pid = <5>; |
| 2445 | transport = "smem"; |
| 2446 | mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP |
| 2447 | IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| 2448 | mbox-names = "dsps_smem"; |
| 2449 | interrupt-parent = <&ipcc_mproc>; |
| 2450 | interrupts = <IPCC_CLIENT_CDSP |
| 2451 | IPCC_MPROC_SIGNAL_GLINK_QMP |
| 2452 | IRQ_TYPE_EDGE_RISING>; |
| 2453 | |
| 2454 | label = "cdsp"; |
| 2455 | qcom,glink-label = "cdsp"; |
| 2456 | |
| 2457 | qcom,cdsp_qrtr { |
Chris Lew | c386112 | 2018-12-14 18:26:01 -0800 | [diff] [blame] | 2458 | qcom,net-id = <1>; |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 2459 | qcom,glink-channels = "IPCRTR"; |
| 2460 | qcom,intents = <0x800 5 |
| 2461 | 0x2000 3 |
| 2462 | 0x4400 2>; |
| 2463 | }; |
| 2464 | |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2465 | qcom,msm_fastrpc_rpmsg { |
| 2466 | compatible = "qcom,msm-fastrpc-rpmsg"; |
| 2467 | qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| 2468 | qcom,intents = <0x64 64>; |
| 2469 | }; |
| 2470 | |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 2471 | qcom,cdsp_glink_ssr { |
| 2472 | qcom,glink-channels = "glink_ssr"; |
| 2473 | qcom,notify-edges = <&glink_adsp>, |
Chris Lew | b2da048 | 2018-11-16 14:50:31 -0800 | [diff] [blame] | 2474 | <&glink_slpi>, |
| 2475 | <&glink_npu>; |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 2476 | }; |
| 2477 | }; |
Chris Lew | 3b1f098 | 2018-10-05 17:28:21 -0700 | [diff] [blame] | 2478 | |
| 2479 | glink_spss: spss { |
| 2480 | qcom,remote-pid = <8>; |
| 2481 | transport = "spss"; |
| 2482 | mboxes = <&sp_scsr 0>; |
| 2483 | mbox-names = "spss_spss"; |
| 2484 | interrupt-parent = <&intsp>; |
| 2485 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; |
| 2486 | |
| 2487 | reg = <0x1885008 0x8>, |
| 2488 | <0x1885010 0x4>; |
| 2489 | reg-names = "qcom,spss-addr", |
| 2490 | "qcom,spss-size"; |
| 2491 | |
| 2492 | label = "spss"; |
| 2493 | qcom,glink-label = "spss"; |
| 2494 | }; |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 2495 | }; |
Bruce Levy | 5122a63 | 2018-09-25 15:51:37 -0700 | [diff] [blame] | 2496 | |
Chris Lew | 3cbe403 | 2018-11-30 18:57:32 -0800 | [diff] [blame] | 2497 | qmp_aop: qcom,qmp-aop@c300000 { |
| 2498 | compatible = "qcom,qmp-mbox"; |
| 2499 | mboxes = <&ipcc_mproc IPCC_CLIENT_AOP |
| 2500 | IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| 2501 | mbox-names = "aop_qmp"; |
| 2502 | interrupt-parent = <&ipcc_mproc>; |
| 2503 | interrupts = <IPCC_CLIENT_AOP |
| 2504 | IPCC_MPROC_SIGNAL_GLINK_QMP |
| 2505 | IRQ_TYPE_EDGE_RISING>; |
| 2506 | reg = <0xc300000 0x1000>; |
| 2507 | reg-names = "msgram"; |
| 2508 | |
| 2509 | label = "aop"; |
| 2510 | qcom,early-boot; |
| 2511 | priority = <0>; |
| 2512 | mbox-desc-offset = <0x0>; |
| 2513 | #mbox-cells = <1>; |
| 2514 | }; |
| 2515 | |
Lina Iyer | 01db103 | 2018-12-06 14:14:45 -0700 | [diff] [blame] | 2516 | aop-msg-client { |
| 2517 | compatible = "qcom,debugfs-qmp-client"; |
| 2518 | mboxes = <&qmp_aop 0>; |
| 2519 | mbox-names = "aop"; |
| 2520 | }; |
| 2521 | |
Venkata Narendra Kumar Gutta | bf14876 | 2019-02-08 20:33:20 -0800 | [diff] [blame] | 2522 | qcom,msm-eud@ff0000 { |
| 2523 | compatible = "qcom,msm-eud"; |
| 2524 | interrupt-names = "eud_irq"; |
Jeevan Shriram | 0d19218 | 2019-02-28 09:54:10 -0800 | [diff] [blame] | 2525 | interrupt-parent = <&pdc>; |
| 2526 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; |
Venkata Narendra Kumar Gutta | bf14876 | 2019-02-08 20:33:20 -0800 | [diff] [blame] | 2527 | reg = <0x088E0000 0x2000>, |
| 2528 | <0x088E2000 0x1000>; |
| 2529 | reg-names = "eud_base", "eud_mode_mgr2"; |
| 2530 | qcom,secure-eud-en; |
| 2531 | qcom,eud-clock-vote-req; |
| 2532 | clocks = <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_BCR>; |
| 2533 | clock-names = "eud_ahb2phy_clk"; |
| 2534 | status = "ok"; |
| 2535 | }; |
| 2536 | |
Bruce Levy | 5122a63 | 2018-09-25 15:51:37 -0700 | [diff] [blame] | 2537 | qcom,lpass@17300000 { |
| 2538 | compatible = "qcom,pil-tz-generic"; |
| 2539 | reg = <0x17300000 0x00100>; |
| 2540 | |
| 2541 | vdd_cx-supply = <&VDD_CX_LEVEL>; |
| 2542 | qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; |
| 2543 | qcom,proxy-reg-names = "vdd_cx"; |
| 2544 | |
| 2545 | clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| 2546 | clock-names = "xo"; |
| 2547 | qcom,proxy-clock-names = "xo"; |
| 2548 | |
| 2549 | qcom,pas-id = <1>; |
| 2550 | qcom,proxy-timeout-ms = <10000>; |
| 2551 | qcom,smem-id = <423>; |
| 2552 | qcom,sysmon-id = <1>; |
| 2553 | qcom,ssctl-instance-id = <0x14>; |
| 2554 | qcom,firmware-name = "adsp"; |
| 2555 | memory-region = <&pil_adsp_mem>; |
| 2556 | qcom,complete-ramdump; |
| 2557 | |
| 2558 | /* Inputs from lpass */ |
Bruce Levy | 6fa1fd5 | 2019-02-26 13:03:03 -0800 | [diff] [blame] | 2559 | interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, |
Bruce Levy | 5122a63 | 2018-09-25 15:51:37 -0700 | [diff] [blame] | 2560 | <&adsp_smp2p_in 0 0>, |
| 2561 | <&adsp_smp2p_in 2 0>, |
| 2562 | <&adsp_smp2p_in 1 0>, |
| 2563 | <&adsp_smp2p_in 3 0>; |
| 2564 | |
| 2565 | interrupt-names = "qcom,wdog", |
| 2566 | "qcom,err-fatal", |
| 2567 | "qcom,proxy-unvote", |
| 2568 | "qcom,err-ready", |
| 2569 | "qcom,stop-ack"; |
| 2570 | |
| 2571 | /* Outputs to lpass */ |
| 2572 | qcom,smem-states = <&adsp_smp2p_out 0>; |
| 2573 | qcom,smem-state-names = "qcom,force-stop"; |
| 2574 | |
| 2575 | mbox-names = "adsp-pil"; |
| 2576 | }; |
| 2577 | |
| 2578 | qcom,turing@8300000 { |
| 2579 | compatible = "qcom,pil-tz-generic"; |
| 2580 | reg = <0x8300000 0x100000>; |
| 2581 | |
| 2582 | vdd_cx-supply = <&VDD_CX_LEVEL>; |
| 2583 | qcom,proxy-reg-names = "vdd_cx"; |
| 2584 | qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; |
| 2585 | |
| 2586 | clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| 2587 | clock-names = "xo"; |
| 2588 | qcom,proxy-clock-names = "xo"; |
| 2589 | |
| 2590 | qcom,pas-id = <18>; |
| 2591 | qcom,proxy-timeout-ms = <10000>; |
| 2592 | qcom,smem-id = <601>; |
| 2593 | qcom,sysmon-id = <7>; |
| 2594 | qcom,ssctl-instance-id = <0x17>; |
| 2595 | qcom,firmware-name = "cdsp"; |
| 2596 | memory-region = <&pil_cdsp_mem>; |
| 2597 | qcom,complete-ramdump; |
| 2598 | |
| 2599 | qcom,msm-bus,name = "pil-cdsp"; |
| 2600 | qcom,msm-bus,num-cases = <2>; |
| 2601 | qcom,msm-bus,num-paths = <1>; |
| 2602 | qcom,msm-bus,vectors-KBps = |
| 2603 | <154 10070 0 0>, |
| 2604 | <154 10070 0 1>; |
| 2605 | |
| 2606 | /* Inputs from turing */ |
Bruce Levy | 821133c | 2018-11-29 11:34:45 -0800 | [diff] [blame] | 2607 | interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, |
Bruce Levy | 5122a63 | 2018-09-25 15:51:37 -0700 | [diff] [blame] | 2608 | <&cdsp_smp2p_in 0 0>, |
| 2609 | <&cdsp_smp2p_in 2 0>, |
| 2610 | <&cdsp_smp2p_in 1 0>, |
| 2611 | <&cdsp_smp2p_in 3 0>; |
| 2612 | |
| 2613 | interrupt-names = "qcom,wdog", |
| 2614 | "qcom,err-fatal", |
| 2615 | "qcom,proxy-unvote", |
| 2616 | "qcom,err-ready", |
| 2617 | "qcom,stop-ack"; |
| 2618 | |
| 2619 | /* Outputs to turing */ |
| 2620 | qcom,smem-states = <&cdsp_smp2p_out 0>; |
| 2621 | qcom,smem-state-names = "qcom,force-stop"; |
| 2622 | |
| 2623 | mbox-names = "cdsp-pil"; |
| 2624 | }; |
Akshay Chandrashekhar Kalghatgi | f7905ad | 2018-11-08 16:30:42 -0800 | [diff] [blame] | 2625 | |
| 2626 | qcom,venus@aab0000 { |
| 2627 | compatible = "qcom,pil-tz-generic"; |
| 2628 | reg = <0xaab0000 0x2000>; |
Chinmay Sawarkar | 2cfeca0 | 2018-11-15 17:59:36 -0800 | [diff] [blame] | 2629 | |
| 2630 | vdd-supply = <&mvs0c_gdsc>; |
| 2631 | qcom,proxy-reg-names = "vdd"; |
| 2632 | qcom,complete-ramdump; |
| 2633 | |
| 2634 | clocks = <&clock_videocc VIDEO_CC_XO_CLK>, |
| 2635 | <&clock_videocc VIDEO_CC_MVS0C_CLK>, |
| 2636 | <&clock_videocc VIDEO_CC_AHB_CLK>; |
| 2637 | clock-names = "xo", "core", "ahb"; |
| 2638 | qcom,proxy-clock-names = "xo", "core", "ahb"; |
| 2639 | |
Akshay Chandrashekhar Kalghatgi | f7905ad | 2018-11-08 16:30:42 -0800 | [diff] [blame] | 2640 | qcom,core-freq = <200000000>; |
| 2641 | qcom,ahb-freq = <200000000>; |
| 2642 | |
| 2643 | qcom,pas-id = <9>; |
| 2644 | qcom,msm-bus,name = "pil-venus"; |
| 2645 | qcom,msm-bus,num-cases = <2>; |
| 2646 | qcom,msm-bus,num-paths = <1>; |
| 2647 | qcom,msm-bus,vectors-KBps = |
| 2648 | <63 512 0 0>, |
| 2649 | <63 512 0 304000>; |
| 2650 | qcom,proxy-timeout-ms = <100>; |
| 2651 | qcom,firmware-name = "venus"; |
| 2652 | memory-region = <&pil_video_mem>; |
| 2653 | }; |
Tharun Kumar Merugu | b8d79dd | 2018-11-02 23:07:31 +0530 | [diff] [blame] | 2654 | |
Amir Samuelov | f52db41 | 2019-01-08 09:30:58 +0200 | [diff] [blame] | 2655 | /* PIL spss node - for loading Secure Processor */ |
| 2656 | qcom,spss@1880000 { |
| 2657 | compatible = "qcom,pil-tz-generic"; |
| 2658 | reg = <0x188101c 0x4>, |
| 2659 | <0x1881024 0x4>, |
| 2660 | <0x1881028 0x4>, |
| 2661 | <0x188103c 0x4>, |
| 2662 | <0x1882014 0x4>; |
| 2663 | reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", |
| 2664 | "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2"; |
| 2665 | interrupts = <0 352 1>; |
| 2666 | |
| 2667 | vdd_cx-supply = <&VDD_CX_LEVEL>; |
| 2668 | qcom,proxy-reg-names = "vdd_cx"; |
| 2669 | qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; |
| 2670 | vdd_mx-supply = <&VDD_MX_LEVEL>; |
| 2671 | vdd_mx-uV = <RPMH_REGULATOR_LEVEL_TURBO 100000>; |
| 2672 | |
| 2673 | clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| 2674 | clock-names = "xo"; |
| 2675 | qcom,proxy-clock-names = "xo"; |
| 2676 | qcom,pil-generic-irq-handler; |
| 2677 | status = "ok"; |
| 2678 | |
Amir Samuelov | 48955b3 | 2019-01-17 17:24:37 +0200 | [diff] [blame] | 2679 | qcom,signal-aop; |
Amir Samuelov | f52db41 | 2019-01-08 09:30:58 +0200 | [diff] [blame] | 2680 | qcom,complete-ramdump; |
| 2681 | |
| 2682 | qcom,pas-id = <14>; |
| 2683 | qcom,proxy-timeout-ms = <10000>; |
| 2684 | qcom,firmware-name = "spss"; |
| 2685 | memory-region = <&pil_spss_mem>; |
| 2686 | qcom,spss-scsr-bits = <24 25>; |
| 2687 | |
Amir Samuelov | 48955b3 | 2019-01-17 17:24:37 +0200 | [diff] [blame] | 2688 | mboxes = <&qmp_aop 0>; |
Amir Samuelov | f52db41 | 2019-01-08 09:30:58 +0200 | [diff] [blame] | 2689 | mbox-names = "spss-pil"; |
| 2690 | }; |
| 2691 | |
George Shen | 9c54c66 | 2018-12-26 15:50:11 -0800 | [diff] [blame] | 2692 | qcom,cvpss@abb0000 { |
| 2693 | compatible = "qcom,pil-tz-generic"; |
| 2694 | reg = <0xabb0000 0x2000>; |
| 2695 | status = "ok"; |
George Shen | 24f6323 | 2019-01-11 14:28:21 -0800 | [diff] [blame] | 2696 | qcom,pas-id = <26>; |
George Shen | 9c54c66 | 2018-12-26 15:50:11 -0800 | [diff] [blame] | 2697 | qcom,firmware-name = "cvpss"; |
| 2698 | |
| 2699 | memory-region = <&pil_cvp_mem>; |
| 2700 | }; |
| 2701 | |
Jilai Wang | d20a529 | 2018-12-04 11:05:10 -0500 | [diff] [blame] | 2702 | qcom,npu@9800000 { |
| 2703 | compatible = "qcom,pil-tz-generic"; |
| 2704 | reg = <0x9800000 0x800000>; |
| 2705 | |
| 2706 | status = "ok"; |
| 2707 | qcom,pas-id = <23>; |
| 2708 | qcom,firmware-name = "npu"; |
| 2709 | memory-region = <&pil_npu_mem>; |
| 2710 | }; |
| 2711 | |
Tharun Kumar Merugu | b8d79dd | 2018-11-02 23:07:31 +0530 | [diff] [blame] | 2712 | qcom,msm-cdsp-loader { |
| 2713 | compatible = "qcom,cdsp-loader"; |
| 2714 | qcom,proc-img-to-load = "cdsp"; |
| 2715 | }; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2716 | |
| 2717 | qcom,msm-adsprpc-mem { |
| 2718 | compatible = "qcom,msm-adsprpc-mem-region"; |
| 2719 | memory-region = <&adsp_mem>; |
Tharun Kumar Merugu | 9bf49d7 | 2018-12-21 02:33:10 +0530 | [diff] [blame] | 2720 | restrict-access; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2721 | }; |
| 2722 | |
| 2723 | msm_fastrpc: qcom,msm_fastrpc { |
| 2724 | compatible = "qcom,msm-fastrpc-compute"; |
Tharun Kumar Merugu | 9bf49d7 | 2018-12-21 02:33:10 +0530 | [diff] [blame] | 2725 | qcom,adsp-remoteheap-vmid = <22 37>; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2726 | qcom,fastrpc-adsp-audio-pdr; |
Tharun Kumar Merugu | 9bf49d7 | 2018-12-21 02:33:10 +0530 | [diff] [blame] | 2727 | qcom,fastrpc-adsp-sensors-pdr; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2728 | qcom,rpc-latency-us = <235>; |
| 2729 | |
| 2730 | qcom,msm_fastrpc_compute_cb1 { |
| 2731 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 2732 | label = "cdsprpc-smd"; |
| 2733 | iommus = <&apps_smmu 0x1001 0x0460>; |
Patrick Daly | 84360e1 | 2019-02-05 14:37:08 -0800 | [diff] [blame] | 2734 | qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 2735 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2736 | dma-coherent; |
| 2737 | }; |
| 2738 | |
| 2739 | qcom,msm_fastrpc_compute_cb2 { |
| 2740 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 2741 | label = "cdsprpc-smd"; |
| 2742 | iommus = <&apps_smmu 0x1002 0x0460>; |
Patrick Daly | 84360e1 | 2019-02-05 14:37:08 -0800 | [diff] [blame] | 2743 | qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 2744 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2745 | dma-coherent; |
| 2746 | }; |
| 2747 | |
| 2748 | qcom,msm_fastrpc_compute_cb3 { |
| 2749 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 2750 | label = "cdsprpc-smd"; |
| 2751 | iommus = <&apps_smmu 0x1003 0x0460>; |
Patrick Daly | 84360e1 | 2019-02-05 14:37:08 -0800 | [diff] [blame] | 2752 | qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 2753 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2754 | dma-coherent; |
| 2755 | }; |
| 2756 | |
| 2757 | qcom,msm_fastrpc_compute_cb4 { |
| 2758 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 2759 | label = "cdsprpc-smd"; |
| 2760 | iommus = <&apps_smmu 0x1004 0x0460>; |
Patrick Daly | 84360e1 | 2019-02-05 14:37:08 -0800 | [diff] [blame] | 2761 | qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 2762 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2763 | dma-coherent; |
| 2764 | }; |
| 2765 | |
| 2766 | qcom,msm_fastrpc_compute_cb5 { |
| 2767 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 2768 | label = "cdsprpc-smd"; |
| 2769 | iommus = <&apps_smmu 0x1005 0x0460>; |
Patrick Daly | 84360e1 | 2019-02-05 14:37:08 -0800 | [diff] [blame] | 2770 | qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 2771 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2772 | dma-coherent; |
| 2773 | }; |
| 2774 | |
| 2775 | qcom,msm_fastrpc_compute_cb6 { |
| 2776 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 2777 | label = "cdsprpc-smd"; |
| 2778 | iommus = <&apps_smmu 0x1006 0x0460>; |
Patrick Daly | 84360e1 | 2019-02-05 14:37:08 -0800 | [diff] [blame] | 2779 | qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 2780 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2781 | dma-coherent; |
| 2782 | }; |
| 2783 | |
| 2784 | qcom,msm_fastrpc_compute_cb7 { |
| 2785 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 2786 | label = "cdsprpc-smd"; |
| 2787 | iommus = <&apps_smmu 0x1007 0x0460>; |
Patrick Daly | 84360e1 | 2019-02-05 14:37:08 -0800 | [diff] [blame] | 2788 | qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 2789 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2790 | dma-coherent; |
| 2791 | }; |
| 2792 | |
| 2793 | qcom,msm_fastrpc_compute_cb8 { |
| 2794 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 2795 | label = "cdsprpc-smd"; |
| 2796 | iommus = <&apps_smmu 0x1008 0x0460>; |
Patrick Daly | 84360e1 | 2019-02-05 14:37:08 -0800 | [diff] [blame] | 2797 | qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 2798 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2799 | dma-coherent; |
| 2800 | }; |
| 2801 | |
| 2802 | qcom,msm_fastrpc_compute_cb9 { |
| 2803 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 2804 | label = "cdsprpc-smd"; |
| 2805 | qcom,secure-context-bank; |
| 2806 | iommus = <&apps_smmu 0x1009 0x0460>; |
Patrick Daly | 84360e1 | 2019-02-05 14:37:08 -0800 | [diff] [blame] | 2807 | qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 2808 | qcom,iommu-faults = "stall-disable"; |
| 2809 | qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2810 | dma-coherent; |
| 2811 | }; |
| 2812 | |
| 2813 | qcom,msm_fastrpc_compute_cb10 { |
| 2814 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 2815 | label = "adsprpc-smd"; |
| 2816 | iommus = <&apps_smmu 0x1803 0x0>; |
Patrick Daly | 84360e1 | 2019-02-05 14:37:08 -0800 | [diff] [blame] | 2817 | qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 2818 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2819 | dma-coherent; |
| 2820 | }; |
| 2821 | |
| 2822 | qcom,msm_fastrpc_compute_cb11 { |
| 2823 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 2824 | label = "adsprpc-smd"; |
| 2825 | iommus = <&apps_smmu 0x1804 0x0>; |
Patrick Daly | 84360e1 | 2019-02-05 14:37:08 -0800 | [diff] [blame] | 2826 | qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 2827 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2828 | dma-coherent; |
| 2829 | }; |
| 2830 | |
| 2831 | qcom,msm_fastrpc_compute_cb12 { |
| 2832 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 2833 | label = "adsprpc-smd"; |
| 2834 | iommus = <&apps_smmu 0x1805 0x0>; |
Patrick Daly | 84360e1 | 2019-02-05 14:37:08 -0800 | [diff] [blame] | 2835 | qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 2836 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2837 | dma-coherent; |
| 2838 | }; |
| 2839 | |
| 2840 | qcom,msm_fastrpc_compute_cb13 { |
| 2841 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 2842 | label = "sdsprpc-smd"; |
| 2843 | iommus = <&apps_smmu 0x0541 0x0>; |
Patrick Daly | 84360e1 | 2019-02-05 14:37:08 -0800 | [diff] [blame] | 2844 | qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 2845 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2846 | dma-coherent; |
| 2847 | }; |
| 2848 | |
| 2849 | qcom,msm_fastrpc_compute_cb14 { |
| 2850 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 2851 | label = "sdsprpc-smd"; |
| 2852 | iommus = <&apps_smmu 0x0542 0x0>; |
Patrick Daly | 84360e1 | 2019-02-05 14:37:08 -0800 | [diff] [blame] | 2853 | qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 2854 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2855 | dma-coherent; |
| 2856 | }; |
| 2857 | |
| 2858 | qcom,msm_fastrpc_compute_cb15 { |
| 2859 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 2860 | label = "sdsprpc-smd"; |
| 2861 | iommus = <&apps_smmu 0x0543 0x0>; |
Patrick Daly | 84360e1 | 2019-02-05 14:37:08 -0800 | [diff] [blame] | 2862 | qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 2863 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 2864 | shared-cb = <4>; |
| 2865 | dma-coherent; |
| 2866 | }; |
| 2867 | }; |
Shaikh Shadul | bfdfdda | 2018-11-14 15:36:21 +0530 | [diff] [blame] | 2868 | |
Tatenda Chipeperekwa | a84e1aa | 2019-01-18 17:43:45 -0800 | [diff] [blame] | 2869 | qcom_msmhdcp: qcom,msm_hdcp { |
| 2870 | compatible = "qcom,msm-hdcp"; |
| 2871 | }; |
| 2872 | |
Tingwei Zhang | d9b535f | 2018-12-03 19:14:06 -0800 | [diff] [blame] | 2873 | mem_dump { |
| 2874 | compatible = "qcom,mem-dump"; |
| 2875 | memory-region = <&dump_mem>; |
| 2876 | |
| 2877 | rpmh { |
| 2878 | qcom,dump-size = <0x2000000>; |
| 2879 | qcom,dump-id = <0xec>; |
| 2880 | }; |
| 2881 | |
| 2882 | rpm_sw { |
| 2883 | qcom,dump-size = <0x28000>; |
| 2884 | qcom,dump-id = <0xea>; |
| 2885 | }; |
| 2886 | |
| 2887 | pmic { |
| 2888 | qcom,dump-size = <0x80000>; |
| 2889 | qcom,dump-id = <0xe4>; |
| 2890 | }; |
| 2891 | |
| 2892 | fcm { |
| 2893 | qcom,dump-size = <0x8400>; |
| 2894 | qcom,dump-id = <0xee>; |
| 2895 | }; |
| 2896 | |
| 2897 | etf_swao { |
| 2898 | qcom,dump-size = <0x10000>; |
| 2899 | qcom,dump-id = <0xf1>; |
| 2900 | }; |
| 2901 | |
| 2902 | etr_reg { |
| 2903 | qcom,dump-size = <0x1000>; |
| 2904 | qcom,dump-id = <0x100>; |
| 2905 | }; |
| 2906 | |
| 2907 | etfswao_reg { |
| 2908 | qcom,dump-size = <0x1000>; |
| 2909 | qcom,dump-id = <0x102>; |
| 2910 | }; |
| 2911 | |
| 2912 | misc_data { |
| 2913 | qcom,dump-size = <0x1000>; |
| 2914 | qcom,dump-id = <0xe8>; |
| 2915 | }; |
| 2916 | }; |
| 2917 | |
Zhen Kong | 93446d2 | 2018-12-27 13:10:09 -0800 | [diff] [blame] | 2918 | qcom_tzlog: tz-log@146bf720 { |
| 2919 | compatible = "qcom,tz-log"; |
| 2920 | reg = <0x146bf720 0x3000>; |
| 2921 | qcom,hyplog-enabled; |
| 2922 | hyplog-address-offset = <0x410>; |
| 2923 | hyplog-size-offset = <0x414>; |
| 2924 | }; |
| 2925 | |
Shaikh Shadul | bfdfdda | 2018-11-14 15:36:21 +0530 | [diff] [blame] | 2926 | qcom,ssc@5c00000 { |
| 2927 | compatible = "qcom,pil-tz-generic"; |
| 2928 | reg = <0x5c00000 0x4000>; |
| 2929 | |
| 2930 | vdd_cx-supply = <&VDD_CX_LEVEL>; |
| 2931 | qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; |
| 2932 | vdd_mx-supply = <&VDD_MX_LEVEL>; |
| 2933 | qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; |
| 2934 | |
| 2935 | qcom,proxy-reg-names = "vdd_cx", "vdd_mx"; |
| 2936 | qcom,keep-proxy-regs-on; |
| 2937 | |
| 2938 | clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| 2939 | clock-names = "xo"; |
| 2940 | qcom,proxy-clock-names = "xo"; |
| 2941 | |
| 2942 | qcom,pas-id = <12>; |
| 2943 | qcom,proxy-timeout-ms = <10000>; |
| 2944 | qcom,smem-id = <424>; |
| 2945 | qcom,sysmon-id = <3>; |
| 2946 | qcom,ssctl-instance-id = <0x16>; |
| 2947 | qcom,firmware-name = "slpi"; |
| 2948 | status = "ok"; |
| 2949 | memory-region = <&pil_slpi_mem>; |
| 2950 | qcom,complete-ramdump; |
| 2951 | |
| 2952 | /* Inputs from ssc */ |
| 2953 | interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, |
| 2954 | <&dsps_smp2p_in 0 0>, |
| 2955 | <&dsps_smp2p_in 2 0>, |
| 2956 | <&dsps_smp2p_in 1 0>, |
| 2957 | <&dsps_smp2p_in 3 0>; |
| 2958 | |
| 2959 | interrupt-names = "qcom,wdog", |
| 2960 | "qcom,err-fatal", |
| 2961 | "qcom,proxy-unvote", |
| 2962 | "qcom,err-ready", |
| 2963 | "qcom,stop-ack"; |
| 2964 | |
| 2965 | /* Outputs to ssc */ |
| 2966 | qcom,smem-states = <&dsps_smp2p_out 0>; |
| 2967 | qcom,smem-state-names = "qcom,force-stop"; |
| 2968 | |
| 2969 | mbox-names = "slpi-pil"; |
| 2970 | }; |
| 2971 | |
| 2972 | ssc_sensors: qcom,msm-ssc-sensors { |
| 2973 | compatible = "qcom,msm-ssc-sensors"; |
| 2974 | status = "ok"; |
| 2975 | qcom,firmware-name = "slpi"; |
| 2976 | }; |
Siddartha Mohanadoss | 42c8d78 | 2018-12-21 14:20:33 -0800 | [diff] [blame] | 2977 | |
Zhen Kong | ec18a5f | 2019-02-13 17:24:17 -0800 | [diff] [blame] | 2978 | qcom_smcinvoke: smcinvoke@87900000 { |
| 2979 | compatible = "qcom,smcinvoke"; |
| 2980 | reg = <0x87900000 0x2200000>; |
| 2981 | reg-names = "secapp-region"; |
| 2982 | }; |
| 2983 | |
Siddartha Mohanadoss | 42c8d78 | 2018-12-21 14:20:33 -0800 | [diff] [blame] | 2984 | tsens0: tsens@c222000 { |
| 2985 | compatible = "qcom,tsens24xx"; |
| 2986 | reg = <0xc222000 0x4>, |
| 2987 | <0xc263000 0x1ff>; |
| 2988 | reg-names = "tsens_srot_physical", |
| 2989 | "tsens_tm_physical"; |
Siddartha Mohanadoss | 404a89a | 2019-01-04 15:29:48 -0800 | [diff] [blame] | 2990 | interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, |
| 2991 | <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; |
Siddartha Mohanadoss | 42c8d78 | 2018-12-21 14:20:33 -0800 | [diff] [blame] | 2992 | interrupt-names = "tsens-upper-lower", "tsens-critical"; |
| 2993 | #thermal-sensor-cells = <1>; |
| 2994 | }; |
| 2995 | |
| 2996 | tsens1: tsens@c223000 { |
| 2997 | compatible = "qcom,tsens24xx"; |
| 2998 | reg = <0xc223000 0x4>, |
| 2999 | <0xc265000 0x1ff>; |
| 3000 | reg-names = "tsens_srot_physical", |
| 3001 | "tsens_tm_physical"; |
Siddartha Mohanadoss | 404a89a | 2019-01-04 15:29:48 -0800 | [diff] [blame] | 3002 | interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, |
| 3003 | <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; |
Siddartha Mohanadoss | 42c8d78 | 2018-12-21 14:20:33 -0800 | [diff] [blame] | 3004 | interrupt-names = "tsens-upper-lower", "tsens-critical"; |
| 3005 | #thermal-sensor-cells = <1>; |
| 3006 | }; |
Rishabh Bhatnagar | f7a853a | 2018-06-28 14:14:54 -0700 | [diff] [blame] | 3007 | |
| 3008 | qcom,msm-rtb { |
| 3009 | compatible = "qcom,msm-rtb"; |
| 3010 | qcom,rtb-size = <0x100000>; |
| 3011 | }; |
| 3012 | |
| 3013 | qcom,mpm2-sleep-counter@c221000 { |
| 3014 | compatible = "qcom,mpm2-sleep-counter"; |
| 3015 | reg = <0xc221000 0x1000>; |
| 3016 | clock-frequency = <32768>; |
| 3017 | }; |
Venkata Narendra Kumar Gutta | b0205a9 | 2018-09-11 13:40:34 -0700 | [diff] [blame] | 3018 | |
| 3019 | cpuss_dump { |
| 3020 | compatible = "qcom,cpuss-dump"; |
| 3021 | |
| 3022 | qcom,l1_i_cache0 { |
| 3023 | qcom,dump-node = <&L1_I_0>; |
| 3024 | qcom,dump-id = <0x60>; |
| 3025 | }; |
| 3026 | |
| 3027 | qcom,l1_i_cache1 { |
| 3028 | qcom,dump-node = <&L1_I_100>; |
| 3029 | qcom,dump-id = <0x61>; |
| 3030 | }; |
| 3031 | |
| 3032 | qcom,l1_i_cache2 { |
| 3033 | qcom,dump-node = <&L1_I_200>; |
| 3034 | qcom,dump-id = <0x62>; |
| 3035 | }; |
| 3036 | |
| 3037 | qcom,l1_i_cache3 { |
| 3038 | qcom,dump-node = <&L1_I_300>; |
| 3039 | qcom,dump-id = <0x63>; |
| 3040 | }; |
| 3041 | |
| 3042 | qcom,l1_i_cache100 { |
| 3043 | qcom,dump-node = <&L1_I_400>; |
| 3044 | qcom,dump-id = <0x64>; |
| 3045 | }; |
| 3046 | |
| 3047 | qcom,l1_i_cache101 { |
| 3048 | qcom,dump-node = <&L1_I_500>; |
| 3049 | qcom,dump-id = <0x65>; |
| 3050 | }; |
| 3051 | |
| 3052 | qcom,l1_i_cache102 { |
| 3053 | qcom,dump-node = <&L1_I_600>; |
| 3054 | qcom,dump-id = <0x66>; |
| 3055 | }; |
| 3056 | |
| 3057 | qcom,l1_i_cache103 { |
| 3058 | qcom,dump-node = <&L1_I_700>; |
| 3059 | qcom,dump-id = <0x67>; |
| 3060 | }; |
| 3061 | |
| 3062 | qcom,l1_d_cache0 { |
| 3063 | qcom,dump-node = <&L1_D_0>; |
| 3064 | qcom,dump-id = <0x80>; |
| 3065 | }; |
| 3066 | |
| 3067 | qcom,l1_d_cache1 { |
| 3068 | qcom,dump-node = <&L1_D_100>; |
| 3069 | qcom,dump-id = <0x81>; |
| 3070 | }; |
| 3071 | |
| 3072 | qcom,l1_d_cache2 { |
| 3073 | qcom,dump-node = <&L1_D_200>; |
| 3074 | qcom,dump-id = <0x82>; |
| 3075 | }; |
| 3076 | |
| 3077 | qcom,l1_d_cache3 { |
| 3078 | qcom,dump-node = <&L1_D_300>; |
| 3079 | qcom,dump-id = <0x83>; |
| 3080 | }; |
| 3081 | |
| 3082 | qcom,l1_d_cache100 { |
| 3083 | qcom,dump-node = <&L1_D_400>; |
| 3084 | qcom,dump-id = <0x84>; |
| 3085 | }; |
| 3086 | |
| 3087 | qcom,l1_d_cache101 { |
| 3088 | qcom,dump-node = <&L1_D_500>; |
| 3089 | qcom,dump-id = <0x85>; |
| 3090 | }; |
| 3091 | |
| 3092 | qcom,l1_d_cache102 { |
| 3093 | qcom,dump-node = <&L1_D_600>; |
| 3094 | qcom,dump-id = <0x86>; |
| 3095 | }; |
| 3096 | |
| 3097 | qcom,l1_d_cache103 { |
| 3098 | qcom,dump-node = <&L1_D_700>; |
| 3099 | qcom,dump-id = <0x87>; |
| 3100 | }; |
| 3101 | |
| 3102 | qcom,l1_i_tlb_dump400 { |
| 3103 | qcom,dump-node = <&L1_ITLB_400>; |
| 3104 | qcom,dump-id = <0x24>; |
| 3105 | }; |
| 3106 | |
| 3107 | qcom,l1_i_tlb_dump500 { |
| 3108 | qcom,dump-node = <&L1_ITLB_500>; |
| 3109 | qcom,dump-id = <0x25>; |
| 3110 | }; |
| 3111 | |
| 3112 | qcom,l1_i_tlb_dump600 { |
| 3113 | qcom,dump-node = <&L1_ITLB_600>; |
| 3114 | qcom,dump-id = <0x26>; |
| 3115 | }; |
| 3116 | |
| 3117 | qcom,l1_i_tlb_dump700 { |
| 3118 | qcom,dump-node = <&L1_ITLB_700>; |
| 3119 | qcom,dump-id = <0x27>; |
| 3120 | }; |
| 3121 | |
| 3122 | qcom,l1_d_tlb_dump400 { |
| 3123 | qcom,dump-node = <&L1_DTLB_400>; |
| 3124 | qcom,dump-id = <0x44>; |
| 3125 | }; |
| 3126 | |
| 3127 | qcom,l1_d_tlb_dump500 { |
| 3128 | qcom,dump-node = <&L1_DTLB_500>; |
| 3129 | qcom,dump-id = <0x45>; |
| 3130 | }; |
| 3131 | |
| 3132 | qcom,l1_d_tlb_dump600 { |
| 3133 | qcom,dump-node = <&L1_DTLB_600>; |
| 3134 | qcom,dump-id = <0x46>; |
| 3135 | }; |
| 3136 | |
| 3137 | qcom,l1_d_tlb_dump700 { |
| 3138 | qcom,dump-node = <&L1_DTLB_700>; |
| 3139 | qcom,dump-id = <0x47>; |
| 3140 | }; |
| 3141 | |
| 3142 | qcom,l2_cache_dump400 { |
| 3143 | qcom,dump-node = <&L2_4>; |
| 3144 | qcom,dump-id = <0xc4>; |
| 3145 | }; |
| 3146 | |
| 3147 | qcom,l2_cache_dump500 { |
| 3148 | qcom,dump-node = <&L2_5>; |
| 3149 | qcom,dump-id = <0xc5>; |
| 3150 | }; |
| 3151 | |
| 3152 | qcom,l2_cache_dump600 { |
| 3153 | qcom,dump-node = <&L2_6>; |
| 3154 | qcom,dump-id = <0xc6>; |
| 3155 | }; |
| 3156 | |
| 3157 | qcom,l2_cache_dump700 { |
| 3158 | qcom,dump-node = <&L2_7>; |
| 3159 | qcom,dump-id = <0xc7>; |
| 3160 | }; |
| 3161 | |
| 3162 | qcom,l2_tlb_dump0 { |
| 3163 | qcom,dump-node = <&L2_TLB_0>; |
| 3164 | qcom,dump-id = <0x120>; |
| 3165 | }; |
| 3166 | |
| 3167 | qcom,l2_tlb_dump100 { |
| 3168 | qcom,dump-node = <&L2_TLB_100>; |
| 3169 | qcom,dump-id = <0x121>; |
| 3170 | }; |
| 3171 | |
| 3172 | qcom,l2_tlb_dump200 { |
| 3173 | qcom,dump-node = <&L2_TLB_200>; |
| 3174 | qcom,dump-id = <0x122>; |
| 3175 | }; |
| 3176 | |
| 3177 | qcom,l2_tlb_dump300 { |
| 3178 | qcom,dump-node = <&L2_TLB_300>; |
| 3179 | qcom,dump-id = <0x123>; |
| 3180 | }; |
| 3181 | |
| 3182 | qcom,l2_tlb_dump400 { |
| 3183 | qcom,dump-node = <&L2_TLB_400>; |
| 3184 | qcom,dump-id = <0x124>; |
| 3185 | }; |
| 3186 | |
| 3187 | qcom,l2_tlb_dump500 { |
| 3188 | qcom,dump-node = <&L2_TLB_500>; |
| 3189 | qcom,dump-id = <0x125>; |
| 3190 | }; |
| 3191 | |
| 3192 | qcom,l2_tlb_dump600 { |
| 3193 | qcom,dump-node = <&L2_TLB_600>; |
| 3194 | qcom,dump-id = <0x126>; |
| 3195 | }; |
| 3196 | |
| 3197 | qcom,l2_tlb_dump700 { |
| 3198 | qcom,dump-node = <&L2_TLB_700>; |
| 3199 | qcom,dump-id = <0x127>; |
| 3200 | }; |
| 3201 | }; |
Vipin Deep Kaur | 1cd6ed0 | 2018-12-27 16:23:43 +0530 | [diff] [blame] | 3202 | |
| 3203 | gpi_dma0: qcom,gpi-dma@900000 { |
| 3204 | #dma-cells = <5>; |
| 3205 | compatible = "qcom,gpi-dma"; |
| 3206 | reg = <0x900000 0x70000>; |
| 3207 | reg-names = "gpi-top"; |
Rishabh Bhatnagar | 7ef1588 | 2019-01-22 11:02:09 -0800 | [diff] [blame] | 3208 | interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, |
| 3209 | <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, |
| 3210 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, |
| 3211 | <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, |
| 3212 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, |
| 3213 | <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, |
| 3214 | <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, |
| 3215 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, |
| 3216 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, |
| 3217 | <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
| 3218 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, |
| 3219 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, |
| 3220 | <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; |
Vipin Deep Kaur | 1cd6ed0 | 2018-12-27 16:23:43 +0530 | [diff] [blame] | 3221 | qcom,max-num-gpii = <13>; |
| 3222 | qcom,gpii-mask = <0x7ff>; |
| 3223 | qcom,ev-factor = <2>; |
| 3224 | iommus = <&apps_smmu 0x5b6 0x0>; |
| 3225 | qcom,smmu-cfg = <0x1>; |
| 3226 | qcom,iova-range = <0x0 0x100000 0x0 0x100000>; |
| 3227 | status = "ok"; |
| 3228 | }; |
| 3229 | |
| 3230 | gpi_dma1: qcom,gpi-dma@a00000 { |
| 3231 | #dma-cells = <5>; |
| 3232 | compatible = "qcom,gpi-dma"; |
| 3233 | reg = <0xa00000 0x70000>; |
| 3234 | reg-names = "gpi-top"; |
Rishabh Bhatnagar | 7ef1588 | 2019-01-22 11:02:09 -0800 | [diff] [blame] | 3235 | interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, |
| 3236 | <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, |
| 3237 | <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, |
| 3238 | <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, |
| 3239 | <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, |
| 3240 | <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, |
| 3241 | <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, |
| 3242 | <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, |
| 3243 | <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, |
| 3244 | <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; |
Vipin Deep Kaur | 1cd6ed0 | 2018-12-27 16:23:43 +0530 | [diff] [blame] | 3245 | qcom,max-num-gpii = <10>; |
| 3246 | qcom,gpii-mask = <0x3f>; |
| 3247 | qcom,ev-factor = <2>; |
| 3248 | iommus = <&apps_smmu 0x56 0x0>; |
| 3249 | qcom,smmu-cfg = <0x1>; |
| 3250 | qcom,iova-range = <0x0 0x100000 0x0 0x100000>; |
| 3251 | status = "ok"; |
| 3252 | }; |
| 3253 | |
| 3254 | gpi_dma2: qcom,gpi-dma@800000 { |
| 3255 | #dma-cells = <5>; |
| 3256 | compatible = "qcom,gpi-dma"; |
| 3257 | reg = <0x800000 0x70000>; |
| 3258 | reg-names = "gpi-top"; |
Rishabh Bhatnagar | 7ef1588 | 2019-01-22 11:02:09 -0800 | [diff] [blame] | 3259 | interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, |
| 3260 | <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, |
| 3261 | <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, |
| 3262 | <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, |
| 3263 | <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, |
| 3264 | <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, |
| 3265 | <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, |
| 3266 | <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, |
| 3267 | <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, |
| 3268 | <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; |
Vipin Deep Kaur | 1cd6ed0 | 2018-12-27 16:23:43 +0530 | [diff] [blame] | 3269 | qcom,max-num-gpii = <10>; |
| 3270 | qcom,gpii-mask = <0x3f>; |
| 3271 | qcom,ev-factor = <2>; |
| 3272 | iommus = <&apps_smmu 0x76 0x0>; |
| 3273 | qcom,smmu-cfg = <0x1>; |
| 3274 | qcom,iova-range = <0x0 0x100000 0x0 0x100000>; |
| 3275 | status = "ok"; |
| 3276 | }; |
| 3277 | |
Yuanyuan Liu | 99e0b9a | 2019-01-16 11:01:38 -0800 | [diff] [blame] | 3278 | qcom,cnss-qca6390@a0000000 { |
| 3279 | compatible = "qcom,cnss-qca6390"; |
Yuanyuan Liu | 10616b83 | 2019-02-20 14:32:31 -0800 | [diff] [blame] | 3280 | reg = <0xb0000000 0x10000>; |
| 3281 | reg-names = "smmu_iova_ipa"; |
Yuanyuan Liu | 09a5209 | 2019-02-05 16:02:43 -0800 | [diff] [blame] | 3282 | wlan-en-gpio = <&tlmm 20 0>; |
Yuanyuan Liu | 99e0b9a | 2019-01-16 11:01:38 -0800 | [diff] [blame] | 3283 | pinctrl-names = "wlan_en_active", "wlan_en_sleep"; |
| 3284 | pinctrl-0 = <&cnss_wlan_en_active>; |
| 3285 | pinctrl-1 = <&cnss_wlan_en_sleep>; |
| 3286 | qcom,wlan-rc-num = <0>; |
| 3287 | qcom,wlan-ramdump-dynamic = <0x400000>; |
Yuanyuan Liu | e0c4907 | 2019-02-07 16:21:09 -0800 | [diff] [blame] | 3288 | qcom,smmu-s1-enable; |
Yuanyuan Liu | 99e0b9a | 2019-01-16 11:01:38 -0800 | [diff] [blame] | 3289 | |
Yuanyuan Liu | 30d201f | 2019-01-22 14:04:54 -0800 | [diff] [blame] | 3290 | vdd-wlan-aon-supply = <&pm8150_s6>; |
| 3291 | vdd-wlan-dig-supply = <&pm8009_s2>; |
| 3292 | vdd-wlan-io-supply = <&pm8150_s4>; |
| 3293 | vdd-wlan-rfa1-supply = <&pm8150_s5>; |
| 3294 | vdd-wlan-rfa2-supply = <&pm8150a_s8>; |
Yuanyuan Liu | 8f91f4a | 2019-01-30 10:42:25 -0800 | [diff] [blame] | 3295 | wlan-ant-switch-supply = <&pm8150a_l5>; |
Yuanyuan Liu | 30d201f | 2019-01-22 14:04:54 -0800 | [diff] [blame] | 3296 | |
Yuanyuan Liu | 99e0b9a | 2019-01-16 11:01:38 -0800 | [diff] [blame] | 3297 | mhi,max-channels = <30>; |
| 3298 | mhi,timeout = <10000>; |
| 3299 | |
| 3300 | mhi_channels { |
| 3301 | #address-cells = <1>; |
| 3302 | #size-cells = <0>; |
| 3303 | |
| 3304 | mhi_chan@0 { |
| 3305 | reg = <0>; |
| 3306 | label = "LOOPBACK"; |
| 3307 | mhi,num-elements = <32>; |
| 3308 | mhi,event-ring = <1>; |
| 3309 | mhi,chan-dir = <1>; |
| 3310 | mhi,data-type = <0>; |
| 3311 | mhi,doorbell-mode = <2>; |
| 3312 | mhi,ee = <0x14>; |
| 3313 | }; |
| 3314 | |
| 3315 | mhi_chan@1 { |
| 3316 | reg = <1>; |
| 3317 | label = "LOOPBACK"; |
| 3318 | mhi,num-elements = <32>; |
| 3319 | mhi,event-ring = <1>; |
| 3320 | mhi,chan-dir = <2>; |
| 3321 | mhi,data-type = <0>; |
| 3322 | mhi,doorbell-mode = <2>; |
| 3323 | mhi,ee = <0x14>; |
| 3324 | }; |
| 3325 | |
| 3326 | mhi_chan@4 { |
| 3327 | reg = <4>; |
| 3328 | label = "DIAG"; |
| 3329 | mhi,num-elements = <32>; |
| 3330 | mhi,event-ring = <1>; |
| 3331 | mhi,chan-dir = <1>; |
| 3332 | mhi,data-type = <0>; |
| 3333 | mhi,doorbell-mode = <2>; |
| 3334 | mhi,ee = <0x14>; |
| 3335 | }; |
| 3336 | |
| 3337 | mhi_chan@5 { |
| 3338 | reg = <5>; |
| 3339 | label = "DIAG"; |
| 3340 | mhi,num-elements = <32>; |
| 3341 | mhi,event-ring = <1>; |
| 3342 | mhi,chan-dir = <2>; |
| 3343 | mhi,data-type = <0>; |
| 3344 | mhi,doorbell-mode = <2>; |
| 3345 | mhi,ee = <0x14>; |
| 3346 | }; |
| 3347 | |
| 3348 | mhi_chan@20 { |
| 3349 | reg = <20>; |
| 3350 | label = "IPCR"; |
| 3351 | mhi,num-elements = <32>; |
| 3352 | mhi,event-ring = <1>; |
| 3353 | mhi,chan-dir = <1>; |
| 3354 | mhi,data-type = <1>; |
| 3355 | mhi,doorbell-mode = <2>; |
| 3356 | mhi,ee = <0x14>; |
| 3357 | mhi,auto-start; |
| 3358 | }; |
| 3359 | |
| 3360 | mhi_chan@21 { |
| 3361 | reg = <21>; |
| 3362 | label = "IPCR"; |
| 3363 | mhi,num-elements = <32>; |
| 3364 | mhi,event-ring = <1>; |
| 3365 | mhi,chan-dir = <2>; |
| 3366 | mhi,data-type = <0>; |
| 3367 | mhi,doorbell-mode = <2>; |
| 3368 | mhi,ee = <0x14>; |
| 3369 | mhi,auto-queue; |
| 3370 | mhi,auto-start; |
| 3371 | }; |
| 3372 | }; |
| 3373 | |
| 3374 | mhi_events { |
| 3375 | mhi_event@0 { |
| 3376 | mhi,num-elements = <32>; |
| 3377 | mhi,intmod = <1>; |
| 3378 | mhi,msi = <1>; |
| 3379 | mhi,priority = <1>; |
| 3380 | mhi,brstmode = <2>; |
| 3381 | mhi,data-type = <1>; |
| 3382 | }; |
| 3383 | |
| 3384 | mhi_event@1 { |
| 3385 | mhi,num-elements = <256>; |
| 3386 | mhi,intmod = <1>; |
| 3387 | mhi,msi = <2>; |
| 3388 | mhi,priority = <1>; |
| 3389 | mhi,brstmode = <2>; |
| 3390 | }; |
| 3391 | }; |
| 3392 | }; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 3393 | }; |
Swathi Sridhar | 4008eb4 | 2018-07-17 15:34:46 -0700 | [diff] [blame] | 3394 | |
David Collins | 61d237d | 2019-01-03 16:01:15 -0800 | [diff] [blame] | 3395 | #include "kona-regulators.dtsi" |
David Dai | b1d6848 | 2018-10-01 19:40:35 -0700 | [diff] [blame] | 3396 | #include "kona-bus.dtsi" |
Swathi Sridhar | bbbc80b | 2018-07-13 10:02:08 -0700 | [diff] [blame] | 3397 | #include "kona-ion.dtsi" |
Tony Truong | c972c64 | 2018-09-12 10:03:51 -0700 | [diff] [blame] | 3398 | #include "kona-pcie.dtsi" |
Sujeev Dias | 5399e55 | 2018-09-18 17:57:54 -0700 | [diff] [blame] | 3399 | #include "kona-mhi.dtsi" |
Yuanyuan Liu | 7c4eb3f | 2019-02-05 19:33:03 -0800 | [diff] [blame] | 3400 | |
| 3401 | &pcie0_rp { |
| 3402 | #address-cells = <5>; |
| 3403 | #size-cells = <0>; |
| 3404 | |
| 3405 | cnss_pci: cnss_pci { |
| 3406 | reg = <0 0 0 0 0>; |
Yuanyuan Liu | 10616b83 | 2019-02-20 14:32:31 -0800 | [diff] [blame] | 3407 | qcom,iommu-group = <&cnss_pci_iommu_group>; |
| 3408 | |
| 3409 | #address-cells = <1>; |
| 3410 | #size-cells = <1>; |
| 3411 | |
| 3412 | cnss_pci_iommu_group: cnss_pci_iommu_group { |
| 3413 | qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; |
| 3414 | qcom,iommu-dma = "fastmap"; |
| 3415 | qcom,iommu-pagetable = "coherent"; |
| 3416 | }; |
Yuanyuan Liu | 7c4eb3f | 2019-02-05 19:33:03 -0800 | [diff] [blame] | 3417 | }; |
| 3418 | }; |
| 3419 | |
Swathi Sridhar | 4008eb4 | 2018-07-17 15:34:46 -0700 | [diff] [blame] | 3420 | #include "msm-arm-smmu-kona.dtsi" |
Rishabh Bhatnagar | a740b0e | 2018-07-20 15:08:35 -0700 | [diff] [blame] | 3421 | #include "kona-pinctrl.dtsi" |
Chris Lew | 86f6bde | 2018-09-06 16:40:39 -0700 | [diff] [blame] | 3422 | #include "kona-smp2p.dtsi" |
Hemant Kumar | 5f58bad | 2018-08-31 14:25:23 -0700 | [diff] [blame] | 3423 | #include "kona-usb.dtsi" |
Tingwei Zhang | 564fa69 | 2018-11-28 00:31:17 -0800 | [diff] [blame] | 3424 | #include "kona-coresight.dtsi" |
Samantha Tran | 7e309f0 | 2018-08-31 17:23:00 -0700 | [diff] [blame] | 3425 | #include "kona-sde.dtsi" |
Satya Rama Aditya Pinapala | 09600b3 | 2018-10-29 10:52:37 -0700 | [diff] [blame] | 3426 | #include "kona-sde-pll.dtsi" |
Mukund Atre | d454ec9 | 2018-11-05 15:32:16 -0800 | [diff] [blame] | 3427 | |
Arjun Bagla | 76f02ef | 2018-09-19 10:00:29 -0700 | [diff] [blame] | 3428 | #include "kona-pm.dtsi" |
Mukund Atre | d454ec9 | 2018-11-05 15:32:16 -0800 | [diff] [blame] | 3429 | #include "kona-camera.dtsi" |
Vipin Deep Kaur | 9a2c13d | 2018-12-19 18:38:46 +0530 | [diff] [blame] | 3430 | #include "kona-qupv3.dtsi" |
Karthikeyan Mani | 7f5b10b | 2019-01-16 16:35:07 -0800 | [diff] [blame] | 3431 | #include "kona-audio.dtsi" |
Siddartha Mohanadoss | 42c8d78 | 2018-12-21 14:20:33 -0800 | [diff] [blame] | 3432 | #include "kona-thermal.dtsi" |
Chinmay Sawarkar | 83d01b4 | 2018-12-14 12:34:50 -0800 | [diff] [blame] | 3433 | #include "kona-vidc.dtsi" |
George Shen | 9c54c66 | 2018-12-26 15:50:11 -0800 | [diff] [blame] | 3434 | #include "kona-cvp.dtsi" |
Jilai Wang | 6fed1a2 | 2019-01-23 16:58:39 -0500 | [diff] [blame] | 3435 | #include "kona-npu.dtsi" |
Urvashi Agrawal | cdc3a3a | 2018-09-23 15:30:24 -0700 | [diff] [blame] | 3436 | #include "kona-gpu.dtsi" |
himta ram | e83f113 | 2019-01-29 18:30:27 +0530 | [diff] [blame] | 3437 | |
| 3438 | &qupv3_se15_i2c { |
| 3439 | status = "ok"; |
| 3440 | nq@64 { |
| 3441 | compatible = "rtc6226"; |
| 3442 | reg = <0x64>; |
| 3443 | fmint-gpio = <&tlmm 51 0>; |
| 3444 | vdd-supply = <&pm8150a_bob>; |
Umesh Vats | a9ba848 | 2019-02-26 14:47:54 -0800 | [diff] [blame] | 3445 | rtc6226,vdd-supply-voltage = <3296000 3296000>; |
himta ram | e83f113 | 2019-01-29 18:30:27 +0530 | [diff] [blame] | 3446 | vio-supply = <&pm8150_s4>; |
| 3447 | rtc6226,vio-supply-voltage = <1800000 1800000 >; |
| 3448 | }; |
| 3449 | }; |