Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/io.c |
| 3 | * |
| 4 | * OMAP2 I/O mapping code |
| 5 | * |
| 6 | * Copyright (C) 2005 Nokia Corporation |
Santosh Shilimkar | 4416907 | 2009-05-28 14:16:04 -0700 | [diff] [blame] | 7 | * Copyright (C) 2007-2009 Texas Instruments |
Tony Lindgren | 646e3ed | 2008-10-06 15:49:36 +0300 | [diff] [blame] | 8 | * |
| 9 | * Author: |
| 10 | * Juha Yrjola <juha.yrjola@nokia.com> |
| 11 | * Syed Khasim <x0khasim@ti.com> |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 12 | * |
Santosh Shilimkar | 4416907 | 2009-05-28 14:16:04 -0700 | [diff] [blame] | 13 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 14 | * |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 15 | * This program is free software; you can redistribute it and/or modify |
| 16 | * it under the terms of the GNU General Public License version 2 as |
| 17 | * published by the Free Software Foundation. |
| 18 | */ |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 19 | #include <linux/module.h> |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/init.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 22 | #include <linux/io.h> |
Paul Walmsley | 2f135ea | 2009-06-19 19:08:25 -0600 | [diff] [blame] | 23 | #include <linux/clk.h> |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 24 | |
Tony Lindgren | 120db2c | 2006-04-02 17:46:27 +0100 | [diff] [blame] | 25 | #include <asm/tlb.h> |
Tony Lindgren | 120db2c | 2006-04-02 17:46:27 +0100 | [diff] [blame] | 26 | #include <asm/mach/map.h> |
| 27 | |
Tony Lindgren | 45c3eb7 | 2012-11-30 08:41:50 -0800 | [diff] [blame] | 28 | #include <linux/omap-dma.h> |
Tony Lindgren | 646e3ed | 2008-10-06 15:49:36 +0300 | [diff] [blame] | 29 | |
Tony Lindgren | dc84328 | 2012-10-03 11:23:43 -0700 | [diff] [blame] | 30 | #include "omap_hwmod.h" |
Tony Lindgren | dbc0416 | 2012-08-31 10:59:07 -0700 | [diff] [blame] | 31 | #include "soc.h" |
Tony Lindgren | ee0839c | 2012-02-24 10:34:35 -0800 | [diff] [blame] | 32 | #include "iomap.h" |
| 33 | #include "voltage.h" |
| 34 | #include "powerdomain.h" |
| 35 | #include "clockdomain.h" |
| 36 | #include "common.h" |
Vaibhav Hiremath | e30384a | 2012-05-29 15:26:41 +0530 | [diff] [blame] | 37 | #include "clock.h" |
Paul Walmsley | e80a972 | 2010-01-26 20:13:12 -0700 | [diff] [blame] | 38 | #include "clock2xxx.h" |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 39 | #include "clock3xxx.h" |
Tony Lindgren | 1d5aef4 | 2012-10-03 16:36:40 -0700 | [diff] [blame] | 40 | #include "omap-pm.h" |
Paul Walmsley | 3e6ece1 | 2012-10-17 00:46:45 +0000 | [diff] [blame] | 41 | #include "sdrc.h" |
Paul Walmsley | b6a4226 | 2012-10-29 20:50:21 -0600 | [diff] [blame] | 42 | #include "control.h" |
Tony Lindgren | 3d82cbb | 2012-10-15 12:50:46 -0700 | [diff] [blame] | 43 | #include "serial.h" |
Tony Lindgren | bf027ca | 2012-10-29 13:54:06 -0700 | [diff] [blame] | 44 | #include "sram.h" |
Paul Walmsley | c4ceedc | 2012-10-29 20:56:29 -0600 | [diff] [blame] | 45 | #include "cm2xxx.h" |
| 46 | #include "cm3xxx.h" |
Tero Kristo | 7632a02 | 2014-10-27 08:39:23 -0700 | [diff] [blame] | 47 | #include "cm33xx.h" |
Tero Kristo | ab6c9bb | 2014-10-27 08:39:25 -0700 | [diff] [blame] | 48 | #include "cm44xx.h" |
Paul Walmsley | d9a16f9 | 2012-10-29 20:57:39 -0600 | [diff] [blame] | 49 | #include "prm.h" |
| 50 | #include "cm.h" |
| 51 | #include "prcm_mpu44xx.h" |
| 52 | #include "prminst44xx.h" |
Paul Walmsley | 63a293e | 2012-11-21 16:15:16 -0700 | [diff] [blame] | 53 | #include "prm2xxx.h" |
| 54 | #include "prm3xxx.h" |
Tero Kristo | d9bbe84 | 2014-10-27 08:39:24 -0700 | [diff] [blame] | 55 | #include "prm33xx.h" |
Paul Walmsley | 63a293e | 2012-11-21 16:15:16 -0700 | [diff] [blame] | 56 | #include "prm44xx.h" |
Tero Kristo | 69a1e7a | 2014-02-24 18:51:05 +0200 | [diff] [blame] | 57 | #include "opp2xxx.h" |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 58 | |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 59 | /* |
Tero Kristo | cfa9667 | 2013-10-22 11:53:02 +0300 | [diff] [blame] | 60 | * omap_clk_soc_init: points to a function that does the SoC-specific |
Rajendra Nayak | ff931c8 | 2013-03-21 16:34:52 +0530 | [diff] [blame] | 61 | * clock initializations |
| 62 | */ |
Tero Kristo | cfa9667 | 2013-10-22 11:53:02 +0300 | [diff] [blame] | 63 | static int (*omap_clk_soc_init)(void); |
Rajendra Nayak | ff931c8 | 2013-03-21 16:34:52 +0530 | [diff] [blame] | 64 | |
| 65 | /* |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 66 | * The machine specific code may provide the extra mapping besides the |
| 67 | * default mapping provided here. |
| 68 | */ |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 69 | |
Tony Lindgren | e48f814 | 2012-03-06 11:49:22 -0800 | [diff] [blame] | 70 | #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 71 | static struct map_desc omap24xx_io_desc[] __initdata = { |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 72 | { |
| 73 | .virtual = L3_24XX_VIRT, |
| 74 | .pfn = __phys_to_pfn(L3_24XX_PHYS), |
| 75 | .length = L3_24XX_SIZE, |
| 76 | .type = MT_DEVICE |
| 77 | }, |
Kyungmin Park | 09f21ed | 2008-02-20 15:30:06 -0800 | [diff] [blame] | 78 | { |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 79 | .virtual = L4_24XX_VIRT, |
| 80 | .pfn = __phys_to_pfn(L4_24XX_PHYS), |
| 81 | .length = L4_24XX_SIZE, |
Syed Mohammed Khasim | 72d0f1c | 2006-12-06 17:14:05 -0800 | [diff] [blame] | 82 | .type = MT_DEVICE |
| 83 | }, |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 84 | }; |
| 85 | |
Tony Lindgren | 59b479e | 2011-01-27 16:39:40 -0800 | [diff] [blame] | 86 | #ifdef CONFIG_SOC_OMAP2420 |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 87 | static struct map_desc omap242x_io_desc[] __initdata = { |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 88 | { |
Paul Walmsley | 7adb998 | 2010-01-08 15:23:05 -0700 | [diff] [blame] | 89 | .virtual = DSP_MEM_2420_VIRT, |
| 90 | .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), |
| 91 | .length = DSP_MEM_2420_SIZE, |
Tony Lindgren | c40fae95 | 2006-12-07 13:58:10 -0800 | [diff] [blame] | 92 | .type = MT_DEVICE |
| 93 | }, |
| 94 | { |
Paul Walmsley | 7adb998 | 2010-01-08 15:23:05 -0700 | [diff] [blame] | 95 | .virtual = DSP_IPI_2420_VIRT, |
| 96 | .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), |
| 97 | .length = DSP_IPI_2420_SIZE, |
Tony Lindgren | c40fae95 | 2006-12-07 13:58:10 -0800 | [diff] [blame] | 98 | .type = MT_DEVICE |
| 99 | }, |
| 100 | { |
Paul Walmsley | 7adb998 | 2010-01-08 15:23:05 -0700 | [diff] [blame] | 101 | .virtual = DSP_MMU_2420_VIRT, |
| 102 | .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), |
| 103 | .length = DSP_MMU_2420_SIZE, |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 104 | .type = MT_DEVICE |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 105 | }, |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 106 | }; |
| 107 | |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 108 | #endif |
| 109 | |
Tony Lindgren | 59b479e | 2011-01-27 16:39:40 -0800 | [diff] [blame] | 110 | #ifdef CONFIG_SOC_OMAP2430 |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 111 | static struct map_desc omap243x_io_desc[] __initdata = { |
| 112 | { |
| 113 | .virtual = L4_WK_243X_VIRT, |
| 114 | .pfn = __phys_to_pfn(L4_WK_243X_PHYS), |
| 115 | .length = L4_WK_243X_SIZE, |
| 116 | .type = MT_DEVICE |
| 117 | }, |
| 118 | { |
| 119 | .virtual = OMAP243X_GPMC_VIRT, |
| 120 | .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), |
| 121 | .length = OMAP243X_GPMC_SIZE, |
| 122 | .type = MT_DEVICE |
| 123 | }, |
| 124 | { |
| 125 | .virtual = OMAP243X_SDRC_VIRT, |
| 126 | .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), |
| 127 | .length = OMAP243X_SDRC_SIZE, |
| 128 | .type = MT_DEVICE |
| 129 | }, |
| 130 | { |
| 131 | .virtual = OMAP243X_SMS_VIRT, |
| 132 | .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), |
| 133 | .length = OMAP243X_SMS_SIZE, |
| 134 | .type = MT_DEVICE |
| 135 | }, |
| 136 | }; |
| 137 | #endif |
| 138 | #endif |
| 139 | |
Tony Lindgren | a8eb7ca | 2010-02-12 12:26:48 -0800 | [diff] [blame] | 140 | #ifdef CONFIG_ARCH_OMAP3 |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 141 | static struct map_desc omap34xx_io_desc[] __initdata = { |
| 142 | { |
| 143 | .virtual = L3_34XX_VIRT, |
| 144 | .pfn = __phys_to_pfn(L3_34XX_PHYS), |
| 145 | .length = L3_34XX_SIZE, |
| 146 | .type = MT_DEVICE |
| 147 | }, |
| 148 | { |
| 149 | .virtual = L4_34XX_VIRT, |
| 150 | .pfn = __phys_to_pfn(L4_34XX_PHYS), |
| 151 | .length = L4_34XX_SIZE, |
| 152 | .type = MT_DEVICE |
| 153 | }, |
| 154 | { |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 155 | .virtual = OMAP34XX_GPMC_VIRT, |
| 156 | .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), |
| 157 | .length = OMAP34XX_GPMC_SIZE, |
| 158 | .type = MT_DEVICE |
| 159 | }, |
| 160 | { |
| 161 | .virtual = OMAP343X_SMS_VIRT, |
| 162 | .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), |
| 163 | .length = OMAP343X_SMS_SIZE, |
| 164 | .type = MT_DEVICE |
| 165 | }, |
| 166 | { |
| 167 | .virtual = OMAP343X_SDRC_VIRT, |
| 168 | .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), |
| 169 | .length = OMAP343X_SDRC_SIZE, |
| 170 | .type = MT_DEVICE |
| 171 | }, |
| 172 | { |
| 173 | .virtual = L4_PER_34XX_VIRT, |
| 174 | .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), |
| 175 | .length = L4_PER_34XX_SIZE, |
| 176 | .type = MT_DEVICE |
| 177 | }, |
| 178 | { |
| 179 | .virtual = L4_EMU_34XX_VIRT, |
| 180 | .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), |
| 181 | .length = L4_EMU_34XX_SIZE, |
| 182 | .type = MT_DEVICE |
| 183 | }, |
| 184 | }; |
| 185 | #endif |
Hemant Pedanekar | 0100171 | 2011-02-16 08:31:39 -0800 | [diff] [blame] | 186 | |
Kevin Hilman | 3395955 | 2012-05-10 11:10:07 -0700 | [diff] [blame] | 187 | #ifdef CONFIG_SOC_TI81XX |
Hemant Pedanekar | a920360 | 2011-12-13 10:46:44 -0800 | [diff] [blame] | 188 | static struct map_desc omapti81xx_io_desc[] __initdata = { |
Hemant Pedanekar | 0100171 | 2011-02-16 08:31:39 -0800 | [diff] [blame] | 189 | { |
| 190 | .virtual = L4_34XX_VIRT, |
| 191 | .pfn = __phys_to_pfn(L4_34XX_PHYS), |
| 192 | .length = L4_34XX_SIZE, |
| 193 | .type = MT_DEVICE |
Afzal Mohammed | 1e6cb14 | 2011-12-13 10:46:43 -0800 | [diff] [blame] | 194 | } |
| 195 | }; |
| 196 | #endif |
| 197 | |
Afzal Mohammed | addb154 | 2013-05-27 20:06:13 +0530 | [diff] [blame] | 198 | #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) |
Afzal Mohammed | 1e6cb14 | 2011-12-13 10:46:43 -0800 | [diff] [blame] | 199 | static struct map_desc omapam33xx_io_desc[] __initdata = { |
Hemant Pedanekar | 0100171 | 2011-02-16 08:31:39 -0800 | [diff] [blame] | 200 | { |
| 201 | .virtual = L4_34XX_VIRT, |
| 202 | .pfn = __phys_to_pfn(L4_34XX_PHYS), |
| 203 | .length = L4_34XX_SIZE, |
| 204 | .type = MT_DEVICE |
| 205 | }, |
Afzal Mohammed | 1e6cb14 | 2011-12-13 10:46:43 -0800 | [diff] [blame] | 206 | { |
| 207 | .virtual = L4_WK_AM33XX_VIRT, |
| 208 | .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), |
| 209 | .length = L4_WK_AM33XX_SIZE, |
| 210 | .type = MT_DEVICE |
| 211 | } |
Hemant Pedanekar | 0100171 | 2011-02-16 08:31:39 -0800 | [diff] [blame] | 212 | }; |
| 213 | #endif |
| 214 | |
Santosh Shilimkar | 4416907 | 2009-05-28 14:16:04 -0700 | [diff] [blame] | 215 | #ifdef CONFIG_ARCH_OMAP4 |
| 216 | static struct map_desc omap44xx_io_desc[] __initdata = { |
| 217 | { |
| 218 | .virtual = L3_44XX_VIRT, |
| 219 | .pfn = __phys_to_pfn(L3_44XX_PHYS), |
| 220 | .length = L3_44XX_SIZE, |
| 221 | .type = MT_DEVICE, |
| 222 | }, |
| 223 | { |
| 224 | .virtual = L4_44XX_VIRT, |
| 225 | .pfn = __phys_to_pfn(L4_44XX_PHYS), |
| 226 | .length = L4_44XX_SIZE, |
| 227 | .type = MT_DEVICE, |
| 228 | }, |
| 229 | { |
Santosh Shilimkar | 4416907 | 2009-05-28 14:16:04 -0700 | [diff] [blame] | 230 | .virtual = L4_PER_44XX_VIRT, |
| 231 | .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), |
| 232 | .length = L4_PER_44XX_SIZE, |
| 233 | .type = MT_DEVICE, |
| 234 | }, |
Santosh Shilimkar | 4416907 | 2009-05-28 14:16:04 -0700 | [diff] [blame] | 235 | }; |
| 236 | #endif |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 237 | |
Nishanth Menon | ea827ad | 2015-06-22 10:12:14 -0500 | [diff] [blame] | 238 | #ifdef CONFIG_SOC_OMAP5 |
R Sricharan | 05e152c | 2012-06-05 16:21:32 +0530 | [diff] [blame] | 239 | static struct map_desc omap54xx_io_desc[] __initdata = { |
| 240 | { |
| 241 | .virtual = L3_54XX_VIRT, |
| 242 | .pfn = __phys_to_pfn(L3_54XX_PHYS), |
| 243 | .length = L3_54XX_SIZE, |
| 244 | .type = MT_DEVICE, |
| 245 | }, |
| 246 | { |
| 247 | .virtual = L4_54XX_VIRT, |
| 248 | .pfn = __phys_to_pfn(L4_54XX_PHYS), |
| 249 | .length = L4_54XX_SIZE, |
| 250 | .type = MT_DEVICE, |
| 251 | }, |
| 252 | { |
| 253 | .virtual = L4_WK_54XX_VIRT, |
| 254 | .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), |
| 255 | .length = L4_WK_54XX_SIZE, |
| 256 | .type = MT_DEVICE, |
| 257 | }, |
| 258 | { |
| 259 | .virtual = L4_PER_54XX_VIRT, |
| 260 | .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), |
| 261 | .length = L4_PER_54XX_SIZE, |
| 262 | .type = MT_DEVICE, |
| 263 | }, |
| 264 | }; |
| 265 | #endif |
| 266 | |
Nishanth Menon | ea827ad | 2015-06-22 10:12:14 -0500 | [diff] [blame] | 267 | #ifdef CONFIG_SOC_DRA7XX |
| 268 | static struct map_desc dra7xx_io_desc[] __initdata = { |
| 269 | { |
| 270 | .virtual = L4_CFG_MPU_DRA7XX_VIRT, |
| 271 | .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS), |
| 272 | .length = L4_CFG_MPU_DRA7XX_SIZE, |
| 273 | .type = MT_DEVICE, |
| 274 | }, |
| 275 | { |
| 276 | .virtual = L3_MAIN_SN_DRA7XX_VIRT, |
| 277 | .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS), |
| 278 | .length = L3_MAIN_SN_DRA7XX_SIZE, |
| 279 | .type = MT_DEVICE, |
| 280 | }, |
| 281 | { |
| 282 | .virtual = L4_PER1_DRA7XX_VIRT, |
| 283 | .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS), |
| 284 | .length = L4_PER1_DRA7XX_SIZE, |
| 285 | .type = MT_DEVICE, |
| 286 | }, |
| 287 | { |
| 288 | .virtual = L4_PER2_DRA7XX_VIRT, |
| 289 | .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS), |
| 290 | .length = L4_PER2_DRA7XX_SIZE, |
| 291 | .type = MT_DEVICE, |
| 292 | }, |
| 293 | { |
| 294 | .virtual = L4_PER3_DRA7XX_VIRT, |
| 295 | .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS), |
| 296 | .length = L4_PER3_DRA7XX_SIZE, |
| 297 | .type = MT_DEVICE, |
| 298 | }, |
| 299 | { |
| 300 | .virtual = L4_CFG_DRA7XX_VIRT, |
| 301 | .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS), |
| 302 | .length = L4_CFG_DRA7XX_SIZE, |
| 303 | .type = MT_DEVICE, |
| 304 | }, |
| 305 | { |
| 306 | .virtual = L4_WKUP_DRA7XX_VIRT, |
| 307 | .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS), |
| 308 | .length = L4_WKUP_DRA7XX_SIZE, |
| 309 | .type = MT_DEVICE, |
| 310 | }, |
| 311 | }; |
| 312 | #endif |
| 313 | |
Tony Lindgren | 59b479e | 2011-01-27 16:39:40 -0800 | [diff] [blame] | 314 | #ifdef CONFIG_SOC_OMAP2420 |
Paul Walmsley | b6a4226 | 2012-10-29 20:50:21 -0600 | [diff] [blame] | 315 | void __init omap242x_map_io(void) |
Tony Lindgren | 6fbd55d | 2010-02-12 12:26:47 -0800 | [diff] [blame] | 316 | { |
| 317 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
| 318 | iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); |
Tony Lindgren | 6fbd55d | 2010-02-12 12:26:47 -0800 | [diff] [blame] | 319 | } |
| 320 | #endif |
| 321 | |
Tony Lindgren | 59b479e | 2011-01-27 16:39:40 -0800 | [diff] [blame] | 322 | #ifdef CONFIG_SOC_OMAP2430 |
Paul Walmsley | b6a4226 | 2012-10-29 20:50:21 -0600 | [diff] [blame] | 323 | void __init omap243x_map_io(void) |
Tony Lindgren | 6fbd55d | 2010-02-12 12:26:47 -0800 | [diff] [blame] | 324 | { |
| 325 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
| 326 | iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); |
Tony Lindgren | 6fbd55d | 2010-02-12 12:26:47 -0800 | [diff] [blame] | 327 | } |
| 328 | #endif |
| 329 | |
Tony Lindgren | a8eb7ca | 2010-02-12 12:26:48 -0800 | [diff] [blame] | 330 | #ifdef CONFIG_ARCH_OMAP3 |
Paul Walmsley | b6a4226 | 2012-10-29 20:50:21 -0600 | [diff] [blame] | 331 | void __init omap3_map_io(void) |
Tony Lindgren | 6fbd55d | 2010-02-12 12:26:47 -0800 | [diff] [blame] | 332 | { |
| 333 | iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); |
Tony Lindgren | 6fbd55d | 2010-02-12 12:26:47 -0800 | [diff] [blame] | 334 | } |
| 335 | #endif |
| 336 | |
Kevin Hilman | 3395955 | 2012-05-10 11:10:07 -0700 | [diff] [blame] | 337 | #ifdef CONFIG_SOC_TI81XX |
Paul Walmsley | b6a4226 | 2012-10-29 20:50:21 -0600 | [diff] [blame] | 338 | void __init ti81xx_map_io(void) |
Hemant Pedanekar | 0100171 | 2011-02-16 08:31:39 -0800 | [diff] [blame] | 339 | { |
Hemant Pedanekar | a920360 | 2011-12-13 10:46:44 -0800 | [diff] [blame] | 340 | iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); |
Hemant Pedanekar | 0100171 | 2011-02-16 08:31:39 -0800 | [diff] [blame] | 341 | } |
| 342 | #endif |
| 343 | |
Afzal Mohammed | addb154 | 2013-05-27 20:06:13 +0530 | [diff] [blame] | 344 | #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) |
Paul Walmsley | b6a4226 | 2012-10-29 20:50:21 -0600 | [diff] [blame] | 345 | void __init am33xx_map_io(void) |
Afzal Mohammed | 1e6cb14 | 2011-12-13 10:46:43 -0800 | [diff] [blame] | 346 | { |
| 347 | iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); |
Tony Lindgren | 6fbd55d | 2010-02-12 12:26:47 -0800 | [diff] [blame] | 348 | } |
| 349 | #endif |
| 350 | |
| 351 | #ifdef CONFIG_ARCH_OMAP4 |
Paul Walmsley | b6a4226 | 2012-10-29 20:50:21 -0600 | [diff] [blame] | 352 | void __init omap4_map_io(void) |
Tony Lindgren | 6fbd55d | 2010-02-12 12:26:47 -0800 | [diff] [blame] | 353 | { |
| 354 | iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); |
Russell King | f746929 | 2015-06-06 00:13:40 +0100 | [diff] [blame] | 355 | omap_barriers_init(); |
Tony Lindgren | 6fbd55d | 2010-02-12 12:26:47 -0800 | [diff] [blame] | 356 | } |
| 357 | #endif |
| 358 | |
Nishanth Menon | ea827ad | 2015-06-22 10:12:14 -0500 | [diff] [blame] | 359 | #ifdef CONFIG_SOC_OMAP5 |
Paul Walmsley | b6a4226 | 2012-10-29 20:50:21 -0600 | [diff] [blame] | 360 | void __init omap5_map_io(void) |
R Sricharan | 05e152c | 2012-06-05 16:21:32 +0530 | [diff] [blame] | 361 | { |
| 362 | iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); |
Russell King | f746929 | 2015-06-06 00:13:40 +0100 | [diff] [blame] | 363 | omap_barriers_init(); |
R Sricharan | 05e152c | 2012-06-05 16:21:32 +0530 | [diff] [blame] | 364 | } |
| 365 | #endif |
Nishanth Menon | ea827ad | 2015-06-22 10:12:14 -0500 | [diff] [blame] | 366 | |
| 367 | #ifdef CONFIG_SOC_DRA7XX |
| 368 | void __init dra7xx_map_io(void) |
| 369 | { |
| 370 | iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc)); |
Nishanth Menon | 456e8d5 | 2016-03-11 10:12:28 -0600 | [diff] [blame] | 371 | omap_barriers_init(); |
Nishanth Menon | ea827ad | 2015-06-22 10:12:14 -0500 | [diff] [blame] | 372 | } |
| 373 | #endif |
Paul Walmsley | 2f135ea | 2009-06-19 19:08:25 -0600 | [diff] [blame] | 374 | /* |
| 375 | * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters |
| 376 | * |
| 377 | * Sets the CORE DPLL3 M2 divider to the same value that it's at |
| 378 | * currently. This has the effect of setting the SDRC SDRAM AC timing |
| 379 | * registers to the values currently defined by the kernel. Currently |
| 380 | * only defined for OMAP3; will return 0 if called on OMAP2. Returns |
| 381 | * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, |
| 382 | * or passes along the return value of clk_set_rate(). |
| 383 | */ |
| 384 | static int __init _omap2_init_reprogram_sdrc(void) |
| 385 | { |
| 386 | struct clk *dpll3_m2_ck; |
| 387 | int v = -EINVAL; |
| 388 | long rate; |
| 389 | |
| 390 | if (!cpu_is_omap34xx()) |
| 391 | return 0; |
| 392 | |
| 393 | dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); |
Aaro Koskinen | e281f7e | 2010-11-30 14:17:58 +0000 | [diff] [blame] | 394 | if (IS_ERR(dpll3_m2_ck)) |
Paul Walmsley | 2f135ea | 2009-06-19 19:08:25 -0600 | [diff] [blame] | 395 | return -EINVAL; |
| 396 | |
| 397 | rate = clk_get_rate(dpll3_m2_ck); |
| 398 | pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); |
| 399 | v = clk_set_rate(dpll3_m2_ck, rate); |
| 400 | if (v) |
| 401 | pr_err("dpll3_m2_clk rate change failed: %d\n", v); |
| 402 | |
| 403 | clk_put(dpll3_m2_ck); |
| 404 | |
| 405 | return v; |
| 406 | } |
| 407 | |
Paul Walmsley | 2092e5c | 2010-12-14 12:42:35 -0700 | [diff] [blame] | 408 | static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) |
| 409 | { |
| 410 | return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); |
| 411 | } |
| 412 | |
Tony Lindgren | 7b250af | 2011-10-04 18:26:28 -0700 | [diff] [blame] | 413 | static void __init omap_hwmod_init_postsetup(void) |
Tony Lindgren | 120db2c | 2006-04-02 17:46:27 +0100 | [diff] [blame] | 414 | { |
Paul Walmsley | 2092e5c | 2010-12-14 12:42:35 -0700 | [diff] [blame] | 415 | u8 postsetup_state; |
| 416 | |
Paul Walmsley | 2092e5c | 2010-12-14 12:42:35 -0700 | [diff] [blame] | 417 | /* Set the default postsetup state for all hwmods */ |
Rafael J. Wysocki | bf7c544 | 2014-12-13 00:42:49 +0100 | [diff] [blame] | 418 | #ifdef CONFIG_PM |
Paul Walmsley | 2092e5c | 2010-12-14 12:42:35 -0700 | [diff] [blame] | 419 | postsetup_state = _HWMOD_STATE_IDLE; |
| 420 | #else |
| 421 | postsetup_state = _HWMOD_STATE_ENABLED; |
| 422 | #endif |
| 423 | omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 424 | |
Kevin Hilman | 53da4ce | 2010-12-09 09:13:48 -0600 | [diff] [blame] | 425 | omap_pm_if_early_init(); |
Paul Walmsley | 4805734 | 2010-12-21 15:25:10 -0700 | [diff] [blame] | 426 | } |
| 427 | |
Arnd Bergmann | 069d0a7 | 2013-07-05 16:20:17 +0200 | [diff] [blame] | 428 | static void __init __maybe_unused omap_common_late_init(void) |
Ruslan Bilovol | 4ed12be | 2013-02-14 13:55:22 +0200 | [diff] [blame] | 429 | { |
| 430 | omap_mux_late_init(); |
| 431 | omap2_common_pm_late_init(); |
Ruslan Bilovol | 6770b21 | 2013-02-14 13:55:24 +0200 | [diff] [blame] | 432 | omap_soc_device_init(); |
Ruslan Bilovol | 4ed12be | 2013-02-14 13:55:22 +0200 | [diff] [blame] | 433 | } |
| 434 | |
Paul Walmsley | 1611079 | 2012-01-25 12:57:46 -0700 | [diff] [blame] | 435 | #ifdef CONFIG_SOC_OMAP2420 |
Tony Lindgren | 8f5b5a4 | 2011-08-22 23:57:24 -0700 | [diff] [blame] | 436 | void __init omap2420_init_early(void) |
| 437 | { |
Paul Walmsley | b6a4226 | 2012-10-29 20:50:21 -0600 | [diff] [blame] | 438 | omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); |
| 439 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), |
| 440 | OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); |
Tero Kristo | 2208bf1 | 2014-11-13 19:17:34 +0200 | [diff] [blame] | 441 | omap2_control_base_init(); |
Vaibhav Hiremath | 4de34f3 | 2011-12-19 15:50:15 +0530 | [diff] [blame] | 442 | omap2xxx_check_revision(); |
Tero Kristo | ab7b2ff | 2014-11-20 15:02:59 +0200 | [diff] [blame] | 443 | omap2_prcm_base_init(); |
Tony Lindgren | 7b250af | 2011-10-04 18:26:28 -0700 | [diff] [blame] | 444 | omap2xxx_voltagedomains_init(); |
| 445 | omap242x_powerdomains_init(); |
| 446 | omap242x_clockdomains_init(); |
| 447 | omap2420_hwmod_init(); |
| 448 | omap_hwmod_init_postsetup(); |
Tero Kristo | 6a194a6 | 2014-03-04 10:53:54 +0200 | [diff] [blame] | 449 | omap_clk_soc_init = omap2420_dt_clk_init; |
| 450 | rate_table = omap2420_rate_table; |
Tony Lindgren | 8f5b5a4 | 2011-08-22 23:57:24 -0700 | [diff] [blame] | 451 | } |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 452 | |
| 453 | void __init omap2420_init_late(void) |
| 454 | { |
Ruslan Bilovol | 4ed12be | 2013-02-14 13:55:22 +0200 | [diff] [blame] | 455 | omap_common_late_init(); |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 456 | omap2_pm_init(); |
Rajendra Nayak | 23fb8ba | 2012-06-01 14:02:49 +0530 | [diff] [blame] | 457 | omap2_clk_enable_autoidle_all(); |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 458 | } |
Paul Walmsley | 1611079 | 2012-01-25 12:57:46 -0700 | [diff] [blame] | 459 | #endif |
Tony Lindgren | 8f5b5a4 | 2011-08-22 23:57:24 -0700 | [diff] [blame] | 460 | |
Paul Walmsley | 1611079 | 2012-01-25 12:57:46 -0700 | [diff] [blame] | 461 | #ifdef CONFIG_SOC_OMAP2430 |
Tony Lindgren | 8f5b5a4 | 2011-08-22 23:57:24 -0700 | [diff] [blame] | 462 | void __init omap2430_init_early(void) |
| 463 | { |
Paul Walmsley | b6a4226 | 2012-10-29 20:50:21 -0600 | [diff] [blame] | 464 | omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); |
| 465 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), |
| 466 | OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); |
Tero Kristo | 2208bf1 | 2014-11-13 19:17:34 +0200 | [diff] [blame] | 467 | omap2_control_base_init(); |
Vaibhav Hiremath | 4de34f3 | 2011-12-19 15:50:15 +0530 | [diff] [blame] | 468 | omap2xxx_check_revision(); |
Tero Kristo | ab7b2ff | 2014-11-20 15:02:59 +0200 | [diff] [blame] | 469 | omap2_prcm_base_init(); |
Tony Lindgren | 7b250af | 2011-10-04 18:26:28 -0700 | [diff] [blame] | 470 | omap2xxx_voltagedomains_init(); |
| 471 | omap243x_powerdomains_init(); |
| 472 | omap243x_clockdomains_init(); |
| 473 | omap2430_hwmod_init(); |
| 474 | omap_hwmod_init_postsetup(); |
Tero Kristo | 6a194a6 | 2014-03-04 10:53:54 +0200 | [diff] [blame] | 475 | omap_clk_soc_init = omap2430_dt_clk_init; |
| 476 | rate_table = omap2430_rate_table; |
Tony Lindgren | 7b250af | 2011-10-04 18:26:28 -0700 | [diff] [blame] | 477 | } |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 478 | |
| 479 | void __init omap2430_init_late(void) |
| 480 | { |
Ruslan Bilovol | 4ed12be | 2013-02-14 13:55:22 +0200 | [diff] [blame] | 481 | omap_common_late_init(); |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 482 | omap2_pm_init(); |
Rajendra Nayak | 23fb8ba | 2012-06-01 14:02:49 +0530 | [diff] [blame] | 483 | omap2_clk_enable_autoidle_all(); |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 484 | } |
Sanjeev Premi | c4e2d24 | 2011-10-13 21:44:10 +0530 | [diff] [blame] | 485 | #endif |
Tony Lindgren | 7b250af | 2011-10-04 18:26:28 -0700 | [diff] [blame] | 486 | |
| 487 | /* |
| 488 | * Currently only board-omap3beagle.c should call this because of the |
| 489 | * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. |
| 490 | */ |
Sanjeev Premi | c4e2d24 | 2011-10-13 21:44:10 +0530 | [diff] [blame] | 491 | #ifdef CONFIG_ARCH_OMAP3 |
Tony Lindgren | 7b250af | 2011-10-04 18:26:28 -0700 | [diff] [blame] | 492 | void __init omap3_init_early(void) |
| 493 | { |
Paul Walmsley | b6a4226 | 2012-10-29 20:50:21 -0600 | [diff] [blame] | 494 | omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); |
| 495 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), |
| 496 | OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); |
Tero Kristo | 2208bf1 | 2014-11-13 19:17:34 +0200 | [diff] [blame] | 497 | /* XXX: remove these once OMAP3 is DT only */ |
| 498 | if (!of_have_populated_dt()) { |
| 499 | omap2_set_globals_control( |
Tero Kristo | efde234 | 2015-02-20 10:08:52 +0200 | [diff] [blame] | 500 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE)); |
Tero Kristo | 2208bf1 | 2014-11-13 19:17:34 +0200 | [diff] [blame] | 501 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); |
| 502 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), |
| 503 | NULL); |
| 504 | } |
| 505 | omap2_control_base_init(); |
Vaibhav Hiremath | 4de34f3 | 2011-12-19 15:50:15 +0530 | [diff] [blame] | 506 | omap3xxx_check_revision(); |
| 507 | omap3xxx_check_features(); |
Tero Kristo | ab7b2ff | 2014-11-20 15:02:59 +0200 | [diff] [blame] | 508 | omap2_prcm_base_init(); |
Tero Kristo | 425dc8b | 2014-11-21 15:51:37 +0200 | [diff] [blame] | 509 | /* XXX: remove these once OMAP3 is DT only */ |
| 510 | if (!of_have_populated_dt()) { |
| 511 | omap3xxx_prm_init(NULL); |
| 512 | omap3xxx_cm_init(NULL); |
| 513 | } |
Tony Lindgren | 7b250af | 2011-10-04 18:26:28 -0700 | [diff] [blame] | 514 | omap3xxx_voltagedomains_init(); |
| 515 | omap3xxx_powerdomains_init(); |
| 516 | omap3xxx_clockdomains_init(); |
| 517 | omap3xxx_hwmod_init(); |
| 518 | omap_hwmod_init_postsetup(); |
Tero Kristo | eded36f | 2014-12-16 18:20:55 +0200 | [diff] [blame] | 519 | if (!of_have_populated_dt()) { |
Tero Kristo | 2208bf1 | 2014-11-13 19:17:34 +0200 | [diff] [blame] | 520 | omap3_control_legacy_iomap_init(); |
Tero Kristo | eded36f | 2014-12-16 18:20:55 +0200 | [diff] [blame] | 521 | if (soc_is_am35xx()) |
| 522 | omap_clk_soc_init = am35xx_clk_legacy_init; |
| 523 | else if (cpu_is_omap3630()) |
| 524 | omap_clk_soc_init = omap36xx_clk_legacy_init; |
| 525 | else if (omap_rev() == OMAP3430_REV_ES1_0) |
| 526 | omap_clk_soc_init = omap3430es1_clk_legacy_init; |
| 527 | else |
| 528 | omap_clk_soc_init = omap3430_clk_legacy_init; |
| 529 | } |
Tony Lindgren | 8f5b5a4 | 2011-08-22 23:57:24 -0700 | [diff] [blame] | 530 | } |
| 531 | |
| 532 | void __init omap3430_init_early(void) |
| 533 | { |
Tony Lindgren | 7b250af | 2011-10-04 18:26:28 -0700 | [diff] [blame] | 534 | omap3_init_early(); |
Tero Kristo | 3e04915 | 2013-08-02 14:32:30 +0300 | [diff] [blame] | 535 | if (of_have_populated_dt()) |
| 536 | omap_clk_soc_init = omap3430_dt_clk_init; |
Tony Lindgren | 8f5b5a4 | 2011-08-22 23:57:24 -0700 | [diff] [blame] | 537 | } |
| 538 | |
| 539 | void __init omap35xx_init_early(void) |
| 540 | { |
Tony Lindgren | 7b250af | 2011-10-04 18:26:28 -0700 | [diff] [blame] | 541 | omap3_init_early(); |
Tero Kristo | 3e04915 | 2013-08-02 14:32:30 +0300 | [diff] [blame] | 542 | if (of_have_populated_dt()) |
| 543 | omap_clk_soc_init = omap3430_dt_clk_init; |
Tony Lindgren | 8f5b5a4 | 2011-08-22 23:57:24 -0700 | [diff] [blame] | 544 | } |
| 545 | |
| 546 | void __init omap3630_init_early(void) |
| 547 | { |
Tony Lindgren | 7b250af | 2011-10-04 18:26:28 -0700 | [diff] [blame] | 548 | omap3_init_early(); |
Tero Kristo | 3e04915 | 2013-08-02 14:32:30 +0300 | [diff] [blame] | 549 | if (of_have_populated_dt()) |
| 550 | omap_clk_soc_init = omap3630_dt_clk_init; |
Tony Lindgren | 8f5b5a4 | 2011-08-22 23:57:24 -0700 | [diff] [blame] | 551 | } |
| 552 | |
| 553 | void __init am35xx_init_early(void) |
| 554 | { |
Tony Lindgren | 7b250af | 2011-10-04 18:26:28 -0700 | [diff] [blame] | 555 | omap3_init_early(); |
Tero Kristo | 3e04915 | 2013-08-02 14:32:30 +0300 | [diff] [blame] | 556 | if (of_have_populated_dt()) |
| 557 | omap_clk_soc_init = am35xx_dt_clk_init; |
Tony Lindgren | 8f5b5a4 | 2011-08-22 23:57:24 -0700 | [diff] [blame] | 558 | } |
| 559 | |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 560 | void __init omap3_init_late(void) |
| 561 | { |
Ruslan Bilovol | 4ed12be | 2013-02-14 13:55:22 +0200 | [diff] [blame] | 562 | omap_common_late_init(); |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 563 | omap3_pm_init(); |
Rajendra Nayak | 23fb8ba | 2012-06-01 14:02:49 +0530 | [diff] [blame] | 564 | omap2_clk_enable_autoidle_all(); |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 565 | } |
| 566 | |
| 567 | void __init omap3430_init_late(void) |
| 568 | { |
Ruslan Bilovol | 4ed12be | 2013-02-14 13:55:22 +0200 | [diff] [blame] | 569 | omap_common_late_init(); |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 570 | omap3_pm_init(); |
Rajendra Nayak | 23fb8ba | 2012-06-01 14:02:49 +0530 | [diff] [blame] | 571 | omap2_clk_enable_autoidle_all(); |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 572 | } |
| 573 | |
| 574 | void __init omap35xx_init_late(void) |
| 575 | { |
Ruslan Bilovol | 4ed12be | 2013-02-14 13:55:22 +0200 | [diff] [blame] | 576 | omap_common_late_init(); |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 577 | omap3_pm_init(); |
Rajendra Nayak | 23fb8ba | 2012-06-01 14:02:49 +0530 | [diff] [blame] | 578 | omap2_clk_enable_autoidle_all(); |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 579 | } |
| 580 | |
| 581 | void __init omap3630_init_late(void) |
| 582 | { |
Ruslan Bilovol | 4ed12be | 2013-02-14 13:55:22 +0200 | [diff] [blame] | 583 | omap_common_late_init(); |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 584 | omap3_pm_init(); |
Rajendra Nayak | 23fb8ba | 2012-06-01 14:02:49 +0530 | [diff] [blame] | 585 | omap2_clk_enable_autoidle_all(); |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 586 | } |
| 587 | |
| 588 | void __init am35xx_init_late(void) |
| 589 | { |
Ruslan Bilovol | 4ed12be | 2013-02-14 13:55:22 +0200 | [diff] [blame] | 590 | omap_common_late_init(); |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 591 | omap3_pm_init(); |
Rajendra Nayak | 23fb8ba | 2012-06-01 14:02:49 +0530 | [diff] [blame] | 592 | omap2_clk_enable_autoidle_all(); |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 593 | } |
| 594 | |
| 595 | void __init ti81xx_init_late(void) |
| 596 | { |
Ruslan Bilovol | 4ed12be | 2013-02-14 13:55:22 +0200 | [diff] [blame] | 597 | omap_common_late_init(); |
Rajendra Nayak | 23fb8ba | 2012-06-01 14:02:49 +0530 | [diff] [blame] | 598 | omap2_clk_enable_autoidle_all(); |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 599 | } |
Sanjeev Premi | c4e2d24 | 2011-10-13 21:44:10 +0530 | [diff] [blame] | 600 | #endif |
Tony Lindgren | 8f5b5a4 | 2011-08-22 23:57:24 -0700 | [diff] [blame] | 601 | |
Aida Mynzhasova | a64459c | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 602 | #ifdef CONFIG_SOC_TI81XX |
| 603 | void __init ti814x_init_early(void) |
| 604 | { |
| 605 | omap2_set_globals_tap(TI814X_CLASS, |
| 606 | OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); |
Tero Kristo | 2208bf1 | 2014-11-13 19:17:34 +0200 | [diff] [blame] | 607 | omap2_control_base_init(); |
Aida Mynzhasova | a64459c | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 608 | omap3xxx_check_revision(); |
| 609 | ti81xx_check_features(); |
Tero Kristo | ab7b2ff | 2014-11-20 15:02:59 +0200 | [diff] [blame] | 610 | omap2_prcm_base_init(); |
Aida Mynzhasova | a64459c | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 611 | omap3xxx_voltagedomains_init(); |
| 612 | omap3xxx_powerdomains_init(); |
Tony Lindgren | 185fde6 | 2015-07-16 01:55:57 -0700 | [diff] [blame] | 613 | ti814x_clockdomains_init(); |
Tony Lindgren | 0f3ccb2 | 2015-07-16 01:55:58 -0700 | [diff] [blame] | 614 | dm814x_hwmod_init(); |
Aida Mynzhasova | a64459c | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 615 | omap_hwmod_init_postsetup(); |
Tony Lindgren | d893656 | 2015-12-03 12:02:32 -0800 | [diff] [blame] | 616 | omap_clk_soc_init = dm814x_dt_clk_init; |
Aida Mynzhasova | a64459c | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 617 | } |
| 618 | |
| 619 | void __init ti816x_init_early(void) |
| 620 | { |
| 621 | omap2_set_globals_tap(TI816X_CLASS, |
| 622 | OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); |
Tero Kristo | 2208bf1 | 2014-11-13 19:17:34 +0200 | [diff] [blame] | 623 | omap2_control_base_init(); |
Aida Mynzhasova | a64459c | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 624 | omap3xxx_check_revision(); |
| 625 | ti81xx_check_features(); |
Tero Kristo | ab7b2ff | 2014-11-20 15:02:59 +0200 | [diff] [blame] | 626 | omap2_prcm_base_init(); |
Aida Mynzhasova | a64459c | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 627 | omap3xxx_voltagedomains_init(); |
| 628 | omap3xxx_powerdomains_init(); |
Tony Lindgren | 185fde6 | 2015-07-16 01:55:57 -0700 | [diff] [blame] | 629 | ti816x_clockdomains_init(); |
Tony Lindgren | 0f3ccb2 | 2015-07-16 01:55:58 -0700 | [diff] [blame] | 630 | dm816x_hwmod_init(); |
Aida Mynzhasova | a64459c | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 631 | omap_hwmod_init_postsetup(); |
| 632 | if (of_have_populated_dt()) |
Tony Lindgren | 9cf705d | 2015-07-16 01:55:57 -0700 | [diff] [blame] | 633 | omap_clk_soc_init = dm816x_dt_clk_init; |
Aida Mynzhasova | a64459c | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 634 | } |
| 635 | #endif |
| 636 | |
Afzal Mohammed | 08f3098 | 2012-05-11 00:38:49 +0530 | [diff] [blame] | 637 | #ifdef CONFIG_SOC_AM33XX |
| 638 | void __init am33xx_init_early(void) |
| 639 | { |
Paul Walmsley | b6a4226 | 2012-10-29 20:50:21 -0600 | [diff] [blame] | 640 | omap2_set_globals_tap(AM335X_CLASS, |
| 641 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); |
Tero Kristo | 2208bf1 | 2014-11-13 19:17:34 +0200 | [diff] [blame] | 642 | omap2_control_base_init(); |
Afzal Mohammed | 08f3098 | 2012-05-11 00:38:49 +0530 | [diff] [blame] | 643 | omap3xxx_check_revision(); |
Vaibhav Hiremath | 7bcad17 | 2013-05-17 15:43:41 +0530 | [diff] [blame] | 644 | am33xx_check_features(); |
Tero Kristo | ab7b2ff | 2014-11-20 15:02:59 +0200 | [diff] [blame] | 645 | omap2_prcm_base_init(); |
Vaibhav Hiremath | 3f0ea76 | 2012-06-18 00:47:27 -0600 | [diff] [blame] | 646 | am33xx_powerdomains_init(); |
Vaibhav Hiremath | 9c80f3a | 2012-06-18 00:47:27 -0600 | [diff] [blame] | 647 | am33xx_clockdomains_init(); |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 648 | am33xx_hwmod_init(); |
| 649 | omap_hwmod_init_postsetup(); |
Tero Kristo | 149c09d | 2013-07-19 11:37:17 +0300 | [diff] [blame] | 650 | omap_clk_soc_init = am33xx_dt_clk_init; |
Afzal Mohammed | 08f3098 | 2012-05-11 00:38:49 +0530 | [diff] [blame] | 651 | } |
Nishanth Menon | 765e7a0 | 2013-10-16 10:39:02 -0500 | [diff] [blame] | 652 | |
| 653 | void __init am33xx_init_late(void) |
| 654 | { |
| 655 | omap_common_late_init(); |
| 656 | } |
Afzal Mohammed | 08f3098 | 2012-05-11 00:38:49 +0530 | [diff] [blame] | 657 | #endif |
| 658 | |
Afzal Mohammed | c510702 | 2013-05-27 20:06:23 +0530 | [diff] [blame] | 659 | #ifdef CONFIG_SOC_AM43XX |
| 660 | void __init am43xx_init_early(void) |
| 661 | { |
| 662 | omap2_set_globals_tap(AM335X_CLASS, |
| 663 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); |
Tero Kristo | 2208bf1 | 2014-11-13 19:17:34 +0200 | [diff] [blame] | 664 | omap2_control_base_init(); |
Afzal Mohammed | c510702 | 2013-05-27 20:06:23 +0530 | [diff] [blame] | 665 | omap3xxx_check_revision(); |
Afzal Mohammed | 7a2e051 | 2014-02-07 15:51:25 +0530 | [diff] [blame] | 666 | am33xx_check_features(); |
Tero Kristo | ab7b2ff | 2014-11-20 15:02:59 +0200 | [diff] [blame] | 667 | omap2_prcm_base_init(); |
Ambresh K | 8835cf6 | 2013-10-12 15:46:37 +0530 | [diff] [blame] | 668 | am43xx_powerdomains_init(); |
| 669 | am43xx_clockdomains_init(); |
| 670 | am43xx_hwmod_init(); |
| 671 | omap_hwmod_init_postsetup(); |
Sekhar Nori | d941f86 | 2014-04-22 13:58:03 +0530 | [diff] [blame] | 672 | omap_l2_cache_init(); |
Tero Kristo | d22031e | 2013-11-21 16:49:59 +0200 | [diff] [blame] | 673 | omap_clk_soc_init = am43xx_dt_clk_init; |
Afzal Mohammed | c510702 | 2013-05-27 20:06:23 +0530 | [diff] [blame] | 674 | } |
Nishanth Menon | 765e7a0 | 2013-10-16 10:39:02 -0500 | [diff] [blame] | 675 | |
| 676 | void __init am43xx_init_late(void) |
| 677 | { |
| 678 | omap_common_late_init(); |
Dave Gerlach | 08224a7 | 2015-09-15 14:47:34 -0500 | [diff] [blame] | 679 | omap2_clk_enable_autoidle_all(); |
Nishanth Menon | 765e7a0 | 2013-10-16 10:39:02 -0500 | [diff] [blame] | 680 | } |
Afzal Mohammed | c510702 | 2013-05-27 20:06:23 +0530 | [diff] [blame] | 681 | #endif |
| 682 | |
Sanjeev Premi | c4e2d24 | 2011-10-13 21:44:10 +0530 | [diff] [blame] | 683 | #ifdef CONFIG_ARCH_OMAP4 |
Tony Lindgren | 8f5b5a4 | 2011-08-22 23:57:24 -0700 | [diff] [blame] | 684 | void __init omap4430_init_early(void) |
| 685 | { |
Paul Walmsley | b6a4226 | 2012-10-29 20:50:21 -0600 | [diff] [blame] | 686 | omap2_set_globals_tap(OMAP443X_CLASS, |
| 687 | OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); |
Paul Walmsley | d9a16f9 | 2012-10-29 20:57:39 -0600 | [diff] [blame] | 688 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); |
Tero Kristo | ca125b5 | 2015-02-12 11:47:04 +0200 | [diff] [blame] | 689 | omap2_control_base_init(); |
Vaibhav Hiremath | 4de34f3 | 2011-12-19 15:50:15 +0530 | [diff] [blame] | 690 | omap4xxx_check_revision(); |
| 691 | omap4xxx_check_features(); |
Tero Kristo | ab7b2ff | 2014-11-20 15:02:59 +0200 | [diff] [blame] | 692 | omap2_prcm_base_init(); |
Tony Lindgren | f4b9f40 | 2016-06-22 01:59:39 -0700 | [diff] [blame^] | 693 | omap4_sar_ram_init(); |
Nishanth Menon | de70af4 | 2014-01-20 14:06:37 -0600 | [diff] [blame] | 694 | omap4_pm_init_early(); |
Tony Lindgren | 7b250af | 2011-10-04 18:26:28 -0700 | [diff] [blame] | 695 | omap44xx_voltagedomains_init(); |
| 696 | omap44xx_powerdomains_init(); |
| 697 | omap44xx_clockdomains_init(); |
| 698 | omap44xx_hwmod_init(); |
| 699 | omap_hwmod_init_postsetup(); |
Sekhar Nori | b39b14e | 2014-04-22 13:58:01 +0530 | [diff] [blame] | 700 | omap_l2_cache_init(); |
Tero Kristo | c8c88d8 | 2013-07-18 16:04:00 +0300 | [diff] [blame] | 701 | omap_clk_soc_init = omap4xxx_dt_clk_init; |
Tony Lindgren | 8f5b5a4 | 2011-08-22 23:57:24 -0700 | [diff] [blame] | 702 | } |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 703 | |
| 704 | void __init omap4430_init_late(void) |
| 705 | { |
Ruslan Bilovol | 4ed12be | 2013-02-14 13:55:22 +0200 | [diff] [blame] | 706 | omap_common_late_init(); |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 707 | omap4_pm_init(); |
Rajendra Nayak | 23fb8ba | 2012-06-01 14:02:49 +0530 | [diff] [blame] | 708 | omap2_clk_enable_autoidle_all(); |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 709 | } |
Sanjeev Premi | c4e2d24 | 2011-10-13 21:44:10 +0530 | [diff] [blame] | 710 | #endif |
Tony Lindgren | 8f5b5a4 | 2011-08-22 23:57:24 -0700 | [diff] [blame] | 711 | |
R Sricharan | 05e152c | 2012-06-05 16:21:32 +0530 | [diff] [blame] | 712 | #ifdef CONFIG_SOC_OMAP5 |
| 713 | void __init omap5_init_early(void) |
| 714 | { |
Paul Walmsley | b6a4226 | 2012-10-29 20:50:21 -0600 | [diff] [blame] | 715 | omap2_set_globals_tap(OMAP54XX_CLASS, |
| 716 | OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); |
Paul Walmsley | d9a16f9 | 2012-10-29 20:57:39 -0600 | [diff] [blame] | 717 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); |
Tero Kristo | ca125b5 | 2015-02-12 11:47:04 +0200 | [diff] [blame] | 718 | omap2_control_base_init(); |
Santosh Shilimkar | 628ed47 | 2014-05-20 16:19:23 -0500 | [diff] [blame] | 719 | omap4_pm_init_early(); |
Tero Kristo | ab7b2ff | 2014-11-20 15:02:59 +0200 | [diff] [blame] | 720 | omap2_prcm_base_init(); |
R Sricharan | 05e152c | 2012-06-05 16:21:32 +0530 | [diff] [blame] | 721 | omap5xxx_check_revision(); |
Tony Lindgren | f4b9f40 | 2016-06-22 01:59:39 -0700 | [diff] [blame^] | 722 | omap4_sar_ram_init(); |
Santosh Shilimkar | e4020aa | 2013-05-29 12:38:12 -0400 | [diff] [blame] | 723 | omap54xx_voltagedomains_init(); |
| 724 | omap54xx_powerdomains_init(); |
| 725 | omap54xx_clockdomains_init(); |
| 726 | omap54xx_hwmod_init(); |
| 727 | omap_hwmod_init_postsetup(); |
Tero Kristo | cfa9667 | 2013-10-22 11:53:02 +0300 | [diff] [blame] | 728 | omap_clk_soc_init = omap5xxx_dt_clk_init; |
R Sricharan | 05e152c | 2012-06-05 16:21:32 +0530 | [diff] [blame] | 729 | } |
Nishanth Menon | 765e7a0 | 2013-10-16 10:39:02 -0500 | [diff] [blame] | 730 | |
| 731 | void __init omap5_init_late(void) |
| 732 | { |
| 733 | omap_common_late_init(); |
Santosh Shilimkar | 628ed47 | 2014-05-20 16:19:23 -0500 | [diff] [blame] | 734 | omap4_pm_init(); |
| 735 | omap2_clk_enable_autoidle_all(); |
Nishanth Menon | 765e7a0 | 2013-10-16 10:39:02 -0500 | [diff] [blame] | 736 | } |
R Sricharan | 05e152c | 2012-06-05 16:21:32 +0530 | [diff] [blame] | 737 | #endif |
| 738 | |
R Sricharan | a3a9384 | 2013-07-03 11:52:04 +0530 | [diff] [blame] | 739 | #ifdef CONFIG_SOC_DRA7XX |
| 740 | void __init dra7xx_init_early(void) |
| 741 | { |
Nishanth Menon | ec490f6 | 2016-04-01 17:53:06 -0500 | [diff] [blame] | 742 | omap2_set_globals_tap(DRA7XX_CLASS, |
| 743 | OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); |
R Sricharan | a3a9384 | 2013-07-03 11:52:04 +0530 | [diff] [blame] | 744 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); |
Tero Kristo | ca125b5 | 2015-02-12 11:47:04 +0200 | [diff] [blame] | 745 | omap2_control_base_init(); |
Rajendra Nayak | 6af16a1 | 2014-08-22 09:02:34 -0500 | [diff] [blame] | 746 | omap4_pm_init_early(); |
Tero Kristo | ab7b2ff | 2014-11-20 15:02:59 +0200 | [diff] [blame] | 747 | omap2_prcm_base_init(); |
Nishanth Menon | 733d20e | 2014-05-19 10:27:11 -0500 | [diff] [blame] | 748 | dra7xxx_check_revision(); |
Ambresh K | 7de516a | 2013-08-23 04:05:08 -0600 | [diff] [blame] | 749 | dra7xx_powerdomains_init(); |
| 750 | dra7xx_clockdomains_init(); |
| 751 | dra7xx_hwmod_init(); |
| 752 | omap_hwmod_init_postsetup(); |
Tero Kristo | f1cf498 | 2013-08-29 11:35:43 +0300 | [diff] [blame] | 753 | omap_clk_soc_init = dra7xx_dt_clk_init; |
R Sricharan | a3a9384 | 2013-07-03 11:52:04 +0530 | [diff] [blame] | 754 | } |
Nishanth Menon | 765e7a0 | 2013-10-16 10:39:02 -0500 | [diff] [blame] | 755 | |
| 756 | void __init dra7xx_init_late(void) |
| 757 | { |
| 758 | omap_common_late_init(); |
Rajendra Nayak | 6af16a1 | 2014-08-22 09:02:34 -0500 | [diff] [blame] | 759 | omap4_pm_init(); |
| 760 | omap2_clk_enable_autoidle_all(); |
Nishanth Menon | 765e7a0 | 2013-10-16 10:39:02 -0500 | [diff] [blame] | 761 | } |
R Sricharan | a3a9384 | 2013-07-03 11:52:04 +0530 | [diff] [blame] | 762 | #endif |
| 763 | |
| 764 | |
Tony Lindgren | a4ca9db | 2011-08-22 23:57:23 -0700 | [diff] [blame] | 765 | void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, |
Paul Walmsley | 4805734 | 2010-12-21 15:25:10 -0700 | [diff] [blame] | 766 | struct omap_sdrc_params *sdrc_cs1) |
| 767 | { |
Tony Lindgren | a66cb34 | 2011-10-04 13:52:57 -0700 | [diff] [blame] | 768 | omap_sram_init(); |
| 769 | |
Hemant Pedanekar | 0100171 | 2011-02-16 08:31:39 -0800 | [diff] [blame] | 770 | if (cpu_is_omap24xx() || omap3_has_sdrc()) { |
Kevin Hilman | aa4b1f6 | 2010-03-10 17:16:31 +0000 | [diff] [blame] | 771 | omap2_sdrc_init(sdrc_cs0, sdrc_cs1); |
| 772 | _omap2_init_reprogram_sdrc(); |
| 773 | } |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 774 | } |
Tero Kristo | cfa9667 | 2013-10-22 11:53:02 +0300 | [diff] [blame] | 775 | |
| 776 | int __init omap_clk_init(void) |
| 777 | { |
| 778 | int ret = 0; |
| 779 | |
| 780 | if (!omap_clk_soc_init) |
| 781 | return 0; |
| 782 | |
Tero Kristo | 8111e01 | 2014-07-02 11:47:39 +0300 | [diff] [blame] | 783 | ti_clk_init_features(); |
| 784 | |
Tero Kristo | e9e6308 | 2015-04-27 21:55:42 +0300 | [diff] [blame] | 785 | omap2_clk_setup_ll_ops(); |
| 786 | |
Tero Kristo | eded36f | 2014-12-16 18:20:55 +0200 | [diff] [blame] | 787 | if (of_have_populated_dt()) { |
Tero Kristo | fe87414 | 2014-03-12 18:33:45 +0200 | [diff] [blame] | 788 | ret = omap_control_init(); |
| 789 | if (ret) |
| 790 | return ret; |
| 791 | |
Tero Kristo | 3a1a388 | 2014-11-18 14:59:36 +0200 | [diff] [blame] | 792 | ret = omap_prcm_init(); |
Tero Kristo | eded36f | 2014-12-16 18:20:55 +0200 | [diff] [blame] | 793 | if (ret) |
| 794 | return ret; |
Tero Kristo | c08ee14 | 2014-09-12 15:01:57 +0300 | [diff] [blame] | 795 | |
Tero Kristo | eded36f | 2014-12-16 18:20:55 +0200 | [diff] [blame] | 796 | of_clk_init(NULL); |
Tero Kristo | c08ee14 | 2014-09-12 15:01:57 +0300 | [diff] [blame] | 797 | |
Tero Kristo | eded36f | 2014-12-16 18:20:55 +0200 | [diff] [blame] | 798 | ti_dt_clk_init_retry_clks(); |
Tero Kristo | c08ee14 | 2014-09-12 15:01:57 +0300 | [diff] [blame] | 799 | |
Tero Kristo | eded36f | 2014-12-16 18:20:55 +0200 | [diff] [blame] | 800 | ti_dt_clockdomains_setup(); |
| 801 | } |
Tero Kristo | c08ee14 | 2014-09-12 15:01:57 +0300 | [diff] [blame] | 802 | |
| 803 | ret = omap_clk_soc_init(); |
Tero Kristo | cfa9667 | 2013-10-22 11:53:02 +0300 | [diff] [blame] | 804 | |
| 805 | return ret; |
| 806 | } |