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gerrit-public.fairphone.software / kernel / msm-4.9 / 07134a365f1c4be6e840a00ae452d1593f15c5fc / . / arch / arm / boot / dts / tegra30-cardhu.dtsi
blob: 0cf0848a82d88964ddd0ed72fca19aa5c6cb135a [file] [log] [blame]
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]1#include "tegra30.dtsi"
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]2
Laxman Dewangan640a7af2012-08-09 16:30:38 +0530[diff] [blame]3/**
4 * This file contains common DT entry for all fab version of Cardhu.
5 * There is multiple fab version of Cardhu starting from A01 to A07.
6 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
7 * A02 will have different sets of GPIOs for fixed regulator compare to
8 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
9 * compatible with fab version A04. Based on Cardhu fab version, the
10 * related dts file need to be chosen like for Cardhu fab version A02,
11 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
12 * tegra30-cardhu-a04.dts.
13 * The identification of board is done in two ways, by looking the sticker
14 * on PCB and by reading board id eeprom.
15 * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
16 * number is the fab version like here it is 002 and hence fab version A02.
17 * The (downstream internal) U-Boot of Cardhu display the board-id as
18 * follows:
19 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
20 * In this Fab version is 02 i.e. A02.
21 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
22 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
23 * wide.
24 */
25
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]26/ {
27 model = "NVIDIA Tegra30 Cardhu evaluation board";
28 compatible = "nvidia,cardhu", "nvidia,tegra30";
29
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]30 aliases {
Stephen Warren763fbff2014-02-13 17:18:26 -0700[diff] [blame]31 rtc0 = "/i2c@7000d000/tps65911@2d";
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]32 rtc1 = "/rtc@7000e000";
33 };
34
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]35 memory {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]36 reg = <0x80000000 0x40000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]37 };
38
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]39 pcie-controller@00003000 {
Jay Agarwal89e7ada2013-08-09 16:49:27 +0200[diff] [blame]40 status = "okay";
41 pex-clk-supply = <&pex_hvdd_3v3_reg>;
42 vdd-supply = <&ldo1_reg>;
43 avdd-supply = <&ldo2_reg>;
44
45 pci@1,0 {
46 nvidia,num-lanes = <4>;
47 };
48
49 pci@2,0 {
50 nvidia,num-lanes = <1>;
51 };
52
53 pci@3,0 {
54 status = "okay";
55 nvidia,num-lanes = <1>;
56 };
57 };
58
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]59 host1x@50000000 {
60 dc@54200000 {
61 rgb {
62 status = "okay";
63
64 nvidia,panel = <&panel>;
65 };
66 };
67 };
68
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]69 pinmux@70000868 {
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]70 pinctrl-names = "default";
71 pinctrl-0 = <&state_default>;
72
73 state_default: pinmux {
74 sdmmc1_clk_pz0 {
75 nvidia,pins = "sdmmc1_clk_pz0";
76 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]77 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]79 };
80 sdmmc1_cmd_pz1 {
81 nvidia,pins = "sdmmc1_cmd_pz1",
82 "sdmmc1_dat0_py7",
83 "sdmmc1_dat1_py6",
84 "sdmmc1_dat2_py5",
85 "sdmmc1_dat3_py4";
86 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]87 nvidia,pull = <TEGRA_PIN_PULL_UP>;
88 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]89 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]90 sdmmc3_clk_pa6 {
91 nvidia,pins = "sdmmc3_clk_pa6";
92 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]93 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
94 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]95 };
96 sdmmc3_cmd_pa7 {
97 nvidia,pins = "sdmmc3_cmd_pa7",
98 "sdmmc3_dat0_pb7",
99 "sdmmc3_dat1_pb6",
100 "sdmmc3_dat2_pb5",
101 "sdmmc3_dat3_pb4";
102 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]103 nvidia,pull = <TEGRA_PIN_PULL_UP>;
104 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]105 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]106 sdmmc4_clk_pcc4 {
107 nvidia,pins = "sdmmc4_clk_pcc4",
108 "sdmmc4_rst_n_pcc3";
109 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]110 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
111 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]112 };
113 sdmmc4_dat0_paa0 {
114 nvidia,pins = "sdmmc4_dat0_paa0",
115 "sdmmc4_dat1_paa1",
116 "sdmmc4_dat2_paa2",
117 "sdmmc4_dat3_paa3",
118 "sdmmc4_dat4_paa4",
119 "sdmmc4_dat5_paa5",
120 "sdmmc4_dat6_paa6",
121 "sdmmc4_dat7_paa7";
122 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]123 nvidia,pull = <TEGRA_PIN_PULL_UP>;
124 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]125 };
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]126 dap2_fs_pa2 {
127 nvidia,pins = "dap2_fs_pa2",
128 "dap2_sclk_pa3",
129 "dap2_din_pa4",
130 "dap2_dout_pa5";
131 nvidia,function = "i2s1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]132 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
133 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]134 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]135 sdio3 {
136 nvidia,pins = "drive_sdio3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]137 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
138 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]139 nvidia,pull-down-strength = <46>;
140 nvidia,pull-up-strength = <42>;
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]141 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
142 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]143 };
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]144 uart3_txd_pw6 {
145 nvidia,pins = "uart3_txd_pw6",
146 "uart3_cts_n_pa1",
147 "uart3_rts_n_pc0",
148 "uart3_rxd_pw7";
149 nvidia,function = "uartc";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]150 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
151 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]152 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]153 };
154 };
155
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]156 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]157 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]158 };
159
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]160 serial@70006200 {
161 compatible = "nvidia,tegra30-hsuart";
162 status = "okay";
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]163 };
164
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]165 pwm@7000a000 {
166 status = "okay";
167 };
168
169 panelddc: i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]170 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]171 clock-frequency = <100000>;
172 };
173
174 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]175 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]176 clock-frequency = <100000>;
177 };
178
179 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]180 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]181 clock-frequency = <100000>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]182
183 /* ALS and Proximity sensor */
184 isl29028@44 {
185 compatible = "isil,isl29028";
186 reg = <0x44>;
187 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]188 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]189 };
Bryan Wu40431d12014-02-07 15:54:58 -0800[diff] [blame]190
191 i2cmux@70 {
192 compatible = "nxp,pca9546";
193 #address-cells = <1>;
194 #size-cells = <0>;
195 reg = <0x70>;
196 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]197 };
198
199 i2c@7000c700 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]200 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]201 clock-frequency = <100000>;
202 };
203
204 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]205 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]206 clock-frequency = <100000>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]207
208 wm8903: wm8903@1a {
209 compatible = "wlf,wm8903";
210 reg = <0x1a>;
211 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]212 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]213
214 gpio-controller;
215 #gpio-cells = <2>;
216
217 micdet-cfg = <0>;
218 micdet-delay = <100>;
219 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
220 };
Laxman Dewangan331da582012-05-10 20:38:45 +0000[diff] [blame]221
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]222 pmic: tps65911@2d {
223 compatible = "ti,tps65911";
224 reg = <0x2d>;
225
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]226 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]227 #interrupt-cells = <2>;
228 interrupt-controller;
229
Stephen Warren44b12ef2012-09-11 11:42:26 -0600[diff] [blame]230 ti,system-power-controller;
231
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]232 #gpio-cells = <2>;
233 gpio-controller;
234
235 vcc1-supply = <&vdd_ac_bat_reg>;
236 vcc2-supply = <&vdd_ac_bat_reg>;
237 vcc3-supply = <&vio_reg>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]238 vcc4-supply = <&vdd_5v0_reg>;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]239 vcc5-supply = <&vdd_ac_bat_reg>;
240 vcc6-supply = <&vdd2_reg>;
241 vcc7-supply = <&vdd_ac_bat_reg>;
242 vccio-supply = <&vdd_ac_bat_reg>;
243
244 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]245 vdd1_reg: vdd1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]246 regulator-name = "vddio_ddr_1v2";
247 regulator-min-microvolt = <1200000>;
248 regulator-max-microvolt = <1200000>;
249 regulator-always-on;
250 };
251
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]252 vdd2_reg: vdd2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]253 regulator-name = "vdd_1v5_gen";
254 regulator-min-microvolt = <1500000>;
255 regulator-max-microvolt = <1500000>;
256 regulator-always-on;
257 };
258
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]259 vddctrl_reg: vddctrl {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]260 regulator-name = "vdd_cpu,vdd_sys";
261 regulator-min-microvolt = <1000000>;
262 regulator-max-microvolt = <1000000>;
263 regulator-always-on;
264 };
265
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]266 vio_reg: vio {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]267 regulator-name = "vdd_1v8_gen";
268 regulator-min-microvolt = <1800000>;
269 regulator-max-microvolt = <1800000>;
270 regulator-always-on;
271 };
272
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]273 ldo1_reg: ldo1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]274 regulator-name = "vdd_pexa,vdd_pexb";
275 regulator-min-microvolt = <1050000>;
276 regulator-max-microvolt = <1050000>;
277 };
278
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]279 ldo2_reg: ldo2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]280 regulator-name = "vdd_sata,avdd_plle";
281 regulator-min-microvolt = <1050000>;
282 regulator-max-microvolt = <1050000>;
283 };
284
285 /* LDO3 is not connected to anything */
286
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]287 ldo4_reg: ldo4 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]288 regulator-name = "vdd_rtc";
289 regulator-min-microvolt = <1200000>;
290 regulator-max-microvolt = <1200000>;
291 regulator-always-on;
292 };
293
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]294 ldo5_reg: ldo5 {
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]295 regulator-name = "vddio_sdmmc,avdd_vdac";
296 regulator-min-microvolt = <3300000>;
297 regulator-max-microvolt = <3300000>;
298 regulator-always-on;
299 };
300
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]301 ldo6_reg: ldo6 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]302 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
303 regulator-min-microvolt = <1200000>;
304 regulator-max-microvolt = <1200000>;
305 };
306
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]307 ldo7_reg: ldo7 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]308 regulator-name = "vdd_pllm,x,u,a_p_c_s";
309 regulator-min-microvolt = <1200000>;
310 regulator-max-microvolt = <1200000>;
311 regulator-always-on;
312 };
313
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]314 ldo8_reg: ldo8 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]315 regulator-name = "vdd_ddr_hs";
316 regulator-min-microvolt = <1000000>;
317 regulator-max-microvolt = <1000000>;
318 regulator-always-on;
319 };
320 };
321 };
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]322
Wei Ni7c7de6b2013-10-07 17:28:29 +0800[diff] [blame]323 temperature-sensor@4c {
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]324 compatible = "onnn,nct1008";
325 reg = <0x4c>;
Wei Ni7c7de6b2013-10-07 17:28:29 +0800[diff] [blame]326 vcc-supply = <&sys_3v3_reg>;
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]327 interrupt-parent = <&gpio>;
328 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
329 };
Stephen Warren2b8584d2013-07-15 10:33:53 -0600[diff] [blame]330
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]331 tps62361@60 {
Stephen Warren2b8584d2013-07-15 10:33:53 -0600[diff] [blame]332 compatible = "ti,tps62361";
333 reg = <0x60>;
334
335 regulator-name = "tps62361-vout";
336 regulator-min-microvolt = <500000>;
337 regulator-max-microvolt = <1500000>;
338 regulator-boot-on;
339 regulator-always-on;
340 ti,vsel0-state-high;
341 ti,vsel1-state-high;
342 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]343 };
Stephen Warren850c4c82012-02-01 16:29:57 -0700[diff] [blame]344
Laxman Dewanganc42cb1c2012-10-31 14:32:54 +0530[diff] [blame]345 spi@7000da00 {
346 status = "okay";
347 spi-max-frequency = <25000000>;
348 spi-flash@1 {
349 compatible = "winbond,w25q32";
350 reg = <1>;
351 spi-max-frequency = <20000000>;
352 };
353 };
354
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]355 pmc@7000e400 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]356 status = "okay";
357 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800[diff] [blame]358 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800[diff] [blame]359 nvidia,cpu-pwr-good-time = <2000>;
360 nvidia,cpu-pwr-off-time = <200>;
361 nvidia,core-pwr-good-time = <3845 3845>;
362 nvidia,core-pwr-off-time = <0>;
363 nvidia,core-power-req-active-high;
364 nvidia,sys-clock-req-active-high;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]365 };
366
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]367 ahub@70080000 {
368 i2s@70080400 {
369 status = "okay";
370 };
371 };
372
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]373 sdhci@78000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]374 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]375 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
376 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
377 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]378 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]379 };
380
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]381 sdhci@78000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]382 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]383 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600[diff] [blame]384 non-removable;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]385 };
386
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300[diff] [blame]387 usb@7d008000 {
388 status = "okay";
389 };
390
391 usb-phy@7d008000 {
392 vbus-supply = <&usb3_vbus_reg>;
393 status = "okay";
394 };
395
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]396 backlight: backlight {
397 compatible = "pwm-backlight";
398
399 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
400 power-supply = <&vdd_bl_reg>;
401 pwms = <&pwm 0 5000000>;
402
403 brightness-levels = <0 4 8 16 32 64 128 255>;
404 default-brightness-level = <6>;
405 };
406
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]407 clocks {
408 compatible = "simple-bus";
409 #address-cells = <1>;
410 #size-cells = <0>;
411
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]412 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]413 compatible = "fixed-clock";
414 reg=<0>;
415 #clock-cells = <0>;
416 clock-frequency = <32768>;
417 };
418 };
419
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]420 panel: panel {
421 compatible = "chunghwa,claa101wb01", "simple-panel";
422 ddc-i2c-bus = <&panelddc>;
423
424 power-supply = <&vdd_pnl1_reg>;
425 enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
426
427 backlight = <&backlight>;
428 };
429
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]430 regulators {
431 compatible = "simple-bus";
432 #address-cells = <1>;
433 #size-cells = <0>;
434
435 vdd_ac_bat_reg: regulator@0 {
436 compatible = "regulator-fixed";
437 reg = <0>;
438 regulator-name = "vdd_ac_bat";
439 regulator-min-microvolt = <5000000>;
440 regulator-max-microvolt = <5000000>;
441 regulator-always-on;
442 };
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]443
444 cam_1v8_reg: regulator@1 {
445 compatible = "regulator-fixed";
446 reg = <1>;
447 regulator-name = "cam_1v8";
448 regulator-min-microvolt = <1800000>;
449 regulator-max-microvolt = <1800000>;
450 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]451 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]452 vin-supply = <&vio_reg>;
453 };
454
455 cp_5v_reg: regulator@2 {
456 compatible = "regulator-fixed";
457 reg = <2>;
458 regulator-name = "cp_5v";
459 regulator-min-microvolt = <5000000>;
460 regulator-max-microvolt = <5000000>;
461 regulator-boot-on;
462 regulator-always-on;
463 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]464 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]465 };
466
467 emmc_3v3_reg: regulator@3 {
468 compatible = "regulator-fixed";
469 reg = <3>;
470 regulator-name = "emmc_3v3";
471 regulator-min-microvolt = <3300000>;
472 regulator-max-microvolt = <3300000>;
473 regulator-always-on;
474 regulator-boot-on;
475 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]476 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]477 vin-supply = <&sys_3v3_reg>;
478 };
479
480 modem_3v3_reg: regulator@4 {
481 compatible = "regulator-fixed";
482 reg = <4>;
483 regulator-name = "modem_3v3";
484 regulator-min-microvolt = <3300000>;
485 regulator-max-microvolt = <3300000>;
486 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]487 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]488 };
489
490 pex_hvdd_3v3_reg: regulator@5 {
491 compatible = "regulator-fixed";
492 reg = <5>;
493 regulator-name = "pex_hvdd_3v3";
494 regulator-min-microvolt = <3300000>;
495 regulator-max-microvolt = <3300000>;
496 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]497 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]498 vin-supply = <&sys_3v3_reg>;
499 };
500
501 vdd_cam1_ldo_reg: regulator@6 {
502 compatible = "regulator-fixed";
503 reg = <6>;
504 regulator-name = "vdd_cam1_ldo";
505 regulator-min-microvolt = <2800000>;
506 regulator-max-microvolt = <2800000>;
507 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]508 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]509 vin-supply = <&sys_3v3_reg>;
510 };
511
512 vdd_cam2_ldo_reg: regulator@7 {
513 compatible = "regulator-fixed";
514 reg = <7>;
515 regulator-name = "vdd_cam2_ldo";
516 regulator-min-microvolt = <2800000>;
517 regulator-max-microvolt = <2800000>;
518 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]519 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]520 vin-supply = <&sys_3v3_reg>;
521 };
522
523 vdd_cam3_ldo_reg: regulator@8 {
524 compatible = "regulator-fixed";
525 reg = <8>;
526 regulator-name = "vdd_cam3_ldo";
527 regulator-min-microvolt = <3300000>;
528 regulator-max-microvolt = <3300000>;
529 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]530 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]531 vin-supply = <&sys_3v3_reg>;
532 };
533
534 vdd_com_reg: regulator@9 {
535 compatible = "regulator-fixed";
536 reg = <9>;
537 regulator-name = "vdd_com";
538 regulator-min-microvolt = <3300000>;
539 regulator-max-microvolt = <3300000>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]540 regulator-always-on;
541 regulator-boot-on;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]542 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]543 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]544 vin-supply = <&sys_3v3_reg>;
545 };
546
547 vdd_fuse_3v3_reg: regulator@10 {
548 compatible = "regulator-fixed";
549 reg = <10>;
550 regulator-name = "vdd_fuse_3v3";
551 regulator-min-microvolt = <3300000>;
552 regulator-max-microvolt = <3300000>;
553 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]554 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]555 vin-supply = <&sys_3v3_reg>;
556 };
557
558 vdd_pnl1_reg: regulator@11 {
559 compatible = "regulator-fixed";
560 reg = <11>;
561 regulator-name = "vdd_pnl1";
562 regulator-min-microvolt = <3300000>;
563 regulator-max-microvolt = <3300000>;
564 regulator-always-on;
565 regulator-boot-on;
566 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]567 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]568 vin-supply = <&sys_3v3_reg>;
569 };
570
571 vdd_vid_reg: regulator@12 {
572 compatible = "regulator-fixed";
573 reg = <12>;
574 regulator-name = "vddio_vid";
575 regulator-min-microvolt = <5000000>;
576 regulator-max-microvolt = <5000000>;
577 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]578 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]579 gpio-open-drain;
580 vin-supply = <&vdd_5v0_reg>;
581 };
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]582 };
583
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]584 sound {
585 compatible = "nvidia,tegra-audio-wm8903-cardhu",
586 "nvidia,tegra-audio-wm8903";
587 nvidia,model = "NVIDIA Tegra Cardhu";
588
589 nvidia,audio-routing =
590 "Headphone Jack", "HPOUTR",
591 "Headphone Jack", "HPOUTL",
592 "Int Spk", "ROP",
593 "Int Spk", "RON",
594 "Int Spk", "LOP",
595 "Int Spk", "LON",
596 "Mic Jack", "MICBIAS",
597 "IN1L", "Mic Jack";
598
599 nvidia,i2s-controller = <&tegra_i2s1>;
600 nvidia,audio-codec = <&wm8903>;
601
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]602 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
603 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
604 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]605
Hiroshi Doyu05849c92013-05-22 19:45:34 +0300[diff] [blame]606 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
607 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
608 <&tegra_car TEGRA30_CLK_EXTERN1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]609 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]610 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]611};