Yuval Mintz | 247fa82 | 2013-01-14 05:11:50 +0000 | [diff] [blame^] | 1 | /* Copyright 2008-2013 Broadcom Corporation |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2 | * |
| 3 | * Unless you and Broadcom execute a separate written software license |
| 4 | * agreement governing use of this software, this software is licensed to you |
| 5 | * under the terms of the GNU General Public License version 2, available |
| 6 | * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). |
| 7 | * |
| 8 | * Notwithstanding the above, under no circumstances may you combine this |
| 9 | * software in any way with any other Broadcom software provided under a |
| 10 | * license other than the GPL, without Broadcom's express prior written |
| 11 | * consent. |
| 12 | * |
| 13 | * Written by Yaniv Rosner |
| 14 | * |
| 15 | */ |
| 16 | |
Joe Perches | 7995c64 | 2010-02-17 15:01:52 +0000 | [diff] [blame] | 17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 18 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 19 | #include <linux/kernel.h> |
| 20 | #include <linux/errno.h> |
| 21 | #include <linux/pci.h> |
| 22 | #include <linux/netdevice.h> |
| 23 | #include <linux/delay.h> |
| 24 | #include <linux/ethtool.h> |
| 25 | #include <linux/mutex.h> |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 26 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 27 | #include "bnx2x.h" |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 28 | #include "bnx2x_cmn.h" |
| 29 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 30 | /********************************************************/ |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 31 | #define ETH_HLEN 14 |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 32 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ |
| 33 | #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 34 | #define ETH_MIN_PACKET_SIZE 60 |
| 35 | #define ETH_MAX_PACKET_SIZE 1500 |
| 36 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 |
| 37 | #define MDIO_ACCESS_TIMEOUT 1000 |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 38 | #define WC_LANE_MAX 4 |
| 39 | #define I2C_SWITCH_WIDTH 2 |
| 40 | #define I2C_BSC0 0 |
| 41 | #define I2C_BSC1 1 |
| 42 | #define I2C_WA_RETRY_CNT 3 |
Yuval Mintz | 50a2984 | 2012-06-16 20:27:14 +0000 | [diff] [blame] | 43 | #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 44 | #define MCPR_IMC_COMMAND_READ_OP 1 |
| 45 | #define MCPR_IMC_COMMAND_WRITE_OP 2 |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 46 | |
Yaniv Rosner | 26ffaf3 | 2011-10-27 05:09:45 +0000 | [diff] [blame] | 47 | /* LED Blink rate that will achieve ~15.9Hz */ |
| 48 | #define LED_BLINK_RATE_VAL_E3 354 |
| 49 | #define LED_BLINK_RATE_VAL_E1X_E2 480 |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 50 | /***********************************************************/ |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 51 | /* Shortcut definitions */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 52 | /***********************************************************/ |
| 53 | |
Eilon Greenstein | 2f90446 | 2009-08-12 08:22:16 +0000 | [diff] [blame] | 54 | #define NIG_LATCH_BC_ENABLE_MI_INT 0 |
| 55 | |
| 56 | #define NIG_STATUS_EMAC0_MI_INT \ |
| 57 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 58 | #define NIG_STATUS_XGXS0_LINK10G \ |
| 59 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G |
| 60 | #define NIG_STATUS_XGXS0_LINK_STATUS \ |
| 61 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS |
| 62 | #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ |
| 63 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE |
| 64 | #define NIG_STATUS_SERDES0_LINK_STATUS \ |
| 65 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS |
| 66 | #define NIG_MASK_MI_INT \ |
| 67 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT |
| 68 | #define NIG_MASK_XGXS0_LINK10G \ |
| 69 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G |
| 70 | #define NIG_MASK_XGXS0_LINK_STATUS \ |
| 71 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS |
| 72 | #define NIG_MASK_SERDES0_LINK_STATUS \ |
| 73 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS |
| 74 | |
| 75 | #define MDIO_AN_CL73_OR_37_COMPLETE \ |
| 76 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ |
| 77 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) |
| 78 | |
| 79 | #define XGXS_RESET_BITS \ |
| 80 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ |
| 81 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ |
| 82 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ |
| 83 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ |
| 84 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) |
| 85 | |
| 86 | #define SERDES_RESET_BITS \ |
| 87 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ |
| 88 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ |
| 89 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ |
| 90 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) |
| 91 | |
| 92 | #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 |
| 93 | #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 94 | #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 95 | #define AUTONEG_PARALLEL \ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 96 | SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 97 | #define AUTONEG_SGMII_FIBER_AUTODET \ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 98 | SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 99 | #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 100 | |
| 101 | #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ |
| 102 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE |
| 103 | #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ |
| 104 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE |
| 105 | #define GP_STATUS_SPEED_MASK \ |
| 106 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK |
| 107 | #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M |
| 108 | #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M |
| 109 | #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G |
| 110 | #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G |
| 111 | #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G |
| 112 | #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G |
| 113 | #define GP_STATUS_10G_HIG \ |
| 114 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG |
| 115 | #define GP_STATUS_10G_CX4 \ |
| 116 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 117 | #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX |
| 118 | #define GP_STATUS_10G_KX4 \ |
| 119 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 120 | #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR |
| 121 | #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI |
| 122 | #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS |
| 123 | #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 124 | #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 125 | #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD |
| 126 | #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 127 | #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 128 | #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 129 | #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD |
| 130 | #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD |
| 131 | #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD |
| 132 | #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD |
| 133 | #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD |
| 134 | #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD |
| 135 | #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 136 | #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD |
| 137 | #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 138 | #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD |
| 139 | #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 140 | |
Yaniv Rosner | 4978140 | 2012-10-31 05:46:55 +0000 | [diff] [blame] | 141 | #define LINK_UPDATE_MASK \ |
| 142 | (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \ |
| 143 | LINK_STATUS_LINK_UP | \ |
| 144 | LINK_STATUS_PHYSICAL_LINK_FLAG | \ |
| 145 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \ |
| 146 | LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \ |
| 147 | LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \ |
| 148 | LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \ |
| 149 | LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \ |
| 150 | LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 151 | |
Eilon Greenstein | 589abe3 | 2009-02-12 08:36:55 +0000 | [diff] [blame] | 152 | #define SFP_EEPROM_CON_TYPE_ADDR 0x2 |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 153 | #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 |
Eilon Greenstein | 589abe3 | 2009-02-12 08:36:55 +0000 | [diff] [blame] | 154 | #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 |
| 155 | |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 156 | |
| 157 | #define SFP_EEPROM_COMP_CODE_ADDR 0x3 |
| 158 | #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) |
| 159 | #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) |
| 160 | #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) |
| 161 | |
Eilon Greenstein | 589abe3 | 2009-02-12 08:36:55 +0000 | [diff] [blame] | 162 | #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 |
| 163 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 164 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 165 | |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 166 | #define SFP_EEPROM_OPTIONS_ADDR 0x40 |
Eilon Greenstein | 589abe3 | 2009-02-12 08:36:55 +0000 | [diff] [blame] | 167 | #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 168 | #define SFP_EEPROM_OPTIONS_SIZE 2 |
Eilon Greenstein | 589abe3 | 2009-02-12 08:36:55 +0000 | [diff] [blame] | 169 | |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 170 | #define EDC_MODE_LINEAR 0x0022 |
| 171 | #define EDC_MODE_LIMITING 0x0044 |
| 172 | #define EDC_MODE_PASSIVE_DAC 0x0055 |
Eilon Greenstein | 589abe3 | 2009-02-12 08:36:55 +0000 | [diff] [blame] | 173 | |
Yaniv Rosner | 866ceda | 2011-11-28 00:49:45 +0000 | [diff] [blame] | 174 | /* ETS defines*/ |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 175 | #define DCBX_INVALID_COS (0xFF) |
| 176 | |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 177 | #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) |
| 178 | #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 179 | #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) |
| 180 | #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) |
| 181 | #define ETS_E3B0_PBF_MIN_W_VAL (10000) |
| 182 | |
| 183 | #define MAX_PACKET_SIZE (9700) |
Yaniv Rosner | a9077bf | 2011-10-27 05:09:46 +0000 | [diff] [blame] | 184 | #define MAX_KR_LINK_RETRY 4 |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 185 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 186 | /**********************************************************/ |
| 187 | /* INTERFACE */ |
| 188 | /**********************************************************/ |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 189 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 190 | #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 191 | bnx2x_cl45_write(_bp, _phy, \ |
Yaniv Rosner | 7aa0711 | 2010-09-07 11:41:01 +0000 | [diff] [blame] | 192 | (_phy)->def_md_devad, \ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 193 | (_bank + (_addr & 0xf)), \ |
| 194 | _val) |
| 195 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 196 | #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 197 | bnx2x_cl45_read(_bp, _phy, \ |
Yaniv Rosner | 7aa0711 | 2010-09-07 11:41:01 +0000 | [diff] [blame] | 198 | (_phy)->def_md_devad, \ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 199 | (_bank + (_addr & 0xf)), \ |
| 200 | _val) |
| 201 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 202 | static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) |
| 203 | { |
| 204 | u32 val = REG_RD(bp, reg); |
| 205 | |
| 206 | val |= bits; |
| 207 | REG_WR(bp, reg, val); |
| 208 | return val; |
| 209 | } |
| 210 | |
| 211 | static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) |
| 212 | { |
| 213 | u32 val = REG_RD(bp, reg); |
| 214 | |
| 215 | val &= ~bits; |
| 216 | REG_WR(bp, reg, val); |
| 217 | return val; |
| 218 | } |
| 219 | |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 220 | /* |
| 221 | * bnx2x_check_lfa - This function checks if link reinitialization is required, |
| 222 | * or link flap can be avoided. |
| 223 | * |
| 224 | * @params: link parameters |
| 225 | * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed |
| 226 | * condition code. |
| 227 | */ |
| 228 | static int bnx2x_check_lfa(struct link_params *params) |
| 229 | { |
| 230 | u32 link_status, cfg_idx, lfa_mask, cfg_size; |
| 231 | u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config; |
| 232 | u32 saved_val, req_val, eee_status; |
| 233 | struct bnx2x *bp = params->bp; |
| 234 | |
| 235 | additional_config = |
| 236 | REG_RD(bp, params->lfa_base + |
| 237 | offsetof(struct shmem_lfa, additional_config)); |
| 238 | |
| 239 | /* NOTE: must be first condition checked - |
| 240 | * to verify DCC bit is cleared in any case! |
| 241 | */ |
| 242 | if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { |
| 243 | DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n"); |
| 244 | REG_WR(bp, params->lfa_base + |
| 245 | offsetof(struct shmem_lfa, additional_config), |
| 246 | additional_config & ~NO_LFA_DUE_TO_DCC_MASK); |
| 247 | return LFA_DCC_LFA_DISABLED; |
| 248 | } |
| 249 | |
| 250 | /* Verify that link is up */ |
| 251 | link_status = REG_RD(bp, params->shmem_base + |
| 252 | offsetof(struct shmem_region, |
| 253 | port_mb[params->port].link_status)); |
| 254 | if (!(link_status & LINK_STATUS_LINK_UP)) |
| 255 | return LFA_LINK_DOWN; |
| 256 | |
Barak Witkowski | c63da99 | 2012-12-05 23:04:03 +0000 | [diff] [blame] | 257 | /* if loaded after BOOT from SAN, don't flap the link in any case and |
| 258 | * rely on link set by preboot driver |
| 259 | */ |
| 260 | if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN) |
| 261 | return 0; |
| 262 | |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 263 | /* Verify that loopback mode is not set */ |
| 264 | if (params->loopback_mode) |
| 265 | return LFA_LOOPBACK_ENABLED; |
| 266 | |
| 267 | /* Verify that MFW supports LFA */ |
| 268 | if (!params->lfa_base) |
| 269 | return LFA_MFW_IS_TOO_OLD; |
| 270 | |
| 271 | if (params->num_phys == 3) { |
| 272 | cfg_size = 2; |
| 273 | lfa_mask = 0xffffffff; |
| 274 | } else { |
| 275 | cfg_size = 1; |
| 276 | lfa_mask = 0xffff; |
| 277 | } |
| 278 | |
| 279 | /* Compare Duplex */ |
| 280 | saved_val = REG_RD(bp, params->lfa_base + |
| 281 | offsetof(struct shmem_lfa, req_duplex)); |
| 282 | req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); |
| 283 | if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { |
| 284 | DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n", |
| 285 | (saved_val & lfa_mask), (req_val & lfa_mask)); |
| 286 | return LFA_DUPLEX_MISMATCH; |
| 287 | } |
| 288 | /* Compare Flow Control */ |
| 289 | saved_val = REG_RD(bp, params->lfa_base + |
| 290 | offsetof(struct shmem_lfa, req_flow_ctrl)); |
| 291 | req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); |
| 292 | if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { |
| 293 | DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n", |
| 294 | (saved_val & lfa_mask), (req_val & lfa_mask)); |
| 295 | return LFA_FLOW_CTRL_MISMATCH; |
| 296 | } |
| 297 | /* Compare Link Speed */ |
| 298 | saved_val = REG_RD(bp, params->lfa_base + |
| 299 | offsetof(struct shmem_lfa, req_line_speed)); |
| 300 | req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); |
| 301 | if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { |
| 302 | DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n", |
| 303 | (saved_val & lfa_mask), (req_val & lfa_mask)); |
| 304 | return LFA_LINK_SPEED_MISMATCH; |
| 305 | } |
| 306 | |
| 307 | for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { |
| 308 | cur_speed_cap_mask = REG_RD(bp, params->lfa_base + |
| 309 | offsetof(struct shmem_lfa, |
| 310 | speed_cap_mask[cfg_idx])); |
| 311 | |
| 312 | if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { |
| 313 | DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n", |
| 314 | cur_speed_cap_mask, |
| 315 | params->speed_cap_mask[cfg_idx]); |
| 316 | return LFA_SPEED_CAP_MISMATCH; |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | cur_req_fc_auto_adv = |
| 321 | REG_RD(bp, params->lfa_base + |
| 322 | offsetof(struct shmem_lfa, additional_config)) & |
| 323 | REQ_FC_AUTO_ADV_MASK; |
| 324 | |
| 325 | if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) { |
| 326 | DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n", |
| 327 | cur_req_fc_auto_adv, params->req_fc_auto_adv); |
| 328 | return LFA_FLOW_CTRL_MISMATCH; |
| 329 | } |
| 330 | |
| 331 | eee_status = REG_RD(bp, params->shmem2_base + |
| 332 | offsetof(struct shmem2_region, |
| 333 | eee_status[params->port])); |
| 334 | |
| 335 | if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^ |
| 336 | (params->eee_mode & EEE_MODE_ENABLE_LPI)) || |
| 337 | ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ |
| 338 | (params->eee_mode & EEE_MODE_ADV_LPI))) { |
| 339 | DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode, |
| 340 | eee_status); |
| 341 | return LFA_EEE_MISMATCH; |
| 342 | } |
| 343 | |
| 344 | /* LFA conditions are met */ |
| 345 | return 0; |
| 346 | } |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 347 | /******************************************************************/ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 348 | /* EPIO/GPIO section */ |
| 349 | /******************************************************************/ |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 350 | static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en) |
| 351 | { |
| 352 | u32 epio_mask, gp_oenable; |
| 353 | *en = 0; |
| 354 | /* Sanity check */ |
| 355 | if (epio_pin > 31) { |
| 356 | DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); |
| 357 | return; |
| 358 | } |
| 359 | |
| 360 | epio_mask = 1 << epio_pin; |
| 361 | /* Set this EPIO to output */ |
| 362 | gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); |
| 363 | REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); |
| 364 | |
| 365 | *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; |
| 366 | } |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 367 | static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en) |
| 368 | { |
| 369 | u32 epio_mask, gp_output, gp_oenable; |
| 370 | |
| 371 | /* Sanity check */ |
| 372 | if (epio_pin > 31) { |
| 373 | DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); |
| 374 | return; |
| 375 | } |
| 376 | DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); |
| 377 | epio_mask = 1 << epio_pin; |
| 378 | /* Set this EPIO to output */ |
| 379 | gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); |
| 380 | if (en) |
| 381 | gp_output |= epio_mask; |
| 382 | else |
| 383 | gp_output &= ~epio_mask; |
| 384 | |
| 385 | REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); |
| 386 | |
| 387 | /* Set the value for this EPIO */ |
| 388 | gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); |
| 389 | REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); |
| 390 | } |
| 391 | |
| 392 | static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) |
| 393 | { |
| 394 | if (pin_cfg == PIN_CFG_NA) |
| 395 | return; |
| 396 | if (pin_cfg >= PIN_CFG_EPIO0) { |
| 397 | bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); |
| 398 | } else { |
| 399 | u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; |
| 400 | u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; |
| 401 | bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); |
| 402 | } |
| 403 | } |
| 404 | |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 405 | static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) |
| 406 | { |
| 407 | if (pin_cfg == PIN_CFG_NA) |
| 408 | return -EINVAL; |
| 409 | if (pin_cfg >= PIN_CFG_EPIO0) { |
| 410 | bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); |
| 411 | } else { |
| 412 | u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; |
| 413 | u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; |
| 414 | *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); |
| 415 | } |
| 416 | return 0; |
| 417 | |
| 418 | } |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 419 | /******************************************************************/ |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 420 | /* ETS section */ |
| 421 | /******************************************************************/ |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 422 | static void bnx2x_ets_e2e3a0_disabled(struct link_params *params) |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 423 | { |
| 424 | /* ETS disabled configuration*/ |
| 425 | struct bnx2x *bp = params->bp; |
| 426 | |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 427 | DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n"); |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 428 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 429 | /* mapping between entry priority to client number (0,1,2 -debug and |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 430 | * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) |
| 431 | * 3bits client num. |
| 432 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 |
| 433 | * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 |
| 434 | */ |
| 435 | |
| 436 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 437 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 438 | * as strict. Bits 0,1,2 - debug and management entries, 3 - |
| 439 | * COS0 entry, 4 - COS1 entry. |
| 440 | * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT |
| 441 | * bit4 bit3 bit2 bit1 bit0 |
| 442 | * MCP and debug are strict |
| 443 | */ |
| 444 | |
| 445 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); |
| 446 | /* defines which entries (clients) are subjected to WFQ arbitration */ |
| 447 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 448 | /* For strict priority entries defines the number of consecutive |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 449 | * slots for the highest priority. |
| 450 | */ |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 451 | REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 452 | /* mapping between the CREDIT_WEIGHT registers and actual client |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 453 | * numbers |
| 454 | */ |
| 455 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); |
| 456 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); |
| 457 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); |
| 458 | |
| 459 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); |
| 460 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); |
| 461 | REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); |
| 462 | /* ETS mode disable */ |
| 463 | REG_WR(bp, PBF_REG_ETS_ENABLED, 0); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 464 | /* If ETS mode is enabled (there is no strict priority) defines a WFQ |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 465 | * weight for COS0/COS1. |
| 466 | */ |
| 467 | REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); |
| 468 | REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); |
| 469 | /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ |
| 470 | REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); |
| 471 | REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); |
| 472 | /* Defines the number of consecutive slots for the strict priority */ |
| 473 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); |
| 474 | } |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 475 | /****************************************************************************** |
| 476 | * Description: |
| 477 | * Getting min_w_val will be set according to line speed . |
| 478 | *. |
| 479 | ******************************************************************************/ |
| 480 | static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars) |
| 481 | { |
| 482 | u32 min_w_val = 0; |
| 483 | /* Calculate min_w_val.*/ |
| 484 | if (vars->link_up) { |
Yaniv Rosner | de0396f | 2011-11-28 00:49:53 +0000 | [diff] [blame] | 485 | if (vars->line_speed == SPEED_20000) |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 486 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; |
| 487 | else |
| 488 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; |
| 489 | } else |
| 490 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 491 | /* If the link isn't up (static configuration for example ) The |
| 492 | * link will be according to 20GBPS. |
| 493 | */ |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 494 | return min_w_val; |
| 495 | } |
| 496 | /****************************************************************************** |
| 497 | * Description: |
| 498 | * Getting credit upper bound form min_w_val. |
| 499 | *. |
| 500 | ******************************************************************************/ |
| 501 | static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val) |
| 502 | { |
| 503 | const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val), |
| 504 | MAX_PACKET_SIZE); |
| 505 | return credit_upper_bound; |
| 506 | } |
| 507 | /****************************************************************************** |
| 508 | * Description: |
| 509 | * Set credit upper bound for NIG. |
| 510 | *. |
| 511 | ******************************************************************************/ |
| 512 | static void bnx2x_ets_e3b0_set_credit_upper_bound_nig( |
| 513 | const struct link_params *params, |
| 514 | const u32 min_w_val) |
| 515 | { |
| 516 | struct bnx2x *bp = params->bp; |
| 517 | const u8 port = params->port; |
| 518 | const u32 credit_upper_bound = |
| 519 | bnx2x_ets_get_credit_upper_bound(min_w_val); |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 520 | |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 521 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : |
| 522 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); |
| 523 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : |
| 524 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); |
| 525 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : |
| 526 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); |
| 527 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : |
| 528 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); |
| 529 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : |
| 530 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); |
| 531 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : |
| 532 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); |
| 533 | |
Yaniv Rosner | de0396f | 2011-11-28 00:49:53 +0000 | [diff] [blame] | 534 | if (!port) { |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 535 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, |
| 536 | credit_upper_bound); |
| 537 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, |
| 538 | credit_upper_bound); |
| 539 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, |
| 540 | credit_upper_bound); |
| 541 | } |
| 542 | } |
| 543 | /****************************************************************************** |
| 544 | * Description: |
| 545 | * Will return the NIG ETS registers to init values.Except |
| 546 | * credit_upper_bound. |
| 547 | * That isn't used in this configuration (No WFQ is enabled) and will be |
| 548 | * configured acording to spec |
| 549 | *. |
| 550 | ******************************************************************************/ |
| 551 | static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params, |
| 552 | const struct link_vars *vars) |
| 553 | { |
| 554 | struct bnx2x *bp = params->bp; |
| 555 | const u8 port = params->port; |
| 556 | const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 557 | /* Mapping between entry priority to client number (0,1,2 -debug and |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 558 | * management clients, 3 - COS0 client, 4 - COS1, ... 8 - |
| 559 | * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by |
| 560 | * reset value or init tool |
| 561 | */ |
| 562 | if (port) { |
| 563 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); |
| 564 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); |
| 565 | } else { |
| 566 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); |
| 567 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); |
| 568 | } |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 569 | /* For strict priority entries defines the number of consecutive |
| 570 | * slots for the highest priority. |
| 571 | */ |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 572 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : |
| 573 | NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 574 | /* Mapping between the CREDIT_WEIGHT registers and actual client |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 575 | * numbers |
| 576 | */ |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 577 | if (port) { |
| 578 | /*Port 1 has 6 COS*/ |
| 579 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); |
| 580 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); |
| 581 | } else { |
| 582 | /*Port 0 has 9 COS*/ |
| 583 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, |
| 584 | 0x43210876); |
| 585 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); |
| 586 | } |
| 587 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 588 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 589 | * as strict. Bits 0,1,2 - debug and management entries, 3 - |
| 590 | * COS0 entry, 4 - COS1 entry. |
| 591 | * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT |
| 592 | * bit4 bit3 bit2 bit1 bit0 |
| 593 | * MCP and debug are strict |
| 594 | */ |
| 595 | if (port) |
| 596 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); |
| 597 | else |
| 598 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); |
| 599 | /* defines which entries (clients) are subjected to WFQ arbitration */ |
| 600 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : |
| 601 | NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); |
| 602 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 603 | /* Please notice the register address are note continuous and a |
| 604 | * for here is note appropriate.In 2 port mode port0 only COS0-5 |
| 605 | * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 |
| 606 | * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT |
| 607 | * are never used for WFQ |
| 608 | */ |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 609 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : |
| 610 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); |
| 611 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : |
| 612 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); |
| 613 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : |
| 614 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); |
| 615 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : |
| 616 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); |
| 617 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : |
| 618 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); |
| 619 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : |
| 620 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); |
Yaniv Rosner | de0396f | 2011-11-28 00:49:53 +0000 | [diff] [blame] | 621 | if (!port) { |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 622 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); |
| 623 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); |
| 624 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); |
| 625 | } |
| 626 | |
| 627 | bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); |
| 628 | } |
| 629 | /****************************************************************************** |
| 630 | * Description: |
| 631 | * Set credit upper bound for PBF. |
| 632 | *. |
| 633 | ******************************************************************************/ |
| 634 | static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf( |
| 635 | const struct link_params *params, |
| 636 | const u32 min_w_val) |
| 637 | { |
| 638 | struct bnx2x *bp = params->bp; |
| 639 | const u32 credit_upper_bound = |
| 640 | bnx2x_ets_get_credit_upper_bound(min_w_val); |
| 641 | const u8 port = params->port; |
| 642 | u32 base_upper_bound = 0; |
| 643 | u8 max_cos = 0; |
| 644 | u8 i = 0; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 645 | /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 |
| 646 | * port mode port1 has COS0-2 that can be used for WFQ. |
| 647 | */ |
Yaniv Rosner | de0396f | 2011-11-28 00:49:53 +0000 | [diff] [blame] | 648 | if (!port) { |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 649 | base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; |
| 650 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; |
| 651 | } else { |
| 652 | base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; |
| 653 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; |
| 654 | } |
| 655 | |
| 656 | for (i = 0; i < max_cos; i++) |
| 657 | REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); |
| 658 | } |
| 659 | |
| 660 | /****************************************************************************** |
| 661 | * Description: |
| 662 | * Will return the PBF ETS registers to init values.Except |
| 663 | * credit_upper_bound. |
| 664 | * That isn't used in this configuration (No WFQ is enabled) and will be |
| 665 | * configured acording to spec |
| 666 | *. |
| 667 | ******************************************************************************/ |
| 668 | static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params) |
| 669 | { |
| 670 | struct bnx2x *bp = params->bp; |
| 671 | const u8 port = params->port; |
| 672 | const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; |
| 673 | u8 i = 0; |
| 674 | u32 base_weight = 0; |
| 675 | u8 max_cos = 0; |
| 676 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 677 | /* Mapping between entry priority to client number 0 - COS0 |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 678 | * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. |
| 679 | * TODO_ETS - Should be done by reset value or init tool |
| 680 | */ |
| 681 | if (port) |
| 682 | /* 0x688 (|011|0 10|00 1|000) */ |
| 683 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); |
| 684 | else |
| 685 | /* (10 1|100 |011|0 10|00 1|000) */ |
| 686 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); |
| 687 | |
| 688 | /* TODO_ETS - Should be done by reset value or init tool */ |
| 689 | if (port) |
| 690 | /* 0x688 (|011|0 10|00 1|000)*/ |
| 691 | REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); |
| 692 | else |
| 693 | /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ |
| 694 | REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); |
| 695 | |
| 696 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : |
| 697 | PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); |
| 698 | |
| 699 | |
| 700 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : |
| 701 | PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); |
| 702 | |
| 703 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : |
| 704 | PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 705 | /* In 2 port mode port0 has COS0-5 that can be used for WFQ. |
| 706 | * In 4 port mode port1 has COS0-2 that can be used for WFQ. |
| 707 | */ |
Yaniv Rosner | de0396f | 2011-11-28 00:49:53 +0000 | [diff] [blame] | 708 | if (!port) { |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 709 | base_weight = PBF_REG_COS0_WEIGHT_P0; |
| 710 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; |
| 711 | } else { |
| 712 | base_weight = PBF_REG_COS0_WEIGHT_P1; |
| 713 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; |
| 714 | } |
| 715 | |
| 716 | for (i = 0; i < max_cos; i++) |
| 717 | REG_WR(bp, base_weight + (0x4 * i), 0); |
| 718 | |
| 719 | bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); |
| 720 | } |
| 721 | /****************************************************************************** |
| 722 | * Description: |
| 723 | * E3B0 disable will return basicly the values to init values. |
| 724 | *. |
| 725 | ******************************************************************************/ |
| 726 | static int bnx2x_ets_e3b0_disabled(const struct link_params *params, |
| 727 | const struct link_vars *vars) |
| 728 | { |
| 729 | struct bnx2x *bp = params->bp; |
| 730 | |
| 731 | if (!CHIP_IS_E3B0(bp)) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 732 | DP(NETIF_MSG_LINK, |
| 733 | "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 734 | return -EINVAL; |
| 735 | } |
| 736 | |
| 737 | bnx2x_ets_e3b0_nig_disabled(params, vars); |
| 738 | |
| 739 | bnx2x_ets_e3b0_pbf_disabled(params); |
| 740 | |
| 741 | return 0; |
| 742 | } |
| 743 | |
| 744 | /****************************************************************************** |
| 745 | * Description: |
| 746 | * Disable will return basicly the values to init values. |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 747 | * |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 748 | ******************************************************************************/ |
| 749 | int bnx2x_ets_disabled(struct link_params *params, |
| 750 | struct link_vars *vars) |
| 751 | { |
| 752 | struct bnx2x *bp = params->bp; |
| 753 | int bnx2x_status = 0; |
| 754 | |
| 755 | if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp))) |
| 756 | bnx2x_ets_e2e3a0_disabled(params); |
| 757 | else if (CHIP_IS_E3B0(bp)) |
| 758 | bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars); |
| 759 | else { |
| 760 | DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n"); |
| 761 | return -EINVAL; |
| 762 | } |
| 763 | |
| 764 | return bnx2x_status; |
| 765 | } |
| 766 | |
| 767 | /****************************************************************************** |
| 768 | * Description |
| 769 | * Set the COS mappimg to SP and BW until this point all the COS are not |
| 770 | * set as SP or BW. |
| 771 | ******************************************************************************/ |
| 772 | static int bnx2x_ets_e3b0_cli_map(const struct link_params *params, |
| 773 | const struct bnx2x_ets_params *ets_params, |
| 774 | const u8 cos_sp_bitmap, |
| 775 | const u8 cos_bw_bitmap) |
| 776 | { |
| 777 | struct bnx2x *bp = params->bp; |
| 778 | const u8 port = params->port; |
| 779 | const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); |
| 780 | const u8 pbf_cli_sp_bitmap = cos_sp_bitmap; |
| 781 | const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; |
| 782 | const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; |
| 783 | |
| 784 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : |
| 785 | NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); |
| 786 | |
| 787 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : |
| 788 | PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); |
| 789 | |
| 790 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : |
| 791 | NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, |
| 792 | nig_cli_subject2wfq_bitmap); |
| 793 | |
| 794 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : |
| 795 | PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, |
| 796 | pbf_cli_subject2wfq_bitmap); |
| 797 | |
| 798 | return 0; |
| 799 | } |
| 800 | |
| 801 | /****************************************************************************** |
| 802 | * Description: |
| 803 | * This function is needed because NIG ARB_CREDIT_WEIGHT_X are |
| 804 | * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. |
| 805 | ******************************************************************************/ |
| 806 | static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, |
| 807 | const u8 cos_entry, |
| 808 | const u32 min_w_val_nig, |
| 809 | const u32 min_w_val_pbf, |
| 810 | const u16 total_bw, |
| 811 | const u8 bw, |
| 812 | const u8 port) |
| 813 | { |
| 814 | u32 nig_reg_adress_crd_weight = 0; |
| 815 | u32 pbf_reg_adress_crd_weight = 0; |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 816 | /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ |
| 817 | const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; |
| 818 | const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 819 | |
| 820 | switch (cos_entry) { |
| 821 | case 0: |
| 822 | nig_reg_adress_crd_weight = |
| 823 | (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : |
| 824 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; |
| 825 | pbf_reg_adress_crd_weight = (port) ? |
| 826 | PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; |
| 827 | break; |
| 828 | case 1: |
| 829 | nig_reg_adress_crd_weight = (port) ? |
| 830 | NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : |
| 831 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; |
| 832 | pbf_reg_adress_crd_weight = (port) ? |
| 833 | PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; |
| 834 | break; |
| 835 | case 2: |
| 836 | nig_reg_adress_crd_weight = (port) ? |
| 837 | NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : |
| 838 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; |
| 839 | |
| 840 | pbf_reg_adress_crd_weight = (port) ? |
| 841 | PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; |
| 842 | break; |
| 843 | case 3: |
| 844 | if (port) |
| 845 | return -EINVAL; |
| 846 | nig_reg_adress_crd_weight = |
| 847 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; |
| 848 | pbf_reg_adress_crd_weight = |
| 849 | PBF_REG_COS3_WEIGHT_P0; |
| 850 | break; |
| 851 | case 4: |
| 852 | if (port) |
| 853 | return -EINVAL; |
| 854 | nig_reg_adress_crd_weight = |
| 855 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; |
| 856 | pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; |
| 857 | break; |
| 858 | case 5: |
| 859 | if (port) |
| 860 | return -EINVAL; |
| 861 | nig_reg_adress_crd_weight = |
| 862 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; |
| 863 | pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; |
| 864 | break; |
| 865 | } |
| 866 | |
| 867 | REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); |
| 868 | |
| 869 | REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); |
| 870 | |
| 871 | return 0; |
| 872 | } |
| 873 | /****************************************************************************** |
| 874 | * Description: |
| 875 | * Calculate the total BW.A value of 0 isn't legal. |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 876 | * |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 877 | ******************************************************************************/ |
| 878 | static int bnx2x_ets_e3b0_get_total_bw( |
| 879 | const struct link_params *params, |
Yaniv Rosner | 870516e1 | 2011-11-28 00:49:46 +0000 | [diff] [blame] | 880 | struct bnx2x_ets_params *ets_params, |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 881 | u16 *total_bw) |
| 882 | { |
| 883 | struct bnx2x *bp = params->bp; |
| 884 | u8 cos_idx = 0; |
Yaniv Rosner | 870516e1 | 2011-11-28 00:49:46 +0000 | [diff] [blame] | 885 | u8 is_bw_cos_exist = 0; |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 886 | |
| 887 | *total_bw = 0 ; |
| 888 | /* Calculate total BW requested */ |
| 889 | for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { |
Yaniv Rosner | de0396f | 2011-11-28 00:49:53 +0000 | [diff] [blame] | 890 | if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) { |
Yaniv Rosner | 870516e1 | 2011-11-28 00:49:46 +0000 | [diff] [blame] | 891 | is_bw_cos_exist = 1; |
| 892 | if (!ets_params->cos[cos_idx].params.bw_params.bw) { |
| 893 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW" |
| 894 | "was set to 0\n"); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 895 | /* This is to prevent a state when ramrods |
Yaniv Rosner | 870516e1 | 2011-11-28 00:49:46 +0000 | [diff] [blame] | 896 | * can't be sent |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 897 | */ |
Yaniv Rosner | 870516e1 | 2011-11-28 00:49:46 +0000 | [diff] [blame] | 898 | ets_params->cos[cos_idx].params.bw_params.bw |
| 899 | = 1; |
| 900 | } |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 901 | *total_bw += |
| 902 | ets_params->cos[cos_idx].params.bw_params.bw; |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 903 | } |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 904 | } |
| 905 | |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 906 | /* Check total BW is valid */ |
Yaniv Rosner | de0396f | 2011-11-28 00:49:53 +0000 | [diff] [blame] | 907 | if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { |
| 908 | if (*total_bw == 0) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 909 | DP(NETIF_MSG_LINK, |
Yaniv Rosner | 2f751a8 | 2011-11-28 00:49:52 +0000 | [diff] [blame] | 910 | "bnx2x_ets_E3B0_config total BW shouldn't be 0\n"); |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 911 | return -EINVAL; |
| 912 | } |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 913 | DP(NETIF_MSG_LINK, |
Yaniv Rosner | 2f751a8 | 2011-11-28 00:49:52 +0000 | [diff] [blame] | 914 | "bnx2x_ets_E3B0_config total BW should be 100\n"); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 915 | /* We can handle a case whre the BW isn't 100 this can happen |
Yaniv Rosner | 2f751a8 | 2011-11-28 00:49:52 +0000 | [diff] [blame] | 916 | * if the TC are joined. |
| 917 | */ |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 918 | } |
| 919 | return 0; |
| 920 | } |
| 921 | |
| 922 | /****************************************************************************** |
| 923 | * Description: |
| 924 | * Invalidate all the sp_pri_to_cos. |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 925 | * |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 926 | ******************************************************************************/ |
| 927 | static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) |
| 928 | { |
| 929 | u8 pri = 0; |
| 930 | for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++) |
| 931 | sp_pri_to_cos[pri] = DCBX_INVALID_COS; |
| 932 | } |
| 933 | /****************************************************************************** |
| 934 | * Description: |
| 935 | * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers |
| 936 | * according to sp_pri_to_cos. |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 937 | * |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 938 | ******************************************************************************/ |
| 939 | static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params, |
| 940 | u8 *sp_pri_to_cos, const u8 pri, |
| 941 | const u8 cos_entry) |
| 942 | { |
| 943 | struct bnx2x *bp = params->bp; |
| 944 | const u8 port = params->port; |
| 945 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : |
| 946 | DCBX_E3B0_MAX_NUM_COS_PORT0; |
| 947 | |
Dan Carpenter | 7e5998a | 2012-04-17 20:53:42 +0000 | [diff] [blame] | 948 | if (pri >= max_num_of_cos) { |
| 949 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " |
| 950 | "parameter Illegal strict priority\n"); |
| 951 | return -EINVAL; |
| 952 | } |
| 953 | |
Yaniv Rosner | de0396f | 2011-11-28 00:49:53 +0000 | [diff] [blame] | 954 | if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 955 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 956 | "parameter There can't be two COS's with " |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 957 | "the same strict pri\n"); |
| 958 | return -EINVAL; |
| 959 | } |
| 960 | |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 961 | sp_pri_to_cos[pri] = cos_entry; |
| 962 | return 0; |
| 963 | |
| 964 | } |
| 965 | |
| 966 | /****************************************************************************** |
| 967 | * Description: |
| 968 | * Returns the correct value according to COS and priority in |
| 969 | * the sp_pri_cli register. |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 970 | * |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 971 | ******************************************************************************/ |
| 972 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, |
| 973 | const u8 pri_set, |
| 974 | const u8 pri_offset, |
| 975 | const u8 entry_size) |
| 976 | { |
| 977 | u64 pri_cli_nig = 0; |
| 978 | pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size * |
| 979 | (pri_set + pri_offset)); |
| 980 | |
| 981 | return pri_cli_nig; |
| 982 | } |
| 983 | /****************************************************************************** |
| 984 | * Description: |
| 985 | * Returns the correct value according to COS and priority in the |
| 986 | * sp_pri_cli register for NIG. |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 987 | * |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 988 | ******************************************************************************/ |
| 989 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) |
| 990 | { |
| 991 | /* MCP Dbg0 and dbg1 are always with higher strict pri*/ |
| 992 | const u8 nig_cos_offset = 3; |
| 993 | const u8 nig_pri_offset = 3; |
| 994 | |
| 995 | return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, |
| 996 | nig_pri_offset, 4); |
| 997 | |
| 998 | } |
| 999 | /****************************************************************************** |
| 1000 | * Description: |
| 1001 | * Returns the correct value according to COS and priority in the |
| 1002 | * sp_pri_cli register for PBF. |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1003 | * |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 1004 | ******************************************************************************/ |
| 1005 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) |
| 1006 | { |
| 1007 | const u8 pbf_cos_offset = 0; |
| 1008 | const u8 pbf_pri_offset = 0; |
| 1009 | |
| 1010 | return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, |
| 1011 | pbf_pri_offset, 3); |
| 1012 | |
| 1013 | } |
| 1014 | |
| 1015 | /****************************************************************************** |
| 1016 | * Description: |
| 1017 | * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers |
| 1018 | * according to sp_pri_to_cos.(which COS has higher priority) |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1019 | * |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 1020 | ******************************************************************************/ |
| 1021 | static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params, |
| 1022 | u8 *sp_pri_to_cos) |
| 1023 | { |
| 1024 | struct bnx2x *bp = params->bp; |
| 1025 | u8 i = 0; |
| 1026 | const u8 port = params->port; |
| 1027 | /* MCP Dbg0 and dbg1 are always with higher strict pri*/ |
| 1028 | u64 pri_cli_nig = 0x210; |
| 1029 | u32 pri_cli_pbf = 0x0; |
| 1030 | u8 pri_set = 0; |
| 1031 | u8 pri_bitmask = 0; |
| 1032 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : |
| 1033 | DCBX_E3B0_MAX_NUM_COS_PORT0; |
| 1034 | |
| 1035 | u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; |
| 1036 | |
| 1037 | /* Set all the strict priority first */ |
| 1038 | for (i = 0; i < max_num_of_cos; i++) { |
Yaniv Rosner | de0396f | 2011-11-28 00:49:53 +0000 | [diff] [blame] | 1039 | if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { |
| 1040 | if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) { |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 1041 | DP(NETIF_MSG_LINK, |
| 1042 | "bnx2x_ets_e3b0_sp_set_pri_cli_reg " |
| 1043 | "invalid cos entry\n"); |
| 1044 | return -EINVAL; |
| 1045 | } |
| 1046 | |
| 1047 | pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( |
| 1048 | sp_pri_to_cos[i], pri_set); |
| 1049 | |
| 1050 | pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( |
| 1051 | sp_pri_to_cos[i], pri_set); |
| 1052 | pri_bitmask = 1 << sp_pri_to_cos[i]; |
| 1053 | /* COS is used remove it from bitmap.*/ |
Yaniv Rosner | de0396f | 2011-11-28 00:49:53 +0000 | [diff] [blame] | 1054 | if (!(pri_bitmask & cos_bit_to_set)) { |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 1055 | DP(NETIF_MSG_LINK, |
| 1056 | "bnx2x_ets_e3b0_sp_set_pri_cli_reg " |
| 1057 | "invalid There can't be two COS's with" |
| 1058 | " the same strict pri\n"); |
| 1059 | return -EINVAL; |
| 1060 | } |
| 1061 | cos_bit_to_set &= ~pri_bitmask; |
| 1062 | pri_set++; |
| 1063 | } |
| 1064 | } |
| 1065 | |
| 1066 | /* Set all the Non strict priority i= COS*/ |
| 1067 | for (i = 0; i < max_num_of_cos; i++) { |
| 1068 | pri_bitmask = 1 << i; |
| 1069 | /* Check if COS was already used for SP */ |
| 1070 | if (pri_bitmask & cos_bit_to_set) { |
| 1071 | /* COS wasn't used for SP */ |
| 1072 | pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( |
| 1073 | i, pri_set); |
| 1074 | |
| 1075 | pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( |
| 1076 | i, pri_set); |
| 1077 | /* COS is used remove it from bitmap.*/ |
| 1078 | cos_bit_to_set &= ~pri_bitmask; |
| 1079 | pri_set++; |
| 1080 | } |
| 1081 | } |
| 1082 | |
| 1083 | if (pri_set != max_num_of_cos) { |
| 1084 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all " |
| 1085 | "entries were set\n"); |
| 1086 | return -EINVAL; |
| 1087 | } |
| 1088 | |
| 1089 | if (port) { |
| 1090 | /* Only 6 usable clients*/ |
| 1091 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, |
| 1092 | (u32)pri_cli_nig); |
| 1093 | |
| 1094 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); |
| 1095 | } else { |
| 1096 | /* Only 9 usable clients*/ |
| 1097 | const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig); |
| 1098 | const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); |
| 1099 | |
| 1100 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, |
| 1101 | pri_cli_nig_lsb); |
| 1102 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, |
| 1103 | pri_cli_nig_msb); |
| 1104 | |
| 1105 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); |
| 1106 | } |
| 1107 | return 0; |
| 1108 | } |
| 1109 | |
| 1110 | /****************************************************************************** |
| 1111 | * Description: |
| 1112 | * Configure the COS to ETS according to BW and SP settings. |
| 1113 | ******************************************************************************/ |
| 1114 | int bnx2x_ets_e3b0_config(const struct link_params *params, |
| 1115 | const struct link_vars *vars, |
Yaniv Rosner | 870516e1 | 2011-11-28 00:49:46 +0000 | [diff] [blame] | 1116 | struct bnx2x_ets_params *ets_params) |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 1117 | { |
| 1118 | struct bnx2x *bp = params->bp; |
| 1119 | int bnx2x_status = 0; |
| 1120 | const u8 port = params->port; |
| 1121 | u16 total_bw = 0; |
| 1122 | const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars); |
| 1123 | const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; |
| 1124 | u8 cos_bw_bitmap = 0; |
| 1125 | u8 cos_sp_bitmap = 0; |
| 1126 | u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0}; |
| 1127 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : |
| 1128 | DCBX_E3B0_MAX_NUM_COS_PORT0; |
| 1129 | u8 cos_entry = 0; |
| 1130 | |
| 1131 | if (!CHIP_IS_E3B0(bp)) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 1132 | DP(NETIF_MSG_LINK, |
| 1133 | "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 1134 | return -EINVAL; |
| 1135 | } |
| 1136 | |
| 1137 | if ((ets_params->num_of_cos > max_num_of_cos)) { |
| 1138 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS " |
| 1139 | "isn't supported\n"); |
| 1140 | return -EINVAL; |
| 1141 | } |
| 1142 | |
| 1143 | /* Prepare sp strict priority parameters*/ |
| 1144 | bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); |
| 1145 | |
| 1146 | /* Prepare BW parameters*/ |
| 1147 | bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params, |
| 1148 | &total_bw); |
Yaniv Rosner | de0396f | 2011-11-28 00:49:53 +0000 | [diff] [blame] | 1149 | if (bnx2x_status) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 1150 | DP(NETIF_MSG_LINK, |
| 1151 | "bnx2x_ets_E3B0_config get_total_bw failed\n"); |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 1152 | return -EINVAL; |
| 1153 | } |
| 1154 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1155 | /* Upper bound is set according to current link speed (min_w_val |
Yaniv Rosner | 2f751a8 | 2011-11-28 00:49:52 +0000 | [diff] [blame] | 1156 | * should be the same for upper bound and COS credit val). |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 1157 | */ |
| 1158 | bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); |
| 1159 | bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); |
| 1160 | |
| 1161 | |
| 1162 | for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { |
| 1163 | if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) { |
| 1164 | cos_bw_bitmap |= (1 << cos_entry); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1165 | /* The function also sets the BW in HW(not the mappin |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 1166 | * yet) |
| 1167 | */ |
| 1168 | bnx2x_status = bnx2x_ets_e3b0_set_cos_bw( |
| 1169 | bp, cos_entry, min_w_val_nig, min_w_val_pbf, |
| 1170 | total_bw, |
| 1171 | ets_params->cos[cos_entry].params.bw_params.bw, |
| 1172 | port); |
| 1173 | } else if (bnx2x_cos_state_strict == |
| 1174 | ets_params->cos[cos_entry].state){ |
| 1175 | cos_sp_bitmap |= (1 << cos_entry); |
| 1176 | |
| 1177 | bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set( |
| 1178 | params, |
| 1179 | sp_pri_to_cos, |
| 1180 | ets_params->cos[cos_entry].params.sp_params.pri, |
| 1181 | cos_entry); |
| 1182 | |
| 1183 | } else { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 1184 | DP(NETIF_MSG_LINK, |
| 1185 | "bnx2x_ets_e3b0_config cos state not valid\n"); |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 1186 | return -EINVAL; |
| 1187 | } |
Yaniv Rosner | de0396f | 2011-11-28 00:49:53 +0000 | [diff] [blame] | 1188 | if (bnx2x_status) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 1189 | DP(NETIF_MSG_LINK, |
| 1190 | "bnx2x_ets_e3b0_config set cos bw failed\n"); |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 1191 | return bnx2x_status; |
| 1192 | } |
| 1193 | } |
| 1194 | |
| 1195 | /* Set SP register (which COS has higher priority) */ |
| 1196 | bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params, |
| 1197 | sp_pri_to_cos); |
| 1198 | |
Yaniv Rosner | de0396f | 2011-11-28 00:49:53 +0000 | [diff] [blame] | 1199 | if (bnx2x_status) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 1200 | DP(NETIF_MSG_LINK, |
| 1201 | "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n"); |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 1202 | return bnx2x_status; |
| 1203 | } |
| 1204 | |
| 1205 | /* Set client mapping of BW and strict */ |
| 1206 | bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params, |
| 1207 | cos_sp_bitmap, |
| 1208 | cos_bw_bitmap); |
| 1209 | |
Yaniv Rosner | de0396f | 2011-11-28 00:49:53 +0000 | [diff] [blame] | 1210 | if (bnx2x_status) { |
Yaniv Rosner | 6c3218c | 2011-06-14 01:34:23 +0000 | [diff] [blame] | 1211 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n"); |
| 1212 | return bnx2x_status; |
| 1213 | } |
| 1214 | return 0; |
| 1215 | } |
Yaniv Rosner | 65a001b | 2011-01-31 04:22:03 +0000 | [diff] [blame] | 1216 | static void bnx2x_ets_bw_limit_common(const struct link_params *params) |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1217 | { |
| 1218 | /* ETS disabled configuration */ |
| 1219 | struct bnx2x *bp = params->bp; |
| 1220 | DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1221 | /* Defines which entries (clients) are subjected to WFQ arbitration |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 1222 | * COS0 0x8 |
| 1223 | * COS1 0x10 |
| 1224 | */ |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1225 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1226 | /* Mapping between the ARB_CREDIT_WEIGHT registers and actual |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 1227 | * client numbers (WEIGHT_0 does not actually have to represent |
| 1228 | * client 0) |
| 1229 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 |
| 1230 | * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 |
| 1231 | */ |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1232 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); |
| 1233 | |
| 1234 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, |
| 1235 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); |
| 1236 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, |
| 1237 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); |
| 1238 | |
| 1239 | /* ETS mode enabled*/ |
| 1240 | REG_WR(bp, PBF_REG_ETS_ENABLED, 1); |
| 1241 | |
| 1242 | /* Defines the number of consecutive slots for the strict priority */ |
| 1243 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1244 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 1245 | * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 |
| 1246 | * entry, 4 - COS1 entry. |
| 1247 | * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT |
| 1248 | * bit4 bit3 bit2 bit1 bit0 |
| 1249 | * MCP and debug are strict |
| 1250 | */ |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1251 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); |
| 1252 | |
| 1253 | /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ |
| 1254 | REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, |
| 1255 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); |
| 1256 | REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, |
| 1257 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); |
| 1258 | } |
| 1259 | |
| 1260 | void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, |
| 1261 | const u32 cos1_bw) |
| 1262 | { |
| 1263 | /* ETS disabled configuration*/ |
| 1264 | struct bnx2x *bp = params->bp; |
| 1265 | const u32 total_bw = cos0_bw + cos1_bw; |
| 1266 | u32 cos0_credit_weight = 0; |
| 1267 | u32 cos1_credit_weight = 0; |
| 1268 | |
| 1269 | DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); |
| 1270 | |
Yaniv Rosner | de0396f | 2011-11-28 00:49:53 +0000 | [diff] [blame] | 1271 | if ((!total_bw) || |
| 1272 | (!cos0_bw) || |
| 1273 | (!cos1_bw)) { |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 1274 | DP(NETIF_MSG_LINK, "Total BW can't be zero\n"); |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1275 | return; |
| 1276 | } |
| 1277 | |
| 1278 | cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ |
| 1279 | total_bw; |
| 1280 | cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ |
| 1281 | total_bw; |
| 1282 | |
| 1283 | bnx2x_ets_bw_limit_common(params); |
| 1284 | |
| 1285 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); |
| 1286 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); |
| 1287 | |
| 1288 | REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); |
| 1289 | REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); |
| 1290 | } |
| 1291 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 1292 | int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos) |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1293 | { |
| 1294 | /* ETS disabled configuration*/ |
| 1295 | struct bnx2x *bp = params->bp; |
| 1296 | u32 val = 0; |
| 1297 | |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1298 | DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n"); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1299 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1300 | * as strict. Bits 0,1,2 - debug and management entries, |
| 1301 | * 3 - COS0 entry, 4 - COS1 entry. |
| 1302 | * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT |
| 1303 | * bit4 bit3 bit2 bit1 bit0 |
| 1304 | * MCP and debug are strict |
| 1305 | */ |
| 1306 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1307 | /* For strict priority entries defines the number of consecutive slots |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1308 | * for the highest priority. |
| 1309 | */ |
| 1310 | REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); |
| 1311 | /* ETS mode disable */ |
| 1312 | REG_WR(bp, PBF_REG_ETS_ENABLED, 0); |
| 1313 | /* Defines the number of consecutive slots for the strict priority */ |
| 1314 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); |
| 1315 | |
| 1316 | /* Defines the number of consecutive slots for the strict priority */ |
| 1317 | REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); |
| 1318 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1319 | /* Mapping between entry priority to client number (0,1,2 -debug and |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 1320 | * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) |
| 1321 | * 3bits client num. |
| 1322 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 |
| 1323 | * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 |
| 1324 | * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 |
| 1325 | */ |
Yaniv Rosner | de0396f | 2011-11-28 00:49:53 +0000 | [diff] [blame] | 1326 | val = (!strict_cos) ? 0x2318 : 0x22E0; |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1327 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); |
| 1328 | |
| 1329 | return 0; |
| 1330 | } |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 1331 | |
| 1332 | /******************************************************************/ |
Dmitry Kravkov | e892067 | 2011-05-04 23:52:40 +0000 | [diff] [blame] | 1333 | /* PFC section */ |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1334 | /******************************************************************/ |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1335 | static void bnx2x_update_pfc_xmac(struct link_params *params, |
| 1336 | struct link_vars *vars, |
| 1337 | u8 is_lb) |
| 1338 | { |
| 1339 | struct bnx2x *bp = params->bp; |
| 1340 | u32 xmac_base; |
| 1341 | u32 pause_val, pfc0_val, pfc1_val; |
| 1342 | |
| 1343 | /* XMAC base adrr */ |
| 1344 | xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; |
| 1345 | |
| 1346 | /* Initialize pause and pfc registers */ |
| 1347 | pause_val = 0x18000; |
| 1348 | pfc0_val = 0xFFFF8000; |
| 1349 | pfc1_val = 0x2; |
| 1350 | |
| 1351 | /* No PFC support */ |
| 1352 | if (!(params->feature_config_flags & |
| 1353 | FEATURE_CONFIG_PFC_ENABLED)) { |
| 1354 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1355 | /* RX flow control - Process pause frame in receive direction |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1356 | */ |
| 1357 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) |
| 1358 | pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; |
| 1359 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1360 | /* TX flow control - Send pause packet when buffer is full */ |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1361 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
| 1362 | pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; |
| 1363 | } else {/* PFC support */ |
| 1364 | pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | |
| 1365 | XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | |
| 1366 | XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | |
Yaniv Rosner | 27d9129 | 2012-04-04 01:28:54 +0000 | [diff] [blame] | 1367 | XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | |
| 1368 | XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; |
| 1369 | /* Write pause and PFC registers */ |
| 1370 | REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); |
| 1371 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); |
| 1372 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); |
| 1373 | pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; |
| 1374 | |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1375 | } |
| 1376 | |
| 1377 | /* Write pause and PFC registers */ |
| 1378 | REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); |
| 1379 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); |
| 1380 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); |
| 1381 | |
Yaniv Rosner | b8d6d08 | 2011-07-05 01:06:27 +0000 | [diff] [blame] | 1382 | |
| 1383 | /* Set MAC address for source TX Pause/PFC frames */ |
| 1384 | REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, |
| 1385 | ((params->mac_addr[2] << 24) | |
| 1386 | (params->mac_addr[3] << 16) | |
| 1387 | (params->mac_addr[4] << 8) | |
| 1388 | (params->mac_addr[5]))); |
| 1389 | REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, |
| 1390 | ((params->mac_addr[0] << 8) | |
| 1391 | (params->mac_addr[1]))); |
| 1392 | |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1393 | udelay(30); |
| 1394 | } |
| 1395 | |
| 1396 | |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1397 | static void bnx2x_emac_get_pfc_stat(struct link_params *params, |
| 1398 | u32 pfc_frames_sent[2], |
| 1399 | u32 pfc_frames_received[2]) |
| 1400 | { |
| 1401 | /* Read pfc statistic */ |
| 1402 | struct bnx2x *bp = params->bp; |
| 1403 | u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
| 1404 | u32 val_xon = 0; |
| 1405 | u32 val_xoff = 0; |
| 1406 | |
| 1407 | DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n"); |
| 1408 | |
| 1409 | /* PFC received frames */ |
| 1410 | val_xoff = REG_RD(bp, emac_base + |
| 1411 | EMAC_REG_RX_PFC_STATS_XOFF_RCVD); |
| 1412 | val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT; |
| 1413 | val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD); |
| 1414 | val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT; |
| 1415 | |
| 1416 | pfc_frames_received[0] = val_xon + val_xoff; |
| 1417 | |
| 1418 | /* PFC received sent */ |
| 1419 | val_xoff = REG_RD(bp, emac_base + |
| 1420 | EMAC_REG_RX_PFC_STATS_XOFF_SENT); |
| 1421 | val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT; |
| 1422 | val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT); |
| 1423 | val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT; |
| 1424 | |
| 1425 | pfc_frames_sent[0] = val_xon + val_xoff; |
| 1426 | } |
| 1427 | |
Yaniv Rosner | b8d6d08 | 2011-07-05 01:06:27 +0000 | [diff] [blame] | 1428 | /* Read pfc statistic*/ |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1429 | void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars, |
| 1430 | u32 pfc_frames_sent[2], |
| 1431 | u32 pfc_frames_received[2]) |
| 1432 | { |
| 1433 | /* Read pfc statistic */ |
| 1434 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | b8d6d08 | 2011-07-05 01:06:27 +0000 | [diff] [blame] | 1435 | |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1436 | DP(NETIF_MSG_LINK, "pfc statistic\n"); |
| 1437 | |
| 1438 | if (!vars->link_up) |
| 1439 | return; |
| 1440 | |
Yaniv Rosner | de0396f | 2011-11-28 00:49:53 +0000 | [diff] [blame] | 1441 | if (vars->mac_type == MAC_TYPE_EMAC) { |
Yaniv Rosner | b8d6d08 | 2011-07-05 01:06:27 +0000 | [diff] [blame] | 1442 | DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n"); |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1443 | bnx2x_emac_get_pfc_stat(params, pfc_frames_sent, |
| 1444 | pfc_frames_received); |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1445 | } |
| 1446 | } |
| 1447 | /******************************************************************/ |
| 1448 | /* MAC/PBF section */ |
| 1449 | /******************************************************************/ |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 1450 | static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, |
| 1451 | u32 emac_base) |
Yaniv Rosner | a198c14 | 2011-05-31 21:29:42 +0000 | [diff] [blame] | 1452 | { |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 1453 | u32 new_mode, cur_mode; |
| 1454 | u32 clc_cnt; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1455 | /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz |
Yaniv Rosner | a198c14 | 2011-05-31 21:29:42 +0000 | [diff] [blame] | 1456 | * (a value of 49==0x31) and make sure that the AUTO poll is off |
| 1457 | */ |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 1458 | cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); |
Yaniv Rosner | a198c14 | 2011-05-31 21:29:42 +0000 | [diff] [blame] | 1459 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 1460 | if (USES_WARPCORE(bp)) |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 1461 | clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 1462 | else |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 1463 | clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; |
Yaniv Rosner | a198c14 | 2011-05-31 21:29:42 +0000 | [diff] [blame] | 1464 | |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 1465 | if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) && |
| 1466 | (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45))) |
| 1467 | return; |
Yaniv Rosner | a198c14 | 2011-05-31 21:29:42 +0000 | [diff] [blame] | 1468 | |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 1469 | new_mode = cur_mode & |
| 1470 | ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); |
| 1471 | new_mode |= clc_cnt; |
| 1472 | new_mode |= (EMAC_MDIO_MODE_CLAUSE_45); |
| 1473 | |
| 1474 | DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n", |
| 1475 | cur_mode, new_mode); |
| 1476 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); |
Yaniv Rosner | a198c14 | 2011-05-31 21:29:42 +0000 | [diff] [blame] | 1477 | udelay(40); |
| 1478 | } |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 1479 | |
| 1480 | static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp, |
| 1481 | struct link_params *params) |
| 1482 | { |
| 1483 | u8 phy_index; |
| 1484 | /* Set mdio clock per phy */ |
| 1485 | for (phy_index = INT_PHY; phy_index < params->num_phys; |
| 1486 | phy_index++) |
| 1487 | bnx2x_set_mdio_clk(bp, params->chip_id, |
| 1488 | params->phy[phy_index].mdio_ctrl); |
| 1489 | } |
| 1490 | |
Yaniv Rosner | 2f751a8 | 2011-11-28 00:49:52 +0000 | [diff] [blame] | 1491 | static u8 bnx2x_is_4_port_mode(struct bnx2x *bp) |
| 1492 | { |
| 1493 | u32 port4mode_ovwr_val; |
| 1494 | /* Check 4-port override enabled */ |
| 1495 | port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); |
| 1496 | if (port4mode_ovwr_val & (1<<0)) { |
| 1497 | /* Return 4-port mode override value */ |
| 1498 | return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); |
| 1499 | } |
| 1500 | /* Return 4-port mode from input pin */ |
| 1501 | return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); |
| 1502 | } |
Yaniv Rosner | a198c14 | 2011-05-31 21:29:42 +0000 | [diff] [blame] | 1503 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1504 | static void bnx2x_emac_init(struct link_params *params, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 1505 | struct link_vars *vars) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1506 | { |
| 1507 | /* reset and unreset the emac core */ |
| 1508 | struct bnx2x *bp = params->bp; |
| 1509 | u8 port = params->port; |
| 1510 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
| 1511 | u32 val; |
| 1512 | u16 timeout; |
| 1513 | |
| 1514 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 1515 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1516 | udelay(5); |
| 1517 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 1518 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1519 | |
| 1520 | /* init emac - use read-modify-write */ |
| 1521 | /* self clear reset */ |
| 1522 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 1523 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1524 | |
| 1525 | timeout = 200; |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 1526 | do { |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1527 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); |
| 1528 | DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); |
| 1529 | if (!timeout) { |
| 1530 | DP(NETIF_MSG_LINK, "EMAC timeout!\n"); |
| 1531 | return; |
| 1532 | } |
| 1533 | timeout--; |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 1534 | } while (val & EMAC_MODE_RESET); |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 1535 | |
| 1536 | bnx2x_set_mdio_emac_per_phy(bp, params); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1537 | /* Set mac address */ |
| 1538 | val = ((params->mac_addr[0] << 8) | |
| 1539 | params->mac_addr[1]); |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 1540 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1541 | |
| 1542 | val = ((params->mac_addr[2] << 24) | |
| 1543 | (params->mac_addr[3] << 16) | |
| 1544 | (params->mac_addr[4] << 8) | |
| 1545 | params->mac_addr[5]); |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 1546 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1547 | } |
| 1548 | |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1549 | static void bnx2x_set_xumac_nig(struct link_params *params, |
| 1550 | u16 tx_pause_en, |
| 1551 | u8 enable) |
| 1552 | { |
| 1553 | struct bnx2x *bp = params->bp; |
| 1554 | |
| 1555 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, |
| 1556 | enable); |
| 1557 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, |
| 1558 | enable); |
| 1559 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : |
| 1560 | NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); |
| 1561 | } |
| 1562 | |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 1563 | static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en) |
Yaniv Rosner | ce7c048 | 2011-10-27 05:09:47 +0000 | [diff] [blame] | 1564 | { |
| 1565 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 1566 | u32 val; |
Yaniv Rosner | ce7c048 | 2011-10-27 05:09:47 +0000 | [diff] [blame] | 1567 | struct bnx2x *bp = params->bp; |
| 1568 | if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & |
| 1569 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) |
| 1570 | return; |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 1571 | val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG); |
| 1572 | if (en) |
| 1573 | val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | |
| 1574 | UMAC_COMMAND_CONFIG_REG_RX_ENA); |
| 1575 | else |
| 1576 | val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | |
| 1577 | UMAC_COMMAND_CONFIG_REG_RX_ENA); |
Yaniv Rosner | ce7c048 | 2011-10-27 05:09:47 +0000 | [diff] [blame] | 1578 | /* Disable RX and TX */ |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 1579 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); |
Yaniv Rosner | ce7c048 | 2011-10-27 05:09:47 +0000 | [diff] [blame] | 1580 | } |
| 1581 | |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1582 | static void bnx2x_umac_enable(struct link_params *params, |
| 1583 | struct link_vars *vars, u8 lb) |
| 1584 | { |
| 1585 | u32 val; |
| 1586 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; |
| 1587 | struct bnx2x *bp = params->bp; |
| 1588 | /* Reset UMAC */ |
| 1589 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
| 1590 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 1591 | usleep_range(1000, 2000); |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1592 | |
| 1593 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
| 1594 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); |
| 1595 | |
| 1596 | DP(NETIF_MSG_LINK, "enabling UMAC\n"); |
| 1597 | |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1598 | /* This register opens the gate for the UMAC despite its name */ |
| 1599 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); |
| 1600 | |
| 1601 | val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | |
| 1602 | UMAC_COMMAND_CONFIG_REG_PAD_EN | |
| 1603 | UMAC_COMMAND_CONFIG_REG_SW_RESET | |
| 1604 | UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; |
| 1605 | switch (vars->line_speed) { |
| 1606 | case SPEED_10: |
| 1607 | val |= (0<<2); |
| 1608 | break; |
| 1609 | case SPEED_100: |
| 1610 | val |= (1<<2); |
| 1611 | break; |
| 1612 | case SPEED_1000: |
| 1613 | val |= (2<<2); |
| 1614 | break; |
| 1615 | case SPEED_2500: |
| 1616 | val |= (3<<2); |
| 1617 | break; |
| 1618 | default: |
| 1619 | DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n", |
| 1620 | vars->line_speed); |
| 1621 | break; |
| 1622 | } |
Yaniv Rosner | 9d5b36b | 2011-08-02 22:59:10 +0000 | [diff] [blame] | 1623 | if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) |
| 1624 | val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; |
| 1625 | |
| 1626 | if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) |
| 1627 | val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; |
| 1628 | |
Mintz Yuval | e18c56b | 2012-02-15 02:10:23 +0000 | [diff] [blame] | 1629 | if (vars->duplex == DUPLEX_HALF) |
| 1630 | val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; |
| 1631 | |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1632 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); |
| 1633 | udelay(50); |
| 1634 | |
Yuval Mintz | 26964bb | 2012-09-10 05:51:08 +0000 | [diff] [blame] | 1635 | /* Configure UMAC for EEE */ |
| 1636 | if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { |
| 1637 | DP(NETIF_MSG_LINK, "configured UMAC for EEE\n"); |
| 1638 | REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, |
| 1639 | UMAC_UMAC_EEE_CTRL_REG_EEE_EN); |
| 1640 | REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); |
| 1641 | } else { |
| 1642 | REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); |
| 1643 | } |
| 1644 | |
Yaniv Rosner | b8d6d08 | 2011-07-05 01:06:27 +0000 | [diff] [blame] | 1645 | /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ |
| 1646 | REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, |
| 1647 | ((params->mac_addr[2] << 24) | |
| 1648 | (params->mac_addr[3] << 16) | |
| 1649 | (params->mac_addr[4] << 8) | |
| 1650 | (params->mac_addr[5]))); |
| 1651 | REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, |
| 1652 | ((params->mac_addr[0] << 8) | |
| 1653 | (params->mac_addr[1]))); |
| 1654 | |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1655 | /* Enable RX and TX */ |
| 1656 | val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; |
| 1657 | val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 1658 | UMAC_COMMAND_CONFIG_REG_RX_ENA; |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1659 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); |
| 1660 | udelay(50); |
| 1661 | |
| 1662 | /* Remove SW Reset */ |
| 1663 | val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; |
| 1664 | |
| 1665 | /* Check loopback mode */ |
| 1666 | if (lb) |
| 1667 | val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; |
| 1668 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); |
| 1669 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1670 | /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1671 | * length used by the MAC receive logic to check frames. |
| 1672 | */ |
| 1673 | REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); |
| 1674 | bnx2x_set_xumac_nig(params, |
| 1675 | ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); |
| 1676 | vars->mac_type = MAC_TYPE_UMAC; |
| 1677 | |
| 1678 | } |
| 1679 | |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1680 | /* Define the XMAC mode */ |
Yaniv Rosner | ce7c048 | 2011-10-27 05:09:47 +0000 | [diff] [blame] | 1681 | static void bnx2x_xmac_init(struct link_params *params, u32 max_speed) |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1682 | { |
Yaniv Rosner | ce7c048 | 2011-10-27 05:09:47 +0000 | [diff] [blame] | 1683 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1684 | u32 is_port4mode = bnx2x_is_4_port_mode(bp); |
| 1685 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1686 | /* In 4-port mode, need to set the mode only once, so if XMAC is |
Yaniv Rosner | 2f751a8 | 2011-11-28 00:49:52 +0000 | [diff] [blame] | 1687 | * already out of reset, it means the mode has already been set, |
| 1688 | * and it must not* reset the XMAC again, since it controls both |
| 1689 | * ports of the path |
| 1690 | */ |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1691 | |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 1692 | if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || |
| 1693 | (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || |
| 1694 | (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) && |
| 1695 | is_port4mode && |
Yaniv Rosner | ce7c048 | 2011-10-27 05:09:47 +0000 | [diff] [blame] | 1696 | (REG_RD(bp, MISC_REG_RESET_REG_2) & |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1697 | MISC_REGISTERS_RESET_REG_2_XMAC)) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 1698 | DP(NETIF_MSG_LINK, |
| 1699 | "XMAC already out of reset in 4-port mode\n"); |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1700 | return; |
| 1701 | } |
| 1702 | |
| 1703 | /* Hard reset */ |
| 1704 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
| 1705 | MISC_REGISTERS_RESET_REG_2_XMAC); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 1706 | usleep_range(1000, 2000); |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1707 | |
| 1708 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
| 1709 | MISC_REGISTERS_RESET_REG_2_XMAC); |
| 1710 | if (is_port4mode) { |
| 1711 | DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n"); |
| 1712 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1713 | /* Set the number of ports on the system side to up to 2 */ |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1714 | REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); |
| 1715 | |
| 1716 | /* Set the number of ports on the Warp Core to 10G */ |
| 1717 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); |
| 1718 | } else { |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1719 | /* Set the number of ports on the system side to 1 */ |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1720 | REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); |
| 1721 | if (max_speed == SPEED_10000) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 1722 | DP(NETIF_MSG_LINK, |
| 1723 | "Init XMAC to 10G x 1 port per path\n"); |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1724 | /* Set the number of ports on the Warp Core to 10G */ |
| 1725 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); |
| 1726 | } else { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 1727 | DP(NETIF_MSG_LINK, |
| 1728 | "Init XMAC to 20G x 2 ports per path\n"); |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1729 | /* Set the number of ports on the Warp Core to 20G */ |
| 1730 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); |
| 1731 | } |
| 1732 | } |
| 1733 | /* Soft reset */ |
| 1734 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
| 1735 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 1736 | usleep_range(1000, 2000); |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1737 | |
| 1738 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
| 1739 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); |
| 1740 | |
| 1741 | } |
| 1742 | |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 1743 | static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en) |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1744 | { |
| 1745 | u8 port = params->port; |
| 1746 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | b507766 | 2011-08-02 22:59:18 +0000 | [diff] [blame] | 1747 | u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 1748 | u32 val; |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1749 | |
| 1750 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & |
| 1751 | MISC_REGISTERS_RESET_REG_2_XMAC) { |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1752 | /* Send an indication to change the state in the NIG back to XON |
Yaniv Rosner | b507766 | 2011-08-02 22:59:18 +0000 | [diff] [blame] | 1753 | * Clearing this bit enables the next set of this bit to get |
| 1754 | * rising edge |
| 1755 | */ |
| 1756 | pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); |
| 1757 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, |
| 1758 | (pfc_ctrl & ~(1<<1))); |
| 1759 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, |
| 1760 | (pfc_ctrl | (1<<1))); |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1761 | DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port); |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 1762 | val = REG_RD(bp, xmac_base + XMAC_REG_CTRL); |
| 1763 | if (en) |
| 1764 | val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); |
| 1765 | else |
| 1766 | val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); |
| 1767 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1768 | } |
| 1769 | } |
| 1770 | |
| 1771 | static int bnx2x_xmac_enable(struct link_params *params, |
| 1772 | struct link_vars *vars, u8 lb) |
| 1773 | { |
| 1774 | u32 val, xmac_base; |
| 1775 | struct bnx2x *bp = params->bp; |
| 1776 | DP(NETIF_MSG_LINK, "enabling XMAC\n"); |
| 1777 | |
| 1778 | xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; |
| 1779 | |
Yaniv Rosner | ce7c048 | 2011-10-27 05:09:47 +0000 | [diff] [blame] | 1780 | bnx2x_xmac_init(params, vars->line_speed); |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1781 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1782 | /* This register determines on which events the MAC will assert |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1783 | * error on the i/f to the NIG along w/ EOP. |
| 1784 | */ |
| 1785 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1786 | /* This register tells the NIG whether to send traffic to UMAC |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1787 | * or XMAC |
| 1788 | */ |
| 1789 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); |
| 1790 | |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 1791 | /* When XMAC is in XLGMII mode, disable sending idles for fault |
| 1792 | * detection. |
| 1793 | */ |
| 1794 | if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) { |
| 1795 | REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL, |
| 1796 | (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE | |
| 1797 | XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE)); |
| 1798 | REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); |
| 1799 | REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, |
| 1800 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | |
| 1801 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); |
| 1802 | } |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1803 | /* Set Max packet size */ |
| 1804 | REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); |
| 1805 | |
| 1806 | /* CRC append for Tx packets */ |
| 1807 | REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); |
| 1808 | |
| 1809 | /* update PFC */ |
| 1810 | bnx2x_update_pfc_xmac(params, vars, 0); |
| 1811 | |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 1812 | if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { |
| 1813 | DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n"); |
| 1814 | REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); |
| 1815 | REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); |
| 1816 | } else { |
| 1817 | REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); |
| 1818 | } |
| 1819 | |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1820 | /* Enable TX and RX */ |
| 1821 | val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; |
| 1822 | |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 1823 | /* Set MAC in XLGMII mode for dual-mode */ |
| 1824 | if ((vars->line_speed == SPEED_20000) && |
| 1825 | (params->phy[INT_PHY].supported & |
| 1826 | SUPPORTED_20000baseKR2_Full)) |
| 1827 | val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB; |
| 1828 | |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1829 | /* Check loopback mode */ |
| 1830 | if (lb) |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 1831 | val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 1832 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); |
| 1833 | bnx2x_set_xumac_nig(params, |
| 1834 | ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); |
| 1835 | |
| 1836 | vars->mac_type = MAC_TYPE_XMAC; |
| 1837 | |
| 1838 | return 0; |
| 1839 | } |
Yaniv Rosner | 2f751a8 | 2011-11-28 00:49:52 +0000 | [diff] [blame] | 1840 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 1841 | static int bnx2x_emac_enable(struct link_params *params, |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 1842 | struct link_vars *vars, u8 lb) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1843 | { |
| 1844 | struct bnx2x *bp = params->bp; |
| 1845 | u8 port = params->port; |
| 1846 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
| 1847 | u32 val; |
| 1848 | |
| 1849 | DP(NETIF_MSG_LINK, "enabling EMAC\n"); |
| 1850 | |
Yaniv Rosner | de6f337 | 2011-08-02 22:59:25 +0000 | [diff] [blame] | 1851 | /* Disable BMAC */ |
| 1852 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
| 1853 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
| 1854 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1855 | /* enable emac and not bmac */ |
| 1856 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); |
| 1857 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1858 | /* ASIC */ |
| 1859 | if (vars->phy_flags & PHY_XGXS_FLAG) { |
| 1860 | u32 ser_lane = ((params->lane_config & |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 1861 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
| 1862 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1863 | |
| 1864 | DP(NETIF_MSG_LINK, "XGXS\n"); |
| 1865 | /* select the master lanes (out of 0-3) */ |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 1866 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1867 | /* select XGXS */ |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 1868 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1869 | |
| 1870 | } else { /* SerDes */ |
| 1871 | DP(NETIF_MSG_LINK, "SerDes\n"); |
| 1872 | /* select SerDes */ |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 1873 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1874 | } |
| 1875 | |
Eilon Greenstein | 811a2f2 | 2009-02-12 08:37:04 +0000 | [diff] [blame] | 1876 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 1877 | EMAC_RX_MODE_RESET); |
Eilon Greenstein | 811a2f2 | 2009-02-12 08:37:04 +0000 | [diff] [blame] | 1878 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 1879 | EMAC_TX_MODE_RESET); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1880 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1881 | /* pause enable/disable */ |
| 1882 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, |
| 1883 | EMAC_RX_MODE_FLOW_EN); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1884 | |
| 1885 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1886 | (EMAC_TX_MODE_EXT_PAUSE_EN | |
| 1887 | EMAC_TX_MODE_FLOW_EN)); |
| 1888 | if (!(params->feature_config_flags & |
| 1889 | FEATURE_CONFIG_PFC_ENABLED)) { |
| 1890 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) |
| 1891 | bnx2x_bits_en(bp, emac_base + |
| 1892 | EMAC_REG_EMAC_RX_MODE, |
| 1893 | EMAC_RX_MODE_FLOW_EN); |
| 1894 | |
| 1895 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
| 1896 | bnx2x_bits_en(bp, emac_base + |
| 1897 | EMAC_REG_EMAC_TX_MODE, |
| 1898 | (EMAC_TX_MODE_EXT_PAUSE_EN | |
| 1899 | EMAC_TX_MODE_FLOW_EN)); |
| 1900 | } else |
| 1901 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, |
| 1902 | EMAC_TX_MODE_FLOW_EN); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1903 | |
| 1904 | /* KEEP_VLAN_TAG, promiscuous */ |
| 1905 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); |
| 1906 | val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1907 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 1908 | /* Setting this bit causes MAC control frames (except for pause |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 1909 | * frames) to be passed on for processing. This setting has no |
| 1910 | * affect on the operation of the pause frames. This bit effects |
| 1911 | * all packets regardless of RX Parser packet sorting logic. |
| 1912 | * Turn the PFC off to make sure we are in Xon state before |
| 1913 | * enabling it. |
| 1914 | */ |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1915 | EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); |
| 1916 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { |
| 1917 | DP(NETIF_MSG_LINK, "PFC is enabled\n"); |
| 1918 | /* Enable PFC again */ |
| 1919 | EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, |
| 1920 | EMAC_REG_RX_PFC_MODE_RX_EN | |
| 1921 | EMAC_REG_RX_PFC_MODE_TX_EN | |
| 1922 | EMAC_REG_RX_PFC_MODE_PRIORITIES); |
| 1923 | |
| 1924 | EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, |
| 1925 | ((0x0101 << |
| 1926 | EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | |
| 1927 | (0x00ff << |
| 1928 | EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); |
| 1929 | val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; |
| 1930 | } |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 1931 | EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1932 | |
| 1933 | /* Set Loopback */ |
| 1934 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); |
| 1935 | if (lb) |
| 1936 | val |= 0x810; |
| 1937 | else |
| 1938 | val &= ~0x810; |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 1939 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1940 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 1941 | /* Enable emac */ |
Eilon Greenstein | 6c55c3cd | 2009-01-14 06:44:13 +0000 | [diff] [blame] | 1942 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); |
| 1943 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 1944 | /* Enable emac for jumbo packets */ |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 1945 | EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1946 | (EMAC_RX_MTU_SIZE_JUMBO_ENA | |
| 1947 | (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); |
| 1948 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 1949 | /* Strip CRC */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1950 | REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); |
| 1951 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 1952 | /* Disable the NIG in/out to the bmac */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1953 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); |
| 1954 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); |
| 1955 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); |
| 1956 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 1957 | /* Enable the NIG in/out to the emac */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1958 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); |
| 1959 | val = 0; |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1960 | if ((params->feature_config_flags & |
| 1961 | FEATURE_CONFIG_PFC_ENABLED) || |
| 1962 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1963 | val = 1; |
| 1964 | |
| 1965 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); |
| 1966 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); |
| 1967 | |
Yaniv Rosner | 02a2316 | 2011-01-31 04:22:53 +0000 | [diff] [blame] | 1968 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 1969 | |
| 1970 | vars->mac_type = MAC_TYPE_EMAC; |
| 1971 | return 0; |
| 1972 | } |
| 1973 | |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1974 | static void bnx2x_update_pfc_bmac1(struct link_params *params, |
| 1975 | struct link_vars *vars) |
| 1976 | { |
| 1977 | u32 wb_data[2]; |
| 1978 | struct bnx2x *bp = params->bp; |
| 1979 | u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : |
| 1980 | NIG_REG_INGRESS_BMAC0_MEM; |
| 1981 | |
| 1982 | u32 val = 0x14; |
| 1983 | if ((!(params->feature_config_flags & |
| 1984 | FEATURE_CONFIG_PFC_ENABLED)) && |
| 1985 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) |
| 1986 | /* Enable BigMAC to react on received Pause packets */ |
| 1987 | val |= (1<<5); |
| 1988 | wb_data[0] = val; |
| 1989 | wb_data[1] = 0; |
| 1990 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); |
| 1991 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 1992 | /* TX control */ |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 1993 | val = 0xc0; |
| 1994 | if (!(params->feature_config_flags & |
| 1995 | FEATURE_CONFIG_PFC_ENABLED) && |
| 1996 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) |
| 1997 | val |= 0x800000; |
| 1998 | wb_data[0] = val; |
| 1999 | wb_data[1] = 0; |
| 2000 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); |
| 2001 | } |
| 2002 | |
| 2003 | static void bnx2x_update_pfc_bmac2(struct link_params *params, |
| 2004 | struct link_vars *vars, |
| 2005 | u8 is_lb) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2006 | { |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 2007 | /* Set rx control: Strip CRC and enable BigMAC to relay |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2008 | * control packets to the system as well |
| 2009 | */ |
| 2010 | u32 wb_data[2]; |
| 2011 | struct bnx2x *bp = params->bp; |
| 2012 | u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : |
| 2013 | NIG_REG_INGRESS_BMAC0_MEM; |
| 2014 | u32 val = 0x14; |
| 2015 | |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2016 | if ((!(params->feature_config_flags & |
| 2017 | FEATURE_CONFIG_PFC_ENABLED)) && |
| 2018 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2019 | /* Enable BigMAC to react on received Pause packets */ |
| 2020 | val |= (1<<5); |
| 2021 | wb_data[0] = val; |
| 2022 | wb_data[1] = 0; |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2023 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2024 | udelay(30); |
| 2025 | |
| 2026 | /* Tx control */ |
| 2027 | val = 0xc0; |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2028 | if (!(params->feature_config_flags & |
| 2029 | FEATURE_CONFIG_PFC_ENABLED) && |
| 2030 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2031 | val |= 0x800000; |
| 2032 | wb_data[0] = val; |
| 2033 | wb_data[1] = 0; |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2034 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2035 | |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2036 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { |
| 2037 | DP(NETIF_MSG_LINK, "PFC is enabled\n"); |
| 2038 | /* Enable PFC RX & TX & STATS and set 8 COS */ |
| 2039 | wb_data[0] = 0x0; |
| 2040 | wb_data[0] |= (1<<0); /* RX */ |
| 2041 | wb_data[0] |= (1<<1); /* TX */ |
| 2042 | wb_data[0] |= (1<<2); /* Force initial Xon */ |
| 2043 | wb_data[0] |= (1<<3); /* 8 cos */ |
| 2044 | wb_data[0] |= (1<<5); /* STATS */ |
| 2045 | wb_data[1] = 0; |
| 2046 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, |
| 2047 | wb_data, 2); |
| 2048 | /* Clear the force Xon */ |
| 2049 | wb_data[0] &= ~(1<<2); |
| 2050 | } else { |
| 2051 | DP(NETIF_MSG_LINK, "PFC is disabled\n"); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2052 | /* Disable PFC RX & TX & STATS and set 8 COS */ |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2053 | wb_data[0] = 0x8; |
| 2054 | wb_data[1] = 0; |
| 2055 | } |
| 2056 | |
| 2057 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); |
| 2058 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 2059 | /* Set Time (based unit is 512 bit time) between automatic |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 2060 | * re-sending of PP packets amd enable automatic re-send of |
| 2061 | * Per-Priroity Packet as long as pp_gen is asserted and |
| 2062 | * pp_disable is low. |
| 2063 | */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2064 | val = 0x8000; |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2065 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) |
| 2066 | val |= (1<<16); /* enable automatic re-send */ |
| 2067 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2068 | wb_data[0] = val; |
| 2069 | wb_data[1] = 0; |
| 2070 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2071 | wb_data, 2); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2072 | |
| 2073 | /* mac control */ |
| 2074 | val = 0x3; /* Enable RX and TX */ |
| 2075 | if (is_lb) { |
| 2076 | val |= 0x4; /* Local loopback */ |
| 2077 | DP(NETIF_MSG_LINK, "enable bmac loopback\n"); |
| 2078 | } |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2079 | /* When PFC enabled, Pass pause frames towards the NIG. */ |
| 2080 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) |
| 2081 | val |= ((1<<6)|(1<<5)); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2082 | |
| 2083 | wb_data[0] = val; |
| 2084 | wb_data[1] = 0; |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2085 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2086 | } |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2087 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 2088 | /****************************************************************************** |
| 2089 | * Description: |
| 2090 | * This function is needed because NIG ARB_CREDIT_WEIGHT_X are |
| 2091 | * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. |
| 2092 | ******************************************************************************/ |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2093 | static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, |
| 2094 | u8 cos_entry, |
| 2095 | u32 priority_mask, u8 port) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 2096 | { |
| 2097 | u32 nig_reg_rx_priority_mask_add = 0; |
| 2098 | |
| 2099 | switch (cos_entry) { |
| 2100 | case 0: |
| 2101 | nig_reg_rx_priority_mask_add = (port) ? |
| 2102 | NIG_REG_P1_RX_COS0_PRIORITY_MASK : |
| 2103 | NIG_REG_P0_RX_COS0_PRIORITY_MASK; |
| 2104 | break; |
| 2105 | case 1: |
| 2106 | nig_reg_rx_priority_mask_add = (port) ? |
| 2107 | NIG_REG_P1_RX_COS1_PRIORITY_MASK : |
| 2108 | NIG_REG_P0_RX_COS1_PRIORITY_MASK; |
| 2109 | break; |
| 2110 | case 2: |
| 2111 | nig_reg_rx_priority_mask_add = (port) ? |
| 2112 | NIG_REG_P1_RX_COS2_PRIORITY_MASK : |
| 2113 | NIG_REG_P0_RX_COS2_PRIORITY_MASK; |
| 2114 | break; |
| 2115 | case 3: |
| 2116 | if (port) |
| 2117 | return -EINVAL; |
| 2118 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; |
| 2119 | break; |
| 2120 | case 4: |
| 2121 | if (port) |
| 2122 | return -EINVAL; |
| 2123 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; |
| 2124 | break; |
| 2125 | case 5: |
| 2126 | if (port) |
| 2127 | return -EINVAL; |
| 2128 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; |
| 2129 | break; |
| 2130 | } |
| 2131 | |
| 2132 | REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); |
| 2133 | |
| 2134 | return 0; |
| 2135 | } |
Yaniv Rosner | b8d6d08 | 2011-07-05 01:06:27 +0000 | [diff] [blame] | 2136 | static void bnx2x_update_mng(struct link_params *params, u32 link_status) |
| 2137 | { |
| 2138 | struct bnx2x *bp = params->bp; |
| 2139 | |
| 2140 | REG_WR(bp, params->shmem_base + |
| 2141 | offsetof(struct shmem_region, |
| 2142 | port_mb[params->port].link_status), link_status); |
| 2143 | } |
| 2144 | |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 2145 | static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr) |
| 2146 | { |
| 2147 | struct bnx2x *bp = params->bp; |
| 2148 | |
| 2149 | if (SHMEM2_HAS(bp, link_attr_sync)) |
| 2150 | REG_WR(bp, params->shmem2_base + |
| 2151 | offsetof(struct shmem2_region, |
| 2152 | link_attr_sync[params->port]), link_attr); |
| 2153 | } |
| 2154 | |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2155 | static void bnx2x_update_pfc_nig(struct link_params *params, |
| 2156 | struct link_vars *vars, |
| 2157 | struct bnx2x_nig_brb_pfc_port_params *nig_params) |
| 2158 | { |
| 2159 | u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; |
Yaniv Rosner | 127302b | 2012-01-17 02:33:26 +0000 | [diff] [blame] | 2160 | u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2161 | u32 pkt_priority_to_cos = 0; |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2162 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 2163 | u8 port = params->port; |
| 2164 | |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2165 | int set_pfc = params->feature_config_flags & |
| 2166 | FEATURE_CONFIG_PFC_ENABLED; |
| 2167 | DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); |
| 2168 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 2169 | /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2170 | * MAC control frames (that are not pause packets) |
| 2171 | * will be forwarded to the XCM. |
| 2172 | */ |
Yaniv Rosner | 127302b | 2012-01-17 02:33:26 +0000 | [diff] [blame] | 2173 | xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : |
| 2174 | NIG_REG_LLH0_XCM_MASK); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 2175 | /* NIG params will override non PFC params, since it's possible to |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2176 | * do transition from PFC to SAFC |
| 2177 | */ |
| 2178 | if (set_pfc) { |
| 2179 | pause_enable = 0; |
| 2180 | llfc_out_en = 0; |
| 2181 | llfc_enable = 0; |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 2182 | if (CHIP_IS_E3(bp)) |
| 2183 | ppp_enable = 0; |
| 2184 | else |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 2185 | ppp_enable = 1; |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2186 | xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : |
| 2187 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); |
Yaniv Rosner | 127302b | 2012-01-17 02:33:26 +0000 | [diff] [blame] | 2188 | xcm_out_en = 0; |
| 2189 | hwpfc_enable = 1; |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2190 | } else { |
| 2191 | if (nig_params) { |
| 2192 | llfc_out_en = nig_params->llfc_out_en; |
| 2193 | llfc_enable = nig_params->llfc_enable; |
| 2194 | pause_enable = nig_params->pause_enable; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 2195 | } else /* Default non PFC mode - PAUSE */ |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2196 | pause_enable = 1; |
| 2197 | |
| 2198 | xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : |
| 2199 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); |
Yaniv Rosner | 127302b | 2012-01-17 02:33:26 +0000 | [diff] [blame] | 2200 | xcm_out_en = 1; |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2201 | } |
| 2202 | |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 2203 | if (CHIP_IS_E3(bp)) |
| 2204 | REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : |
| 2205 | NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2206 | REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : |
| 2207 | NIG_REG_LLFC_OUT_EN_0, llfc_out_en); |
| 2208 | REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : |
| 2209 | NIG_REG_LLFC_ENABLE_0, llfc_enable); |
| 2210 | REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : |
| 2211 | NIG_REG_PAUSE_ENABLE_0, pause_enable); |
| 2212 | |
| 2213 | REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : |
| 2214 | NIG_REG_PPP_ENABLE_0, ppp_enable); |
| 2215 | |
| 2216 | REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : |
| 2217 | NIG_REG_LLH0_XCM_MASK, xcm_mask); |
| 2218 | |
Yaniv Rosner | 127302b | 2012-01-17 02:33:26 +0000 | [diff] [blame] | 2219 | REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : |
| 2220 | NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2221 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2222 | /* Output enable for RX_XCM # IF */ |
Yaniv Rosner | 127302b | 2012-01-17 02:33:26 +0000 | [diff] [blame] | 2223 | REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : |
| 2224 | NIG_REG_XCM0_OUT_EN, xcm_out_en); |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2225 | |
| 2226 | /* HW PFC TX enable */ |
Yaniv Rosner | 127302b | 2012-01-17 02:33:26 +0000 | [diff] [blame] | 2227 | REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : |
| 2228 | NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2229 | |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2230 | if (nig_params) { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 2231 | u8 i = 0; |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2232 | pkt_priority_to_cos = nig_params->pkt_priority_to_cos; |
| 2233 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 2234 | for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) |
| 2235 | bnx2x_pfc_nig_rx_priority_mask(bp, i, |
| 2236 | nig_params->rx_cos_priority_mask[i], port); |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2237 | |
| 2238 | REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : |
| 2239 | NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, |
| 2240 | nig_params->llfc_high_priority_classes); |
| 2241 | |
| 2242 | REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : |
| 2243 | NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, |
| 2244 | nig_params->llfc_low_priority_classes); |
| 2245 | } |
| 2246 | REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : |
| 2247 | NIG_REG_P0_PKT_PRIORITY_TO_COS, |
| 2248 | pkt_priority_to_cos); |
| 2249 | } |
| 2250 | |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 2251 | int bnx2x_update_pfc(struct link_params *params, |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2252 | struct link_vars *vars, |
| 2253 | struct bnx2x_nig_brb_pfc_port_params *pfc_params) |
| 2254 | { |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 2255 | /* The PFC and pause are orthogonal to one another, meaning when |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2256 | * PFC is enabled, the pause are disabled, and when PFC is |
| 2257 | * disabled, pause are set according to the pause result. |
| 2258 | */ |
| 2259 | u32 val; |
| 2260 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 2261 | int bnx2x_status = 0; |
| 2262 | u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC); |
Yaniv Rosner | b8d6d08 | 2011-07-05 01:06:27 +0000 | [diff] [blame] | 2263 | |
| 2264 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) |
| 2265 | vars->link_status |= LINK_STATUS_PFC_ENABLED; |
| 2266 | else |
| 2267 | vars->link_status &= ~LINK_STATUS_PFC_ENABLED; |
| 2268 | |
| 2269 | bnx2x_update_mng(params, vars->link_status); |
| 2270 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2271 | /* Update NIG params */ |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2272 | bnx2x_update_pfc_nig(params, vars, pfc_params); |
| 2273 | |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2274 | if (!vars->link_up) |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 2275 | return bnx2x_status; |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2276 | |
| 2277 | DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n"); |
Yaniv Rosner | 375944c | 2012-09-11 04:34:10 +0000 | [diff] [blame] | 2278 | |
| 2279 | if (CHIP_IS_E3(bp)) { |
| 2280 | if (vars->mac_type == MAC_TYPE_XMAC) |
| 2281 | bnx2x_update_pfc_xmac(params, vars, 0); |
| 2282 | } else { |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 2283 | val = REG_RD(bp, MISC_REG_RESET_REG_2); |
| 2284 | if ((val & |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 2285 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 2286 | == 0) { |
| 2287 | DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n"); |
| 2288 | bnx2x_emac_enable(params, vars, 0); |
| 2289 | return bnx2x_status; |
| 2290 | } |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 2291 | if (CHIP_IS_E2(bp)) |
| 2292 | bnx2x_update_pfc_bmac2(params, vars, bmac_loopback); |
| 2293 | else |
| 2294 | bnx2x_update_pfc_bmac1(params, vars); |
| 2295 | |
| 2296 | val = 0; |
| 2297 | if ((params->feature_config_flags & |
| 2298 | FEATURE_CONFIG_PFC_ENABLED) || |
| 2299 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) |
| 2300 | val = 1; |
| 2301 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); |
| 2302 | } |
| 2303 | return bnx2x_status; |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2304 | } |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2305 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 2306 | static int bnx2x_bmac1_enable(struct link_params *params, |
| 2307 | struct link_vars *vars, |
| 2308 | u8 is_lb) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2309 | { |
| 2310 | struct bnx2x *bp = params->bp; |
| 2311 | u8 port = params->port; |
| 2312 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : |
| 2313 | NIG_REG_INGRESS_BMAC0_MEM; |
| 2314 | u32 wb_data[2]; |
| 2315 | u32 val; |
| 2316 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2317 | DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2318 | |
| 2319 | /* XGXS control */ |
| 2320 | wb_data[0] = 0x3c; |
| 2321 | wb_data[1] = 0; |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2322 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, |
| 2323 | wb_data, 2); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2324 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2325 | /* TX MAC SA */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2326 | wb_data[0] = ((params->mac_addr[2] << 24) | |
| 2327 | (params->mac_addr[3] << 16) | |
| 2328 | (params->mac_addr[4] << 8) | |
| 2329 | params->mac_addr[5]); |
| 2330 | wb_data[1] = ((params->mac_addr[0] << 8) | |
| 2331 | params->mac_addr[1]); |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2332 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2333 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2334 | /* MAC control */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2335 | val = 0x3; |
| 2336 | if (is_lb) { |
| 2337 | val |= 0x4; |
| 2338 | DP(NETIF_MSG_LINK, "enable bmac loopback\n"); |
| 2339 | } |
| 2340 | wb_data[0] = val; |
| 2341 | wb_data[1] = 0; |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2342 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2343 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2344 | /* Set rx mtu */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2345 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
| 2346 | wb_data[1] = 0; |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2347 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2348 | |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2349 | bnx2x_update_pfc_bmac1(params, vars); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2350 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2351 | /* Set tx mtu */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2352 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
| 2353 | wb_data[1] = 0; |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2354 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2355 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2356 | /* Set cnt max size */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2357 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
| 2358 | wb_data[1] = 0; |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2359 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2360 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2361 | /* Configure SAFC */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2362 | wb_data[0] = 0x1000200; |
| 2363 | wb_data[1] = 0; |
| 2364 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, |
| 2365 | wb_data, 2); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2366 | |
| 2367 | return 0; |
| 2368 | } |
| 2369 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 2370 | static int bnx2x_bmac2_enable(struct link_params *params, |
| 2371 | struct link_vars *vars, |
| 2372 | u8 is_lb) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2373 | { |
| 2374 | struct bnx2x *bp = params->bp; |
| 2375 | u8 port = params->port; |
| 2376 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : |
| 2377 | NIG_REG_INGRESS_BMAC0_MEM; |
| 2378 | u32 wb_data[2]; |
| 2379 | |
| 2380 | DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); |
| 2381 | |
| 2382 | wb_data[0] = 0; |
| 2383 | wb_data[1] = 0; |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2384 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2385 | udelay(30); |
| 2386 | |
| 2387 | /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ |
| 2388 | wb_data[0] = 0x3c; |
| 2389 | wb_data[1] = 0; |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2390 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, |
| 2391 | wb_data, 2); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2392 | |
| 2393 | udelay(30); |
| 2394 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2395 | /* TX MAC SA */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2396 | wb_data[0] = ((params->mac_addr[2] << 24) | |
| 2397 | (params->mac_addr[3] << 16) | |
| 2398 | (params->mac_addr[4] << 8) | |
| 2399 | params->mac_addr[5]); |
| 2400 | wb_data[1] = ((params->mac_addr[0] << 8) | |
| 2401 | params->mac_addr[1]); |
| 2402 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2403 | wb_data, 2); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2404 | |
| 2405 | udelay(30); |
| 2406 | |
| 2407 | /* Configure SAFC */ |
| 2408 | wb_data[0] = 0x1000200; |
| 2409 | wb_data[1] = 0; |
| 2410 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2411 | wb_data, 2); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2412 | udelay(30); |
| 2413 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2414 | /* Set RX MTU */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2415 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
| 2416 | wb_data[1] = 0; |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2417 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2418 | udelay(30); |
| 2419 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2420 | /* Set TX MTU */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2421 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
| 2422 | wb_data[1] = 0; |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2423 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2424 | udelay(30); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2425 | /* Set cnt max size */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2426 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2; |
| 2427 | wb_data[1] = 0; |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2428 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2429 | udelay(30); |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2430 | bnx2x_update_pfc_bmac2(params, vars, is_lb); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2431 | |
| 2432 | return 0; |
| 2433 | } |
| 2434 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 2435 | static int bnx2x_bmac_enable(struct link_params *params, |
| 2436 | struct link_vars *vars, |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 2437 | u8 is_lb, u8 reset_bmac) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2438 | { |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 2439 | int rc = 0; |
| 2440 | u8 port = params->port; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2441 | struct bnx2x *bp = params->bp; |
| 2442 | u32 val; |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2443 | /* Reset and unreset the BigMac */ |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 2444 | if (reset_bmac) { |
| 2445 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
| 2446 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
| 2447 | usleep_range(1000, 2000); |
| 2448 | } |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2449 | |
| 2450 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2451 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2452 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2453 | /* Enable access for bmac registers */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2454 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); |
| 2455 | |
| 2456 | /* Enable BMAC according to BMAC type*/ |
| 2457 | if (CHIP_IS_E2(bp)) |
| 2458 | rc = bnx2x_bmac2_enable(params, vars, is_lb); |
| 2459 | else |
| 2460 | rc = bnx2x_bmac1_enable(params, vars, is_lb); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2461 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); |
| 2462 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); |
| 2463 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); |
| 2464 | val = 0; |
Vladislav Zolotarov | bcab15c | 2010-12-13 05:44:25 +0000 | [diff] [blame] | 2465 | if ((params->feature_config_flags & |
| 2466 | FEATURE_CONFIG_PFC_ENABLED) || |
| 2467 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2468 | val = 1; |
| 2469 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); |
| 2470 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); |
| 2471 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); |
| 2472 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); |
| 2473 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); |
| 2474 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); |
| 2475 | |
| 2476 | vars->mac_type = MAC_TYPE_BMAC; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2477 | return rc; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2478 | } |
| 2479 | |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 2480 | static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2481 | { |
| 2482 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2483 | NIG_REG_INGRESS_BMAC0_MEM; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2484 | u32 wb_data[2]; |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 2485 | u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2486 | |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 2487 | if (CHIP_IS_E2(bp)) |
| 2488 | bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; |
| 2489 | else |
| 2490 | bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2491 | /* Only if the bmac is out of reset */ |
| 2492 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & |
| 2493 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && |
| 2494 | nig_bmac_enable) { |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 2495 | /* Clear Rx Enable bit in BMAC_CONTROL register */ |
| 2496 | REG_RD_DMAE(bp, bmac_addr, wb_data, 2); |
| 2497 | if (en) |
| 2498 | wb_data[0] |= BMAC_CONTROL_RX_ENABLE; |
| 2499 | else |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2500 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 2501 | REG_WR_DMAE(bp, bmac_addr, wb_data, 2); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2502 | usleep_range(1000, 2000); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2503 | } |
| 2504 | } |
| 2505 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 2506 | static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, |
| 2507 | u32 line_speed) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2508 | { |
| 2509 | struct bnx2x *bp = params->bp; |
| 2510 | u8 port = params->port; |
| 2511 | u32 init_crd, crd; |
| 2512 | u32 count = 1000; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2513 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2514 | /* Disable port */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2515 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); |
| 2516 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2517 | /* Wait for init credit */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2518 | init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); |
| 2519 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); |
| 2520 | DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); |
| 2521 | |
| 2522 | while ((init_crd != crd) && count) { |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2523 | usleep_range(5000, 10000); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2524 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); |
| 2525 | count--; |
| 2526 | } |
| 2527 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); |
| 2528 | if (init_crd != crd) { |
| 2529 | DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", |
| 2530 | init_crd, crd); |
| 2531 | return -EINVAL; |
| 2532 | } |
| 2533 | |
David S. Miller | c0700f9 | 2008-12-16 23:53:20 -0800 | [diff] [blame] | 2534 | if (flow_ctrl & BNX2X_FLOW_CTRL_RX || |
Yaniv Rosner | 8c99e7b | 2008-08-13 15:56:17 -0700 | [diff] [blame] | 2535 | line_speed == SPEED_10 || |
| 2536 | line_speed == SPEED_100 || |
| 2537 | line_speed == SPEED_1000 || |
| 2538 | line_speed == SPEED_2500) { |
| 2539 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2540 | /* Update threshold */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2541 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2542 | /* Update init credit */ |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2543 | init_crd = 778; /* (800-18-4) */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2544 | |
| 2545 | } else { |
| 2546 | u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + |
| 2547 | ETH_OVREHEAD)/16; |
Yaniv Rosner | 8c99e7b | 2008-08-13 15:56:17 -0700 | [diff] [blame] | 2548 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2549 | /* Update threshold */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2550 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2551 | /* Update init credit */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2552 | switch (line_speed) { |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2553 | case SPEED_10000: |
| 2554 | init_crd = thresh + 553 - 22; |
| 2555 | break; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2556 | default: |
| 2557 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", |
| 2558 | line_speed); |
| 2559 | return -EINVAL; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2560 | } |
| 2561 | } |
| 2562 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); |
| 2563 | DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", |
| 2564 | line_speed, init_crd); |
| 2565 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2566 | /* Probe the credit changes */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2567 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2568 | usleep_range(5000, 10000); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2569 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); |
| 2570 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2571 | /* Enable port */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2572 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); |
| 2573 | return 0; |
| 2574 | } |
| 2575 | |
Dmitry Kravkov | e892067 | 2011-05-04 23:52:40 +0000 | [diff] [blame] | 2576 | /** |
| 2577 | * bnx2x_get_emac_base - retrive emac base address |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 2578 | * |
Dmitry Kravkov | e892067 | 2011-05-04 23:52:40 +0000 | [diff] [blame] | 2579 | * @bp: driver handle |
| 2580 | * @mdc_mdio_access: access type |
| 2581 | * @port: port id |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 2582 | * |
| 2583 | * This function selects the MDC/MDIO access (through emac0 or |
| 2584 | * emac1) depend on the mdc_mdio_access, port, port swapped. Each |
| 2585 | * phy has a default access mode, which could also be overridden |
| 2586 | * by nvram configuration. This parameter, whether this is the |
| 2587 | * default phy configuration, or the nvram overrun |
| 2588 | * configuration, is passed here as mdc_mdio_access and selects |
| 2589 | * the emac_base for the CL45 read/writes operations |
| 2590 | */ |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 2591 | static u32 bnx2x_get_emac_base(struct bnx2x *bp, |
| 2592 | u32 mdc_mdio_access, u8 port) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2593 | { |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 2594 | u32 emac_base = 0; |
| 2595 | switch (mdc_mdio_access) { |
| 2596 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: |
| 2597 | break; |
| 2598 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: |
| 2599 | if (REG_RD(bp, NIG_REG_PORT_SWAP)) |
| 2600 | emac_base = GRCBASE_EMAC1; |
| 2601 | else |
| 2602 | emac_base = GRCBASE_EMAC0; |
| 2603 | break; |
| 2604 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: |
Eilon Greenstein | 589abe3 | 2009-02-12 08:36:55 +0000 | [diff] [blame] | 2605 | if (REG_RD(bp, NIG_REG_PORT_SWAP)) |
| 2606 | emac_base = GRCBASE_EMAC0; |
| 2607 | else |
| 2608 | emac_base = GRCBASE_EMAC1; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2609 | break; |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 2610 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: |
| 2611 | emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
| 2612 | break; |
| 2613 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: |
Eilon Greenstein | 6378c02 | 2008-08-13 15:59:25 -0700 | [diff] [blame] | 2614 | emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2615 | break; |
| 2616 | default: |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2617 | break; |
| 2618 | } |
| 2619 | return emac_base; |
| 2620 | |
| 2621 | } |
| 2622 | |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 2623 | /******************************************************************/ |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 2624 | /* CL22 access functions */ |
| 2625 | /******************************************************************/ |
| 2626 | static int bnx2x_cl22_write(struct bnx2x *bp, |
| 2627 | struct bnx2x_phy *phy, |
| 2628 | u16 reg, u16 val) |
| 2629 | { |
| 2630 | u32 tmp, mode; |
| 2631 | u8 i; |
| 2632 | int rc = 0; |
| 2633 | /* Switch to CL22 */ |
| 2634 | mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); |
| 2635 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, |
| 2636 | mode & ~EMAC_MDIO_MODE_CLAUSE_45); |
| 2637 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2638 | /* Address */ |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 2639 | tmp = ((phy->addr << 21) | (reg << 16) | val | |
| 2640 | EMAC_MDIO_COMM_COMMAND_WRITE_22 | |
| 2641 | EMAC_MDIO_COMM_START_BUSY); |
| 2642 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
| 2643 | |
| 2644 | for (i = 0; i < 50; i++) { |
| 2645 | udelay(10); |
| 2646 | |
| 2647 | tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
| 2648 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { |
| 2649 | udelay(5); |
| 2650 | break; |
| 2651 | } |
| 2652 | } |
| 2653 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { |
| 2654 | DP(NETIF_MSG_LINK, "write phy register failed\n"); |
| 2655 | rc = -EFAULT; |
| 2656 | } |
| 2657 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); |
| 2658 | return rc; |
| 2659 | } |
| 2660 | |
| 2661 | static int bnx2x_cl22_read(struct bnx2x *bp, |
| 2662 | struct bnx2x_phy *phy, |
| 2663 | u16 reg, u16 *ret_val) |
| 2664 | { |
| 2665 | u32 val, mode; |
| 2666 | u16 i; |
| 2667 | int rc = 0; |
| 2668 | |
| 2669 | /* Switch to CL22 */ |
| 2670 | mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); |
| 2671 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, |
| 2672 | mode & ~EMAC_MDIO_MODE_CLAUSE_45); |
| 2673 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2674 | /* Address */ |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 2675 | val = ((phy->addr << 21) | (reg << 16) | |
| 2676 | EMAC_MDIO_COMM_COMMAND_READ_22 | |
| 2677 | EMAC_MDIO_COMM_START_BUSY); |
| 2678 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
| 2679 | |
| 2680 | for (i = 0; i < 50; i++) { |
| 2681 | udelay(10); |
| 2682 | |
| 2683 | val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
| 2684 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { |
| 2685 | *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); |
| 2686 | udelay(5); |
| 2687 | break; |
| 2688 | } |
| 2689 | } |
| 2690 | if (val & EMAC_MDIO_COMM_START_BUSY) { |
| 2691 | DP(NETIF_MSG_LINK, "read phy register failed\n"); |
| 2692 | |
| 2693 | *ret_val = 0; |
| 2694 | rc = -EFAULT; |
| 2695 | } |
| 2696 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); |
| 2697 | return rc; |
| 2698 | } |
| 2699 | |
| 2700 | /******************************************************************/ |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 2701 | /* CL45 access functions */ |
| 2702 | /******************************************************************/ |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 2703 | static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, |
| 2704 | u8 devad, u16 reg, u16 *ret_val) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2705 | { |
Yaniv Rosner | a198c14 | 2011-05-31 21:29:42 +0000 | [diff] [blame] | 2706 | u32 val; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2707 | u16 i; |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 2708 | int rc = 0; |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 2709 | u32 chip_id; |
| 2710 | if (phy->flags & FLAGS_MDC_MDIO_WA_G) { |
| 2711 | chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | |
| 2712 | ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); |
| 2713 | bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); |
| 2714 | } |
| 2715 | |
Yaniv Rosner | 157fa28 | 2011-08-02 22:59:32 +0000 | [diff] [blame] | 2716 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
| 2717 | bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, |
| 2718 | EMAC_MDIO_STATUS_10MB); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2719 | /* Address */ |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 2720 | val = ((phy->addr << 21) | (devad << 16) | reg | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2721 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
| 2722 | EMAC_MDIO_COMM_START_BUSY); |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 2723 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2724 | |
| 2725 | for (i = 0; i < 50; i++) { |
| 2726 | udelay(10); |
| 2727 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 2728 | val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2729 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { |
| 2730 | udelay(5); |
| 2731 | break; |
| 2732 | } |
| 2733 | } |
| 2734 | if (val & EMAC_MDIO_COMM_START_BUSY) { |
| 2735 | DP(NETIF_MSG_LINK, "read phy register failed\n"); |
Yaniv Rosner | 6d870c3 | 2011-01-31 04:22:20 +0000 | [diff] [blame] | 2736 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2737 | *ret_val = 0; |
| 2738 | rc = -EFAULT; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2739 | } else { |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2740 | /* Data */ |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 2741 | val = ((phy->addr << 21) | (devad << 16) | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2742 | EMAC_MDIO_COMM_COMMAND_READ_45 | |
| 2743 | EMAC_MDIO_COMM_START_BUSY); |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 2744 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2745 | |
| 2746 | for (i = 0; i < 50; i++) { |
| 2747 | udelay(10); |
| 2748 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 2749 | val = REG_RD(bp, phy->mdio_ctrl + |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 2750 | EMAC_REG_EMAC_MDIO_COMM); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2751 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { |
| 2752 | *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); |
| 2753 | break; |
| 2754 | } |
| 2755 | } |
| 2756 | if (val & EMAC_MDIO_COMM_START_BUSY) { |
| 2757 | DP(NETIF_MSG_LINK, "read phy register failed\n"); |
Yaniv Rosner | 6d870c3 | 2011-01-31 04:22:20 +0000 | [diff] [blame] | 2758 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2759 | *ret_val = 0; |
| 2760 | rc = -EFAULT; |
| 2761 | } |
| 2762 | } |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 2763 | /* Work around for E3 A0 */ |
| 2764 | if (phy->flags & FLAGS_MDC_MDIO_WA) { |
| 2765 | phy->flags ^= FLAGS_DUMMY_READ; |
| 2766 | if (phy->flags & FLAGS_DUMMY_READ) { |
| 2767 | u16 temp_val; |
| 2768 | bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); |
| 2769 | } |
| 2770 | } |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2771 | |
Yaniv Rosner | 157fa28 | 2011-08-02 22:59:32 +0000 | [diff] [blame] | 2772 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
| 2773 | bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, |
| 2774 | EMAC_MDIO_STATUS_10MB); |
Yaniv Rosner | a198c14 | 2011-05-31 21:29:42 +0000 | [diff] [blame] | 2775 | return rc; |
| 2776 | } |
| 2777 | |
| 2778 | static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, |
| 2779 | u8 devad, u16 reg, u16 val) |
| 2780 | { |
| 2781 | u32 tmp; |
| 2782 | u8 i; |
| 2783 | int rc = 0; |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 2784 | u32 chip_id; |
| 2785 | if (phy->flags & FLAGS_MDC_MDIO_WA_G) { |
| 2786 | chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | |
| 2787 | ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); |
| 2788 | bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); |
| 2789 | } |
| 2790 | |
Yaniv Rosner | 157fa28 | 2011-08-02 22:59:32 +0000 | [diff] [blame] | 2791 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
| 2792 | bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, |
| 2793 | EMAC_MDIO_STATUS_10MB); |
Yaniv Rosner | a198c14 | 2011-05-31 21:29:42 +0000 | [diff] [blame] | 2794 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2795 | /* Address */ |
Yaniv Rosner | a198c14 | 2011-05-31 21:29:42 +0000 | [diff] [blame] | 2796 | tmp = ((phy->addr << 21) | (devad << 16) | reg | |
| 2797 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
| 2798 | EMAC_MDIO_COMM_START_BUSY); |
| 2799 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
| 2800 | |
| 2801 | for (i = 0; i < 50; i++) { |
| 2802 | udelay(10); |
| 2803 | |
| 2804 | tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
| 2805 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { |
| 2806 | udelay(5); |
| 2807 | break; |
| 2808 | } |
| 2809 | } |
| 2810 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { |
| 2811 | DP(NETIF_MSG_LINK, "write phy register failed\n"); |
| 2812 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
| 2813 | rc = -EFAULT; |
Yaniv Rosner | a198c14 | 2011-05-31 21:29:42 +0000 | [diff] [blame] | 2814 | } else { |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 2815 | /* Data */ |
Yaniv Rosner | a198c14 | 2011-05-31 21:29:42 +0000 | [diff] [blame] | 2816 | tmp = ((phy->addr << 21) | (devad << 16) | val | |
| 2817 | EMAC_MDIO_COMM_COMMAND_WRITE_45 | |
| 2818 | EMAC_MDIO_COMM_START_BUSY); |
| 2819 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
| 2820 | |
| 2821 | for (i = 0; i < 50; i++) { |
| 2822 | udelay(10); |
| 2823 | |
| 2824 | tmp = REG_RD(bp, phy->mdio_ctrl + |
| 2825 | EMAC_REG_EMAC_MDIO_COMM); |
| 2826 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { |
| 2827 | udelay(5); |
| 2828 | break; |
| 2829 | } |
| 2830 | } |
| 2831 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { |
| 2832 | DP(NETIF_MSG_LINK, "write phy register failed\n"); |
| 2833 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
| 2834 | rc = -EFAULT; |
| 2835 | } |
| 2836 | } |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 2837 | /* Work around for E3 A0 */ |
| 2838 | if (phy->flags & FLAGS_MDC_MDIO_WA) { |
| 2839 | phy->flags ^= FLAGS_DUMMY_READ; |
| 2840 | if (phy->flags & FLAGS_DUMMY_READ) { |
| 2841 | u16 temp_val; |
| 2842 | bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); |
| 2843 | } |
| 2844 | } |
Yaniv Rosner | 157fa28 | 2011-08-02 22:59:32 +0000 | [diff] [blame] | 2845 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
| 2846 | bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, |
| 2847 | EMAC_MDIO_STATUS_10MB); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 2848 | return rc; |
| 2849 | } |
Yuval Mintz | ec4010e | 2012-09-10 05:51:06 +0000 | [diff] [blame] | 2850 | |
| 2851 | /******************************************************************/ |
| 2852 | /* EEE section */ |
| 2853 | /******************************************************************/ |
| 2854 | static u8 bnx2x_eee_has_cap(struct link_params *params) |
| 2855 | { |
| 2856 | struct bnx2x *bp = params->bp; |
| 2857 | |
| 2858 | if (REG_RD(bp, params->shmem2_base) <= |
| 2859 | offsetof(struct shmem2_region, eee_status[params->port])) |
| 2860 | return 0; |
| 2861 | |
| 2862 | return 1; |
| 2863 | } |
| 2864 | |
| 2865 | static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer) |
| 2866 | { |
| 2867 | switch (nvram_mode) { |
| 2868 | case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: |
| 2869 | *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME; |
| 2870 | break; |
| 2871 | case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: |
| 2872 | *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME; |
| 2873 | break; |
| 2874 | case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: |
| 2875 | *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME; |
| 2876 | break; |
| 2877 | default: |
| 2878 | *idle_timer = 0; |
| 2879 | break; |
| 2880 | } |
| 2881 | |
| 2882 | return 0; |
| 2883 | } |
| 2884 | |
| 2885 | static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode) |
| 2886 | { |
| 2887 | switch (idle_timer) { |
| 2888 | case EEE_MODE_NVRAM_BALANCED_TIME: |
| 2889 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; |
| 2890 | break; |
| 2891 | case EEE_MODE_NVRAM_AGGRESSIVE_TIME: |
| 2892 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; |
| 2893 | break; |
| 2894 | case EEE_MODE_NVRAM_LATENCY_TIME: |
| 2895 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; |
| 2896 | break; |
| 2897 | default: |
| 2898 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; |
| 2899 | break; |
| 2900 | } |
| 2901 | |
| 2902 | return 0; |
| 2903 | } |
| 2904 | |
| 2905 | static u32 bnx2x_eee_calc_timer(struct link_params *params) |
| 2906 | { |
| 2907 | u32 eee_mode, eee_idle; |
| 2908 | struct bnx2x *bp = params->bp; |
| 2909 | |
| 2910 | if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) { |
| 2911 | if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { |
| 2912 | /* time value in eee_mode --> used directly*/ |
| 2913 | eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK; |
| 2914 | } else { |
| 2915 | /* hsi value in eee_mode --> time */ |
| 2916 | if (bnx2x_eee_nvram_to_time(params->eee_mode & |
| 2917 | EEE_MODE_NVRAM_MASK, |
| 2918 | &eee_idle)) |
| 2919 | return 0; |
| 2920 | } |
| 2921 | } else { |
| 2922 | /* hsi values in nvram --> time*/ |
| 2923 | eee_mode = ((REG_RD(bp, params->shmem_base + |
| 2924 | offsetof(struct shmem_region, dev_info. |
| 2925 | port_feature_config[params->port]. |
| 2926 | eee_power_mode)) & |
| 2927 | PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> |
| 2928 | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); |
| 2929 | |
| 2930 | if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle)) |
| 2931 | return 0; |
| 2932 | } |
| 2933 | |
| 2934 | return eee_idle; |
| 2935 | } |
| 2936 | |
| 2937 | static int bnx2x_eee_set_timers(struct link_params *params, |
| 2938 | struct link_vars *vars) |
| 2939 | { |
| 2940 | u32 eee_idle = 0, eee_mode; |
| 2941 | struct bnx2x *bp = params->bp; |
| 2942 | |
| 2943 | eee_idle = bnx2x_eee_calc_timer(params); |
| 2944 | |
| 2945 | if (eee_idle) { |
| 2946 | REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), |
| 2947 | eee_idle); |
| 2948 | } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) && |
| 2949 | (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) && |
| 2950 | (params->eee_mode & EEE_MODE_OUTPUT_TIME)) { |
| 2951 | DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n"); |
| 2952 | return -EINVAL; |
| 2953 | } |
| 2954 | |
| 2955 | vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); |
| 2956 | if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { |
| 2957 | /* eee_idle in 1u --> eee_status in 16u */ |
| 2958 | eee_idle >>= 4; |
| 2959 | vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | |
| 2960 | SHMEM_EEE_TIME_OUTPUT_BIT; |
| 2961 | } else { |
| 2962 | if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode)) |
| 2963 | return -EINVAL; |
| 2964 | vars->eee_status |= eee_mode; |
| 2965 | } |
| 2966 | |
| 2967 | return 0; |
| 2968 | } |
| 2969 | |
| 2970 | static int bnx2x_eee_initial_config(struct link_params *params, |
| 2971 | struct link_vars *vars, u8 mode) |
| 2972 | { |
| 2973 | vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT; |
| 2974 | |
| 2975 | /* Propogate params' bits --> vars (for migration exposure) */ |
| 2976 | if (params->eee_mode & EEE_MODE_ENABLE_LPI) |
| 2977 | vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; |
| 2978 | else |
| 2979 | vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; |
| 2980 | |
| 2981 | if (params->eee_mode & EEE_MODE_ADV_LPI) |
| 2982 | vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; |
| 2983 | else |
| 2984 | vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; |
| 2985 | |
| 2986 | return bnx2x_eee_set_timers(params, vars); |
| 2987 | } |
| 2988 | |
| 2989 | static int bnx2x_eee_disable(struct bnx2x_phy *phy, |
| 2990 | struct link_params *params, |
| 2991 | struct link_vars *vars) |
| 2992 | { |
| 2993 | struct bnx2x *bp = params->bp; |
| 2994 | |
| 2995 | /* Make Certain LPI is disabled */ |
| 2996 | REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); |
| 2997 | |
| 2998 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); |
| 2999 | |
| 3000 | vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; |
| 3001 | |
| 3002 | return 0; |
| 3003 | } |
| 3004 | |
| 3005 | static int bnx2x_eee_advertise(struct bnx2x_phy *phy, |
| 3006 | struct link_params *params, |
| 3007 | struct link_vars *vars, u8 modes) |
| 3008 | { |
| 3009 | struct bnx2x *bp = params->bp; |
| 3010 | u16 val = 0; |
| 3011 | |
| 3012 | /* Mask events preventing LPI generation */ |
| 3013 | REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); |
| 3014 | |
| 3015 | if (modes & SHMEM_EEE_10G_ADV) { |
| 3016 | DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n"); |
| 3017 | val |= 0x8; |
| 3018 | } |
| 3019 | if (modes & SHMEM_EEE_1G_ADV) { |
| 3020 | DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n"); |
| 3021 | val |= 0x4; |
| 3022 | } |
| 3023 | |
| 3024 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); |
| 3025 | |
| 3026 | vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; |
| 3027 | vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); |
| 3028 | |
| 3029 | return 0; |
| 3030 | } |
| 3031 | |
| 3032 | static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status) |
| 3033 | { |
| 3034 | struct bnx2x *bp = params->bp; |
| 3035 | |
| 3036 | if (bnx2x_eee_has_cap(params)) |
| 3037 | REG_WR(bp, params->shmem2_base + |
| 3038 | offsetof(struct shmem2_region, |
| 3039 | eee_status[params->port]), eee_status); |
| 3040 | } |
| 3041 | |
| 3042 | static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy, |
| 3043 | struct link_params *params, |
| 3044 | struct link_vars *vars) |
| 3045 | { |
| 3046 | struct bnx2x *bp = params->bp; |
| 3047 | u16 adv = 0, lp = 0; |
| 3048 | u32 lp_adv = 0; |
| 3049 | u8 neg = 0; |
| 3050 | |
| 3051 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); |
| 3052 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); |
| 3053 | |
| 3054 | if (lp & 0x2) { |
| 3055 | lp_adv |= SHMEM_EEE_100M_ADV; |
| 3056 | if (adv & 0x2) { |
| 3057 | if (vars->line_speed == SPEED_100) |
| 3058 | neg = 1; |
| 3059 | DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n"); |
| 3060 | } |
| 3061 | } |
| 3062 | if (lp & 0x14) { |
| 3063 | lp_adv |= SHMEM_EEE_1G_ADV; |
| 3064 | if (adv & 0x14) { |
| 3065 | if (vars->line_speed == SPEED_1000) |
| 3066 | neg = 1; |
| 3067 | DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n"); |
| 3068 | } |
| 3069 | } |
| 3070 | if (lp & 0x68) { |
| 3071 | lp_adv |= SHMEM_EEE_10G_ADV; |
| 3072 | if (adv & 0x68) { |
| 3073 | if (vars->line_speed == SPEED_10000) |
| 3074 | neg = 1; |
| 3075 | DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n"); |
| 3076 | } |
| 3077 | } |
| 3078 | |
| 3079 | vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; |
| 3080 | vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); |
| 3081 | |
| 3082 | if (neg) { |
| 3083 | DP(NETIF_MSG_LINK, "EEE is active\n"); |
| 3084 | vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; |
| 3085 | } |
| 3086 | |
| 3087 | } |
| 3088 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3089 | /******************************************************************/ |
| 3090 | /* BSC access functions from E3 */ |
| 3091 | /******************************************************************/ |
| 3092 | static void bnx2x_bsc_module_sel(struct link_params *params) |
| 3093 | { |
| 3094 | int idx; |
| 3095 | u32 board_cfg, sfp_ctrl; |
| 3096 | u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; |
| 3097 | struct bnx2x *bp = params->bp; |
| 3098 | u8 port = params->port; |
| 3099 | /* Read I2C output PINs */ |
| 3100 | board_cfg = REG_RD(bp, params->shmem_base + |
| 3101 | offsetof(struct shmem_region, |
| 3102 | dev_info.shared_hw_config.board)); |
| 3103 | i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; |
| 3104 | i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> |
| 3105 | SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; |
| 3106 | |
| 3107 | /* Read I2C output value */ |
| 3108 | sfp_ctrl = REG_RD(bp, params->shmem_base + |
| 3109 | offsetof(struct shmem_region, |
| 3110 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)); |
| 3111 | i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; |
| 3112 | i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; |
| 3113 | DP(NETIF_MSG_LINK, "Setting BSC switch\n"); |
| 3114 | for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) |
| 3115 | bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]); |
| 3116 | } |
| 3117 | |
| 3118 | static int bnx2x_bsc_read(struct link_params *params, |
| 3119 | struct bnx2x_phy *phy, |
| 3120 | u8 sl_devid, |
| 3121 | u16 sl_addr, |
| 3122 | u8 lc_addr, |
| 3123 | u8 xfer_cnt, |
| 3124 | u32 *data_array) |
| 3125 | { |
| 3126 | u32 val, i; |
| 3127 | int rc = 0; |
| 3128 | struct bnx2x *bp = params->bp; |
| 3129 | |
| 3130 | if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) { |
| 3131 | DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid); |
| 3132 | return -EINVAL; |
| 3133 | } |
| 3134 | |
| 3135 | if (xfer_cnt > 16) { |
| 3136 | DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n", |
| 3137 | xfer_cnt); |
| 3138 | return -EINVAL; |
| 3139 | } |
| 3140 | bnx2x_bsc_module_sel(params); |
| 3141 | |
| 3142 | xfer_cnt = 16 - lc_addr; |
| 3143 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 3144 | /* Enable the engine */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3145 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); |
| 3146 | val |= MCPR_IMC_COMMAND_ENABLE; |
| 3147 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); |
| 3148 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 3149 | /* Program slave device ID */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3150 | val = (sl_devid << 16) | sl_addr; |
| 3151 | REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); |
| 3152 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 3153 | /* Start xfer with 0 byte to update the address pointer ???*/ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3154 | val = (MCPR_IMC_COMMAND_ENABLE) | |
| 3155 | (MCPR_IMC_COMMAND_WRITE_OP << |
| 3156 | MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | |
| 3157 | (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); |
| 3158 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); |
| 3159 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 3160 | /* Poll for completion */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3161 | i = 0; |
| 3162 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); |
| 3163 | while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { |
| 3164 | udelay(10); |
| 3165 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); |
| 3166 | if (i++ > 1000) { |
| 3167 | DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n", |
| 3168 | i); |
| 3169 | rc = -EFAULT; |
| 3170 | break; |
| 3171 | } |
| 3172 | } |
| 3173 | if (rc == -EFAULT) |
| 3174 | return rc; |
| 3175 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 3176 | /* Start xfer with read op */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3177 | val = (MCPR_IMC_COMMAND_ENABLE) | |
| 3178 | (MCPR_IMC_COMMAND_READ_OP << |
| 3179 | MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | |
| 3180 | (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | |
| 3181 | (xfer_cnt); |
| 3182 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); |
| 3183 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 3184 | /* Poll for completion */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3185 | i = 0; |
| 3186 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); |
| 3187 | while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { |
| 3188 | udelay(10); |
| 3189 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); |
| 3190 | if (i++ > 1000) { |
| 3191 | DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i); |
| 3192 | rc = -EFAULT; |
| 3193 | break; |
| 3194 | } |
| 3195 | } |
| 3196 | if (rc == -EFAULT) |
| 3197 | return rc; |
| 3198 | |
| 3199 | for (i = (lc_addr >> 2); i < 4; i++) { |
| 3200 | data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); |
| 3201 | #ifdef __BIG_ENDIAN |
| 3202 | data_array[i] = ((data_array[i] & 0x000000ff) << 24) | |
| 3203 | ((data_array[i] & 0x0000ff00) << 8) | |
| 3204 | ((data_array[i] & 0x00ff0000) >> 8) | |
| 3205 | ((data_array[i] & 0xff000000) >> 24); |
| 3206 | #endif |
| 3207 | } |
| 3208 | return rc; |
| 3209 | } |
| 3210 | |
| 3211 | static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, |
| 3212 | u8 devad, u16 reg, u16 or_val) |
| 3213 | { |
| 3214 | u16 val; |
| 3215 | bnx2x_cl45_read(bp, phy, devad, reg, &val); |
| 3216 | bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); |
| 3217 | } |
| 3218 | |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 3219 | static void bnx2x_cl45_read_and_write(struct bnx2x *bp, |
| 3220 | struct bnx2x_phy *phy, |
| 3221 | u8 devad, u16 reg, u16 and_val) |
| 3222 | { |
| 3223 | u16 val; |
| 3224 | bnx2x_cl45_read(bp, phy, devad, reg, &val); |
| 3225 | bnx2x_cl45_write(bp, phy, devad, reg, val & and_val); |
| 3226 | } |
| 3227 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 3228 | int bnx2x_phy_read(struct link_params *params, u8 phy_addr, |
| 3229 | u8 devad, u16 reg, u16 *ret_val) |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 3230 | { |
| 3231 | u8 phy_index; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 3232 | /* Probe for the phy according to the given phy_addr, and execute |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 3233 | * the read request on it |
| 3234 | */ |
| 3235 | for (phy_index = 0; phy_index < params->num_phys; phy_index++) { |
| 3236 | if (params->phy[phy_index].addr == phy_addr) { |
| 3237 | return bnx2x_cl45_read(params->bp, |
| 3238 | ¶ms->phy[phy_index], devad, |
| 3239 | reg, ret_val); |
| 3240 | } |
| 3241 | } |
| 3242 | return -EINVAL; |
| 3243 | } |
| 3244 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 3245 | int bnx2x_phy_write(struct link_params *params, u8 phy_addr, |
| 3246 | u8 devad, u16 reg, u16 val) |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 3247 | { |
| 3248 | u8 phy_index; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 3249 | /* Probe for the phy according to the given phy_addr, and execute |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 3250 | * the write request on it |
| 3251 | */ |
| 3252 | for (phy_index = 0; phy_index < params->num_phys; phy_index++) { |
| 3253 | if (params->phy[phy_index].addr == phy_addr) { |
| 3254 | return bnx2x_cl45_write(params->bp, |
| 3255 | ¶ms->phy[phy_index], devad, |
| 3256 | reg, val); |
| 3257 | } |
| 3258 | } |
| 3259 | return -EINVAL; |
| 3260 | } |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3261 | static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy, |
| 3262 | struct link_params *params) |
| 3263 | { |
| 3264 | u8 lane = 0; |
| 3265 | struct bnx2x *bp = params->bp; |
| 3266 | u32 path_swap, path_swap_ovr; |
| 3267 | u8 path, port; |
| 3268 | |
| 3269 | path = BP_PATH(bp); |
| 3270 | port = params->port; |
| 3271 | |
| 3272 | if (bnx2x_is_4_port_mode(bp)) { |
| 3273 | u32 port_swap, port_swap_ovr; |
| 3274 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 3275 | /* Figure out path swap value */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3276 | path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); |
| 3277 | if (path_swap_ovr & 0x1) |
| 3278 | path_swap = (path_swap_ovr & 0x2); |
| 3279 | else |
| 3280 | path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); |
| 3281 | |
| 3282 | if (path_swap) |
| 3283 | path = path ^ 1; |
| 3284 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 3285 | /* Figure out port swap value */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3286 | port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); |
| 3287 | if (port_swap_ovr & 0x1) |
| 3288 | port_swap = (port_swap_ovr & 0x2); |
| 3289 | else |
| 3290 | port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); |
| 3291 | |
| 3292 | if (port_swap) |
| 3293 | port = port ^ 1; |
| 3294 | |
| 3295 | lane = (port<<1) + path; |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 3296 | } else { /* Two port mode - no port swap */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3297 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 3298 | /* Figure out path swap value */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3299 | path_swap_ovr = |
| 3300 | REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); |
| 3301 | if (path_swap_ovr & 0x1) { |
| 3302 | path_swap = (path_swap_ovr & 0x2); |
| 3303 | } else { |
| 3304 | path_swap = |
| 3305 | REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); |
| 3306 | } |
| 3307 | if (path_swap) |
| 3308 | path = path ^ 1; |
| 3309 | |
| 3310 | lane = path << 1 ; |
| 3311 | } |
| 3312 | return lane; |
| 3313 | } |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 3314 | |
Yaniv Rosner | ec146a6 | 2011-05-31 21:29:27 +0000 | [diff] [blame] | 3315 | static void bnx2x_set_aer_mmd(struct link_params *params, |
| 3316 | struct bnx2x_phy *phy) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 3317 | { |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 3318 | u32 ser_lane; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 3319 | u16 offset, aer_val; |
| 3320 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 3321 | ser_lane = ((params->lane_config & |
| 3322 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
| 3323 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); |
| 3324 | |
Yaniv Rosner | ec146a6 | 2011-05-31 21:29:27 +0000 | [diff] [blame] | 3325 | offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? |
| 3326 | (phy->addr + ser_lane) : 0; |
| 3327 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3328 | if (USES_WARPCORE(bp)) { |
| 3329 | aer_val = bnx2x_get_warpcore_lane(phy, params); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 3330 | /* In Dual-lane mode, two lanes are joined together, |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3331 | * so in order to configure them, the AER broadcast method is |
| 3332 | * used here. |
| 3333 | * 0x200 is the broadcast address for lanes 0,1 |
| 3334 | * 0x201 is the broadcast address for lanes 2,3 |
| 3335 | */ |
| 3336 | if (phy->flags & FLAGS_WC_DUAL_MODE) |
| 3337 | aer_val = (aer_val >> 1) | 0x200; |
| 3338 | } else if (CHIP_IS_E2(bp)) |
Yaniv Rosner | 82a0d47 | 2011-01-18 04:33:52 +0000 | [diff] [blame] | 3339 | aer_val = 0x3800 + offset - 1; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 3340 | else |
| 3341 | aer_val = 0x3800 + offset; |
Yaniv Rosner | 2f751a8 | 2011-11-28 00:49:52 +0000 | [diff] [blame] | 3342 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 3343 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 3344 | MDIO_AER_BLOCK_AER_REG, aer_val); |
Yaniv Rosner | ec146a6 | 2011-05-31 21:29:27 +0000 | [diff] [blame] | 3345 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 3346 | } |
| 3347 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 3348 | /******************************************************************/ |
| 3349 | /* Internal phy section */ |
| 3350 | /******************************************************************/ |
| 3351 | |
| 3352 | static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) |
| 3353 | { |
| 3354 | u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
| 3355 | |
| 3356 | /* Set Clause 22 */ |
| 3357 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); |
| 3358 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); |
| 3359 | udelay(500); |
| 3360 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); |
| 3361 | udelay(500); |
| 3362 | /* Set Clause 45 */ |
| 3363 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); |
| 3364 | } |
| 3365 | |
| 3366 | static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) |
| 3367 | { |
| 3368 | u32 val; |
| 3369 | |
| 3370 | DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n"); |
| 3371 | |
| 3372 | val = SERDES_RESET_BITS << (port*16); |
| 3373 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 3374 | /* Reset and unreset the SerDes/XGXS */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 3375 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); |
| 3376 | udelay(500); |
| 3377 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); |
| 3378 | |
| 3379 | bnx2x_set_serdes_access(bp, port); |
| 3380 | |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 3381 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, |
| 3382 | DEFAULT_PHY_DEV_ADDR); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 3383 | } |
| 3384 | |
Yaniv Rosner | a75bb00 | 2012-10-31 05:46:53 +0000 | [diff] [blame] | 3385 | static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy, |
| 3386 | struct link_params *params, |
| 3387 | u32 action) |
| 3388 | { |
| 3389 | struct bnx2x *bp = params->bp; |
| 3390 | switch (action) { |
| 3391 | case PHY_INIT: |
| 3392 | /* Set correct devad */ |
| 3393 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); |
| 3394 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, |
| 3395 | phy->def_md_devad); |
| 3396 | break; |
| 3397 | } |
| 3398 | } |
| 3399 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 3400 | static void bnx2x_xgxs_deassert(struct link_params *params) |
| 3401 | { |
| 3402 | struct bnx2x *bp = params->bp; |
| 3403 | u8 port; |
| 3404 | u32 val; |
| 3405 | DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n"); |
| 3406 | port = params->port; |
| 3407 | |
| 3408 | val = XGXS_RESET_BITS << (port*16); |
| 3409 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 3410 | /* Reset and unreset the SerDes/XGXS */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 3411 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); |
| 3412 | udelay(500); |
| 3413 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); |
Yaniv Rosner | a75bb00 | 2012-10-31 05:46:53 +0000 | [diff] [blame] | 3414 | bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params, |
| 3415 | PHY_INIT); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 3416 | } |
| 3417 | |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 3418 | static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, |
| 3419 | struct link_params *params, u16 *ieee_fc) |
| 3420 | { |
| 3421 | struct bnx2x *bp = params->bp; |
| 3422 | *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 3423 | /* Resolve pause mode and advertisement Please refer to Table |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 3424 | * 28B-3 of the 802.3ab-1999 spec |
| 3425 | */ |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 3426 | |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 3427 | switch (phy->req_flow_ctrl) { |
| 3428 | case BNX2X_FLOW_CTRL_AUTO: |
| 3429 | if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) |
| 3430 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; |
| 3431 | else |
| 3432 | *ieee_fc |= |
| 3433 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; |
| 3434 | break; |
| 3435 | |
| 3436 | case BNX2X_FLOW_CTRL_TX: |
| 3437 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; |
| 3438 | break; |
| 3439 | |
| 3440 | case BNX2X_FLOW_CTRL_RX: |
| 3441 | case BNX2X_FLOW_CTRL_BOTH: |
| 3442 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; |
| 3443 | break; |
| 3444 | |
| 3445 | case BNX2X_FLOW_CTRL_NONE: |
| 3446 | default: |
| 3447 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; |
| 3448 | break; |
| 3449 | } |
| 3450 | DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); |
| 3451 | } |
| 3452 | |
| 3453 | static void set_phy_vars(struct link_params *params, |
| 3454 | struct link_vars *vars) |
| 3455 | { |
| 3456 | struct bnx2x *bp = params->bp; |
| 3457 | u8 actual_phy_idx, phy_index, link_cfg_idx; |
| 3458 | u8 phy_config_swapped = params->multi_phy_config & |
| 3459 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; |
| 3460 | for (phy_index = INT_PHY; phy_index < params->num_phys; |
| 3461 | phy_index++) { |
| 3462 | link_cfg_idx = LINK_CONFIG_IDX(phy_index); |
| 3463 | actual_phy_idx = phy_index; |
| 3464 | if (phy_config_swapped) { |
| 3465 | if (phy_index == EXT_PHY1) |
| 3466 | actual_phy_idx = EXT_PHY2; |
| 3467 | else if (phy_index == EXT_PHY2) |
| 3468 | actual_phy_idx = EXT_PHY1; |
| 3469 | } |
| 3470 | params->phy[actual_phy_idx].req_flow_ctrl = |
| 3471 | params->req_flow_ctrl[link_cfg_idx]; |
| 3472 | |
| 3473 | params->phy[actual_phy_idx].req_line_speed = |
| 3474 | params->req_line_speed[link_cfg_idx]; |
| 3475 | |
| 3476 | params->phy[actual_phy_idx].speed_cap_mask = |
| 3477 | params->speed_cap_mask[link_cfg_idx]; |
| 3478 | |
| 3479 | params->phy[actual_phy_idx].req_duplex = |
| 3480 | params->req_duplex[link_cfg_idx]; |
| 3481 | |
| 3482 | if (params->req_line_speed[link_cfg_idx] == |
| 3483 | SPEED_AUTO_NEG) |
| 3484 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; |
| 3485 | |
| 3486 | DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x," |
| 3487 | " speed_cap_mask %x\n", |
| 3488 | params->phy[actual_phy_idx].req_flow_ctrl, |
| 3489 | params->phy[actual_phy_idx].req_line_speed, |
| 3490 | params->phy[actual_phy_idx].speed_cap_mask); |
| 3491 | } |
| 3492 | } |
| 3493 | |
| 3494 | static void bnx2x_ext_phy_set_pause(struct link_params *params, |
| 3495 | struct bnx2x_phy *phy, |
| 3496 | struct link_vars *vars) |
| 3497 | { |
| 3498 | u16 val; |
| 3499 | struct bnx2x *bp = params->bp; |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 3500 | /* Read modify write pause advertizing */ |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 3501 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); |
| 3502 | |
| 3503 | val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; |
| 3504 | |
| 3505 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ |
| 3506 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); |
| 3507 | if ((vars->ieee_fc & |
| 3508 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == |
| 3509 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { |
| 3510 | val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; |
| 3511 | } |
| 3512 | if ((vars->ieee_fc & |
| 3513 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == |
| 3514 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { |
| 3515 | val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; |
| 3516 | } |
| 3517 | DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); |
| 3518 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); |
| 3519 | } |
| 3520 | |
| 3521 | static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) |
| 3522 | { /* LD LP */ |
| 3523 | switch (pause_result) { /* ASYM P ASYM P */ |
| 3524 | case 0xb: /* 1 0 1 1 */ |
| 3525 | vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; |
| 3526 | break; |
| 3527 | |
| 3528 | case 0xe: /* 1 1 1 0 */ |
| 3529 | vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; |
| 3530 | break; |
| 3531 | |
| 3532 | case 0x5: /* 0 1 0 1 */ |
| 3533 | case 0x7: /* 0 1 1 1 */ |
| 3534 | case 0xd: /* 1 1 0 1 */ |
| 3535 | case 0xf: /* 1 1 1 1 */ |
| 3536 | vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; |
| 3537 | break; |
| 3538 | |
| 3539 | default: |
| 3540 | break; |
| 3541 | } |
| 3542 | if (pause_result & (1<<0)) |
| 3543 | vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; |
| 3544 | if (pause_result & (1<<1)) |
| 3545 | vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 3546 | |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 3547 | } |
| 3548 | |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 3549 | static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, |
| 3550 | struct link_params *params, |
| 3551 | struct link_vars *vars) |
| 3552 | { |
| 3553 | u16 ld_pause; /* local */ |
| 3554 | u16 lp_pause; /* link partner */ |
| 3555 | u16 pause_result; |
| 3556 | struct bnx2x *bp = params->bp; |
| 3557 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { |
| 3558 | bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); |
| 3559 | bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); |
Yaniv Rosner | ca05f29 | 2012-04-04 01:28:55 +0000 | [diff] [blame] | 3560 | } else if (CHIP_IS_E3(bp) && |
| 3561 | SINGLE_MEDIA_DIRECT(params)) { |
| 3562 | u8 lane = bnx2x_get_warpcore_lane(phy, params); |
| 3563 | u16 gp_status, gp_mask; |
| 3564 | bnx2x_cl45_read(bp, phy, |
| 3565 | MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, |
| 3566 | &gp_status); |
| 3567 | gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | |
| 3568 | MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << |
| 3569 | lane; |
| 3570 | if ((gp_status & gp_mask) == gp_mask) { |
| 3571 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, |
| 3572 | MDIO_AN_REG_ADV_PAUSE, &ld_pause); |
| 3573 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, |
| 3574 | MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); |
| 3575 | } else { |
| 3576 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, |
| 3577 | MDIO_AN_REG_CL37_FC_LD, &ld_pause); |
| 3578 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, |
| 3579 | MDIO_AN_REG_CL37_FC_LP, &lp_pause); |
| 3580 | ld_pause = ((ld_pause & |
| 3581 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) |
| 3582 | << 3); |
| 3583 | lp_pause = ((lp_pause & |
| 3584 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) |
| 3585 | << 3); |
| 3586 | } |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 3587 | } else { |
| 3588 | bnx2x_cl45_read(bp, phy, |
| 3589 | MDIO_AN_DEVAD, |
| 3590 | MDIO_AN_REG_ADV_PAUSE, &ld_pause); |
| 3591 | bnx2x_cl45_read(bp, phy, |
| 3592 | MDIO_AN_DEVAD, |
| 3593 | MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); |
| 3594 | } |
| 3595 | pause_result = (ld_pause & |
| 3596 | MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; |
| 3597 | pause_result |= (lp_pause & |
| 3598 | MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; |
| 3599 | DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result); |
| 3600 | bnx2x_pause_resolve(vars, pause_result); |
| 3601 | |
| 3602 | } |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 3603 | |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 3604 | static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, |
| 3605 | struct link_params *params, |
| 3606 | struct link_vars *vars) |
| 3607 | { |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 3608 | u8 ret = 0; |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 3609 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 3610 | if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { |
| 3611 | /* Update the advertised flow-controled of LD/LP in AN */ |
| 3612 | if (phy->req_line_speed == SPEED_AUTO_NEG) |
| 3613 | bnx2x_ext_phy_update_adv_fc(phy, params, vars); |
| 3614 | /* But set the flow-control result as the requested one */ |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 3615 | vars->flow_ctrl = phy->req_flow_ctrl; |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 3616 | } else if (phy->req_line_speed != SPEED_AUTO_NEG) |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 3617 | vars->flow_ctrl = params->req_fc_auto_adv; |
| 3618 | else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { |
| 3619 | ret = 1; |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 3620 | bnx2x_ext_phy_update_adv_fc(phy, params, vars); |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 3621 | } |
| 3622 | return ret; |
| 3623 | } |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3624 | /******************************************************************/ |
| 3625 | /* Warpcore section */ |
| 3626 | /******************************************************************/ |
| 3627 | /* The init_internal_warpcore should mirror the xgxs, |
| 3628 | * i.e. reset the lane (if needed), set aer for the |
| 3629 | * init configuration, and set/clear SGMII flag. Internal |
| 3630 | * phy init is done purely in phy_init stage. |
| 3631 | */ |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 3632 | static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy, |
| 3633 | struct link_params *params, |
| 3634 | struct link_vars *vars) |
| 3635 | { |
| 3636 | struct bnx2x *bp = params->bp; |
| 3637 | u16 i; |
| 3638 | static struct bnx2x_reg_set reg_set[] = { |
| 3639 | /* Step 1 - Program the TX/RX alignment markers */ |
| 3640 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, |
| 3641 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, |
| 3642 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, |
| 3643 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, |
| 3644 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, |
| 3645 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, |
| 3646 | /* Step 2 - Configure the NP registers */ |
| 3647 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, |
| 3648 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, |
| 3649 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, |
| 3650 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, |
| 3651 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, |
| 3652 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, |
| 3653 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, |
| 3654 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, |
| 3655 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} |
| 3656 | }; |
| 3657 | DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n"); |
| 3658 | |
| 3659 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 3660 | MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6)); |
| 3661 | |
Sasha Levin | b5a0555 | 2012-12-20 09:11:24 +0000 | [diff] [blame] | 3662 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 3663 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, |
| 3664 | reg_set[i].val); |
| 3665 | |
| 3666 | /* Start KR2 work-around timer which handles BCM8073 link-parner */ |
| 3667 | vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; |
| 3668 | bnx2x_update_link_attr(params, vars->link_attr_sync); |
| 3669 | } |
Yuval Mintz | ec4010e | 2012-09-10 05:51:06 +0000 | [diff] [blame] | 3670 | |
| 3671 | static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy, |
| 3672 | struct link_params *params) |
| 3673 | { |
| 3674 | struct bnx2x *bp = params->bp; |
| 3675 | |
| 3676 | DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n"); |
| 3677 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3678 | MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); |
| 3679 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 3680 | MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); |
| 3681 | } |
| 3682 | |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 3683 | static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy, |
| 3684 | struct link_params *params) |
| 3685 | { |
| 3686 | /* Restart autoneg on the leading lane only */ |
| 3687 | struct bnx2x *bp = params->bp; |
| 3688 | u16 lane = bnx2x_get_warpcore_lane(phy, params); |
| 3689 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
| 3690 | MDIO_AER_BLOCK_AER_REG, lane); |
| 3691 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
| 3692 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); |
| 3693 | |
| 3694 | /* Restore AER */ |
| 3695 | bnx2x_set_aer_mmd(params, phy); |
| 3696 | } |
| 3697 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3698 | static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, |
| 3699 | struct link_params *params, |
| 3700 | struct link_vars *vars) { |
Yaniv Rosner | cd1a26a | 2012-10-31 05:46:54 +0000 | [diff] [blame] | 3701 | u16 lane, i, cl72_ctrl, an_adv = 0; |
| 3702 | u16 ucode_ver; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3703 | struct bnx2x *bp = params->bp; |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3704 | static struct bnx2x_reg_set reg_set[] = { |
| 3705 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3706 | {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, |
| 3707 | {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, |
| 3708 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, |
| 3709 | /* Disable Autoneg: re-enable it after adv is done. */ |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 3710 | {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}, |
| 3711 | {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}, |
| 3712 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3713 | }; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3714 | DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n"); |
Yaniv Rosner | 6a51c0d | 2012-04-04 01:28:56 +0000 | [diff] [blame] | 3715 | /* Set to default registers that may be overriden by 10G force */ |
Sasha Levin | b5a0555 | 2012-12-20 09:11:24 +0000 | [diff] [blame] | 3716 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3717 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, |
| 3718 | reg_set[i].val); |
Yaniv Rosner | a9077bf | 2011-10-27 05:09:46 +0000 | [diff] [blame] | 3719 | |
Yaniv Rosner | b457bcb | 2012-10-31 05:46:52 +0000 | [diff] [blame] | 3720 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 3721 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 3722 | cl72_ctrl &= 0x08ff; |
Yaniv Rosner | b457bcb | 2012-10-31 05:46:52 +0000 | [diff] [blame] | 3723 | cl72_ctrl |= 0x3800; |
| 3724 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 3725 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); |
Yaniv Rosner | b457bcb | 2012-10-31 05:46:52 +0000 | [diff] [blame] | 3726 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3727 | /* Check adding advertisement for 1G KX */ |
| 3728 | if (((vars->line_speed == SPEED_AUTO_NEG) && |
| 3729 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || |
| 3730 | (vars->line_speed == SPEED_1000)) { |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3731 | u32 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; |
Yaniv Rosner | cd1a26a | 2012-10-31 05:46:54 +0000 | [diff] [blame] | 3732 | an_adv |= (1<<5); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3733 | |
| 3734 | /* Enable CL37 1G Parallel Detect */ |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3735 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3736 | DP(NETIF_MSG_LINK, "Advertize 1G\n"); |
| 3737 | } |
| 3738 | if (((vars->line_speed == SPEED_AUTO_NEG) && |
| 3739 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || |
| 3740 | (vars->line_speed == SPEED_10000)) { |
| 3741 | /* Check adding advertisement for 10G KR */ |
Yaniv Rosner | cd1a26a | 2012-10-31 05:46:54 +0000 | [diff] [blame] | 3742 | an_adv |= (1<<7); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3743 | /* Enable 10G Parallel Detect */ |
Yaniv Rosner | cd1a26a | 2012-10-31 05:46:54 +0000 | [diff] [blame] | 3744 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
| 3745 | MDIO_AER_BLOCK_AER_REG, 0); |
| 3746 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3747 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3748 | MDIO_WC_REG_PAR_DET_10G_CTRL, 1); |
Yaniv Rosner | cd1a26a | 2012-10-31 05:46:54 +0000 | [diff] [blame] | 3749 | bnx2x_set_aer_mmd(params, phy); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3750 | DP(NETIF_MSG_LINK, "Advertize 10G\n"); |
| 3751 | } |
| 3752 | |
| 3753 | /* Set Transmit PMD settings */ |
| 3754 | lane = bnx2x_get_warpcore_lane(phy, params); |
| 3755 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3756 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, |
| 3757 | ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | |
| 3758 | (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | |
| 3759 | (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))); |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 3760 | /* Configure the next lane if dual mode */ |
| 3761 | if (phy->flags & FLAGS_WC_DUAL_MODE) |
| 3762 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3763 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), |
| 3764 | ((0x02 << |
| 3765 | MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | |
| 3766 | (0x06 << |
| 3767 | MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | |
| 3768 | (0x09 << |
| 3769 | MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3770 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3771 | MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, |
| 3772 | 0x03f0); |
| 3773 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3774 | MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, |
| 3775 | 0x03f0); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3776 | |
| 3777 | /* Advertised speeds */ |
| 3778 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
Yaniv Rosner | cd1a26a | 2012-10-31 05:46:54 +0000 | [diff] [blame] | 3779 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3780 | |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 3781 | /* Advertised and set FEC (Forward Error Correction) */ |
| 3782 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
| 3783 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, |
| 3784 | (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | |
| 3785 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); |
| 3786 | |
Yaniv Rosner | a34bc96 | 2011-07-05 01:06:41 +0000 | [diff] [blame] | 3787 | /* Enable CL37 BAM */ |
| 3788 | if (REG_RD(bp, params->shmem_base + |
| 3789 | offsetof(struct shmem_region, dev_info. |
| 3790 | port_hw_config[params->port].default_cfg)) & |
| 3791 | PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3792 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 3793 | MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, |
| 3794 | 1); |
Yaniv Rosner | a34bc96 | 2011-07-05 01:06:41 +0000 | [diff] [blame] | 3795 | DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); |
| 3796 | } |
| 3797 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3798 | /* Advertise pause */ |
| 3799 | bnx2x_ext_phy_set_pause(params, phy, vars); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 3800 | /* Set KR Autoneg Work-Around flag for Warpcore version older than D108 |
Yaniv Rosner | 6ab48a5 | 2012-01-17 02:33:29 +0000 | [diff] [blame] | 3801 | */ |
| 3802 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
Yaniv Rosner | cd1a26a | 2012-10-31 05:46:54 +0000 | [diff] [blame] | 3803 | MDIO_WC_REG_UC_INFO_B1_VERSION, &ucode_ver); |
| 3804 | if (ucode_ver < 0xd108) { |
| 3805 | DP(NETIF_MSG_LINK, "Enable AN KR work-around. WC ver:0x%x\n", |
| 3806 | ucode_ver); |
Yaniv Rosner | 6ab48a5 | 2012-01-17 02:33:29 +0000 | [diff] [blame] | 3807 | vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; |
| 3808 | } |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3809 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 3810 | MDIO_WC_REG_DIGITAL5_MISC7, 0x100); |
Yaniv Rosner | a9077bf | 2011-10-27 05:09:46 +0000 | [diff] [blame] | 3811 | |
| 3812 | /* Over 1G - AN local device user page 1 */ |
| 3813 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3814 | MDIO_WC_REG_DIGITAL3_UP1, 0x1f); |
| 3815 | |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 3816 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
| 3817 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || |
| 3818 | (phy->req_line_speed == SPEED_20000)) { |
Yaniv Rosner | a9077bf | 2011-10-27 05:09:46 +0000 | [diff] [blame] | 3819 | |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 3820 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
| 3821 | MDIO_AER_BLOCK_AER_REG, lane); |
| 3822 | |
| 3823 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 3824 | MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), |
| 3825 | (1<<11)); |
| 3826 | |
| 3827 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3828 | MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); |
| 3829 | bnx2x_set_aer_mmd(params, phy); |
| 3830 | |
| 3831 | bnx2x_warpcore_enable_AN_KR2(phy, params, vars); |
| 3832 | } |
| 3833 | |
| 3834 | /* Enable Autoneg: only on the main lane */ |
| 3835 | bnx2x_warpcore_restart_AN_KR(phy, params); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3836 | } |
| 3837 | |
| 3838 | static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, |
| 3839 | struct link_params *params, |
| 3840 | struct link_vars *vars) |
| 3841 | { |
| 3842 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | cd1a26a | 2012-10-31 05:46:54 +0000 | [diff] [blame] | 3843 | u16 val16, i, lane; |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3844 | static struct bnx2x_reg_set reg_set[] = { |
| 3845 | /* Disable Autoneg */ |
| 3846 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3847 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, |
| 3848 | 0x3f00}, |
| 3849 | {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, |
| 3850 | {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, |
| 3851 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, |
| 3852 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3853 | /* Leave cl72 training enable, needed for KR */ |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 3854 | {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2} |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3855 | }; |
| 3856 | |
Sasha Levin | b5a0555 | 2012-12-20 09:11:24 +0000 | [diff] [blame] | 3857 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3858 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, |
| 3859 | reg_set[i].val); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3860 | |
Yaniv Rosner | cd1a26a | 2012-10-31 05:46:54 +0000 | [diff] [blame] | 3861 | lane = bnx2x_get_warpcore_lane(phy, params); |
| 3862 | /* Global registers */ |
| 3863 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
| 3864 | MDIO_AER_BLOCK_AER_REG, 0); |
| 3865 | /* Disable CL36 PCS Tx */ |
| 3866 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 3867 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); |
| 3868 | val16 &= ~(0x0011 << lane); |
| 3869 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3870 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3871 | |
Yaniv Rosner | cd1a26a | 2012-10-31 05:46:54 +0000 | [diff] [blame] | 3872 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 3873 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); |
| 3874 | val16 |= (0x0303 << (lane << 1)); |
| 3875 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3876 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); |
| 3877 | /* Restore AER */ |
| 3878 | bnx2x_set_aer_mmd(params, phy); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3879 | /* Set speed via PMA/PMD register */ |
| 3880 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, |
| 3881 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); |
| 3882 | |
| 3883 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, |
| 3884 | MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); |
| 3885 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 3886 | /* Enable encoded forced speed */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3887 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3888 | MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); |
| 3889 | |
| 3890 | /* Turn TX scramble payload only the 64/66 scrambler */ |
| 3891 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3892 | MDIO_WC_REG_TX66_CONTROL, 0x9); |
| 3893 | |
| 3894 | /* Turn RX scramble payload only the 64/66 scrambler */ |
| 3895 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 3896 | MDIO_WC_REG_RX66_CONTROL, 0xF9); |
| 3897 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 3898 | /* Set and clear loopback to cause a reset to 64/66 decoder */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3899 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3900 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); |
| 3901 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3902 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); |
| 3903 | |
| 3904 | } |
| 3905 | |
| 3906 | static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, |
| 3907 | struct link_params *params, |
| 3908 | u8 is_xfi) |
| 3909 | { |
| 3910 | struct bnx2x *bp = params->bp; |
| 3911 | u16 misc1_val, tap_val, tx_driver_val, lane, val; |
| 3912 | /* Hold rxSeqStart */ |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3913 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 3914 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3915 | |
| 3916 | /* Hold tx_fifo_reset */ |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3917 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 3918 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3919 | |
| 3920 | /* Disable CL73 AN */ |
| 3921 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); |
| 3922 | |
| 3923 | /* Disable 100FX Enable and Auto-Detect */ |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 3924 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
| 3925 | MDIO_WC_REG_FX100_CTRL1, 0xFFFA); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3926 | |
| 3927 | /* Disable 100FX Idle detect */ |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3928 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 3929 | MDIO_WC_REG_FX100_CTRL3, 0x0080); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3930 | |
| 3931 | /* Set Block address to Remote PHY & Clear forced_speed[5] */ |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 3932 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
| 3933 | MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3934 | |
| 3935 | /* Turn off auto-detect & fiber mode */ |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 3936 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
| 3937 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, |
| 3938 | 0xFFEE); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3939 | |
| 3940 | /* Set filter_force_link, disable_false_link and parallel_detect */ |
| 3941 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 3942 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); |
| 3943 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3944 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, |
| 3945 | ((val | 0x0006) & 0xFFFE)); |
| 3946 | |
| 3947 | /* Set XFI / SFI */ |
| 3948 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 3949 | MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); |
| 3950 | |
| 3951 | misc1_val &= ~(0x1f); |
| 3952 | |
| 3953 | if (is_xfi) { |
| 3954 | misc1_val |= 0x5; |
| 3955 | tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | |
| 3956 | (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | |
| 3957 | (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)); |
| 3958 | tx_driver_val = |
| 3959 | ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | |
| 3960 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | |
| 3961 | (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)); |
| 3962 | |
| 3963 | } else { |
| 3964 | misc1_val |= 0x9; |
Yaniv Rosner | 25182fc | 2012-04-04 01:28:57 +0000 | [diff] [blame] | 3965 | tap_val = ((0x0f << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | |
| 3966 | (0x2b << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | |
| 3967 | (0x02 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3968 | tx_driver_val = |
Yaniv Rosner | 25182fc | 2012-04-04 01:28:57 +0000 | [diff] [blame] | 3969 | ((0x03 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3970 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | |
Yaniv Rosner | 25182fc | 2012-04-04 01:28:57 +0000 | [diff] [blame] | 3971 | (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3972 | } |
| 3973 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3974 | MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); |
| 3975 | |
| 3976 | /* Set Transmit PMD settings */ |
| 3977 | lane = bnx2x_get_warpcore_lane(phy, params); |
| 3978 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3979 | MDIO_WC_REG_TX_FIR_TAP, |
| 3980 | tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); |
| 3981 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3982 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, |
| 3983 | tx_driver_val); |
| 3984 | |
| 3985 | /* Enable fiber mode, enable and invert sig_det */ |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3986 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 3987 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3988 | |
| 3989 | /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 3990 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 3991 | MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3992 | |
Yuval Mintz | ec4010e | 2012-09-10 05:51:06 +0000 | [diff] [blame] | 3993 | bnx2x_warpcore_set_lpi_passthrough(phy, params); |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 3994 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 3995 | /* 10G XFI Full Duplex */ |
| 3996 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3997 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); |
| 3998 | |
| 3999 | /* Release tx_fifo_reset */ |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 4000 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
| 4001 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, |
| 4002 | 0xFFFE); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4003 | /* Release rxSeqStart */ |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 4004 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
| 4005 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4006 | } |
| 4007 | |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 4008 | static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy, |
| 4009 | struct link_params *params) |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4010 | { |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 4011 | u16 val; |
| 4012 | struct bnx2x *bp = params->bp; |
| 4013 | /* Set global registers, so set AER lane to 0 */ |
| 4014 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
| 4015 | MDIO_AER_BLOCK_AER_REG, 0); |
| 4016 | |
| 4017 | /* Disable sequencer */ |
| 4018 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
| 4019 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13)); |
| 4020 | |
| 4021 | bnx2x_set_aer_mmd(params, phy); |
| 4022 | |
| 4023 | bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD, |
| 4024 | MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1)); |
| 4025 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
| 4026 | MDIO_AN_REG_CTRL, 0); |
| 4027 | /* Turn off CL73 */ |
| 4028 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 4029 | MDIO_WC_REG_CL73_USERB0_CTRL, &val); |
| 4030 | val &= ~(1<<5); |
| 4031 | val |= (1<<6); |
| 4032 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4033 | MDIO_WC_REG_CL73_USERB0_CTRL, val); |
| 4034 | |
| 4035 | /* Set 20G KR2 force speed */ |
| 4036 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 4037 | MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f); |
| 4038 | |
| 4039 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 4040 | MDIO_WC_REG_DIGITAL4_MISC3, (1<<7)); |
| 4041 | |
| 4042 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 4043 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val); |
| 4044 | val &= ~(3<<14); |
| 4045 | val |= (1<<15); |
| 4046 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4047 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val); |
| 4048 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4049 | MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A); |
| 4050 | |
| 4051 | /* Enable sequencer (over lane 0) */ |
| 4052 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
| 4053 | MDIO_AER_BLOCK_AER_REG, 0); |
| 4054 | |
| 4055 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 4056 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13)); |
| 4057 | |
| 4058 | bnx2x_set_aer_mmd(params, phy); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4059 | } |
| 4060 | |
| 4061 | static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, |
| 4062 | struct bnx2x_phy *phy, |
| 4063 | u16 lane) |
| 4064 | { |
| 4065 | /* Rx0 anaRxControl1G */ |
| 4066 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4067 | MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); |
| 4068 | |
| 4069 | /* Rx2 anaRxControl1G */ |
| 4070 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4071 | MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); |
| 4072 | |
| 4073 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4074 | MDIO_WC_REG_RX66_SCW0, 0xE070); |
| 4075 | |
| 4076 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4077 | MDIO_WC_REG_RX66_SCW1, 0xC0D0); |
| 4078 | |
| 4079 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4080 | MDIO_WC_REG_RX66_SCW2, 0xA0B0); |
| 4081 | |
| 4082 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4083 | MDIO_WC_REG_RX66_SCW3, 0x8090); |
| 4084 | |
| 4085 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4086 | MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); |
| 4087 | |
| 4088 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4089 | MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); |
| 4090 | |
| 4091 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4092 | MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); |
| 4093 | |
| 4094 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4095 | MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); |
| 4096 | |
| 4097 | /* Serdes Digital Misc1 */ |
| 4098 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4099 | MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); |
| 4100 | |
| 4101 | /* Serdes Digital4 Misc3 */ |
| 4102 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4103 | MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); |
| 4104 | |
| 4105 | /* Set Transmit PMD settings */ |
| 4106 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4107 | MDIO_WC_REG_TX_FIR_TAP, |
| 4108 | ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | |
| 4109 | (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | |
| 4110 | (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) | |
| 4111 | MDIO_WC_REG_TX_FIR_TAP_ENABLE)); |
| 4112 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4113 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, |
| 4114 | ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | |
| 4115 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | |
| 4116 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))); |
| 4117 | } |
| 4118 | |
| 4119 | static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, |
| 4120 | struct link_params *params, |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 4121 | u8 fiber_mode, |
| 4122 | u8 always_autoneg) |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4123 | { |
| 4124 | struct bnx2x *bp = params->bp; |
| 4125 | u16 val16, digctrl_kx1, digctrl_kx2; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4126 | |
| 4127 | /* Clear XFI clock comp in non-10G single lane mode. */ |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 4128 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
| 4129 | MDIO_WC_REG_RX66_CONTROL, ~(3<<13)); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4130 | |
Yuval Mintz | 26964bb | 2012-09-10 05:51:08 +0000 | [diff] [blame] | 4131 | bnx2x_warpcore_set_lpi_passthrough(phy, params); |
| 4132 | |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 4133 | if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4134 | /* SGMII Autoneg */ |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 4135 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 4136 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, |
| 4137 | 0x1000); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4138 | DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); |
| 4139 | } else { |
| 4140 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 4141 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 4142 | val16 &= 0xcebf; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4143 | switch (phy->req_line_speed) { |
| 4144 | case SPEED_10: |
| 4145 | break; |
| 4146 | case SPEED_100: |
| 4147 | val16 |= 0x2000; |
| 4148 | break; |
| 4149 | case SPEED_1000: |
| 4150 | val16 |= 0x0040; |
| 4151 | break; |
| 4152 | default: |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 4153 | DP(NETIF_MSG_LINK, |
| 4154 | "Speed not supported: 0x%x\n", phy->req_line_speed); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4155 | return; |
| 4156 | } |
| 4157 | |
| 4158 | if (phy->req_duplex == DUPLEX_FULL) |
| 4159 | val16 |= 0x0100; |
| 4160 | |
| 4161 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4162 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); |
| 4163 | |
| 4164 | DP(NETIF_MSG_LINK, "set SGMII force speed %d\n", |
| 4165 | phy->req_line_speed); |
| 4166 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 4167 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); |
| 4168 | DP(NETIF_MSG_LINK, " (readback) %x\n", val16); |
| 4169 | } |
| 4170 | |
| 4171 | /* SGMII Slave mode and disable signal detect */ |
| 4172 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 4173 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); |
| 4174 | if (fiber_mode) |
| 4175 | digctrl_kx1 = 1; |
| 4176 | else |
| 4177 | digctrl_kx1 &= 0xff4a; |
| 4178 | |
| 4179 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4180 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, |
| 4181 | digctrl_kx1); |
| 4182 | |
| 4183 | /* Turn off parallel detect */ |
| 4184 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 4185 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); |
| 4186 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4187 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, |
| 4188 | (digctrl_kx2 & ~(1<<2))); |
| 4189 | |
| 4190 | /* Re-enable parallel detect */ |
| 4191 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4192 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, |
| 4193 | (digctrl_kx2 | (1<<2))); |
| 4194 | |
| 4195 | /* Enable autodet */ |
| 4196 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4197 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, |
| 4198 | (digctrl_kx1 | 0x10)); |
| 4199 | } |
| 4200 | |
| 4201 | static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, |
| 4202 | struct bnx2x_phy *phy, |
| 4203 | u8 reset) |
| 4204 | { |
| 4205 | u16 val; |
| 4206 | /* Take lane out of reset after configuration is finished */ |
| 4207 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 4208 | MDIO_WC_REG_DIGITAL5_MISC6, &val); |
| 4209 | if (reset) |
| 4210 | val |= 0xC000; |
| 4211 | else |
| 4212 | val &= 0x3FFF; |
| 4213 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4214 | MDIO_WC_REG_DIGITAL5_MISC6, val); |
| 4215 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 4216 | MDIO_WC_REG_DIGITAL5_MISC6, &val); |
| 4217 | } |
Yaniv Rosner | 2f751a8 | 2011-11-28 00:49:52 +0000 | [diff] [blame] | 4218 | /* Clear SFI/XFI link settings registers */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4219 | static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, |
| 4220 | struct link_params *params, |
| 4221 | u16 lane) |
| 4222 | { |
| 4223 | struct bnx2x *bp = params->bp; |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 4224 | u16 i; |
| 4225 | static struct bnx2x_reg_set wc_regs[] = { |
| 4226 | {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, |
| 4227 | {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, |
| 4228 | {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, |
| 4229 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, |
| 4230 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, |
| 4231 | 0x0195}, |
| 4232 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, |
| 4233 | 0x0007}, |
| 4234 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, |
| 4235 | 0x0002}, |
| 4236 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, |
| 4237 | {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, |
| 4238 | {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, |
| 4239 | {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} |
| 4240 | }; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4241 | /* Set XFI clock comp as default. */ |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 4242 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 4243 | MDIO_WC_REG_RX66_CONTROL, (3<<13)); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4244 | |
Sasha Levin | b5a0555 | 2012-12-20 09:11:24 +0000 | [diff] [blame] | 4245 | for (i = 0; i < ARRAY_SIZE(wc_regs); i++) |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 4246 | bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, |
| 4247 | wc_regs[i].val); |
| 4248 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4249 | lane = bnx2x_get_warpcore_lane(phy, params); |
| 4250 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4251 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 4252 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4253 | } |
| 4254 | |
| 4255 | static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, |
| 4256 | u32 chip_id, |
| 4257 | u32 shmem_base, u8 port, |
| 4258 | u8 *gpio_num, u8 *gpio_port) |
| 4259 | { |
| 4260 | u32 cfg_pin; |
| 4261 | *gpio_num = 0; |
| 4262 | *gpio_port = 0; |
| 4263 | if (CHIP_IS_E3(bp)) { |
| 4264 | cfg_pin = (REG_RD(bp, shmem_base + |
| 4265 | offsetof(struct shmem_region, |
| 4266 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & |
| 4267 | PORT_HW_CFG_E3_MOD_ABS_MASK) >> |
| 4268 | PORT_HW_CFG_E3_MOD_ABS_SHIFT; |
| 4269 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 4270 | /* Should not happen. This function called upon interrupt |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4271 | * triggered by GPIO ( since EPIO can only generate interrupts |
| 4272 | * to MCP). |
| 4273 | * So if this function was called and none of the GPIOs was set, |
| 4274 | * it means the shit hit the fan. |
| 4275 | */ |
| 4276 | if ((cfg_pin < PIN_CFG_GPIO0_P0) || |
| 4277 | (cfg_pin > PIN_CFG_GPIO3_P1)) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 4278 | DP(NETIF_MSG_LINK, |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 4279 | "No cfg pin %x for module detect indication\n", |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 4280 | cfg_pin); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4281 | return -EINVAL; |
| 4282 | } |
| 4283 | |
| 4284 | *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; |
| 4285 | *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; |
| 4286 | } else { |
| 4287 | *gpio_num = MISC_REGISTERS_GPIO_3; |
| 4288 | *gpio_port = port; |
| 4289 | } |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 4290 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4291 | return 0; |
| 4292 | } |
| 4293 | |
| 4294 | static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, |
| 4295 | struct link_params *params) |
| 4296 | { |
| 4297 | struct bnx2x *bp = params->bp; |
| 4298 | u8 gpio_num, gpio_port; |
| 4299 | u32 gpio_val; |
| 4300 | if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, |
| 4301 | params->shmem_base, params->port, |
| 4302 | &gpio_num, &gpio_port) != 0) |
| 4303 | return 0; |
| 4304 | gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); |
| 4305 | |
| 4306 | /* Call the handling function in case module is detected */ |
| 4307 | if (gpio_val == 0) |
| 4308 | return 1; |
| 4309 | else |
| 4310 | return 0; |
| 4311 | } |
Yaniv Rosner | a9077bf | 2011-10-27 05:09:46 +0000 | [diff] [blame] | 4312 | static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 4313 | struct link_params *params) |
Yaniv Rosner | a9077bf | 2011-10-27 05:09:46 +0000 | [diff] [blame] | 4314 | { |
| 4315 | u16 gp2_status_reg0, lane; |
| 4316 | struct bnx2x *bp = params->bp; |
| 4317 | |
| 4318 | lane = bnx2x_get_warpcore_lane(phy, params); |
| 4319 | |
| 4320 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, |
| 4321 | &gp2_status_reg0); |
| 4322 | |
| 4323 | return (gp2_status_reg0 >> (8+lane)) & 0x1; |
| 4324 | } |
| 4325 | |
| 4326 | static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 4327 | struct link_params *params, |
| 4328 | struct link_vars *vars) |
Yaniv Rosner | a9077bf | 2011-10-27 05:09:46 +0000 | [diff] [blame] | 4329 | { |
| 4330 | struct bnx2x *bp = params->bp; |
| 4331 | u32 serdes_net_if; |
| 4332 | u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; |
| 4333 | u16 lane = bnx2x_get_warpcore_lane(phy, params); |
| 4334 | |
| 4335 | vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; |
| 4336 | |
| 4337 | if (!vars->turn_to_run_wc_rt) |
| 4338 | return; |
| 4339 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 4340 | /* Return if there is no link partner */ |
Yaniv Rosner | a9077bf | 2011-10-27 05:09:46 +0000 | [diff] [blame] | 4341 | if (!(bnx2x_warpcore_get_sigdet(phy, params))) { |
| 4342 | DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n"); |
| 4343 | return; |
| 4344 | } |
| 4345 | |
| 4346 | if (vars->rx_tx_asic_rst) { |
| 4347 | serdes_net_if = (REG_RD(bp, params->shmem_base + |
| 4348 | offsetof(struct shmem_region, dev_info. |
| 4349 | port_hw_config[params->port].default_cfg)) & |
| 4350 | PORT_HW_CFG_NET_SERDES_IF_MASK); |
| 4351 | |
| 4352 | switch (serdes_net_if) { |
| 4353 | case PORT_HW_CFG_NET_SERDES_IF_KR: |
| 4354 | /* Do we get link yet? */ |
| 4355 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 4356 | &gp_status1); |
Yaniv Rosner | a9077bf | 2011-10-27 05:09:46 +0000 | [diff] [blame] | 4357 | lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ |
| 4358 | /*10G KR*/ |
| 4359 | lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; |
| 4360 | |
| 4361 | DP(NETIF_MSG_LINK, |
| 4362 | "gp_status1 0x%x\n", gp_status1); |
| 4363 | |
| 4364 | if (lnkup_kr || lnkup) { |
| 4365 | vars->rx_tx_asic_rst = 0; |
| 4366 | DP(NETIF_MSG_LINK, |
| 4367 | "link up, rx_tx_asic_rst 0x%x\n", |
| 4368 | vars->rx_tx_asic_rst); |
| 4369 | } else { |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 4370 | /* Reset the lane to see if link comes up.*/ |
Yaniv Rosner | a9077bf | 2011-10-27 05:09:46 +0000 | [diff] [blame] | 4371 | bnx2x_warpcore_reset_lane(bp, phy, 1); |
| 4372 | bnx2x_warpcore_reset_lane(bp, phy, 0); |
| 4373 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 4374 | /* Restart Autoneg */ |
Yaniv Rosner | a9077bf | 2011-10-27 05:09:46 +0000 | [diff] [blame] | 4375 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
| 4376 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); |
| 4377 | |
| 4378 | vars->rx_tx_asic_rst--; |
| 4379 | DP(NETIF_MSG_LINK, "0x%x retry left\n", |
| 4380 | vars->rx_tx_asic_rst); |
| 4381 | } |
| 4382 | break; |
| 4383 | |
| 4384 | default: |
| 4385 | break; |
| 4386 | } |
| 4387 | |
| 4388 | } /*params->rx_tx_asic_rst*/ |
| 4389 | |
| 4390 | } |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 4391 | static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy, |
| 4392 | struct link_params *params) |
| 4393 | { |
| 4394 | u16 lane = bnx2x_get_warpcore_lane(phy, params); |
| 4395 | struct bnx2x *bp = params->bp; |
| 4396 | bnx2x_warpcore_clear_regs(phy, params, lane); |
| 4397 | if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] == |
| 4398 | SPEED_10000) && |
| 4399 | (phy->media_type != ETH_PHY_SFP_1G_FIBER)) { |
| 4400 | DP(NETIF_MSG_LINK, "Setting 10G SFI\n"); |
| 4401 | bnx2x_warpcore_set_10G_XFI(phy, params, 0); |
| 4402 | } else { |
| 4403 | DP(NETIF_MSG_LINK, "Setting 1G Fiber\n"); |
| 4404 | bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0); |
| 4405 | } |
| 4406 | } |
| 4407 | |
Yaniv Rosner | 5a1fbf4 | 2012-11-27 03:46:31 +0000 | [diff] [blame] | 4408 | static void bnx2x_sfp_e3_set_transmitter(struct link_params *params, |
| 4409 | struct bnx2x_phy *phy, |
| 4410 | u8 tx_en) |
| 4411 | { |
| 4412 | struct bnx2x *bp = params->bp; |
| 4413 | u32 cfg_pin; |
| 4414 | u8 port = params->port; |
| 4415 | |
| 4416 | cfg_pin = REG_RD(bp, params->shmem_base + |
| 4417 | offsetof(struct shmem_region, |
| 4418 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & |
| 4419 | PORT_HW_CFG_E3_TX_LASER_MASK; |
| 4420 | /* Set the !tx_en since this pin is DISABLE_TX_LASER */ |
| 4421 | DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en); |
| 4422 | |
| 4423 | /* For 20G, the expected pin to be used is 3 pins after the current */ |
| 4424 | bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1); |
| 4425 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) |
| 4426 | bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1); |
| 4427 | } |
| 4428 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4429 | static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, |
| 4430 | struct link_params *params, |
| 4431 | struct link_vars *vars) |
| 4432 | { |
| 4433 | struct bnx2x *bp = params->bp; |
| 4434 | u32 serdes_net_if; |
| 4435 | u8 fiber_mode; |
| 4436 | u16 lane = bnx2x_get_warpcore_lane(phy, params); |
| 4437 | serdes_net_if = (REG_RD(bp, params->shmem_base + |
| 4438 | offsetof(struct shmem_region, dev_info. |
| 4439 | port_hw_config[params->port].default_cfg)) & |
| 4440 | PORT_HW_CFG_NET_SERDES_IF_MASK); |
| 4441 | DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, " |
| 4442 | "serdes_net_if = 0x%x\n", |
| 4443 | vars->line_speed, serdes_net_if); |
| 4444 | bnx2x_set_aer_mmd(params, phy); |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 4445 | bnx2x_warpcore_reset_lane(bp, phy, 1); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4446 | vars->phy_flags |= PHY_XGXS_FLAG; |
| 4447 | if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || |
| 4448 | (phy->req_line_speed && |
| 4449 | ((phy->req_line_speed == SPEED_100) || |
| 4450 | (phy->req_line_speed == SPEED_10)))) { |
| 4451 | vars->phy_flags |= PHY_SGMII_FLAG; |
| 4452 | DP(NETIF_MSG_LINK, "Setting SGMII mode\n"); |
| 4453 | bnx2x_warpcore_clear_regs(phy, params, lane); |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 4454 | bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4455 | } else { |
| 4456 | switch (serdes_net_if) { |
| 4457 | case PORT_HW_CFG_NET_SERDES_IF_KR: |
| 4458 | /* Enable KR Auto Neg */ |
Yaniv Rosner | 6a51c0d | 2012-04-04 01:28:56 +0000 | [diff] [blame] | 4459 | if (params->loopback_mode != LOOPBACK_EXT) |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4460 | bnx2x_warpcore_enable_AN_KR(phy, params, vars); |
| 4461 | else { |
| 4462 | DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n"); |
| 4463 | bnx2x_warpcore_set_10G_KR(phy, params, vars); |
| 4464 | } |
| 4465 | break; |
| 4466 | |
| 4467 | case PORT_HW_CFG_NET_SERDES_IF_XFI: |
| 4468 | bnx2x_warpcore_clear_regs(phy, params, lane); |
| 4469 | if (vars->line_speed == SPEED_10000) { |
| 4470 | DP(NETIF_MSG_LINK, "Setting 10G XFI\n"); |
| 4471 | bnx2x_warpcore_set_10G_XFI(phy, params, 1); |
| 4472 | } else { |
| 4473 | if (SINGLE_MEDIA_DIRECT(params)) { |
| 4474 | DP(NETIF_MSG_LINK, "1G Fiber\n"); |
| 4475 | fiber_mode = 1; |
| 4476 | } else { |
| 4477 | DP(NETIF_MSG_LINK, "10/100/1G SGMII\n"); |
| 4478 | fiber_mode = 0; |
| 4479 | } |
| 4480 | bnx2x_warpcore_set_sgmii_speed(phy, |
| 4481 | params, |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 4482 | fiber_mode, |
| 4483 | 0); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4484 | } |
| 4485 | |
| 4486 | break; |
| 4487 | |
| 4488 | case PORT_HW_CFG_NET_SERDES_IF_SFI: |
Yaniv Rosner | 5a1fbf4 | 2012-11-27 03:46:31 +0000 | [diff] [blame] | 4489 | /* Issue Module detection if module is plugged, or |
| 4490 | * enabled transmitter to avoid current leakage in case |
| 4491 | * no module is connected |
| 4492 | */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4493 | if (bnx2x_is_sfp_module_plugged(phy, params)) |
| 4494 | bnx2x_sfp_module_detection(phy, params); |
Yaniv Rosner | 5a1fbf4 | 2012-11-27 03:46:31 +0000 | [diff] [blame] | 4495 | else |
| 4496 | bnx2x_sfp_e3_set_transmitter(params, phy, 1); |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 4497 | |
| 4498 | bnx2x_warpcore_config_sfi(phy, params); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4499 | break; |
| 4500 | |
| 4501 | case PORT_HW_CFG_NET_SERDES_IF_DXGXS: |
| 4502 | if (vars->line_speed != SPEED_20000) { |
| 4503 | DP(NETIF_MSG_LINK, "Speed not supported yet\n"); |
| 4504 | return; |
| 4505 | } |
| 4506 | DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n"); |
| 4507 | bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); |
| 4508 | /* Issue Module detection */ |
| 4509 | |
| 4510 | bnx2x_sfp_module_detection(phy, params); |
| 4511 | break; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4512 | case PORT_HW_CFG_NET_SERDES_IF_KR2: |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 4513 | if (!params->loopback_mode) { |
| 4514 | bnx2x_warpcore_enable_AN_KR(phy, params, vars); |
| 4515 | } else { |
| 4516 | DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n"); |
| 4517 | bnx2x_warpcore_set_20G_force_KR2(phy, params); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4518 | } |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4519 | break; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4520 | default: |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 4521 | DP(NETIF_MSG_LINK, |
| 4522 | "Unsupported Serdes Net Interface 0x%x\n", |
| 4523 | serdes_net_if); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4524 | return; |
| 4525 | } |
| 4526 | } |
| 4527 | |
| 4528 | /* Take lane out of reset after configuration is finished */ |
| 4529 | bnx2x_warpcore_reset_lane(bp, phy, 0); |
| 4530 | DP(NETIF_MSG_LINK, "Exit config init\n"); |
| 4531 | } |
| 4532 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4533 | static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, |
| 4534 | struct link_params *params) |
| 4535 | { |
| 4536 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | cd1a26a | 2012-10-31 05:46:54 +0000 | [diff] [blame] | 4537 | u16 val16, lane; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4538 | bnx2x_sfp_e3_set_transmitter(params, phy, 0); |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 4539 | bnx2x_set_mdio_emac_per_phy(bp, params); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4540 | bnx2x_set_aer_mmd(params, phy); |
| 4541 | /* Global register */ |
| 4542 | bnx2x_warpcore_reset_lane(bp, phy, 1); |
| 4543 | |
| 4544 | /* Clear loopback settings (if any) */ |
| 4545 | /* 10G & 20G */ |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 4546 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
| 4547 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4548 | |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 4549 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
| 4550 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4551 | |
| 4552 | /* Update those 1-copy registers */ |
| 4553 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
| 4554 | MDIO_AER_BLOCK_AER_REG, 0); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 4555 | /* Enable 1G MDIO (1-copy) */ |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 4556 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
| 4557 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, |
| 4558 | ~0x10); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4559 | |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 4560 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
| 4561 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); |
Yaniv Rosner | cd1a26a | 2012-10-31 05:46:54 +0000 | [diff] [blame] | 4562 | lane = bnx2x_get_warpcore_lane(phy, params); |
| 4563 | /* Disable CL36 PCS Tx */ |
| 4564 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 4565 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); |
| 4566 | val16 |= (0x11 << lane); |
| 4567 | if (phy->flags & FLAGS_WC_DUAL_MODE) |
| 4568 | val16 |= (0x22 << lane); |
| 4569 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4570 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); |
| 4571 | |
| 4572 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 4573 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); |
| 4574 | val16 &= ~(0x0303 << (lane << 1)); |
| 4575 | val16 |= (0x0101 << (lane << 1)); |
| 4576 | if (phy->flags & FLAGS_WC_DUAL_MODE) { |
| 4577 | val16 &= ~(0x0c0c << (lane << 1)); |
| 4578 | val16 |= (0x0404 << (lane << 1)); |
| 4579 | } |
| 4580 | |
| 4581 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4582 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); |
| 4583 | /* Restore AER */ |
| 4584 | bnx2x_set_aer_mmd(params, phy); |
| 4585 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4586 | } |
| 4587 | |
| 4588 | static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, |
| 4589 | struct link_params *params) |
| 4590 | { |
| 4591 | struct bnx2x *bp = params->bp; |
| 4592 | u16 val16; |
| 4593 | u32 lane; |
| 4594 | DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n", |
| 4595 | params->loopback_mode, phy->req_line_speed); |
| 4596 | |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 4597 | if (phy->req_line_speed < SPEED_10000 || |
| 4598 | phy->supported & SUPPORTED_20000baseKR2_Full) { |
| 4599 | /* 10/100/1000/20G-KR2 */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4600 | |
| 4601 | /* Update those 1-copy registers */ |
| 4602 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
| 4603 | MDIO_AER_BLOCK_AER_REG, 0); |
| 4604 | /* Enable 1G MDIO (1-copy) */ |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 4605 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 4606 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, |
| 4607 | 0x10); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4608 | /* Set 1G loopback based on lane (1-copy) */ |
| 4609 | lane = bnx2x_get_warpcore_lane(phy, params); |
| 4610 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 4611 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 4612 | val16 |= (1<<lane); |
| 4613 | if (phy->flags & FLAGS_WC_DUAL_MODE) |
| 4614 | val16 |= (2<<lane); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4615 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 4616 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, |
| 4617 | val16); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4618 | |
| 4619 | /* Switch back to 4-copy registers */ |
| 4620 | bnx2x_set_aer_mmd(params, phy); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4621 | } else { |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 4622 | /* 10G / 20G-DXGXS */ |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 4623 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 4624 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, |
| 4625 | 0x4000); |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 4626 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 4627 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4628 | } |
| 4629 | } |
| 4630 | |
| 4631 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 4632 | |
| 4633 | static void bnx2x_sync_link(struct link_params *params, |
| 4634 | struct link_vars *vars) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 4635 | { |
| 4636 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 4637 | u8 link_10g_plus; |
Yaniv Rosner | de6f337 | 2011-08-02 22:59:25 +0000 | [diff] [blame] | 4638 | if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) |
| 4639 | vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; |
Yaniv Rosner | 2f751a8 | 2011-11-28 00:49:52 +0000 | [diff] [blame] | 4640 | vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 4641 | if (vars->link_up) { |
| 4642 | DP(NETIF_MSG_LINK, "phy link up\n"); |
| 4643 | |
| 4644 | vars->phy_link_up = 1; |
| 4645 | vars->duplex = DUPLEX_FULL; |
| 4646 | switch (vars->link_status & |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4647 | LINK_STATUS_SPEED_AND_DUPLEX_MASK) { |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 4648 | case LINK_10THD: |
| 4649 | vars->duplex = DUPLEX_HALF; |
| 4650 | /* Fall thru */ |
| 4651 | case LINK_10TFD: |
| 4652 | vars->line_speed = SPEED_10; |
| 4653 | break; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 4654 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 4655 | case LINK_100TXHD: |
| 4656 | vars->duplex = DUPLEX_HALF; |
| 4657 | /* Fall thru */ |
| 4658 | case LINK_100T4: |
| 4659 | case LINK_100TXFD: |
| 4660 | vars->line_speed = SPEED_100; |
| 4661 | break; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 4662 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 4663 | case LINK_1000THD: |
| 4664 | vars->duplex = DUPLEX_HALF; |
| 4665 | /* Fall thru */ |
| 4666 | case LINK_1000TFD: |
| 4667 | vars->line_speed = SPEED_1000; |
| 4668 | break; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 4669 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 4670 | case LINK_2500THD: |
| 4671 | vars->duplex = DUPLEX_HALF; |
| 4672 | /* Fall thru */ |
| 4673 | case LINK_2500TFD: |
| 4674 | vars->line_speed = SPEED_2500; |
| 4675 | break; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 4676 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 4677 | case LINK_10GTFD: |
| 4678 | vars->line_speed = SPEED_10000; |
| 4679 | break; |
| 4680 | case LINK_20GTFD: |
| 4681 | vars->line_speed = SPEED_20000; |
| 4682 | break; |
| 4683 | default: |
| 4684 | break; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 4685 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 4686 | vars->flow_ctrl = 0; |
| 4687 | if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) |
| 4688 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; |
| 4689 | |
| 4690 | if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) |
| 4691 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; |
| 4692 | |
| 4693 | if (!vars->flow_ctrl) |
| 4694 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
| 4695 | |
| 4696 | if (vars->line_speed && |
| 4697 | ((vars->line_speed == SPEED_10) || |
| 4698 | (vars->line_speed == SPEED_100))) { |
| 4699 | vars->phy_flags |= PHY_SGMII_FLAG; |
| 4700 | } else { |
| 4701 | vars->phy_flags &= ~PHY_SGMII_FLAG; |
| 4702 | } |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4703 | if (vars->line_speed && |
| 4704 | USES_WARPCORE(bp) && |
| 4705 | (vars->line_speed == SPEED_1000)) |
| 4706 | vars->phy_flags |= PHY_SGMII_FLAG; |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 4707 | /* Anything 10 and over uses the bmac */ |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 4708 | link_10g_plus = (vars->line_speed >= SPEED_10000); |
| 4709 | |
| 4710 | if (link_10g_plus) { |
| 4711 | if (USES_WARPCORE(bp)) |
| 4712 | vars->mac_type = MAC_TYPE_XMAC; |
| 4713 | else |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4714 | vars->mac_type = MAC_TYPE_BMAC; |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 4715 | } else { |
| 4716 | if (USES_WARPCORE(bp)) |
| 4717 | vars->mac_type = MAC_TYPE_UMAC; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 4718 | else |
| 4719 | vars->mac_type = MAC_TYPE_EMAC; |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 4720 | } |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 4721 | } else { /* Link down */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 4722 | DP(NETIF_MSG_LINK, "phy link down\n"); |
| 4723 | |
| 4724 | vars->phy_link_up = 0; |
| 4725 | |
| 4726 | vars->line_speed = 0; |
| 4727 | vars->duplex = DUPLEX_FULL; |
| 4728 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
| 4729 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 4730 | /* Indicate no mac active */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 4731 | vars->mac_type = MAC_TYPE_NONE; |
Yaniv Rosner | de6f337 | 2011-08-02 22:59:25 +0000 | [diff] [blame] | 4732 | if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) |
| 4733 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; |
Yuval Mintz | d0b8a6f | 2012-06-20 19:05:18 +0000 | [diff] [blame] | 4734 | if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) |
| 4735 | vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 4736 | } |
Yaniv Rosner | 2f751a8 | 2011-11-28 00:49:52 +0000 | [diff] [blame] | 4737 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 4738 | |
Yaniv Rosner | 2f751a8 | 2011-11-28 00:49:52 +0000 | [diff] [blame] | 4739 | void bnx2x_link_status_update(struct link_params *params, |
| 4740 | struct link_vars *vars) |
| 4741 | { |
| 4742 | struct bnx2x *bp = params->bp; |
| 4743 | u8 port = params->port; |
| 4744 | u32 sync_offset, media_types; |
| 4745 | /* Update PHY configuration */ |
| 4746 | set_phy_vars(params, vars); |
| 4747 | |
| 4748 | vars->link_status = REG_RD(bp, params->shmem_base + |
| 4749 | offsetof(struct shmem_region, |
| 4750 | port_mb[port].link_status)); |
Yuval Mintz | 08e9acc | 2012-09-10 05:51:04 +0000 | [diff] [blame] | 4751 | if (bnx2x_eee_has_cap(params)) |
| 4752 | vars->eee_status = REG_RD(bp, params->shmem2_base + |
| 4753 | offsetof(struct shmem2_region, |
| 4754 | eee_status[params->port])); |
Yaniv Rosner | 2f751a8 | 2011-11-28 00:49:52 +0000 | [diff] [blame] | 4755 | |
| 4756 | vars->phy_flags = PHY_XGXS_FLAG; |
| 4757 | bnx2x_sync_link(params, vars); |
Yaniv Rosner | 1ac9e42 | 2011-05-31 21:26:11 +0000 | [diff] [blame] | 4758 | /* Sync media type */ |
| 4759 | sync_offset = params->shmem_base + |
| 4760 | offsetof(struct shmem_region, |
| 4761 | dev_info.port_hw_config[port].media_type); |
| 4762 | media_types = REG_RD(bp, sync_offset); |
| 4763 | |
| 4764 | params->phy[INT_PHY].media_type = |
| 4765 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> |
| 4766 | PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; |
| 4767 | params->phy[EXT_PHY1].media_type = |
| 4768 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> |
| 4769 | PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; |
| 4770 | params->phy[EXT_PHY2].media_type = |
| 4771 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> |
| 4772 | PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; |
| 4773 | DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types); |
| 4774 | |
Yaniv Rosner | 020c7e3 | 2011-05-31 21:28:43 +0000 | [diff] [blame] | 4775 | /* Sync AEU offset */ |
| 4776 | sync_offset = params->shmem_base + |
| 4777 | offsetof(struct shmem_region, |
| 4778 | dev_info.port_hw_config[port].aeu_int_mask); |
| 4779 | |
| 4780 | vars->aeu_int_mask = REG_RD(bp, sync_offset); |
| 4781 | |
Yaniv Rosner | b8d6d08 | 2011-07-05 01:06:27 +0000 | [diff] [blame] | 4782 | /* Sync PFC status */ |
| 4783 | if (vars->link_status & LINK_STATUS_PFC_ENABLED) |
| 4784 | params->feature_config_flags |= |
| 4785 | FEATURE_CONFIG_PFC_ENABLED; |
| 4786 | else |
| 4787 | params->feature_config_flags &= |
| 4788 | ~FEATURE_CONFIG_PFC_ENABLED; |
| 4789 | |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 4790 | if (SHMEM2_HAS(bp, link_attr_sync)) |
| 4791 | vars->link_attr_sync = SHMEM2_RD(bp, |
| 4792 | link_attr_sync[params->port]); |
| 4793 | |
Yaniv Rosner | 020c7e3 | 2011-05-31 21:28:43 +0000 | [diff] [blame] | 4794 | DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", |
| 4795 | vars->link_status, vars->phy_link_up, vars->aeu_int_mask); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 4796 | DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", |
| 4797 | vars->line_speed, vars->duplex, vars->flow_ctrl); |
| 4798 | } |
| 4799 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 4800 | static void bnx2x_set_master_ln(struct link_params *params, |
| 4801 | struct bnx2x_phy *phy) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4802 | { |
| 4803 | struct bnx2x *bp = params->bp; |
| 4804 | u16 new_master_ln, ser_lane; |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4805 | ser_lane = ((params->lane_config & |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4806 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4807 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4808 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 4809 | /* Set the master_ln for AN */ |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4810 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4811 | MDIO_REG_BANK_XGXS_BLOCK2, |
| 4812 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, |
| 4813 | &new_master_ln); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4814 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4815 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4816 | MDIO_REG_BANK_XGXS_BLOCK2 , |
| 4817 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, |
| 4818 | (new_master_ln | ser_lane)); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4819 | } |
| 4820 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 4821 | static int bnx2x_reset_unicore(struct link_params *params, |
| 4822 | struct bnx2x_phy *phy, |
| 4823 | u8 set_serdes) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4824 | { |
| 4825 | struct bnx2x *bp = params->bp; |
| 4826 | u16 mii_control; |
| 4827 | u16 i; |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4828 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4829 | MDIO_REG_BANK_COMBO_IEEE0, |
| 4830 | MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4831 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 4832 | /* Reset the unicore */ |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4833 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4834 | MDIO_REG_BANK_COMBO_IEEE0, |
| 4835 | MDIO_COMBO_IEEE0_MII_CONTROL, |
| 4836 | (mii_control | |
| 4837 | MDIO_COMBO_IEEO_MII_CONTROL_RESET)); |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 4838 | if (set_serdes) |
| 4839 | bnx2x_set_serdes_access(bp, params->port); |
Eilon Greenstein | c1b7399 | 2009-02-12 08:37:07 +0000 | [diff] [blame] | 4840 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 4841 | /* Wait for the reset to self clear */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4842 | for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { |
| 4843 | udelay(5); |
| 4844 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 4845 | /* The reset erased the previous bank value */ |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4846 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4847 | MDIO_REG_BANK_COMBO_IEEE0, |
| 4848 | MDIO_COMBO_IEEE0_MII_CONTROL, |
| 4849 | &mii_control); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4850 | |
| 4851 | if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { |
| 4852 | udelay(5); |
| 4853 | return 0; |
| 4854 | } |
| 4855 | } |
| 4856 | |
Yaniv Rosner | 6d870c3 | 2011-01-31 04:22:20 +0000 | [diff] [blame] | 4857 | netdev_err(bp->dev, "Warning: PHY was not initialized," |
| 4858 | " Port %d\n", |
| 4859 | params->port); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4860 | DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n"); |
| 4861 | return -EINVAL; |
| 4862 | |
| 4863 | } |
| 4864 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 4865 | static void bnx2x_set_swap_lanes(struct link_params *params, |
| 4866 | struct bnx2x_phy *phy) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4867 | { |
| 4868 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 4869 | /* Each two bits represents a lane number: |
| 4870 | * No swap is 0123 => 0x1b no need to enable the swap |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 4871 | */ |
Yaniv Rosner | 2f751a8 | 2011-11-28 00:49:52 +0000 | [diff] [blame] | 4872 | u16 rx_lane_swap, tx_lane_swap; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4873 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4874 | rx_lane_swap = ((params->lane_config & |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4875 | PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> |
| 4876 | PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4877 | tx_lane_swap = ((params->lane_config & |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4878 | PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> |
| 4879 | PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4880 | |
| 4881 | if (rx_lane_swap != 0x1b) { |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4882 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4883 | MDIO_REG_BANK_XGXS_BLOCK2, |
| 4884 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, |
| 4885 | (rx_lane_swap | |
| 4886 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | |
| 4887 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4888 | } else { |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4889 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4890 | MDIO_REG_BANK_XGXS_BLOCK2, |
| 4891 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4892 | } |
| 4893 | |
| 4894 | if (tx_lane_swap != 0x1b) { |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4895 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4896 | MDIO_REG_BANK_XGXS_BLOCK2, |
| 4897 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, |
| 4898 | (tx_lane_swap | |
| 4899 | MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4900 | } else { |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4901 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4902 | MDIO_REG_BANK_XGXS_BLOCK2, |
| 4903 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4904 | } |
| 4905 | } |
| 4906 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 4907 | static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, |
| 4908 | struct link_params *params) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4909 | { |
| 4910 | struct bnx2x *bp = params->bp; |
| 4911 | u16 control2; |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4912 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4913 | MDIO_REG_BANK_SERDES_DIGITAL, |
| 4914 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, |
| 4915 | &control2); |
Yaniv Rosner | 7aa0711 | 2010-09-07 11:41:01 +0000 | [diff] [blame] | 4916 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) |
Yaniv Rosner | 18afb0a | 2009-11-05 19:18:04 +0200 | [diff] [blame] | 4917 | control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; |
| 4918 | else |
| 4919 | control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; |
Yaniv Rosner | 7aa0711 | 2010-09-07 11:41:01 +0000 | [diff] [blame] | 4920 | DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", |
| 4921 | phy->speed_cap_mask, control2); |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4922 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4923 | MDIO_REG_BANK_SERDES_DIGITAL, |
| 4924 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, |
| 4925 | control2); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4926 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 4927 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 4928 | (phy->speed_cap_mask & |
Yaniv Rosner | 18afb0a | 2009-11-05 19:18:04 +0200 | [diff] [blame] | 4929 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4930 | DP(NETIF_MSG_LINK, "XGXS\n"); |
| 4931 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4932 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4933 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
| 4934 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, |
| 4935 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4936 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4937 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4938 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
| 4939 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, |
| 4940 | &control2); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4941 | |
| 4942 | |
| 4943 | control2 |= |
| 4944 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; |
| 4945 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4946 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4947 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
| 4948 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, |
| 4949 | control2); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4950 | |
| 4951 | /* Disable parallel detection of HiG */ |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4952 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4953 | MDIO_REG_BANK_XGXS_BLOCK2, |
| 4954 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, |
| 4955 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | |
| 4956 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4957 | } |
| 4958 | } |
| 4959 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 4960 | static void bnx2x_set_autoneg(struct bnx2x_phy *phy, |
| 4961 | struct link_params *params, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4962 | struct link_vars *vars, |
| 4963 | u8 enable_cl73) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4964 | { |
| 4965 | struct bnx2x *bp = params->bp; |
| 4966 | u16 reg_val; |
| 4967 | |
| 4968 | /* CL37 Autoneg */ |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4969 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4970 | MDIO_REG_BANK_COMBO_IEEE0, |
| 4971 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4972 | |
| 4973 | /* CL37 Autoneg Enabled */ |
Yaniv Rosner | 8c99e7b | 2008-08-13 15:56:17 -0700 | [diff] [blame] | 4974 | if (vars->line_speed == SPEED_AUTO_NEG) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4975 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; |
| 4976 | else /* CL37 Autoneg Disabled */ |
| 4977 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
| 4978 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); |
| 4979 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4980 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4981 | MDIO_REG_BANK_COMBO_IEEE0, |
| 4982 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4983 | |
| 4984 | /* Enable/Disable Autodetection */ |
| 4985 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4986 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4987 | MDIO_REG_BANK_SERDES_DIGITAL, |
| 4988 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 4989 | reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | |
| 4990 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); |
| 4991 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; |
Yaniv Rosner | 8c99e7b | 2008-08-13 15:56:17 -0700 | [diff] [blame] | 4992 | if (vars->line_speed == SPEED_AUTO_NEG) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 4993 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; |
| 4994 | else |
| 4995 | reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; |
| 4996 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 4997 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 4998 | MDIO_REG_BANK_SERDES_DIGITAL, |
| 4999 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5000 | |
| 5001 | /* Enable TetonII and BAM autoneg */ |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5002 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5003 | MDIO_REG_BANK_BAM_NEXT_PAGE, |
| 5004 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5005 | ®_val); |
Yaniv Rosner | 8c99e7b | 2008-08-13 15:56:17 -0700 | [diff] [blame] | 5006 | if (vars->line_speed == SPEED_AUTO_NEG) { |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5007 | /* Enable BAM aneg Mode and TetonII aneg Mode */ |
| 5008 | reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | |
| 5009 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); |
| 5010 | } else { |
| 5011 | /* TetonII and BAM Autoneg Disabled */ |
| 5012 | reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | |
| 5013 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); |
| 5014 | } |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5015 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5016 | MDIO_REG_BANK_BAM_NEXT_PAGE, |
| 5017 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, |
| 5018 | reg_val); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5019 | |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5020 | if (enable_cl73) { |
| 5021 | /* Enable Cl73 FSM status bits */ |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5022 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5023 | MDIO_REG_BANK_CL73_USERB0, |
| 5024 | MDIO_CL73_USERB0_CL73_UCTRL, |
| 5025 | 0xe); |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5026 | |
| 5027 | /* Enable BAM Station Manager*/ |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5028 | CL22_WR_OVER_CL45(bp, phy, |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5029 | MDIO_REG_BANK_CL73_USERB0, |
| 5030 | MDIO_CL73_USERB0_CL73_BAM_CTRL1, |
| 5031 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | |
| 5032 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | |
| 5033 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); |
| 5034 | |
Yaniv Rosner | 7846e47 | 2009-11-05 19:18:07 +0200 | [diff] [blame] | 5035 | /* Advertise CL73 link speeds */ |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5036 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5037 | MDIO_REG_BANK_CL73_IEEEB1, |
| 5038 | MDIO_CL73_IEEEB1_AN_ADV2, |
| 5039 | ®_val); |
Yaniv Rosner | 7aa0711 | 2010-09-07 11:41:01 +0000 | [diff] [blame] | 5040 | if (phy->speed_cap_mask & |
Yaniv Rosner | 7846e47 | 2009-11-05 19:18:07 +0200 | [diff] [blame] | 5041 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
| 5042 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; |
Yaniv Rosner | 7aa0711 | 2010-09-07 11:41:01 +0000 | [diff] [blame] | 5043 | if (phy->speed_cap_mask & |
Yaniv Rosner | 7846e47 | 2009-11-05 19:18:07 +0200 | [diff] [blame] | 5044 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) |
| 5045 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5046 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5047 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5048 | MDIO_REG_BANK_CL73_IEEEB1, |
| 5049 | MDIO_CL73_IEEEB1_AN_ADV2, |
| 5050 | reg_val); |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5051 | |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5052 | /* CL73 Autoneg Enabled */ |
| 5053 | reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; |
| 5054 | |
| 5055 | } else /* CL73 Autoneg Disabled */ |
| 5056 | reg_val = 0; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5057 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5058 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5059 | MDIO_REG_BANK_CL73_IEEEB0, |
| 5060 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5061 | } |
| 5062 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5063 | /* Program SerDes, forced speed */ |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 5064 | static void bnx2x_program_serdes(struct bnx2x_phy *phy, |
| 5065 | struct link_params *params, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5066 | struct link_vars *vars) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5067 | { |
| 5068 | struct bnx2x *bp = params->bp; |
| 5069 | u16 reg_val; |
| 5070 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5071 | /* Program duplex, disable autoneg and sgmii*/ |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5072 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5073 | MDIO_REG_BANK_COMBO_IEEE0, |
| 5074 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5075 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | |
Eilon Greenstein | 5793720 | 2009-08-12 08:23:53 +0000 | [diff] [blame] | 5076 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
| 5077 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); |
Yaniv Rosner | 7aa0711 | 2010-09-07 11:41:01 +0000 | [diff] [blame] | 5078 | if (phy->req_duplex == DUPLEX_FULL) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5079 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5080 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5081 | MDIO_REG_BANK_COMBO_IEEE0, |
| 5082 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5083 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 5084 | /* Program speed |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 5085 | * - needed only if the speed is greater than 1G (2.5G or 10G) |
| 5086 | */ |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5087 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5088 | MDIO_REG_BANK_SERDES_DIGITAL, |
| 5089 | MDIO_SERDES_DIGITAL_MISC1, ®_val); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5090 | /* Clearing the speed value before setting the right speed */ |
Yaniv Rosner | 8c99e7b | 2008-08-13 15:56:17 -0700 | [diff] [blame] | 5091 | DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); |
| 5092 | |
| 5093 | reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | |
| 5094 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); |
| 5095 | |
| 5096 | if (!((vars->line_speed == SPEED_1000) || |
| 5097 | (vars->line_speed == SPEED_100) || |
| 5098 | (vars->line_speed == SPEED_10))) { |
| 5099 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5100 | reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | |
| 5101 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); |
Yaniv Rosner | 8c99e7b | 2008-08-13 15:56:17 -0700 | [diff] [blame] | 5102 | if (vars->line_speed == SPEED_10000) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5103 | reg_val |= |
| 5104 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; |
Yaniv Rosner | 8c99e7b | 2008-08-13 15:56:17 -0700 | [diff] [blame] | 5105 | } |
| 5106 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5107 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5108 | MDIO_REG_BANK_SERDES_DIGITAL, |
| 5109 | MDIO_SERDES_DIGITAL_MISC1, reg_val); |
Yaniv Rosner | 8c99e7b | 2008-08-13 15:56:17 -0700 | [diff] [blame] | 5110 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5111 | } |
| 5112 | |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 5113 | static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy, |
| 5114 | struct link_params *params) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5115 | { |
| 5116 | struct bnx2x *bp = params->bp; |
| 5117 | u16 val = 0; |
| 5118 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5119 | /* Set extended capabilities */ |
Yaniv Rosner | 7aa0711 | 2010-09-07 11:41:01 +0000 | [diff] [blame] | 5120 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5121 | val |= MDIO_OVER_1G_UP1_2_5G; |
Yaniv Rosner | 7aa0711 | 2010-09-07 11:41:01 +0000 | [diff] [blame] | 5122 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5123 | val |= MDIO_OVER_1G_UP1_10G; |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5124 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5125 | MDIO_REG_BANK_OVER_1G, |
| 5126 | MDIO_OVER_1G_UP1, val); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5127 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5128 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5129 | MDIO_REG_BANK_OVER_1G, |
| 5130 | MDIO_OVER_1G_UP3, 0x400); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5131 | } |
| 5132 | |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 5133 | static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy, |
| 5134 | struct link_params *params, |
| 5135 | u16 ieee_fc) |
Yaniv Rosner | 8c99e7b | 2008-08-13 15:56:17 -0700 | [diff] [blame] | 5136 | { |
| 5137 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 7846e47 | 2009-11-05 19:18:07 +0200 | [diff] [blame] | 5138 | u16 val; |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5139 | /* For AN, we are always publishing full duplex */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5140 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5141 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5142 | MDIO_REG_BANK_COMBO_IEEE0, |
| 5143 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5144 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5145 | MDIO_REG_BANK_CL73_IEEEB1, |
| 5146 | MDIO_CL73_IEEEB1_AN_ADV1, &val); |
Yaniv Rosner | 7846e47 | 2009-11-05 19:18:07 +0200 | [diff] [blame] | 5147 | val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; |
| 5148 | val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5149 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5150 | MDIO_REG_BANK_CL73_IEEEB1, |
| 5151 | MDIO_CL73_IEEEB1_AN_ADV1, val); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5152 | } |
| 5153 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 5154 | static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, |
| 5155 | struct link_params *params, |
| 5156 | u8 enable_cl73) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5157 | { |
| 5158 | struct bnx2x *bp = params->bp; |
Eilon Greenstein | 3a36f2e | 2009-02-12 08:37:09 +0000 | [diff] [blame] | 5159 | u16 mii_control; |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5160 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5161 | DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); |
Eilon Greenstein | 3a36f2e | 2009-02-12 08:37:09 +0000 | [diff] [blame] | 5162 | /* Enable and restart BAM/CL37 aneg */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5163 | |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5164 | if (enable_cl73) { |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5165 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5166 | MDIO_REG_BANK_CL73_IEEEB0, |
| 5167 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, |
| 5168 | &mii_control); |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5169 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5170 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5171 | MDIO_REG_BANK_CL73_IEEEB0, |
| 5172 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, |
| 5173 | (mii_control | |
| 5174 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | |
| 5175 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5176 | } else { |
| 5177 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5178 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5179 | MDIO_REG_BANK_COMBO_IEEE0, |
| 5180 | MDIO_COMBO_IEEE0_MII_CONTROL, |
| 5181 | &mii_control); |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5182 | DP(NETIF_MSG_LINK, |
| 5183 | "bnx2x_restart_autoneg mii_control before = 0x%x\n", |
| 5184 | mii_control); |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5185 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5186 | MDIO_REG_BANK_COMBO_IEEE0, |
| 5187 | MDIO_COMBO_IEEE0_MII_CONTROL, |
| 5188 | (mii_control | |
| 5189 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
| 5190 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5191 | } |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5192 | } |
| 5193 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 5194 | static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, |
| 5195 | struct link_params *params, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5196 | struct link_vars *vars) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5197 | { |
| 5198 | struct bnx2x *bp = params->bp; |
| 5199 | u16 control1; |
| 5200 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5201 | /* In SGMII mode, the unicore is always slave */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5202 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5203 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5204 | MDIO_REG_BANK_SERDES_DIGITAL, |
| 5205 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, |
| 5206 | &control1); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5207 | control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5208 | /* Set sgmii mode (and not fiber) */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5209 | control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | |
| 5210 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | |
| 5211 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5212 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5213 | MDIO_REG_BANK_SERDES_DIGITAL, |
| 5214 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, |
| 5215 | control1); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5216 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5217 | /* If forced speed */ |
Yaniv Rosner | 8c99e7b | 2008-08-13 15:56:17 -0700 | [diff] [blame] | 5218 | if (!(vars->line_speed == SPEED_AUTO_NEG)) { |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5219 | /* Set speed, disable autoneg */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5220 | u16 mii_control; |
| 5221 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5222 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5223 | MDIO_REG_BANK_COMBO_IEEE0, |
| 5224 | MDIO_COMBO_IEEE0_MII_CONTROL, |
| 5225 | &mii_control); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5226 | mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
| 5227 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| |
| 5228 | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); |
| 5229 | |
Yaniv Rosner | 8c99e7b | 2008-08-13 15:56:17 -0700 | [diff] [blame] | 5230 | switch (vars->line_speed) { |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5231 | case SPEED_100: |
| 5232 | mii_control |= |
| 5233 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; |
| 5234 | break; |
| 5235 | case SPEED_1000: |
| 5236 | mii_control |= |
| 5237 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; |
| 5238 | break; |
| 5239 | case SPEED_10: |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5240 | /* There is nothing to set for 10M */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5241 | break; |
| 5242 | default: |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5243 | /* Invalid speed for SGMII */ |
Yaniv Rosner | 8c99e7b | 2008-08-13 15:56:17 -0700 | [diff] [blame] | 5244 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", |
| 5245 | vars->line_speed); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5246 | break; |
| 5247 | } |
| 5248 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5249 | /* Setting the full duplex */ |
Yaniv Rosner | 7aa0711 | 2010-09-07 11:41:01 +0000 | [diff] [blame] | 5250 | if (phy->req_duplex == DUPLEX_FULL) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5251 | mii_control |= |
| 5252 | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5253 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5254 | MDIO_REG_BANK_COMBO_IEEE0, |
| 5255 | MDIO_COMBO_IEEE0_MII_CONTROL, |
| 5256 | mii_control); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5257 | |
| 5258 | } else { /* AN mode */ |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5259 | /* Enable and restart AN */ |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 5260 | bnx2x_restart_autoneg(phy, params, 0); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5261 | } |
| 5262 | } |
| 5263 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 5264 | /* Link management |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5265 | */ |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 5266 | static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, |
| 5267 | struct link_params *params) |
Yaniv Rosner | 15ddd2d | 2009-11-05 19:18:12 +0200 | [diff] [blame] | 5268 | { |
| 5269 | struct bnx2x *bp = params->bp; |
| 5270 | u16 pd_10g, status2_1000x; |
Yaniv Rosner | 7aa0711 | 2010-09-07 11:41:01 +0000 | [diff] [blame] | 5271 | if (phy->req_line_speed != SPEED_AUTO_NEG) |
| 5272 | return 0; |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5273 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5274 | MDIO_REG_BANK_SERDES_DIGITAL, |
| 5275 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, |
| 5276 | &status2_1000x); |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5277 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5278 | MDIO_REG_BANK_SERDES_DIGITAL, |
| 5279 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, |
| 5280 | &status2_1000x); |
Yaniv Rosner | 15ddd2d | 2009-11-05 19:18:12 +0200 | [diff] [blame] | 5281 | if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { |
| 5282 | DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", |
| 5283 | params->port); |
| 5284 | return 1; |
| 5285 | } |
| 5286 | |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5287 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5288 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
| 5289 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, |
| 5290 | &pd_10g); |
Yaniv Rosner | 15ddd2d | 2009-11-05 19:18:12 +0200 | [diff] [blame] | 5291 | |
| 5292 | if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { |
| 5293 | DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", |
| 5294 | params->port); |
| 5295 | return 1; |
| 5296 | } |
| 5297 | return 0; |
| 5298 | } |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5299 | |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 5300 | static void bnx2x_update_adv_fc(struct bnx2x_phy *phy, |
| 5301 | struct link_params *params, |
| 5302 | struct link_vars *vars, |
| 5303 | u32 gp_status) |
| 5304 | { |
| 5305 | u16 ld_pause; /* local driver */ |
| 5306 | u16 lp_pause; /* link partner */ |
| 5307 | u16 pause_result; |
| 5308 | struct bnx2x *bp = params->bp; |
| 5309 | if ((gp_status & |
| 5310 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | |
| 5311 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == |
| 5312 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | |
| 5313 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { |
| 5314 | |
| 5315 | CL22_RD_OVER_CL45(bp, phy, |
| 5316 | MDIO_REG_BANK_CL73_IEEEB1, |
| 5317 | MDIO_CL73_IEEEB1_AN_ADV1, |
| 5318 | &ld_pause); |
| 5319 | CL22_RD_OVER_CL45(bp, phy, |
| 5320 | MDIO_REG_BANK_CL73_IEEEB1, |
| 5321 | MDIO_CL73_IEEEB1_AN_LP_ADV1, |
| 5322 | &lp_pause); |
| 5323 | pause_result = (ld_pause & |
| 5324 | MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; |
| 5325 | pause_result |= (lp_pause & |
| 5326 | MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; |
| 5327 | DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result); |
| 5328 | } else { |
| 5329 | CL22_RD_OVER_CL45(bp, phy, |
| 5330 | MDIO_REG_BANK_COMBO_IEEE0, |
| 5331 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, |
| 5332 | &ld_pause); |
| 5333 | CL22_RD_OVER_CL45(bp, phy, |
| 5334 | MDIO_REG_BANK_COMBO_IEEE0, |
| 5335 | MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, |
| 5336 | &lp_pause); |
| 5337 | pause_result = (ld_pause & |
| 5338 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; |
| 5339 | pause_result |= (lp_pause & |
| 5340 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; |
| 5341 | DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result); |
| 5342 | } |
| 5343 | bnx2x_pause_resolve(vars, pause_result); |
| 5344 | |
| 5345 | } |
| 5346 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 5347 | static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, |
| 5348 | struct link_params *params, |
| 5349 | struct link_vars *vars, |
| 5350 | u32 gp_status) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5351 | { |
| 5352 | struct bnx2x *bp = params->bp; |
David S. Miller | c0700f9 | 2008-12-16 23:53:20 -0800 | [diff] [blame] | 5353 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5354 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5355 | /* Resolve from gp_status in case of AN complete and not sgmii */ |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 5356 | if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { |
| 5357 | /* Update the advertised flow-controled of LD/LP in AN */ |
| 5358 | if (phy->req_line_speed == SPEED_AUTO_NEG) |
| 5359 | bnx2x_update_adv_fc(phy, params, vars, gp_status); |
| 5360 | /* But set the flow-control result as the requested one */ |
Yaniv Rosner | 7aa0711 | 2010-09-07 11:41:01 +0000 | [diff] [blame] | 5361 | vars->flow_ctrl = phy->req_flow_ctrl; |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 5362 | } else if (phy->req_line_speed != SPEED_AUTO_NEG) |
Yaniv Rosner | 7aa0711 | 2010-09-07 11:41:01 +0000 | [diff] [blame] | 5363 | vars->flow_ctrl = params->req_fc_auto_adv; |
| 5364 | else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && |
| 5365 | (!(vars->phy_flags & PHY_SGMII_FLAG))) { |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 5366 | if (bnx2x_direct_parallel_detect_used(phy, params)) { |
Yaniv Rosner | 15ddd2d | 2009-11-05 19:18:12 +0200 | [diff] [blame] | 5367 | vars->flow_ctrl = params->req_fc_auto_adv; |
| 5368 | return; |
| 5369 | } |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 5370 | bnx2x_update_adv_fc(phy, params, vars, gp_status); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5371 | } |
| 5372 | DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); |
| 5373 | } |
| 5374 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 5375 | static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, |
| 5376 | struct link_params *params) |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5377 | { |
| 5378 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 5379 | u16 rx_status, ustat_val, cl37_fsm_received; |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5380 | DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); |
| 5381 | /* Step 1: Make sure signal is detected */ |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5382 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5383 | MDIO_REG_BANK_RX0, |
| 5384 | MDIO_RX0_RX_STATUS, |
| 5385 | &rx_status); |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5386 | if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != |
| 5387 | (MDIO_RX0_RX_STATUS_SIGDET)) { |
| 5388 | DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." |
| 5389 | "rx_status(0x80b0) = 0x%x\n", rx_status); |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5390 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5391 | MDIO_REG_BANK_CL73_IEEEB0, |
| 5392 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, |
| 5393 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5394 | return; |
| 5395 | } |
| 5396 | /* Step 2: Check CL73 state machine */ |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5397 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5398 | MDIO_REG_BANK_CL73_USERB0, |
| 5399 | MDIO_CL73_USERB0_CL73_USTAT1, |
| 5400 | &ustat_val); |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5401 | if ((ustat_val & |
| 5402 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | |
| 5403 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != |
| 5404 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | |
| 5405 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { |
| 5406 | DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " |
| 5407 | "ustat_val(0x8371) = 0x%x\n", ustat_val); |
| 5408 | return; |
| 5409 | } |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 5410 | /* Step 3: Check CL37 Message Pages received to indicate LP |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 5411 | * supports only CL37 |
| 5412 | */ |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5413 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5414 | MDIO_REG_BANK_REMOTE_PHY, |
| 5415 | MDIO_REMOTE_PHY_MISC_RX_STATUS, |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 5416 | &cl37_fsm_received); |
| 5417 | if ((cl37_fsm_received & |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5418 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | |
| 5419 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != |
| 5420 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | |
| 5421 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { |
| 5422 | DP(NETIF_MSG_LINK, "No CL37 FSM were received. " |
| 5423 | "misc_rx_status(0x8330) = 0x%x\n", |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 5424 | cl37_fsm_received); |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5425 | return; |
| 5426 | } |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 5427 | /* The combined cl37/cl73 fsm state information indicating that |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 5428 | * we are connected to a device which does not support cl73, but |
| 5429 | * does support cl37 BAM. In this case we disable cl73 and |
| 5430 | * restart cl37 auto-neg |
| 5431 | */ |
| 5432 | |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5433 | /* Disable CL73 */ |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5434 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5435 | MDIO_REG_BANK_CL73_IEEEB0, |
| 5436 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, |
| 5437 | 0); |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5438 | /* Restart CL37 autoneg */ |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 5439 | bnx2x_restart_autoneg(phy, params, 0); |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5440 | DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); |
| 5441 | } |
Yaniv Rosner | 7aa0711 | 2010-09-07 11:41:01 +0000 | [diff] [blame] | 5442 | |
| 5443 | static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, |
| 5444 | struct link_params *params, |
| 5445 | struct link_vars *vars, |
| 5446 | u32 gp_status) |
| 5447 | { |
| 5448 | if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) |
| 5449 | vars->link_status |= |
| 5450 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; |
| 5451 | |
| 5452 | if (bnx2x_direct_parallel_detect_used(phy, params)) |
| 5453 | vars->link_status |= |
| 5454 | LINK_STATUS_PARALLEL_DETECTION_USED; |
| 5455 | } |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5456 | static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy, |
| 5457 | struct link_params *params, |
| 5458 | struct link_vars *vars, |
| 5459 | u16 is_link_up, |
| 5460 | u16 speed_mask, |
| 5461 | u16 is_duplex) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5462 | { |
| 5463 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 7aa0711 | 2010-09-07 11:41:01 +0000 | [diff] [blame] | 5464 | if (phy->req_line_speed == SPEED_AUTO_NEG) |
| 5465 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5466 | if (is_link_up) { |
| 5467 | DP(NETIF_MSG_LINK, "phy link up\n"); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5468 | |
| 5469 | vars->phy_link_up = 1; |
| 5470 | vars->link_status |= LINK_STATUS_LINK_UP; |
| 5471 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5472 | switch (speed_mask) { |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5473 | case GP_STATUS_10M: |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5474 | vars->line_speed = SPEED_10; |
Yaniv Rosner | 430d172 | 2012-09-11 04:34:11 +0000 | [diff] [blame] | 5475 | if (is_duplex == DUPLEX_FULL) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5476 | vars->link_status |= LINK_10TFD; |
| 5477 | else |
| 5478 | vars->link_status |= LINK_10THD; |
| 5479 | break; |
| 5480 | |
| 5481 | case GP_STATUS_100M: |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5482 | vars->line_speed = SPEED_100; |
Yaniv Rosner | 430d172 | 2012-09-11 04:34:11 +0000 | [diff] [blame] | 5483 | if (is_duplex == DUPLEX_FULL) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5484 | vars->link_status |= LINK_100TXFD; |
| 5485 | else |
| 5486 | vars->link_status |= LINK_100TXHD; |
| 5487 | break; |
| 5488 | |
| 5489 | case GP_STATUS_1G: |
| 5490 | case GP_STATUS_1G_KX: |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5491 | vars->line_speed = SPEED_1000; |
Yaniv Rosner | 430d172 | 2012-09-11 04:34:11 +0000 | [diff] [blame] | 5492 | if (is_duplex == DUPLEX_FULL) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5493 | vars->link_status |= LINK_1000TFD; |
| 5494 | else |
| 5495 | vars->link_status |= LINK_1000THD; |
| 5496 | break; |
| 5497 | |
| 5498 | case GP_STATUS_2_5G: |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5499 | vars->line_speed = SPEED_2500; |
Yaniv Rosner | 430d172 | 2012-09-11 04:34:11 +0000 | [diff] [blame] | 5500 | if (is_duplex == DUPLEX_FULL) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5501 | vars->link_status |= LINK_2500TFD; |
| 5502 | else |
| 5503 | vars->link_status |= LINK_2500THD; |
| 5504 | break; |
| 5505 | |
| 5506 | case GP_STATUS_5G: |
| 5507 | case GP_STATUS_6G: |
| 5508 | DP(NETIF_MSG_LINK, |
| 5509 | "link speed unsupported gp_status 0x%x\n", |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5510 | speed_mask); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5511 | return -EINVAL; |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 5512 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5513 | case GP_STATUS_10G_KX4: |
| 5514 | case GP_STATUS_10G_HIG: |
| 5515 | case GP_STATUS_10G_CX4: |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5516 | case GP_STATUS_10G_KR: |
| 5517 | case GP_STATUS_10G_SFI: |
| 5518 | case GP_STATUS_10G_XFI: |
| 5519 | vars->line_speed = SPEED_10000; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5520 | vars->link_status |= LINK_10GTFD; |
| 5521 | break; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5522 | case GP_STATUS_20G_DXGXS: |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 5523 | case GP_STATUS_20G_KR2: |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5524 | vars->line_speed = SPEED_20000; |
| 5525 | vars->link_status |= LINK_20GTFD; |
| 5526 | break; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5527 | default: |
| 5528 | DP(NETIF_MSG_LINK, |
| 5529 | "link speed unsupported gp_status 0x%x\n", |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5530 | speed_mask); |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 5531 | return -EINVAL; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5532 | } |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5533 | } else { /* link_down */ |
| 5534 | DP(NETIF_MSG_LINK, "phy link down\n"); |
| 5535 | |
| 5536 | vars->phy_link_up = 0; |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 5537 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5538 | vars->duplex = DUPLEX_FULL; |
David S. Miller | c0700f9 | 2008-12-16 23:53:20 -0800 | [diff] [blame] | 5539 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5540 | vars->mac_type = MAC_TYPE_NONE; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5541 | } |
| 5542 | DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n", |
| 5543 | vars->phy_link_up, vars->line_speed); |
| 5544 | return 0; |
| 5545 | } |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5546 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5547 | static int bnx2x_link_settings_status(struct bnx2x_phy *phy, |
| 5548 | struct link_params *params, |
| 5549 | struct link_vars *vars) |
| 5550 | { |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5551 | struct bnx2x *bp = params->bp; |
| 5552 | |
| 5553 | u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; |
| 5554 | int rc = 0; |
| 5555 | |
| 5556 | /* Read gp_status */ |
| 5557 | CL22_RD_OVER_CL45(bp, phy, |
| 5558 | MDIO_REG_BANK_GP_STATUS, |
| 5559 | MDIO_GP_STATUS_TOP_AN_STATUS1, |
| 5560 | &gp_status); |
| 5561 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) |
| 5562 | duplex = DUPLEX_FULL; |
| 5563 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) |
| 5564 | link_up = 1; |
| 5565 | speed_mask = gp_status & GP_STATUS_SPEED_MASK; |
| 5566 | DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", |
| 5567 | gp_status, link_up, speed_mask); |
| 5568 | rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, |
| 5569 | duplex); |
| 5570 | if (rc == -EINVAL) |
| 5571 | return rc; |
| 5572 | |
| 5573 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { |
| 5574 | if (SINGLE_MEDIA_DIRECT(params)) { |
Yaniv Rosner | 430d172 | 2012-09-11 04:34:11 +0000 | [diff] [blame] | 5575 | vars->duplex = duplex; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5576 | bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); |
| 5577 | if (phy->req_line_speed == SPEED_AUTO_NEG) |
| 5578 | bnx2x_xgxs_an_resolve(phy, params, vars, |
| 5579 | gp_status); |
| 5580 | } |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5581 | } else { /* Link_down */ |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 5582 | if ((phy->req_line_speed == SPEED_AUTO_NEG) && |
| 5583 | SINGLE_MEDIA_DIRECT(params)) { |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5584 | /* Check signal is detected */ |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 5585 | bnx2x_check_fallback_to_cl37(phy, params); |
Eilon Greenstein | 239d686 | 2009-08-12 08:23:04 +0000 | [diff] [blame] | 5586 | } |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5587 | } |
| 5588 | |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 5589 | /* Read LP advertised speeds*/ |
| 5590 | if (SINGLE_MEDIA_DIRECT(params) && |
| 5591 | (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { |
| 5592 | u16 val; |
| 5593 | |
| 5594 | CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, |
| 5595 | MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); |
| 5596 | |
| 5597 | if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) |
| 5598 | vars->link_status |= |
| 5599 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; |
| 5600 | if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | |
| 5601 | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) |
| 5602 | vars->link_status |= |
| 5603 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; |
| 5604 | |
| 5605 | CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, |
| 5606 | MDIO_OVER_1G_LP_UP1, &val); |
| 5607 | |
| 5608 | if (val & MDIO_OVER_1G_UP1_2_5G) |
| 5609 | vars->link_status |= |
| 5610 | LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; |
| 5611 | if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) |
| 5612 | vars->link_status |= |
| 5613 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; |
| 5614 | } |
| 5615 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 5616 | DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", |
| 5617 | vars->duplex, vars->flow_ctrl, vars->link_status); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5618 | return rc; |
| 5619 | } |
| 5620 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5621 | static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, |
| 5622 | struct link_params *params, |
| 5623 | struct link_vars *vars) |
| 5624 | { |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5625 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5626 | u8 lane; |
| 5627 | u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; |
| 5628 | int rc = 0; |
| 5629 | lane = bnx2x_get_warpcore_lane(phy, params); |
| 5630 | /* Read gp_status */ |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 5631 | if ((params->loopback_mode) && |
| 5632 | (phy->flags & FLAGS_WC_DUAL_MODE)) { |
| 5633 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 5634 | MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); |
| 5635 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 5636 | MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); |
| 5637 | link_up &= 0x1; |
| 5638 | } else if ((phy->req_line_speed > SPEED_10000) && |
| 5639 | (phy->supported & SUPPORTED_20000baseMLD2_Full)) { |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5640 | u16 temp_link_up; |
| 5641 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 5642 | 1, &temp_link_up); |
| 5643 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 5644 | 1, &link_up); |
| 5645 | DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n", |
| 5646 | temp_link_up, link_up); |
| 5647 | link_up &= (1<<2); |
| 5648 | if (link_up) |
| 5649 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
| 5650 | } else { |
| 5651 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 5652 | MDIO_WC_REG_GP2_STATUS_GP_2_1, |
| 5653 | &gp_status1); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5654 | DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1); |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 5655 | /* Check for either KR, 1G, or AN up. */ |
| 5656 | link_up = ((gp_status1 >> 8) | |
| 5657 | (gp_status1 >> 12) | |
| 5658 | (gp_status1)) & |
| 5659 | (1 << lane); |
| 5660 | if (phy->supported & SUPPORTED_20000baseKR2_Full) { |
| 5661 | u16 an_link; |
| 5662 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, |
| 5663 | MDIO_AN_REG_STATUS, &an_link); |
| 5664 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, |
| 5665 | MDIO_AN_REG_STATUS, &an_link); |
| 5666 | link_up |= (an_link & (1<<2)); |
| 5667 | } |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5668 | if (link_up && SINGLE_MEDIA_DIRECT(params)) { |
| 5669 | u16 pd, gp_status4; |
| 5670 | if (phy->req_line_speed == SPEED_AUTO_NEG) { |
| 5671 | /* Check Autoneg complete */ |
| 5672 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 5673 | MDIO_WC_REG_GP2_STATUS_GP_2_4, |
| 5674 | &gp_status4); |
| 5675 | if (gp_status4 & ((1<<12)<<lane)) |
| 5676 | vars->link_status |= |
| 5677 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; |
| 5678 | |
| 5679 | /* Check parallel detect used */ |
| 5680 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 5681 | MDIO_WC_REG_PAR_DET_10G_STATUS, |
| 5682 | &pd); |
| 5683 | if (pd & (1<<15)) |
| 5684 | vars->link_status |= |
| 5685 | LINK_STATUS_PARALLEL_DETECTION_USED; |
| 5686 | } |
| 5687 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
Yaniv Rosner | 430d172 | 2012-09-11 04:34:11 +0000 | [diff] [blame] | 5688 | vars->duplex = duplex; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5689 | } |
| 5690 | } |
| 5691 | |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 5692 | if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && |
| 5693 | SINGLE_MEDIA_DIRECT(params)) { |
| 5694 | u16 val; |
| 5695 | |
| 5696 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, |
| 5697 | MDIO_AN_REG_LP_AUTO_NEG2, &val); |
| 5698 | |
| 5699 | if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) |
| 5700 | vars->link_status |= |
| 5701 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; |
| 5702 | if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | |
| 5703 | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) |
| 5704 | vars->link_status |= |
| 5705 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; |
| 5706 | |
| 5707 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 5708 | MDIO_WC_REG_DIGITAL3_LP_UP1, &val); |
| 5709 | |
| 5710 | if (val & MDIO_OVER_1G_UP1_2_5G) |
| 5711 | vars->link_status |= |
| 5712 | LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; |
| 5713 | if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) |
| 5714 | vars->link_status |= |
| 5715 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; |
| 5716 | |
| 5717 | } |
| 5718 | |
| 5719 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5720 | if (lane < 2) { |
| 5721 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 5722 | MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); |
| 5723 | } else { |
| 5724 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 5725 | MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); |
| 5726 | } |
| 5727 | DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed); |
| 5728 | |
| 5729 | if ((lane & 1) == 0) |
| 5730 | gp_speed <<= 8; |
| 5731 | gp_speed &= 0x3f00; |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 5732 | link_up = !!link_up; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5733 | |
| 5734 | rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, |
| 5735 | duplex); |
| 5736 | |
| 5737 | DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", |
| 5738 | vars->duplex, vars->flow_ctrl, vars->link_status); |
| 5739 | return rc; |
| 5740 | } |
Eilon Greenstein | ed8680a | 2009-02-12 08:37:12 +0000 | [diff] [blame] | 5741 | static void bnx2x_set_gmii_tx_driver(struct link_params *params) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5742 | { |
| 5743 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 5744 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5745 | u16 lp_up2; |
| 5746 | u16 tx_driver; |
Eilon Greenstein | c2c8b03 | 2009-02-12 08:37:14 +0000 | [diff] [blame] | 5747 | u16 bank; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5748 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5749 | /* Read precomp */ |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5750 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5751 | MDIO_REG_BANK_OVER_1G, |
| 5752 | MDIO_OVER_1G_LP_UP2, &lp_up2); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5753 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5754 | /* Bits [10:7] at lp_up2, positioned at [15:12] */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5755 | lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> |
| 5756 | MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << |
| 5757 | MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); |
| 5758 | |
Eilon Greenstein | c2c8b03 | 2009-02-12 08:37:14 +0000 | [diff] [blame] | 5759 | if (lp_up2 == 0) |
| 5760 | return; |
| 5761 | |
| 5762 | for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; |
| 5763 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5764 | CL22_RD_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5765 | bank, |
| 5766 | MDIO_TX0_TX_DRIVER, &tx_driver); |
Eilon Greenstein | c2c8b03 | 2009-02-12 08:37:14 +0000 | [diff] [blame] | 5767 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5768 | /* Replace tx_driver bits [15:12] */ |
Eilon Greenstein | c2c8b03 | 2009-02-12 08:37:14 +0000 | [diff] [blame] | 5769 | if (lp_up2 != |
| 5770 | (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { |
| 5771 | tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; |
| 5772 | tx_driver |= lp_up2; |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5773 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5774 | bank, |
| 5775 | MDIO_TX0_TX_DRIVER, tx_driver); |
Eilon Greenstein | c2c8b03 | 2009-02-12 08:37:14 +0000 | [diff] [blame] | 5776 | } |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5777 | } |
| 5778 | } |
| 5779 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 5780 | static int bnx2x_emac_program(struct link_params *params, |
| 5781 | struct link_vars *vars) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5782 | { |
| 5783 | struct bnx2x *bp = params->bp; |
| 5784 | u8 port = params->port; |
| 5785 | u16 mode = 0; |
| 5786 | |
| 5787 | DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); |
| 5788 | bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5789 | EMAC_REG_EMAC_MODE, |
| 5790 | (EMAC_MODE_25G_MODE | |
| 5791 | EMAC_MODE_PORT_MII_10M | |
| 5792 | EMAC_MODE_HALF_DUPLEX)); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 5793 | switch (vars->line_speed) { |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5794 | case SPEED_10: |
| 5795 | mode |= EMAC_MODE_PORT_MII_10M; |
| 5796 | break; |
| 5797 | |
| 5798 | case SPEED_100: |
| 5799 | mode |= EMAC_MODE_PORT_MII; |
| 5800 | break; |
| 5801 | |
| 5802 | case SPEED_1000: |
| 5803 | mode |= EMAC_MODE_PORT_GMII; |
| 5804 | break; |
| 5805 | |
| 5806 | case SPEED_2500: |
| 5807 | mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); |
| 5808 | break; |
| 5809 | |
| 5810 | default: |
| 5811 | /* 10G not valid for EMAC */ |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 5812 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", |
| 5813 | vars->line_speed); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5814 | return -EINVAL; |
| 5815 | } |
| 5816 | |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 5817 | if (vars->duplex == DUPLEX_HALF) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5818 | mode |= EMAC_MODE_HALF_DUPLEX; |
| 5819 | bnx2x_bits_en(bp, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5820 | GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, |
| 5821 | mode); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5822 | |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 5823 | bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5824 | return 0; |
| 5825 | } |
| 5826 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 5827 | static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, |
| 5828 | struct link_params *params) |
| 5829 | { |
| 5830 | |
| 5831 | u16 bank, i = 0; |
| 5832 | struct bnx2x *bp = params->bp; |
| 5833 | |
| 5834 | for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; |
| 5835 | bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5836 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 5837 | bank, |
| 5838 | MDIO_RX0_RX_EQ_BOOST, |
| 5839 | phy->rx_preemphasis[i]); |
| 5840 | } |
| 5841 | |
| 5842 | for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; |
| 5843 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { |
Yaniv Rosner | cd2be89 | 2011-01-31 04:21:45 +0000 | [diff] [blame] | 5844 | CL22_WR_OVER_CL45(bp, phy, |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 5845 | bank, |
| 5846 | MDIO_TX0_TX_DRIVER, |
| 5847 | phy->tx_preemphasis[i]); |
| 5848 | } |
| 5849 | } |
| 5850 | |
Yaniv Rosner | ec146a6 | 2011-05-31 21:29:27 +0000 | [diff] [blame] | 5851 | static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy, |
| 5852 | struct link_params *params, |
| 5853 | struct link_vars *vars) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 5854 | { |
| 5855 | struct bnx2x *bp = params->bp; |
| 5856 | u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) || |
| 5857 | (params->loopback_mode == LOOPBACK_XGXS)); |
| 5858 | if (!(vars->phy_flags & PHY_SGMII_FLAG)) { |
| 5859 | if (SINGLE_MEDIA_DIRECT(params) && |
| 5860 | (params->feature_config_flags & |
| 5861 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) |
| 5862 | bnx2x_set_preemphasis(phy, params); |
| 5863 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5864 | /* Forced speed requested? */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 5865 | if (vars->line_speed != SPEED_AUTO_NEG || |
| 5866 | (SINGLE_MEDIA_DIRECT(params) && |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 5867 | params->loopback_mode == LOOPBACK_EXT)) { |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 5868 | DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); |
| 5869 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5870 | /* Disable autoneg */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 5871 | bnx2x_set_autoneg(phy, params, vars, 0); |
| 5872 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5873 | /* Program speed and duplex */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 5874 | bnx2x_program_serdes(phy, params, vars); |
| 5875 | |
| 5876 | } else { /* AN_mode */ |
| 5877 | DP(NETIF_MSG_LINK, "not SGMII, AN\n"); |
| 5878 | |
| 5879 | /* AN enabled */ |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 5880 | bnx2x_set_brcm_cl37_advertisement(phy, params); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 5881 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5882 | /* Program duplex & pause advertisement (for aneg) */ |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 5883 | bnx2x_set_ieee_aneg_advertisement(phy, params, |
| 5884 | vars->ieee_fc); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 5885 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5886 | /* Enable autoneg */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 5887 | bnx2x_set_autoneg(phy, params, vars, enable_cl73); |
| 5888 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5889 | /* Enable and restart AN */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 5890 | bnx2x_restart_autoneg(phy, params, enable_cl73); |
| 5891 | } |
| 5892 | |
| 5893 | } else { /* SGMII mode */ |
| 5894 | DP(NETIF_MSG_LINK, "SGMII\n"); |
| 5895 | |
| 5896 | bnx2x_initialize_sgmii_process(phy, params, vars); |
| 5897 | } |
| 5898 | } |
| 5899 | |
Yaniv Rosner | ec146a6 | 2011-05-31 21:29:27 +0000 | [diff] [blame] | 5900 | static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy, |
| 5901 | struct link_params *params, |
| 5902 | struct link_vars *vars) |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 5903 | { |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 5904 | int rc; |
Yaniv Rosner | ec146a6 | 2011-05-31 21:29:27 +0000 | [diff] [blame] | 5905 | vars->phy_flags |= PHY_XGXS_FLAG; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 5906 | if ((phy->req_line_speed && |
| 5907 | ((phy->req_line_speed == SPEED_100) || |
| 5908 | (phy->req_line_speed == SPEED_10))) || |
| 5909 | (!phy->req_line_speed && |
| 5910 | (phy->speed_cap_mask >= |
| 5911 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && |
| 5912 | (phy->speed_cap_mask < |
Yaniv Rosner | ec146a6 | 2011-05-31 21:29:27 +0000 | [diff] [blame] | 5913 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || |
| 5914 | (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 5915 | vars->phy_flags |= PHY_SGMII_FLAG; |
| 5916 | else |
| 5917 | vars->phy_flags &= ~PHY_SGMII_FLAG; |
| 5918 | |
| 5919 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); |
Yaniv Rosner | ec146a6 | 2011-05-31 21:29:27 +0000 | [diff] [blame] | 5920 | bnx2x_set_aer_mmd(params, phy); |
| 5921 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
| 5922 | bnx2x_set_master_ln(params, phy); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 5923 | |
| 5924 | rc = bnx2x_reset_unicore(params, phy, 0); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5925 | /* Reset the SerDes and wait for reset bit return low */ |
| 5926 | if (rc) |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 5927 | return rc; |
| 5928 | |
Yaniv Rosner | ec146a6 | 2011-05-31 21:29:27 +0000 | [diff] [blame] | 5929 | bnx2x_set_aer_mmd(params, phy); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5930 | /* Setting the masterLn_def again after the reset */ |
Yaniv Rosner | ec146a6 | 2011-05-31 21:29:27 +0000 | [diff] [blame] | 5931 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { |
| 5932 | bnx2x_set_master_ln(params, phy); |
| 5933 | bnx2x_set_swap_lanes(params, phy); |
| 5934 | } |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 5935 | |
| 5936 | return rc; |
| 5937 | } |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 5938 | |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 5939 | static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, |
Yaniv Rosner | 6d870c3 | 2011-01-31 04:22:20 +0000 | [diff] [blame] | 5940 | struct bnx2x_phy *phy, |
| 5941 | struct link_params *params) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5942 | { |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 5943 | u16 cnt, ctrl; |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 5944 | /* Wait for soft reset to get cleared up to 1 sec */ |
Yaniv Rosner | 62b29a5 | 2010-09-07 11:40:58 +0000 | [diff] [blame] | 5945 | for (cnt = 0; cnt < 1000; cnt++) { |
Yaniv Rosner | 52c4d6c | 2011-07-05 01:06:34 +0000 | [diff] [blame] | 5946 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 5947 | bnx2x_cl22_read(bp, phy, |
| 5948 | MDIO_PMA_REG_CTRL, &ctrl); |
| 5949 | else |
| 5950 | bnx2x_cl45_read(bp, phy, |
| 5951 | MDIO_PMA_DEVAD, |
| 5952 | MDIO_PMA_REG_CTRL, &ctrl); |
Yaniv Rosner | 62b29a5 | 2010-09-07 11:40:58 +0000 | [diff] [blame] | 5953 | if (!(ctrl & (1<<15))) |
| 5954 | break; |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 5955 | usleep_range(1000, 2000); |
Yaniv Rosner | 62b29a5 | 2010-09-07 11:40:58 +0000 | [diff] [blame] | 5956 | } |
Yaniv Rosner | 6d870c3 | 2011-01-31 04:22:20 +0000 | [diff] [blame] | 5957 | |
| 5958 | if (cnt == 1000) |
| 5959 | netdev_err(bp->dev, "Warning: PHY was not initialized," |
| 5960 | " Port %d\n", |
| 5961 | params->port); |
Yaniv Rosner | 62b29a5 | 2010-09-07 11:40:58 +0000 | [diff] [blame] | 5962 | DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); |
| 5963 | return cnt; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 5964 | } |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5965 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5966 | static void bnx2x_link_int_enable(struct link_params *params) |
| 5967 | { |
| 5968 | u8 port = params->port; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5969 | u32 mask; |
| 5970 | struct bnx2x *bp = params->bp; |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 5971 | |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 5972 | /* Setting the status to report on link up for either XGXS or SerDes */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 5973 | if (CHIP_IS_E3(bp)) { |
| 5974 | mask = NIG_MASK_XGXS0_LINK_STATUS; |
| 5975 | if (!(SINGLE_MEDIA_DIRECT(params))) |
| 5976 | mask |= NIG_MASK_MI_INT; |
| 5977 | } else if (params->switch_cfg == SWITCH_CFG_10G) { |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5978 | mask = (NIG_MASK_XGXS0_LINK10G | |
| 5979 | NIG_MASK_XGXS0_LINK_STATUS); |
| 5980 | DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 5981 | if (!(SINGLE_MEDIA_DIRECT(params)) && |
| 5982 | params->phy[INT_PHY].type != |
| 5983 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5984 | mask |= NIG_MASK_MI_INT; |
| 5985 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); |
| 5986 | } |
| 5987 | |
| 5988 | } else { /* SerDes */ |
| 5989 | mask = NIG_MASK_SERDES0_LINK_STATUS; |
| 5990 | DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 5991 | if (!(SINGLE_MEDIA_DIRECT(params)) && |
| 5992 | params->phy[INT_PHY].type != |
| 5993 | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 5994 | mask |= NIG_MASK_MI_INT; |
| 5995 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); |
| 5996 | } |
| 5997 | } |
| 5998 | bnx2x_bits_en(bp, |
| 5999 | NIG_REG_MASK_INTERRUPT_PORT0 + port*4, |
| 6000 | mask); |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 6001 | |
| 6002 | DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6003 | (params->switch_cfg == SWITCH_CFG_10G), |
| 6004 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6005 | DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", |
| 6006 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), |
| 6007 | REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), |
| 6008 | REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); |
| 6009 | DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", |
| 6010 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), |
| 6011 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); |
| 6012 | } |
| 6013 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6014 | static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, |
| 6015 | u8 exp_mi_int) |
Eilon Greenstein | 2f90446 | 2009-08-12 08:22:16 +0000 | [diff] [blame] | 6016 | { |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6017 | u32 latch_status = 0; |
| 6018 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6019 | /* Disable the MI INT ( external phy int ) by writing 1 to the |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6020 | * status register. Link down indication is high-active-signal, |
| 6021 | * so in this case we need to write the status to clear the XOR |
Eilon Greenstein | 2f90446 | 2009-08-12 08:22:16 +0000 | [diff] [blame] | 6022 | */ |
| 6023 | /* Read Latched signals */ |
| 6024 | latch_status = REG_RD(bp, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6025 | NIG_REG_LATCH_STATUS_0 + port*8); |
| 6026 | DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); |
Eilon Greenstein | 2f90446 | 2009-08-12 08:22:16 +0000 | [diff] [blame] | 6027 | /* Handle only those with latched-signal=up.*/ |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6028 | if (exp_mi_int) |
| 6029 | bnx2x_bits_en(bp, |
| 6030 | NIG_REG_STATUS_INTERRUPT_PORT0 |
| 6031 | + port*4, |
| 6032 | NIG_STATUS_EMAC0_MI_INT); |
| 6033 | else |
| 6034 | bnx2x_bits_dis(bp, |
| 6035 | NIG_REG_STATUS_INTERRUPT_PORT0 |
| 6036 | + port*4, |
| 6037 | NIG_STATUS_EMAC0_MI_INT); |
| 6038 | |
Eilon Greenstein | 2f90446 | 2009-08-12 08:22:16 +0000 | [diff] [blame] | 6039 | if (latch_status & 1) { |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6040 | |
Eilon Greenstein | 2f90446 | 2009-08-12 08:22:16 +0000 | [diff] [blame] | 6041 | /* For all latched-signal=up : Re-Arm Latch signals */ |
| 6042 | REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6043 | (latch_status & 0xfffe) | (latch_status & 1)); |
Eilon Greenstein | 2f90446 | 2009-08-12 08:22:16 +0000 | [diff] [blame] | 6044 | } |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6045 | /* For all latched-signal=up,Write original_signal to status */ |
Eilon Greenstein | 2f90446 | 2009-08-12 08:22:16 +0000 | [diff] [blame] | 6046 | } |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 6047 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6048 | static void bnx2x_link_int_ack(struct link_params *params, |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6049 | struct link_vars *vars, u8 is_10g_plus) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6050 | { |
| 6051 | struct bnx2x *bp = params->bp; |
| 6052 | u8 port = params->port; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6053 | u32 mask; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6054 | /* First reset all status we assume only one line will be |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 6055 | * change at a time |
| 6056 | */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6057 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6058 | (NIG_STATUS_XGXS0_LINK10G | |
| 6059 | NIG_STATUS_XGXS0_LINK_STATUS | |
| 6060 | NIG_STATUS_SERDES0_LINK_STATUS)); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6061 | if (vars->phy_link_up) { |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6062 | if (USES_WARPCORE(bp)) |
| 6063 | mask = NIG_STATUS_XGXS0_LINK_STATUS; |
| 6064 | else { |
| 6065 | if (is_10g_plus) |
| 6066 | mask = NIG_STATUS_XGXS0_LINK10G; |
| 6067 | else if (params->switch_cfg == SWITCH_CFG_10G) { |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6068 | /* Disable the link interrupt by writing 1 to |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6069 | * the relevant lane in the status register |
| 6070 | */ |
| 6071 | u32 ser_lane = |
| 6072 | ((params->lane_config & |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6073 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
| 6074 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6075 | mask = ((1 << ser_lane) << |
| 6076 | NIG_STATUS_XGXS0_LINK_STATUS_SIZE); |
| 6077 | } else |
| 6078 | mask = NIG_STATUS_SERDES0_LINK_STATUS; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6079 | } |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6080 | DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n", |
| 6081 | mask); |
| 6082 | bnx2x_bits_en(bp, |
| 6083 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, |
| 6084 | mask); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6085 | } |
| 6086 | } |
| 6087 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 6088 | static int bnx2x_format_ver(u32 num, u8 *str, u16 *len) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6089 | { |
| 6090 | u8 *str_ptr = str; |
| 6091 | u32 mask = 0xf0000000; |
| 6092 | u8 shift = 8*4; |
| 6093 | u8 digit; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6094 | u8 remove_leading_zeros = 1; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6095 | if (*len < 10) { |
Frederik Schwarzer | 025dfda | 2008-10-16 19:02:37 +0200 | [diff] [blame] | 6096 | /* Need more than 10chars for this format */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6097 | *str_ptr = '\0'; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6098 | (*len)--; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6099 | return -EINVAL; |
| 6100 | } |
| 6101 | while (shift > 0) { |
| 6102 | |
| 6103 | shift -= 4; |
| 6104 | digit = ((num & mask) >> shift); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6105 | if (digit == 0 && remove_leading_zeros) { |
| 6106 | mask = mask >> 4; |
| 6107 | continue; |
| 6108 | } else if (digit < 0xa) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6109 | *str_ptr = digit + '0'; |
| 6110 | else |
| 6111 | *str_ptr = digit - 0xa + 'a'; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6112 | remove_leading_zeros = 0; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6113 | str_ptr++; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6114 | (*len)--; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6115 | mask = mask >> 4; |
| 6116 | if (shift == 4*4) { |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6117 | *str_ptr = '.'; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6118 | str_ptr++; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6119 | (*len)--; |
| 6120 | remove_leading_zeros = 1; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6121 | } |
| 6122 | } |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6123 | return 0; |
| 6124 | } |
| 6125 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6126 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 6127 | static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6128 | { |
| 6129 | str[0] = '\0'; |
| 6130 | (*len)--; |
| 6131 | return 0; |
| 6132 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 6133 | |
Mintz Yuval | a1e785e | 2012-02-15 02:10:32 +0000 | [diff] [blame] | 6134 | int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version, |
| 6135 | u16 len) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6136 | { |
Julia Lawall | 0376d5b | 2009-07-19 05:26:35 +0000 | [diff] [blame] | 6137 | struct bnx2x *bp; |
Eilon Greenstein | a35da8d | 2009-02-12 08:37:02 +0000 | [diff] [blame] | 6138 | u32 spirom_ver = 0; |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 6139 | int status = 0; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6140 | u8 *ver_p = version; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6141 | u16 remain_len = len; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6142 | if (version == NULL || params == NULL) |
| 6143 | return -EINVAL; |
Julia Lawall | 0376d5b | 2009-07-19 05:26:35 +0000 | [diff] [blame] | 6144 | bp = params->bp; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6145 | |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6146 | /* Extract first external phy*/ |
| 6147 | version[0] = '\0'; |
| 6148 | spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); |
Eilon Greenstein | a35da8d | 2009-02-12 08:37:02 +0000 | [diff] [blame] | 6149 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6150 | if (params->phy[EXT_PHY1].format_fw_ver) { |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6151 | status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, |
| 6152 | ver_p, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6153 | &remain_len); |
| 6154 | ver_p += (len - remain_len); |
| 6155 | } |
| 6156 | if ((params->num_phys == MAX_PHYS) && |
| 6157 | (params->phy[EXT_PHY2].ver_addr != 0)) { |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6158 | spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6159 | if (params->phy[EXT_PHY2].format_fw_ver) { |
| 6160 | *ver_p = '/'; |
| 6161 | ver_p++; |
| 6162 | remain_len--; |
| 6163 | status |= params->phy[EXT_PHY2].format_fw_ver( |
| 6164 | spirom_ver, |
| 6165 | ver_p, |
| 6166 | &remain_len); |
| 6167 | ver_p = version + (len - remain_len); |
| 6168 | } |
| 6169 | } |
| 6170 | *ver_p = '\0'; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6171 | return status; |
| 6172 | } |
| 6173 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 6174 | static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, |
Yaniv Rosner | 62b29a5 | 2010-09-07 11:40:58 +0000 | [diff] [blame] | 6175 | struct link_params *params) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6176 | { |
| 6177 | u8 port = params->port; |
| 6178 | struct bnx2x *bp = params->bp; |
| 6179 | |
Yaniv Rosner | 62b29a5 | 2010-09-07 11:40:58 +0000 | [diff] [blame] | 6180 | if (phy->req_line_speed != SPEED_1000) { |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6181 | u32 md_devad = 0; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6182 | |
| 6183 | DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); |
| 6184 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6185 | if (!CHIP_IS_E3(bp)) { |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 6186 | /* Change the uni_phy_addr in the nig */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6187 | md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + |
| 6188 | port*0x18)); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6189 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6190 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, |
| 6191 | 0x5); |
| 6192 | } |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6193 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 6194 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6195 | 5, |
| 6196 | (MDIO_REG_BANK_AER_BLOCK + |
| 6197 | (MDIO_AER_BLOCK_AER_REG & 0xf)), |
| 6198 | 0x2800); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6199 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 6200 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6201 | 5, |
| 6202 | (MDIO_REG_BANK_CL73_IEEEB0 + |
| 6203 | (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), |
| 6204 | 0x6041); |
Eilon Greenstein | 3858276 | 2009-01-14 06:44:16 +0000 | [diff] [blame] | 6205 | msleep(200); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 6206 | /* Set aer mmd back */ |
Yaniv Rosner | ec146a6 | 2011-05-31 21:29:27 +0000 | [diff] [blame] | 6207 | bnx2x_set_aer_mmd(params, phy); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6208 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6209 | if (!CHIP_IS_E3(bp)) { |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 6210 | /* And md_devad */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6211 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, |
| 6212 | md_devad); |
| 6213 | } |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6214 | } else { |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 6215 | u16 mii_ctrl; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6216 | DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 6217 | bnx2x_cl45_read(bp, phy, 5, |
| 6218 | (MDIO_REG_BANK_COMBO_IEEE0 + |
| 6219 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), |
| 6220 | &mii_ctrl); |
| 6221 | bnx2x_cl45_write(bp, phy, 5, |
| 6222 | (MDIO_REG_BANK_COMBO_IEEE0 + |
| 6223 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), |
| 6224 | mii_ctrl | |
| 6225 | MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6226 | } |
| 6227 | } |
| 6228 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 6229 | int bnx2x_set_led(struct link_params *params, |
| 6230 | struct link_vars *vars, u8 mode, u32 speed) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6231 | { |
Yaniv Rosner | 7846e47 | 2009-11-05 19:18:07 +0200 | [diff] [blame] | 6232 | u8 port = params->port; |
| 6233 | u16 hw_led_mode = params->hw_led_mode; |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 6234 | int rc = 0; |
| 6235 | u8 phy_idx; |
Eilon Greenstein | 345b5d5 | 2008-08-13 15:58:12 -0700 | [diff] [blame] | 6236 | u32 tmp; |
| 6237 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
Yaniv Rosner | 7846e47 | 2009-11-05 19:18:07 +0200 | [diff] [blame] | 6238 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6239 | DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); |
| 6240 | DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", |
| 6241 | speed, hw_led_mode); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 6242 | /* In case */ |
| 6243 | for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) { |
| 6244 | if (params->phy[phy_idx].set_link_led) { |
| 6245 | params->phy[phy_idx].set_link_led( |
| 6246 | ¶ms->phy[phy_idx], params, mode); |
| 6247 | } |
| 6248 | } |
| 6249 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6250 | switch (mode) { |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 6251 | case LED_MODE_FRONT_PANEL_OFF: |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6252 | case LED_MODE_OFF: |
| 6253 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); |
| 6254 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6255 | SHARED_HW_CFG_LED_MAC1); |
Eilon Greenstein | 345b5d5 | 2008-08-13 15:58:12 -0700 | [diff] [blame] | 6256 | |
| 6257 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); |
Yaniv Rosner | 001cea7 | 2011-10-27 05:09:48 +0000 | [diff] [blame] | 6258 | if (params->phy[EXT_PHY1].type == |
Yaniv Rosner | 9379c9b | 2012-04-04 01:28:58 +0000 | [diff] [blame] | 6259 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) |
| 6260 | tmp &= ~(EMAC_LED_1000MB_OVERRIDE | |
| 6261 | EMAC_LED_100MB_OVERRIDE | |
| 6262 | EMAC_LED_10MB_OVERRIDE); |
| 6263 | else |
| 6264 | tmp |= EMAC_LED_OVERRIDE; |
| 6265 | |
| 6266 | EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6267 | break; |
| 6268 | |
| 6269 | case LED_MODE_OPER: |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6270 | /* For all other phys, OPER mode is same as ON, so in case |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 6271 | * link is down, do nothing |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 6272 | */ |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 6273 | if (!vars->link_up) |
| 6274 | break; |
| 6275 | case LED_MODE_ON: |
Yaniv Rosner | e4d78f1 | 2011-05-31 21:25:55 +0000 | [diff] [blame] | 6276 | if (((params->phy[EXT_PHY1].type == |
| 6277 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || |
| 6278 | (params->phy[EXT_PHY1].type == |
| 6279 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && |
Yaniv Rosner | 1f48353 | 2011-01-18 04:33:31 +0000 | [diff] [blame] | 6280 | CHIP_IS_E2(bp) && params->num_phys == 2) { |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6281 | /* This is a work-around for E2+8727 Configurations */ |
Yaniv Rosner | 1f48353 | 2011-01-18 04:33:31 +0000 | [diff] [blame] | 6282 | if (mode == LED_MODE_ON || |
| 6283 | speed == SPEED_10000){ |
| 6284 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); |
| 6285 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); |
| 6286 | |
| 6287 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); |
| 6288 | EMAC_WR(bp, EMAC_REG_EMAC_LED, |
| 6289 | (tmp | EMAC_LED_OVERRIDE)); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6290 | /* Return here without enabling traffic |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 6291 | * LED blink and setting rate in ON mode. |
Yaniv Rosner | 793bd45 | 2011-08-02 22:59:40 +0000 | [diff] [blame] | 6292 | * In oper mode, enabling LED blink |
| 6293 | * and setting rate is needed. |
| 6294 | */ |
| 6295 | if (mode == LED_MODE_ON) |
| 6296 | return rc; |
Yaniv Rosner | 1f48353 | 2011-01-18 04:33:31 +0000 | [diff] [blame] | 6297 | } |
Yaniv Rosner | 793bd45 | 2011-08-02 22:59:40 +0000 | [diff] [blame] | 6298 | } else if (SINGLE_MEDIA_DIRECT(params)) { |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6299 | /* This is a work-around for HW issue found when link |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 6300 | * is up in CL73 |
| 6301 | */ |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 6302 | if ((!CHIP_IS_E3(bp)) || |
| 6303 | (CHIP_IS_E3(bp) && |
| 6304 | mode == LED_MODE_ON)) |
| 6305 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); |
| 6306 | |
Yaniv Rosner | 793bd45 | 2011-08-02 22:59:40 +0000 | [diff] [blame] | 6307 | if (CHIP_IS_E1x(bp) || |
| 6308 | CHIP_IS_E2(bp) || |
| 6309 | (mode == LED_MODE_ON)) |
| 6310 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); |
| 6311 | else |
| 6312 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, |
| 6313 | hw_led_mode); |
Yaniv Rosner | 001cea7 | 2011-10-27 05:09:48 +0000 | [diff] [blame] | 6314 | } else if ((params->phy[EXT_PHY1].type == |
| 6315 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && |
Yaniv Rosner | 9379c9b | 2012-04-04 01:28:58 +0000 | [diff] [blame] | 6316 | (mode == LED_MODE_ON)) { |
Yaniv Rosner | 001cea7 | 2011-10-27 05:09:48 +0000 | [diff] [blame] | 6317 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); |
| 6318 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); |
Yaniv Rosner | 9379c9b | 2012-04-04 01:28:58 +0000 | [diff] [blame] | 6319 | EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | |
| 6320 | EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); |
| 6321 | /* Break here; otherwise, it'll disable the |
| 6322 | * intended override. |
| 6323 | */ |
| 6324 | break; |
Yaniv Rosner | 793bd45 | 2011-08-02 22:59:40 +0000 | [diff] [blame] | 6325 | } else |
Yaniv Rosner | 001cea7 | 2011-10-27 05:09:48 +0000 | [diff] [blame] | 6326 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, |
| 6327 | hw_led_mode); |
Yaniv Rosner | 7846e47 | 2009-11-05 19:18:07 +0200 | [diff] [blame] | 6328 | |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6329 | REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6330 | /* Set blinking rate to ~15.9Hz */ |
Yaniv Rosner | 26ffaf3 | 2011-10-27 05:09:45 +0000 | [diff] [blame] | 6331 | if (CHIP_IS_E3(bp)) |
| 6332 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, |
| 6333 | LED_BLINK_RATE_VAL_E3); |
| 6334 | else |
| 6335 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, |
| 6336 | LED_BLINK_RATE_VAL_E1X_E2); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6337 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6338 | port*4, 1); |
Yaniv Rosner | 9379c9b | 2012-04-04 01:28:58 +0000 | [diff] [blame] | 6339 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); |
| 6340 | EMAC_WR(bp, EMAC_REG_EMAC_LED, |
| 6341 | (tmp & (~EMAC_LED_OVERRIDE))); |
Eilon Greenstein | 345b5d5 | 2008-08-13 15:58:12 -0700 | [diff] [blame] | 6342 | |
Yaniv Rosner | 7846e47 | 2009-11-05 19:18:07 +0200 | [diff] [blame] | 6343 | if (CHIP_IS_E1(bp) && |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6344 | ((speed == SPEED_2500) || |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6345 | (speed == SPEED_1000) || |
| 6346 | (speed == SPEED_100) || |
| 6347 | (speed == SPEED_10))) { |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6348 | /* For speeds less than 10G LED scheme is different */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6349 | REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6350 | + port*4, 1); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6351 | REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6352 | port*4, 0); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6353 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6354 | port*4, 1); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6355 | } |
| 6356 | break; |
| 6357 | |
| 6358 | default: |
| 6359 | rc = -EINVAL; |
| 6360 | DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n", |
| 6361 | mode); |
| 6362 | break; |
| 6363 | } |
| 6364 | return rc; |
| 6365 | |
| 6366 | } |
| 6367 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6368 | /* This function comes to reflect the actual link state read DIRECTLY from the |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6369 | * HW |
| 6370 | */ |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 6371 | int bnx2x_test_link(struct link_params *params, struct link_vars *vars, |
| 6372 | u8 is_serdes) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6373 | { |
| 6374 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 6375 | u16 gp_status = 0, phy_index = 0; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6376 | u8 ext_phy_link_up = 0, serdes_phy_type; |
| 6377 | struct link_vars temp_vars; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6378 | struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6379 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6380 | if (CHIP_IS_E3(bp)) { |
| 6381 | u16 link_up; |
| 6382 | if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] |
| 6383 | > SPEED_10000) { |
| 6384 | /* Check 20G link */ |
| 6385 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, |
| 6386 | 1, &link_up); |
| 6387 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, |
| 6388 | 1, &link_up); |
| 6389 | link_up &= (1<<2); |
| 6390 | } else { |
| 6391 | /* Check 10G link and below*/ |
| 6392 | u8 lane = bnx2x_get_warpcore_lane(int_phy, params); |
| 6393 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, |
| 6394 | MDIO_WC_REG_GP2_STATUS_GP_2_1, |
| 6395 | &gp_status); |
| 6396 | gp_status = ((gp_status >> 8) & 0xf) | |
| 6397 | ((gp_status >> 12) & 0xf); |
| 6398 | link_up = gp_status & (1 << lane); |
| 6399 | } |
| 6400 | if (!link_up) |
| 6401 | return -ESRCH; |
| 6402 | } else { |
| 6403 | CL22_RD_OVER_CL45(bp, int_phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6404 | MDIO_REG_BANK_GP_STATUS, |
| 6405 | MDIO_GP_STATUS_TOP_AN_STATUS1, |
| 6406 | &gp_status); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 6407 | /* Link is up only if both local phy and external phy are up */ |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6408 | if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) |
| 6409 | return -ESRCH; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6410 | } |
| 6411 | /* In XGXS loopback mode, do not check external PHY */ |
| 6412 | if (params->loopback_mode == LOOPBACK_XGXS) |
| 6413 | return 0; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6414 | |
| 6415 | switch (params->num_phys) { |
| 6416 | case 1: |
| 6417 | /* No external PHY */ |
| 6418 | return 0; |
| 6419 | case 2: |
| 6420 | ext_phy_link_up = params->phy[EXT_PHY1].read_status( |
| 6421 | ¶ms->phy[EXT_PHY1], |
| 6422 | params, &temp_vars); |
| 6423 | break; |
| 6424 | case 3: /* Dual Media */ |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 6425 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
| 6426 | phy_index++) { |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6427 | serdes_phy_type = ((params->phy[phy_index].media_type == |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 6428 | ETH_PHY_SFPP_10G_FIBER) || |
| 6429 | (params->phy[phy_index].media_type == |
| 6430 | ETH_PHY_SFP_1G_FIBER) || |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6431 | (params->phy[phy_index].media_type == |
Yaniv Rosner | 1ac9e42 | 2011-05-31 21:26:11 +0000 | [diff] [blame] | 6432 | ETH_PHY_XFP_FIBER) || |
| 6433 | (params->phy[phy_index].media_type == |
| 6434 | ETH_PHY_DA_TWINAX)); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6435 | |
| 6436 | if (is_serdes != serdes_phy_type) |
| 6437 | continue; |
| 6438 | if (params->phy[phy_index].read_status) { |
| 6439 | ext_phy_link_up |= |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 6440 | params->phy[phy_index].read_status( |
| 6441 | ¶ms->phy[phy_index], |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6442 | params, &temp_vars); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6443 | } |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 6444 | } |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6445 | break; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6446 | } |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6447 | if (ext_phy_link_up) |
| 6448 | return 0; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6449 | return -ESRCH; |
| 6450 | } |
| 6451 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 6452 | static int bnx2x_link_initialize(struct link_params *params, |
| 6453 | struct link_vars *vars) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6454 | { |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 6455 | int rc = 0; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6456 | u8 phy_index, non_ext_phy; |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 6457 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6458 | /* In case of external phy existence, the line speed would be the |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 6459 | * line speed linked up by the external phy. In case it is direct |
| 6460 | * only, then the line_speed during initialization will be |
| 6461 | * equal to the req_line_speed |
| 6462 | */ |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 6463 | vars->line_speed = params->phy[INT_PHY].req_line_speed; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6464 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6465 | /* Initialize the internal phy in case this is a direct board |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 6466 | * (no external phys), or this board has external phy which requires |
| 6467 | * to first. |
| 6468 | */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6469 | if (!USES_WARPCORE(bp)) |
| 6470 | bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6471 | /* init ext phy and enable link state int */ |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 6472 | non_ext_phy = (SINGLE_MEDIA_DIRECT(params) || |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 6473 | (params->loopback_mode == LOOPBACK_XGXS)); |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6474 | |
| 6475 | if (non_ext_phy || |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 6476 | (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || |
Eilon Greenstein | 8660d8c | 2009-03-02 08:01:02 +0000 | [diff] [blame] | 6477 | (params->loopback_mode == LOOPBACK_EXT_PHY)) { |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 6478 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6479 | if (vars->line_speed == SPEED_AUTO_NEG && |
| 6480 | (CHIP_IS_E1x(bp) || |
| 6481 | CHIP_IS_E2(bp))) |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 6482 | bnx2x_set_parallel_detection(phy, params); |
Yaniv Rosner | ec146a6 | 2011-05-31 21:29:27 +0000 | [diff] [blame] | 6483 | if (params->phy[INT_PHY].config_init) |
| 6484 | params->phy[INT_PHY].config_init(phy, |
| 6485 | params, |
| 6486 | vars); |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6487 | } |
| 6488 | |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 6489 | /* Init external phy*/ |
Yaniv Rosner | fd36a2e | 2011-05-31 21:29:05 +0000 | [diff] [blame] | 6490 | if (non_ext_phy) { |
| 6491 | if (params->phy[INT_PHY].supported & |
| 6492 | SUPPORTED_FIBRE) |
| 6493 | vars->link_status |= LINK_STATUS_SERDES_LINK; |
| 6494 | } else { |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6495 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
| 6496 | phy_index++) { |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6497 | /* No need to initialize second phy in case of first |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6498 | * phy only selection. In case of second phy, we do |
| 6499 | * need to initialize the first phy, since they are |
| 6500 | * connected. |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 6501 | */ |
Yaniv Rosner | fd36a2e | 2011-05-31 21:29:05 +0000 | [diff] [blame] | 6502 | if (params->phy[phy_index].supported & |
| 6503 | SUPPORTED_FIBRE) |
| 6504 | vars->link_status |= LINK_STATUS_SERDES_LINK; |
| 6505 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6506 | if (phy_index == EXT_PHY2 && |
| 6507 | (bnx2x_phy_selection(params) == |
| 6508 | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 6509 | DP(NETIF_MSG_LINK, |
| 6510 | "Not initializing second phy\n"); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6511 | continue; |
| 6512 | } |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6513 | params->phy[phy_index].config_init( |
| 6514 | ¶ms->phy[phy_index], |
| 6515 | params, vars); |
| 6516 | } |
Yaniv Rosner | fd36a2e | 2011-05-31 21:29:05 +0000 | [diff] [blame] | 6517 | } |
Yaniv Rosner | d90d96b | 2010-09-07 11:41:04 +0000 | [diff] [blame] | 6518 | /* Reset the interrupt indication after phy was initialized */ |
| 6519 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + |
| 6520 | params->port*4, |
| 6521 | (NIG_STATUS_XGXS0_LINK10G | |
| 6522 | NIG_STATUS_XGXS0_LINK_STATUS | |
| 6523 | NIG_STATUS_SERDES0_LINK_STATUS | |
| 6524 | NIG_MASK_MI_INT)); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6525 | return rc; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6526 | } |
| 6527 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 6528 | static void bnx2x_int_link_reset(struct bnx2x_phy *phy, |
| 6529 | struct link_params *params) |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6530 | { |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 6531 | /* Reset the SerDes/XGXS */ |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6532 | REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, |
| 6533 | (0x1ff << (params->port*16))); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6534 | } |
| 6535 | |
| 6536 | static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, |
| 6537 | struct link_params *params) |
| 6538 | { |
| 6539 | struct bnx2x *bp = params->bp; |
| 6540 | u8 gpio_port; |
| 6541 | /* HW reset */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6542 | if (CHIP_IS_E2(bp)) |
| 6543 | gpio_port = BP_PATH(bp); |
| 6544 | else |
| 6545 | gpio_port = params->port; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6546 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6547 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
| 6548 | gpio_port); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6549 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6550 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
| 6551 | gpio_port); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6552 | DP(NETIF_MSG_LINK, "reset external PHY\n"); |
| 6553 | } |
| 6554 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 6555 | static int bnx2x_update_link_down(struct link_params *params, |
| 6556 | struct link_vars *vars) |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6557 | { |
| 6558 | struct bnx2x *bp = params->bp; |
| 6559 | u8 port = params->port; |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 6560 | |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6561 | DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 6562 | bnx2x_set_led(params, vars, LED_MODE_OFF, 0); |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 6563 | vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 6564 | /* Indicate no mac active */ |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6565 | vars->mac_type = MAC_TYPE_NONE; |
| 6566 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 6567 | /* Update shared memory */ |
Yaniv Rosner | 4978140 | 2012-10-31 05:46:55 +0000 | [diff] [blame] | 6568 | vars->link_status &= ~LINK_UPDATE_MASK; |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6569 | vars->line_speed = 0; |
| 6570 | bnx2x_update_mng(params, vars->link_status); |
| 6571 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 6572 | /* Activate nig drain */ |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6573 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); |
| 6574 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 6575 | /* Disable emac */ |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 6576 | if (!CHIP_IS_E3(bp)) |
| 6577 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); |
Eilon Greenstein | 6c55c3cd | 2009-01-14 06:44:13 +0000 | [diff] [blame] | 6578 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 6579 | usleep_range(10000, 20000); |
| 6580 | /* Reset BigMac/Xmac */ |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 6581 | if (CHIP_IS_E1x(bp) || |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 6582 | CHIP_IS_E2(bp)) |
| 6583 | bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); |
| 6584 | |
Yaniv Rosner | ce7c048 | 2011-10-27 05:09:47 +0000 | [diff] [blame] | 6585 | if (CHIP_IS_E3(bp)) { |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 6586 | /* Prevent LPI Generation by chip */ |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 6587 | REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), |
| 6588 | 0); |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 6589 | REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), |
| 6590 | 0); |
| 6591 | vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | |
| 6592 | SHMEM_EEE_ACTIVE_BIT); |
| 6593 | |
| 6594 | bnx2x_update_mng_eee(params, vars->eee_status); |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 6595 | bnx2x_set_xmac_rxtx(params, 0); |
| 6596 | bnx2x_set_umac_rxtx(params, 0); |
Yaniv Rosner | ce7c048 | 2011-10-27 05:09:47 +0000 | [diff] [blame] | 6597 | } |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 6598 | |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6599 | return 0; |
| 6600 | } |
| 6601 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 6602 | static int bnx2x_update_link_up(struct link_params *params, |
| 6603 | struct link_vars *vars, |
| 6604 | u8 link_10g) |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6605 | { |
| 6606 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 55098c5 | 2012-04-03 18:41:27 +0000 | [diff] [blame] | 6607 | u8 phy_idx, port = params->port; |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 6608 | int rc = 0; |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 6609 | |
Yaniv Rosner | de6f337 | 2011-08-02 22:59:25 +0000 | [diff] [blame] | 6610 | vars->link_status |= (LINK_STATUS_LINK_UP | |
| 6611 | LINK_STATUS_PHYSICAL_LINK_FLAG); |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 6612 | vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 6613 | |
Yaniv Rosner | 7aa0711 | 2010-09-07 11:41:01 +0000 | [diff] [blame] | 6614 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
| 6615 | vars->link_status |= |
| 6616 | LINK_STATUS_TX_FLOW_CONTROL_ENABLED; |
| 6617 | |
| 6618 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) |
| 6619 | vars->link_status |= |
| 6620 | LINK_STATUS_RX_FLOW_CONTROL_ENABLED; |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 6621 | if (USES_WARPCORE(bp)) { |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 6622 | if (link_10g) { |
| 6623 | if (bnx2x_xmac_enable(params, vars, 0) == |
| 6624 | -ESRCH) { |
| 6625 | DP(NETIF_MSG_LINK, "Found errors on XMAC\n"); |
| 6626 | vars->link_up = 0; |
| 6627 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; |
| 6628 | vars->link_status &= ~LINK_STATUS_LINK_UP; |
| 6629 | } |
| 6630 | } else |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 6631 | bnx2x_umac_enable(params, vars, 0); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 6632 | bnx2x_set_led(params, vars, |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 6633 | LED_MODE_OPER, vars->line_speed); |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 6634 | |
| 6635 | if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && |
| 6636 | (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { |
| 6637 | DP(NETIF_MSG_LINK, "Enabling LPI assertion\n"); |
| 6638 | REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + |
| 6639 | (params->port << 2), 1); |
| 6640 | REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); |
| 6641 | REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + |
| 6642 | (params->port << 2), 0xfc20); |
| 6643 | } |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 6644 | } |
| 6645 | if ((CHIP_IS_E1x(bp) || |
| 6646 | CHIP_IS_E2(bp))) { |
| 6647 | if (link_10g) { |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 6648 | if (bnx2x_bmac_enable(params, vars, 0, 1) == |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 6649 | -ESRCH) { |
| 6650 | DP(NETIF_MSG_LINK, "Found errors on BMAC\n"); |
| 6651 | vars->link_up = 0; |
| 6652 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; |
| 6653 | vars->link_status &= ~LINK_STATUS_LINK_UP; |
| 6654 | } |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6655 | |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 6656 | bnx2x_set_led(params, vars, |
| 6657 | LED_MODE_OPER, SPEED_10000); |
| 6658 | } else { |
| 6659 | rc = bnx2x_emac_program(params, vars); |
| 6660 | bnx2x_emac_enable(params, vars, 0); |
Yaniv Rosner | 0c786f0 | 2009-11-05 19:18:32 +0200 | [diff] [blame] | 6661 | |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 6662 | /* AN complete? */ |
| 6663 | if ((vars->link_status & |
| 6664 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) |
| 6665 | && (!(vars->phy_flags & PHY_SGMII_FLAG)) && |
| 6666 | SINGLE_MEDIA_DIRECT(params)) |
| 6667 | bnx2x_set_gmii_tx_driver(params); |
| 6668 | } |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6669 | } |
| 6670 | |
| 6671 | /* PBF - link up */ |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 6672 | if (CHIP_IS_E1x(bp)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6673 | rc |= bnx2x_pbf_update(params, vars->flow_ctrl, |
| 6674 | vars->line_speed); |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6675 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 6676 | /* Disable drain */ |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6677 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); |
| 6678 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 6679 | /* Update shared memory */ |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6680 | bnx2x_update_mng(params, vars->link_status); |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 6681 | bnx2x_update_mng_eee(params, vars->eee_status); |
Yaniv Rosner | 55098c5 | 2012-04-03 18:41:27 +0000 | [diff] [blame] | 6682 | /* Check remote fault */ |
| 6683 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { |
| 6684 | if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { |
| 6685 | bnx2x_check_half_open_conn(params, vars, 0); |
| 6686 | break; |
| 6687 | } |
| 6688 | } |
Eilon Greenstein | 6c55c3cd | 2009-01-14 06:44:13 +0000 | [diff] [blame] | 6689 | msleep(20); |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6690 | return rc; |
| 6691 | } |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6692 | /* The bnx2x_link_update function should be called upon link |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6693 | * interrupt. |
| 6694 | * Link is considered up as follows: |
| 6695 | * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs |
| 6696 | * to be up |
| 6697 | * - SINGLE_MEDIA - The link between the 577xx and the external |
| 6698 | * phy (XGXS) need to up as well as the external link of the |
| 6699 | * phy (PHY_EXT1) |
| 6700 | * - DUAL_MEDIA - The link between the 577xx and the first |
| 6701 | * external phy needs to be up, and at least one of the 2 |
| 6702 | * external phy link must be up. |
Yaniv Rosner | 62b29a5 | 2010-09-07 11:40:58 +0000 | [diff] [blame] | 6703 | */ |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 6704 | int bnx2x_link_update(struct link_params *params, struct link_vars *vars) |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6705 | { |
| 6706 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6707 | struct link_vars phy_vars[MAX_PHYS]; |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6708 | u8 port = params->port; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6709 | u8 link_10g_plus, phy_index; |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 6710 | u8 ext_phy_link_up = 0, cur_link_up; |
| 6711 | int rc = 0; |
Eilon Greenstein | 2f90446 | 2009-08-12 08:22:16 +0000 | [diff] [blame] | 6712 | u8 is_mi_int = 0; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6713 | u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; |
| 6714 | u8 active_external_phy = INT_PHY; |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 6715 | vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; |
Yaniv Rosner | 4978140 | 2012-10-31 05:46:55 +0000 | [diff] [blame] | 6716 | vars->link_status &= ~LINK_UPDATE_MASK; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6717 | for (phy_index = INT_PHY; phy_index < params->num_phys; |
| 6718 | phy_index++) { |
| 6719 | phy_vars[phy_index].flow_ctrl = 0; |
| 6720 | phy_vars[phy_index].link_status = 0; |
| 6721 | phy_vars[phy_index].line_speed = 0; |
| 6722 | phy_vars[phy_index].duplex = DUPLEX_FULL; |
| 6723 | phy_vars[phy_index].phy_link_up = 0; |
| 6724 | phy_vars[phy_index].link_up = 0; |
Yaniv Rosner | c688fe2 | 2011-05-31 21:27:06 +0000 | [diff] [blame] | 6725 | phy_vars[phy_index].fault_detected = 0; |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 6726 | /* different consideration, since vars holds inner state */ |
| 6727 | phy_vars[phy_index].eee_status = vars->eee_status; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6728 | } |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6729 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6730 | if (USES_WARPCORE(bp)) |
| 6731 | bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); |
| 6732 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6733 | DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", |
Eilon Greenstein | 2f90446 | 2009-08-12 08:22:16 +0000 | [diff] [blame] | 6734 | port, (vars->phy_flags & PHY_XGXS_FLAG), |
| 6735 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6736 | |
Eilon Greenstein | 2f90446 | 2009-08-12 08:22:16 +0000 | [diff] [blame] | 6737 | is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6738 | port*0x18) > 0); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6739 | DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", |
Eilon Greenstein | 2f90446 | 2009-08-12 08:22:16 +0000 | [diff] [blame] | 6740 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), |
| 6741 | is_mi_int, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6742 | REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6743 | |
| 6744 | DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", |
| 6745 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), |
| 6746 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); |
| 6747 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 6748 | /* Disable emac */ |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 6749 | if (!CHIP_IS_E3(bp)) |
| 6750 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); |
Eilon Greenstein | 6c55c3cd | 2009-01-14 06:44:13 +0000 | [diff] [blame] | 6751 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6752 | /* Step 1: |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 6753 | * Check external link change only for external phys, and apply |
| 6754 | * priority selection between them in case the link on both phys |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 6755 | * is up. Note that instead of the common vars, a temporary |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 6756 | * vars argument is used since each phy may have different link/ |
| 6757 | * speed/duplex result |
| 6758 | */ |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6759 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
| 6760 | phy_index++) { |
| 6761 | struct bnx2x_phy *phy = ¶ms->phy[phy_index]; |
| 6762 | if (!phy->read_status) |
| 6763 | continue; |
| 6764 | /* Read link status and params of this ext phy */ |
| 6765 | cur_link_up = phy->read_status(phy, params, |
| 6766 | &phy_vars[phy_index]); |
| 6767 | if (cur_link_up) { |
| 6768 | DP(NETIF_MSG_LINK, "phy in index %d link is up\n", |
| 6769 | phy_index); |
| 6770 | } else { |
| 6771 | DP(NETIF_MSG_LINK, "phy in index %d link is down\n", |
| 6772 | phy_index); |
| 6773 | continue; |
| 6774 | } |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6775 | |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6776 | if (!ext_phy_link_up) { |
| 6777 | ext_phy_link_up = 1; |
| 6778 | active_external_phy = phy_index; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6779 | } else { |
| 6780 | switch (bnx2x_phy_selection(params)) { |
| 6781 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: |
| 6782 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6783 | /* In this option, the first PHY makes sure to pass the |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6784 | * traffic through itself only. |
| 6785 | * Its not clear how to reset the link on the second phy |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 6786 | */ |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6787 | active_external_phy = EXT_PHY1; |
| 6788 | break; |
| 6789 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6790 | /* In this option, the first PHY makes sure to pass the |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6791 | * traffic through the second PHY. |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 6792 | */ |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6793 | active_external_phy = EXT_PHY2; |
| 6794 | break; |
| 6795 | default: |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6796 | /* Link indication on both PHYs with the following cases |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6797 | * is invalid: |
| 6798 | * - FIRST_PHY means that second phy wasn't initialized, |
| 6799 | * hence its link is expected to be down |
| 6800 | * - SECOND_PHY means that first phy should not be able |
| 6801 | * to link up by itself (using configuration) |
| 6802 | * - DEFAULT should be overriden during initialiazation |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 6803 | */ |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6804 | DP(NETIF_MSG_LINK, "Invalid link indication" |
| 6805 | "mpc=0x%x. DISABLING LINK !!!\n", |
| 6806 | params->multi_phy_config); |
| 6807 | ext_phy_link_up = 0; |
| 6808 | break; |
| 6809 | } |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6810 | } |
| 6811 | } |
| 6812 | prev_line_speed = vars->line_speed; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6813 | /* Step 2: |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 6814 | * Read the status of the internal phy. In case of |
| 6815 | * DIRECT_SINGLE_MEDIA board, this link is the external link, |
| 6816 | * otherwise this is the link between the 577xx and the first |
| 6817 | * external phy |
| 6818 | */ |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6819 | if (params->phy[INT_PHY].read_status) |
| 6820 | params->phy[INT_PHY].read_status( |
| 6821 | ¶ms->phy[INT_PHY], |
| 6822 | params, vars); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6823 | /* The INT_PHY flow control reside in the vars. This include the |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6824 | * case where the speed or flow control are not set to AUTO. |
| 6825 | * Otherwise, the active external phy flow control result is set |
| 6826 | * to the vars. The ext_phy_line_speed is needed to check if the |
| 6827 | * speed is different between the internal phy and external phy. |
| 6828 | * This case may be result of intermediate link speed change. |
| 6829 | */ |
| 6830 | if (active_external_phy > INT_PHY) { |
| 6831 | vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6832 | /* Link speed is taken from the XGXS. AN and FC result from |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6833 | * the external phy. |
| 6834 | */ |
| 6835 | vars->link_status |= phy_vars[active_external_phy].link_status; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6836 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6837 | /* if active_external_phy is first PHY and link is up - disable |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6838 | * disable TX on second external PHY |
| 6839 | */ |
| 6840 | if (active_external_phy == EXT_PHY1) { |
| 6841 | if (params->phy[EXT_PHY2].phy_specific_func) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 6842 | DP(NETIF_MSG_LINK, |
| 6843 | "Disabling TX on EXT_PHY2\n"); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6844 | params->phy[EXT_PHY2].phy_specific_func( |
| 6845 | ¶ms->phy[EXT_PHY2], |
| 6846 | params, DISABLE_TX); |
| 6847 | } |
| 6848 | } |
| 6849 | |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6850 | ext_phy_line_speed = phy_vars[active_external_phy].line_speed; |
| 6851 | vars->duplex = phy_vars[active_external_phy].duplex; |
| 6852 | if (params->phy[active_external_phy].supported & |
| 6853 | SUPPORTED_FIBRE) |
| 6854 | vars->link_status |= LINK_STATUS_SERDES_LINK; |
Yaniv Rosner | fd36a2e | 2011-05-31 21:29:05 +0000 | [diff] [blame] | 6855 | else |
| 6856 | vars->link_status &= ~LINK_STATUS_SERDES_LINK; |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 6857 | |
| 6858 | vars->eee_status = phy_vars[active_external_phy].eee_status; |
| 6859 | |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6860 | DP(NETIF_MSG_LINK, "Active external phy selected: %x\n", |
| 6861 | active_external_phy); |
| 6862 | } |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6863 | |
| 6864 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
| 6865 | phy_index++) { |
| 6866 | if (params->phy[phy_index].flags & |
| 6867 | FLAGS_REARM_LATCH_SIGNAL) { |
| 6868 | bnx2x_rearm_latch_signal(bp, port, |
| 6869 | phy_index == |
| 6870 | active_external_phy); |
| 6871 | break; |
| 6872 | } |
| 6873 | } |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6874 | DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," |
| 6875 | " ext_phy_line_speed = %d\n", vars->flow_ctrl, |
| 6876 | vars->link_status, ext_phy_line_speed); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6877 | /* Upon link speed change set the NIG into drain mode. Comes to |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6878 | * deals with possible FIFO glitch due to clk change when speed |
| 6879 | * is decreased without link down indicator |
| 6880 | */ |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6881 | |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6882 | if (vars->phy_link_up) { |
| 6883 | if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && |
| 6884 | (ext_phy_line_speed != vars->line_speed)) { |
| 6885 | DP(NETIF_MSG_LINK, "Internal link speed %d is" |
| 6886 | " different than the external" |
| 6887 | " link speed %d\n", vars->line_speed, |
| 6888 | ext_phy_line_speed); |
| 6889 | vars->phy_link_up = 0; |
| 6890 | } else if (prev_line_speed != vars->line_speed) { |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6891 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, |
| 6892 | 0); |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 6893 | usleep_range(1000, 2000); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6894 | } |
| 6895 | } |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6896 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 6897 | /* Anything 10 and over uses the bmac */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6898 | link_10g_plus = (vars->line_speed >= SPEED_10000); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6899 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6900 | bnx2x_link_int_ack(params, vars, link_10g_plus); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6901 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6902 | /* In case external phy link is up, and internal link is down |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 6903 | * (not initialized yet probably after link initialization, it |
| 6904 | * needs to be initialized. |
| 6905 | * Note that after link down-up as result of cable plug, the xgxs |
| 6906 | * link would probably become up again without the need |
| 6907 | * initialize it |
| 6908 | */ |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6909 | if (!(SINGLE_MEDIA_DIRECT(params))) { |
| 6910 | DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d," |
| 6911 | " init_preceding = %d\n", ext_phy_link_up, |
| 6912 | vars->phy_link_up, |
| 6913 | params->phy[EXT_PHY1].flags & |
| 6914 | FLAGS_INIT_XGXS_FIRST); |
| 6915 | if (!(params->phy[EXT_PHY1].flags & |
| 6916 | FLAGS_INIT_XGXS_FIRST) |
| 6917 | && ext_phy_link_up && !vars->phy_link_up) { |
| 6918 | vars->line_speed = ext_phy_line_speed; |
| 6919 | if (vars->line_speed < SPEED_1000) |
| 6920 | vars->phy_flags |= PHY_SGMII_FLAG; |
| 6921 | else |
| 6922 | vars->phy_flags &= ~PHY_SGMII_FLAG; |
Yaniv Rosner | ec146a6 | 2011-05-31 21:29:27 +0000 | [diff] [blame] | 6923 | |
| 6924 | if (params->phy[INT_PHY].config_init) |
| 6925 | params->phy[INT_PHY].config_init( |
| 6926 | ¶ms->phy[INT_PHY], params, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6927 | vars); |
| 6928 | } |
| 6929 | } |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 6930 | /* Link is up only if both local phy and external phy (in case of |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 6931 | * non-direct board) are up and no fault detected on active PHY. |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6932 | */ |
| 6933 | vars->link_up = (vars->phy_link_up && |
| 6934 | (ext_phy_link_up || |
Yaniv Rosner | c688fe2 | 2011-05-31 21:27:06 +0000 | [diff] [blame] | 6935 | SINGLE_MEDIA_DIRECT(params)) && |
| 6936 | (phy_vars[active_external_phy].fault_detected == 0)); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6937 | |
Yaniv Rosner | 27d9129 | 2012-04-04 01:28:54 +0000 | [diff] [blame] | 6938 | /* Update the PFC configuration in case it was changed */ |
| 6939 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) |
| 6940 | vars->link_status |= LINK_STATUS_PFC_ENABLED; |
| 6941 | else |
| 6942 | vars->link_status &= ~LINK_STATUS_PFC_ENABLED; |
| 6943 | |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6944 | if (vars->link_up) |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 6945 | rc = bnx2x_update_link_up(params, vars, link_10g_plus); |
Yaniv Rosner | 57963ed | 2008-08-13 15:55:28 -0700 | [diff] [blame] | 6946 | else |
| 6947 | rc = bnx2x_update_link_down(params, vars); |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6948 | |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 6949 | /* Update MCP link status was changed */ |
| 6950 | if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX) |
| 6951 | bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); |
| 6952 | |
Yaniv Rosner | ea4e040 | 2008-06-23 20:27:26 -0700 | [diff] [blame] | 6953 | return rc; |
| 6954 | } |
| 6955 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 6956 | /*****************************************************************************/ |
| 6957 | /* External Phy section */ |
| 6958 | /*****************************************************************************/ |
| 6959 | void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6960 | { |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 6961 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6962 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 6963 | usleep_range(1000, 2000); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 6964 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6965 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 6966 | } |
| 6967 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 6968 | static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, |
| 6969 | u32 spirom_ver, u32 ver_addr) |
| 6970 | { |
| 6971 | DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", |
| 6972 | (u16)(spirom_ver>>16), (u16)spirom_ver, port); |
| 6973 | |
| 6974 | if (ver_addr) |
| 6975 | REG_WR(bp, ver_addr, spirom_ver); |
| 6976 | } |
| 6977 | |
| 6978 | static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, |
| 6979 | struct bnx2x_phy *phy, |
| 6980 | u8 port) |
| 6981 | { |
| 6982 | u16 fw_ver1, fw_ver2; |
| 6983 | |
| 6984 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6985 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 6986 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 6987 | MDIO_PMA_REG_ROM_VER2, &fw_ver2); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 6988 | bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), |
| 6989 | phy->ver_addr); |
| 6990 | } |
| 6991 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 6992 | static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, |
| 6993 | struct bnx2x_phy *phy, |
| 6994 | struct link_vars *vars) |
| 6995 | { |
| 6996 | u16 val; |
| 6997 | bnx2x_cl45_read(bp, phy, |
| 6998 | MDIO_AN_DEVAD, |
| 6999 | MDIO_AN_REG_STATUS, &val); |
| 7000 | bnx2x_cl45_read(bp, phy, |
| 7001 | MDIO_AN_DEVAD, |
| 7002 | MDIO_AN_REG_STATUS, &val); |
| 7003 | if (val & (1<<5)) |
| 7004 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; |
| 7005 | if ((val & (1<<0)) == 0) |
| 7006 | vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; |
| 7007 | } |
| 7008 | |
| 7009 | /******************************************************************/ |
| 7010 | /* common BCM8073/BCM8727 PHY SECTION */ |
| 7011 | /******************************************************************/ |
| 7012 | static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, |
| 7013 | struct link_params *params, |
| 7014 | struct link_vars *vars) |
| 7015 | { |
| 7016 | struct bnx2x *bp = params->bp; |
| 7017 | if (phy->req_line_speed == SPEED_10 || |
| 7018 | phy->req_line_speed == SPEED_100) { |
| 7019 | vars->flow_ctrl = phy->req_flow_ctrl; |
| 7020 | return; |
| 7021 | } |
| 7022 | |
| 7023 | if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && |
| 7024 | (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) { |
| 7025 | u16 pause_result; |
| 7026 | u16 ld_pause; /* local */ |
| 7027 | u16 lp_pause; /* link partner */ |
| 7028 | bnx2x_cl45_read(bp, phy, |
| 7029 | MDIO_AN_DEVAD, |
| 7030 | MDIO_AN_REG_CL37_FC_LD, &ld_pause); |
| 7031 | |
| 7032 | bnx2x_cl45_read(bp, phy, |
| 7033 | MDIO_AN_DEVAD, |
| 7034 | MDIO_AN_REG_CL37_FC_LP, &lp_pause); |
| 7035 | pause_result = (ld_pause & |
| 7036 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; |
| 7037 | pause_result |= (lp_pause & |
| 7038 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; |
| 7039 | |
| 7040 | bnx2x_pause_resolve(vars, pause_result); |
| 7041 | DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", |
| 7042 | pause_result); |
| 7043 | } |
| 7044 | } |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 7045 | static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, |
| 7046 | struct bnx2x_phy *phy, |
| 7047 | u8 port) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7048 | { |
Yaniv Rosner | 5c99274b | 2011-01-18 04:33:36 +0000 | [diff] [blame] | 7049 | u32 count = 0; |
| 7050 | u16 fw_ver1, fw_msgout; |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 7051 | int rc = 0; |
Yaniv Rosner | 5c99274b | 2011-01-18 04:33:36 +0000 | [diff] [blame] | 7052 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7053 | /* Boot port from external ROM */ |
| 7054 | /* EDC grst */ |
| 7055 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7056 | MDIO_PMA_DEVAD, |
| 7057 | MDIO_PMA_REG_GEN_CTRL, |
| 7058 | 0x0001); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7059 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 7060 | /* Ucode reboot and rst */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7061 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7062 | MDIO_PMA_DEVAD, |
| 7063 | MDIO_PMA_REG_GEN_CTRL, |
| 7064 | 0x008c); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7065 | |
| 7066 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7067 | MDIO_PMA_DEVAD, |
| 7068 | MDIO_PMA_REG_MISC_CTRL1, 0x0001); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7069 | |
| 7070 | /* Reset internal microprocessor */ |
| 7071 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7072 | MDIO_PMA_DEVAD, |
| 7073 | MDIO_PMA_REG_GEN_CTRL, |
| 7074 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7075 | |
| 7076 | /* Release srst bit */ |
| 7077 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7078 | MDIO_PMA_DEVAD, |
| 7079 | MDIO_PMA_REG_GEN_CTRL, |
| 7080 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7081 | |
Yaniv Rosner | 5c99274b | 2011-01-18 04:33:36 +0000 | [diff] [blame] | 7082 | /* Delay 100ms per the PHY specifications */ |
| 7083 | msleep(100); |
| 7084 | |
| 7085 | /* 8073 sometimes taking longer to download */ |
| 7086 | do { |
| 7087 | count++; |
| 7088 | if (count > 300) { |
| 7089 | DP(NETIF_MSG_LINK, |
| 7090 | "bnx2x_8073_8727_external_rom_boot port %x:" |
| 7091 | "Download failed. fw version = 0x%x\n", |
| 7092 | port, fw_ver1); |
| 7093 | rc = -EINVAL; |
| 7094 | break; |
| 7095 | } |
| 7096 | |
| 7097 | bnx2x_cl45_read(bp, phy, |
| 7098 | MDIO_PMA_DEVAD, |
| 7099 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); |
| 7100 | bnx2x_cl45_read(bp, phy, |
| 7101 | MDIO_PMA_DEVAD, |
| 7102 | MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); |
| 7103 | |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 7104 | usleep_range(1000, 2000); |
Yaniv Rosner | 5c99274b | 2011-01-18 04:33:36 +0000 | [diff] [blame] | 7105 | } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || |
| 7106 | ((fw_msgout & 0xff) != 0x03 && (phy->type == |
| 7107 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7108 | |
| 7109 | /* Clear ser_boot_ctl bit */ |
| 7110 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7111 | MDIO_PMA_DEVAD, |
| 7112 | MDIO_PMA_REG_MISC_CTRL1, 0x0000); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7113 | bnx2x_save_bcm_spirom_ver(bp, phy, port); |
Yaniv Rosner | 5c99274b | 2011-01-18 04:33:36 +0000 | [diff] [blame] | 7114 | |
| 7115 | DP(NETIF_MSG_LINK, |
| 7116 | "bnx2x_8073_8727_external_rom_boot port %x:" |
| 7117 | "Download complete. fw version = 0x%x\n", |
| 7118 | port, fw_ver1); |
| 7119 | |
| 7120 | return rc; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7121 | } |
| 7122 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7123 | /******************************************************************/ |
| 7124 | /* BCM8073 PHY SECTION */ |
| 7125 | /******************************************************************/ |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 7126 | static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7127 | { |
| 7128 | /* This is only required for 8073A1, version 102 only */ |
| 7129 | u16 val; |
| 7130 | |
| 7131 | /* Read 8073 HW revision*/ |
| 7132 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7133 | MDIO_PMA_DEVAD, |
| 7134 | MDIO_PMA_REG_8073_CHIP_REV, &val); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7135 | |
| 7136 | if (val != 1) { |
| 7137 | /* No need to workaround in 8073 A1 */ |
| 7138 | return 0; |
| 7139 | } |
| 7140 | |
| 7141 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7142 | MDIO_PMA_DEVAD, |
| 7143 | MDIO_PMA_REG_ROM_VER2, &val); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7144 | |
| 7145 | /* SNR should be applied only for version 0x102 */ |
| 7146 | if (val != 0x102) |
| 7147 | return 0; |
| 7148 | |
| 7149 | return 1; |
| 7150 | } |
| 7151 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 7152 | static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7153 | { |
| 7154 | u16 val, cnt, cnt1 ; |
| 7155 | |
| 7156 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7157 | MDIO_PMA_DEVAD, |
| 7158 | MDIO_PMA_REG_8073_CHIP_REV, &val); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7159 | |
| 7160 | if (val > 0) { |
| 7161 | /* No need to workaround in 8073 A1 */ |
| 7162 | return 0; |
| 7163 | } |
| 7164 | /* XAUI workaround in 8073 A0: */ |
| 7165 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 7166 | /* After loading the boot ROM and restarting Autoneg, poll |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 7167 | * Dev1, Reg $C820: |
| 7168 | */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7169 | |
| 7170 | for (cnt = 0; cnt < 1000; cnt++) { |
| 7171 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7172 | MDIO_PMA_DEVAD, |
| 7173 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, |
| 7174 | &val); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 7175 | /* If bit [14] = 0 or bit [13] = 0, continue on with |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 7176 | * system initialization (XAUI work-around not required, as |
| 7177 | * these bits indicate 2.5G or 1G link up). |
| 7178 | */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7179 | if (!(val & (1<<14)) || !(val & (1<<13))) { |
| 7180 | DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); |
| 7181 | return 0; |
| 7182 | } else if (!(val & (1<<15))) { |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 7183 | DP(NETIF_MSG_LINK, "bit 15 went off\n"); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 7184 | /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 7185 | * MSB (bit15) goes to 1 (indicating that the XAUI |
| 7186 | * workaround has completed), then continue on with |
| 7187 | * system initialization. |
| 7188 | */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7189 | for (cnt1 = 0; cnt1 < 1000; cnt1++) { |
| 7190 | bnx2x_cl45_read(bp, phy, |
| 7191 | MDIO_PMA_DEVAD, |
| 7192 | MDIO_PMA_REG_8073_XAUI_WA, &val); |
| 7193 | if (val & (1<<15)) { |
| 7194 | DP(NETIF_MSG_LINK, |
| 7195 | "XAUI workaround has completed\n"); |
| 7196 | return 0; |
| 7197 | } |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 7198 | usleep_range(3000, 6000); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7199 | } |
| 7200 | break; |
| 7201 | } |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 7202 | usleep_range(3000, 6000); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7203 | } |
| 7204 | DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); |
| 7205 | return -EINVAL; |
| 7206 | } |
| 7207 | |
| 7208 | static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) |
| 7209 | { |
| 7210 | /* Force KR or KX */ |
| 7211 | bnx2x_cl45_write(bp, phy, |
| 7212 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); |
| 7213 | bnx2x_cl45_write(bp, phy, |
| 7214 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); |
| 7215 | bnx2x_cl45_write(bp, phy, |
| 7216 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); |
| 7217 | bnx2x_cl45_write(bp, phy, |
| 7218 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); |
| 7219 | } |
| 7220 | |
| 7221 | static void bnx2x_8073_set_pause_cl37(struct link_params *params, |
| 7222 | struct bnx2x_phy *phy, |
| 7223 | struct link_vars *vars) |
| 7224 | { |
| 7225 | u16 cl37_val; |
| 7226 | struct bnx2x *bp = params->bp; |
| 7227 | bnx2x_cl45_read(bp, phy, |
| 7228 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); |
| 7229 | |
| 7230 | cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; |
| 7231 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ |
| 7232 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); |
| 7233 | if ((vars->ieee_fc & |
| 7234 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == |
| 7235 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { |
| 7236 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; |
| 7237 | } |
| 7238 | if ((vars->ieee_fc & |
| 7239 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == |
| 7240 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { |
| 7241 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; |
| 7242 | } |
| 7243 | if ((vars->ieee_fc & |
| 7244 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == |
| 7245 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { |
| 7246 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; |
| 7247 | } |
| 7248 | DP(NETIF_MSG_LINK, |
| 7249 | "Ext phy AN advertize cl37 0x%x\n", cl37_val); |
| 7250 | |
| 7251 | bnx2x_cl45_write(bp, phy, |
| 7252 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); |
| 7253 | msleep(500); |
| 7254 | } |
| 7255 | |
Yaniv Rosner | 5c107fd | 2012-09-13 02:56:19 +0000 | [diff] [blame] | 7256 | static void bnx2x_8073_specific_func(struct bnx2x_phy *phy, |
| 7257 | struct link_params *params, |
| 7258 | u32 action) |
| 7259 | { |
| 7260 | struct bnx2x *bp = params->bp; |
| 7261 | switch (action) { |
| 7262 | case PHY_INIT: |
| 7263 | /* Enable LASI */ |
| 7264 | bnx2x_cl45_write(bp, phy, |
| 7265 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); |
| 7266 | bnx2x_cl45_write(bp, phy, |
| 7267 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); |
| 7268 | break; |
| 7269 | } |
| 7270 | } |
| 7271 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 7272 | static int bnx2x_8073_config_init(struct bnx2x_phy *phy, |
| 7273 | struct link_params *params, |
| 7274 | struct link_vars *vars) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7275 | { |
| 7276 | struct bnx2x *bp = params->bp; |
| 7277 | u16 val = 0, tmp1; |
| 7278 | u8 gpio_port; |
| 7279 | DP(NETIF_MSG_LINK, "Init 8073\n"); |
| 7280 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7281 | if (CHIP_IS_E2(bp)) |
| 7282 | gpio_port = BP_PATH(bp); |
| 7283 | else |
| 7284 | gpio_port = params->port; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7285 | /* Restore normal power mode*/ |
| 7286 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7287 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7288 | |
| 7289 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7290 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7291 | |
Yaniv Rosner | 5c107fd | 2012-09-13 02:56:19 +0000 | [diff] [blame] | 7292 | bnx2x_8073_specific_func(phy, params, PHY_INIT); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7293 | bnx2x_8073_set_pause_cl37(params, phy, vars); |
| 7294 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7295 | bnx2x_cl45_read(bp, phy, |
| 7296 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); |
| 7297 | |
| 7298 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 7299 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7300 | |
| 7301 | DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); |
| 7302 | |
Yaniv Rosner | 74d7a11 | 2011-01-18 04:33:18 +0000 | [diff] [blame] | 7303 | /* Swap polarity if required - Must be done only in non-1G mode */ |
| 7304 | if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { |
| 7305 | /* Configure the 8073 to swap _P and _N of the KR lines */ |
| 7306 | DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n"); |
| 7307 | /* 10G Rx/Tx and 1G Tx signal polarity swap */ |
| 7308 | bnx2x_cl45_read(bp, phy, |
| 7309 | MDIO_PMA_DEVAD, |
| 7310 | MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); |
| 7311 | bnx2x_cl45_write(bp, phy, |
| 7312 | MDIO_PMA_DEVAD, |
| 7313 | MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, |
| 7314 | (val | (3<<9))); |
| 7315 | } |
| 7316 | |
| 7317 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7318 | /* Enable CL37 BAM */ |
Yaniv Rosner | 121839b | 2010-11-01 05:32:38 +0000 | [diff] [blame] | 7319 | if (REG_RD(bp, params->shmem_base + |
| 7320 | offsetof(struct shmem_region, dev_info. |
| 7321 | port_hw_config[params->port].default_cfg)) & |
| 7322 | PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7323 | |
Yaniv Rosner | 121839b | 2010-11-01 05:32:38 +0000 | [diff] [blame] | 7324 | bnx2x_cl45_read(bp, phy, |
| 7325 | MDIO_AN_DEVAD, |
| 7326 | MDIO_AN_REG_8073_BAM, &val); |
| 7327 | bnx2x_cl45_write(bp, phy, |
| 7328 | MDIO_AN_DEVAD, |
| 7329 | MDIO_AN_REG_8073_BAM, val | 1); |
| 7330 | DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); |
| 7331 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7332 | if (params->loopback_mode == LOOPBACK_EXT) { |
| 7333 | bnx2x_807x_force_10G(bp, phy); |
| 7334 | DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); |
| 7335 | return 0; |
| 7336 | } else { |
| 7337 | bnx2x_cl45_write(bp, phy, |
| 7338 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); |
| 7339 | } |
| 7340 | if (phy->req_line_speed != SPEED_AUTO_NEG) { |
| 7341 | if (phy->req_line_speed == SPEED_10000) { |
| 7342 | val = (1<<7); |
| 7343 | } else if (phy->req_line_speed == SPEED_2500) { |
| 7344 | val = (1<<5); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 7345 | /* Note that 2.5G works only when used with 1G |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 7346 | * advertisement |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 7347 | */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7348 | } else |
| 7349 | val = (1<<5); |
| 7350 | } else { |
| 7351 | val = 0; |
| 7352 | if (phy->speed_cap_mask & |
| 7353 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
| 7354 | val |= (1<<7); |
| 7355 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 7356 | /* Note that 2.5G works only when used with 1G advertisement */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7357 | if (phy->speed_cap_mask & |
| 7358 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | |
| 7359 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
| 7360 | val |= (1<<5); |
| 7361 | DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); |
| 7362 | } |
| 7363 | |
| 7364 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); |
| 7365 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); |
| 7366 | |
| 7367 | if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && |
| 7368 | (phy->req_line_speed == SPEED_AUTO_NEG)) || |
| 7369 | (phy->req_line_speed == SPEED_2500)) { |
| 7370 | u16 phy_ver; |
| 7371 | /* Allow 2.5G for A1 and above */ |
| 7372 | bnx2x_cl45_read(bp, phy, |
| 7373 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, |
| 7374 | &phy_ver); |
| 7375 | DP(NETIF_MSG_LINK, "Add 2.5G\n"); |
| 7376 | if (phy_ver > 0) |
| 7377 | tmp1 |= 1; |
| 7378 | else |
| 7379 | tmp1 &= 0xfffe; |
| 7380 | } else { |
| 7381 | DP(NETIF_MSG_LINK, "Disable 2.5G\n"); |
| 7382 | tmp1 &= 0xfffe; |
| 7383 | } |
| 7384 | |
| 7385 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); |
| 7386 | /* Add support for CL37 (passive mode) II */ |
| 7387 | |
| 7388 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); |
| 7389 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, |
| 7390 | (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? |
| 7391 | 0x20 : 0x40))); |
| 7392 | |
| 7393 | /* Add support for CL37 (passive mode) III */ |
| 7394 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); |
| 7395 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 7396 | /* The SNR will improve about 2db by changing BW and FEE main |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 7397 | * tap. Rest commands are executed after link is up |
| 7398 | * Change FFE main cursor to 5 in EDC register |
| 7399 | */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7400 | if (bnx2x_8073_is_snr_needed(bp, phy)) |
| 7401 | bnx2x_cl45_write(bp, phy, |
| 7402 | MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, |
| 7403 | 0xFB0C); |
| 7404 | |
| 7405 | /* Enable FEC (Forware Error Correction) Request in the AN */ |
| 7406 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); |
| 7407 | tmp1 |= (1<<15); |
| 7408 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); |
| 7409 | |
| 7410 | bnx2x_ext_phy_set_pause(params, phy, vars); |
| 7411 | |
| 7412 | /* Restart autoneg */ |
| 7413 | msleep(500); |
| 7414 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); |
| 7415 | DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", |
| 7416 | ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); |
| 7417 | return 0; |
| 7418 | } |
| 7419 | |
| 7420 | static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, |
| 7421 | struct link_params *params, |
| 7422 | struct link_vars *vars) |
| 7423 | { |
| 7424 | struct bnx2x *bp = params->bp; |
| 7425 | u8 link_up = 0; |
| 7426 | u16 val1, val2; |
| 7427 | u16 link_status = 0; |
| 7428 | u16 an1000_status = 0; |
| 7429 | |
| 7430 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 7431 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7432 | |
| 7433 | DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); |
| 7434 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 7435 | /* Clear the interrupt LASI status register */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7436 | bnx2x_cl45_read(bp, phy, |
| 7437 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); |
| 7438 | bnx2x_cl45_read(bp, phy, |
| 7439 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); |
| 7440 | DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); |
| 7441 | /* Clear MSG-OUT */ |
| 7442 | bnx2x_cl45_read(bp, phy, |
| 7443 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); |
| 7444 | |
| 7445 | /* Check the LASI */ |
| 7446 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 7447 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7448 | |
| 7449 | DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); |
| 7450 | |
| 7451 | /* Check the link status */ |
| 7452 | bnx2x_cl45_read(bp, phy, |
| 7453 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); |
| 7454 | DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); |
| 7455 | |
| 7456 | bnx2x_cl45_read(bp, phy, |
| 7457 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); |
| 7458 | bnx2x_cl45_read(bp, phy, |
| 7459 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); |
| 7460 | link_up = ((val1 & 4) == 4); |
| 7461 | DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); |
| 7462 | |
| 7463 | if (link_up && |
| 7464 | ((phy->req_line_speed != SPEED_10000))) { |
| 7465 | if (bnx2x_8073_xaui_wa(bp, phy) != 0) |
| 7466 | return 0; |
| 7467 | } |
| 7468 | bnx2x_cl45_read(bp, phy, |
| 7469 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); |
| 7470 | bnx2x_cl45_read(bp, phy, |
| 7471 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); |
| 7472 | |
| 7473 | /* Check the link status on 1.1.2 */ |
| 7474 | bnx2x_cl45_read(bp, phy, |
| 7475 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); |
| 7476 | bnx2x_cl45_read(bp, phy, |
| 7477 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); |
| 7478 | DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," |
| 7479 | "an_link_status=0x%x\n", val2, val1, an1000_status); |
| 7480 | |
| 7481 | link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); |
| 7482 | if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 7483 | /* The SNR will improve about 2dbby changing the BW and FEE main |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 7484 | * tap. The 1st write to change FFE main tap is set before |
| 7485 | * restart AN. Change PLL Bandwidth in EDC register |
| 7486 | */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7487 | bnx2x_cl45_write(bp, phy, |
| 7488 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, |
| 7489 | 0x26BC); |
| 7490 | |
| 7491 | /* Change CDR Bandwidth in EDC register */ |
| 7492 | bnx2x_cl45_write(bp, phy, |
| 7493 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, |
| 7494 | 0x0333); |
| 7495 | } |
| 7496 | bnx2x_cl45_read(bp, phy, |
| 7497 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, |
| 7498 | &link_status); |
| 7499 | |
| 7500 | /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ |
| 7501 | if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { |
| 7502 | link_up = 1; |
| 7503 | vars->line_speed = SPEED_10000; |
| 7504 | DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", |
| 7505 | params->port); |
| 7506 | } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { |
| 7507 | link_up = 1; |
| 7508 | vars->line_speed = SPEED_2500; |
| 7509 | DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", |
| 7510 | params->port); |
| 7511 | } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { |
| 7512 | link_up = 1; |
| 7513 | vars->line_speed = SPEED_1000; |
| 7514 | DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", |
| 7515 | params->port); |
| 7516 | } else { |
| 7517 | link_up = 0; |
| 7518 | DP(NETIF_MSG_LINK, "port %x: External link is down\n", |
| 7519 | params->port); |
| 7520 | } |
| 7521 | |
| 7522 | if (link_up) { |
Yaniv Rosner | 74d7a11 | 2011-01-18 04:33:18 +0000 | [diff] [blame] | 7523 | /* Swap polarity if required */ |
| 7524 | if (params->lane_config & |
| 7525 | PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { |
| 7526 | /* Configure the 8073 to swap P and N of the KR lines */ |
| 7527 | bnx2x_cl45_read(bp, phy, |
| 7528 | MDIO_XS_DEVAD, |
| 7529 | MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 7530 | /* Set bit 3 to invert Rx in 1G mode and clear this bit |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 7531 | * when it`s in 10G mode. |
| 7532 | */ |
Yaniv Rosner | 74d7a11 | 2011-01-18 04:33:18 +0000 | [diff] [blame] | 7533 | if (vars->line_speed == SPEED_1000) { |
| 7534 | DP(NETIF_MSG_LINK, "Swapping 1G polarity for" |
| 7535 | "the 8073\n"); |
| 7536 | val1 |= (1<<3); |
| 7537 | } else |
| 7538 | val1 &= ~(1<<3); |
| 7539 | |
| 7540 | bnx2x_cl45_write(bp, phy, |
| 7541 | MDIO_XS_DEVAD, |
| 7542 | MDIO_XS_REG_8073_RX_CTRL_PCIE, |
| 7543 | val1); |
| 7544 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7545 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); |
| 7546 | bnx2x_8073_resolve_fc(phy, params, vars); |
Yaniv Rosner | 791f18c | 2011-01-18 04:33:42 +0000 | [diff] [blame] | 7547 | vars->duplex = DUPLEX_FULL; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7548 | } |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 7549 | |
| 7550 | if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { |
| 7551 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, |
| 7552 | MDIO_AN_REG_LP_AUTO_NEG2, &val1); |
| 7553 | |
| 7554 | if (val1 & (1<<5)) |
| 7555 | vars->link_status |= |
| 7556 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; |
| 7557 | if (val1 & (1<<7)) |
| 7558 | vars->link_status |= |
| 7559 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; |
| 7560 | } |
| 7561 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7562 | return link_up; |
| 7563 | } |
| 7564 | |
| 7565 | static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, |
| 7566 | struct link_params *params) |
| 7567 | { |
| 7568 | struct bnx2x *bp = params->bp; |
| 7569 | u8 gpio_port; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7570 | if (CHIP_IS_E2(bp)) |
| 7571 | gpio_port = BP_PATH(bp); |
| 7572 | else |
| 7573 | gpio_port = params->port; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7574 | DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", |
| 7575 | gpio_port); |
| 7576 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7577 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
| 7578 | gpio_port); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7579 | } |
| 7580 | |
| 7581 | /******************************************************************/ |
| 7582 | /* BCM8705 PHY SECTION */ |
| 7583 | /******************************************************************/ |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 7584 | static int bnx2x_8705_config_init(struct bnx2x_phy *phy, |
| 7585 | struct link_params *params, |
| 7586 | struct link_vars *vars) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7587 | { |
| 7588 | struct bnx2x *bp = params->bp; |
| 7589 | DP(NETIF_MSG_LINK, "init 8705\n"); |
| 7590 | /* Restore normal power mode*/ |
| 7591 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7592 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7593 | /* HW reset */ |
| 7594 | bnx2x_ext_phy_hw_reset(bp, params->port); |
| 7595 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); |
Yaniv Rosner | 6d870c3 | 2011-01-31 04:22:20 +0000 | [diff] [blame] | 7596 | bnx2x_wait_reset_complete(bp, phy, params); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7597 | |
| 7598 | bnx2x_cl45_write(bp, phy, |
| 7599 | MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); |
| 7600 | bnx2x_cl45_write(bp, phy, |
| 7601 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); |
| 7602 | bnx2x_cl45_write(bp, phy, |
| 7603 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); |
| 7604 | bnx2x_cl45_write(bp, phy, |
| 7605 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); |
| 7606 | /* BCM8705 doesn't have microcode, hence the 0 */ |
| 7607 | bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); |
| 7608 | return 0; |
| 7609 | } |
| 7610 | |
| 7611 | static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, |
| 7612 | struct link_params *params, |
| 7613 | struct link_vars *vars) |
| 7614 | { |
| 7615 | u8 link_up = 0; |
| 7616 | u16 val1, rx_sd; |
| 7617 | struct bnx2x *bp = params->bp; |
| 7618 | DP(NETIF_MSG_LINK, "read status 8705\n"); |
| 7619 | bnx2x_cl45_read(bp, phy, |
| 7620 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); |
| 7621 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); |
| 7622 | |
| 7623 | bnx2x_cl45_read(bp, phy, |
| 7624 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); |
| 7625 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); |
| 7626 | |
| 7627 | bnx2x_cl45_read(bp, phy, |
| 7628 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); |
| 7629 | |
| 7630 | bnx2x_cl45_read(bp, phy, |
| 7631 | MDIO_PMA_DEVAD, 0xc809, &val1); |
| 7632 | bnx2x_cl45_read(bp, phy, |
| 7633 | MDIO_PMA_DEVAD, 0xc809, &val1); |
| 7634 | |
| 7635 | DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); |
| 7636 | link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); |
| 7637 | if (link_up) { |
| 7638 | vars->line_speed = SPEED_10000; |
| 7639 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
| 7640 | } |
| 7641 | return link_up; |
| 7642 | } |
| 7643 | |
| 7644 | /******************************************************************/ |
| 7645 | /* SFP+ module Section */ |
| 7646 | /******************************************************************/ |
Yaniv Rosner | 85242ee | 2011-07-05 01:06:53 +0000 | [diff] [blame] | 7647 | static void bnx2x_set_disable_pmd_transmit(struct link_params *params, |
| 7648 | struct bnx2x_phy *phy, |
| 7649 | u8 pmd_dis) |
| 7650 | { |
| 7651 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 7652 | /* Disable transmitter only for bootcodes which can enable it afterwards |
Yaniv Rosner | 85242ee | 2011-07-05 01:06:53 +0000 | [diff] [blame] | 7653 | * (for D3 link) |
| 7654 | */ |
| 7655 | if (pmd_dis) { |
| 7656 | if (params->feature_config_flags & |
| 7657 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) |
| 7658 | DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n"); |
| 7659 | else { |
| 7660 | DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n"); |
| 7661 | return; |
| 7662 | } |
| 7663 | } else |
| 7664 | DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n"); |
| 7665 | bnx2x_cl45_write(bp, phy, |
| 7666 | MDIO_PMA_DEVAD, |
| 7667 | MDIO_PMA_REG_TX_DISABLE, pmd_dis); |
| 7668 | } |
| 7669 | |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 7670 | static u8 bnx2x_get_gpio_port(struct link_params *params) |
| 7671 | { |
| 7672 | u8 gpio_port; |
| 7673 | u32 swap_val, swap_override; |
| 7674 | struct bnx2x *bp = params->bp; |
| 7675 | if (CHIP_IS_E2(bp)) |
| 7676 | gpio_port = BP_PATH(bp); |
| 7677 | else |
| 7678 | gpio_port = params->port; |
| 7679 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); |
| 7680 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); |
| 7681 | return gpio_port ^ (swap_val && swap_override); |
| 7682 | } |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 7683 | |
| 7684 | static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params, |
| 7685 | struct bnx2x_phy *phy, |
| 7686 | u8 tx_en) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7687 | { |
| 7688 | u16 val; |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 7689 | u8 port = params->port; |
| 7690 | struct bnx2x *bp = params->bp; |
| 7691 | u32 tx_en_mode; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7692 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7693 | /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 7694 | tx_en_mode = REG_RD(bp, params->shmem_base + |
| 7695 | offsetof(struct shmem_region, |
| 7696 | dev_info.port_hw_config[port].sfp_ctrl)) & |
| 7697 | PORT_HW_CFG_TX_LASER_MASK; |
| 7698 | DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x " |
| 7699 | "mode = %x\n", tx_en, port, tx_en_mode); |
| 7700 | switch (tx_en_mode) { |
| 7701 | case PORT_HW_CFG_TX_LASER_MDIO: |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7702 | |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 7703 | bnx2x_cl45_read(bp, phy, |
| 7704 | MDIO_PMA_DEVAD, |
| 7705 | MDIO_PMA_REG_PHY_IDENTIFIER, |
| 7706 | &val); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7707 | |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 7708 | if (tx_en) |
| 7709 | val &= ~(1<<15); |
| 7710 | else |
| 7711 | val |= (1<<15); |
| 7712 | |
| 7713 | bnx2x_cl45_write(bp, phy, |
| 7714 | MDIO_PMA_DEVAD, |
| 7715 | MDIO_PMA_REG_PHY_IDENTIFIER, |
| 7716 | val); |
| 7717 | break; |
| 7718 | case PORT_HW_CFG_TX_LASER_GPIO0: |
| 7719 | case PORT_HW_CFG_TX_LASER_GPIO1: |
| 7720 | case PORT_HW_CFG_TX_LASER_GPIO2: |
| 7721 | case PORT_HW_CFG_TX_LASER_GPIO3: |
| 7722 | { |
| 7723 | u16 gpio_pin; |
| 7724 | u8 gpio_port, gpio_mode; |
| 7725 | if (tx_en) |
| 7726 | gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; |
| 7727 | else |
| 7728 | gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; |
| 7729 | |
| 7730 | gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; |
| 7731 | gpio_port = bnx2x_get_gpio_port(params); |
| 7732 | bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); |
| 7733 | break; |
| 7734 | } |
| 7735 | default: |
| 7736 | DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); |
| 7737 | break; |
| 7738 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7739 | } |
| 7740 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 7741 | static void bnx2x_sfp_set_transmitter(struct link_params *params, |
| 7742 | struct bnx2x_phy *phy, |
| 7743 | u8 tx_en) |
| 7744 | { |
| 7745 | struct bnx2x *bp = params->bp; |
| 7746 | DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en); |
| 7747 | if (CHIP_IS_E3(bp)) |
| 7748 | bnx2x_sfp_e3_set_transmitter(params, phy, tx_en); |
| 7749 | else |
| 7750 | bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en); |
| 7751 | } |
| 7752 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 7753 | static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
| 7754 | struct link_params *params, |
| 7755 | u16 addr, u8 byte_cnt, u8 *o_buf) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7756 | { |
| 7757 | struct bnx2x *bp = params->bp; |
| 7758 | u16 val = 0; |
| 7759 | u16 i; |
Yuval Mintz | 24ea818 | 2012-06-20 19:05:23 +0000 | [diff] [blame] | 7760 | if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 7761 | DP(NETIF_MSG_LINK, |
| 7762 | "Reading from eeprom is limited to 0xf\n"); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7763 | return -EINVAL; |
| 7764 | } |
| 7765 | /* Set the read command byte count */ |
| 7766 | bnx2x_cl45_write(bp, phy, |
| 7767 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7768 | (byte_cnt | 0xa000)); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7769 | |
| 7770 | /* Set the read command address */ |
| 7771 | bnx2x_cl45_write(bp, phy, |
| 7772 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7773 | addr); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7774 | |
| 7775 | /* Activate read command */ |
| 7776 | bnx2x_cl45_write(bp, phy, |
| 7777 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7778 | 0x2c0f); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7779 | |
| 7780 | /* Wait up to 500us for command complete status */ |
| 7781 | for (i = 0; i < 100; i++) { |
| 7782 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7783 | MDIO_PMA_DEVAD, |
| 7784 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7785 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
| 7786 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) |
| 7787 | break; |
| 7788 | udelay(5); |
| 7789 | } |
| 7790 | |
| 7791 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != |
| 7792 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { |
| 7793 | DP(NETIF_MSG_LINK, |
| 7794 | "Got bad status 0x%x when reading from SFP+ EEPROM\n", |
| 7795 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); |
| 7796 | return -EINVAL; |
| 7797 | } |
| 7798 | |
| 7799 | /* Read the buffer */ |
| 7800 | for (i = 0; i < byte_cnt; i++) { |
| 7801 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7802 | MDIO_PMA_DEVAD, |
| 7803 | MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7804 | o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); |
| 7805 | } |
| 7806 | |
| 7807 | for (i = 0; i < 100; i++) { |
| 7808 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7809 | MDIO_PMA_DEVAD, |
| 7810 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7811 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
| 7812 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) |
Joe Perches | 6f38ad9 | 2010-11-14 17:04:31 +0000 | [diff] [blame] | 7813 | return 0; |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 7814 | usleep_range(1000, 2000); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7815 | } |
| 7816 | return -EINVAL; |
| 7817 | } |
| 7818 | |
Yuval Mintz | 50a2984 | 2012-06-16 20:27:14 +0000 | [diff] [blame] | 7819 | static void bnx2x_warpcore_power_module(struct link_params *params, |
Yuval Mintz | 50a2984 | 2012-06-16 20:27:14 +0000 | [diff] [blame] | 7820 | u8 power) |
| 7821 | { |
| 7822 | u32 pin_cfg; |
| 7823 | struct bnx2x *bp = params->bp; |
| 7824 | |
| 7825 | pin_cfg = (REG_RD(bp, params->shmem_base + |
| 7826 | offsetof(struct shmem_region, |
| 7827 | dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & |
| 7828 | PORT_HW_CFG_E3_PWR_DIS_MASK) >> |
| 7829 | PORT_HW_CFG_E3_PWR_DIS_SHIFT; |
| 7830 | |
| 7831 | if (pin_cfg == PIN_CFG_NA) |
| 7832 | return; |
| 7833 | DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n", |
| 7834 | power, pin_cfg); |
| 7835 | /* Low ==> corresponding SFP+ module is powered |
| 7836 | * high ==> the SFP+ module is powered down |
| 7837 | */ |
| 7838 | bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); |
| 7839 | } |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 7840 | static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
| 7841 | struct link_params *params, |
| 7842 | u16 addr, u8 byte_cnt, |
Yaniv Rosner | e82041d | 2012-10-31 05:46:56 +0000 | [diff] [blame] | 7843 | u8 *o_buf, u8 is_init) |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 7844 | { |
| 7845 | int rc = 0; |
| 7846 | u8 i, j = 0, cnt = 0; |
| 7847 | u32 data_array[4]; |
| 7848 | u16 addr32; |
| 7849 | struct bnx2x *bp = params->bp; |
Yuval Mintz | 24ea818 | 2012-06-20 19:05:23 +0000 | [diff] [blame] | 7850 | |
| 7851 | if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 7852 | DP(NETIF_MSG_LINK, |
| 7853 | "Reading from eeprom is limited to 16 bytes\n"); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 7854 | return -EINVAL; |
| 7855 | } |
| 7856 | |
| 7857 | /* 4 byte aligned address */ |
| 7858 | addr32 = addr & (~0x3); |
| 7859 | do { |
Yaniv Rosner | e82041d | 2012-10-31 05:46:56 +0000 | [diff] [blame] | 7860 | if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) { |
Yaniv Rosner | 5a1fbf4 | 2012-11-27 03:46:31 +0000 | [diff] [blame] | 7861 | bnx2x_warpcore_power_module(params, 0); |
Yuval Mintz | 50a2984 | 2012-06-16 20:27:14 +0000 | [diff] [blame] | 7862 | /* Note that 100us are not enough here */ |
Yaniv Rosner | e82041d | 2012-10-31 05:46:56 +0000 | [diff] [blame] | 7863 | usleep_range(1000, 2000); |
Yaniv Rosner | 5a1fbf4 | 2012-11-27 03:46:31 +0000 | [diff] [blame] | 7864 | bnx2x_warpcore_power_module(params, 1); |
Yuval Mintz | 50a2984 | 2012-06-16 20:27:14 +0000 | [diff] [blame] | 7865 | } |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 7866 | rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt, |
| 7867 | data_array); |
| 7868 | } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT)); |
| 7869 | |
| 7870 | if (rc == 0) { |
| 7871 | for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { |
| 7872 | o_buf[j] = *((u8 *)data_array + i); |
| 7873 | j++; |
| 7874 | } |
| 7875 | } |
| 7876 | |
| 7877 | return rc; |
| 7878 | } |
| 7879 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 7880 | static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
| 7881 | struct link_params *params, |
| 7882 | u16 addr, u8 byte_cnt, u8 *o_buf) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7883 | { |
| 7884 | struct bnx2x *bp = params->bp; |
| 7885 | u16 val, i; |
| 7886 | |
Yuval Mintz | 24ea818 | 2012-06-20 19:05:23 +0000 | [diff] [blame] | 7887 | if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 7888 | DP(NETIF_MSG_LINK, |
| 7889 | "Reading from eeprom is limited to 0xf\n"); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7890 | return -EINVAL; |
| 7891 | } |
| 7892 | |
| 7893 | /* Need to read from 1.8000 to clear it */ |
| 7894 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7895 | MDIO_PMA_DEVAD, |
| 7896 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, |
| 7897 | &val); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7898 | |
| 7899 | /* Set the read command byte count */ |
| 7900 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7901 | MDIO_PMA_DEVAD, |
| 7902 | MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, |
| 7903 | ((byte_cnt < 2) ? 2 : byte_cnt)); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7904 | |
| 7905 | /* Set the read command address */ |
| 7906 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7907 | MDIO_PMA_DEVAD, |
| 7908 | MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, |
| 7909 | addr); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7910 | /* Set the destination address */ |
| 7911 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7912 | MDIO_PMA_DEVAD, |
| 7913 | 0x8004, |
| 7914 | MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7915 | |
| 7916 | /* Activate read command */ |
| 7917 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7918 | MDIO_PMA_DEVAD, |
| 7919 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, |
| 7920 | 0x8002); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 7921 | /* Wait appropriate time for two-wire command to finish before |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 7922 | * polling the status register |
| 7923 | */ |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 7924 | usleep_range(1000, 2000); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7925 | |
| 7926 | /* Wait up to 500us for command complete status */ |
| 7927 | for (i = 0; i < 100; i++) { |
| 7928 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7929 | MDIO_PMA_DEVAD, |
| 7930 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7931 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
| 7932 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) |
| 7933 | break; |
| 7934 | udelay(5); |
| 7935 | } |
| 7936 | |
| 7937 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != |
| 7938 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { |
| 7939 | DP(NETIF_MSG_LINK, |
| 7940 | "Got bad status 0x%x when reading from SFP+ EEPROM\n", |
| 7941 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); |
Yaniv Rosner | 65a001b | 2011-01-31 04:22:03 +0000 | [diff] [blame] | 7942 | return -EFAULT; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7943 | } |
| 7944 | |
| 7945 | /* Read the buffer */ |
| 7946 | for (i = 0; i < byte_cnt; i++) { |
| 7947 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7948 | MDIO_PMA_DEVAD, |
| 7949 | MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7950 | o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); |
| 7951 | } |
| 7952 | |
| 7953 | for (i = 0; i < 100; i++) { |
| 7954 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 7955 | MDIO_PMA_DEVAD, |
| 7956 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7957 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
| 7958 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) |
Joe Perches | 6f38ad9 | 2010-11-14 17:04:31 +0000 | [diff] [blame] | 7959 | return 0; |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 7960 | usleep_range(1000, 2000); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7961 | } |
| 7962 | |
| 7963 | return -EINVAL; |
| 7964 | } |
| 7965 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 7966 | int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
| 7967 | struct link_params *params, u16 addr, |
| 7968 | u8 byte_cnt, u8 *o_buf) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7969 | { |
Yuval Mintz | 24ea818 | 2012-06-20 19:05:23 +0000 | [diff] [blame] | 7970 | int rc = -EOPNOTSUPP; |
Yaniv Rosner | e4d78f1 | 2011-05-31 21:25:55 +0000 | [diff] [blame] | 7971 | switch (phy->type) { |
| 7972 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: |
| 7973 | rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr, |
| 7974 | byte_cnt, o_buf); |
| 7975 | break; |
| 7976 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
| 7977 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: |
| 7978 | rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr, |
| 7979 | byte_cnt, o_buf); |
| 7980 | break; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 7981 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
| 7982 | rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr, |
Yaniv Rosner | e82041d | 2012-10-31 05:46:56 +0000 | [diff] [blame] | 7983 | byte_cnt, o_buf, 0); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 7984 | break; |
Yaniv Rosner | e4d78f1 | 2011-05-31 21:25:55 +0000 | [diff] [blame] | 7985 | } |
| 7986 | return rc; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7987 | } |
| 7988 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 7989 | static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, |
| 7990 | struct link_params *params, |
| 7991 | u16 *edc_mode) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7992 | { |
| 7993 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 1ac9e42 | 2011-05-31 21:26:11 +0000 | [diff] [blame] | 7994 | u32 sync_offset = 0, phy_idx, media_types; |
Yaniv Rosner | 52160da | 2012-11-27 03:46:35 +0000 | [diff] [blame] | 7995 | u8 gport, val[2], check_limiting_mode = 0; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7996 | *edc_mode = EDC_MODE_LIMITING; |
Yaniv Rosner | 1ac9e42 | 2011-05-31 21:26:11 +0000 | [diff] [blame] | 7997 | phy->media_type = ETH_PHY_UNSPECIFIED; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 7998 | /* First check for copper cable */ |
| 7999 | if (bnx2x_read_sfp_module_eeprom(phy, |
| 8000 | params, |
| 8001 | SFP_EEPROM_CON_TYPE_ADDR, |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 8002 | 2, |
| 8003 | (u8 *)val) != 0) { |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8004 | DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); |
| 8005 | return -EINVAL; |
| 8006 | } |
| 8007 | |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 8008 | switch (val[0]) { |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8009 | case SFP_EEPROM_CON_TYPE_VAL_COPPER: |
| 8010 | { |
| 8011 | u8 copper_module_type; |
Yaniv Rosner | 1ac9e42 | 2011-05-31 21:26:11 +0000 | [diff] [blame] | 8012 | phy->media_type = ETH_PHY_DA_TWINAX; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 8013 | /* Check if its active cable (includes SFP+ module) |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 8014 | * of passive cable |
| 8015 | */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8016 | if (bnx2x_read_sfp_module_eeprom(phy, |
| 8017 | params, |
| 8018 | SFP_EEPROM_FC_TX_TECH_ADDR, |
| 8019 | 1, |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 8020 | &copper_module_type) != 0) { |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8021 | DP(NETIF_MSG_LINK, |
| 8022 | "Failed to read copper-cable-type" |
| 8023 | " from SFP+ EEPROM\n"); |
| 8024 | return -EINVAL; |
| 8025 | } |
| 8026 | |
| 8027 | if (copper_module_type & |
| 8028 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { |
| 8029 | DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); |
| 8030 | check_limiting_mode = 1; |
| 8031 | } else if (copper_module_type & |
| 8032 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 8033 | DP(NETIF_MSG_LINK, |
| 8034 | "Passive Copper cable detected\n"); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8035 | *edc_mode = |
| 8036 | EDC_MODE_PASSIVE_DAC; |
| 8037 | } else { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 8038 | DP(NETIF_MSG_LINK, |
| 8039 | "Unknown copper-cable-type 0x%x !!!\n", |
| 8040 | copper_module_type); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8041 | return -EINVAL; |
| 8042 | } |
| 8043 | break; |
| 8044 | } |
| 8045 | case SFP_EEPROM_CON_TYPE_VAL_LC: |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8046 | check_limiting_mode = 1; |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 8047 | if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK | |
| 8048 | SFP_EEPROM_COMP_CODE_LR_MASK | |
| 8049 | SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) { |
| 8050 | DP(NETIF_MSG_LINK, "1G Optic module detected\n"); |
Yaniv Rosner | 52160da | 2012-11-27 03:46:35 +0000 | [diff] [blame] | 8051 | gport = params->port; |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 8052 | phy->media_type = ETH_PHY_SFP_1G_FIBER; |
| 8053 | phy->req_line_speed = SPEED_1000; |
Yaniv Rosner | 52160da | 2012-11-27 03:46:35 +0000 | [diff] [blame] | 8054 | if (!CHIP_IS_E1x(bp)) |
| 8055 | gport = BP_PATH(bp) + (params->port << 1); |
| 8056 | netdev_err(bp->dev, "Warning: Link speed was forced to 1000Mbps." |
| 8057 | " Current SFP module in port %d is not" |
| 8058 | " compliant with 10G Ethernet\n", |
| 8059 | gport); |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 8060 | } else { |
| 8061 | int idx, cfg_idx = 0; |
| 8062 | DP(NETIF_MSG_LINK, "10G Optic module detected\n"); |
| 8063 | for (idx = INT_PHY; idx < MAX_PHYS; idx++) { |
| 8064 | if (params->phy[idx].type == phy->type) { |
| 8065 | cfg_idx = LINK_CONFIG_IDX(idx); |
| 8066 | break; |
| 8067 | } |
| 8068 | } |
| 8069 | phy->media_type = ETH_PHY_SFPP_10G_FIBER; |
| 8070 | phy->req_line_speed = params->req_line_speed[cfg_idx]; |
| 8071 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8072 | break; |
| 8073 | default: |
| 8074 | DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 8075 | val[0]); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8076 | return -EINVAL; |
| 8077 | } |
Yaniv Rosner | 1ac9e42 | 2011-05-31 21:26:11 +0000 | [diff] [blame] | 8078 | sync_offset = params->shmem_base + |
| 8079 | offsetof(struct shmem_region, |
| 8080 | dev_info.port_hw_config[params->port].media_type); |
| 8081 | media_types = REG_RD(bp, sync_offset); |
| 8082 | /* Update media type for non-PMF sync */ |
| 8083 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { |
| 8084 | if (&(params->phy[phy_idx]) == phy) { |
| 8085 | media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << |
| 8086 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); |
| 8087 | media_types |= ((phy->media_type & |
| 8088 | PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << |
| 8089 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); |
| 8090 | break; |
| 8091 | } |
| 8092 | } |
| 8093 | REG_WR(bp, sync_offset, media_types); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8094 | if (check_limiting_mode) { |
| 8095 | u8 options[SFP_EEPROM_OPTIONS_SIZE]; |
| 8096 | if (bnx2x_read_sfp_module_eeprom(phy, |
| 8097 | params, |
| 8098 | SFP_EEPROM_OPTIONS_ADDR, |
| 8099 | SFP_EEPROM_OPTIONS_SIZE, |
| 8100 | options) != 0) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 8101 | DP(NETIF_MSG_LINK, |
| 8102 | "Failed to read Option field from module EEPROM\n"); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8103 | return -EINVAL; |
| 8104 | } |
| 8105 | if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) |
| 8106 | *edc_mode = EDC_MODE_LINEAR; |
| 8107 | else |
| 8108 | *edc_mode = EDC_MODE_LIMITING; |
| 8109 | } |
| 8110 | DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); |
| 8111 | return 0; |
| 8112 | } |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 8113 | /* This function read the relevant field from the module (SFP+), and verify it |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 8114 | * is compliant with this board |
| 8115 | */ |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 8116 | static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, |
| 8117 | struct link_params *params) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8118 | { |
| 8119 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 8120 | u32 val, cmd; |
| 8121 | u32 fw_resp, fw_cmd_param; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8122 | char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1]; |
| 8123 | char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1]; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 8124 | phy->flags &= ~FLAGS_SFP_NOT_APPROVED; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8125 | val = REG_RD(bp, params->shmem_base + |
| 8126 | offsetof(struct shmem_region, dev_info. |
| 8127 | port_feature_config[params->port].config)); |
| 8128 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == |
| 8129 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { |
| 8130 | DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); |
| 8131 | return 0; |
| 8132 | } |
| 8133 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 8134 | if (params->feature_config_flags & |
| 8135 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { |
| 8136 | /* Use specific phy request */ |
| 8137 | cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; |
| 8138 | } else if (params->feature_config_flags & |
| 8139 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { |
| 8140 | /* Use first phy request only in case of non-dual media*/ |
| 8141 | if (DUAL_MEDIA(params)) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 8142 | DP(NETIF_MSG_LINK, |
| 8143 | "FW does not support OPT MDL verification\n"); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 8144 | return -EINVAL; |
| 8145 | } |
| 8146 | cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; |
| 8147 | } else { |
| 8148 | /* No support in OPT MDL detection */ |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 8149 | DP(NETIF_MSG_LINK, |
| 8150 | "FW does not support OPT MDL verification\n"); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8151 | return -EINVAL; |
| 8152 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8153 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 8154 | fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); |
| 8155 | fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8156 | if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { |
| 8157 | DP(NETIF_MSG_LINK, "Approved module\n"); |
| 8158 | return 0; |
| 8159 | } |
| 8160 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 8161 | /* Format the warning message */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8162 | if (bnx2x_read_sfp_module_eeprom(phy, |
| 8163 | params, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8164 | SFP_EEPROM_VENDOR_NAME_ADDR, |
| 8165 | SFP_EEPROM_VENDOR_NAME_SIZE, |
| 8166 | (u8 *)vendor_name)) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8167 | vendor_name[0] = '\0'; |
| 8168 | else |
| 8169 | vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; |
| 8170 | if (bnx2x_read_sfp_module_eeprom(phy, |
| 8171 | params, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8172 | SFP_EEPROM_PART_NO_ADDR, |
| 8173 | SFP_EEPROM_PART_NO_SIZE, |
| 8174 | (u8 *)vendor_pn)) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8175 | vendor_pn[0] = '\0'; |
| 8176 | else |
| 8177 | vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; |
| 8178 | |
Yaniv Rosner | 6d870c3 | 2011-01-31 04:22:20 +0000 | [diff] [blame] | 8179 | netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," |
| 8180 | " Port %d from %s part number %s\n", |
| 8181 | params->port, vendor_name, vendor_pn); |
Yaniv Rosner | 59a2e53 | 2012-04-04 01:28:59 +0000 | [diff] [blame] | 8182 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != |
| 8183 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) |
| 8184 | phy->flags |= FLAGS_SFP_NOT_APPROVED; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8185 | return -EINVAL; |
| 8186 | } |
| 8187 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 8188 | static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, |
| 8189 | struct link_params *params) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8190 | |
| 8191 | { |
| 8192 | u8 val; |
Yaniv Rosner | e82041d | 2012-10-31 05:46:56 +0000 | [diff] [blame] | 8193 | int rc; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8194 | struct bnx2x *bp = params->bp; |
| 8195 | u16 timeout; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 8196 | /* Initialization time after hot-plug may take up to 300ms for |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 8197 | * some phys type ( e.g. JDSU ) |
| 8198 | */ |
| 8199 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8200 | for (timeout = 0; timeout < 60; timeout++) { |
Yaniv Rosner | e82041d | 2012-10-31 05:46:56 +0000 | [diff] [blame] | 8201 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
| 8202 | rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, |
| 8203 | params, 1, |
| 8204 | 1, &val, 1); |
| 8205 | else |
| 8206 | rc = bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, |
| 8207 | &val); |
| 8208 | if (rc == 0) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 8209 | DP(NETIF_MSG_LINK, |
| 8210 | "SFP+ module initialization took %d ms\n", |
| 8211 | timeout * 5); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8212 | return 0; |
| 8213 | } |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 8214 | usleep_range(5000, 10000); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8215 | } |
Yaniv Rosner | e82041d | 2012-10-31 05:46:56 +0000 | [diff] [blame] | 8216 | rc = bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val); |
| 8217 | return rc; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8218 | } |
| 8219 | |
| 8220 | static void bnx2x_8727_power_module(struct bnx2x *bp, |
| 8221 | struct bnx2x_phy *phy, |
| 8222 | u8 is_power_up) { |
| 8223 | /* Make sure GPIOs are not using for LED mode */ |
| 8224 | u16 val; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 8225 | /* In the GPIO register, bit 4 is use to determine if the GPIOs are |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8226 | * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for |
| 8227 | * output |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8228 | * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 |
| 8229 | * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8230 | * where the 1st bit is the over-current(only input), and 2nd bit is |
| 8231 | * for power( only output ) |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 8232 | * |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8233 | * In case of NOC feature is disabled and power is up, set GPIO control |
| 8234 | * as input to enable listening of over-current indication |
| 8235 | */ |
| 8236 | if (phy->flags & FLAGS_NOC) |
| 8237 | return; |
Yaniv Rosner | 27d0243 | 2011-05-31 21:27:48 +0000 | [diff] [blame] | 8238 | if (is_power_up) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8239 | val = (1<<4); |
| 8240 | else |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 8241 | /* Set GPIO control to OUTPUT, and set the power bit |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8242 | * to according to the is_power_up |
| 8243 | */ |
Yaniv Rosner | 27d0243 | 2011-05-31 21:27:48 +0000 | [diff] [blame] | 8244 | val = (1<<1); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8245 | |
| 8246 | bnx2x_cl45_write(bp, phy, |
| 8247 | MDIO_PMA_DEVAD, |
| 8248 | MDIO_PMA_REG_8727_GPIO_CTRL, |
| 8249 | val); |
| 8250 | } |
| 8251 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 8252 | static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp, |
| 8253 | struct bnx2x_phy *phy, |
| 8254 | u16 edc_mode) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8255 | { |
| 8256 | u16 cur_limiting_mode; |
| 8257 | |
| 8258 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8259 | MDIO_PMA_DEVAD, |
| 8260 | MDIO_PMA_REG_ROM_VER2, |
| 8261 | &cur_limiting_mode); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8262 | DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", |
| 8263 | cur_limiting_mode); |
| 8264 | |
| 8265 | if (edc_mode == EDC_MODE_LIMITING) { |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8266 | DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n"); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8267 | bnx2x_cl45_write(bp, phy, |
| 8268 | MDIO_PMA_DEVAD, |
| 8269 | MDIO_PMA_REG_ROM_VER2, |
| 8270 | EDC_MODE_LIMITING); |
| 8271 | } else { /* LRM mode ( default )*/ |
| 8272 | |
| 8273 | DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); |
| 8274 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 8275 | /* Changing to LRM mode takes quite few seconds. So do it only |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 8276 | * if current mode is limiting (default is LRM) |
| 8277 | */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8278 | if (cur_limiting_mode != EDC_MODE_LIMITING) |
| 8279 | return 0; |
| 8280 | |
| 8281 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8282 | MDIO_PMA_DEVAD, |
| 8283 | MDIO_PMA_REG_LRM_MODE, |
| 8284 | 0); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8285 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8286 | MDIO_PMA_DEVAD, |
| 8287 | MDIO_PMA_REG_ROM_VER2, |
| 8288 | 0x128); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8289 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8290 | MDIO_PMA_DEVAD, |
| 8291 | MDIO_PMA_REG_MISC_CTRL0, |
| 8292 | 0x4008); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8293 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8294 | MDIO_PMA_DEVAD, |
| 8295 | MDIO_PMA_REG_LRM_MODE, |
| 8296 | 0xaaaa); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8297 | } |
| 8298 | return 0; |
| 8299 | } |
| 8300 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 8301 | static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp, |
| 8302 | struct bnx2x_phy *phy, |
| 8303 | u16 edc_mode) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8304 | { |
| 8305 | u16 phy_identifier; |
| 8306 | u16 rom_ver2_val; |
| 8307 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8308 | MDIO_PMA_DEVAD, |
| 8309 | MDIO_PMA_REG_PHY_IDENTIFIER, |
| 8310 | &phy_identifier); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8311 | |
| 8312 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8313 | MDIO_PMA_DEVAD, |
| 8314 | MDIO_PMA_REG_PHY_IDENTIFIER, |
| 8315 | (phy_identifier & ~(1<<9))); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8316 | |
| 8317 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8318 | MDIO_PMA_DEVAD, |
| 8319 | MDIO_PMA_REG_ROM_VER2, |
| 8320 | &rom_ver2_val); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8321 | /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ |
| 8322 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8323 | MDIO_PMA_DEVAD, |
| 8324 | MDIO_PMA_REG_ROM_VER2, |
| 8325 | (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8326 | |
| 8327 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8328 | MDIO_PMA_DEVAD, |
| 8329 | MDIO_PMA_REG_PHY_IDENTIFIER, |
| 8330 | (phy_identifier | (1<<9))); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8331 | |
| 8332 | return 0; |
| 8333 | } |
| 8334 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 8335 | static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, |
| 8336 | struct link_params *params, |
| 8337 | u32 action) |
| 8338 | { |
| 8339 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 5c107fd | 2012-09-13 02:56:19 +0000 | [diff] [blame] | 8340 | u16 val; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 8341 | switch (action) { |
| 8342 | case DISABLE_TX: |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 8343 | bnx2x_sfp_set_transmitter(params, phy, 0); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 8344 | break; |
| 8345 | case ENABLE_TX: |
| 8346 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 8347 | bnx2x_sfp_set_transmitter(params, phy, 1); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 8348 | break; |
Yaniv Rosner | 5c107fd | 2012-09-13 02:56:19 +0000 | [diff] [blame] | 8349 | case PHY_INIT: |
| 8350 | bnx2x_cl45_write(bp, phy, |
| 8351 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
| 8352 | (1<<2) | (1<<5)); |
| 8353 | bnx2x_cl45_write(bp, phy, |
| 8354 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, |
| 8355 | 0); |
| 8356 | bnx2x_cl45_write(bp, phy, |
| 8357 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); |
| 8358 | /* Make MOD_ABS give interrupt on change */ |
| 8359 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
| 8360 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, |
| 8361 | &val); |
| 8362 | val |= (1<<12); |
| 8363 | if (phy->flags & FLAGS_NOC) |
| 8364 | val |= (3<<5); |
| 8365 | /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 |
| 8366 | * status which reflect SFP+ module over-current |
| 8367 | */ |
| 8368 | if (!(phy->flags & FLAGS_NOC)) |
| 8369 | val &= 0xff8f; /* Reset bits 4-6 */ |
| 8370 | bnx2x_cl45_write(bp, phy, |
| 8371 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, |
| 8372 | val); |
| 8373 | |
| 8374 | /* Set 2-wire transfer rate of SFP+ module EEPROM |
| 8375 | * to 100Khz since some DACs(direct attached cables) do |
| 8376 | * not work at 400Khz. |
| 8377 | */ |
| 8378 | bnx2x_cl45_write(bp, phy, |
| 8379 | MDIO_PMA_DEVAD, |
| 8380 | MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, |
| 8381 | 0xa001); |
| 8382 | break; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 8383 | default: |
| 8384 | DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", |
| 8385 | action); |
| 8386 | return; |
| 8387 | } |
| 8388 | } |
| 8389 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8390 | static void bnx2x_set_e1e2_module_fault_led(struct link_params *params, |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 8391 | u8 gpio_mode) |
| 8392 | { |
| 8393 | struct bnx2x *bp = params->bp; |
| 8394 | |
| 8395 | u32 fault_led_gpio = REG_RD(bp, params->shmem_base + |
| 8396 | offsetof(struct shmem_region, |
| 8397 | dev_info.port_hw_config[params->port].sfp_ctrl)) & |
| 8398 | PORT_HW_CFG_FAULT_MODULE_LED_MASK; |
| 8399 | switch (fault_led_gpio) { |
| 8400 | case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: |
| 8401 | return; |
| 8402 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: |
| 8403 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: |
| 8404 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: |
| 8405 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: |
| 8406 | { |
| 8407 | u8 gpio_port = bnx2x_get_gpio_port(params); |
| 8408 | u16 gpio_pin = fault_led_gpio - |
| 8409 | PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; |
| 8410 | DP(NETIF_MSG_LINK, "Set fault module-detected led " |
| 8411 | "pin %x port %x mode %x\n", |
| 8412 | gpio_pin, gpio_port, gpio_mode); |
| 8413 | bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); |
| 8414 | } |
| 8415 | break; |
| 8416 | default: |
| 8417 | DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n", |
| 8418 | fault_led_gpio); |
| 8419 | } |
| 8420 | } |
| 8421 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8422 | static void bnx2x_set_e3_module_fault_led(struct link_params *params, |
| 8423 | u8 gpio_mode) |
| 8424 | { |
| 8425 | u32 pin_cfg; |
| 8426 | u8 port = params->port; |
| 8427 | struct bnx2x *bp = params->bp; |
| 8428 | pin_cfg = (REG_RD(bp, params->shmem_base + |
| 8429 | offsetof(struct shmem_region, |
| 8430 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & |
| 8431 | PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> |
| 8432 | PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; |
| 8433 | DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n", |
| 8434 | gpio_mode, pin_cfg); |
| 8435 | bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode); |
| 8436 | } |
| 8437 | |
| 8438 | static void bnx2x_set_sfp_module_fault_led(struct link_params *params, |
| 8439 | u8 gpio_mode) |
| 8440 | { |
| 8441 | struct bnx2x *bp = params->bp; |
| 8442 | DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode); |
| 8443 | if (CHIP_IS_E3(bp)) { |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 8444 | /* Low ==> if SFP+ module is supported otherwise |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8445 | * High ==> if SFP+ module is not on the approved vendor list |
| 8446 | */ |
| 8447 | bnx2x_set_e3_module_fault_led(params, gpio_mode); |
| 8448 | } else |
| 8449 | bnx2x_set_e1e2_module_fault_led(params, gpio_mode); |
| 8450 | } |
| 8451 | |
Yaniv Rosner | 985848f | 2011-07-05 01:06:48 +0000 | [diff] [blame] | 8452 | static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy, |
| 8453 | struct link_params *params) |
| 8454 | { |
Yaniv Rosner | b76070b | 2011-11-28 00:49:47 +0000 | [diff] [blame] | 8455 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 5a1fbf4 | 2012-11-27 03:46:31 +0000 | [diff] [blame] | 8456 | bnx2x_warpcore_power_module(params, 0); |
Yaniv Rosner | b76070b | 2011-11-28 00:49:47 +0000 | [diff] [blame] | 8457 | /* Put Warpcore in low power mode */ |
| 8458 | REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); |
| 8459 | |
| 8460 | /* Put LCPLL in low power mode */ |
| 8461 | REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); |
| 8462 | REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); |
| 8463 | REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); |
Yaniv Rosner | 985848f | 2011-07-05 01:06:48 +0000 | [diff] [blame] | 8464 | } |
| 8465 | |
Yaniv Rosner | e4d78f1 | 2011-05-31 21:25:55 +0000 | [diff] [blame] | 8466 | static void bnx2x_power_sfp_module(struct link_params *params, |
| 8467 | struct bnx2x_phy *phy, |
| 8468 | u8 power) |
| 8469 | { |
| 8470 | struct bnx2x *bp = params->bp; |
| 8471 | DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power); |
| 8472 | |
| 8473 | switch (phy->type) { |
| 8474 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
| 8475 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: |
| 8476 | bnx2x_8727_power_module(params->bp, phy, power); |
| 8477 | break; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8478 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
Yaniv Rosner | 5a1fbf4 | 2012-11-27 03:46:31 +0000 | [diff] [blame] | 8479 | bnx2x_warpcore_power_module(params, power); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8480 | break; |
Yaniv Rosner | e4d78f1 | 2011-05-31 21:25:55 +0000 | [diff] [blame] | 8481 | default: |
| 8482 | break; |
| 8483 | } |
| 8484 | } |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8485 | static void bnx2x_warpcore_set_limiting_mode(struct link_params *params, |
| 8486 | struct bnx2x_phy *phy, |
| 8487 | u16 edc_mode) |
| 8488 | { |
| 8489 | u16 val = 0; |
| 8490 | u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; |
| 8491 | struct bnx2x *bp = params->bp; |
| 8492 | |
| 8493 | u8 lane = bnx2x_get_warpcore_lane(phy, params); |
| 8494 | /* This is a global register which controls all lanes */ |
| 8495 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 8496 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); |
| 8497 | val &= ~(0xf << (lane << 2)); |
| 8498 | |
| 8499 | switch (edc_mode) { |
| 8500 | case EDC_MODE_LINEAR: |
| 8501 | case EDC_MODE_LIMITING: |
| 8502 | mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; |
| 8503 | break; |
| 8504 | case EDC_MODE_PASSIVE_DAC: |
| 8505 | mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; |
| 8506 | break; |
| 8507 | default: |
| 8508 | break; |
| 8509 | } |
| 8510 | |
| 8511 | val |= (mode << (lane << 2)); |
| 8512 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 8513 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); |
| 8514 | /* A must read */ |
| 8515 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 8516 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); |
| 8517 | |
Yaniv Rosner | 19af03a | 2011-08-02 22:59:47 +0000 | [diff] [blame] | 8518 | /* Restart microcode to re-read the new mode */ |
| 8519 | bnx2x_warpcore_reset_lane(bp, phy, 1); |
| 8520 | bnx2x_warpcore_reset_lane(bp, phy, 0); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8521 | |
| 8522 | } |
Yaniv Rosner | e4d78f1 | 2011-05-31 21:25:55 +0000 | [diff] [blame] | 8523 | |
| 8524 | static void bnx2x_set_limiting_mode(struct link_params *params, |
| 8525 | struct bnx2x_phy *phy, |
| 8526 | u16 edc_mode) |
| 8527 | { |
| 8528 | switch (phy->type) { |
| 8529 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: |
| 8530 | bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); |
| 8531 | break; |
| 8532 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
| 8533 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: |
| 8534 | bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); |
| 8535 | break; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8536 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
| 8537 | bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode); |
| 8538 | break; |
Yaniv Rosner | e4d78f1 | 2011-05-31 21:25:55 +0000 | [diff] [blame] | 8539 | } |
| 8540 | } |
| 8541 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 8542 | int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, |
| 8543 | struct link_params *params) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8544 | { |
| 8545 | struct bnx2x *bp = params->bp; |
| 8546 | u16 edc_mode; |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 8547 | int rc = 0; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8548 | |
| 8549 | u32 val = REG_RD(bp, params->shmem_base + |
| 8550 | offsetof(struct shmem_region, dev_info. |
| 8551 | port_feature_config[params->port].config)); |
Yaniv Rosner | 5a1fbf4 | 2012-11-27 03:46:31 +0000 | [diff] [blame] | 8552 | /* Enabled transmitter by default */ |
| 8553 | bnx2x_sfp_set_transmitter(params, phy, 1); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8554 | DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", |
| 8555 | params->port); |
Yaniv Rosner | e4d78f1 | 2011-05-31 21:25:55 +0000 | [diff] [blame] | 8556 | /* Power up module */ |
| 8557 | bnx2x_power_sfp_module(params, phy, 1); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8558 | if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { |
| 8559 | DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); |
| 8560 | return -EINVAL; |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8561 | } else if (bnx2x_verify_sfp_module(phy, params) != 0) { |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 8562 | /* Check SFP+ module compatibility */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8563 | DP(NETIF_MSG_LINK, "Module verification failed!!\n"); |
| 8564 | rc = -EINVAL; |
| 8565 | /* Turn on fault module-detected led */ |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 8566 | bnx2x_set_sfp_module_fault_led(params, |
| 8567 | MISC_REGISTERS_GPIO_HIGH); |
| 8568 | |
Yaniv Rosner | e4d78f1 | 2011-05-31 21:25:55 +0000 | [diff] [blame] | 8569 | /* Check if need to power down the SFP+ module */ |
| 8570 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == |
| 8571 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8572 | DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); |
Yaniv Rosner | e4d78f1 | 2011-05-31 21:25:55 +0000 | [diff] [blame] | 8573 | bnx2x_power_sfp_module(params, phy, 0); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8574 | return rc; |
| 8575 | } |
| 8576 | } else { |
| 8577 | /* Turn off fault module-detected led */ |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 8578 | bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8579 | } |
| 8580 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 8581 | /* Check and set limiting mode / LRM mode on 8726. On 8727 it |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 8582 | * is done automatically |
| 8583 | */ |
Yaniv Rosner | e4d78f1 | 2011-05-31 21:25:55 +0000 | [diff] [blame] | 8584 | bnx2x_set_limiting_mode(params, phy, edc_mode); |
| 8585 | |
Yaniv Rosner | 5a1fbf4 | 2012-11-27 03:46:31 +0000 | [diff] [blame] | 8586 | /* Disable transmit for this module if the module is not approved, and |
| 8587 | * laser needs to be disabled. |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8588 | */ |
Yaniv Rosner | 5a1fbf4 | 2012-11-27 03:46:31 +0000 | [diff] [blame] | 8589 | if ((rc) && |
| 8590 | ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == |
| 8591 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)) |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 8592 | bnx2x_sfp_set_transmitter(params, phy, 0); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8593 | |
| 8594 | return rc; |
| 8595 | } |
| 8596 | |
| 8597 | void bnx2x_handle_module_detect_int(struct link_params *params) |
| 8598 | { |
| 8599 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8600 | struct bnx2x_phy *phy; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8601 | u32 gpio_val; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8602 | u8 gpio_num, gpio_port; |
Yaniv Rosner | 5a1fbf4 | 2012-11-27 03:46:31 +0000 | [diff] [blame] | 8603 | if (CHIP_IS_E3(bp)) { |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8604 | phy = ¶ms->phy[INT_PHY]; |
Yaniv Rosner | 5a1fbf4 | 2012-11-27 03:46:31 +0000 | [diff] [blame] | 8605 | /* Always enable TX laser,will be disabled in case of fault */ |
| 8606 | bnx2x_sfp_set_transmitter(params, phy, 1); |
| 8607 | } else { |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8608 | phy = ¶ms->phy[EXT_PHY1]; |
Yaniv Rosner | 5a1fbf4 | 2012-11-27 03:46:31 +0000 | [diff] [blame] | 8609 | } |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8610 | if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, |
| 8611 | params->port, &gpio_num, &gpio_port) == |
| 8612 | -EINVAL) { |
| 8613 | DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n"); |
| 8614 | return; |
| 8615 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8616 | |
| 8617 | /* Set valid module led off */ |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 8618 | bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8619 | |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 8620 | /* Get current gpio val reflecting module plugged in / out*/ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8621 | gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8622 | |
| 8623 | /* Call the handling function in case module is detected */ |
| 8624 | if (gpio_val == 0) { |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 8625 | bnx2x_set_mdio_emac_per_phy(bp, params); |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 8626 | bnx2x_set_aer_mmd(params, phy); |
| 8627 | |
Yaniv Rosner | e4d78f1 | 2011-05-31 21:25:55 +0000 | [diff] [blame] | 8628 | bnx2x_power_sfp_module(params, phy, 1); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8629 | bnx2x_set_gpio_int(bp, gpio_num, |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8630 | MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8631 | gpio_port); |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 8632 | if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) { |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8633 | bnx2x_sfp_module_detection(phy, params); |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 8634 | if (CHIP_IS_E3(bp)) { |
| 8635 | u16 rx_tx_in_reset; |
| 8636 | /* In case WC is out of reset, reconfigure the |
| 8637 | * link speed while taking into account 1G |
| 8638 | * module limitation. |
| 8639 | */ |
| 8640 | bnx2x_cl45_read(bp, phy, |
| 8641 | MDIO_WC_DEVAD, |
| 8642 | MDIO_WC_REG_DIGITAL5_MISC6, |
| 8643 | &rx_tx_in_reset); |
| 8644 | if (!rx_tx_in_reset) { |
| 8645 | bnx2x_warpcore_reset_lane(bp, phy, 1); |
| 8646 | bnx2x_warpcore_config_sfi(phy, params); |
| 8647 | bnx2x_warpcore_reset_lane(bp, phy, 0); |
| 8648 | } |
| 8649 | } |
| 8650 | } else { |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8651 | DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 8652 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8653 | } else { |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8654 | bnx2x_set_gpio_int(bp, gpio_num, |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8655 | MISC_REGISTERS_GPIO_INT_OUTPUT_SET, |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 8656 | gpio_port); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 8657 | /* Module was plugged out. |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 8658 | * Disable transmit for this module |
| 8659 | */ |
Yaniv Rosner | 1ac9e42 | 2011-05-31 21:26:11 +0000 | [diff] [blame] | 8660 | phy->media_type = ETH_PHY_NOT_PRESENT; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8661 | } |
| 8662 | } |
| 8663 | |
| 8664 | /******************************************************************/ |
Yaniv Rosner | c688fe2 | 2011-05-31 21:27:06 +0000 | [diff] [blame] | 8665 | /* Used by 8706 and 8727 */ |
| 8666 | /******************************************************************/ |
| 8667 | static void bnx2x_sfp_mask_fault(struct bnx2x *bp, |
| 8668 | struct bnx2x_phy *phy, |
| 8669 | u16 alarm_status_offset, |
| 8670 | u16 alarm_ctrl_offset) |
| 8671 | { |
| 8672 | u16 alarm_status, val; |
| 8673 | bnx2x_cl45_read(bp, phy, |
| 8674 | MDIO_PMA_DEVAD, alarm_status_offset, |
| 8675 | &alarm_status); |
| 8676 | bnx2x_cl45_read(bp, phy, |
| 8677 | MDIO_PMA_DEVAD, alarm_status_offset, |
| 8678 | &alarm_status); |
| 8679 | /* Mask or enable the fault event. */ |
| 8680 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); |
| 8681 | if (alarm_status & (1<<0)) |
| 8682 | val &= ~(1<<0); |
| 8683 | else |
| 8684 | val |= (1<<0); |
| 8685 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); |
| 8686 | } |
| 8687 | /******************************************************************/ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8688 | /* common BCM8706/BCM8726 PHY SECTION */ |
| 8689 | /******************************************************************/ |
| 8690 | static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, |
| 8691 | struct link_params *params, |
| 8692 | struct link_vars *vars) |
| 8693 | { |
| 8694 | u8 link_up = 0; |
| 8695 | u16 val1, val2, rx_sd, pcs_status; |
| 8696 | struct bnx2x *bp = params->bp; |
| 8697 | DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); |
| 8698 | /* Clear RX Alarm*/ |
| 8699 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 8700 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); |
Yaniv Rosner | c688fe2 | 2011-05-31 21:27:06 +0000 | [diff] [blame] | 8701 | |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 8702 | bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, |
| 8703 | MDIO_PMA_LASI_TXCTRL); |
Yaniv Rosner | c688fe2 | 2011-05-31 21:27:06 +0000 | [diff] [blame] | 8704 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 8705 | /* Clear LASI indication*/ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8706 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 8707 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8708 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 8709 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8710 | DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); |
| 8711 | |
| 8712 | bnx2x_cl45_read(bp, phy, |
| 8713 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); |
| 8714 | bnx2x_cl45_read(bp, phy, |
| 8715 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); |
| 8716 | bnx2x_cl45_read(bp, phy, |
| 8717 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); |
| 8718 | bnx2x_cl45_read(bp, phy, |
| 8719 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); |
| 8720 | |
| 8721 | DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" |
| 8722 | " link_status 0x%x\n", rx_sd, pcs_status, val2); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 8723 | /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 8724 | * are set, or if the autoneg bit 1 is set |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8725 | */ |
| 8726 | link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); |
| 8727 | if (link_up) { |
| 8728 | if (val2 & (1<<1)) |
| 8729 | vars->line_speed = SPEED_1000; |
| 8730 | else |
| 8731 | vars->line_speed = SPEED_10000; |
| 8732 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
Yaniv Rosner | 791f18c | 2011-01-18 04:33:42 +0000 | [diff] [blame] | 8733 | vars->duplex = DUPLEX_FULL; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8734 | } |
Yaniv Rosner | c688fe2 | 2011-05-31 21:27:06 +0000 | [diff] [blame] | 8735 | |
| 8736 | /* Capture 10G link fault. Read twice to clear stale value. */ |
| 8737 | if (vars->line_speed == SPEED_10000) { |
| 8738 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 8739 | MDIO_PMA_LASI_TXSTAT, &val1); |
Yaniv Rosner | c688fe2 | 2011-05-31 21:27:06 +0000 | [diff] [blame] | 8740 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 8741 | MDIO_PMA_LASI_TXSTAT, &val1); |
Yaniv Rosner | c688fe2 | 2011-05-31 21:27:06 +0000 | [diff] [blame] | 8742 | if (val1 & (1<<0)) |
| 8743 | vars->fault_detected = 1; |
| 8744 | } |
| 8745 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8746 | return link_up; |
| 8747 | } |
| 8748 | |
| 8749 | /******************************************************************/ |
| 8750 | /* BCM8706 PHY SECTION */ |
| 8751 | /******************************************************************/ |
| 8752 | static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, |
| 8753 | struct link_params *params, |
| 8754 | struct link_vars *vars) |
| 8755 | { |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 8756 | u32 tx_en_mode; |
| 8757 | u16 cnt, val, tmp1; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8758 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 8759 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8760 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8761 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8762 | /* HW reset */ |
| 8763 | bnx2x_ext_phy_hw_reset(bp, params->port); |
| 8764 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); |
Yaniv Rosner | 6d870c3 | 2011-01-31 04:22:20 +0000 | [diff] [blame] | 8765 | bnx2x_wait_reset_complete(bp, phy, params); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8766 | |
| 8767 | /* Wait until fw is loaded */ |
| 8768 | for (cnt = 0; cnt < 100; cnt++) { |
| 8769 | bnx2x_cl45_read(bp, phy, |
| 8770 | MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); |
| 8771 | if (val) |
| 8772 | break; |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 8773 | usleep_range(10000, 20000); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8774 | } |
| 8775 | DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); |
| 8776 | if ((params->feature_config_flags & |
| 8777 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { |
| 8778 | u8 i; |
| 8779 | u16 reg; |
| 8780 | for (i = 0; i < 4; i++) { |
| 8781 | reg = MDIO_XS_8706_REG_BANK_RX0 + |
| 8782 | i*(MDIO_XS_8706_REG_BANK_RX1 - |
| 8783 | MDIO_XS_8706_REG_BANK_RX0); |
| 8784 | bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); |
| 8785 | /* Clear first 3 bits of the control */ |
| 8786 | val &= ~0x7; |
| 8787 | /* Set control bits according to configuration */ |
| 8788 | val |= (phy->rx_preemphasis[i] & 0x7); |
| 8789 | DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706" |
| 8790 | " reg 0x%x <-- val 0x%x\n", reg, val); |
| 8791 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); |
| 8792 | } |
| 8793 | } |
| 8794 | /* Force speed */ |
| 8795 | if (phy->req_line_speed == SPEED_10000) { |
| 8796 | DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); |
| 8797 | |
| 8798 | bnx2x_cl45_write(bp, phy, |
| 8799 | MDIO_PMA_DEVAD, |
| 8800 | MDIO_PMA_REG_DIGITAL_CTRL, 0x400); |
| 8801 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 8802 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, |
Yaniv Rosner | c688fe2 | 2011-05-31 21:27:06 +0000 | [diff] [blame] | 8803 | 0); |
| 8804 | /* Arm LASI for link and Tx fault. */ |
| 8805 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 8806 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8807 | } else { |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 8808 | /* Force 1Gbps using autoneg with 1G advertisement */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8809 | |
| 8810 | /* Allow CL37 through CL73 */ |
| 8811 | DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); |
| 8812 | bnx2x_cl45_write(bp, phy, |
| 8813 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); |
| 8814 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 8815 | /* Enable Full-Duplex advertisement on CL37 */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8816 | bnx2x_cl45_write(bp, phy, |
| 8817 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); |
| 8818 | /* Enable CL37 AN */ |
| 8819 | bnx2x_cl45_write(bp, phy, |
| 8820 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); |
| 8821 | /* 1G support */ |
| 8822 | bnx2x_cl45_write(bp, phy, |
| 8823 | MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); |
| 8824 | |
| 8825 | /* Enable clause 73 AN */ |
| 8826 | bnx2x_cl45_write(bp, phy, |
| 8827 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); |
| 8828 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 8829 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8830 | 0x0400); |
| 8831 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 8832 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8833 | 0x0004); |
| 8834 | } |
| 8835 | bnx2x_save_bcm_spirom_ver(bp, phy, params->port); |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 8836 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 8837 | /* If TX Laser is controlled by GPIO_0, do not let PHY go into low |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 8838 | * power mode, if TX Laser is disabled |
| 8839 | */ |
| 8840 | |
| 8841 | tx_en_mode = REG_RD(bp, params->shmem_base + |
| 8842 | offsetof(struct shmem_region, |
| 8843 | dev_info.port_hw_config[params->port].sfp_ctrl)) |
| 8844 | & PORT_HW_CFG_TX_LASER_MASK; |
| 8845 | |
| 8846 | if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { |
| 8847 | DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); |
| 8848 | bnx2x_cl45_read(bp, phy, |
| 8849 | MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); |
| 8850 | tmp1 |= 0x1; |
| 8851 | bnx2x_cl45_write(bp, phy, |
| 8852 | MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); |
| 8853 | } |
| 8854 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8855 | return 0; |
| 8856 | } |
| 8857 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 8858 | static int bnx2x_8706_read_status(struct bnx2x_phy *phy, |
| 8859 | struct link_params *params, |
| 8860 | struct link_vars *vars) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8861 | { |
| 8862 | return bnx2x_8706_8726_read_status(phy, params, vars); |
| 8863 | } |
| 8864 | |
| 8865 | /******************************************************************/ |
| 8866 | /* BCM8726 PHY SECTION */ |
| 8867 | /******************************************************************/ |
| 8868 | static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, |
| 8869 | struct link_params *params) |
| 8870 | { |
| 8871 | struct bnx2x *bp = params->bp; |
| 8872 | DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); |
| 8873 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); |
| 8874 | } |
| 8875 | |
| 8876 | static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, |
| 8877 | struct link_params *params) |
| 8878 | { |
| 8879 | struct bnx2x *bp = params->bp; |
| 8880 | /* Need to wait 100ms after reset */ |
| 8881 | msleep(100); |
| 8882 | |
| 8883 | /* Micro controller re-boot */ |
| 8884 | bnx2x_cl45_write(bp, phy, |
| 8885 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); |
| 8886 | |
| 8887 | /* Set soft reset */ |
| 8888 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8889 | MDIO_PMA_DEVAD, |
| 8890 | MDIO_PMA_REG_GEN_CTRL, |
| 8891 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8892 | |
| 8893 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8894 | MDIO_PMA_DEVAD, |
| 8895 | MDIO_PMA_REG_MISC_CTRL1, 0x0001); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8896 | |
| 8897 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8898 | MDIO_PMA_DEVAD, |
| 8899 | MDIO_PMA_REG_GEN_CTRL, |
| 8900 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8901 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 8902 | /* Wait for 150ms for microcode load */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8903 | msleep(150); |
| 8904 | |
| 8905 | /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ |
| 8906 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 8907 | MDIO_PMA_DEVAD, |
| 8908 | MDIO_PMA_REG_MISC_CTRL1, 0x0000); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8909 | |
| 8910 | msleep(200); |
| 8911 | bnx2x_save_bcm_spirom_ver(bp, phy, params->port); |
| 8912 | } |
| 8913 | |
| 8914 | static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, |
| 8915 | struct link_params *params, |
| 8916 | struct link_vars *vars) |
| 8917 | { |
| 8918 | struct bnx2x *bp = params->bp; |
| 8919 | u16 val1; |
| 8920 | u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); |
| 8921 | if (link_up) { |
| 8922 | bnx2x_cl45_read(bp, phy, |
| 8923 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, |
| 8924 | &val1); |
| 8925 | if (val1 & (1<<15)) { |
| 8926 | DP(NETIF_MSG_LINK, "Tx is disabled\n"); |
| 8927 | link_up = 0; |
| 8928 | vars->line_speed = 0; |
| 8929 | } |
| 8930 | } |
| 8931 | return link_up; |
| 8932 | } |
| 8933 | |
| 8934 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 8935 | static int bnx2x_8726_config_init(struct bnx2x_phy *phy, |
| 8936 | struct link_params *params, |
| 8937 | struct link_vars *vars) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8938 | { |
| 8939 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8940 | DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8941 | |
| 8942 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
Yaniv Rosner | 6d870c3 | 2011-01-31 04:22:20 +0000 | [diff] [blame] | 8943 | bnx2x_wait_reset_complete(bp, phy, params); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8944 | |
| 8945 | bnx2x_8726_external_rom_boot(phy, params); |
| 8946 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 8947 | /* Need to call module detected on initialization since the module |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 8948 | * detection triggered by actual module insertion might occur before |
| 8949 | * driver is loaded, and when driver is loaded, it reset all |
| 8950 | * registers, including the transmitter |
| 8951 | */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8952 | bnx2x_sfp_module_detection(phy, params); |
| 8953 | |
| 8954 | if (phy->req_line_speed == SPEED_1000) { |
| 8955 | DP(NETIF_MSG_LINK, "Setting 1G force\n"); |
| 8956 | bnx2x_cl45_write(bp, phy, |
| 8957 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); |
| 8958 | bnx2x_cl45_write(bp, phy, |
| 8959 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); |
| 8960 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 8961 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8962 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 8963 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8964 | 0x400); |
| 8965 | } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && |
| 8966 | (phy->speed_cap_mask & |
| 8967 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && |
| 8968 | ((phy->speed_cap_mask & |
| 8969 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != |
| 8970 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { |
| 8971 | DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); |
| 8972 | /* Set Flow control */ |
| 8973 | bnx2x_ext_phy_set_pause(params, phy, vars); |
| 8974 | bnx2x_cl45_write(bp, phy, |
| 8975 | MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); |
| 8976 | bnx2x_cl45_write(bp, phy, |
| 8977 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); |
| 8978 | bnx2x_cl45_write(bp, phy, |
| 8979 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); |
| 8980 | bnx2x_cl45_write(bp, phy, |
| 8981 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); |
| 8982 | bnx2x_cl45_write(bp, phy, |
| 8983 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 8984 | /* Enable RX-ALARM control to receive interrupt for 1G speed |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 8985 | * change |
| 8986 | */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8987 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 8988 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8989 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 8990 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8991 | 0x400); |
| 8992 | |
| 8993 | } else { /* Default 10G. Set only LASI control */ |
| 8994 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 8995 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 8996 | } |
| 8997 | |
| 8998 | /* Set TX PreEmphasis if needed */ |
| 8999 | if ((params->feature_config_flags & |
| 9000 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 9001 | DP(NETIF_MSG_LINK, |
| 9002 | "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9003 | phy->tx_preemphasis[0], |
| 9004 | phy->tx_preemphasis[1]); |
| 9005 | bnx2x_cl45_write(bp, phy, |
| 9006 | MDIO_PMA_DEVAD, |
| 9007 | MDIO_PMA_REG_8726_TX_CTRL1, |
| 9008 | phy->tx_preemphasis[0]); |
| 9009 | |
| 9010 | bnx2x_cl45_write(bp, phy, |
| 9011 | MDIO_PMA_DEVAD, |
| 9012 | MDIO_PMA_REG_8726_TX_CTRL2, |
| 9013 | phy->tx_preemphasis[1]); |
| 9014 | } |
| 9015 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9016 | return 0; |
| 9017 | |
| 9018 | } |
| 9019 | |
| 9020 | static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, |
| 9021 | struct link_params *params) |
| 9022 | { |
| 9023 | struct bnx2x *bp = params->bp; |
| 9024 | DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); |
| 9025 | /* Set serial boot control for external load */ |
| 9026 | bnx2x_cl45_write(bp, phy, |
| 9027 | MDIO_PMA_DEVAD, |
| 9028 | MDIO_PMA_REG_GEN_CTRL, 0x0001); |
| 9029 | } |
| 9030 | |
| 9031 | /******************************************************************/ |
| 9032 | /* BCM8727 PHY SECTION */ |
| 9033 | /******************************************************************/ |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 9034 | |
| 9035 | static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, |
| 9036 | struct link_params *params, u8 mode) |
| 9037 | { |
| 9038 | struct bnx2x *bp = params->bp; |
| 9039 | u16 led_mode_bitmask = 0; |
| 9040 | u16 gpio_pins_bitmask = 0; |
| 9041 | u16 val; |
| 9042 | /* Only NOC flavor requires to set the LED specifically */ |
| 9043 | if (!(phy->flags & FLAGS_NOC)) |
| 9044 | return; |
| 9045 | switch (mode) { |
| 9046 | case LED_MODE_FRONT_PANEL_OFF: |
| 9047 | case LED_MODE_OFF: |
| 9048 | led_mode_bitmask = 0; |
| 9049 | gpio_pins_bitmask = 0x03; |
| 9050 | break; |
| 9051 | case LED_MODE_ON: |
| 9052 | led_mode_bitmask = 0; |
| 9053 | gpio_pins_bitmask = 0x02; |
| 9054 | break; |
| 9055 | case LED_MODE_OPER: |
| 9056 | led_mode_bitmask = 0x60; |
| 9057 | gpio_pins_bitmask = 0x11; |
| 9058 | break; |
| 9059 | } |
| 9060 | bnx2x_cl45_read(bp, phy, |
| 9061 | MDIO_PMA_DEVAD, |
| 9062 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, |
| 9063 | &val); |
| 9064 | val &= 0xff8f; |
| 9065 | val |= led_mode_bitmask; |
| 9066 | bnx2x_cl45_write(bp, phy, |
| 9067 | MDIO_PMA_DEVAD, |
| 9068 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, |
| 9069 | val); |
| 9070 | bnx2x_cl45_read(bp, phy, |
| 9071 | MDIO_PMA_DEVAD, |
| 9072 | MDIO_PMA_REG_8727_GPIO_CTRL, |
| 9073 | &val); |
| 9074 | val &= 0xffe0; |
| 9075 | val |= gpio_pins_bitmask; |
| 9076 | bnx2x_cl45_write(bp, phy, |
| 9077 | MDIO_PMA_DEVAD, |
| 9078 | MDIO_PMA_REG_8727_GPIO_CTRL, |
| 9079 | val); |
| 9080 | } |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 9081 | static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, |
| 9082 | struct link_params *params) { |
| 9083 | u32 swap_val, swap_override; |
| 9084 | u8 port; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 9085 | /* The PHY reset is controlled by GPIO 1. Fake the port number |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 9086 | * to cancel the swap done in set_gpio() |
| 9087 | */ |
| 9088 | struct bnx2x *bp = params->bp; |
| 9089 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); |
| 9090 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); |
| 9091 | port = (swap_val && swap_override) ^ 1; |
| 9092 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 9093 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 9094 | } |
| 9095 | |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 9096 | static void bnx2x_8727_config_speed(struct bnx2x_phy *phy, |
| 9097 | struct link_params *params) |
| 9098 | { |
| 9099 | struct bnx2x *bp = params->bp; |
| 9100 | u16 tmp1, val; |
| 9101 | /* Set option 1G speed */ |
| 9102 | if ((phy->req_line_speed == SPEED_1000) || |
| 9103 | (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { |
| 9104 | DP(NETIF_MSG_LINK, "Setting 1G force\n"); |
| 9105 | bnx2x_cl45_write(bp, phy, |
| 9106 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); |
| 9107 | bnx2x_cl45_write(bp, phy, |
| 9108 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); |
| 9109 | bnx2x_cl45_read(bp, phy, |
| 9110 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); |
| 9111 | DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); |
| 9112 | /* Power down the XAUI until link is up in case of dual-media |
| 9113 | * and 1G |
| 9114 | */ |
| 9115 | if (DUAL_MEDIA(params)) { |
| 9116 | bnx2x_cl45_read(bp, phy, |
| 9117 | MDIO_PMA_DEVAD, |
| 9118 | MDIO_PMA_REG_8727_PCS_GP, &val); |
| 9119 | val |= (3<<10); |
| 9120 | bnx2x_cl45_write(bp, phy, |
| 9121 | MDIO_PMA_DEVAD, |
| 9122 | MDIO_PMA_REG_8727_PCS_GP, val); |
| 9123 | } |
| 9124 | } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && |
| 9125 | ((phy->speed_cap_mask & |
| 9126 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && |
| 9127 | ((phy->speed_cap_mask & |
| 9128 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != |
| 9129 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { |
| 9130 | |
| 9131 | DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); |
| 9132 | bnx2x_cl45_write(bp, phy, |
| 9133 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); |
| 9134 | bnx2x_cl45_write(bp, phy, |
| 9135 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); |
| 9136 | } else { |
| 9137 | /* Since the 8727 has only single reset pin, need to set the 10G |
| 9138 | * registers although it is default |
| 9139 | */ |
| 9140 | bnx2x_cl45_write(bp, phy, |
| 9141 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, |
| 9142 | 0x0020); |
| 9143 | bnx2x_cl45_write(bp, phy, |
| 9144 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); |
| 9145 | bnx2x_cl45_write(bp, phy, |
| 9146 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); |
| 9147 | bnx2x_cl45_write(bp, phy, |
| 9148 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, |
| 9149 | 0x0008); |
| 9150 | } |
| 9151 | } |
| 9152 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 9153 | static int bnx2x_8727_config_init(struct bnx2x_phy *phy, |
| 9154 | struct link_params *params, |
| 9155 | struct link_vars *vars) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9156 | { |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 9157 | u32 tx_en_mode; |
Yaniv Rosner | 5c107fd | 2012-09-13 02:56:19 +0000 | [diff] [blame] | 9158 | u16 tmp1, mod_abs, tmp2; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9159 | struct bnx2x *bp = params->bp; |
| 9160 | /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ |
| 9161 | |
Yaniv Rosner | 6d870c3 | 2011-01-31 04:22:20 +0000 | [diff] [blame] | 9162 | bnx2x_wait_reset_complete(bp, phy, params); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9163 | |
| 9164 | DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9165 | |
Yaniv Rosner | 5c107fd | 2012-09-13 02:56:19 +0000 | [diff] [blame] | 9166 | bnx2x_8727_specific_func(phy, params, PHY_INIT); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 9167 | /* Initially configure MOD_ABS to interrupt when module is |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 9168 | * presence( bit 8) |
| 9169 | */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9170 | bnx2x_cl45_read(bp, phy, |
| 9171 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 9172 | /* Set EDC off by setting OPTXLOS signal input to low (bit 9). |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 9173 | * When the EDC is off it locks onto a reference clock and avoids |
| 9174 | * becoming 'lost' |
| 9175 | */ |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 9176 | mod_abs &= ~(1<<8); |
| 9177 | if (!(phy->flags & FLAGS_NOC)) |
| 9178 | mod_abs &= ~(1<<9); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9179 | bnx2x_cl45_write(bp, phy, |
| 9180 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); |
| 9181 | |
Yaniv Rosner | 85242ee | 2011-07-05 01:06:53 +0000 | [diff] [blame] | 9182 | /* Enable/Disable PHY transmitter output */ |
| 9183 | bnx2x_set_disable_pmd_transmit(params, phy, 0); |
| 9184 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9185 | bnx2x_8727_power_module(bp, phy, 1); |
| 9186 | |
| 9187 | bnx2x_cl45_read(bp, phy, |
| 9188 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); |
| 9189 | |
| 9190 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 9191 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9192 | |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 9193 | bnx2x_8727_config_speed(phy, params); |
Yaniv Rosner | 5c107fd | 2012-09-13 02:56:19 +0000 | [diff] [blame] | 9194 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9195 | |
| 9196 | /* Set TX PreEmphasis if needed */ |
| 9197 | if ((params->feature_config_flags & |
| 9198 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { |
| 9199 | DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", |
| 9200 | phy->tx_preemphasis[0], |
| 9201 | phy->tx_preemphasis[1]); |
| 9202 | bnx2x_cl45_write(bp, phy, |
| 9203 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, |
| 9204 | phy->tx_preemphasis[0]); |
| 9205 | |
| 9206 | bnx2x_cl45_write(bp, phy, |
| 9207 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, |
| 9208 | phy->tx_preemphasis[1]); |
| 9209 | } |
| 9210 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 9211 | /* If TX Laser is controlled by GPIO_0, do not let PHY go into low |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 9212 | * power mode, if TX Laser is disabled |
| 9213 | */ |
| 9214 | tx_en_mode = REG_RD(bp, params->shmem_base + |
| 9215 | offsetof(struct shmem_region, |
| 9216 | dev_info.port_hw_config[params->port].sfp_ctrl)) |
| 9217 | & PORT_HW_CFG_TX_LASER_MASK; |
| 9218 | |
| 9219 | if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { |
| 9220 | |
| 9221 | DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); |
| 9222 | bnx2x_cl45_read(bp, phy, |
| 9223 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); |
| 9224 | tmp2 |= 0x1000; |
| 9225 | tmp2 &= 0xFFEF; |
| 9226 | bnx2x_cl45_write(bp, phy, |
| 9227 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); |
Yaniv Rosner | 59a2e53 | 2012-04-04 01:28:59 +0000 | [diff] [blame] | 9228 | bnx2x_cl45_read(bp, phy, |
| 9229 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, |
| 9230 | &tmp2); |
| 9231 | bnx2x_cl45_write(bp, phy, |
| 9232 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, |
| 9233 | (tmp2 & 0x7fff)); |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 9234 | } |
| 9235 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9236 | return 0; |
| 9237 | } |
| 9238 | |
| 9239 | static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, |
| 9240 | struct link_params *params) |
| 9241 | { |
| 9242 | struct bnx2x *bp = params->bp; |
| 9243 | u16 mod_abs, rx_alarm_status; |
| 9244 | u32 val = REG_RD(bp, params->shmem_base + |
| 9245 | offsetof(struct shmem_region, dev_info. |
| 9246 | port_feature_config[params->port]. |
| 9247 | config)); |
| 9248 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 9249 | MDIO_PMA_DEVAD, |
| 9250 | MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9251 | if (mod_abs & (1<<8)) { |
| 9252 | |
| 9253 | /* Module is absent */ |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 9254 | DP(NETIF_MSG_LINK, |
| 9255 | "MOD_ABS indication show module is absent\n"); |
Yaniv Rosner | 1ac9e42 | 2011-05-31 21:26:11 +0000 | [diff] [blame] | 9256 | phy->media_type = ETH_PHY_NOT_PRESENT; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 9257 | /* 1. Set mod_abs to detect next module |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 9258 | * presence event |
| 9259 | * 2. Set EDC off by setting OPTXLOS signal input to low |
| 9260 | * (bit 9). |
| 9261 | * When the EDC is off it locks onto a reference clock and |
| 9262 | * avoids becoming 'lost'. |
| 9263 | */ |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 9264 | mod_abs &= ~(1<<8); |
| 9265 | if (!(phy->flags & FLAGS_NOC)) |
| 9266 | mod_abs &= ~(1<<9); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9267 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 9268 | MDIO_PMA_DEVAD, |
| 9269 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9270 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 9271 | /* Clear RX alarm since it stays up as long as |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 9272 | * the mod_abs wasn't changed |
| 9273 | */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9274 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 9275 | MDIO_PMA_DEVAD, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 9276 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9277 | |
| 9278 | } else { |
| 9279 | /* Module is present */ |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 9280 | DP(NETIF_MSG_LINK, |
| 9281 | "MOD_ABS indication show module is present\n"); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 9282 | /* First disable transmitter, and if the module is ok, the |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 9283 | * module_detection will enable it |
| 9284 | * 1. Set mod_abs to detect next module absent event ( bit 8) |
| 9285 | * 2. Restore the default polarity of the OPRXLOS signal and |
| 9286 | * this signal will then correctly indicate the presence or |
| 9287 | * absence of the Rx signal. (bit 9) |
| 9288 | */ |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 9289 | mod_abs |= (1<<8); |
| 9290 | if (!(phy->flags & FLAGS_NOC)) |
| 9291 | mod_abs |= (1<<9); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9292 | bnx2x_cl45_write(bp, phy, |
| 9293 | MDIO_PMA_DEVAD, |
| 9294 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); |
| 9295 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 9296 | /* Clear RX alarm since it stays up as long as the mod_abs |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 9297 | * wasn't changed. This is need to be done before calling the |
| 9298 | * module detection, otherwise it will clear* the link update |
| 9299 | * alarm |
| 9300 | */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9301 | bnx2x_cl45_read(bp, phy, |
| 9302 | MDIO_PMA_DEVAD, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 9303 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9304 | |
| 9305 | |
| 9306 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == |
| 9307 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 9308 | bnx2x_sfp_set_transmitter(params, phy, 0); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9309 | |
| 9310 | if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) |
| 9311 | bnx2x_sfp_module_detection(phy, params); |
| 9312 | else |
| 9313 | DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 9314 | |
| 9315 | /* Reconfigure link speed based on module type limitations */ |
| 9316 | bnx2x_8727_config_speed(phy, params); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9317 | } |
| 9318 | |
| 9319 | DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 9320 | rx_alarm_status); |
| 9321 | /* No need to check link status in case of module plugged in/out */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9322 | } |
| 9323 | |
| 9324 | static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, |
| 9325 | struct link_params *params, |
| 9326 | struct link_vars *vars) |
| 9327 | |
| 9328 | { |
| 9329 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 27d0243 | 2011-05-31 21:27:48 +0000 | [diff] [blame] | 9330 | u8 link_up = 0, oc_port = params->port; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9331 | u16 link_status = 0; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 9332 | u16 rx_alarm_status, lasi_ctrl, val1; |
| 9333 | |
| 9334 | /* If PHY is not initialized, do not check link status */ |
| 9335 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 9336 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 9337 | &lasi_ctrl); |
| 9338 | if (!lasi_ctrl) |
| 9339 | return 0; |
| 9340 | |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 9341 | /* Check the LASI on Rx */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9342 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 9343 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9344 | &rx_alarm_status); |
| 9345 | vars->line_speed = 0; |
| 9346 | DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); |
| 9347 | |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 9348 | bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, |
| 9349 | MDIO_PMA_LASI_TXCTRL); |
Yaniv Rosner | c688fe2 | 2011-05-31 21:27:06 +0000 | [diff] [blame] | 9350 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9351 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 9352 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9353 | |
| 9354 | DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); |
| 9355 | |
| 9356 | /* Clear MSG-OUT */ |
| 9357 | bnx2x_cl45_read(bp, phy, |
| 9358 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); |
| 9359 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 9360 | /* If a module is present and there is need to check |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9361 | * for over current |
| 9362 | */ |
| 9363 | if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { |
| 9364 | /* Check over-current using 8727 GPIO0 input*/ |
| 9365 | bnx2x_cl45_read(bp, phy, |
| 9366 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, |
| 9367 | &val1); |
| 9368 | |
| 9369 | if ((val1 & (1<<8)) == 0) { |
Yaniv Rosner | 27d0243 | 2011-05-31 21:27:48 +0000 | [diff] [blame] | 9370 | if (!CHIP_IS_E1x(bp)) |
| 9371 | oc_port = BP_PATH(bp) + (params->port << 1); |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 9372 | DP(NETIF_MSG_LINK, |
| 9373 | "8727 Power fault has been detected on port %d\n", |
| 9374 | oc_port); |
Yaniv Rosner | 2f751a8 | 2011-11-28 00:49:52 +0000 | [diff] [blame] | 9375 | netdev_err(bp->dev, "Error: Power fault on Port %d has " |
| 9376 | "been detected and the power to " |
| 9377 | "that SFP+ module has been removed " |
| 9378 | "to prevent failure of the card. " |
| 9379 | "Please remove the SFP+ module and " |
| 9380 | "restart the system to clear this " |
| 9381 | "error.\n", |
Yaniv Rosner | 27d0243 | 2011-05-31 21:27:48 +0000 | [diff] [blame] | 9382 | oc_port); |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 9383 | /* Disable all RX_ALARMs except for mod_abs */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9384 | bnx2x_cl45_write(bp, phy, |
| 9385 | MDIO_PMA_DEVAD, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 9386 | MDIO_PMA_LASI_RXCTRL, (1<<5)); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9387 | |
| 9388 | bnx2x_cl45_read(bp, phy, |
| 9389 | MDIO_PMA_DEVAD, |
| 9390 | MDIO_PMA_REG_PHY_IDENTIFIER, &val1); |
| 9391 | /* Wait for module_absent_event */ |
| 9392 | val1 |= (1<<8); |
| 9393 | bnx2x_cl45_write(bp, phy, |
| 9394 | MDIO_PMA_DEVAD, |
| 9395 | MDIO_PMA_REG_PHY_IDENTIFIER, val1); |
| 9396 | /* Clear RX alarm */ |
| 9397 | bnx2x_cl45_read(bp, phy, |
| 9398 | MDIO_PMA_DEVAD, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 9399 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
Yaniv Rosner | 5a1fbf4 | 2012-11-27 03:46:31 +0000 | [diff] [blame] | 9400 | bnx2x_8727_power_module(params->bp, phy, 0); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9401 | return 0; |
| 9402 | } |
| 9403 | } /* Over current check */ |
| 9404 | |
| 9405 | /* When module absent bit is set, check module */ |
| 9406 | if (rx_alarm_status & (1<<5)) { |
| 9407 | bnx2x_8727_handle_mod_abs(phy, params); |
| 9408 | /* Enable all mod_abs and link detection bits */ |
| 9409 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 9410 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9411 | ((1<<5) | (1<<2))); |
| 9412 | } |
Yaniv Rosner | 59a2e53 | 2012-04-04 01:28:59 +0000 | [diff] [blame] | 9413 | |
| 9414 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { |
| 9415 | DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n"); |
| 9416 | bnx2x_sfp_set_transmitter(params, phy, 1); |
| 9417 | } else { |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9418 | DP(NETIF_MSG_LINK, "Tx is disabled\n"); |
| 9419 | return 0; |
| 9420 | } |
| 9421 | |
| 9422 | bnx2x_cl45_read(bp, phy, |
| 9423 | MDIO_PMA_DEVAD, |
| 9424 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); |
| 9425 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 9426 | /* Bits 0..2 --> speed detected, |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 9427 | * Bits 13..15--> link is down |
| 9428 | */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9429 | if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { |
| 9430 | link_up = 1; |
| 9431 | vars->line_speed = SPEED_10000; |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 9432 | DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", |
| 9433 | params->port); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9434 | } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { |
| 9435 | link_up = 1; |
| 9436 | vars->line_speed = SPEED_1000; |
| 9437 | DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", |
| 9438 | params->port); |
| 9439 | } else { |
| 9440 | link_up = 0; |
| 9441 | DP(NETIF_MSG_LINK, "port %x: External link is down\n", |
| 9442 | params->port); |
| 9443 | } |
Yaniv Rosner | c688fe2 | 2011-05-31 21:27:06 +0000 | [diff] [blame] | 9444 | |
| 9445 | /* Capture 10G link fault. */ |
| 9446 | if (vars->line_speed == SPEED_10000) { |
| 9447 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 9448 | MDIO_PMA_LASI_TXSTAT, &val1); |
Yaniv Rosner | c688fe2 | 2011-05-31 21:27:06 +0000 | [diff] [blame] | 9449 | |
| 9450 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 9451 | MDIO_PMA_LASI_TXSTAT, &val1); |
Yaniv Rosner | c688fe2 | 2011-05-31 21:27:06 +0000 | [diff] [blame] | 9452 | |
| 9453 | if (val1 & (1<<0)) { |
| 9454 | vars->fault_detected = 1; |
| 9455 | } |
| 9456 | } |
| 9457 | |
Yaniv Rosner | 791f18c | 2011-01-18 04:33:42 +0000 | [diff] [blame] | 9458 | if (link_up) { |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9459 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
Yaniv Rosner | 791f18c | 2011-01-18 04:33:42 +0000 | [diff] [blame] | 9460 | vars->duplex = DUPLEX_FULL; |
| 9461 | DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); |
| 9462 | } |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 9463 | |
| 9464 | if ((DUAL_MEDIA(params)) && |
| 9465 | (phy->req_line_speed == SPEED_1000)) { |
| 9466 | bnx2x_cl45_read(bp, phy, |
| 9467 | MDIO_PMA_DEVAD, |
| 9468 | MDIO_PMA_REG_8727_PCS_GP, &val1); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 9469 | /* In case of dual-media board and 1G, power up the XAUI side, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 9470 | * otherwise power it down. For 10G it is done automatically |
| 9471 | */ |
| 9472 | if (link_up) |
| 9473 | val1 &= ~(3<<10); |
| 9474 | else |
| 9475 | val1 |= (3<<10); |
| 9476 | bnx2x_cl45_write(bp, phy, |
| 9477 | MDIO_PMA_DEVAD, |
| 9478 | MDIO_PMA_REG_8727_PCS_GP, val1); |
| 9479 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9480 | return link_up; |
| 9481 | } |
| 9482 | |
| 9483 | static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, |
| 9484 | struct link_params *params) |
| 9485 | { |
| 9486 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 85242ee | 2011-07-05 01:06:53 +0000 | [diff] [blame] | 9487 | |
| 9488 | /* Enable/Disable PHY transmitter output */ |
| 9489 | bnx2x_set_disable_pmd_transmit(params, phy, 1); |
| 9490 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9491 | /* Disable Transmitter */ |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 9492 | bnx2x_sfp_set_transmitter(params, phy, 0); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 9493 | /* Clear LASI */ |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 9494 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 9495 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9496 | } |
| 9497 | |
| 9498 | /******************************************************************/ |
| 9499 | /* BCM8481/BCM84823/BCM84833 PHY SECTION */ |
| 9500 | /******************************************************************/ |
| 9501 | static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 9502 | struct bnx2x *bp, |
| 9503 | u8 port) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9504 | { |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 9505 | u16 val, fw_ver2, cnt, i; |
| 9506 | static struct bnx2x_reg_set reg_set[] = { |
| 9507 | {MDIO_PMA_DEVAD, 0xA819, 0x0014}, |
| 9508 | {MDIO_PMA_DEVAD, 0xA81A, 0xc200}, |
| 9509 | {MDIO_PMA_DEVAD, 0xA81B, 0x0000}, |
| 9510 | {MDIO_PMA_DEVAD, 0xA81C, 0x0300}, |
| 9511 | {MDIO_PMA_DEVAD, 0xA817, 0x0009} |
| 9512 | }; |
| 9513 | u16 fw_ver1; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9514 | |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 9515 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
| 9516 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 9517 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); |
Yaniv Rosner | 8267bbb0 | 2012-04-04 01:29:00 +0000 | [diff] [blame] | 9518 | bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff, |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 9519 | phy->ver_addr); |
| 9520 | } else { |
| 9521 | /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ |
| 9522 | /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ |
Sasha Levin | b5a0555 | 2012-12-20 09:11:24 +0000 | [diff] [blame] | 9523 | for (i = 0; i < ARRAY_SIZE(reg_set); |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 9524 | i++) |
| 9525 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, |
| 9526 | reg_set[i].reg, reg_set[i].val); |
Yaniv Rosner | c87bca1 | 2011-01-31 04:22:41 +0000 | [diff] [blame] | 9527 | |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 9528 | for (cnt = 0; cnt < 100; cnt++) { |
| 9529 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); |
| 9530 | if (val & 1) |
| 9531 | break; |
| 9532 | udelay(5); |
| 9533 | } |
| 9534 | if (cnt == 100) { |
| 9535 | DP(NETIF_MSG_LINK, "Unable to read 848xx " |
| 9536 | "phy fw version(1)\n"); |
| 9537 | bnx2x_save_spirom_version(bp, port, 0, |
| 9538 | phy->ver_addr); |
| 9539 | return; |
| 9540 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9541 | |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 9542 | |
| 9543 | /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ |
| 9544 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); |
| 9545 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); |
| 9546 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); |
| 9547 | for (cnt = 0; cnt < 100; cnt++) { |
| 9548 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); |
| 9549 | if (val & 1) |
| 9550 | break; |
| 9551 | udelay(5); |
| 9552 | } |
| 9553 | if (cnt == 100) { |
| 9554 | DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw " |
| 9555 | "version(2)\n"); |
| 9556 | bnx2x_save_spirom_version(bp, port, 0, |
| 9557 | phy->ver_addr); |
| 9558 | return; |
| 9559 | } |
| 9560 | |
| 9561 | /* lower 16 bits of the register SPI_FW_STATUS */ |
| 9562 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); |
| 9563 | /* upper 16 bits of register SPI_FW_STATUS */ |
| 9564 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); |
| 9565 | |
| 9566 | bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1, |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9567 | phy->ver_addr); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9568 | } |
| 9569 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9570 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9571 | static void bnx2x_848xx_set_led(struct bnx2x *bp, |
| 9572 | struct bnx2x_phy *phy) |
| 9573 | { |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 9574 | u16 val, offset, i; |
| 9575 | static struct bnx2x_reg_set reg_set[] = { |
| 9576 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080}, |
| 9577 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018}, |
| 9578 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, |
| 9579 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000}, |
| 9580 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, |
| 9581 | MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, |
| 9582 | {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} |
| 9583 | }; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9584 | /* PHYC_CTL_LED_CTL */ |
| 9585 | bnx2x_cl45_read(bp, phy, |
| 9586 | MDIO_PMA_DEVAD, |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 9587 | MDIO_PMA_REG_8481_LINK_SIGNAL, &val); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9588 | val &= 0xFE00; |
| 9589 | val |= 0x0092; |
| 9590 | |
| 9591 | bnx2x_cl45_write(bp, phy, |
| 9592 | MDIO_PMA_DEVAD, |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 9593 | MDIO_PMA_REG_8481_LINK_SIGNAL, val); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9594 | |
Sasha Levin | b5a0555 | 2012-12-20 09:11:24 +0000 | [diff] [blame] | 9595 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 9596 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, |
| 9597 | reg_set[i].val); |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9598 | |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 9599 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
| 9600 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9601 | offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; |
| 9602 | else |
| 9603 | offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; |
| 9604 | |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 9605 | /* stretch_en for LED3*/ |
| 9606 | bnx2x_cl45_read_or_write(bp, phy, |
| 9607 | MDIO_PMA_DEVAD, offset, |
| 9608 | MDIO_PMA_REG_84823_LED3_STRETCH_EN); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9609 | } |
| 9610 | |
Yaniv Rosner | 5c107fd | 2012-09-13 02:56:19 +0000 | [diff] [blame] | 9611 | static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy, |
| 9612 | struct link_params *params, |
| 9613 | u32 action) |
| 9614 | { |
| 9615 | struct bnx2x *bp = params->bp; |
| 9616 | switch (action) { |
| 9617 | case PHY_INIT: |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 9618 | if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && |
| 9619 | (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { |
Yaniv Rosner | 5c107fd | 2012-09-13 02:56:19 +0000 | [diff] [blame] | 9620 | /* Save spirom version */ |
| 9621 | bnx2x_save_848xx_spirom_version(phy, bp, params->port); |
| 9622 | } |
| 9623 | /* This phy uses the NIG latch mechanism since link indication |
| 9624 | * arrives through its LED4 and not via its LASI signal, so we |
| 9625 | * get steady signal instead of clear on read |
| 9626 | */ |
| 9627 | bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, |
| 9628 | 1 << NIG_LATCH_BC_ENABLE_MI_INT); |
| 9629 | |
| 9630 | bnx2x_848xx_set_led(bp, phy); |
| 9631 | break; |
| 9632 | } |
| 9633 | } |
| 9634 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 9635 | static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, |
| 9636 | struct link_params *params, |
| 9637 | struct link_vars *vars) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9638 | { |
| 9639 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 9640 | u16 autoneg_val, an_1000_val, an_10_100_val; |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 9641 | |
Yaniv Rosner | 5c107fd | 2012-09-13 02:56:19 +0000 | [diff] [blame] | 9642 | bnx2x_848xx_specific_func(phy, params, PHY_INIT); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9643 | bnx2x_cl45_write(bp, phy, |
| 9644 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); |
| 9645 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9646 | /* set 1000 speed advertisement */ |
| 9647 | bnx2x_cl45_read(bp, phy, |
| 9648 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, |
| 9649 | &an_1000_val); |
| 9650 | |
| 9651 | bnx2x_ext_phy_set_pause(params, phy, vars); |
| 9652 | bnx2x_cl45_read(bp, phy, |
| 9653 | MDIO_AN_DEVAD, |
| 9654 | MDIO_AN_REG_8481_LEGACY_AN_ADV, |
| 9655 | &an_10_100_val); |
| 9656 | bnx2x_cl45_read(bp, phy, |
| 9657 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, |
| 9658 | &autoneg_val); |
| 9659 | /* Disable forced speed */ |
| 9660 | autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); |
| 9661 | an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); |
| 9662 | |
| 9663 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
| 9664 | (phy->speed_cap_mask & |
| 9665 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || |
| 9666 | (phy->req_line_speed == SPEED_1000)) { |
| 9667 | an_1000_val |= (1<<8); |
| 9668 | autoneg_val |= (1<<9 | 1<<12); |
| 9669 | if (phy->req_duplex == DUPLEX_FULL) |
| 9670 | an_1000_val |= (1<<9); |
| 9671 | DP(NETIF_MSG_LINK, "Advertising 1G\n"); |
| 9672 | } else |
| 9673 | an_1000_val &= ~((1<<8) | (1<<9)); |
| 9674 | |
| 9675 | bnx2x_cl45_write(bp, phy, |
| 9676 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, |
| 9677 | an_1000_val); |
| 9678 | |
Yaniv Rosner | 0520e63 | 2011-07-05 01:06:59 +0000 | [diff] [blame] | 9679 | /* set 100 speed advertisement */ |
Yaniv Rosner | 7531832 | 2012-01-17 02:33:27 +0000 | [diff] [blame] | 9680 | if ((phy->req_line_speed == SPEED_AUTO_NEG) && |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9681 | (phy->speed_cap_mask & |
Yaniv Rosner | 0520e63 | 2011-07-05 01:06:59 +0000 | [diff] [blame] | 9682 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | |
Yaniv Rosner | 7531832 | 2012-01-17 02:33:27 +0000 | [diff] [blame] | 9683 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) { |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9684 | an_10_100_val |= (1<<7); |
| 9685 | /* Enable autoneg and restart autoneg for legacy speeds */ |
| 9686 | autoneg_val |= (1<<9 | 1<<12); |
| 9687 | |
| 9688 | if (phy->req_duplex == DUPLEX_FULL) |
| 9689 | an_10_100_val |= (1<<8); |
| 9690 | DP(NETIF_MSG_LINK, "Advertising 100M\n"); |
| 9691 | } |
| 9692 | /* set 10 speed advertisement */ |
| 9693 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
Yaniv Rosner | 0520e63 | 2011-07-05 01:06:59 +0000 | [diff] [blame] | 9694 | (phy->speed_cap_mask & |
| 9695 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | |
| 9696 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) && |
| 9697 | (phy->supported & |
| 9698 | (SUPPORTED_10baseT_Half | |
| 9699 | SUPPORTED_10baseT_Full)))) { |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9700 | an_10_100_val |= (1<<5); |
| 9701 | autoneg_val |= (1<<9 | 1<<12); |
| 9702 | if (phy->req_duplex == DUPLEX_FULL) |
| 9703 | an_10_100_val |= (1<<6); |
| 9704 | DP(NETIF_MSG_LINK, "Advertising 10M\n"); |
| 9705 | } |
| 9706 | |
| 9707 | /* Only 10/100 are allowed to work in FORCE mode */ |
Yaniv Rosner | 0520e63 | 2011-07-05 01:06:59 +0000 | [diff] [blame] | 9708 | if ((phy->req_line_speed == SPEED_100) && |
| 9709 | (phy->supported & |
| 9710 | (SUPPORTED_100baseT_Half | |
| 9711 | SUPPORTED_100baseT_Full))) { |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9712 | autoneg_val |= (1<<13); |
| 9713 | /* Enabled AUTO-MDIX when autoneg is disabled */ |
| 9714 | bnx2x_cl45_write(bp, phy, |
| 9715 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, |
| 9716 | (1<<15 | 1<<9 | 7<<0)); |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9717 | /* The PHY needs this set even for forced link. */ |
| 9718 | an_10_100_val |= (1<<8) | (1<<7); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9719 | DP(NETIF_MSG_LINK, "Setting 100M force\n"); |
| 9720 | } |
Yaniv Rosner | 0520e63 | 2011-07-05 01:06:59 +0000 | [diff] [blame] | 9721 | if ((phy->req_line_speed == SPEED_10) && |
| 9722 | (phy->supported & |
| 9723 | (SUPPORTED_10baseT_Half | |
| 9724 | SUPPORTED_10baseT_Full))) { |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9725 | /* Enabled AUTO-MDIX when autoneg is disabled */ |
| 9726 | bnx2x_cl45_write(bp, phy, |
| 9727 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, |
| 9728 | (1<<15 | 1<<9 | 7<<0)); |
| 9729 | DP(NETIF_MSG_LINK, "Setting 10M force\n"); |
| 9730 | } |
| 9731 | |
| 9732 | bnx2x_cl45_write(bp, phy, |
| 9733 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, |
| 9734 | an_10_100_val); |
| 9735 | |
| 9736 | if (phy->req_duplex == DUPLEX_FULL) |
| 9737 | autoneg_val |= (1<<8); |
| 9738 | |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 9739 | /* Always write this if this is not 84833/4. |
| 9740 | * For 84833/4, write it only when it's a forced speed. |
Yaniv Rosner | fd38f73e | 2011-08-02 22:59:53 +0000 | [diff] [blame] | 9741 | */ |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 9742 | if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && |
| 9743 | (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) || |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 9744 | ((autoneg_val & (1<<12)) == 0)) |
Yaniv Rosner | fd38f73e | 2011-08-02 22:59:53 +0000 | [diff] [blame] | 9745 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9746 | MDIO_AN_DEVAD, |
| 9747 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); |
| 9748 | |
| 9749 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
| 9750 | (phy->speed_cap_mask & |
| 9751 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || |
| 9752 | (phy->req_line_speed == SPEED_10000)) { |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 9753 | DP(NETIF_MSG_LINK, "Advertising 10G\n"); |
| 9754 | /* Restart autoneg for 10G*/ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9755 | |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 9756 | bnx2x_cl45_read_or_write( |
| 9757 | bp, phy, |
| 9758 | MDIO_AN_DEVAD, |
| 9759 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, |
| 9760 | 0x1000); |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9761 | bnx2x_cl45_write(bp, phy, |
| 9762 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, |
| 9763 | 0x3200); |
Yaniv Rosner | fd38f73e | 2011-08-02 22:59:53 +0000 | [diff] [blame] | 9764 | } else |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9765 | bnx2x_cl45_write(bp, phy, |
| 9766 | MDIO_AN_DEVAD, |
| 9767 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, |
| 9768 | 1); |
Yaniv Rosner | fd38f73e | 2011-08-02 22:59:53 +0000 | [diff] [blame] | 9769 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9770 | return 0; |
| 9771 | } |
| 9772 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 9773 | static int bnx2x_8481_config_init(struct bnx2x_phy *phy, |
| 9774 | struct link_params *params, |
| 9775 | struct link_vars *vars) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9776 | { |
| 9777 | struct bnx2x *bp = params->bp; |
| 9778 | /* Restore normal power mode*/ |
| 9779 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 9780 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9781 | |
| 9782 | /* HW reset */ |
| 9783 | bnx2x_ext_phy_hw_reset(bp, params->port); |
Yaniv Rosner | 6d870c3 | 2011-01-31 04:22:20 +0000 | [diff] [blame] | 9784 | bnx2x_wait_reset_complete(bp, phy, params); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9785 | |
| 9786 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
| 9787 | return bnx2x_848xx_cmn_config_init(phy, params, vars); |
| 9788 | } |
| 9789 | |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9790 | #define PHY84833_CMDHDLR_WAIT 300 |
| 9791 | #define PHY84833_CMDHDLR_MAX_ARGS 5 |
| 9792 | static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 9793 | struct link_params *params, u16 fw_cmd, |
| 9794 | u16 cmd_args[], int argc) |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9795 | { |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 9796 | int idx; |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9797 | u16 val; |
| 9798 | struct bnx2x *bp = params->bp; |
| 9799 | /* Write CMD_OPEN_OVERRIDE to STATUS reg */ |
| 9800 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
| 9801 | MDIO_84833_CMD_HDLR_STATUS, |
| 9802 | PHY84833_STATUS_CMD_OPEN_OVERRIDE); |
| 9803 | for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { |
| 9804 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
| 9805 | MDIO_84833_CMD_HDLR_STATUS, &val); |
| 9806 | if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) |
| 9807 | break; |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 9808 | usleep_range(1000, 2000); |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9809 | } |
| 9810 | if (idx >= PHY84833_CMDHDLR_WAIT) { |
| 9811 | DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); |
| 9812 | return -EINVAL; |
| 9813 | } |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 9814 | |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9815 | /* Prepare argument(s) and issue command */ |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 9816 | for (idx = 0; idx < argc; idx++) { |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9817 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
| 9818 | MDIO_84833_CMD_HDLR_DATA1 + idx, |
| 9819 | cmd_args[idx]); |
| 9820 | } |
| 9821 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
| 9822 | MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); |
| 9823 | for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { |
| 9824 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
| 9825 | MDIO_84833_CMD_HDLR_STATUS, &val); |
| 9826 | if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || |
| 9827 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) |
| 9828 | break; |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 9829 | usleep_range(1000, 2000); |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9830 | } |
| 9831 | if ((idx >= PHY84833_CMDHDLR_WAIT) || |
| 9832 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { |
| 9833 | DP(NETIF_MSG_LINK, "FW cmd failed.\n"); |
| 9834 | return -EINVAL; |
| 9835 | } |
| 9836 | /* Gather returning data */ |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 9837 | for (idx = 0; idx < argc; idx++) { |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9838 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
| 9839 | MDIO_84833_CMD_HDLR_DATA1 + idx, |
| 9840 | &cmd_args[idx]); |
| 9841 | } |
| 9842 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
| 9843 | MDIO_84833_CMD_HDLR_STATUS, |
| 9844 | PHY84833_STATUS_CMD_CLEAR_COMPLETE); |
| 9845 | return 0; |
| 9846 | } |
| 9847 | |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 9848 | static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy, |
| 9849 | struct link_params *params, |
| 9850 | struct link_vars *vars) |
| 9851 | { |
Yaniv Rosner | 0520e63 | 2011-07-05 01:06:59 +0000 | [diff] [blame] | 9852 | u32 pair_swap; |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9853 | u16 data[PHY84833_CMDHDLR_MAX_ARGS]; |
| 9854 | int status; |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 9855 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 9856 | |
Yaniv Rosner | 0520e63 | 2011-07-05 01:06:59 +0000 | [diff] [blame] | 9857 | /* Check for configuration. */ |
| 9858 | pair_swap = REG_RD(bp, params->shmem_base + |
| 9859 | offsetof(struct shmem_region, |
| 9860 | dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & |
| 9861 | PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; |
| 9862 | |
| 9863 | if (pair_swap == 0) |
| 9864 | return 0; |
| 9865 | |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9866 | /* Only the second argument is used for this command */ |
| 9867 | data[1] = (u16)pair_swap; |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 9868 | |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9869 | status = bnx2x_84833_cmd_hdlr(phy, params, |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 9870 | PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS); |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9871 | if (status == 0) |
| 9872 | DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]); |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 9873 | |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9874 | return status; |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 9875 | } |
| 9876 | |
Yaniv Rosner | 985848f | 2011-07-05 01:06:48 +0000 | [diff] [blame] | 9877 | static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp, |
| 9878 | u32 shmem_base_path[], |
| 9879 | u32 chip_id) |
Yaniv Rosner | 0d40f0d | 2011-06-14 01:34:27 +0000 | [diff] [blame] | 9880 | { |
| 9881 | u32 reset_pin[2]; |
| 9882 | u32 idx; |
| 9883 | u8 reset_gpios; |
| 9884 | if (CHIP_IS_E3(bp)) { |
| 9885 | /* Assume that these will be GPIOs, not EPIOs. */ |
| 9886 | for (idx = 0; idx < 2; idx++) { |
| 9887 | /* Map config param to register bit. */ |
| 9888 | reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + |
| 9889 | offsetof(struct shmem_region, |
| 9890 | dev_info.port_hw_config[0].e3_cmn_pin_cfg)); |
| 9891 | reset_pin[idx] = (reset_pin[idx] & |
| 9892 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> |
| 9893 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; |
| 9894 | reset_pin[idx] -= PIN_CFG_GPIO0_P0; |
| 9895 | reset_pin[idx] = (1 << reset_pin[idx]); |
| 9896 | } |
| 9897 | reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); |
| 9898 | } else { |
| 9899 | /* E2, look from diff place of shmem. */ |
| 9900 | for (idx = 0; idx < 2; idx++) { |
| 9901 | reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + |
| 9902 | offsetof(struct shmem_region, |
| 9903 | dev_info.port_hw_config[0].default_cfg)); |
| 9904 | reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; |
| 9905 | reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; |
| 9906 | reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; |
| 9907 | reset_pin[idx] = (1 << reset_pin[idx]); |
| 9908 | } |
| 9909 | reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); |
| 9910 | } |
| 9911 | |
Yaniv Rosner | 985848f | 2011-07-05 01:06:48 +0000 | [diff] [blame] | 9912 | return reset_gpios; |
| 9913 | } |
| 9914 | |
| 9915 | static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy, |
| 9916 | struct link_params *params) |
| 9917 | { |
| 9918 | struct bnx2x *bp = params->bp; |
| 9919 | u8 reset_gpios; |
| 9920 | u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + |
| 9921 | offsetof(struct shmem2_region, |
| 9922 | other_shmem_base_addr)); |
| 9923 | |
| 9924 | u32 shmem_base_path[2]; |
Yaniv Rosner | 99bf7f3 | 2012-04-04 01:29:01 +0000 | [diff] [blame] | 9925 | |
| 9926 | /* Work around for 84833 LED failure inside RESET status */ |
| 9927 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
| 9928 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, |
| 9929 | MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); |
| 9930 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
| 9931 | MDIO_AN_REG_8481_1G_100T_EXT_CTRL, |
| 9932 | MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); |
| 9933 | |
Yaniv Rosner | 985848f | 2011-07-05 01:06:48 +0000 | [diff] [blame] | 9934 | shmem_base_path[0] = params->shmem_base; |
| 9935 | shmem_base_path[1] = other_shmem_base_addr; |
| 9936 | |
| 9937 | reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, |
| 9938 | params->chip_id); |
| 9939 | |
| 9940 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); |
| 9941 | udelay(10); |
| 9942 | DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n", |
| 9943 | reset_gpios); |
| 9944 | |
| 9945 | return 0; |
| 9946 | } |
| 9947 | |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 9948 | static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy, |
| 9949 | struct link_params *params, |
| 9950 | struct link_vars *vars) |
| 9951 | { |
| 9952 | int rc; |
| 9953 | struct bnx2x *bp = params->bp; |
| 9954 | u16 cmd_args = 0; |
| 9955 | |
| 9956 | DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n"); |
| 9957 | |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 9958 | /* Prevent Phy from working in EEE and advertising it */ |
| 9959 | rc = bnx2x_84833_cmd_hdlr(phy, params, |
| 9960 | PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 9961 | if (rc) { |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 9962 | DP(NETIF_MSG_LINK, "EEE disable failed.\n"); |
| 9963 | return rc; |
| 9964 | } |
| 9965 | |
Yuval Mintz | ec4010e | 2012-09-10 05:51:06 +0000 | [diff] [blame] | 9966 | return bnx2x_eee_disable(phy, params, vars); |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 9967 | } |
| 9968 | |
| 9969 | static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy, |
| 9970 | struct link_params *params, |
| 9971 | struct link_vars *vars) |
| 9972 | { |
| 9973 | int rc; |
| 9974 | struct bnx2x *bp = params->bp; |
| 9975 | u16 cmd_args = 1; |
| 9976 | |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 9977 | rc = bnx2x_84833_cmd_hdlr(phy, params, |
| 9978 | PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 9979 | if (rc) { |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 9980 | DP(NETIF_MSG_LINK, "EEE enable failed.\n"); |
| 9981 | return rc; |
| 9982 | } |
| 9983 | |
Yuval Mintz | ec4010e | 2012-09-10 05:51:06 +0000 | [diff] [blame] | 9984 | return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 9985 | } |
| 9986 | |
Yaniv Rosner | a89a1d4 | 2011-07-05 01:07:05 +0000 | [diff] [blame] | 9987 | #define PHY84833_CONSTANT_LATENCY 1193 |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 9988 | static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, |
| 9989 | struct link_params *params, |
| 9990 | struct link_vars *vars) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 9991 | { |
| 9992 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 6a71bbe | 2010-11-01 05:32:31 +0000 | [diff] [blame] | 9993 | u8 port, initialize = 1; |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 9994 | u16 val; |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 9995 | u32 actual_phy_selection; |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 9996 | u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 9997 | int rc = 0; |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 9998 | |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 9999 | usleep_range(1000, 2000); |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 10000 | |
Yuval Mintz | 5481388 | 2012-06-16 20:27:15 +0000 | [diff] [blame] | 10001 | if (!(CHIP_IS_E1x(bp))) |
Yaniv Rosner | 6a71bbe | 2010-11-01 05:32:31 +0000 | [diff] [blame] | 10002 | port = BP_PATH(bp); |
| 10003 | else |
| 10004 | port = params->port; |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 10005 | |
| 10006 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { |
| 10007 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, |
| 10008 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, |
| 10009 | port); |
| 10010 | } else { |
Yaniv Rosner | 985848f | 2011-07-05 01:06:48 +0000 | [diff] [blame] | 10011 | /* MDIO reset */ |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 10012 | bnx2x_cl45_write(bp, phy, |
| 10013 | MDIO_PMA_DEVAD, |
| 10014 | MDIO_PMA_REG_CTRL, 0x8000); |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 10015 | } |
| 10016 | |
| 10017 | bnx2x_wait_reset_complete(bp, phy, params); |
| 10018 | |
| 10019 | /* Wait for GPHY to come out of reset */ |
| 10020 | msleep(50); |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 10021 | if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && |
| 10022 | (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 10023 | /* BCM84823 requires that XGXS links up first @ 10G for normal |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 10024 | * behavior. |
| 10025 | */ |
| 10026 | u16 temp; |
| 10027 | temp = vars->line_speed; |
| 10028 | vars->line_speed = SPEED_10000; |
| 10029 | bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); |
| 10030 | bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); |
| 10031 | vars->line_speed = temp; |
| 10032 | } |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10033 | |
| 10034 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 10035 | MDIO_CTL_REG_84823_MEDIA, &val); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10036 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | |
| 10037 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK | |
| 10038 | MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | |
| 10039 | MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | |
| 10040 | MDIO_CTL_REG_84823_MEDIA_FIBER_1G); |
Yaniv Rosner | 0d40f0d | 2011-06-14 01:34:27 +0000 | [diff] [blame] | 10041 | |
| 10042 | if (CHIP_IS_E3(bp)) { |
| 10043 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | |
| 10044 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK); |
| 10045 | } else { |
| 10046 | val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | |
| 10047 | MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); |
| 10048 | } |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10049 | |
| 10050 | actual_phy_selection = bnx2x_phy_selection(params); |
| 10051 | |
| 10052 | switch (actual_phy_selection) { |
| 10053 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 10054 | /* Do nothing. Essentially this is like the priority copper */ |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10055 | break; |
| 10056 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: |
| 10057 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; |
| 10058 | break; |
| 10059 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: |
| 10060 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; |
| 10061 | break; |
| 10062 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: |
| 10063 | /* Do nothing here. The first PHY won't be initialized at all */ |
| 10064 | break; |
| 10065 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: |
| 10066 | val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; |
| 10067 | initialize = 0; |
| 10068 | break; |
| 10069 | } |
| 10070 | if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) |
| 10071 | val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; |
| 10072 | |
| 10073 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 10074 | MDIO_CTL_REG_84823_MEDIA, val); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10075 | DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", |
| 10076 | params->multi_phy_config, val); |
| 10077 | |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 10078 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
| 10079 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 10080 | bnx2x_84833_pair_swap_cfg(phy, params, vars); |
Yaniv Rosner | a89a1d4 | 2011-07-05 01:07:05 +0000 | [diff] [blame] | 10081 | |
Yaniv Rosner | 096b952 | 2012-01-17 02:33:28 +0000 | [diff] [blame] | 10082 | /* Keep AutogrEEEn disabled. */ |
| 10083 | cmd_args[0] = 0x0; |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 10084 | cmd_args[1] = 0x0; |
| 10085 | cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; |
| 10086 | cmd_args[3] = PHY84833_CONSTANT_LATENCY; |
| 10087 | rc = bnx2x_84833_cmd_hdlr(phy, params, |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 10088 | PHY84833_CMD_SET_EEE_MODE, cmd_args, |
| 10089 | PHY84833_CMDHDLR_MAX_ARGS); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 10090 | if (rc) |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 10091 | DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n"); |
| 10092 | } |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10093 | if (initialize) |
| 10094 | rc = bnx2x_848xx_cmn_config_init(phy, params, vars); |
| 10095 | else |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 10096 | bnx2x_save_848xx_spirom_version(phy, bp, params->port); |
Yaniv Rosner | a89a1d4 | 2011-07-05 01:07:05 +0000 | [diff] [blame] | 10097 | /* 84833 PHY has a better feature and doesn't need to support this. */ |
| 10098 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 10099 | u32 cms_enable = REG_RD(bp, params->shmem_base + |
Yaniv Rosner | 1bef68e | 2011-01-31 04:22:46 +0000 | [diff] [blame] | 10100 | offsetof(struct shmem_region, |
| 10101 | dev_info.port_hw_config[params->port].default_cfg)) & |
| 10102 | PORT_HW_CFG_ENABLE_CMS_MASK; |
| 10103 | |
Yaniv Rosner | a89a1d4 | 2011-07-05 01:07:05 +0000 | [diff] [blame] | 10104 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
| 10105 | MDIO_CTL_REG_84823_USER_CTRL_REG, &val); |
| 10106 | if (cms_enable) |
| 10107 | val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; |
| 10108 | else |
| 10109 | val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; |
| 10110 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
| 10111 | MDIO_CTL_REG_84823_USER_CTRL_REG, val); |
| 10112 | } |
Yaniv Rosner | 1bef68e | 2011-01-31 04:22:46 +0000 | [diff] [blame] | 10113 | |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 10114 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
| 10115 | MDIO_84833_TOP_CFG_FW_REV, &val); |
| 10116 | |
| 10117 | /* Configure EEE support */ |
Yuval Mintz | f6b6eb6 | 2012-09-10 05:51:07 +0000 | [diff] [blame] | 10118 | if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && |
| 10119 | (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && |
| 10120 | bnx2x_eee_has_cap(params)) { |
Yuval Mintz | ec4010e | 2012-09-10 05:51:06 +0000 | [diff] [blame] | 10121 | rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 10122 | if (rc) { |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 10123 | DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); |
| 10124 | bnx2x_8483x_disable_eee(phy, params, vars); |
| 10125 | return rc; |
| 10126 | } |
| 10127 | |
Yaniv Rosner | fd5dfca | 2012-11-27 03:46:36 +0000 | [diff] [blame] | 10128 | if ((phy->req_duplex == DUPLEX_FULL) && |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 10129 | (params->eee_mode & EEE_MODE_ADV_LPI) && |
| 10130 | (bnx2x_eee_calc_timer(params) || |
| 10131 | !(params->eee_mode & EEE_MODE_ENABLE_LPI))) |
| 10132 | rc = bnx2x_8483x_enable_eee(phy, params, vars); |
| 10133 | else |
| 10134 | rc = bnx2x_8483x_disable_eee(phy, params, vars); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 10135 | if (rc) { |
Masanari Iida | efc7ce0 | 2012-11-02 04:36:17 +0000 | [diff] [blame] | 10136 | DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n"); |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 10137 | return rc; |
| 10138 | } |
| 10139 | } else { |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 10140 | vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; |
| 10141 | } |
| 10142 | |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 10143 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
| 10144 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 10145 | /* Bring PHY out of super isolate mode as the final step. */ |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 10146 | bnx2x_cl45_read_and_write(bp, phy, |
| 10147 | MDIO_CTL_DEVAD, |
| 10148 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, |
| 10149 | (u16)~MDIO_84833_SUPER_ISOLATE); |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 10150 | } |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10151 | return rc; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10152 | } |
| 10153 | |
| 10154 | static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10155 | struct link_params *params, |
| 10156 | struct link_vars *vars) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10157 | { |
| 10158 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 10159 | u16 val, val1, val2; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10160 | u8 link_up = 0; |
| 10161 | |
Yaniv Rosner | c87bca1 | 2011-01-31 04:22:41 +0000 | [diff] [blame] | 10162 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10163 | /* Check 10G-BaseT link status */ |
| 10164 | /* Check PMD signal ok */ |
| 10165 | bnx2x_cl45_read(bp, phy, |
| 10166 | MDIO_AN_DEVAD, 0xFFFA, &val1); |
| 10167 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 10168 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10169 | &val2); |
| 10170 | DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); |
| 10171 | |
| 10172 | /* Check link 10G */ |
| 10173 | if (val2 & (1<<11)) { |
| 10174 | vars->line_speed = SPEED_10000; |
Yaniv Rosner | 791f18c | 2011-01-18 04:33:42 +0000 | [diff] [blame] | 10175 | vars->duplex = DUPLEX_FULL; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10176 | link_up = 1; |
| 10177 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); |
| 10178 | } else { /* Check Legacy speed link */ |
| 10179 | u16 legacy_status, legacy_speed; |
| 10180 | |
| 10181 | /* Enable expansion register 0x42 (Operation mode status) */ |
| 10182 | bnx2x_cl45_write(bp, phy, |
| 10183 | MDIO_AN_DEVAD, |
| 10184 | MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); |
| 10185 | |
| 10186 | /* Get legacy speed operation status */ |
| 10187 | bnx2x_cl45_read(bp, phy, |
| 10188 | MDIO_AN_DEVAD, |
| 10189 | MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, |
| 10190 | &legacy_status); |
| 10191 | |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 10192 | DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n", |
| 10193 | legacy_status); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10194 | link_up = ((legacy_status & (1<<11)) == (1<<11)); |
Yuval Mintz | 1440090 | 2012-06-20 19:05:20 +0000 | [diff] [blame] | 10195 | legacy_speed = (legacy_status & (3<<9)); |
| 10196 | if (legacy_speed == (0<<9)) |
| 10197 | vars->line_speed = SPEED_10; |
| 10198 | else if (legacy_speed == (1<<9)) |
| 10199 | vars->line_speed = SPEED_100; |
| 10200 | else if (legacy_speed == (2<<9)) |
| 10201 | vars->line_speed = SPEED_1000; |
| 10202 | else { /* Should not happen: Treat as link down */ |
| 10203 | vars->line_speed = 0; |
| 10204 | link_up = 0; |
| 10205 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10206 | |
Yuval Mintz | 1440090 | 2012-06-20 19:05:20 +0000 | [diff] [blame] | 10207 | if (link_up) { |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10208 | if (legacy_status & (1<<8)) |
| 10209 | vars->duplex = DUPLEX_FULL; |
| 10210 | else |
| 10211 | vars->duplex = DUPLEX_HALF; |
| 10212 | |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 10213 | DP(NETIF_MSG_LINK, |
| 10214 | "Link is up in %dMbps, is_duplex_full= %d\n", |
| 10215 | vars->line_speed, |
| 10216 | (vars->duplex == DUPLEX_FULL)); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10217 | /* Check legacy speed AN resolution */ |
| 10218 | bnx2x_cl45_read(bp, phy, |
| 10219 | MDIO_AN_DEVAD, |
| 10220 | MDIO_AN_REG_8481_LEGACY_MII_STATUS, |
| 10221 | &val); |
| 10222 | if (val & (1<<5)) |
| 10223 | vars->link_status |= |
| 10224 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; |
| 10225 | bnx2x_cl45_read(bp, phy, |
| 10226 | MDIO_AN_DEVAD, |
| 10227 | MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, |
| 10228 | &val); |
| 10229 | if ((val & (1<<0)) == 0) |
| 10230 | vars->link_status |= |
| 10231 | LINK_STATUS_PARALLEL_DETECTION_USED; |
| 10232 | } |
| 10233 | } |
| 10234 | if (link_up) { |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 10235 | DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n", |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10236 | vars->line_speed); |
| 10237 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 10238 | |
| 10239 | /* Read LP advertised speeds */ |
| 10240 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, |
| 10241 | MDIO_AN_REG_CL37_FC_LP, &val); |
| 10242 | if (val & (1<<5)) |
| 10243 | vars->link_status |= |
| 10244 | LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; |
| 10245 | if (val & (1<<6)) |
| 10246 | vars->link_status |= |
| 10247 | LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; |
| 10248 | if (val & (1<<7)) |
| 10249 | vars->link_status |= |
| 10250 | LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; |
| 10251 | if (val & (1<<8)) |
| 10252 | vars->link_status |= |
| 10253 | LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; |
| 10254 | if (val & (1<<9)) |
| 10255 | vars->link_status |= |
| 10256 | LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; |
| 10257 | |
| 10258 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, |
| 10259 | MDIO_AN_REG_1000T_STATUS, &val); |
| 10260 | |
| 10261 | if (val & (1<<10)) |
| 10262 | vars->link_status |= |
| 10263 | LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; |
| 10264 | if (val & (1<<11)) |
| 10265 | vars->link_status |= |
| 10266 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; |
| 10267 | |
| 10268 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, |
| 10269 | MDIO_AN_REG_MASTER_STATUS, &val); |
| 10270 | |
| 10271 | if (val & (1<<11)) |
| 10272 | vars->link_status |= |
| 10273 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 10274 | |
| 10275 | /* Determine if EEE was negotiated */ |
Yuval Mintz | ec4010e | 2012-09-10 05:51:06 +0000 | [diff] [blame] | 10276 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) |
| 10277 | bnx2x_eee_an_resolve(phy, params, vars); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10278 | } |
| 10279 | |
| 10280 | return link_up; |
| 10281 | } |
| 10282 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 10283 | static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10284 | { |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 10285 | int status = 0; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10286 | u32 spirom_ver; |
| 10287 | spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); |
| 10288 | status = bnx2x_format_ver(spirom_ver, str, len); |
| 10289 | return status; |
| 10290 | } |
| 10291 | |
| 10292 | static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, |
| 10293 | struct link_params *params) |
| 10294 | { |
| 10295 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10296 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10297 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10298 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10299 | } |
| 10300 | |
| 10301 | static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, |
| 10302 | struct link_params *params) |
| 10303 | { |
| 10304 | bnx2x_cl45_write(params->bp, phy, |
| 10305 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); |
| 10306 | bnx2x_cl45_write(params->bp, phy, |
| 10307 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); |
| 10308 | } |
| 10309 | |
| 10310 | static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, |
| 10311 | struct link_params *params) |
| 10312 | { |
| 10313 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 6a71bbe | 2010-11-01 05:32:31 +0000 | [diff] [blame] | 10314 | u8 port; |
Yaniv Rosner | 0d40f0d | 2011-06-14 01:34:27 +0000 | [diff] [blame] | 10315 | u16 val16; |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 10316 | |
Yaniv Rosner | f93fb01 | 2012-04-04 01:29:02 +0000 | [diff] [blame] | 10317 | if (!(CHIP_IS_E1x(bp))) |
Yaniv Rosner | 6a71bbe | 2010-11-01 05:32:31 +0000 | [diff] [blame] | 10318 | port = BP_PATH(bp); |
| 10319 | else |
| 10320 | port = params->port; |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 10321 | |
| 10322 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { |
| 10323 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, |
| 10324 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
| 10325 | port); |
| 10326 | } else { |
Yaniv Rosner | 0d40f0d | 2011-06-14 01:34:27 +0000 | [diff] [blame] | 10327 | bnx2x_cl45_read(bp, phy, |
| 10328 | MDIO_CTL_DEVAD, |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 10329 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); |
| 10330 | val16 |= MDIO_84833_SUPER_ISOLATE; |
Yaniv Rosner | fd38f73e | 2011-08-02 22:59:53 +0000 | [diff] [blame] | 10331 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 10332 | MDIO_CTL_DEVAD, |
| 10333 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 10334 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10335 | } |
| 10336 | |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10337 | static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, |
| 10338 | struct link_params *params, u8 mode) |
| 10339 | { |
| 10340 | struct bnx2x *bp = params->bp; |
| 10341 | u16 val; |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 10342 | u8 port; |
| 10343 | |
Yaniv Rosner | f93fb01 | 2012-04-04 01:29:02 +0000 | [diff] [blame] | 10344 | if (!(CHIP_IS_E1x(bp))) |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 10345 | port = BP_PATH(bp); |
| 10346 | else |
| 10347 | port = params->port; |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10348 | |
| 10349 | switch (mode) { |
| 10350 | case LED_MODE_OFF: |
| 10351 | |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 10352 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10353 | |
| 10354 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == |
| 10355 | SHARED_HW_CFG_LED_EXTPHY1) { |
| 10356 | |
| 10357 | /* Set LED masks */ |
| 10358 | bnx2x_cl45_write(bp, phy, |
| 10359 | MDIO_PMA_DEVAD, |
| 10360 | MDIO_PMA_REG_8481_LED1_MASK, |
| 10361 | 0x0); |
| 10362 | |
| 10363 | bnx2x_cl45_write(bp, phy, |
| 10364 | MDIO_PMA_DEVAD, |
| 10365 | MDIO_PMA_REG_8481_LED2_MASK, |
| 10366 | 0x0); |
| 10367 | |
| 10368 | bnx2x_cl45_write(bp, phy, |
| 10369 | MDIO_PMA_DEVAD, |
| 10370 | MDIO_PMA_REG_8481_LED3_MASK, |
| 10371 | 0x0); |
| 10372 | |
| 10373 | bnx2x_cl45_write(bp, phy, |
| 10374 | MDIO_PMA_DEVAD, |
| 10375 | MDIO_PMA_REG_8481_LED5_MASK, |
| 10376 | 0x0); |
| 10377 | |
| 10378 | } else { |
| 10379 | bnx2x_cl45_write(bp, phy, |
| 10380 | MDIO_PMA_DEVAD, |
| 10381 | MDIO_PMA_REG_8481_LED1_MASK, |
| 10382 | 0x0); |
| 10383 | } |
| 10384 | break; |
| 10385 | case LED_MODE_FRONT_PANEL_OFF: |
| 10386 | |
| 10387 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 10388 | port); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10389 | |
| 10390 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == |
| 10391 | SHARED_HW_CFG_LED_EXTPHY1) { |
| 10392 | |
| 10393 | /* Set LED masks */ |
| 10394 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10395 | MDIO_PMA_DEVAD, |
| 10396 | MDIO_PMA_REG_8481_LED1_MASK, |
| 10397 | 0x0); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10398 | |
| 10399 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10400 | MDIO_PMA_DEVAD, |
| 10401 | MDIO_PMA_REG_8481_LED2_MASK, |
| 10402 | 0x0); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10403 | |
| 10404 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10405 | MDIO_PMA_DEVAD, |
| 10406 | MDIO_PMA_REG_8481_LED3_MASK, |
| 10407 | 0x0); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10408 | |
| 10409 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10410 | MDIO_PMA_DEVAD, |
| 10411 | MDIO_PMA_REG_8481_LED5_MASK, |
| 10412 | 0x20); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10413 | |
| 10414 | } else { |
| 10415 | bnx2x_cl45_write(bp, phy, |
| 10416 | MDIO_PMA_DEVAD, |
| 10417 | MDIO_PMA_REG_8481_LED1_MASK, |
| 10418 | 0x0); |
| 10419 | } |
| 10420 | break; |
| 10421 | case LED_MODE_ON: |
| 10422 | |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 10423 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10424 | |
| 10425 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == |
| 10426 | SHARED_HW_CFG_LED_EXTPHY1) { |
| 10427 | /* Set control reg */ |
| 10428 | bnx2x_cl45_read(bp, phy, |
| 10429 | MDIO_PMA_DEVAD, |
| 10430 | MDIO_PMA_REG_8481_LINK_SIGNAL, |
| 10431 | &val); |
| 10432 | val &= 0x8000; |
| 10433 | val |= 0x2492; |
| 10434 | |
| 10435 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10436 | MDIO_PMA_DEVAD, |
| 10437 | MDIO_PMA_REG_8481_LINK_SIGNAL, |
| 10438 | val); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10439 | |
| 10440 | /* Set LED masks */ |
| 10441 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10442 | MDIO_PMA_DEVAD, |
| 10443 | MDIO_PMA_REG_8481_LED1_MASK, |
| 10444 | 0x0); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10445 | |
| 10446 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10447 | MDIO_PMA_DEVAD, |
| 10448 | MDIO_PMA_REG_8481_LED2_MASK, |
| 10449 | 0x20); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10450 | |
| 10451 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10452 | MDIO_PMA_DEVAD, |
| 10453 | MDIO_PMA_REG_8481_LED3_MASK, |
| 10454 | 0x20); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10455 | |
| 10456 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10457 | MDIO_PMA_DEVAD, |
| 10458 | MDIO_PMA_REG_8481_LED5_MASK, |
| 10459 | 0x0); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10460 | } else { |
| 10461 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10462 | MDIO_PMA_DEVAD, |
| 10463 | MDIO_PMA_REG_8481_LED1_MASK, |
| 10464 | 0x20); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10465 | } |
| 10466 | break; |
| 10467 | |
| 10468 | case LED_MODE_OPER: |
| 10469 | |
Yaniv Rosner | bac27bd | 2011-05-31 21:28:10 +0000 | [diff] [blame] | 10470 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10471 | |
| 10472 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == |
| 10473 | SHARED_HW_CFG_LED_EXTPHY1) { |
| 10474 | |
| 10475 | /* Set control reg */ |
| 10476 | bnx2x_cl45_read(bp, phy, |
| 10477 | MDIO_PMA_DEVAD, |
| 10478 | MDIO_PMA_REG_8481_LINK_SIGNAL, |
| 10479 | &val); |
| 10480 | |
| 10481 | if (!((val & |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10482 | MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) |
| 10483 | >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 10484 | DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n"); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10485 | bnx2x_cl45_write(bp, phy, |
| 10486 | MDIO_PMA_DEVAD, |
| 10487 | MDIO_PMA_REG_8481_LINK_SIGNAL, |
| 10488 | 0xa492); |
| 10489 | } |
| 10490 | |
| 10491 | /* Set LED masks */ |
| 10492 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10493 | MDIO_PMA_DEVAD, |
| 10494 | MDIO_PMA_REG_8481_LED1_MASK, |
| 10495 | 0x10); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10496 | |
| 10497 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10498 | MDIO_PMA_DEVAD, |
| 10499 | MDIO_PMA_REG_8481_LED2_MASK, |
| 10500 | 0x80); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10501 | |
| 10502 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10503 | MDIO_PMA_DEVAD, |
| 10504 | MDIO_PMA_REG_8481_LED3_MASK, |
| 10505 | 0x98); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10506 | |
| 10507 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 10508 | MDIO_PMA_DEVAD, |
| 10509 | MDIO_PMA_REG_8481_LED5_MASK, |
| 10510 | 0x40); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10511 | |
| 10512 | } else { |
| 10513 | bnx2x_cl45_write(bp, phy, |
| 10514 | MDIO_PMA_DEVAD, |
| 10515 | MDIO_PMA_REG_8481_LED1_MASK, |
| 10516 | 0x80); |
Yaniv Rosner | 53eda06 | 2011-01-30 04:14:55 +0000 | [diff] [blame] | 10517 | |
| 10518 | /* Tell LED3 to blink on source */ |
| 10519 | bnx2x_cl45_read(bp, phy, |
| 10520 | MDIO_PMA_DEVAD, |
| 10521 | MDIO_PMA_REG_8481_LINK_SIGNAL, |
| 10522 | &val); |
| 10523 | val &= ~(7<<6); |
| 10524 | val |= (1<<6); /* A83B[8:6]= 1 */ |
| 10525 | bnx2x_cl45_write(bp, phy, |
| 10526 | MDIO_PMA_DEVAD, |
| 10527 | MDIO_PMA_REG_8481_LINK_SIGNAL, |
| 10528 | val); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10529 | } |
| 10530 | break; |
| 10531 | } |
Yaniv Rosner | 0d40f0d | 2011-06-14 01:34:27 +0000 | [diff] [blame] | 10532 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 10533 | /* This is a workaround for E3+84833 until autoneg |
Yaniv Rosner | 0d40f0d | 2011-06-14 01:34:27 +0000 | [diff] [blame] | 10534 | * restart is fixed in f/w |
| 10535 | */ |
| 10536 | if (CHIP_IS_E3(bp)) { |
| 10537 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 10538 | MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); |
| 10539 | } |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 10540 | } |
Yaniv Rosner | 0d40f0d | 2011-06-14 01:34:27 +0000 | [diff] [blame] | 10541 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10542 | /******************************************************************/ |
Yaniv Rosner | 52c4d6c | 2011-07-05 01:06:34 +0000 | [diff] [blame] | 10543 | /* 54618SE PHY SECTION */ |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10544 | /******************************************************************/ |
Yaniv Rosner | 5c107fd | 2012-09-13 02:56:19 +0000 | [diff] [blame] | 10545 | static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy, |
| 10546 | struct link_params *params, |
| 10547 | u32 action) |
| 10548 | { |
| 10549 | struct bnx2x *bp = params->bp; |
| 10550 | u16 temp; |
| 10551 | switch (action) { |
| 10552 | case PHY_INIT: |
| 10553 | /* Configure LED4: set to INTR (0x6). */ |
| 10554 | /* Accessing shadow register 0xe. */ |
| 10555 | bnx2x_cl22_write(bp, phy, |
| 10556 | MDIO_REG_GPHY_SHADOW, |
| 10557 | MDIO_REG_GPHY_SHADOW_LED_SEL2); |
| 10558 | bnx2x_cl22_read(bp, phy, |
| 10559 | MDIO_REG_GPHY_SHADOW, |
| 10560 | &temp); |
| 10561 | temp &= ~(0xf << 4); |
| 10562 | temp |= (0x6 << 4); |
| 10563 | bnx2x_cl22_write(bp, phy, |
| 10564 | MDIO_REG_GPHY_SHADOW, |
| 10565 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); |
| 10566 | /* Configure INTR based on link status change. */ |
| 10567 | bnx2x_cl22_write(bp, phy, |
| 10568 | MDIO_REG_INTR_MASK, |
| 10569 | ~MDIO_REG_INTR_MASK_LINK_STATUS); |
| 10570 | break; |
| 10571 | } |
| 10572 | } |
| 10573 | |
Yaniv Rosner | 52c4d6c | 2011-07-05 01:06:34 +0000 | [diff] [blame] | 10574 | static int bnx2x_54618se_config_init(struct bnx2x_phy *phy, |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10575 | struct link_params *params, |
| 10576 | struct link_vars *vars) |
| 10577 | { |
| 10578 | struct bnx2x *bp = params->bp; |
| 10579 | u8 port; |
| 10580 | u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; |
| 10581 | u32 cfg_pin; |
| 10582 | |
Yaniv Rosner | 52c4d6c | 2011-07-05 01:06:34 +0000 | [diff] [blame] | 10583 | DP(NETIF_MSG_LINK, "54618SE cfg init\n"); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 10584 | usleep_range(1000, 2000); |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10585 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 10586 | /* This works with E3 only, no need to check the chip |
Yaniv Rosner | 2f751a8 | 2011-11-28 00:49:52 +0000 | [diff] [blame] | 10587 | * before determining the port. |
| 10588 | */ |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10589 | port = params->port; |
| 10590 | |
| 10591 | cfg_pin = (REG_RD(bp, params->shmem_base + |
| 10592 | offsetof(struct shmem_region, |
| 10593 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & |
| 10594 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> |
| 10595 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; |
| 10596 | |
| 10597 | /* Drive pin high to bring the GPHY out of reset. */ |
| 10598 | bnx2x_set_cfg_pin(bp, cfg_pin, 1); |
| 10599 | |
| 10600 | /* wait for GPHY to reset */ |
| 10601 | msleep(50); |
| 10602 | |
| 10603 | /* reset phy */ |
| 10604 | bnx2x_cl22_write(bp, phy, |
| 10605 | MDIO_PMA_REG_CTRL, 0x8000); |
| 10606 | bnx2x_wait_reset_complete(bp, phy, params); |
| 10607 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 10608 | /* Wait for GPHY to reset */ |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10609 | msleep(50); |
| 10610 | |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10611 | |
Yaniv Rosner | 5c107fd | 2012-09-13 02:56:19 +0000 | [diff] [blame] | 10612 | bnx2x_54618se_specific_func(phy, params, PHY_INIT); |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10613 | /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ |
| 10614 | bnx2x_cl22_write(bp, phy, |
| 10615 | MDIO_REG_GPHY_SHADOW, |
| 10616 | MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); |
| 10617 | bnx2x_cl22_read(bp, phy, |
| 10618 | MDIO_REG_GPHY_SHADOW, |
| 10619 | &temp); |
| 10620 | temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; |
| 10621 | bnx2x_cl22_write(bp, phy, |
| 10622 | MDIO_REG_GPHY_SHADOW, |
| 10623 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); |
| 10624 | |
| 10625 | /* Set up fc */ |
| 10626 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ |
| 10627 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); |
| 10628 | fc_val = 0; |
| 10629 | if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == |
| 10630 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) |
| 10631 | fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; |
| 10632 | |
| 10633 | if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == |
| 10634 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) |
| 10635 | fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; |
| 10636 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 10637 | /* Read all advertisement */ |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10638 | bnx2x_cl22_read(bp, phy, |
| 10639 | 0x09, |
| 10640 | &an_1000_val); |
| 10641 | |
| 10642 | bnx2x_cl22_read(bp, phy, |
| 10643 | 0x04, |
| 10644 | &an_10_100_val); |
| 10645 | |
| 10646 | bnx2x_cl22_read(bp, phy, |
| 10647 | MDIO_PMA_REG_CTRL, |
| 10648 | &autoneg_val); |
| 10649 | |
| 10650 | /* Disable forced speed */ |
| 10651 | autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); |
| 10652 | an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | |
| 10653 | (1<<11)); |
| 10654 | |
| 10655 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
| 10656 | (phy->speed_cap_mask & |
| 10657 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || |
| 10658 | (phy->req_line_speed == SPEED_1000)) { |
| 10659 | an_1000_val |= (1<<8); |
| 10660 | autoneg_val |= (1<<9 | 1<<12); |
| 10661 | if (phy->req_duplex == DUPLEX_FULL) |
| 10662 | an_1000_val |= (1<<9); |
| 10663 | DP(NETIF_MSG_LINK, "Advertising 1G\n"); |
| 10664 | } else |
| 10665 | an_1000_val &= ~((1<<8) | (1<<9)); |
| 10666 | |
| 10667 | bnx2x_cl22_write(bp, phy, |
| 10668 | 0x09, |
| 10669 | an_1000_val); |
| 10670 | bnx2x_cl22_read(bp, phy, |
| 10671 | 0x09, |
| 10672 | &an_1000_val); |
| 10673 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 10674 | /* Set 100 speed advertisement */ |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10675 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
| 10676 | (phy->speed_cap_mask & |
| 10677 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | |
| 10678 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) { |
| 10679 | an_10_100_val |= (1<<7); |
| 10680 | /* Enable autoneg and restart autoneg for legacy speeds */ |
| 10681 | autoneg_val |= (1<<9 | 1<<12); |
| 10682 | |
| 10683 | if (phy->req_duplex == DUPLEX_FULL) |
| 10684 | an_10_100_val |= (1<<8); |
| 10685 | DP(NETIF_MSG_LINK, "Advertising 100M\n"); |
| 10686 | } |
| 10687 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 10688 | /* Set 10 speed advertisement */ |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10689 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
| 10690 | (phy->speed_cap_mask & |
| 10691 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | |
| 10692 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) { |
| 10693 | an_10_100_val |= (1<<5); |
| 10694 | autoneg_val |= (1<<9 | 1<<12); |
| 10695 | if (phy->req_duplex == DUPLEX_FULL) |
| 10696 | an_10_100_val |= (1<<6); |
| 10697 | DP(NETIF_MSG_LINK, "Advertising 10M\n"); |
| 10698 | } |
| 10699 | |
| 10700 | /* Only 10/100 are allowed to work in FORCE mode */ |
| 10701 | if (phy->req_line_speed == SPEED_100) { |
| 10702 | autoneg_val |= (1<<13); |
| 10703 | /* Enabled AUTO-MDIX when autoneg is disabled */ |
| 10704 | bnx2x_cl22_write(bp, phy, |
| 10705 | 0x18, |
| 10706 | (1<<15 | 1<<9 | 7<<0)); |
| 10707 | DP(NETIF_MSG_LINK, "Setting 100M force\n"); |
| 10708 | } |
| 10709 | if (phy->req_line_speed == SPEED_10) { |
| 10710 | /* Enabled AUTO-MDIX when autoneg is disabled */ |
| 10711 | bnx2x_cl22_write(bp, phy, |
| 10712 | 0x18, |
| 10713 | (1<<15 | 1<<9 | 7<<0)); |
| 10714 | DP(NETIF_MSG_LINK, "Setting 10M force\n"); |
| 10715 | } |
| 10716 | |
Yuval Mintz | 26964bb | 2012-09-10 05:51:08 +0000 | [diff] [blame] | 10717 | if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) { |
| 10718 | int rc; |
| 10719 | |
| 10720 | bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, |
| 10721 | MDIO_REG_GPHY_EXP_ACCESS_TOP | |
| 10722 | MDIO_REG_GPHY_EXP_TOP_2K_BUF); |
| 10723 | bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); |
| 10724 | temp &= 0xfffe; |
| 10725 | bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); |
| 10726 | |
| 10727 | rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); |
| 10728 | if (rc) { |
| 10729 | DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); |
| 10730 | bnx2x_eee_disable(phy, params, vars); |
| 10731 | } else if ((params->eee_mode & EEE_MODE_ADV_LPI) && |
| 10732 | (phy->req_duplex == DUPLEX_FULL) && |
| 10733 | (bnx2x_eee_calc_timer(params) || |
| 10734 | !(params->eee_mode & EEE_MODE_ENABLE_LPI))) { |
| 10735 | /* Need to advertise EEE only when requested, |
| 10736 | * and either no LPI assertion was requested, |
| 10737 | * or it was requested and a valid timer was set. |
| 10738 | * Also notice full duplex is required for EEE. |
| 10739 | */ |
| 10740 | bnx2x_eee_advertise(phy, params, vars, |
| 10741 | SHMEM_EEE_1G_ADV); |
Yaniv Rosner | a89a1d4 | 2011-07-05 01:07:05 +0000 | [diff] [blame] | 10742 | } else { |
Yuval Mintz | 26964bb | 2012-09-10 05:51:08 +0000 | [diff] [blame] | 10743 | DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n"); |
| 10744 | bnx2x_eee_disable(phy, params, vars); |
Yaniv Rosner | a89a1d4 | 2011-07-05 01:07:05 +0000 | [diff] [blame] | 10745 | } |
Yuval Mintz | 26964bb | 2012-09-10 05:51:08 +0000 | [diff] [blame] | 10746 | } else { |
| 10747 | vars->eee_status &= ~SHMEM_EEE_1G_ADV << |
| 10748 | SHMEM_EEE_SUPPORTED_SHIFT; |
| 10749 | |
| 10750 | if (phy->flags & FLAGS_EEE) { |
| 10751 | /* Handle legacy auto-grEEEn */ |
| 10752 | if (params->feature_config_flags & |
| 10753 | FEATURE_CONFIG_AUTOGREEEN_ENABLED) { |
| 10754 | temp = 6; |
| 10755 | DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n"); |
| 10756 | } else { |
| 10757 | temp = 0; |
| 10758 | DP(NETIF_MSG_LINK, "Don't Adv. EEE\n"); |
| 10759 | } |
| 10760 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
| 10761 | MDIO_AN_REG_EEE_ADV, temp); |
| 10762 | } |
Yaniv Rosner | a89a1d4 | 2011-07-05 01:07:05 +0000 | [diff] [blame] | 10763 | } |
| 10764 | |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10765 | bnx2x_cl22_write(bp, phy, |
| 10766 | 0x04, |
| 10767 | an_10_100_val | fc_val); |
| 10768 | |
| 10769 | if (phy->req_duplex == DUPLEX_FULL) |
| 10770 | autoneg_val |= (1<<8); |
| 10771 | |
| 10772 | bnx2x_cl22_write(bp, phy, |
| 10773 | MDIO_PMA_REG_CTRL, autoneg_val); |
| 10774 | |
| 10775 | return 0; |
| 10776 | } |
| 10777 | |
Yaniv Rosner | 1d125bd | 2011-11-23 03:54:08 +0000 | [diff] [blame] | 10778 | |
| 10779 | static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy, |
| 10780 | struct link_params *params, u8 mode) |
| 10781 | { |
| 10782 | struct bnx2x *bp = params->bp; |
| 10783 | u16 temp; |
| 10784 | |
| 10785 | bnx2x_cl22_write(bp, phy, |
| 10786 | MDIO_REG_GPHY_SHADOW, |
| 10787 | MDIO_REG_GPHY_SHADOW_LED_SEL1); |
| 10788 | bnx2x_cl22_read(bp, phy, |
| 10789 | MDIO_REG_GPHY_SHADOW, |
| 10790 | &temp); |
| 10791 | temp &= 0xff00; |
| 10792 | |
| 10793 | DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode); |
| 10794 | switch (mode) { |
| 10795 | case LED_MODE_FRONT_PANEL_OFF: |
| 10796 | case LED_MODE_OFF: |
| 10797 | temp |= 0x00ee; |
| 10798 | break; |
| 10799 | case LED_MODE_OPER: |
| 10800 | temp |= 0x0001; |
| 10801 | break; |
| 10802 | case LED_MODE_ON: |
| 10803 | temp |= 0x00ff; |
| 10804 | break; |
| 10805 | default: |
| 10806 | break; |
| 10807 | } |
| 10808 | bnx2x_cl22_write(bp, phy, |
| 10809 | MDIO_REG_GPHY_SHADOW, |
| 10810 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); |
| 10811 | return; |
| 10812 | } |
| 10813 | |
| 10814 | |
Yaniv Rosner | 52c4d6c | 2011-07-05 01:06:34 +0000 | [diff] [blame] | 10815 | static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, |
| 10816 | struct link_params *params) |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10817 | { |
| 10818 | struct bnx2x *bp = params->bp; |
| 10819 | u32 cfg_pin; |
| 10820 | u8 port; |
| 10821 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 10822 | /* In case of no EPIO routed to reset the GPHY, put it |
Yaniv Rosner | d2059a0 | 2011-08-02 23:00:00 +0000 | [diff] [blame] | 10823 | * in low power mode. |
| 10824 | */ |
| 10825 | bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 10826 | /* This works with E3 only, no need to check the chip |
Yaniv Rosner | d2059a0 | 2011-08-02 23:00:00 +0000 | [diff] [blame] | 10827 | * before determining the port. |
| 10828 | */ |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10829 | port = params->port; |
| 10830 | cfg_pin = (REG_RD(bp, params->shmem_base + |
| 10831 | offsetof(struct shmem_region, |
| 10832 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & |
| 10833 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> |
| 10834 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; |
| 10835 | |
| 10836 | /* Drive pin low to put GPHY in reset. */ |
| 10837 | bnx2x_set_cfg_pin(bp, cfg_pin, 0); |
| 10838 | } |
| 10839 | |
Yaniv Rosner | 52c4d6c | 2011-07-05 01:06:34 +0000 | [diff] [blame] | 10840 | static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy, |
| 10841 | struct link_params *params, |
| 10842 | struct link_vars *vars) |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10843 | { |
| 10844 | struct bnx2x *bp = params->bp; |
| 10845 | u16 val; |
| 10846 | u8 link_up = 0; |
| 10847 | u16 legacy_status, legacy_speed; |
| 10848 | |
| 10849 | /* Get speed operation status */ |
| 10850 | bnx2x_cl22_read(bp, phy, |
Yuval Mintz | a351d49 | 2012-06-20 19:05:21 +0000 | [diff] [blame] | 10851 | MDIO_REG_GPHY_AUX_STATUS, |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10852 | &legacy_status); |
Yaniv Rosner | 52c4d6c | 2011-07-05 01:06:34 +0000 | [diff] [blame] | 10853 | DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status); |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10854 | |
| 10855 | /* Read status to clear the PHY interrupt. */ |
| 10856 | bnx2x_cl22_read(bp, phy, |
| 10857 | MDIO_REG_INTR_STATUS, |
| 10858 | &val); |
| 10859 | |
| 10860 | link_up = ((legacy_status & (1<<2)) == (1<<2)); |
| 10861 | |
| 10862 | if (link_up) { |
| 10863 | legacy_speed = (legacy_status & (7<<8)); |
| 10864 | if (legacy_speed == (7<<8)) { |
| 10865 | vars->line_speed = SPEED_1000; |
| 10866 | vars->duplex = DUPLEX_FULL; |
| 10867 | } else if (legacy_speed == (6<<8)) { |
| 10868 | vars->line_speed = SPEED_1000; |
| 10869 | vars->duplex = DUPLEX_HALF; |
| 10870 | } else if (legacy_speed == (5<<8)) { |
| 10871 | vars->line_speed = SPEED_100; |
| 10872 | vars->duplex = DUPLEX_FULL; |
| 10873 | } |
| 10874 | /* Omitting 100Base-T4 for now */ |
| 10875 | else if (legacy_speed == (3<<8)) { |
| 10876 | vars->line_speed = SPEED_100; |
| 10877 | vars->duplex = DUPLEX_HALF; |
| 10878 | } else if (legacy_speed == (2<<8)) { |
| 10879 | vars->line_speed = SPEED_10; |
| 10880 | vars->duplex = DUPLEX_FULL; |
| 10881 | } else if (legacy_speed == (1<<8)) { |
| 10882 | vars->line_speed = SPEED_10; |
| 10883 | vars->duplex = DUPLEX_HALF; |
| 10884 | } else /* Should not happen */ |
| 10885 | vars->line_speed = 0; |
| 10886 | |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 10887 | DP(NETIF_MSG_LINK, |
| 10888 | "Link is up in %dMbps, is_duplex_full= %d\n", |
| 10889 | vars->line_speed, |
| 10890 | (vars->duplex == DUPLEX_FULL)); |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10891 | |
| 10892 | /* Check legacy speed AN resolution */ |
| 10893 | bnx2x_cl22_read(bp, phy, |
| 10894 | 0x01, |
| 10895 | &val); |
| 10896 | if (val & (1<<5)) |
| 10897 | vars->link_status |= |
| 10898 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; |
| 10899 | bnx2x_cl22_read(bp, phy, |
| 10900 | 0x06, |
| 10901 | &val); |
| 10902 | if ((val & (1<<0)) == 0) |
| 10903 | vars->link_status |= |
| 10904 | LINK_STATUS_PARALLEL_DETECTION_USED; |
| 10905 | |
Yaniv Rosner | 52c4d6c | 2011-07-05 01:06:34 +0000 | [diff] [blame] | 10906 | DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n", |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10907 | vars->line_speed); |
Yaniv Rosner | 52c4d6c | 2011-07-05 01:06:34 +0000 | [diff] [blame] | 10908 | |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10909 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 10910 | |
| 10911 | if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 10912 | /* Report LP advertised speeds */ |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 10913 | bnx2x_cl22_read(bp, phy, 0x5, &val); |
| 10914 | |
| 10915 | if (val & (1<<5)) |
| 10916 | vars->link_status |= |
| 10917 | LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; |
| 10918 | if (val & (1<<6)) |
| 10919 | vars->link_status |= |
| 10920 | LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; |
| 10921 | if (val & (1<<7)) |
| 10922 | vars->link_status |= |
| 10923 | LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; |
| 10924 | if (val & (1<<8)) |
| 10925 | vars->link_status |= |
| 10926 | LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; |
| 10927 | if (val & (1<<9)) |
| 10928 | vars->link_status |= |
| 10929 | LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; |
| 10930 | |
| 10931 | bnx2x_cl22_read(bp, phy, 0xa, &val); |
| 10932 | if (val & (1<<10)) |
| 10933 | vars->link_status |= |
| 10934 | LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; |
| 10935 | if (val & (1<<11)) |
| 10936 | vars->link_status |= |
| 10937 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; |
Yuval Mintz | 26964bb | 2012-09-10 05:51:08 +0000 | [diff] [blame] | 10938 | |
| 10939 | if ((phy->flags & FLAGS_EEE) && |
| 10940 | bnx2x_eee_has_cap(params)) |
| 10941 | bnx2x_eee_an_resolve(phy, params, vars); |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 10942 | } |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10943 | } |
| 10944 | return link_up; |
| 10945 | } |
| 10946 | |
Yaniv Rosner | 52c4d6c | 2011-07-05 01:06:34 +0000 | [diff] [blame] | 10947 | static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy, |
| 10948 | struct link_params *params) |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10949 | { |
| 10950 | struct bnx2x *bp = params->bp; |
| 10951 | u16 val; |
| 10952 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; |
| 10953 | |
Yaniv Rosner | 52c4d6c | 2011-07-05 01:06:34 +0000 | [diff] [blame] | 10954 | DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n"); |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10955 | |
| 10956 | /* Enable master/slave manual mmode and set to master */ |
| 10957 | /* mii write 9 [bits set 11 12] */ |
| 10958 | bnx2x_cl22_write(bp, phy, 0x09, 3<<11); |
| 10959 | |
| 10960 | /* forced 1G and disable autoneg */ |
| 10961 | /* set val [mii read 0] */ |
| 10962 | /* set val [expr $val & [bits clear 6 12 13]] */ |
| 10963 | /* set val [expr $val | [bits set 6 8]] */ |
| 10964 | /* mii write 0 $val */ |
| 10965 | bnx2x_cl22_read(bp, phy, 0x00, &val); |
| 10966 | val &= ~((1<<6) | (1<<12) | (1<<13)); |
| 10967 | val |= (1<<6) | (1<<8); |
| 10968 | bnx2x_cl22_write(bp, phy, 0x00, val); |
| 10969 | |
| 10970 | /* Set external loopback and Tx using 6dB coding */ |
| 10971 | /* mii write 0x18 7 */ |
| 10972 | /* set val [mii read 0x18] */ |
| 10973 | /* mii write 0x18 [expr $val | [bits set 10 15]] */ |
| 10974 | bnx2x_cl22_write(bp, phy, 0x18, 7); |
| 10975 | bnx2x_cl22_read(bp, phy, 0x18, &val); |
| 10976 | bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); |
| 10977 | |
| 10978 | /* This register opens the gate for the UMAC despite its name */ |
| 10979 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); |
| 10980 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 10981 | /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 10982 | * length used by the MAC receive logic to check frames. |
| 10983 | */ |
| 10984 | REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); |
| 10985 | } |
| 10986 | |
| 10987 | /******************************************************************/ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 10988 | /* SFX7101 PHY SECTION */ |
| 10989 | /******************************************************************/ |
| 10990 | static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, |
| 10991 | struct link_params *params) |
| 10992 | { |
| 10993 | struct bnx2x *bp = params->bp; |
| 10994 | /* SFX7101_XGXS_TEST1 */ |
| 10995 | bnx2x_cl45_write(bp, phy, |
| 10996 | MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); |
| 10997 | } |
| 10998 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 10999 | static int bnx2x_7101_config_init(struct bnx2x_phy *phy, |
| 11000 | struct link_params *params, |
| 11001 | struct link_vars *vars) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 11002 | { |
| 11003 | u16 fw_ver1, fw_ver2, val; |
| 11004 | struct bnx2x *bp = params->bp; |
| 11005 | DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n"); |
| 11006 | |
| 11007 | /* Restore normal power mode*/ |
| 11008 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11009 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 11010 | /* HW reset */ |
| 11011 | bnx2x_ext_phy_hw_reset(bp, params->port); |
Yaniv Rosner | 6d870c3 | 2011-01-31 04:22:20 +0000 | [diff] [blame] | 11012 | bnx2x_wait_reset_complete(bp, phy, params); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 11013 | |
| 11014 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 11015 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 11016 | DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n"); |
| 11017 | bnx2x_cl45_write(bp, phy, |
| 11018 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); |
| 11019 | |
| 11020 | bnx2x_ext_phy_set_pause(params, phy, vars); |
| 11021 | /* Restart autoneg */ |
| 11022 | bnx2x_cl45_read(bp, phy, |
| 11023 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); |
| 11024 | val |= 0x200; |
| 11025 | bnx2x_cl45_write(bp, phy, |
| 11026 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); |
| 11027 | |
| 11028 | /* Save spirom version */ |
| 11029 | bnx2x_cl45_read(bp, phy, |
| 11030 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); |
| 11031 | |
| 11032 | bnx2x_cl45_read(bp, phy, |
| 11033 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); |
| 11034 | bnx2x_save_spirom_version(bp, params->port, |
| 11035 | (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); |
| 11036 | return 0; |
| 11037 | } |
| 11038 | |
| 11039 | static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, |
| 11040 | struct link_params *params, |
| 11041 | struct link_vars *vars) |
| 11042 | { |
| 11043 | struct bnx2x *bp = params->bp; |
| 11044 | u8 link_up; |
| 11045 | u16 val1, val2; |
| 11046 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 11047 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 11048 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | 60d2fe0 | 2011-06-14 01:34:38 +0000 | [diff] [blame] | 11049 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 11050 | DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", |
| 11051 | val2, val1); |
| 11052 | bnx2x_cl45_read(bp, phy, |
| 11053 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); |
| 11054 | bnx2x_cl45_read(bp, phy, |
| 11055 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); |
| 11056 | DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", |
| 11057 | val2, val1); |
| 11058 | link_up = ((val1 & 4) == 4); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 11059 | /* If link is up print the AN outcome of the SFX7101 PHY */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 11060 | if (link_up) { |
| 11061 | bnx2x_cl45_read(bp, phy, |
| 11062 | MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, |
| 11063 | &val2); |
| 11064 | vars->line_speed = SPEED_10000; |
Yaniv Rosner | 791f18c | 2011-01-18 04:33:42 +0000 | [diff] [blame] | 11065 | vars->duplex = DUPLEX_FULL; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 11066 | DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", |
| 11067 | val2, (val2 & (1<<14))); |
| 11068 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); |
| 11069 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 11070 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 11071 | /* Read LP advertised speeds */ |
Mintz Yuval | 9e7e839 | 2012-02-15 02:10:24 +0000 | [diff] [blame] | 11072 | if (val2 & (1<<11)) |
| 11073 | vars->link_status |= |
| 11074 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 11075 | } |
| 11076 | return link_up; |
| 11077 | } |
| 11078 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 11079 | static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 11080 | { |
| 11081 | if (*len < 5) |
| 11082 | return -EINVAL; |
| 11083 | str[0] = (spirom_ver & 0xFF); |
| 11084 | str[1] = (spirom_ver & 0xFF00) >> 8; |
| 11085 | str[2] = (spirom_ver & 0xFF0000) >> 16; |
| 11086 | str[3] = (spirom_ver & 0xFF000000) >> 24; |
| 11087 | str[4] = '\0'; |
| 11088 | *len -= 5; |
| 11089 | return 0; |
| 11090 | } |
| 11091 | |
| 11092 | void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) |
| 11093 | { |
| 11094 | u16 val, cnt; |
| 11095 | |
| 11096 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11097 | MDIO_PMA_DEVAD, |
| 11098 | MDIO_PMA_REG_7101_RESET, &val); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 11099 | |
| 11100 | for (cnt = 0; cnt < 10; cnt++) { |
| 11101 | msleep(50); |
| 11102 | /* Writes a self-clearing reset */ |
| 11103 | bnx2x_cl45_write(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11104 | MDIO_PMA_DEVAD, |
| 11105 | MDIO_PMA_REG_7101_RESET, |
| 11106 | (val | (1<<15))); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 11107 | /* Wait for clear */ |
| 11108 | bnx2x_cl45_read(bp, phy, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11109 | MDIO_PMA_DEVAD, |
| 11110 | MDIO_PMA_REG_7101_RESET, &val); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 11111 | |
| 11112 | if ((val & (1<<15)) == 0) |
| 11113 | break; |
| 11114 | } |
| 11115 | } |
| 11116 | |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11117 | static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, |
| 11118 | struct link_params *params) { |
| 11119 | /* Low power mode is controlled by GPIO 2 */ |
| 11120 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11121 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11122 | /* The PHY reset is controlled by GPIO 1 */ |
| 11123 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11124 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11125 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 11126 | |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 11127 | static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, |
| 11128 | struct link_params *params, u8 mode) |
| 11129 | { |
| 11130 | u16 val = 0; |
| 11131 | struct bnx2x *bp = params->bp; |
| 11132 | switch (mode) { |
| 11133 | case LED_MODE_FRONT_PANEL_OFF: |
| 11134 | case LED_MODE_OFF: |
| 11135 | val = 2; |
| 11136 | break; |
| 11137 | case LED_MODE_ON: |
| 11138 | val = 1; |
| 11139 | break; |
| 11140 | case LED_MODE_OPER: |
| 11141 | val = 0; |
| 11142 | break; |
| 11143 | } |
| 11144 | bnx2x_cl45_write(bp, phy, |
| 11145 | MDIO_PMA_DEVAD, |
| 11146 | MDIO_PMA_REG_7107_LINK_LED_CNTL, |
| 11147 | val); |
| 11148 | } |
| 11149 | |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11150 | /******************************************************************/ |
| 11151 | /* STATIC PHY DECLARATION */ |
| 11152 | /******************************************************************/ |
| 11153 | |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 11154 | static const struct bnx2x_phy phy_null = { |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11155 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, |
| 11156 | .addr = 0, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11157 | .def_md_devad = 0, |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 11158 | .flags = FLAGS_INIT_XGXS_FIRST, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11159 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11160 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11161 | .mdio_ctrl = 0, |
| 11162 | .supported = 0, |
| 11163 | .media_type = ETH_PHY_NOT_PRESENT, |
| 11164 | .ver_addr = 0, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11165 | .req_flow_ctrl = 0, |
| 11166 | .req_line_speed = 0, |
| 11167 | .speed_cap_mask = 0, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11168 | .req_duplex = 0, |
| 11169 | .rsrv = 0, |
| 11170 | .config_init = (config_init_t)NULL, |
| 11171 | .read_status = (read_status_t)NULL, |
| 11172 | .link_reset = (link_reset_t)NULL, |
| 11173 | .config_loopback = (config_loopback_t)NULL, |
| 11174 | .format_fw_ver = (format_fw_ver_t)NULL, |
| 11175 | .hw_reset = (hw_reset_t)NULL, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11176 | .set_link_led = (set_link_led_t)NULL, |
| 11177 | .phy_specific_func = (phy_specific_func_t)NULL |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11178 | }; |
| 11179 | |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 11180 | static const struct bnx2x_phy phy_serdes = { |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11181 | .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, |
| 11182 | .addr = 0xff, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11183 | .def_md_devad = 0, |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 11184 | .flags = 0, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11185 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11186 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11187 | .mdio_ctrl = 0, |
| 11188 | .supported = (SUPPORTED_10baseT_Half | |
| 11189 | SUPPORTED_10baseT_Full | |
| 11190 | SUPPORTED_100baseT_Half | |
| 11191 | SUPPORTED_100baseT_Full | |
| 11192 | SUPPORTED_1000baseT_Full | |
| 11193 | SUPPORTED_2500baseX_Full | |
| 11194 | SUPPORTED_TP | |
| 11195 | SUPPORTED_Autoneg | |
| 11196 | SUPPORTED_Pause | |
| 11197 | SUPPORTED_Asym_Pause), |
Yaniv Rosner | 1ac9e42 | 2011-05-31 21:26:11 +0000 | [diff] [blame] | 11198 | .media_type = ETH_PHY_BASE_T, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11199 | .ver_addr = 0, |
| 11200 | .req_flow_ctrl = 0, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11201 | .req_line_speed = 0, |
| 11202 | .speed_cap_mask = 0, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11203 | .req_duplex = 0, |
| 11204 | .rsrv = 0, |
Yaniv Rosner | ec146a6 | 2011-05-31 21:29:27 +0000 | [diff] [blame] | 11205 | .config_init = (config_init_t)bnx2x_xgxs_config_init, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11206 | .read_status = (read_status_t)bnx2x_link_settings_status, |
| 11207 | .link_reset = (link_reset_t)bnx2x_int_link_reset, |
| 11208 | .config_loopback = (config_loopback_t)NULL, |
| 11209 | .format_fw_ver = (format_fw_ver_t)NULL, |
| 11210 | .hw_reset = (hw_reset_t)NULL, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11211 | .set_link_led = (set_link_led_t)NULL, |
| 11212 | .phy_specific_func = (phy_specific_func_t)NULL |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11213 | }; |
| 11214 | |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 11215 | static const struct bnx2x_phy phy_xgxs = { |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11216 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, |
| 11217 | .addr = 0xff, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11218 | .def_md_devad = 0, |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 11219 | .flags = 0, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11220 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11221 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11222 | .mdio_ctrl = 0, |
| 11223 | .supported = (SUPPORTED_10baseT_Half | |
| 11224 | SUPPORTED_10baseT_Full | |
| 11225 | SUPPORTED_100baseT_Half | |
| 11226 | SUPPORTED_100baseT_Full | |
| 11227 | SUPPORTED_1000baseT_Full | |
| 11228 | SUPPORTED_2500baseX_Full | |
| 11229 | SUPPORTED_10000baseT_Full | |
| 11230 | SUPPORTED_FIBRE | |
| 11231 | SUPPORTED_Autoneg | |
| 11232 | SUPPORTED_Pause | |
| 11233 | SUPPORTED_Asym_Pause), |
Yaniv Rosner | 1ac9e42 | 2011-05-31 21:26:11 +0000 | [diff] [blame] | 11234 | .media_type = ETH_PHY_CX4, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11235 | .ver_addr = 0, |
| 11236 | .req_flow_ctrl = 0, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11237 | .req_line_speed = 0, |
| 11238 | .speed_cap_mask = 0, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11239 | .req_duplex = 0, |
| 11240 | .rsrv = 0, |
Yaniv Rosner | ec146a6 | 2011-05-31 21:29:27 +0000 | [diff] [blame] | 11241 | .config_init = (config_init_t)bnx2x_xgxs_config_init, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11242 | .read_status = (read_status_t)bnx2x_link_settings_status, |
| 11243 | .link_reset = (link_reset_t)bnx2x_int_link_reset, |
| 11244 | .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback, |
| 11245 | .format_fw_ver = (format_fw_ver_t)NULL, |
| 11246 | .hw_reset = (hw_reset_t)NULL, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11247 | .set_link_led = (set_link_led_t)NULL, |
Yaniv Rosner | a75bb00 | 2012-10-31 05:46:53 +0000 | [diff] [blame] | 11248 | .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11249 | }; |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 11250 | static const struct bnx2x_phy phy_warpcore = { |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 11251 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, |
| 11252 | .addr = 0xff, |
| 11253 | .def_md_devad = 0, |
Yaniv Rosner | 8203c4b | 2012-11-27 03:46:33 +0000 | [diff] [blame] | 11254 | .flags = FLAGS_TX_ERROR_CHECK, |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 11255 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11256 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11257 | .mdio_ctrl = 0, |
| 11258 | .supported = (SUPPORTED_10baseT_Half | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 11259 | SUPPORTED_10baseT_Full | |
| 11260 | SUPPORTED_100baseT_Half | |
| 11261 | SUPPORTED_100baseT_Full | |
| 11262 | SUPPORTED_1000baseT_Full | |
| 11263 | SUPPORTED_10000baseT_Full | |
| 11264 | SUPPORTED_20000baseKR2_Full | |
| 11265 | SUPPORTED_20000baseMLD2_Full | |
| 11266 | SUPPORTED_FIBRE | |
| 11267 | SUPPORTED_Autoneg | |
| 11268 | SUPPORTED_Pause | |
| 11269 | SUPPORTED_Asym_Pause), |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 11270 | .media_type = ETH_PHY_UNSPECIFIED, |
| 11271 | .ver_addr = 0, |
| 11272 | .req_flow_ctrl = 0, |
| 11273 | .req_line_speed = 0, |
| 11274 | .speed_cap_mask = 0, |
| 11275 | /* req_duplex = */0, |
| 11276 | /* rsrv = */0, |
| 11277 | .config_init = (config_init_t)bnx2x_warpcore_config_init, |
| 11278 | .read_status = (read_status_t)bnx2x_warpcore_read_status, |
| 11279 | .link_reset = (link_reset_t)bnx2x_warpcore_link_reset, |
| 11280 | .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback, |
| 11281 | .format_fw_ver = (format_fw_ver_t)NULL, |
Yaniv Rosner | 985848f | 2011-07-05 01:06:48 +0000 | [diff] [blame] | 11282 | .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset, |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 11283 | .set_link_led = (set_link_led_t)NULL, |
| 11284 | .phy_specific_func = (phy_specific_func_t)NULL |
| 11285 | }; |
| 11286 | |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11287 | |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 11288 | static const struct bnx2x_phy phy_7101 = { |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11289 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, |
| 11290 | .addr = 0xff, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11291 | .def_md_devad = 0, |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 11292 | .flags = FLAGS_FAN_FAILURE_DET_REQ, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11293 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11294 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11295 | .mdio_ctrl = 0, |
| 11296 | .supported = (SUPPORTED_10000baseT_Full | |
| 11297 | SUPPORTED_TP | |
| 11298 | SUPPORTED_Autoneg | |
| 11299 | SUPPORTED_Pause | |
| 11300 | SUPPORTED_Asym_Pause), |
| 11301 | .media_type = ETH_PHY_BASE_T, |
| 11302 | .ver_addr = 0, |
| 11303 | .req_flow_ctrl = 0, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11304 | .req_line_speed = 0, |
| 11305 | .speed_cap_mask = 0, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11306 | .req_duplex = 0, |
| 11307 | .rsrv = 0, |
| 11308 | .config_init = (config_init_t)bnx2x_7101_config_init, |
| 11309 | .read_status = (read_status_t)bnx2x_7101_read_status, |
| 11310 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, |
| 11311 | .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback, |
| 11312 | .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver, |
| 11313 | .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset, |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 11314 | .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11315 | .phy_specific_func = (phy_specific_func_t)NULL |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11316 | }; |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 11317 | static const struct bnx2x_phy phy_8073 = { |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11318 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, |
| 11319 | .addr = 0xff, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11320 | .def_md_devad = 0, |
Yaniv Rosner | 8203c4b | 2012-11-27 03:46:33 +0000 | [diff] [blame] | 11321 | .flags = 0, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11322 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11323 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11324 | .mdio_ctrl = 0, |
| 11325 | .supported = (SUPPORTED_10000baseT_Full | |
| 11326 | SUPPORTED_2500baseX_Full | |
| 11327 | SUPPORTED_1000baseT_Full | |
| 11328 | SUPPORTED_FIBRE | |
| 11329 | SUPPORTED_Autoneg | |
| 11330 | SUPPORTED_Pause | |
| 11331 | SUPPORTED_Asym_Pause), |
Yaniv Rosner | 1ac9e42 | 2011-05-31 21:26:11 +0000 | [diff] [blame] | 11332 | .media_type = ETH_PHY_KR, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11333 | .ver_addr = 0, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11334 | .req_flow_ctrl = 0, |
| 11335 | .req_line_speed = 0, |
| 11336 | .speed_cap_mask = 0, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11337 | .req_duplex = 0, |
| 11338 | .rsrv = 0, |
Yaniv Rosner | 62b29a5 | 2010-09-07 11:40:58 +0000 | [diff] [blame] | 11339 | .config_init = (config_init_t)bnx2x_8073_config_init, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11340 | .read_status = (read_status_t)bnx2x_8073_read_status, |
| 11341 | .link_reset = (link_reset_t)bnx2x_8073_link_reset, |
| 11342 | .config_loopback = (config_loopback_t)NULL, |
| 11343 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, |
| 11344 | .hw_reset = (hw_reset_t)NULL, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11345 | .set_link_led = (set_link_led_t)NULL, |
Yaniv Rosner | 5c107fd | 2012-09-13 02:56:19 +0000 | [diff] [blame] | 11346 | .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11347 | }; |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 11348 | static const struct bnx2x_phy phy_8705 = { |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11349 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, |
| 11350 | .addr = 0xff, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11351 | .def_md_devad = 0, |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 11352 | .flags = FLAGS_INIT_XGXS_FIRST, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11353 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11354 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11355 | .mdio_ctrl = 0, |
| 11356 | .supported = (SUPPORTED_10000baseT_Full | |
| 11357 | SUPPORTED_FIBRE | |
| 11358 | SUPPORTED_Pause | |
| 11359 | SUPPORTED_Asym_Pause), |
| 11360 | .media_type = ETH_PHY_XFP_FIBER, |
| 11361 | .ver_addr = 0, |
| 11362 | .req_flow_ctrl = 0, |
| 11363 | .req_line_speed = 0, |
| 11364 | .speed_cap_mask = 0, |
| 11365 | .req_duplex = 0, |
| 11366 | .rsrv = 0, |
| 11367 | .config_init = (config_init_t)bnx2x_8705_config_init, |
| 11368 | .read_status = (read_status_t)bnx2x_8705_read_status, |
| 11369 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, |
| 11370 | .config_loopback = (config_loopback_t)NULL, |
| 11371 | .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver, |
| 11372 | .hw_reset = (hw_reset_t)NULL, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11373 | .set_link_led = (set_link_led_t)NULL, |
| 11374 | .phy_specific_func = (phy_specific_func_t)NULL |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11375 | }; |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 11376 | static const struct bnx2x_phy phy_8706 = { |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11377 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, |
| 11378 | .addr = 0xff, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11379 | .def_md_devad = 0, |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 11380 | .flags = FLAGS_INIT_XGXS_FIRST, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11381 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11382 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11383 | .mdio_ctrl = 0, |
| 11384 | .supported = (SUPPORTED_10000baseT_Full | |
| 11385 | SUPPORTED_1000baseT_Full | |
| 11386 | SUPPORTED_FIBRE | |
| 11387 | SUPPORTED_Pause | |
| 11388 | SUPPORTED_Asym_Pause), |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 11389 | .media_type = ETH_PHY_SFPP_10G_FIBER, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11390 | .ver_addr = 0, |
| 11391 | .req_flow_ctrl = 0, |
| 11392 | .req_line_speed = 0, |
| 11393 | .speed_cap_mask = 0, |
| 11394 | .req_duplex = 0, |
| 11395 | .rsrv = 0, |
| 11396 | .config_init = (config_init_t)bnx2x_8706_config_init, |
| 11397 | .read_status = (read_status_t)bnx2x_8706_read_status, |
| 11398 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, |
| 11399 | .config_loopback = (config_loopback_t)NULL, |
| 11400 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, |
| 11401 | .hw_reset = (hw_reset_t)NULL, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11402 | .set_link_led = (set_link_led_t)NULL, |
| 11403 | .phy_specific_func = (phy_specific_func_t)NULL |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11404 | }; |
| 11405 | |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 11406 | static const struct bnx2x_phy phy_8726 = { |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11407 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, |
| 11408 | .addr = 0xff, |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 11409 | .def_md_devad = 0, |
Yaniv Rosner | 8203c4b | 2012-11-27 03:46:33 +0000 | [diff] [blame] | 11410 | .flags = (FLAGS_INIT_XGXS_FIRST | |
Yaniv Rosner | 55098c5 | 2012-04-03 18:41:27 +0000 | [diff] [blame] | 11411 | FLAGS_TX_ERROR_CHECK), |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11412 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11413 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11414 | .mdio_ctrl = 0, |
| 11415 | .supported = (SUPPORTED_10000baseT_Full | |
| 11416 | SUPPORTED_1000baseT_Full | |
| 11417 | SUPPORTED_Autoneg | |
| 11418 | SUPPORTED_FIBRE | |
| 11419 | SUPPORTED_Pause | |
| 11420 | SUPPORTED_Asym_Pause), |
Yaniv Rosner | 1ac9e42 | 2011-05-31 21:26:11 +0000 | [diff] [blame] | 11421 | .media_type = ETH_PHY_NOT_PRESENT, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11422 | .ver_addr = 0, |
| 11423 | .req_flow_ctrl = 0, |
| 11424 | .req_line_speed = 0, |
| 11425 | .speed_cap_mask = 0, |
| 11426 | .req_duplex = 0, |
| 11427 | .rsrv = 0, |
| 11428 | .config_init = (config_init_t)bnx2x_8726_config_init, |
| 11429 | .read_status = (read_status_t)bnx2x_8726_read_status, |
| 11430 | .link_reset = (link_reset_t)bnx2x_8726_link_reset, |
| 11431 | .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback, |
| 11432 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, |
| 11433 | .hw_reset = (hw_reset_t)NULL, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11434 | .set_link_led = (set_link_led_t)NULL, |
| 11435 | .phy_specific_func = (phy_specific_func_t)NULL |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11436 | }; |
| 11437 | |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 11438 | static const struct bnx2x_phy phy_8727 = { |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11439 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, |
| 11440 | .addr = 0xff, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11441 | .def_md_devad = 0, |
Yaniv Rosner | 55098c5 | 2012-04-03 18:41:27 +0000 | [diff] [blame] | 11442 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
| 11443 | FLAGS_TX_ERROR_CHECK), |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11444 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11445 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11446 | .mdio_ctrl = 0, |
| 11447 | .supported = (SUPPORTED_10000baseT_Full | |
| 11448 | SUPPORTED_1000baseT_Full | |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11449 | SUPPORTED_FIBRE | |
| 11450 | SUPPORTED_Pause | |
| 11451 | SUPPORTED_Asym_Pause), |
Yaniv Rosner | 1ac9e42 | 2011-05-31 21:26:11 +0000 | [diff] [blame] | 11452 | .media_type = ETH_PHY_NOT_PRESENT, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11453 | .ver_addr = 0, |
| 11454 | .req_flow_ctrl = 0, |
| 11455 | .req_line_speed = 0, |
| 11456 | .speed_cap_mask = 0, |
| 11457 | .req_duplex = 0, |
| 11458 | .rsrv = 0, |
| 11459 | .config_init = (config_init_t)bnx2x_8727_config_init, |
| 11460 | .read_status = (read_status_t)bnx2x_8727_read_status, |
| 11461 | .link_reset = (link_reset_t)bnx2x_8727_link_reset, |
| 11462 | .config_loopback = (config_loopback_t)NULL, |
| 11463 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, |
| 11464 | .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset, |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 11465 | .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11466 | .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11467 | }; |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 11468 | static const struct bnx2x_phy phy_8481 = { |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11469 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, |
| 11470 | .addr = 0xff, |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 11471 | .def_md_devad = 0, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11472 | .flags = FLAGS_FAN_FAILURE_DET_REQ | |
| 11473 | FLAGS_REARM_LATCH_SIGNAL, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11474 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11475 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11476 | .mdio_ctrl = 0, |
| 11477 | .supported = (SUPPORTED_10baseT_Half | |
| 11478 | SUPPORTED_10baseT_Full | |
| 11479 | SUPPORTED_100baseT_Half | |
| 11480 | SUPPORTED_100baseT_Full | |
| 11481 | SUPPORTED_1000baseT_Full | |
| 11482 | SUPPORTED_10000baseT_Full | |
| 11483 | SUPPORTED_TP | |
| 11484 | SUPPORTED_Autoneg | |
| 11485 | SUPPORTED_Pause | |
| 11486 | SUPPORTED_Asym_Pause), |
| 11487 | .media_type = ETH_PHY_BASE_T, |
| 11488 | .ver_addr = 0, |
| 11489 | .req_flow_ctrl = 0, |
| 11490 | .req_line_speed = 0, |
| 11491 | .speed_cap_mask = 0, |
| 11492 | .req_duplex = 0, |
| 11493 | .rsrv = 0, |
| 11494 | .config_init = (config_init_t)bnx2x_8481_config_init, |
| 11495 | .read_status = (read_status_t)bnx2x_848xx_read_status, |
| 11496 | .link_reset = (link_reset_t)bnx2x_8481_link_reset, |
| 11497 | .config_loopback = (config_loopback_t)NULL, |
| 11498 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, |
| 11499 | .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset, |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 11500 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11501 | .phy_specific_func = (phy_specific_func_t)NULL |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11502 | }; |
| 11503 | |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 11504 | static const struct bnx2x_phy phy_84823 = { |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11505 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, |
| 11506 | .addr = 0xff, |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 11507 | .def_md_devad = 0, |
Yaniv Rosner | 55098c5 | 2012-04-03 18:41:27 +0000 | [diff] [blame] | 11508 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
| 11509 | FLAGS_REARM_LATCH_SIGNAL | |
| 11510 | FLAGS_TX_ERROR_CHECK), |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11511 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11512 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11513 | .mdio_ctrl = 0, |
| 11514 | .supported = (SUPPORTED_10baseT_Half | |
| 11515 | SUPPORTED_10baseT_Full | |
| 11516 | SUPPORTED_100baseT_Half | |
| 11517 | SUPPORTED_100baseT_Full | |
| 11518 | SUPPORTED_1000baseT_Full | |
| 11519 | SUPPORTED_10000baseT_Full | |
| 11520 | SUPPORTED_TP | |
| 11521 | SUPPORTED_Autoneg | |
| 11522 | SUPPORTED_Pause | |
| 11523 | SUPPORTED_Asym_Pause), |
| 11524 | .media_type = ETH_PHY_BASE_T, |
| 11525 | .ver_addr = 0, |
| 11526 | .req_flow_ctrl = 0, |
| 11527 | .req_line_speed = 0, |
| 11528 | .speed_cap_mask = 0, |
| 11529 | .req_duplex = 0, |
| 11530 | .rsrv = 0, |
| 11531 | .config_init = (config_init_t)bnx2x_848x3_config_init, |
| 11532 | .read_status = (read_status_t)bnx2x_848xx_read_status, |
| 11533 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, |
| 11534 | .config_loopback = (config_loopback_t)NULL, |
| 11535 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, |
| 11536 | .hw_reset = (hw_reset_t)NULL, |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 11537 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
Yaniv Rosner | 5c107fd | 2012-09-13 02:56:19 +0000 | [diff] [blame] | 11538 | .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11539 | }; |
| 11540 | |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 11541 | static const struct bnx2x_phy phy_84833 = { |
Yaniv Rosner | c87bca1 | 2011-01-31 04:22:41 +0000 | [diff] [blame] | 11542 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, |
| 11543 | .addr = 0xff, |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 11544 | .def_md_devad = 0, |
Yaniv Rosner | 55098c5 | 2012-04-03 18:41:27 +0000 | [diff] [blame] | 11545 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
| 11546 | FLAGS_REARM_LATCH_SIGNAL | |
Yuval Mintz | f6b6eb6 | 2012-09-10 05:51:07 +0000 | [diff] [blame] | 11547 | FLAGS_TX_ERROR_CHECK), |
Yaniv Rosner | c87bca1 | 2011-01-31 04:22:41 +0000 | [diff] [blame] | 11548 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11549 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11550 | .mdio_ctrl = 0, |
Yaniv Rosner | 0520e63 | 2011-07-05 01:06:59 +0000 | [diff] [blame] | 11551 | .supported = (SUPPORTED_100baseT_Half | |
Yaniv Rosner | c87bca1 | 2011-01-31 04:22:41 +0000 | [diff] [blame] | 11552 | SUPPORTED_100baseT_Full | |
| 11553 | SUPPORTED_1000baseT_Full | |
| 11554 | SUPPORTED_10000baseT_Full | |
| 11555 | SUPPORTED_TP | |
| 11556 | SUPPORTED_Autoneg | |
| 11557 | SUPPORTED_Pause | |
| 11558 | SUPPORTED_Asym_Pause), |
| 11559 | .media_type = ETH_PHY_BASE_T, |
| 11560 | .ver_addr = 0, |
| 11561 | .req_flow_ctrl = 0, |
| 11562 | .req_line_speed = 0, |
| 11563 | .speed_cap_mask = 0, |
| 11564 | .req_duplex = 0, |
| 11565 | .rsrv = 0, |
| 11566 | .config_init = (config_init_t)bnx2x_848x3_config_init, |
| 11567 | .read_status = (read_status_t)bnx2x_848xx_read_status, |
| 11568 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, |
| 11569 | .config_loopback = (config_loopback_t)NULL, |
| 11570 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, |
Yaniv Rosner | 985848f | 2011-07-05 01:06:48 +0000 | [diff] [blame] | 11571 | .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, |
Yaniv Rosner | c87bca1 | 2011-01-31 04:22:41 +0000 | [diff] [blame] | 11572 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
Yaniv Rosner | 5c107fd | 2012-09-13 02:56:19 +0000 | [diff] [blame] | 11573 | .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func |
Yaniv Rosner | c87bca1 | 2011-01-31 04:22:41 +0000 | [diff] [blame] | 11574 | }; |
| 11575 | |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 11576 | static const struct bnx2x_phy phy_84834 = { |
| 11577 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834, |
| 11578 | .addr = 0xff, |
| 11579 | .def_md_devad = 0, |
| 11580 | .flags = FLAGS_FAN_FAILURE_DET_REQ | |
| 11581 | FLAGS_REARM_LATCH_SIGNAL, |
| 11582 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11583 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11584 | .mdio_ctrl = 0, |
| 11585 | .supported = (SUPPORTED_100baseT_Half | |
| 11586 | SUPPORTED_100baseT_Full | |
| 11587 | SUPPORTED_1000baseT_Full | |
| 11588 | SUPPORTED_10000baseT_Full | |
| 11589 | SUPPORTED_TP | |
| 11590 | SUPPORTED_Autoneg | |
| 11591 | SUPPORTED_Pause | |
| 11592 | SUPPORTED_Asym_Pause), |
| 11593 | .media_type = ETH_PHY_BASE_T, |
| 11594 | .ver_addr = 0, |
| 11595 | .req_flow_ctrl = 0, |
| 11596 | .req_line_speed = 0, |
| 11597 | .speed_cap_mask = 0, |
| 11598 | .req_duplex = 0, |
| 11599 | .rsrv = 0, |
| 11600 | .config_init = (config_init_t)bnx2x_848x3_config_init, |
| 11601 | .read_status = (read_status_t)bnx2x_848xx_read_status, |
| 11602 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, |
| 11603 | .config_loopback = (config_loopback_t)NULL, |
| 11604 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, |
| 11605 | .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, |
| 11606 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
| 11607 | .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func |
| 11608 | }; |
| 11609 | |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 11610 | static const struct bnx2x_phy phy_54618se = { |
Yaniv Rosner | 52c4d6c | 2011-07-05 01:06:34 +0000 | [diff] [blame] | 11611 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 11612 | .addr = 0xff, |
| 11613 | .def_md_devad = 0, |
| 11614 | .flags = FLAGS_INIT_XGXS_FIRST, |
| 11615 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11616 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
| 11617 | .mdio_ctrl = 0, |
| 11618 | .supported = (SUPPORTED_10baseT_Half | |
| 11619 | SUPPORTED_10baseT_Full | |
| 11620 | SUPPORTED_100baseT_Half | |
| 11621 | SUPPORTED_100baseT_Full | |
| 11622 | SUPPORTED_1000baseT_Full | |
| 11623 | SUPPORTED_TP | |
| 11624 | SUPPORTED_Autoneg | |
| 11625 | SUPPORTED_Pause | |
| 11626 | SUPPORTED_Asym_Pause), |
| 11627 | .media_type = ETH_PHY_BASE_T, |
| 11628 | .ver_addr = 0, |
| 11629 | .req_flow_ctrl = 0, |
| 11630 | .req_line_speed = 0, |
| 11631 | .speed_cap_mask = 0, |
| 11632 | /* req_duplex = */0, |
| 11633 | /* rsrv = */0, |
Yaniv Rosner | 52c4d6c | 2011-07-05 01:06:34 +0000 | [diff] [blame] | 11634 | .config_init = (config_init_t)bnx2x_54618se_config_init, |
| 11635 | .read_status = (read_status_t)bnx2x_54618se_read_status, |
| 11636 | .link_reset = (link_reset_t)bnx2x_54618se_link_reset, |
| 11637 | .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback, |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 11638 | .format_fw_ver = (format_fw_ver_t)NULL, |
| 11639 | .hw_reset = (hw_reset_t)NULL, |
Yaniv Rosner | 1d125bd | 2011-11-23 03:54:08 +0000 | [diff] [blame] | 11640 | .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led, |
Yaniv Rosner | 5c107fd | 2012-09-13 02:56:19 +0000 | [diff] [blame] | 11641 | .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 11642 | }; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11643 | /*****************************************************************/ |
| 11644 | /* */ |
| 11645 | /* Populate the phy according. Main function: bnx2x_populate_phy */ |
| 11646 | /* */ |
| 11647 | /*****************************************************************/ |
| 11648 | |
| 11649 | static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, |
| 11650 | struct bnx2x_phy *phy, u8 port, |
| 11651 | u8 phy_index) |
| 11652 | { |
| 11653 | /* Get the 4 lanes xgxs config rx and tx */ |
| 11654 | u32 rx = 0, tx = 0, i; |
| 11655 | for (i = 0; i < 2; i++) { |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 11656 | /* INT_PHY and EXT_PHY1 share the same value location in |
| 11657 | * the shmem. When num_phys is greater than 1, than this value |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11658 | * applies only to EXT_PHY1 |
| 11659 | */ |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11660 | if (phy_index == INT_PHY || phy_index == EXT_PHY1) { |
| 11661 | rx = REG_RD(bp, shmem_base + |
| 11662 | offsetof(struct shmem_region, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11663 | dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11664 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11665 | tx = REG_RD(bp, shmem_base + |
| 11666 | offsetof(struct shmem_region, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11667 | dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11668 | } else { |
| 11669 | rx = REG_RD(bp, shmem_base + |
| 11670 | offsetof(struct shmem_region, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11671 | dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11672 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11673 | tx = REG_RD(bp, shmem_base + |
| 11674 | offsetof(struct shmem_region, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11675 | dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11676 | } |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11677 | |
| 11678 | phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); |
| 11679 | phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); |
| 11680 | |
| 11681 | phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); |
| 11682 | phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); |
| 11683 | } |
| 11684 | } |
| 11685 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 11686 | static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, |
| 11687 | u8 phy_index, u8 port) |
| 11688 | { |
| 11689 | u32 ext_phy_config = 0; |
| 11690 | switch (phy_index) { |
| 11691 | case EXT_PHY1: |
| 11692 | ext_phy_config = REG_RD(bp, shmem_base + |
| 11693 | offsetof(struct shmem_region, |
| 11694 | dev_info.port_hw_config[port].external_phy_config)); |
| 11695 | break; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11696 | case EXT_PHY2: |
| 11697 | ext_phy_config = REG_RD(bp, shmem_base + |
| 11698 | offsetof(struct shmem_region, |
| 11699 | dev_info.port_hw_config[port].external_phy_config2)); |
| 11700 | break; |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 11701 | default: |
| 11702 | DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index); |
| 11703 | return -EINVAL; |
| 11704 | } |
| 11705 | |
| 11706 | return ext_phy_config; |
| 11707 | } |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 11708 | static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, |
| 11709 | struct bnx2x_phy *phy) |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11710 | { |
| 11711 | u32 phy_addr; |
| 11712 | u32 chip_id; |
| 11713 | u32 switch_cfg = (REG_RD(bp, shmem_base + |
| 11714 | offsetof(struct shmem_region, |
| 11715 | dev_info.port_feature_config[port].link_config)) & |
| 11716 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
Yaniv Rosner | ec15b89 | 2011-11-28 00:49:49 +0000 | [diff] [blame] | 11717 | chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | |
| 11718 | ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); |
| 11719 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 11720 | DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id); |
| 11721 | if (USES_WARPCORE(bp)) { |
| 11722 | u32 serdes_net_if; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11723 | phy_addr = REG_RD(bp, |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 11724 | MISC_REG_WC0_CTRL_PHY_ADDR); |
| 11725 | *phy = phy_warpcore; |
| 11726 | if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) |
| 11727 | phy->flags |= FLAGS_4_PORT_MODE; |
| 11728 | else |
| 11729 | phy->flags &= ~FLAGS_4_PORT_MODE; |
| 11730 | /* Check Dual mode */ |
| 11731 | serdes_net_if = (REG_RD(bp, shmem_base + |
| 11732 | offsetof(struct shmem_region, dev_info. |
| 11733 | port_hw_config[port].default_cfg)) & |
| 11734 | PORT_HW_CFG_NET_SERDES_IF_MASK); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 11735 | /* Set the appropriate supported and flags indications per |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 11736 | * interface type of the chip |
| 11737 | */ |
| 11738 | switch (serdes_net_if) { |
| 11739 | case PORT_HW_CFG_NET_SERDES_IF_SGMII: |
| 11740 | phy->supported &= (SUPPORTED_10baseT_Half | |
| 11741 | SUPPORTED_10baseT_Full | |
| 11742 | SUPPORTED_100baseT_Half | |
| 11743 | SUPPORTED_100baseT_Full | |
| 11744 | SUPPORTED_1000baseT_Full | |
| 11745 | SUPPORTED_FIBRE | |
| 11746 | SUPPORTED_Autoneg | |
| 11747 | SUPPORTED_Pause | |
| 11748 | SUPPORTED_Asym_Pause); |
| 11749 | phy->media_type = ETH_PHY_BASE_T; |
| 11750 | break; |
| 11751 | case PORT_HW_CFG_NET_SERDES_IF_XFI: |
Yaniv Rosner | 03c3148 | 2012-10-31 05:46:57 +0000 | [diff] [blame] | 11752 | phy->supported &= (SUPPORTED_1000baseT_Full | |
| 11753 | SUPPORTED_10000baseT_Full | |
| 11754 | SUPPORTED_FIBRE | |
| 11755 | SUPPORTED_Pause | |
| 11756 | SUPPORTED_Asym_Pause); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 11757 | phy->media_type = ETH_PHY_XFP_FIBER; |
| 11758 | break; |
| 11759 | case PORT_HW_CFG_NET_SERDES_IF_SFI: |
| 11760 | phy->supported &= (SUPPORTED_1000baseT_Full | |
| 11761 | SUPPORTED_10000baseT_Full | |
| 11762 | SUPPORTED_FIBRE | |
| 11763 | SUPPORTED_Pause | |
| 11764 | SUPPORTED_Asym_Pause); |
Yuval Mintz | dbef807 | 2012-06-20 19:05:22 +0000 | [diff] [blame] | 11765 | phy->media_type = ETH_PHY_SFPP_10G_FIBER; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 11766 | break; |
| 11767 | case PORT_HW_CFG_NET_SERDES_IF_KR: |
| 11768 | phy->media_type = ETH_PHY_KR; |
| 11769 | phy->supported &= (SUPPORTED_1000baseT_Full | |
| 11770 | SUPPORTED_10000baseT_Full | |
| 11771 | SUPPORTED_FIBRE | |
| 11772 | SUPPORTED_Autoneg | |
| 11773 | SUPPORTED_Pause | |
| 11774 | SUPPORTED_Asym_Pause); |
| 11775 | break; |
| 11776 | case PORT_HW_CFG_NET_SERDES_IF_DXGXS: |
| 11777 | phy->media_type = ETH_PHY_KR; |
| 11778 | phy->flags |= FLAGS_WC_DUAL_MODE; |
| 11779 | phy->supported &= (SUPPORTED_20000baseMLD2_Full | |
| 11780 | SUPPORTED_FIBRE | |
| 11781 | SUPPORTED_Pause | |
| 11782 | SUPPORTED_Asym_Pause); |
| 11783 | break; |
| 11784 | case PORT_HW_CFG_NET_SERDES_IF_KR2: |
| 11785 | phy->media_type = ETH_PHY_KR; |
| 11786 | phy->flags |= FLAGS_WC_DUAL_MODE; |
| 11787 | phy->supported &= (SUPPORTED_20000baseKR2_Full | |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 11788 | SUPPORTED_Autoneg | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 11789 | SUPPORTED_FIBRE | |
| 11790 | SUPPORTED_Pause | |
| 11791 | SUPPORTED_Asym_Pause); |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 11792 | phy->flags &= ~FLAGS_TX_ERROR_CHECK; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 11793 | break; |
| 11794 | default: |
| 11795 | DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n", |
| 11796 | serdes_net_if); |
| 11797 | break; |
| 11798 | } |
| 11799 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 11800 | /* Enable MDC/MDIO work-around for E3 A0 since free running MDC |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 11801 | * was not set as expected. For B0, ECO will be enabled so there |
| 11802 | * won't be an issue there |
| 11803 | */ |
| 11804 | if (CHIP_REV(bp) == CHIP_REV_Ax) |
| 11805 | phy->flags |= FLAGS_MDC_MDIO_WA; |
Yaniv Rosner | 157fa28 | 2011-08-02 22:59:32 +0000 | [diff] [blame] | 11806 | else |
| 11807 | phy->flags |= FLAGS_MDC_MDIO_WA_B0; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 11808 | } else { |
| 11809 | switch (switch_cfg) { |
| 11810 | case SWITCH_CFG_1G: |
| 11811 | phy_addr = REG_RD(bp, |
| 11812 | NIG_REG_SERDES0_CTRL_PHY_ADDR + |
| 11813 | port * 0x10); |
| 11814 | *phy = phy_serdes; |
| 11815 | break; |
| 11816 | case SWITCH_CFG_10G: |
| 11817 | phy_addr = REG_RD(bp, |
| 11818 | NIG_REG_XGXS0_CTRL_PHY_ADDR + |
| 11819 | port * 0x18); |
| 11820 | *phy = phy_xgxs; |
| 11821 | break; |
| 11822 | default: |
| 11823 | DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); |
| 11824 | return -EINVAL; |
| 11825 | } |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11826 | } |
| 11827 | phy->addr = (u8)phy_addr; |
| 11828 | phy->mdio_ctrl = bnx2x_get_emac_base(bp, |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 11829 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11830 | port); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 11831 | if (CHIP_IS_E2(bp)) |
| 11832 | phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; |
| 11833 | else |
| 11834 | phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11835 | |
| 11836 | DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", |
| 11837 | port, phy->addr, phy->mdio_ctrl); |
| 11838 | |
| 11839 | bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); |
| 11840 | return 0; |
| 11841 | } |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 11842 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 11843 | static int bnx2x_populate_ext_phy(struct bnx2x *bp, |
| 11844 | u8 phy_index, |
| 11845 | u32 shmem_base, |
| 11846 | u32 shmem2_base, |
| 11847 | u8 port, |
| 11848 | struct bnx2x_phy *phy) |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 11849 | { |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 11850 | u32 ext_phy_config, phy_type, config2; |
| 11851 | u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 11852 | ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, |
| 11853 | phy_index, port); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11854 | phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); |
| 11855 | /* Select the phy type */ |
| 11856 | switch (phy_type) { |
| 11857 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 11858 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11859 | *phy = phy_8073; |
| 11860 | break; |
| 11861 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: |
| 11862 | *phy = phy_8705; |
| 11863 | break; |
| 11864 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: |
| 11865 | *phy = phy_8706; |
| 11866 | break; |
| 11867 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 11868 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11869 | *phy = phy_8726; |
| 11870 | break; |
| 11871 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: |
| 11872 | /* BCM8727_NOC => BCM8727 no over current */ |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 11873 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11874 | *phy = phy_8727; |
| 11875 | phy->flags |= FLAGS_NOC; |
| 11876 | break; |
Yaniv Rosner | e4d78f1 | 2011-05-31 21:25:55 +0000 | [diff] [blame] | 11877 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11878 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 11879 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11880 | *phy = phy_8727; |
| 11881 | break; |
| 11882 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: |
| 11883 | *phy = phy_8481; |
| 11884 | break; |
| 11885 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: |
| 11886 | *phy = phy_84823; |
| 11887 | break; |
Yaniv Rosner | c87bca1 | 2011-01-31 04:22:41 +0000 | [diff] [blame] | 11888 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: |
| 11889 | *phy = phy_84833; |
| 11890 | break; |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 11891 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: |
| 11892 | *phy = phy_84834; |
| 11893 | break; |
Yaniv Rosner | 3756a89 | 2011-08-23 06:33:24 +0000 | [diff] [blame] | 11894 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: |
Yaniv Rosner | 52c4d6c | 2011-07-05 01:06:34 +0000 | [diff] [blame] | 11895 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: |
| 11896 | *phy = phy_54618se; |
Yuval Mintz | 26964bb | 2012-09-10 05:51:08 +0000 | [diff] [blame] | 11897 | if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) |
| 11898 | phy->flags |= FLAGS_EEE; |
Yaniv Rosner | 6583e33 | 2011-06-14 01:34:17 +0000 | [diff] [blame] | 11899 | break; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11900 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: |
| 11901 | *phy = phy_7101; |
| 11902 | break; |
| 11903 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: |
| 11904 | *phy = phy_null; |
| 11905 | return -EINVAL; |
| 11906 | default: |
| 11907 | *phy = phy_null; |
Yaniv Rosner | 6db5193 | 2011-11-28 00:49:50 +0000 | [diff] [blame] | 11908 | /* In case external PHY wasn't found */ |
| 11909 | if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && |
| 11910 | (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) |
| 11911 | return -EINVAL; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11912 | return 0; |
| 11913 | } |
| 11914 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 11915 | phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11916 | bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); |
Yaniv Rosner | 62b29a5 | 2010-09-07 11:40:58 +0000 | [diff] [blame] | 11917 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 11918 | /* The shmem address of the phy version is located on different |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 11919 | * structures. In case this structure is too old, do not set |
| 11920 | * the address |
| 11921 | */ |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 11922 | config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, |
| 11923 | dev_info.shared_hw_config.config2)); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11924 | if (phy_index == EXT_PHY1) { |
| 11925 | phy->ver_addr = shmem_base + offsetof(struct shmem_region, |
| 11926 | port_mb[port].ext_phy_fw_version); |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 11927 | |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11928 | /* Check specific mdc mdio settings */ |
| 11929 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) |
| 11930 | mdc_mdio_access = config2 & |
| 11931 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11932 | } else { |
| 11933 | u32 size = REG_RD(bp, shmem2_base); |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 11934 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11935 | if (size > |
| 11936 | offsetof(struct shmem2_region, ext_phy_fw_version2)) { |
| 11937 | phy->ver_addr = shmem2_base + |
| 11938 | offsetof(struct shmem2_region, |
| 11939 | ext_phy_fw_version2[port]); |
| 11940 | } |
| 11941 | /* Check specific mdc mdio settings */ |
| 11942 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) |
| 11943 | mdc_mdio_access = (config2 & |
| 11944 | SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> |
| 11945 | (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - |
| 11946 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); |
| 11947 | } |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 11948 | phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); |
| 11949 | |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 11950 | if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
| 11951 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) && |
Yaniv Rosner | 7531832 | 2012-01-17 02:33:27 +0000 | [diff] [blame] | 11952 | (phy->ver_addr)) { |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 11953 | /* Remove 100Mb link supported for BCM84833/4 when phy fw |
Yaniv Rosner | 7531832 | 2012-01-17 02:33:27 +0000 | [diff] [blame] | 11954 | * version lower than or equal to 1.39 |
| 11955 | */ |
| 11956 | u32 raw_ver = REG_RD(bp, phy->ver_addr); |
| 11957 | if (((raw_ver & 0x7F) <= 39) && |
| 11958 | (((raw_ver & 0xF80) >> 7) <= 1)) |
| 11959 | phy->supported &= ~(SUPPORTED_100baseT_Half | |
| 11960 | SUPPORTED_100baseT_Full); |
| 11961 | } |
| 11962 | |
Yaniv Rosner | c18aa15 | 2010-09-07 11:41:07 +0000 | [diff] [blame] | 11963 | DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", |
| 11964 | phy_type, port, phy_index); |
| 11965 | DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", |
| 11966 | phy->addr, phy->mdio_ctrl); |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 11967 | return 0; |
| 11968 | } |
| 11969 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 11970 | static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, |
| 11971 | u32 shmem2_base, u8 port, struct bnx2x_phy *phy) |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 11972 | { |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 11973 | int status = 0; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11974 | phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; |
| 11975 | if (phy_index == INT_PHY) |
| 11976 | return bnx2x_populate_int_phy(bp, shmem_base, port, phy); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11977 | status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 11978 | port, phy); |
| 11979 | return status; |
| 11980 | } |
| 11981 | |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11982 | static void bnx2x_phy_def_cfg(struct link_params *params, |
| 11983 | struct bnx2x_phy *phy, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11984 | u8 phy_index) |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 11985 | { |
| 11986 | struct bnx2x *bp = params->bp; |
| 11987 | u32 link_config; |
| 11988 | /* Populate the default phy configuration for MF mode */ |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11989 | if (phy_index == EXT_PHY2) { |
| 11990 | link_config = REG_RD(bp, params->shmem_base + |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11991 | offsetof(struct shmem_region, dev_info. |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11992 | port_feature_config[params->port].link_config2)); |
| 11993 | phy->speed_cap_mask = REG_RD(bp, params->shmem_base + |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11994 | offsetof(struct shmem_region, |
| 11995 | dev_info. |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 11996 | port_hw_config[params->port].speed_capability_mask2)); |
| 11997 | } else { |
| 11998 | link_config = REG_RD(bp, params->shmem_base + |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 11999 | offsetof(struct shmem_region, dev_info. |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 12000 | port_feature_config[params->port].link_config)); |
| 12001 | phy->speed_cap_mask = REG_RD(bp, params->shmem_base + |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 12002 | offsetof(struct shmem_region, |
| 12003 | dev_info. |
| 12004 | port_hw_config[params->port].speed_capability_mask)); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 12005 | } |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 12006 | DP(NETIF_MSG_LINK, |
| 12007 | "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", |
| 12008 | phy_index, link_config, phy->speed_cap_mask); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 12009 | |
| 12010 | phy->req_duplex = DUPLEX_FULL; |
| 12011 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { |
| 12012 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
| 12013 | phy->req_duplex = DUPLEX_HALF; |
| 12014 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
| 12015 | phy->req_line_speed = SPEED_10; |
| 12016 | break; |
| 12017 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
| 12018 | phy->req_duplex = DUPLEX_HALF; |
| 12019 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
| 12020 | phy->req_line_speed = SPEED_100; |
| 12021 | break; |
| 12022 | case PORT_FEATURE_LINK_SPEED_1G: |
| 12023 | phy->req_line_speed = SPEED_1000; |
| 12024 | break; |
| 12025 | case PORT_FEATURE_LINK_SPEED_2_5G: |
| 12026 | phy->req_line_speed = SPEED_2500; |
| 12027 | break; |
| 12028 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
| 12029 | phy->req_line_speed = SPEED_10000; |
| 12030 | break; |
| 12031 | default: |
| 12032 | phy->req_line_speed = SPEED_AUTO_NEG; |
| 12033 | break; |
| 12034 | } |
| 12035 | |
| 12036 | switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { |
| 12037 | case PORT_FEATURE_FLOW_CONTROL_AUTO: |
| 12038 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; |
| 12039 | break; |
| 12040 | case PORT_FEATURE_FLOW_CONTROL_TX: |
| 12041 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; |
| 12042 | break; |
| 12043 | case PORT_FEATURE_FLOW_CONTROL_RX: |
| 12044 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; |
| 12045 | break; |
| 12046 | case PORT_FEATURE_FLOW_CONTROL_BOTH: |
| 12047 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; |
| 12048 | break; |
| 12049 | default: |
| 12050 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
| 12051 | break; |
| 12052 | } |
| 12053 | } |
| 12054 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 12055 | u32 bnx2x_phy_selection(struct link_params *params) |
| 12056 | { |
| 12057 | u32 phy_config_swapped, prio_cfg; |
| 12058 | u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; |
| 12059 | |
| 12060 | phy_config_swapped = params->multi_phy_config & |
| 12061 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; |
| 12062 | |
| 12063 | prio_cfg = params->multi_phy_config & |
| 12064 | PORT_HW_CFG_PHY_SELECTION_MASK; |
| 12065 | |
| 12066 | if (phy_config_swapped) { |
| 12067 | switch (prio_cfg) { |
| 12068 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: |
| 12069 | return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; |
| 12070 | break; |
| 12071 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: |
| 12072 | return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; |
| 12073 | break; |
| 12074 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: |
| 12075 | return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; |
| 12076 | break; |
| 12077 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: |
| 12078 | return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; |
| 12079 | break; |
| 12080 | } |
| 12081 | } else |
| 12082 | return_cfg = prio_cfg; |
| 12083 | |
| 12084 | return return_cfg; |
| 12085 | } |
| 12086 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 12087 | int bnx2x_phy_probe(struct link_params *params) |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 12088 | { |
Yaniv Rosner | 2f751a8 | 2011-11-28 00:49:52 +0000 | [diff] [blame] | 12089 | u8 phy_index, actual_phy_idx; |
Yaniv Rosner | 1ac9e42 | 2011-05-31 21:26:11 +0000 | [diff] [blame] | 12090 | u32 phy_config_swapped, sync_offset, media_types; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 12091 | struct bnx2x *bp = params->bp; |
| 12092 | struct bnx2x_phy *phy; |
| 12093 | params->num_phys = 0; |
| 12094 | DP(NETIF_MSG_LINK, "Begin phy probe\n"); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 12095 | phy_config_swapped = params->multi_phy_config & |
| 12096 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 12097 | |
| 12098 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; |
| 12099 | phy_index++) { |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 12100 | actual_phy_idx = phy_index; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 12101 | if (phy_config_swapped) { |
| 12102 | if (phy_index == EXT_PHY1) |
| 12103 | actual_phy_idx = EXT_PHY2; |
| 12104 | else if (phy_index == EXT_PHY2) |
| 12105 | actual_phy_idx = EXT_PHY1; |
| 12106 | } |
| 12107 | DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x," |
| 12108 | " actual_phy_idx %x\n", phy_config_swapped, |
| 12109 | phy_index, actual_phy_idx); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 12110 | phy = ¶ms->phy[actual_phy_idx]; |
| 12111 | if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 12112 | params->shmem2_base, params->port, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 12113 | phy) != 0) { |
| 12114 | params->num_phys = 0; |
| 12115 | DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n", |
| 12116 | phy_index); |
| 12117 | for (phy_index = INT_PHY; |
| 12118 | phy_index < MAX_PHYS; |
| 12119 | phy_index++) |
| 12120 | *phy = phy_null; |
| 12121 | return -EINVAL; |
| 12122 | } |
| 12123 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) |
| 12124 | break; |
| 12125 | |
Yaniv Rosner | 55098c5 | 2012-04-03 18:41:27 +0000 | [diff] [blame] | 12126 | if (params->feature_config_flags & |
| 12127 | FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) |
| 12128 | phy->flags &= ~FLAGS_TX_ERROR_CHECK; |
| 12129 | |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 12130 | if (!(params->feature_config_flags & |
| 12131 | FEATURE_CONFIG_MT_SUPPORT)) |
| 12132 | phy->flags |= FLAGS_MDC_MDIO_WA_G; |
| 12133 | |
Yaniv Rosner | 1ac9e42 | 2011-05-31 21:26:11 +0000 | [diff] [blame] | 12134 | sync_offset = params->shmem_base + |
| 12135 | offsetof(struct shmem_region, |
| 12136 | dev_info.port_hw_config[params->port].media_type); |
| 12137 | media_types = REG_RD(bp, sync_offset); |
| 12138 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 12139 | /* Update media type for non-PMF sync only for the first time |
Yaniv Rosner | 1ac9e42 | 2011-05-31 21:26:11 +0000 | [diff] [blame] | 12140 | * In case the media type changes afterwards, it will be updated |
| 12141 | * using the update_status function |
| 12142 | */ |
| 12143 | if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << |
| 12144 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * |
| 12145 | actual_phy_idx))) == 0) { |
| 12146 | media_types |= ((phy->media_type & |
| 12147 | PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << |
| 12148 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * |
| 12149 | actual_phy_idx)); |
| 12150 | } |
| 12151 | REG_WR(bp, sync_offset, media_types); |
| 12152 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 12153 | bnx2x_phy_def_cfg(params, phy, phy_index); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 12154 | params->num_phys++; |
| 12155 | } |
| 12156 | |
| 12157 | DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); |
| 12158 | return 0; |
| 12159 | } |
| 12160 | |
Merav Sicron | 910cc72 | 2012-11-11 03:56:08 +0000 | [diff] [blame] | 12161 | static void bnx2x_init_bmac_loopback(struct link_params *params, |
| 12162 | struct link_vars *vars) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12163 | { |
| 12164 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 12165 | vars->link_up = 1; |
| 12166 | vars->line_speed = SPEED_10000; |
| 12167 | vars->duplex = DUPLEX_FULL; |
| 12168 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
| 12169 | vars->mac_type = MAC_TYPE_BMAC; |
| 12170 | |
| 12171 | vars->phy_flags = PHY_XGXS_FLAG; |
| 12172 | |
| 12173 | bnx2x_xgxs_deassert(params); |
| 12174 | |
| 12175 | /* set bmac loopback */ |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 12176 | bnx2x_bmac_enable(params, vars, 1, 1); |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 12177 | |
| 12178 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
| 12179 | } |
| 12180 | |
Merav Sicron | 910cc72 | 2012-11-11 03:56:08 +0000 | [diff] [blame] | 12181 | static void bnx2x_init_emac_loopback(struct link_params *params, |
| 12182 | struct link_vars *vars) |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 12183 | { |
| 12184 | struct bnx2x *bp = params->bp; |
| 12185 | vars->link_up = 1; |
| 12186 | vars->line_speed = SPEED_1000; |
| 12187 | vars->duplex = DUPLEX_FULL; |
| 12188 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
| 12189 | vars->mac_type = MAC_TYPE_EMAC; |
| 12190 | |
| 12191 | vars->phy_flags = PHY_XGXS_FLAG; |
| 12192 | |
| 12193 | bnx2x_xgxs_deassert(params); |
| 12194 | /* set bmac loopback */ |
| 12195 | bnx2x_emac_enable(params, vars, 1); |
| 12196 | bnx2x_emac_program(params, vars); |
| 12197 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
| 12198 | } |
| 12199 | |
Merav Sicron | 910cc72 | 2012-11-11 03:56:08 +0000 | [diff] [blame] | 12200 | static void bnx2x_init_xmac_loopback(struct link_params *params, |
| 12201 | struct link_vars *vars) |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 12202 | { |
| 12203 | struct bnx2x *bp = params->bp; |
| 12204 | vars->link_up = 1; |
| 12205 | if (!params->req_line_speed[0]) |
| 12206 | vars->line_speed = SPEED_10000; |
| 12207 | else |
| 12208 | vars->line_speed = params->req_line_speed[0]; |
| 12209 | vars->duplex = DUPLEX_FULL; |
| 12210 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
| 12211 | vars->mac_type = MAC_TYPE_XMAC; |
| 12212 | vars->phy_flags = PHY_XGXS_FLAG; |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 12213 | /* Set WC to loopback mode since link is required to provide clock |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 12214 | * to the XMAC in 20G mode |
| 12215 | */ |
Yaniv Rosner | afad009 | 2011-08-02 23:00:06 +0000 | [diff] [blame] | 12216 | bnx2x_set_aer_mmd(params, ¶ms->phy[0]); |
| 12217 | bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); |
| 12218 | params->phy[INT_PHY].config_loopback( |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 12219 | ¶ms->phy[INT_PHY], |
| 12220 | params); |
Yaniv Rosner | afad009 | 2011-08-02 23:00:06 +0000 | [diff] [blame] | 12221 | |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 12222 | bnx2x_xmac_enable(params, vars, 1); |
| 12223 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
| 12224 | } |
| 12225 | |
Merav Sicron | 910cc72 | 2012-11-11 03:56:08 +0000 | [diff] [blame] | 12226 | static void bnx2x_init_umac_loopback(struct link_params *params, |
| 12227 | struct link_vars *vars) |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 12228 | { |
| 12229 | struct bnx2x *bp = params->bp; |
| 12230 | vars->link_up = 1; |
| 12231 | vars->line_speed = SPEED_1000; |
| 12232 | vars->duplex = DUPLEX_FULL; |
| 12233 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
| 12234 | vars->mac_type = MAC_TYPE_UMAC; |
| 12235 | vars->phy_flags = PHY_XGXS_FLAG; |
| 12236 | bnx2x_umac_enable(params, vars, 1); |
| 12237 | |
| 12238 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
| 12239 | } |
| 12240 | |
Merav Sicron | 910cc72 | 2012-11-11 03:56:08 +0000 | [diff] [blame] | 12241 | static void bnx2x_init_xgxs_loopback(struct link_params *params, |
| 12242 | struct link_vars *vars) |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 12243 | { |
| 12244 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 12245 | struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 12246 | vars->link_up = 1; |
| 12247 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
| 12248 | vars->duplex = DUPLEX_FULL; |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 12249 | if (params->req_line_speed[0] == SPEED_1000) |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 12250 | vars->line_speed = SPEED_1000; |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 12251 | else if ((params->req_line_speed[0] == SPEED_20000) || |
| 12252 | (int_phy->flags & FLAGS_WC_DUAL_MODE)) |
| 12253 | vars->line_speed = SPEED_20000; |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 12254 | else |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 12255 | vars->line_speed = SPEED_10000; |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 12256 | |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 12257 | if (!USES_WARPCORE(bp)) |
| 12258 | bnx2x_xgxs_deassert(params); |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 12259 | bnx2x_link_initialize(params, vars); |
| 12260 | |
| 12261 | if (params->req_line_speed[0] == SPEED_1000) { |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 12262 | if (USES_WARPCORE(bp)) |
| 12263 | bnx2x_umac_enable(params, vars, 0); |
| 12264 | else { |
| 12265 | bnx2x_emac_program(params, vars); |
| 12266 | bnx2x_emac_enable(params, vars, 0); |
| 12267 | } |
| 12268 | } else { |
| 12269 | if (USES_WARPCORE(bp)) |
| 12270 | bnx2x_xmac_enable(params, vars, 0); |
| 12271 | else |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 12272 | bnx2x_bmac_enable(params, vars, 0, 1); |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 12273 | } |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 12274 | |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 12275 | if (params->loopback_mode == LOOPBACK_XGXS) { |
| 12276 | /* Set 10G XGXS loopback */ |
| 12277 | int_phy->config_loopback(int_phy, params); |
| 12278 | } else { |
| 12279 | /* Set external phy loopback */ |
| 12280 | u8 phy_index; |
| 12281 | for (phy_index = EXT_PHY1; |
| 12282 | phy_index < params->num_phys; phy_index++) |
| 12283 | if (params->phy[phy_index].config_loopback) |
| 12284 | params->phy[phy_index].config_loopback( |
| 12285 | ¶ms->phy[phy_index], |
| 12286 | params); |
| 12287 | } |
| 12288 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12289 | |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 12290 | bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12291 | } |
| 12292 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 12293 | void bnx2x_set_rx_filter(struct link_params *params, u8 en) |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 12294 | { |
| 12295 | struct bnx2x *bp = params->bp; |
| 12296 | u8 val = en * 0x1F; |
| 12297 | |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 12298 | /* Open / close the gate between the NIG and the BRB */ |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 12299 | if (!CHIP_IS_E1x(bp)) |
| 12300 | val |= en * 0x20; |
| 12301 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); |
| 12302 | |
| 12303 | if (!CHIP_IS_E1(bp)) { |
| 12304 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, |
| 12305 | en*0x3); |
| 12306 | } |
| 12307 | |
| 12308 | REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : |
| 12309 | NIG_REG_LLH0_BRB1_NOT_MCP), en); |
| 12310 | } |
| 12311 | static int bnx2x_avoid_link_flap(struct link_params *params, |
| 12312 | struct link_vars *vars) |
| 12313 | { |
| 12314 | u32 phy_idx; |
| 12315 | u32 dont_clear_stat, lfa_sts; |
| 12316 | struct bnx2x *bp = params->bp; |
| 12317 | |
| 12318 | /* Sync the link parameters */ |
| 12319 | bnx2x_link_status_update(params, vars); |
| 12320 | |
| 12321 | /* |
| 12322 | * The module verification was already done by previous link owner, |
| 12323 | * so this call is meant only to get warning message |
| 12324 | */ |
| 12325 | |
| 12326 | for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) { |
| 12327 | struct bnx2x_phy *phy = ¶ms->phy[phy_idx]; |
| 12328 | if (phy->phy_specific_func) { |
| 12329 | DP(NETIF_MSG_LINK, "Calling PHY specific func\n"); |
| 12330 | phy->phy_specific_func(phy, params, PHY_INIT); |
| 12331 | } |
| 12332 | if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) || |
| 12333 | (phy->media_type == ETH_PHY_SFP_1G_FIBER) || |
| 12334 | (phy->media_type == ETH_PHY_DA_TWINAX)) |
| 12335 | bnx2x_verify_sfp_module(phy, params); |
| 12336 | } |
| 12337 | lfa_sts = REG_RD(bp, params->lfa_base + |
| 12338 | offsetof(struct shmem_lfa, |
| 12339 | lfa_sts)); |
| 12340 | |
| 12341 | dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; |
| 12342 | |
| 12343 | /* Re-enable the NIG/MAC */ |
| 12344 | if (CHIP_IS_E3(bp)) { |
| 12345 | if (!dont_clear_stat) { |
| 12346 | REG_WR(bp, GRCBASE_MISC + |
| 12347 | MISC_REGISTERS_RESET_REG_2_CLEAR, |
| 12348 | (MISC_REGISTERS_RESET_REG_2_MSTAT0 << |
| 12349 | params->port)); |
| 12350 | REG_WR(bp, GRCBASE_MISC + |
| 12351 | MISC_REGISTERS_RESET_REG_2_SET, |
| 12352 | (MISC_REGISTERS_RESET_REG_2_MSTAT0 << |
| 12353 | params->port)); |
| 12354 | } |
| 12355 | if (vars->line_speed < SPEED_10000) |
| 12356 | bnx2x_umac_enable(params, vars, 0); |
| 12357 | else |
| 12358 | bnx2x_xmac_enable(params, vars, 0); |
| 12359 | } else { |
| 12360 | if (vars->line_speed < SPEED_10000) |
| 12361 | bnx2x_emac_enable(params, vars, 0); |
| 12362 | else |
| 12363 | bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat); |
| 12364 | } |
| 12365 | |
| 12366 | /* Increment LFA count */ |
| 12367 | lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) | |
| 12368 | (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >> |
| 12369 | LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) |
| 12370 | << LINK_FLAP_AVOIDANCE_COUNT_OFFSET)); |
| 12371 | /* Clear link flap reason */ |
| 12372 | lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; |
| 12373 | |
| 12374 | REG_WR(bp, params->lfa_base + |
| 12375 | offsetof(struct shmem_lfa, lfa_sts), lfa_sts); |
| 12376 | |
| 12377 | /* Disable NIG DRAIN */ |
| 12378 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
| 12379 | |
| 12380 | /* Enable interrupts */ |
| 12381 | bnx2x_link_int_enable(params); |
| 12382 | return 0; |
| 12383 | } |
| 12384 | |
| 12385 | static void bnx2x_cannot_avoid_link_flap(struct link_params *params, |
| 12386 | struct link_vars *vars, |
| 12387 | int lfa_status) |
| 12388 | { |
| 12389 | u32 lfa_sts, cfg_idx, tmp_val; |
| 12390 | struct bnx2x *bp = params->bp; |
| 12391 | |
| 12392 | bnx2x_link_reset(params, vars, 1); |
| 12393 | |
| 12394 | if (!params->lfa_base) |
| 12395 | return; |
| 12396 | /* Store the new link parameters */ |
| 12397 | REG_WR(bp, params->lfa_base + |
| 12398 | offsetof(struct shmem_lfa, req_duplex), |
| 12399 | params->req_duplex[0] | (params->req_duplex[1] << 16)); |
| 12400 | |
| 12401 | REG_WR(bp, params->lfa_base + |
| 12402 | offsetof(struct shmem_lfa, req_flow_ctrl), |
| 12403 | params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); |
| 12404 | |
| 12405 | REG_WR(bp, params->lfa_base + |
| 12406 | offsetof(struct shmem_lfa, req_line_speed), |
| 12407 | params->req_line_speed[0] | (params->req_line_speed[1] << 16)); |
| 12408 | |
| 12409 | for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { |
| 12410 | REG_WR(bp, params->lfa_base + |
| 12411 | offsetof(struct shmem_lfa, |
| 12412 | speed_cap_mask[cfg_idx]), |
| 12413 | params->speed_cap_mask[cfg_idx]); |
| 12414 | } |
| 12415 | |
| 12416 | tmp_val = REG_RD(bp, params->lfa_base + |
| 12417 | offsetof(struct shmem_lfa, additional_config)); |
| 12418 | tmp_val &= ~REQ_FC_AUTO_ADV_MASK; |
| 12419 | tmp_val |= params->req_fc_auto_adv; |
| 12420 | |
| 12421 | REG_WR(bp, params->lfa_base + |
| 12422 | offsetof(struct shmem_lfa, additional_config), tmp_val); |
| 12423 | |
| 12424 | lfa_sts = REG_RD(bp, params->lfa_base + |
| 12425 | offsetof(struct shmem_lfa, lfa_sts)); |
| 12426 | |
| 12427 | /* Clear the "Don't Clear Statistics" bit, and set reason */ |
| 12428 | lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT; |
| 12429 | |
| 12430 | /* Set link flap reason */ |
| 12431 | lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; |
| 12432 | lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) << |
| 12433 | LFA_LINK_FLAP_REASON_OFFSET); |
| 12434 | |
| 12435 | /* Increment link flap counter */ |
| 12436 | lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) | |
| 12437 | (((((lfa_sts & LINK_FLAP_COUNT_MASK) >> |
| 12438 | LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) |
| 12439 | << LINK_FLAP_COUNT_OFFSET)); |
| 12440 | REG_WR(bp, params->lfa_base + |
| 12441 | offsetof(struct shmem_lfa, lfa_sts), lfa_sts); |
| 12442 | /* Proceed with regular link initialization */ |
| 12443 | } |
| 12444 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 12445 | int bnx2x_phy_init(struct link_params *params, struct link_vars *vars) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12446 | { |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 12447 | int lfa_status; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12448 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12449 | DP(NETIF_MSG_LINK, "Phy Initialization started\n"); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 12450 | DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n", |
| 12451 | params->req_line_speed[0], params->req_flow_ctrl[0]); |
| 12452 | DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", |
| 12453 | params->req_line_speed[1], params->req_flow_ctrl[1]); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12454 | vars->link_status = 0; |
| 12455 | vars->phy_link_up = 0; |
| 12456 | vars->link_up = 0; |
| 12457 | vars->line_speed = 0; |
| 12458 | vars->duplex = DUPLEX_FULL; |
| 12459 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
| 12460 | vars->mac_type = MAC_TYPE_NONE; |
| 12461 | vars->phy_flags = 0; |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 12462 | /* Driver opens NIG-BRB filters */ |
| 12463 | bnx2x_set_rx_filter(params, 1); |
| 12464 | /* Check if link flap can be avoided */ |
| 12465 | lfa_status = bnx2x_check_lfa(params); |
| 12466 | |
| 12467 | if (lfa_status == 0) { |
| 12468 | DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n"); |
| 12469 | return bnx2x_avoid_link_flap(params, vars); |
| 12470 | } |
| 12471 | |
| 12472 | DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n", |
| 12473 | lfa_status); |
| 12474 | bnx2x_cannot_avoid_link_flap(params, vars, lfa_status); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12475 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 12476 | /* Disable attentions */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12477 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, |
| 12478 | (NIG_MASK_XGXS0_LINK_STATUS | |
| 12479 | NIG_MASK_XGXS0_LINK10G | |
| 12480 | NIG_MASK_SERDES0_LINK_STATUS | |
| 12481 | NIG_MASK_MI_INT)); |
| 12482 | |
| 12483 | bnx2x_emac_init(params, vars); |
| 12484 | |
Yaniv Rosner | 27d9129 | 2012-04-04 01:28:54 +0000 | [diff] [blame] | 12485 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) |
| 12486 | vars->link_status |= LINK_STATUS_PFC_ENABLED; |
| 12487 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12488 | if (params->num_phys == 0) { |
| 12489 | DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); |
| 12490 | return -EINVAL; |
| 12491 | } |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 12492 | set_phy_vars(params, vars); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12493 | |
| 12494 | DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 12495 | switch (params->loopback_mode) { |
| 12496 | case LOOPBACK_BMAC: |
| 12497 | bnx2x_init_bmac_loopback(params, vars); |
| 12498 | break; |
| 12499 | case LOOPBACK_EMAC: |
| 12500 | bnx2x_init_emac_loopback(params, vars); |
| 12501 | break; |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 12502 | case LOOPBACK_XMAC: |
| 12503 | bnx2x_init_xmac_loopback(params, vars); |
| 12504 | break; |
| 12505 | case LOOPBACK_UMAC: |
| 12506 | bnx2x_init_umac_loopback(params, vars); |
| 12507 | break; |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 12508 | case LOOPBACK_XGXS: |
| 12509 | case LOOPBACK_EXT_PHY: |
| 12510 | bnx2x_init_xgxs_loopback(params, vars); |
| 12511 | break; |
| 12512 | default: |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 12513 | if (!CHIP_IS_E3(bp)) { |
| 12514 | if (params->switch_cfg == SWITCH_CFG_10G) |
| 12515 | bnx2x_xgxs_deassert(params); |
| 12516 | else |
| 12517 | bnx2x_serdes_deassert(bp, params->port); |
| 12518 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12519 | bnx2x_link_initialize(params, vars); |
| 12520 | msleep(30); |
| 12521 | bnx2x_link_int_enable(params); |
Yaniv Rosner | 9045f6b4 | 2011-05-31 21:28:27 +0000 | [diff] [blame] | 12522 | break; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12523 | } |
Yaniv Rosner | 55098c5 | 2012-04-03 18:41:27 +0000 | [diff] [blame] | 12524 | bnx2x_update_mng(params, vars->link_status); |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 12525 | |
| 12526 | bnx2x_update_mng_eee(params, vars->eee_status); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12527 | return 0; |
| 12528 | } |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 12529 | |
| 12530 | int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, |
| 12531 | u8 reset_ext_phy) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12532 | { |
| 12533 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | cf1d972 | 2010-11-01 05:32:34 +0000 | [diff] [blame] | 12534 | u8 phy_index, port = params->port, clear_latch_ind = 0; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12535 | DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 12536 | /* Disable attentions */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12537 | vars->link_status = 0; |
| 12538 | bnx2x_update_mng(params, vars->link_status); |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 12539 | vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | |
| 12540 | SHMEM_EEE_ACTIVE_BIT); |
| 12541 | bnx2x_update_mng_eee(params, vars->eee_status); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12542 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 12543 | (NIG_MASK_XGXS0_LINK_STATUS | |
| 12544 | NIG_MASK_XGXS0_LINK10G | |
| 12545 | NIG_MASK_SERDES0_LINK_STATUS | |
| 12546 | NIG_MASK_MI_INT)); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12547 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 12548 | /* Activate nig drain */ |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12549 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); |
| 12550 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 12551 | /* Disable nig egress interface */ |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 12552 | if (!CHIP_IS_E3(bp)) { |
| 12553 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); |
| 12554 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); |
| 12555 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12556 | |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 12557 | if (!CHIP_IS_E3(bp)) { |
| 12558 | bnx2x_set_bmac_rx(bp, params->chip_id, port, 0); |
| 12559 | } else { |
| 12560 | bnx2x_set_xmac_rxtx(params, 0); |
| 12561 | bnx2x_set_umac_rxtx(params, 0); |
| 12562 | } |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 12563 | /* Disable emac */ |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 12564 | if (!CHIP_IS_E3(bp)) |
| 12565 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12566 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 12567 | usleep_range(10000, 20000); |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 12568 | /* The PHY reset is controlled by GPIO 1 |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12569 | * Hold it as vars low |
| 12570 | */ |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 12571 | /* Clear link led */ |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 12572 | bnx2x_set_mdio_emac_per_phy(bp, params); |
Yaniv Rosner | 7f02c4a | 2010-09-07 11:41:23 +0000 | [diff] [blame] | 12573 | bnx2x_set_led(params, vars, LED_MODE_OFF, 0); |
| 12574 | |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12575 | if (reset_ext_phy) { |
| 12576 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
| 12577 | phy_index++) { |
Yaniv Rosner | 28f4881 | 2011-08-02 23:00:12 +0000 | [diff] [blame] | 12578 | if (params->phy[phy_index].link_reset) { |
| 12579 | bnx2x_set_aer_mmd(params, |
| 12580 | ¶ms->phy[phy_index]); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12581 | params->phy[phy_index].link_reset( |
| 12582 | ¶ms->phy[phy_index], |
| 12583 | params); |
Yaniv Rosner | 28f4881 | 2011-08-02 23:00:12 +0000 | [diff] [blame] | 12584 | } |
Yaniv Rosner | cf1d972 | 2010-11-01 05:32:34 +0000 | [diff] [blame] | 12585 | if (params->phy[phy_index].flags & |
| 12586 | FLAGS_REARM_LATCH_SIGNAL) |
| 12587 | clear_latch_ind = 1; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12588 | } |
| 12589 | } |
| 12590 | |
Yaniv Rosner | cf1d972 | 2010-11-01 05:32:34 +0000 | [diff] [blame] | 12591 | if (clear_latch_ind) { |
| 12592 | /* Clear latching indication */ |
| 12593 | bnx2x_rearm_latch_signal(bp, port, 0); |
| 12594 | bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, |
| 12595 | 1 << NIG_LATCH_BC_ENABLE_MI_INT); |
| 12596 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12597 | if (params->phy[INT_PHY].link_reset) |
| 12598 | params->phy[INT_PHY].link_reset( |
| 12599 | ¶ms->phy[INT_PHY], params); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12600 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 12601 | /* Disable nig ingress interface */ |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 12602 | if (!CHIP_IS_E3(bp)) { |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 12603 | /* Reset BigMac */ |
Yaniv Rosner | ce7c048 | 2011-10-27 05:09:47 +0000 | [diff] [blame] | 12604 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
| 12605 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 12606 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); |
| 12607 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); |
Yaniv Rosner | ce7c048 | 2011-10-27 05:09:47 +0000 | [diff] [blame] | 12608 | } else { |
| 12609 | u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; |
| 12610 | bnx2x_set_xumac_nig(params, 0, 0); |
| 12611 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & |
| 12612 | MISC_REGISTERS_RESET_REG_2_XMAC) |
| 12613 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, |
| 12614 | XMAC_CTRL_REG_SOFT_RESET); |
Yaniv Rosner | 9380bb9 | 2011-06-14 01:34:07 +0000 | [diff] [blame] | 12615 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12616 | vars->link_up = 0; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 12617 | vars->phy_flags = 0; |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12618 | return 0; |
| 12619 | } |
Yaniv Rosner | d3a8f13 | 2012-09-13 02:56:20 +0000 | [diff] [blame] | 12620 | int bnx2x_lfa_reset(struct link_params *params, |
| 12621 | struct link_vars *vars) |
| 12622 | { |
| 12623 | struct bnx2x *bp = params->bp; |
| 12624 | vars->link_up = 0; |
| 12625 | vars->phy_flags = 0; |
| 12626 | if (!params->lfa_base) |
| 12627 | return bnx2x_link_reset(params, vars, 1); |
| 12628 | /* |
| 12629 | * Activate NIG drain so that during this time the device won't send |
| 12630 | * anything while it is unable to response. |
| 12631 | */ |
| 12632 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); |
| 12633 | |
| 12634 | /* |
| 12635 | * Close gracefully the gate from BMAC to NIG such that no half packets |
| 12636 | * are passed. |
| 12637 | */ |
| 12638 | if (!CHIP_IS_E3(bp)) |
| 12639 | bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); |
| 12640 | |
| 12641 | if (CHIP_IS_E3(bp)) { |
| 12642 | bnx2x_set_xmac_rxtx(params, 0); |
| 12643 | bnx2x_set_umac_rxtx(params, 0); |
| 12644 | } |
| 12645 | /* Wait 10ms for the pipe to clean up*/ |
| 12646 | usleep_range(10000, 20000); |
| 12647 | |
| 12648 | /* Clean the NIG-BRB using the network filters in a way that will |
| 12649 | * not cut a packet in the middle. |
| 12650 | */ |
| 12651 | bnx2x_set_rx_filter(params, 0); |
| 12652 | |
| 12653 | /* |
| 12654 | * Re-open the gate between the BMAC and the NIG, after verifying the |
| 12655 | * gate to the BRB is closed, otherwise packets may arrive to the |
| 12656 | * firmware before driver had initialized it. The target is to achieve |
| 12657 | * minimum management protocol down time. |
| 12658 | */ |
| 12659 | if (!CHIP_IS_E3(bp)) |
| 12660 | bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1); |
| 12661 | |
| 12662 | if (CHIP_IS_E3(bp)) { |
| 12663 | bnx2x_set_xmac_rxtx(params, 1); |
| 12664 | bnx2x_set_umac_rxtx(params, 1); |
| 12665 | } |
| 12666 | /* Disable NIG drain */ |
| 12667 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
| 12668 | return 0; |
| 12669 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12670 | |
| 12671 | /****************************************************************************/ |
| 12672 | /* Common function */ |
| 12673 | /****************************************************************************/ |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 12674 | static int bnx2x_8073_common_init_phy(struct bnx2x *bp, |
| 12675 | u32 shmem_base_path[], |
| 12676 | u32 shmem2_base_path[], u8 phy_index, |
| 12677 | u32 chip_id) |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12678 | { |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 12679 | struct bnx2x_phy phy[PORT_MAX]; |
| 12680 | struct bnx2x_phy *phy_blk[PORT_MAX]; |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12681 | u16 val; |
Yaniv Rosner | c8e64df | 2011-01-30 04:15:00 +0000 | [diff] [blame] | 12682 | s8 port = 0; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12683 | s8 port_of_path = 0; |
Yaniv Rosner | c8e64df | 2011-01-30 04:15:00 +0000 | [diff] [blame] | 12684 | u32 swap_val, swap_override; |
| 12685 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); |
| 12686 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); |
| 12687 | port ^= (swap_val && swap_override); |
| 12688 | bnx2x_ext_phy_hw_reset(bp, port); |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12689 | /* PART1 - Reset both phys */ |
| 12690 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12691 | u32 shmem_base, shmem2_base; |
| 12692 | /* In E2, same phy is using for port0 of the two paths */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 12693 | if (CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12694 | shmem_base = shmem_base_path[0]; |
| 12695 | shmem2_base = shmem2_base_path[0]; |
| 12696 | port_of_path = port; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 12697 | } else { |
| 12698 | shmem_base = shmem_base_path[port]; |
| 12699 | shmem2_base = shmem2_base_path[port]; |
| 12700 | port_of_path = 0; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12701 | } |
| 12702 | |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12703 | /* Extract the ext phy address for the port */ |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 12704 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12705 | port_of_path, &phy[port]) != |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 12706 | 0) { |
| 12707 | DP(NETIF_MSG_LINK, "populate_phy failed\n"); |
| 12708 | return -EINVAL; |
| 12709 | } |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 12710 | /* Disable attentions */ |
Yaniv Rosner | 6a71bbe | 2010-11-01 05:32:31 +0000 | [diff] [blame] | 12711 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + |
| 12712 | port_of_path*4, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 12713 | (NIG_MASK_XGXS0_LINK_STATUS | |
| 12714 | NIG_MASK_XGXS0_LINK10G | |
| 12715 | NIG_MASK_SERDES0_LINK_STATUS | |
| 12716 | NIG_MASK_MI_INT)); |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12717 | |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12718 | /* Need to take the phy out of low power mode in order |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 12719 | * to write to access its registers |
| 12720 | */ |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12721 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 12722 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, |
| 12723 | port); |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12724 | |
| 12725 | /* Reset the phy */ |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 12726 | bnx2x_cl45_write(bp, &phy[port], |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 12727 | MDIO_PMA_DEVAD, |
| 12728 | MDIO_PMA_REG_CTRL, |
| 12729 | 1<<15); |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12730 | } |
| 12731 | |
| 12732 | /* Add delay of 150ms after reset */ |
| 12733 | msleep(150); |
| 12734 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 12735 | if (phy[PORT_0].addr & 0x1) { |
| 12736 | phy_blk[PORT_0] = &(phy[PORT_1]); |
| 12737 | phy_blk[PORT_1] = &(phy[PORT_0]); |
| 12738 | } else { |
| 12739 | phy_blk[PORT_0] = &(phy[PORT_0]); |
| 12740 | phy_blk[PORT_1] = &(phy[PORT_1]); |
| 12741 | } |
| 12742 | |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12743 | /* PART2 - Download firmware to both phys */ |
| 12744 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 12745 | if (CHIP_IS_E1x(bp)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12746 | port_of_path = port; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 12747 | else |
| 12748 | port_of_path = 0; |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12749 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12750 | DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", |
| 12751 | phy_blk[port]->addr); |
Yaniv Rosner | 5c99274b | 2011-01-18 04:33:36 +0000 | [diff] [blame] | 12752 | if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], |
| 12753 | port_of_path)) |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12754 | return -EINVAL; |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12755 | |
| 12756 | /* Only set bit 10 = 1 (Tx power down) */ |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 12757 | bnx2x_cl45_read(bp, phy_blk[port], |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 12758 | MDIO_PMA_DEVAD, |
| 12759 | MDIO_PMA_REG_TX_POWER_DOWN, &val); |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12760 | |
| 12761 | /* Phase1 of TX_POWER_DOWN reset */ |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 12762 | bnx2x_cl45_write(bp, phy_blk[port], |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 12763 | MDIO_PMA_DEVAD, |
| 12764 | MDIO_PMA_REG_TX_POWER_DOWN, |
| 12765 | (val | 1<<10)); |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12766 | } |
| 12767 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 12768 | /* Toggle Transmitter: Power down and then up with 600ms delay |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 12769 | * between |
| 12770 | */ |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12771 | msleep(600); |
| 12772 | |
| 12773 | /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ |
| 12774 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
Eilon Greenstein | f537225 | 2009-02-12 08:38:30 +0000 | [diff] [blame] | 12775 | /* Phase2 of POWER_DOWN_RESET */ |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12776 | /* Release bit 10 (Release Tx power down) */ |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 12777 | bnx2x_cl45_read(bp, phy_blk[port], |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 12778 | MDIO_PMA_DEVAD, |
| 12779 | MDIO_PMA_REG_TX_POWER_DOWN, &val); |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12780 | |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 12781 | bnx2x_cl45_write(bp, phy_blk[port], |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 12782 | MDIO_PMA_DEVAD, |
| 12783 | MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 12784 | usleep_range(15000, 30000); |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12785 | |
| 12786 | /* Read modify write the SPI-ROM version select register */ |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 12787 | bnx2x_cl45_read(bp, phy_blk[port], |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 12788 | MDIO_PMA_DEVAD, |
| 12789 | MDIO_PMA_REG_EDC_FFE_MAIN, &val); |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 12790 | bnx2x_cl45_write(bp, phy_blk[port], |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 12791 | MDIO_PMA_DEVAD, |
| 12792 | MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12793 | |
| 12794 | /* set GPIO2 back to LOW */ |
| 12795 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 12796 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12797 | } |
| 12798 | return 0; |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 12799 | } |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 12800 | static int bnx2x_8726_common_init_phy(struct bnx2x *bp, |
| 12801 | u32 shmem_base_path[], |
| 12802 | u32 shmem2_base_path[], u8 phy_index, |
| 12803 | u32 chip_id) |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12804 | { |
| 12805 | u32 val; |
| 12806 | s8 port; |
| 12807 | struct bnx2x_phy phy; |
| 12808 | /* Use port1 because of the static port-swap */ |
| 12809 | /* Enable the module detection interrupt */ |
| 12810 | val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); |
| 12811 | val |= ((1<<MISC_REGISTERS_GPIO_3)| |
| 12812 | (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); |
| 12813 | REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); |
| 12814 | |
Yaniv Rosner | 650154b | 2010-11-01 05:32:36 +0000 | [diff] [blame] | 12815 | bnx2x_ext_phy_hw_reset(bp, 0); |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 12816 | usleep_range(5000, 10000); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12817 | for (port = 0; port < PORT_MAX; port++) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12818 | u32 shmem_base, shmem2_base; |
| 12819 | |
| 12820 | /* In E2, same phy is using for port0 of the two paths */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 12821 | if (CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12822 | shmem_base = shmem_base_path[0]; |
| 12823 | shmem2_base = shmem2_base_path[0]; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 12824 | } else { |
| 12825 | shmem_base = shmem_base_path[port]; |
| 12826 | shmem2_base = shmem2_base_path[port]; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12827 | } |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12828 | /* Extract the ext phy address for the port */ |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 12829 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12830 | port, &phy) != |
| 12831 | 0) { |
| 12832 | DP(NETIF_MSG_LINK, "populate phy failed\n"); |
| 12833 | return -EINVAL; |
| 12834 | } |
| 12835 | |
| 12836 | /* Reset phy*/ |
| 12837 | bnx2x_cl45_write(bp, &phy, |
| 12838 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); |
| 12839 | |
| 12840 | |
| 12841 | /* Set fault module detected LED on */ |
| 12842 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 12843 | MISC_REGISTERS_GPIO_HIGH, |
| 12844 | port); |
Yaniv Rosner | de6eae1 | 2010-09-07 11:41:13 +0000 | [diff] [blame] | 12845 | } |
| 12846 | |
| 12847 | return 0; |
| 12848 | } |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 12849 | static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base, |
| 12850 | u8 *io_gpio, u8 *io_port) |
| 12851 | { |
| 12852 | |
| 12853 | u32 phy_gpio_reset = REG_RD(bp, shmem_base + |
| 12854 | offsetof(struct shmem_region, |
| 12855 | dev_info.port_hw_config[PORT_0].default_cfg)); |
| 12856 | switch (phy_gpio_reset) { |
| 12857 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: |
| 12858 | *io_gpio = 0; |
| 12859 | *io_port = 0; |
| 12860 | break; |
| 12861 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: |
| 12862 | *io_gpio = 1; |
| 12863 | *io_port = 0; |
| 12864 | break; |
| 12865 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: |
| 12866 | *io_gpio = 2; |
| 12867 | *io_port = 0; |
| 12868 | break; |
| 12869 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: |
| 12870 | *io_gpio = 3; |
| 12871 | *io_port = 0; |
| 12872 | break; |
| 12873 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: |
| 12874 | *io_gpio = 0; |
| 12875 | *io_port = 1; |
| 12876 | break; |
| 12877 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: |
| 12878 | *io_gpio = 1; |
| 12879 | *io_port = 1; |
| 12880 | break; |
| 12881 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: |
| 12882 | *io_gpio = 2; |
| 12883 | *io_port = 1; |
| 12884 | break; |
| 12885 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: |
| 12886 | *io_gpio = 3; |
| 12887 | *io_port = 1; |
| 12888 | break; |
| 12889 | default: |
| 12890 | /* Don't override the io_gpio and io_port */ |
| 12891 | break; |
| 12892 | } |
| 12893 | } |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 12894 | |
| 12895 | static int bnx2x_8727_common_init_phy(struct bnx2x *bp, |
| 12896 | u32 shmem_base_path[], |
| 12897 | u32 shmem2_base_path[], u8 phy_index, |
| 12898 | u32 chip_id) |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 12899 | { |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 12900 | s8 port, reset_gpio; |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 12901 | u32 swap_val, swap_override; |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 12902 | struct bnx2x_phy phy[PORT_MAX]; |
| 12903 | struct bnx2x_phy *phy_blk[PORT_MAX]; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12904 | s8 port_of_path; |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 12905 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); |
| 12906 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 12907 | |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 12908 | reset_gpio = MISC_REGISTERS_GPIO_1; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 12909 | port = 1; |
| 12910 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 12911 | /* Retrieve the reset gpio/port which control the reset. |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 12912 | * Default is GPIO1, PORT1 |
| 12913 | */ |
| 12914 | bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], |
| 12915 | (u8 *)&reset_gpio, (u8 *)&port); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 12916 | |
| 12917 | /* Calculate the port based on port swap */ |
| 12918 | port ^= (swap_val && swap_override); |
| 12919 | |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 12920 | /* Initiate PHY reset*/ |
| 12921 | bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, |
| 12922 | port); |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 12923 | usleep_range(1000, 2000); |
Yaniv Rosner | a8db5b4 | 2011-01-31 04:22:28 +0000 | [diff] [blame] | 12924 | bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, |
| 12925 | port); |
| 12926 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 12927 | usleep_range(5000, 10000); |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 12928 | |
| 12929 | /* PART1 - Reset both phys */ |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 12930 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12931 | u32 shmem_base, shmem2_base; |
| 12932 | |
| 12933 | /* In E2, same phy is using for port0 of the two paths */ |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 12934 | if (CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12935 | shmem_base = shmem_base_path[0]; |
| 12936 | shmem2_base = shmem2_base_path[0]; |
| 12937 | port_of_path = port; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 12938 | } else { |
| 12939 | shmem_base = shmem_base_path[port]; |
| 12940 | shmem2_base = shmem2_base_path[port]; |
| 12941 | port_of_path = 0; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12942 | } |
| 12943 | |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 12944 | /* Extract the ext phy address for the port */ |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 12945 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12946 | port_of_path, &phy[port]) != |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 12947 | 0) { |
| 12948 | DP(NETIF_MSG_LINK, "populate phy failed\n"); |
| 12949 | return -EINVAL; |
| 12950 | } |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 12951 | /* disable attentions */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12952 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + |
| 12953 | port_of_path*4, |
| 12954 | (NIG_MASK_XGXS0_LINK_STATUS | |
| 12955 | NIG_MASK_XGXS0_LINK10G | |
| 12956 | NIG_MASK_SERDES0_LINK_STATUS | |
| 12957 | NIG_MASK_MI_INT)); |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 12958 | |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 12959 | |
| 12960 | /* Reset the phy */ |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 12961 | bnx2x_cl45_write(bp, &phy[port], |
Yaniv Rosner | cd88cce | 2011-01-31 04:21:34 +0000 | [diff] [blame] | 12962 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 12963 | } |
| 12964 | |
| 12965 | /* Add delay of 150ms after reset */ |
| 12966 | msleep(150); |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 12967 | if (phy[PORT_0].addr & 0x1) { |
| 12968 | phy_blk[PORT_0] = &(phy[PORT_1]); |
| 12969 | phy_blk[PORT_1] = &(phy[PORT_0]); |
| 12970 | } else { |
| 12971 | phy_blk[PORT_0] = &(phy[PORT_0]); |
| 12972 | phy_blk[PORT_1] = &(phy[PORT_1]); |
| 12973 | } |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 12974 | /* PART2 - Download firmware to both phys */ |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 12975 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 12976 | if (CHIP_IS_E1x(bp)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12977 | port_of_path = port; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 12978 | else |
| 12979 | port_of_path = 0; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 12980 | DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", |
| 12981 | phy_blk[port]->addr); |
Yaniv Rosner | 5c99274b | 2011-01-18 04:33:36 +0000 | [diff] [blame] | 12982 | if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], |
| 12983 | port_of_path)) |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 12984 | return -EINVAL; |
Yaniv Rosner | 85242ee | 2011-07-05 01:06:53 +0000 | [diff] [blame] | 12985 | /* Disable PHY transmitter output */ |
| 12986 | bnx2x_cl45_write(bp, phy_blk[port], |
| 12987 | MDIO_PMA_DEVAD, |
| 12988 | MDIO_PMA_REG_TX_DISABLE, 1); |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 12989 | |
Yaniv Rosner | 5c99274b | 2011-01-18 04:33:36 +0000 | [diff] [blame] | 12990 | } |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 12991 | return 0; |
| 12992 | } |
| 12993 | |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 12994 | static int bnx2x_84833_common_init_phy(struct bnx2x *bp, |
| 12995 | u32 shmem_base_path[], |
| 12996 | u32 shmem2_base_path[], |
| 12997 | u8 phy_index, |
| 12998 | u32 chip_id) |
| 12999 | { |
| 13000 | u8 reset_gpios; |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 13001 | reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id); |
| 13002 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); |
| 13003 | udelay(10); |
| 13004 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); |
| 13005 | DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n", |
| 13006 | reset_gpios); |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 13007 | return 0; |
| 13008 | } |
| 13009 | |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 13010 | static int bnx2x_84833_pre_init_phy(struct bnx2x *bp, |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 13011 | struct bnx2x_phy *phy, |
| 13012 | u8 port) |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 13013 | { |
| 13014 | u16 val, cnt; |
| 13015 | /* Wait for FW completing its initialization. */ |
| 13016 | for (cnt = 0; cnt < 1500; cnt++) { |
| 13017 | bnx2x_cl45_read(bp, phy, |
| 13018 | MDIO_PMA_DEVAD, |
| 13019 | MDIO_PMA_REG_CTRL, &val); |
| 13020 | if (!(val & (1<<15))) |
| 13021 | break; |
Yaniv Rosner | 503976e | 2012-11-27 03:46:34 +0000 | [diff] [blame] | 13022 | usleep_range(1000, 2000); |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 13023 | } |
| 13024 | if (cnt >= 1500) { |
| 13025 | DP(NETIF_MSG_LINK, "84833 reset timeout\n"); |
| 13026 | return -EINVAL; |
| 13027 | } |
| 13028 | |
| 13029 | /* Put the port in super isolate mode. */ |
| 13030 | bnx2x_cl45_read(bp, phy, |
| 13031 | MDIO_CTL_DEVAD, |
| 13032 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val); |
| 13033 | val |= MDIO_84833_SUPER_ISOLATE; |
| 13034 | bnx2x_cl45_write(bp, phy, |
| 13035 | MDIO_CTL_DEVAD, |
| 13036 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, val); |
| 13037 | |
| 13038 | /* Save spirom version */ |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 13039 | bnx2x_save_848xx_spirom_version(phy, bp, port); |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 13040 | return 0; |
| 13041 | } |
| 13042 | |
| 13043 | int bnx2x_pre_init_phy(struct bnx2x *bp, |
| 13044 | u32 shmem_base, |
| 13045 | u32 shmem2_base, |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 13046 | u32 chip_id, |
| 13047 | u8 port) |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 13048 | { |
| 13049 | int rc = 0; |
| 13050 | struct bnx2x_phy phy; |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 13051 | if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base, shmem2_base, |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 13052 | port, &phy) != 0) { |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 13053 | DP(NETIF_MSG_LINK, "populate_phy failed\n"); |
| 13054 | return -EINVAL; |
| 13055 | } |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 13056 | bnx2x_set_mdio_clk(bp, chip_id, phy.mdio_ctrl); |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 13057 | switch (phy.type) { |
| 13058 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 13059 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: |
| 13060 | rc = bnx2x_84833_pre_init_phy(bp, &phy, port); |
Yaniv Rosner | 11b2ec6 | 2012-01-17 02:33:25 +0000 | [diff] [blame] | 13061 | break; |
| 13062 | default: |
| 13063 | break; |
| 13064 | } |
| 13065 | return rc; |
| 13066 | } |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 13067 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 13068 | static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], |
| 13069 | u32 shmem2_base_path[], u8 phy_index, |
| 13070 | u32 ext_phy_type, u32 chip_id) |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 13071 | { |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 13072 | int rc = 0; |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 13073 | |
| 13074 | switch (ext_phy_type) { |
| 13075 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 13076 | rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, |
| 13077 | shmem2_base_path, |
| 13078 | phy_index, chip_id); |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 13079 | break; |
Yaniv Rosner | e4d78f1 | 2011-05-31 21:25:55 +0000 | [diff] [blame] | 13080 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 13081 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
| 13082 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 13083 | rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, |
| 13084 | shmem2_base_path, |
| 13085 | phy_index, chip_id); |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 13086 | break; |
| 13087 | |
Eilon Greenstein | 589abe3 | 2009-02-12 08:36:55 +0000 | [diff] [blame] | 13088 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 13089 | /* GPIO1 affects both ports, so there's need to pull |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 13090 | * it for single port alone |
| 13091 | */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 13092 | rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, |
| 13093 | shmem2_base_path, |
| 13094 | phy_index, chip_id); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 13095 | break; |
Yaniv Rosner | 0d40f0d | 2011-06-14 01:34:27 +0000 | [diff] [blame] | 13096 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: |
Yaniv Rosner | 0f6bb03 | 2012-11-27 03:46:32 +0000 | [diff] [blame] | 13097 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 13098 | /* GPIO3's are linked, and so both need to be toggled |
Yaniv Rosner | 0d40f0d | 2011-06-14 01:34:27 +0000 | [diff] [blame] | 13099 | * to obtain required 2us pulse. |
| 13100 | */ |
Yaniv Rosner | 521683d | 2011-11-28 00:49:48 +0000 | [diff] [blame] | 13101 | rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, |
| 13102 | shmem2_base_path, |
| 13103 | phy_index, chip_id); |
Yaniv Rosner | 0d40f0d | 2011-06-14 01:34:27 +0000 | [diff] [blame] | 13104 | break; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 13105 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: |
| 13106 | rc = -EINVAL; |
Yaniv Rosner | 4f60dab | 2009-11-05 19:18:23 +0200 | [diff] [blame] | 13107 | break; |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 13108 | default: |
| 13109 | DP(NETIF_MSG_LINK, |
Yaniv Rosner | 2cf7acf | 2011-01-31 04:21:55 +0000 | [diff] [blame] | 13110 | "ext_phy 0x%x common init not required\n", |
| 13111 | ext_phy_type); |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 13112 | break; |
| 13113 | } |
| 13114 | |
Yuval Mintz | d231023 | 2012-06-20 19:05:19 +0000 | [diff] [blame] | 13115 | if (rc) |
Yaniv Rosner | 6d870c3 | 2011-01-31 04:22:20 +0000 | [diff] [blame] | 13116 | netdev_err(bp->dev, "Warning: PHY was not initialized," |
| 13117 | " Port %d\n", |
| 13118 | 0); |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 13119 | return rc; |
| 13120 | } |
| 13121 | |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 13122 | int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], |
| 13123 | u32 shmem2_base_path[], u32 chip_id) |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 13124 | { |
Yaniv Rosner | fcf5b65 | 2011-05-31 21:26:28 +0000 | [diff] [blame] | 13125 | int rc = 0; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 13126 | u32 phy_ver, val; |
| 13127 | u8 phy_index = 0; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 13128 | u32 ext_phy_type, ext_phy_config; |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 13129 | |
| 13130 | bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0); |
| 13131 | bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 13132 | DP(NETIF_MSG_LINK, "Begin common phy init\n"); |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 13133 | if (CHIP_IS_E3(bp)) { |
| 13134 | /* Enable EPIO */ |
| 13135 | val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); |
| 13136 | REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); |
| 13137 | } |
Yaniv Rosner | b21a342 | 2011-01-18 04:33:24 +0000 | [diff] [blame] | 13138 | /* Check if common init was already done */ |
| 13139 | phy_ver = REG_RD(bp, shmem_base_path[0] + |
| 13140 | offsetof(struct shmem_region, |
| 13141 | port_mb[PORT_0].ext_phy_fw_version)); |
| 13142 | if (phy_ver) { |
| 13143 | DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n", |
| 13144 | phy_ver); |
| 13145 | return 0; |
| 13146 | } |
| 13147 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 13148 | /* Read the ext_phy_type for arbitrary port(0) */ |
| 13149 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; |
| 13150 | phy_index++) { |
| 13151 | ext_phy_config = bnx2x_get_ext_phy_config(bp, |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 13152 | shmem_base_path[0], |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 13153 | phy_index, 0); |
| 13154 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 13155 | rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, |
| 13156 | shmem2_base_path, |
| 13157 | phy_index, ext_phy_type, |
| 13158 | chip_id); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 13159 | } |
| 13160 | return rc; |
| 13161 | } |
| 13162 | |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13163 | static void bnx2x_check_over_curr(struct link_params *params, |
| 13164 | struct link_vars *vars) |
| 13165 | { |
| 13166 | struct bnx2x *bp = params->bp; |
| 13167 | u32 cfg_pin; |
| 13168 | u8 port = params->port; |
| 13169 | u32 pin_val; |
| 13170 | |
| 13171 | cfg_pin = (REG_RD(bp, params->shmem_base + |
| 13172 | offsetof(struct shmem_region, |
| 13173 | dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & |
| 13174 | PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> |
| 13175 | PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; |
| 13176 | |
| 13177 | /* Ignore check if no external input PIN available */ |
| 13178 | if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) |
| 13179 | return; |
| 13180 | |
| 13181 | if (!pin_val) { |
| 13182 | if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { |
| 13183 | netdev_err(bp->dev, "Error: Power fault on Port %d has" |
| 13184 | " been detected and the power to " |
| 13185 | "that SFP+ module has been removed" |
| 13186 | " to prevent failure of the card." |
| 13187 | " Please remove the SFP+ module and" |
| 13188 | " restart the system to clear this" |
| 13189 | " error.\n", |
| 13190 | params->port); |
| 13191 | vars->phy_flags |= PHY_OVER_CURRENT_FLAG; |
Yaniv Rosner | 5a1fbf4 | 2012-11-27 03:46:31 +0000 | [diff] [blame] | 13192 | bnx2x_warpcore_power_module(params, 0); |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13193 | } |
| 13194 | } else |
| 13195 | vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; |
| 13196 | } |
| 13197 | |
Yuval Mintz | d0b8a6f | 2012-06-20 19:05:18 +0000 | [diff] [blame] | 13198 | /* Returns 0 if no change occured since last check; 1 otherwise. */ |
| 13199 | static u8 bnx2x_analyze_link_error(struct link_params *params, |
| 13200 | struct link_vars *vars, u32 status, |
| 13201 | u32 phy_flag, u32 link_flag, u8 notify) |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13202 | { |
| 13203 | struct bnx2x *bp = params->bp; |
| 13204 | /* Compare new value with previous value */ |
| 13205 | u8 led_mode; |
Yuval Mintz | d0b8a6f | 2012-06-20 19:05:18 +0000 | [diff] [blame] | 13206 | u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13207 | |
Yuval Mintz | d0b8a6f | 2012-06-20 19:05:18 +0000 | [diff] [blame] | 13208 | if ((status ^ old_status) == 0) |
| 13209 | return 0; |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13210 | |
| 13211 | /* If values differ */ |
Yuval Mintz | d0b8a6f | 2012-06-20 19:05:18 +0000 | [diff] [blame] | 13212 | switch (phy_flag) { |
| 13213 | case PHY_HALF_OPEN_CONN_FLAG: |
| 13214 | DP(NETIF_MSG_LINK, "Analyze Remote Fault\n"); |
| 13215 | break; |
| 13216 | case PHY_SFP_TX_FAULT_FLAG: |
| 13217 | DP(NETIF_MSG_LINK, "Analyze TX Fault\n"); |
| 13218 | break; |
| 13219 | default: |
Masanari Iida | efc7ce0 | 2012-11-02 04:36:17 +0000 | [diff] [blame] | 13220 | DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n"); |
Yuval Mintz | d0b8a6f | 2012-06-20 19:05:18 +0000 | [diff] [blame] | 13221 | } |
| 13222 | DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up, |
| 13223 | old_status, status); |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13224 | |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 13225 | /* a. Update shmem->link_status accordingly |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13226 | * b. Update link_vars->link_up |
| 13227 | */ |
Yuval Mintz | d0b8a6f | 2012-06-20 19:05:18 +0000 | [diff] [blame] | 13228 | if (status) { |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13229 | vars->link_status &= ~LINK_STATUS_LINK_UP; |
Yuval Mintz | d0b8a6f | 2012-06-20 19:05:18 +0000 | [diff] [blame] | 13230 | vars->link_status |= link_flag; |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13231 | vars->link_up = 0; |
Yuval Mintz | d0b8a6f | 2012-06-20 19:05:18 +0000 | [diff] [blame] | 13232 | vars->phy_flags |= phy_flag; |
Yaniv Rosner | 55098c5 | 2012-04-03 18:41:27 +0000 | [diff] [blame] | 13233 | |
| 13234 | /* activate nig drain */ |
| 13235 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 13236 | /* Set LED mode to off since the PHY doesn't know about these |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13237 | * errors |
| 13238 | */ |
| 13239 | led_mode = LED_MODE_OFF; |
| 13240 | } else { |
| 13241 | vars->link_status |= LINK_STATUS_LINK_UP; |
Yuval Mintz | d0b8a6f | 2012-06-20 19:05:18 +0000 | [diff] [blame] | 13242 | vars->link_status &= ~link_flag; |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13243 | vars->link_up = 1; |
Yuval Mintz | d0b8a6f | 2012-06-20 19:05:18 +0000 | [diff] [blame] | 13244 | vars->phy_flags &= ~phy_flag; |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13245 | led_mode = LED_MODE_OPER; |
Yaniv Rosner | 55098c5 | 2012-04-03 18:41:27 +0000 | [diff] [blame] | 13246 | |
| 13247 | /* Clear nig drain */ |
| 13248 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13249 | } |
Yaniv Rosner | 55098c5 | 2012-04-03 18:41:27 +0000 | [diff] [blame] | 13250 | bnx2x_sync_link(params, vars); |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13251 | /* Update the LED according to the link state */ |
| 13252 | bnx2x_set_led(params, vars, led_mode, SPEED_10000); |
| 13253 | |
| 13254 | /* Update link status in the shared memory */ |
| 13255 | bnx2x_update_mng(params, vars->link_status); |
| 13256 | |
| 13257 | /* C. Trigger General Attention */ |
| 13258 | vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT; |
Yaniv Rosner | 55098c5 | 2012-04-03 18:41:27 +0000 | [diff] [blame] | 13259 | if (notify) |
| 13260 | bnx2x_notify_link_changed(bp); |
Yuval Mintz | d0b8a6f | 2012-06-20 19:05:18 +0000 | [diff] [blame] | 13261 | |
| 13262 | return 1; |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13263 | } |
| 13264 | |
Yaniv Rosner | de6f337 | 2011-08-02 22:59:25 +0000 | [diff] [blame] | 13265 | /****************************************************************************** |
| 13266 | * Description: |
| 13267 | * This function checks for half opened connection change indication. |
| 13268 | * When such change occurs, it calls the bnx2x_analyze_link_error |
| 13269 | * to check if Remote Fault is set or cleared. Reception of remote fault |
| 13270 | * status message in the MAC indicates that the peer's MAC has detected |
| 13271 | * a fault, for example, due to break in the TX side of fiber. |
| 13272 | * |
| 13273 | ******************************************************************************/ |
Yaniv Rosner | 55098c5 | 2012-04-03 18:41:27 +0000 | [diff] [blame] | 13274 | int bnx2x_check_half_open_conn(struct link_params *params, |
| 13275 | struct link_vars *vars, |
| 13276 | u8 notify) |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13277 | { |
| 13278 | struct bnx2x *bp = params->bp; |
| 13279 | u32 lss_status = 0; |
| 13280 | u32 mac_base; |
| 13281 | /* In case link status is physically up @ 10G do */ |
Yaniv Rosner | 55098c5 | 2012-04-03 18:41:27 +0000 | [diff] [blame] | 13282 | if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || |
| 13283 | (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) |
| 13284 | return 0; |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13285 | |
Yaniv Rosner | de6f337 | 2011-08-02 22:59:25 +0000 | [diff] [blame] | 13286 | if (CHIP_IS_E3(bp) && |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13287 | (REG_RD(bp, MISC_REG_RESET_REG_2) & |
Yaniv Rosner | de6f337 | 2011-08-02 22:59:25 +0000 | [diff] [blame] | 13288 | (MISC_REGISTERS_RESET_REG_2_XMAC))) { |
| 13289 | /* Check E3 XMAC */ |
Yaniv Rosner | 8f73f0b | 2012-04-03 18:41:31 +0000 | [diff] [blame] | 13290 | /* Note that link speed cannot be queried here, since it may be |
Yaniv Rosner | de6f337 | 2011-08-02 22:59:25 +0000 | [diff] [blame] | 13291 | * zero while link is down. In case UMAC is active, LSS will |
| 13292 | * simply not be set |
| 13293 | */ |
| 13294 | mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; |
| 13295 | |
| 13296 | /* Clear stick bits (Requires rising edge) */ |
| 13297 | REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); |
| 13298 | REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, |
| 13299 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | |
| 13300 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); |
| 13301 | if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) |
| 13302 | lss_status = 1; |
| 13303 | |
Yuval Mintz | d0b8a6f | 2012-06-20 19:05:18 +0000 | [diff] [blame] | 13304 | bnx2x_analyze_link_error(params, vars, lss_status, |
| 13305 | PHY_HALF_OPEN_CONN_FLAG, |
| 13306 | LINK_STATUS_NONE, notify); |
Yaniv Rosner | de6f337 | 2011-08-02 22:59:25 +0000 | [diff] [blame] | 13307 | } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & |
| 13308 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13309 | /* Check E1X / E2 BMAC */ |
| 13310 | u32 lss_status_reg; |
| 13311 | u32 wb_data[2]; |
| 13312 | mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : |
| 13313 | NIG_REG_INGRESS_BMAC0_MEM; |
| 13314 | /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ |
| 13315 | if (CHIP_IS_E2(bp)) |
| 13316 | lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; |
| 13317 | else |
| 13318 | lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; |
| 13319 | |
| 13320 | REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); |
| 13321 | lss_status = (wb_data[0] > 0); |
| 13322 | |
Yuval Mintz | d0b8a6f | 2012-06-20 19:05:18 +0000 | [diff] [blame] | 13323 | bnx2x_analyze_link_error(params, vars, lss_status, |
| 13324 | PHY_HALF_OPEN_CONN_FLAG, |
| 13325 | LINK_STATUS_NONE, notify); |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13326 | } |
Yaniv Rosner | 55098c5 | 2012-04-03 18:41:27 +0000 | [diff] [blame] | 13327 | return 0; |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13328 | } |
Yuval Mintz | d0b8a6f | 2012-06-20 19:05:18 +0000 | [diff] [blame] | 13329 | static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy, |
| 13330 | struct link_params *params, |
| 13331 | struct link_vars *vars) |
| 13332 | { |
| 13333 | struct bnx2x *bp = params->bp; |
| 13334 | u32 cfg_pin, value = 0; |
| 13335 | u8 led_change, port = params->port; |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13336 | |
Yuval Mintz | d0b8a6f | 2012-06-20 19:05:18 +0000 | [diff] [blame] | 13337 | /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ |
| 13338 | cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, |
| 13339 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & |
| 13340 | PORT_HW_CFG_E3_TX_FAULT_MASK) >> |
| 13341 | PORT_HW_CFG_E3_TX_FAULT_SHIFT; |
| 13342 | |
| 13343 | if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) { |
| 13344 | DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin); |
| 13345 | return; |
| 13346 | } |
| 13347 | |
| 13348 | led_change = bnx2x_analyze_link_error(params, vars, value, |
| 13349 | PHY_SFP_TX_FAULT_FLAG, |
| 13350 | LINK_STATUS_SFP_TX_FAULT, 1); |
| 13351 | |
| 13352 | if (led_change) { |
| 13353 | /* Change TX_Fault led, set link status for further syncs */ |
| 13354 | u8 led_mode; |
| 13355 | |
| 13356 | if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { |
| 13357 | led_mode = MISC_REGISTERS_GPIO_HIGH; |
| 13358 | vars->link_status |= LINK_STATUS_SFP_TX_FAULT; |
| 13359 | } else { |
| 13360 | led_mode = MISC_REGISTERS_GPIO_LOW; |
| 13361 | vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; |
| 13362 | } |
| 13363 | |
| 13364 | /* If module is unapproved, led should be on regardless */ |
| 13365 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { |
| 13366 | DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n", |
| 13367 | led_mode); |
| 13368 | bnx2x_set_e3_module_fault_led(params, led_mode); |
| 13369 | } |
| 13370 | } |
| 13371 | } |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 13372 | static void bnx2x_disable_kr2(struct link_params *params, |
| 13373 | struct link_vars *vars, |
| 13374 | struct bnx2x_phy *phy) |
| 13375 | { |
| 13376 | struct bnx2x *bp = params->bp; |
| 13377 | int i; |
| 13378 | static struct bnx2x_reg_set reg_set[] = { |
| 13379 | /* Step 1 - Program the TX/RX alignment markers */ |
| 13380 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, |
| 13381 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, |
| 13382 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, |
| 13383 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, |
| 13384 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, |
| 13385 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, |
| 13386 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, |
| 13387 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, |
| 13388 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, |
| 13389 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, |
| 13390 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, |
| 13391 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, |
| 13392 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, |
| 13393 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, |
| 13394 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} |
| 13395 | }; |
| 13396 | DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n"); |
| 13397 | |
Sasha Levin | b5a0555 | 2012-12-20 09:11:24 +0000 | [diff] [blame] | 13398 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 13399 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, |
| 13400 | reg_set[i].val); |
| 13401 | vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; |
| 13402 | bnx2x_update_link_attr(params, vars->link_attr_sync); |
| 13403 | |
| 13404 | /* Restart AN on leading lane */ |
| 13405 | bnx2x_warpcore_restart_AN_KR(phy, params); |
| 13406 | } |
| 13407 | |
| 13408 | static void bnx2x_kr2_recovery(struct link_params *params, |
| 13409 | struct link_vars *vars, |
| 13410 | struct bnx2x_phy *phy) |
| 13411 | { |
| 13412 | struct bnx2x *bp = params->bp; |
| 13413 | DP(NETIF_MSG_LINK, "KR2 recovery\n"); |
| 13414 | bnx2x_warpcore_enable_AN_KR2(phy, params, vars); |
| 13415 | bnx2x_warpcore_restart_AN_KR(phy, params); |
| 13416 | } |
| 13417 | |
| 13418 | static void bnx2x_check_kr2_wa(struct link_params *params, |
| 13419 | struct link_vars *vars, |
| 13420 | struct bnx2x_phy *phy) |
| 13421 | { |
| 13422 | struct bnx2x *bp = params->bp; |
| 13423 | u16 base_page, next_page, not_kr2_device, lane; |
| 13424 | int sigdet = bnx2x_warpcore_get_sigdet(phy, params); |
| 13425 | |
| 13426 | if (!sigdet) { |
| 13427 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) |
| 13428 | bnx2x_kr2_recovery(params, vars, phy); |
| 13429 | return; |
| 13430 | } |
| 13431 | |
| 13432 | lane = bnx2x_get_warpcore_lane(phy, params); |
| 13433 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
| 13434 | MDIO_AER_BLOCK_AER_REG, lane); |
| 13435 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, |
| 13436 | MDIO_AN_REG_LP_AUTO_NEG, &base_page); |
| 13437 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, |
| 13438 | MDIO_AN_REG_LP_AUTO_NEG2, &next_page); |
| 13439 | bnx2x_set_aer_mmd(params, phy); |
| 13440 | |
| 13441 | /* CL73 has not begun yet */ |
| 13442 | if (base_page == 0) { |
| 13443 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) |
| 13444 | bnx2x_kr2_recovery(params, vars, phy); |
| 13445 | return; |
| 13446 | } |
| 13447 | |
| 13448 | /* In case NP bit is not set in the BasePage, or it is set, |
| 13449 | * but only KX is advertised, declare this link partner as non-KR2 |
| 13450 | * device. |
| 13451 | */ |
| 13452 | not_kr2_device = (((base_page & 0x8000) == 0) || |
| 13453 | (((base_page & 0x8000) && |
| 13454 | ((next_page & 0xe0) == 0x2)))); |
| 13455 | |
| 13456 | /* In case KR2 is already disabled, check if we need to re-enable it */ |
| 13457 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { |
| 13458 | if (!not_kr2_device) { |
| 13459 | DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, |
Yaniv Rosner | fd5dfca | 2012-11-27 03:46:36 +0000 | [diff] [blame] | 13460 | next_page); |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 13461 | bnx2x_kr2_recovery(params, vars, phy); |
| 13462 | } |
| 13463 | return; |
| 13464 | } |
| 13465 | /* KR2 is enabled, but not KR2 device */ |
| 13466 | if (not_kr2_device) { |
| 13467 | /* Disable KR2 on both lanes */ |
| 13468 | DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page); |
| 13469 | bnx2x_disable_kr2(params, vars, phy); |
| 13470 | return; |
| 13471 | } |
| 13472 | } |
| 13473 | |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13474 | void bnx2x_period_func(struct link_params *params, struct link_vars *vars) |
| 13475 | { |
Yaniv Rosner | de6f337 | 2011-08-02 22:59:25 +0000 | [diff] [blame] | 13476 | u16 phy_idx; |
Yaniv Rosner | 55098c5 | 2012-04-03 18:41:27 +0000 | [diff] [blame] | 13477 | struct bnx2x *bp = params->bp; |
Yaniv Rosner | de6f337 | 2011-08-02 22:59:25 +0000 | [diff] [blame] | 13478 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { |
| 13479 | if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { |
| 13480 | bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); |
Yaniv Rosner | 55098c5 | 2012-04-03 18:41:27 +0000 | [diff] [blame] | 13481 | if (bnx2x_check_half_open_conn(params, vars, 1) != |
| 13482 | 0) |
| 13483 | DP(NETIF_MSG_LINK, "Fault detection failed\n"); |
Yaniv Rosner | de6f337 | 2011-08-02 22:59:25 +0000 | [diff] [blame] | 13484 | break; |
| 13485 | } |
| 13486 | } |
| 13487 | |
Yaniv Rosner | a9077bf | 2011-10-27 05:09:46 +0000 | [diff] [blame] | 13488 | if (CHIP_IS_E3(bp)) { |
| 13489 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; |
| 13490 | bnx2x_set_aer_mmd(params, phy); |
Yaniv Rosner | 4e7b499 | 2012-11-27 03:46:29 +0000 | [diff] [blame] | 13491 | if ((phy->supported & SUPPORTED_20000baseKR2_Full) && |
| 13492 | (phy->speed_cap_mask & SPEED_20000)) |
| 13493 | bnx2x_check_kr2_wa(params, vars, phy); |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13494 | bnx2x_check_over_curr(params, vars); |
Yuval Mintz | d0b8a6f | 2012-06-20 19:05:18 +0000 | [diff] [blame] | 13495 | if (vars->rx_tx_asic_rst) |
| 13496 | bnx2x_warpcore_config_runtime(phy, params, vars); |
| 13497 | |
| 13498 | if ((REG_RD(bp, params->shmem_base + |
| 13499 | offsetof(struct shmem_region, dev_info. |
| 13500 | port_hw_config[params->port].default_cfg)) |
| 13501 | & PORT_HW_CFG_NET_SERDES_IF_MASK) == |
| 13502 | PORT_HW_CFG_NET_SERDES_IF_SFI) { |
| 13503 | if (bnx2x_is_sfp_module_plugged(phy, params)) { |
| 13504 | bnx2x_sfp_tx_fault_detection(phy, params, vars); |
| 13505 | } else if (vars->link_status & |
| 13506 | LINK_STATUS_SFP_TX_FAULT) { |
| 13507 | /* Clean trail, interrupt corrects the leds */ |
| 13508 | vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; |
| 13509 | vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; |
| 13510 | /* Update link status in the shared memory */ |
| 13511 | bnx2x_update_mng(params, vars->link_status); |
| 13512 | } |
| 13513 | } |
Yaniv Rosner | a9077bf | 2011-10-27 05:09:46 +0000 | [diff] [blame] | 13514 | } |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13515 | } |
| 13516 | |
Yaniv Rosner | d90d96b | 2010-09-07 11:41:04 +0000 | [diff] [blame] | 13517 | u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, |
| 13518 | u32 shmem_base, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 13519 | u32 shmem2_base, |
Yaniv Rosner | d90d96b | 2010-09-07 11:41:04 +0000 | [diff] [blame] | 13520 | u8 port) |
| 13521 | { |
| 13522 | u8 phy_index, fan_failure_det_req = 0; |
| 13523 | struct bnx2x_phy phy; |
| 13524 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; |
| 13525 | phy_index++) { |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 13526 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
Yaniv Rosner | d90d96b | 2010-09-07 11:41:04 +0000 | [diff] [blame] | 13527 | port, &phy) |
| 13528 | != 0) { |
| 13529 | DP(NETIF_MSG_LINK, "populate phy failed\n"); |
| 13530 | return 0; |
| 13531 | } |
| 13532 | fan_failure_det_req |= (phy.flags & |
| 13533 | FLAGS_FAN_FAILURE_DET_REQ); |
| 13534 | } |
| 13535 | return fan_failure_det_req; |
| 13536 | } |
| 13537 | |
| 13538 | void bnx2x_hw_reset_phy(struct link_params *params) |
| 13539 | { |
| 13540 | u8 phy_index; |
Yaniv Rosner | 985848f | 2011-07-05 01:06:48 +0000 | [diff] [blame] | 13541 | struct bnx2x *bp = params->bp; |
| 13542 | bnx2x_update_mng(params, 0); |
| 13543 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, |
| 13544 | (NIG_MASK_XGXS0_LINK_STATUS | |
| 13545 | NIG_MASK_XGXS0_LINK10G | |
| 13546 | NIG_MASK_SERDES0_LINK_STATUS | |
| 13547 | NIG_MASK_MI_INT)); |
| 13548 | |
| 13549 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; |
Yaniv Rosner | d90d96b | 2010-09-07 11:41:04 +0000 | [diff] [blame] | 13550 | phy_index++) { |
| 13551 | if (params->phy[phy_index].hw_reset) { |
| 13552 | params->phy[phy_index].hw_reset( |
| 13553 | ¶ms->phy[phy_index], |
| 13554 | params); |
| 13555 | params->phy[phy_index] = phy_null; |
| 13556 | } |
| 13557 | } |
| 13558 | } |
Yaniv Rosner | 020c7e3 | 2011-05-31 21:28:43 +0000 | [diff] [blame] | 13559 | |
| 13560 | void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, |
| 13561 | u32 chip_id, u32 shmem_base, u32 shmem2_base, |
| 13562 | u8 port) |
| 13563 | { |
| 13564 | u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; |
| 13565 | u32 val; |
| 13566 | u32 offset, aeu_mask, swap_val, swap_override, sync_offset; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 13567 | if (CHIP_IS_E3(bp)) { |
| 13568 | if (bnx2x_get_mod_abs_int_cfg(bp, chip_id, |
| 13569 | shmem_base, |
| 13570 | port, |
| 13571 | &gpio_num, |
| 13572 | &gpio_port) != 0) |
| 13573 | return; |
| 13574 | } else { |
Yaniv Rosner | 020c7e3 | 2011-05-31 21:28:43 +0000 | [diff] [blame] | 13575 | struct bnx2x_phy phy; |
| 13576 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; |
| 13577 | phy_index++) { |
| 13578 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, |
| 13579 | shmem2_base, port, &phy) |
| 13580 | != 0) { |
| 13581 | DP(NETIF_MSG_LINK, "populate phy failed\n"); |
| 13582 | return; |
| 13583 | } |
| 13584 | if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { |
| 13585 | gpio_num = MISC_REGISTERS_GPIO_3; |
| 13586 | gpio_port = port; |
| 13587 | break; |
| 13588 | } |
| 13589 | } |
| 13590 | } |
| 13591 | |
| 13592 | if (gpio_num == 0xff) |
| 13593 | return; |
| 13594 | |
| 13595 | /* Set GPIO3 to trigger SFP+ module insertion/removal */ |
| 13596 | bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); |
| 13597 | |
| 13598 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); |
| 13599 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); |
| 13600 | gpio_port ^= (swap_val && swap_override); |
| 13601 | |
| 13602 | vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << |
| 13603 | (gpio_num + (gpio_port << 2)); |
| 13604 | |
| 13605 | sync_offset = shmem_base + |
| 13606 | offsetof(struct shmem_region, |
| 13607 | dev_info.port_hw_config[port].aeu_int_mask); |
| 13608 | REG_WR(bp, sync_offset, vars->aeu_int_mask); |
| 13609 | |
| 13610 | DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", |
| 13611 | gpio_num, gpio_port, vars->aeu_int_mask); |
| 13612 | |
| 13613 | if (port == 0) |
| 13614 | offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; |
| 13615 | else |
| 13616 | offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; |
| 13617 | |
| 13618 | /* Open appropriate AEU for interrupts */ |
| 13619 | aeu_mask = REG_RD(bp, offset); |
| 13620 | aeu_mask |= vars->aeu_int_mask; |
| 13621 | REG_WR(bp, offset, aeu_mask); |
| 13622 | |
| 13623 | /* Enable the GPIO to trigger interrupt */ |
| 13624 | val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); |
| 13625 | val |= 1 << (gpio_num + (gpio_port << 2)); |
| 13626 | REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); |
| 13627 | } |