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gerrit-public.fairphone.software / kernel / msm-4.9 / 31aac5fd9e669427539f0ead7f5b79b8fd11e95a / . / arch / arm64 / boot / dts / qcom / sdm845-v2.dtsi
blob: 1cc46350c50ca9ec8d339d75614e9a431da111cc [file] [log] [blame]
Channagoud Kadabi459f0112017-03-20 12:42:15 -0700[diff] [blame]1/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "sdm845.dtsi"
Soundrapandian Jeyaprakash3cc03bb2017-08-09 15:16:41 -0700[diff] [blame]14#include "sdm845-v2-camera.dtsi"
Channagoud Kadabi459f0112017-03-20 12:42:15 -0700[diff] [blame]15
16/ {
17 model = "Qualcomm Technologies, Inc. SDM845 V2";
18 qcom,msm-id = <321 0x20000>;
19};
David Collins36050182017-04-26 11:41:22 -0700[diff] [blame]20
Subhash Jadavani0842b272017-07-19 17:05:13 -0700[diff] [blame]21&sdhc_2 {
Subhash Jadavani3497a962017-07-31 13:57:47 -0700[diff] [blame]22 /delete-property/ qcom,sdr104-wa;
Subhash Jadavani0842b272017-07-19 17:05:13 -0700[diff] [blame]23};
24
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]25/delete-node/ &apc0_cpr;
26/delete-node/ &apc1_cpr;
27
28&soc {
29 /* CPR controller regulators */
30 apc0_cpr: cprh-ctrl@17dc0000 {
31 compatible = "qcom,cprh-sdm845-v2-kbss-regulator";
32 reg = <0x17dc0000 0x4000>,
33 <0x00784000 0x1000>,
34 <0x17840000 0x1000>;
35 reg-names = "cpr_ctrl", "fuse_base", "saw";
36 clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
37 clock-names = "core_clk";
38 qcom,cpr-ctrl-name = "apc0";
39 qcom,cpr-controller-id = <0>;
40
41 qcom,cpr-sensor-time = <1000>;
42 qcom,cpr-loop-time = <5000000>;
43 qcom,cpr-idle-cycles = <15>;
44 qcom,cpr-up-down-delay-time = <3000>;
45 qcom,cpr-step-quot-init-min = <11>;
46 qcom,cpr-step-quot-init-max = <12>;
47 qcom,cpr-count-mode = <0>; /* All at once */
48 qcom,cpr-count-repeat = <20>;
49 qcom,cpr-down-error-step-limit = <1>;
50 qcom,cpr-up-error-step-limit = <1>;
51 qcom,cpr-corner-switch-delay-time = <1042>;
52 qcom,cpr-voltage-settling-time = <1760>;
53 qcom,cpr-reset-step-quot-loop-en;
54
55 qcom,voltage-step = <4000>;
56 qcom,voltage-base = <352000>;
57 qcom,cpr-saw-use-unit-mV;
58
59 qcom,saw-avs-ctrl = <0x101C031>;
60 qcom,saw-avs-limit = <0x3B803B8>;
61
62 qcom,cpr-enable;
63 qcom,cpr-hw-closed-loop;
64
65 qcom,cpr-panic-reg-addr-list =
66 <0x17dc3a84 0x17dc3a88 0x17840c18>;
67 qcom,cpr-panic-reg-name-list =
68 "APSS_SILVER_CPRH_STATUS_0",
69 "APSS_SILVER_CPRH_STATUS_1",
70 "SILVER_SAW4_PMIC_STS";
71
David Collinsfc666ff2017-08-31 10:46:18 -0700[diff] [blame]72 qcom,cpr-aging-ref-voltage = <1000000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]73 vdd-supply = <&pm8998_s13>;
74
75 thread@0 {
76 qcom,cpr-thread-id = <0>;
77 qcom,cpr-consecutive-up = <0>;
78 qcom,cpr-consecutive-down = <0>;
79 qcom,cpr-up-threshold = <2>;
80 qcom,cpr-down-threshold = <2>;
81
82 apc0_pwrcl_vreg: regulator {
83 regulator-name = "apc0_pwrcl_corner";
84 regulator-min-microvolt = <1>;
85 regulator-max-microvolt = <18>;
86
87 qcom,cpr-fuse-corners = <4>;
88 qcom,cpr-fuse-combos = <16>;
89 qcom,cpr-speed-bins = <2>;
90 qcom,cpr-speed-bin-corners = <18 18>;
91 qcom,cpr-corners = <18>;
92
93 qcom,cpr-corner-fmax-map = <6 12 15 18>;
94
95 qcom,cpr-voltage-ceiling =
96 <828000 828000 828000 828000 828000
97 828000 828000 828000 828000 828000
98 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]99 932000 1000000 1000000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]100
101 qcom,cpr-voltage-floor =
102 <568000 568000 568000 568000 568000
103 568000 568000 568000 568000 568000
104 568000 568000 568000 568000 568000
105 568000 568000 568000>;
106
107 qcom,cpr-floor-to-ceiling-max-range =
108 <32000 32000 32000 32000 32000
109 32000 32000 32000 32000 32000
110 32000 32000 32000 32000 32000
111 32000 40000 40000>;
112
113 qcom,corner-frequencies =
114 <300000000 403200000 480000000
115 576000000 652800000 748800000
116 825600000 902400000 979200000
117 1056000000 1132800000 1228800000
118 1324800000 1420800000 1516800000
119 1612800000 1689600000 1766400000>;
120
121 qcom,cpr-ro-scaling-factor =
122 <2594 2795 2576 2761 2469 2673 2198
123 2553 3188 3255 3191 2962 3055 2984
124 2043 2947>,
125 <2594 2795 2576 2761 2469 2673 2198
126 2553 3188 3255 3191 2962 3055 2984
127 2043 2947>,
128 <2259 2389 2387 2531 2294 2464 2218
129 2476 2525 2855 2817 2836 2740 2490
130 1950 2632>,
131 <2259 2389 2387 2531 2294 2464 2218
132 2476 2525 2855 2817 2836 2740 2490
133 1950 2632>;
134
135 qcom,cpr-open-loop-voltage-fuse-adjustment =
David Collins33b588a2017-08-22 15:28:03 -0700[diff] [blame]136 < 0 0 12000 12000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]137
138 qcom,cpr-closed-loop-voltage-fuse-adjustment =
David Collins33b588a2017-08-22 15:28:03 -0700[diff] [blame]139 < 0 0 12000 10000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]140
141 qcom,allow-voltage-interpolation;
142 qcom,allow-quotient-interpolation;
143 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
144
145 qcom,cpr-aging-max-voltage-adjustment = <15000>;
146 qcom,cpr-aging-ref-corner = <18>;
147 qcom,cpr-aging-ro-scaling-factor = <1620>;
148 qcom,allow-aging-voltage-adjustment =
149 /* Speed bin 0 */
150 <0 1 1 1 1 1 1 1>,
151 /* Speed bin 1 */
152 <0 1 1 1 1 1 1 1>;
153 qcom,allow-aging-open-loop-voltage-adjustment =
154 <1>;
155 };
156 };
157
158 thread@1 {
159 qcom,cpr-thread-id = <1>;
160 qcom,cpr-consecutive-up = <0>;
161 qcom,cpr-consecutive-down = <0>;
162 qcom,cpr-up-threshold = <2>;
163 qcom,cpr-down-threshold = <2>;
164
165 apc0_l3_vreg: regulator {
166 regulator-name = "apc0_l3_corner";
167 regulator-min-microvolt = <1>;
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]168 regulator-max-microvolt = <15>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]169
170 qcom,cpr-fuse-corners = <4>;
171 qcom,cpr-fuse-combos = <16>;
172 qcom,cpr-speed-bins = <2>;
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]173 qcom,cpr-speed-bin-corners = <14 15>;
174 qcom,cpr-corners =
175 /* Speed bin 0 */
176 <14 14 14 14 14 14 14 14>,
177 /* Speed bin 1 */
178 <15 15 15 15 15 15 15 15>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]179
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]180 qcom,cpr-corner-fmax-map =
181 /* Speed bin 0 */
182 <4 8 11 14>,
183 /* Speed bin 1 */
184 <4 8 11 15>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]185
186 qcom,cpr-voltage-ceiling =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]187 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]188 <828000 828000 828000 828000 828000
189 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]190 828000 932000 932000 1000000>,
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]191 /* Speed bin 1 */
192 <828000 828000 828000 828000 828000
193 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]194 828000 932000 932000 1000000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]195 1000000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]196
197 qcom,cpr-voltage-floor =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]198 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]199 <568000 568000 568000 568000 568000
200 568000 568000 568000 568000 568000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]201 568000 568000 568000 568000>,
202 /* Speed bin 1 */
203 <568000 568000 568000 568000 568000
204 568000 568000 568000 568000 568000
205 568000 568000 568000 568000
206 568000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]207
208 qcom,cpr-floor-to-ceiling-max-range =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]209 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]210 <32000 32000 32000 32000 32000
211 32000 32000 32000 32000 32000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]212 32000 32000 32000 40000>,
213 /* Speed bin 1 */
214 <32000 32000 32000 32000 32000
215 32000 32000 32000 32000 32000
216 32000 32000 32000 40000 40000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]217
218 qcom,corner-frequencies =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]219 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]220 <300000000 403200000 480000000
221 576000000 652800000 748800000
222 844800000 940800000 1036800000
223 1132800000 1209600000 1305600000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]224 1401600000 1478400000>,
225 /* Speed bin 1 */
226 <300000000 403200000 480000000
227 576000000 652800000 748800000
228 844800000 940800000 1036800000
229 1132800000 1209600000 1305600000
230 1401600000 1497600000 1593600000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]231
232 qcom,cpr-ro-scaling-factor =
233 <2857 3056 2828 2952 2699 2796 2447
234 2631 2630 2579 2244 3343 3287 3137
235 3164 2656>,
236 <2857 3056 2828 2952 2699 2796 2447
237 2631 2630 2579 2244 3343 3287 3137
238 3164 2656>,
239 <2439 2577 2552 2667 2461 2577 2394
240 2536 2132 2307 2191 2903 2838 2912
241 2501 2095>,
242 <2439 2577 2552 2667 2461 2577 2394
243 2536 2132 2307 2191 2903 2838 2912
244 2501 2095>;
245
246 qcom,cpr-open-loop-voltage-fuse-adjustment =
David Collins33b588a2017-08-22 15:28:03 -0700[diff] [blame]247 < 8000 16000 16000 12000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]248
249 qcom,cpr-closed-loop-voltage-fuse-adjustment =
David Collins33b588a2017-08-22 15:28:03 -0700[diff] [blame]250 < 6000 14000 16000 12000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]251
252 qcom,allow-voltage-interpolation;
253 qcom,allow-quotient-interpolation;
254 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
255
256 qcom,cpr-aging-max-voltage-adjustment = <15000>;
David Collinsfc666ff2017-08-31 10:46:18 -0700[diff] [blame]257 qcom,cpr-aging-ref-corner = <14 15>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]258 qcom,cpr-aging-ro-scaling-factor = <1620>;
259 qcom,allow-aging-voltage-adjustment =
260 /* Speed bin 0 */
261 <0 1 1 1 1 1 1 1>,
262 /* Speed bin 1 */
263 <0 1 1 1 1 1 1 1>;
264 qcom,allow-aging-open-loop-voltage-adjustment =
265 <1>;
266 };
267 };
268 };
269
270 apc1_cpr: cprh-ctrl@17db0000 {
271 compatible = "qcom,cprh-sdm845-v2-kbss-regulator";
272 reg = <0x17db0000 0x4000>,
273 <0x00784000 0x1000>,
274 <0x17830000 0x1000>;
275 reg-names = "cpr_ctrl", "fuse_base", "saw";
276 clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
277 clock-names = "core_clk";
278 qcom,cpr-ctrl-name = "apc1";
279 qcom,cpr-controller-id = <1>;
280
281 qcom,cpr-sensor-time = <1000>;
282 qcom,cpr-loop-time = <5000000>;
283 qcom,cpr-idle-cycles = <15>;
284 qcom,cpr-up-down-delay-time = <3000>;
285 qcom,cpr-step-quot-init-min = <9>;
286 qcom,cpr-step-quot-init-max = <14>;
287 qcom,cpr-count-mode = <0>; /* All at once */
288 qcom,cpr-count-repeat = <20>;
289 qcom,cpr-down-error-step-limit = <1>;
290 qcom,cpr-up-error-step-limit = <1>;
291 qcom,cpr-corner-switch-delay-time = <1042>;
292 qcom,cpr-voltage-settling-time = <1760>;
293 qcom,cpr-reset-step-quot-loop-en;
294
295 qcom,apm-threshold-voltage = <800000>;
296 qcom,apm-crossover-voltage = <880000>;
297 qcom,mem-acc-threshold-voltage = <852000>;
298 qcom,mem-acc-crossover-voltage = <852000>;
299
300 qcom,voltage-step = <4000>;
301 qcom,voltage-base = <352000>;
302 qcom,cpr-saw-use-unit-mV;
303
304 qcom,saw-avs-ctrl = <0x101C031>;
305 qcom,saw-avs-limit = <0x4700470>;
306
307 qcom,cpr-enable;
308 qcom,cpr-hw-closed-loop;
309
310 qcom,cpr-panic-reg-addr-list =
311 <0x17db3a84 0x17830c18>;
312 qcom,cpr-panic-reg-name-list =
313 "APSS_GOLD_CPRH_STATUS_0", "GOLD_SAW4_PMIC_STS";
314
315 qcom,cpr-aging-ref-voltage = <1136000>;
316 vdd-supply = <&pm8998_s12>;
317
318 thread@0 {
319 qcom,cpr-thread-id = <0>;
320 qcom,cpr-consecutive-up = <0>;
321 qcom,cpr-consecutive-down = <0>;
322 qcom,cpr-up-threshold = <2>;
323 qcom,cpr-down-threshold = <2>;
324
325 apc1_perfcl_vreg: regulator {
326 regulator-name = "apc1_perfcl_corner";
327 regulator-min-microvolt = <1>;
328 regulator-max-microvolt = <33>;
329
330 qcom,cpr-fuse-corners = <5>;
331 qcom,cpr-fuse-combos = <16>;
332 qcom,cpr-speed-bins = <2>;
333 qcom,cpr-speed-bin-corners = <28 31>;
334 qcom,cpr-corners =
335 /* Speed bin 0 */
336 <28 28 28 28 28 28 28 28>,
337 /* Speed bin 1 */
338 <31 31 31 31 31 31 31 31>;
339
340 qcom,cpr-corner-fmax-map =
341 /* Speed bin 0 */
342 <7 14 22 27 28>,
343 /* Speed bin 1 */
344 <7 14 22 27 31>;
345
346 qcom,cpr-voltage-ceiling =
347 /* Speed bin 0 */
348 <828000 828000 828000 828000 828000
349 828000 828000 828000 828000 828000
350 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]351 828000 828000 828000 932000 932000
352 932000 932000 1104000 1104000 1104000
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]353 1104000 1136000 1136000>,
354 /* Speed bin 1 */
355 <828000 828000 828000 828000 828000
356 828000 828000 828000 828000 828000
357 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]358 828000 828000 828000 932000 932000
359 932000 932000 1104000 1104000 1104000
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]360 1104000 1136000 1136000 1136000 1136000
361 1136000>;
362
363 qcom,cpr-voltage-floor =
364 /* Speed bin 0 */
365 <568000 568000 568000 568000 568000
366 568000 568000 568000 568000 568000
367 568000 568000 568000 568000 568000
368 568000 568000 568000 568000 568000
369 568000 568000 568000 568000 568000
370 568000 568000 568000>,
371 /* Speed bin 1 */
372 <568000 568000 568000 568000 568000
373 568000 568000 568000 568000 568000
374 568000 568000 568000 568000 568000
375 568000 568000 568000 568000 568000
376 568000 568000 568000 568000 568000
377 568000 568000 568000 568000 568000
378 568000>;
379
380 qcom,cpr-floor-to-ceiling-max-range =
381 /* Speed bin 0 */
382 <32000 32000 32000 32000 32000
383 32000 32000 32000 32000 32000
384 32000 32000 32000 32000 32000
385 32000 32000 32000 32000 32000
386 32000 32000 32000 32000 32000
387 32000 32000 32000>,
388 /* Speed bin 1 */
389 <32000 32000 32000 32000 32000
390 32000 32000 32000 32000 32000
391 32000 32000 32000 32000 32000
392 32000 32000 32000 32000 32000
393 32000 32000 32000 32000 32000
394 32000 32000 40000 40000 40000
395 40000>;
396
397 qcom,corner-frequencies =
398 /* Speed bin 0 */
399 <300000000 403200000 480000000
400 576000000 652800000 748800000
401 825600000 902400000 979200000
402 1056000000 1132800000 1209600000
403 1286400000 1363200000 1459200000
404 1536000000 1612800000 1689600000
405 1766400000 1843200000 1920000000
406 1996800000 2092800000 2169600000
407 2246400000 2323200000 2400000000
408 2400000000>,
409 /* Speed bin 1 */
410 <300000000 403200000 480000000
411 576000000 652800000 748800000
412 825600000 902400000 979200000
413 1056000000 1132800000 1209600000
414 1286400000 1363200000 1459200000
415 1536000000 1612800000 1689600000
416 1766400000 1843200000 1920000000
417 1996800000 2092800000 2169600000
418 2246400000 2323200000 2400000000
David Collinsae2591d2017-08-22 14:15:14 -0700[diff] [blame]419 2476800000 2553600000 2649600000
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]420 2707200000>;
421
422 qcom,cpr-ro-scaling-factor =
423 <2857 3056 2828 2952 2699 2796 2447
424 2631 2630 2579 2244 3343 3287 3137
425 3164 2656>,
426 <2857 3056 2828 2952 2699 2796 2447
427 2631 2630 2579 2244 3343 3287 3137
428 3164 2656>,
429 <2086 2208 2273 2408 2203 2327 2213
430 2340 1755 2039 2049 2474 2437 2618
431 2003 1675>,
432 <2086 2208 2273 2408 2203 2327 2213
433 2340 1755 2039 2049 2474 2437 2618
434 2003 1675>,
435 <2086 2208 2273 2408 2203 2327 2213
436 2340 1755 2039 2049 2474 2437 2618
437 2003 1675>;
438
439 qcom,cpr-open-loop-voltage-fuse-adjustment =
David Collins33b588a2017-08-22 15:28:03 -0700[diff] [blame]440 /* Speed bin 0 */
441 < 8000 8000 8000 0 0>,
442 /* Speed bin 1 */
443 < 8000 8000 8000 0 16000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]444
445 qcom,cpr-closed-loop-voltage-fuse-adjustment =
David Collins33b588a2017-08-22 15:28:03 -0700[diff] [blame]446 /* Speed bin 0 */
447 < 6000 6000 8000 0 0>,
448 /* Speed bin 1 */
449 < 6000 6000 8000 0 16000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]450
451 qcom,allow-voltage-interpolation;
452 qcom,allow-quotient-interpolation;
453 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
454
455 qcom,cpr-aging-max-voltage-adjustment = <15000>;
456 qcom,cpr-aging-ref-corner = <27 31>;
457 qcom,cpr-aging-ro-scaling-factor = <1700>;
458 qcom,allow-aging-voltage-adjustment =
459 /* Speed bin 0 */
460 <0 1 1 1 1 1 1 1>,
461 /* Speed bin 1 */
462 <0 1 1 1 1 1 1 1>;
463 qcom,allow-aging-open-loop-voltage-adjustment =
464 <1>;
465 };
466 };
467 };
Vicky Wallaceddf4fad2017-08-03 20:15:55 -0700[diff] [blame]468
469 gpu_gx_domain_addr: syscon@0x5091508 {
470 compatible = "syscon";
471 reg = <0x5091508 0x4>;
472 };
473
474 gpu_gx_sw_reset: syscon@0x5091008 {
475 compatible = "syscon";
476 reg = <0x5091008 0x4>;
477 };
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]478};
479
David Collinsfc666ff2017-08-31 10:46:18 -0700[diff] [blame]480/* VDD_APC0 */
481&pm8998_s13 {
482 regulator-min-microvolt = <568000>;
483 regulator-max-microvolt = <1000000>;
484};
485
486/* VDD_APC1 */
487&pm8998_s12 {
488 regulator-min-microvolt = <568000>;
489 regulator-max-microvolt = <1136000>;
490};
491
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]492&clock_cpucc {
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]493 compatible = "qcom,clk-cpu-osm-v2";
494
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]495 vdd-l3-supply = <&apc0_l3_vreg>;
496 vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]497 vdd-perfcl-supply = <&apc1_perfcl_vreg>;
498
499 qcom,l3-speedbin0-v0 =
500 < 300000000 0x000c000f 0x00002020 0x1 1 >,
501 < 403200000 0x500c0115 0x00002020 0x1 2 >,
502 < 480000000 0x50140219 0x00002020 0x1 3 >,
503 < 576000000 0x5014031e 0x00002020 0x1 4 >,
504 < 652800000 0x401c0422 0x00002020 0x1 5 >,
505 < 748800000 0x401c0527 0x00002020 0x1 6 >,
506 < 844800000 0x4024062c 0x00002323 0x2 7 >,
507 < 940800000 0x40240731 0x00002727 0x2 8 >,
508 < 1036800000 0x40240836 0x00002b2b 0x2 9 >,
509 < 1132800000 0x402c093b 0x00002f2f 0x2 10 >,
510 < 1209600000 0x402c0a3f 0x00003232 0x2 11 >,
511 < 1305600000 0x40340b44 0x00003636 0x2 12 >,
512 < 1401600000 0x40340c49 0x00003a3a 0x2 13 >,
513 < 1478400000 0x403c0d4d 0x00003e3e 0x2 14 >;
514
Deepak Katragadda288d2b52017-08-11 10:13:59 -0700[diff] [blame]515 qcom,l3-speedbin1-v0 =
516 < 300000000 0x000c000f 0x00002020 0x1 1 >,
517 < 403200000 0x500c0115 0x00002020 0x1 2 >,
518 < 480000000 0x50140219 0x00002020 0x1 3 >,
519 < 576000000 0x5014031e 0x00002020 0x1 4 >,
520 < 652800000 0x401c0422 0x00002020 0x1 5 >,
521 < 748800000 0x401c0527 0x00002020 0x1 6 >,
522 < 844800000 0x4024062c 0x00002323 0x2 7 >,
523 < 940800000 0x40240731 0x00002727 0x2 8 >,
524 < 1036800000 0x40240836 0x00002b2b 0x2 9 >,
525 < 1132800000 0x402c093b 0x00002f2f 0x2 10 >,
526 < 1209600000 0x402c0a3f 0x00003232 0x2 11 >,
527 < 1305600000 0x40340b44 0x00003636 0x2 12 >,
528 < 1401600000 0x40340c49 0x00003a3a 0x2 13 >,
529 < 1497600000 0x403c0d4e 0x00003e3e 0x2 14 >,
530 < 1593600000 0x403c0e53 0x00004242 0x2 15 >;
531
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]532 qcom,pwrcl-speedbin0-v0 =
533 < 300000000 0x000c000f 0x00002020 0x1 1 >,
534 < 403200000 0x500c0115 0x00002020 0x1 2 >,
535 < 480000000 0x50140219 0x00002020 0x1 3 >,
536 < 576000000 0x5014031e 0x00002020 0x1 4 >,
537 < 652800000 0x401c0422 0x00002020 0x1 5 >,
538 < 748800000 0x401c0527 0x00002020 0x1 6 >,
539 < 825600000 0x401c062b 0x00002222 0x1 7 >,
540 < 902400000 0x4024072f 0x00002626 0x1 8 >,
541 < 979200000 0x40240833 0x00002929 0x1 9 >,
542 < 1056000000 0x402c0937 0x00002c2c 0x2 10 >,
543 < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >,
544 < 1228800000 0x402c0b40 0x00003333 0x2 12 >,
545 < 1324800000 0x40340c45 0x00003737 0x2 13 >,
546 < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >,
547 < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >,
548 < 1612800000 0x403c0f54 0x00004343 0x2 16 >,
549 < 1689600000 0x40441058 0x00004646 0x2 17 >,
550 < 1766400000 0x4044115c 0x00004a4a 0x2 18 >;
551
Deepak Katragadda401fcb92017-08-21 16:30:15 -0700[diff] [blame]552 qcom,pwrcl-speedbin1-v0 =
553 < 300000000 0x000c000f 0x00002020 0x1 1 >,
554 < 403200000 0x500c0115 0x00002020 0x1 2 >,
555 < 480000000 0x50140219 0x00002020 0x1 3 >,
556 < 576000000 0x5014031e 0x00002020 0x1 4 >,
557 < 652800000 0x401c0422 0x00002020 0x1 5 >,
558 < 748800000 0x401c0527 0x00002020 0x1 6 >,
559 < 825600000 0x401c062b 0x00002222 0x1 7 >,
560 < 902400000 0x4024072f 0x00002626 0x1 8 >,
561 < 979200000 0x40240833 0x00002929 0x1 9 >,
562 < 1056000000 0x402c0937 0x00002c2c 0x2 10 >,
563 < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >,
564 < 1228800000 0x402c0b40 0x00003333 0x2 12 >,
565 < 1324800000 0x40340c45 0x00003737 0x2 13 >,
566 < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >,
567 < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >,
568 < 1612800000 0x403c0f54 0x00004343 0x2 16 >,
569 < 1689600000 0x40441058 0x00004646 0x2 17 >,
570 < 1766400000 0x4044115c 0x00004a4a 0x2 18 >;
571
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]572 qcom,perfcl-speedbin0-v0 =
573 < 300000000 0x000c000f 0x00002020 0x1 1 >,
574 < 403200000 0x500c0115 0x00002020 0x1 2 >,
575 < 480000000 0x50140219 0x00002020 0x1 3 >,
576 < 576000000 0x5014031e 0x00002020 0x1 4 >,
577 < 652800000 0x401c0422 0x00002020 0x1 5 >,
578 < 748800000 0x401c0527 0x00002020 0x1 6 >,
579 < 825600000 0x401c062b 0x00002222 0x1 7 >,
580 < 902400000 0x4024072f 0x00002626 0x1 8 >,
581 < 979200000 0x40240833 0x00002929 0x1 9 >,
582 < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
583 < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
584 < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
585 < 1286400000 0x40340c43 0x00003636 0x2 13 >,
586 < 1363200000 0x40340d47 0x00003939 0x2 14 >,
587 < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
588 < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
589 < 1612800000 0x403c1054 0x00004343 0x2 17 >,
590 < 1689600000 0x40441158 0x00004646 0x2 18 >,
591 < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
592 < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
593 < 1920000000 0x404c1464 0x00005050 0x2 21 >,
594 < 1996800000 0x404c1568 0x00005353 0x2 22 >,
595 < 2092800000 0x4054166d 0x00005757 0x2 23 >,
596 < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
597 < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
598 < 2323200000 0x40541979 0x00006161 0x2 26 >,
599 < 2400000000 0x40541a7d 0x00006464 0x2 27 >;
600
601 qcom,perfcl-speedbin1-v0 =
602 < 300000000 0x000c000f 0x00002020 0x1 1 >,
603 < 403200000 0x500c0115 0x00002020 0x1 2 >,
604 < 480000000 0x50140219 0x00002020 0x1 3 >,
605 < 576000000 0x5014031e 0x00002020 0x1 4 >,
606 < 652800000 0x401c0422 0x00002020 0x1 5 >,
607 < 748800000 0x401c0527 0x00002020 0x1 6 >,
608 < 825600000 0x401c062b 0x00002222 0x1 7 >,
609 < 902400000 0x4024072f 0x00002626 0x1 8 >,
610 < 979200000 0x40240833 0x00002929 0x1 9 >,
611 < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
612 < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
613 < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
614 < 1286400000 0x40340c43 0x00003636 0x2 13 >,
615 < 1363200000 0x40340d47 0x00003939 0x2 14 >,
616 < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
617 < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
618 < 1612800000 0x403c1054 0x00004343 0x2 17 >,
619 < 1689600000 0x40441158 0x00004646 0x2 18 >,
620 < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
621 < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
622 < 1920000000 0x404c1464 0x00005050 0x2 21 >,
623 < 1996800000 0x404c1568 0x00005353 0x2 22 >,
624 < 2092800000 0x4054166d 0x00005757 0x2 23 >,
625 < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
626 < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
627 < 2323200000 0x40541979 0x00006161 0x2 26 >,
628 < 2400000000 0x40541a7d 0x00006464 0x2 27 >,
629 < 2476800000 0x40541b81 0x00006767 0x2 28 >,
630 < 2553600000 0x40541c85 0x00006a6a 0x2 29 >,
Deepak Katragadda1a183252017-08-21 12:44:34 -0700[diff] [blame]631 < 2649600000 0x40541d8a 0x00006e6e 0x2 30 >,
632 < 2745600000 0x40511e8f 0x00007272 0x2 31 >;
Deepak Katragadda30d72dd2017-08-01 13:56:00 -0700[diff] [blame]633
634 qcom,l3-memacc-level-vc-bin0 = <8 13>;
Deepak Katragadda288d2b52017-08-11 10:13:59 -0700[diff] [blame]635 qcom,l3-memacc-level-vc-bin1 = <8 13>;
Deepak Katragadda30d72dd2017-08-01 13:56:00 -0700[diff] [blame]636
637 qcom,pwrcl-memacc-level-vc-bin0 = <12 16>;
Deepak Katragadda401fcb92017-08-21 16:30:15 -0700[diff] [blame]638 qcom,pwrcl-memacc-level-vc-bin1 = <12 16>;
Deepak Katragadda30d72dd2017-08-01 13:56:00 -0700[diff] [blame]639
640 qcom,perfcl-memacc-level-vc-bin0 = <14 22>;
641 qcom,perfcl-memacc-level-vc-bin1 = <14 22>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]642};
643
Tony Truong80258d62017-08-16 11:41:33 -0700[diff] [blame]644&pcie1 {
645 qcom,phy-sequence = <0x1804 0x03 0x0
646 0x00dc 0x27 0x0
647 0x0014 0x01 0x0
648 0x0020 0x31 0x0
649 0x0024 0x01 0x0
650 0x0028 0xde 0x0
651 0x002c 0x07 0x0
652 0x0034 0x4c 0x0
653 0x0038 0x06 0x0
654 0x0054 0x18 0x0
655 0x0058 0xb0 0x0
656 0x006c 0x8c 0x0
657 0x0070 0x20 0x0
658 0x0078 0x14 0x0
659 0x007c 0x34 0x0
660 0x00b4 0x06 0x0
661 0x00b8 0x06 0x0
662 0x00c0 0x16 0x0
663 0x00c4 0x16 0x0
664 0x00cc 0x36 0x0
665 0x00d0 0x36 0x0
666 0x00f0 0x05 0x0
667 0x00f8 0x42 0x0
668 0x0100 0x82 0x0
669 0x0108 0x68 0x0
670 0x011c 0x55 0x0
671 0x0120 0x55 0x0
672 0x0124 0x03 0x0
673 0x0128 0xab 0x0
674 0x012c 0xaa 0x0
675 0x0130 0x02 0x0
676 0x0150 0x3f 0x0
677 0x0158 0x3f 0x0
678 0x0178 0x10 0x0
679 0x01cc 0x04 0x0
680 0x01d0 0x30 0x0
681 0x01e0 0x04 0x0
682 0x01e8 0x73 0x0
683 0x01f0 0x1c 0x0
684 0x01fc 0x15 0x0
685 0x021c 0x04 0x0
686 0x0224 0x01 0x0
687 0x0228 0x22 0x0
688 0x022c 0x00 0x0
689 0x0098 0x05 0x0
690 0x080c 0x00 0x0
691 0x0818 0x0d 0x0
692 0x0860 0x01 0x0
693 0x0864 0x3a 0x0
694 0x087c 0x2f 0x0
695 0x08c0 0x09 0x0
696 0x08c4 0x09 0x0
697 0x08c8 0x1a 0x0
698 0x08d0 0x01 0x0
699 0x08d4 0x07 0x0
700 0x08d8 0x31 0x0
701 0x08dc 0x31 0x0
702 0x08e0 0x03 0x0
703 0x08fc 0x02 0x0
704 0x0900 0x01 0x0
705 0x0908 0x12 0x0
706 0x0914 0x25 0x0
707 0x0918 0x00 0x0
708 0x091c 0x05 0x0
709 0x0920 0x01 0x0
710 0x0924 0x26 0x0
711 0x0928 0x12 0x0
712 0x0930 0x04 0x0
713 0x0934 0x04 0x0
714 0x0938 0x09 0x0
715 0x0954 0x15 0x0
716 0x0960 0x32 0x0
717 0x0968 0x7f 0x0
718 0x096c 0x07 0x0
719 0x0978 0x04 0x0
720 0x0980 0x70 0x0
721 0x0984 0x8b 0x0
722 0x0988 0x08 0x0
723 0x098c 0x09 0x0
724 0x0990 0x03 0x0
725 0x0994 0x04 0x0
726 0x0998 0x02 0x0
727 0x099c 0x0c 0x0
728 0x09a4 0x02 0x0
729 0x09c0 0x5c 0x0
730 0x09c4 0x3e 0x0
731 0x09c8 0x3f 0x0
732 0x0a30 0x01 0x0
733 0x0a34 0xa0 0x0
734 0x0a38 0x08 0x0
735 0x0aa4 0x01 0x0
736 0x0aac 0xc3 0x0
737 0x0ab0 0x00 0x0
738 0x0ab8 0x8c 0x0
739 0x0ac0 0x7f 0x0
740 0x0ac4 0x2a 0x0
741 0x0810 0x0c 0x0
742 0x0814 0x00 0x0
743 0x0acc 0x04 0x0
744 0x093c 0x20 0x0
745 0x100c 0x00 0x0
746 0x1018 0x0d 0x0
747 0x1060 0x01 0x0
748 0x1064 0x3a 0x0
749 0x107c 0x2f 0x0
750 0x10c0 0x09 0x0
751 0x10c4 0x09 0x0
752 0x10c8 0x1a 0x0
753 0x10d0 0x01 0x0
754 0x10d4 0x07 0x0
755 0x10d8 0x31 0x0
756 0x10dc 0x31 0x0
757 0x10e0 0x03 0x0
758 0x10fc 0x02 0x0
759 0x1100 0x01 0x0
760 0x1108 0x12 0x0
761 0x1114 0x25 0x0
762 0x1118 0x00 0x0
763 0x111c 0x05 0x0
764 0x1120 0x01 0x0
765 0x1124 0x26 0x0
766 0x1128 0x12 0x0
767 0x1130 0x04 0x0
768 0x1134 0x04 0x0
769 0x1138 0x09 0x0
770 0x1154 0x15 0x0
771 0x1160 0x32 0x0
772 0x1168 0x7f 0x0
773 0x116c 0x07 0x0
774 0x1178 0x04 0x0
775 0x1180 0x70 0x0
776 0x1184 0x8b 0x0
777 0x1188 0x08 0x0
778 0x118c 0x09 0x0
779 0x1190 0x03 0x0
780 0x1194 0x04 0x0
781 0x1198 0x02 0x0
782 0x119c 0x0c 0x0
783 0x11a4 0x02 0x0
784 0x11c0 0x5c 0x0
785 0x11c4 0x3e 0x0
786 0x11c8 0x3f 0x0
787 0x1230 0x01 0x0
788 0x1234 0xa0 0x0
789 0x1238 0x08 0x0
790 0x12a4 0x01 0x0
791 0x12ac 0xc3 0x0
792 0x12b0 0x00 0x0
793 0x12b8 0x8c 0x0
794 0x12c0 0x7f 0x0
795 0x12c4 0x2a 0x0
796 0x1010 0x0c 0x0
797 0x1014 0x0f 0x0
798 0x12cc 0x04 0x0
799 0x113c 0x20 0x0
800 0x195c 0x3f 0x0
801 0x1974 0x50 0x0
802 0x196c 0x9f 0x0
803 0x182c 0x19 0x0
804 0x1840 0x07 0x0
805 0x1854 0x17 0x0
806 0x1868 0x09 0x0
807 0x1800 0x00 0x0
808 0x0aa8 0x01 0x0
809 0x12a8 0x01 0x0
810 0x1808 0x01 0x0>;
811};
812
Jonathan Avila29bc1972017-08-24 16:49:18 -0700[diff] [blame]813&devfreq_l3lat_0 {
814 qcom,core-dev-table =
815 < 300000 300000000 >,
816 < 480000 403200000 >,
817 < 652800 480000000 >,
818 < 748800 576000000 >,
819 < 902400 652800000 >,
820 < 979200 748800000 >,
821 < 1132800 844800000 >,
822 < 1228800 940800000 >,
823 < 1324800 1036800000 >,
824 < 1420800 1132800000 >,
825 < 1516800 1209600000 >,
826 < 1612800 1401600000 >,
827 < 1689600 1497600000 >,
828 < 1766400 1593600000 >;
829};
830
831&devfreq_l3lat_4 {
832 qcom,core-dev-table =
833 < 300000 300000000 >,
834 < 825600 576000000 >,
835 < 1132800 748800000 >,
836 < 1363200 940800000 >,
837 < 1689600 1209600000 >,
838 < 1996800 1401600000 >,
839 < 2400000 1593600000 >;
840};
841
Stephen Boydcbe46a02017-08-02 13:59:31 -0700[diff] [blame]842&bwmon {
843 qcom,count-unit = <0x10000>;
844};
845
Stephen Boyd31aac5f2017-09-01 09:16:06 -0700[diff] [blame^]846&cpubw {
847 qcom,bw-tbl =
848 < MHZ_TO_MBPS(150, 16) >, /* 2288 MB/s */
849 < MHZ_TO_MBPS(300, 16) >, /* 4577 MB/s */
850 < MHZ_TO_MBPS(426, 16) >, /* 6500 MB/s */
851 < MHZ_TO_MBPS(533, 16) >, /* 8132 MB/s */
852 < MHZ_TO_MBPS(600, 16) >, /* 9155 MB/s */
853 < MHZ_TO_MBPS(806, 16) >, /* 12298 MB/s */
854 < MHZ_TO_MBPS(933, 16) >; /* 14236 MB/s */
855};
856
857&devfreq_cpufreq {
858 mincpubw-cpufreq {
859 cpu-to-dev-map-4 =
860 < 1881600 MHZ_TO_MBPS(200, 4) >,
861 < 2400000 MHZ_TO_MBPS(681, 4) >;
862 };
863};
864
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]865&clock_gcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]866 compatible = "qcom,gcc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]867};
868
869&clock_camcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]870 compatible = "qcom,cam_cc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]871};
872
873&clock_dispcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]874 compatible = "qcom,dispcc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]875};
876
Vicky Wallace1762ab32017-07-12 19:00:04 -0700[diff] [blame]877&clock_gpucc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]878 compatible = "qcom,gpucc-sdm845-v2", "syscon";
Vicky Wallace1762ab32017-07-12 19:00:04 -0700[diff] [blame]879};
880
881&clock_gfx {
882 compatible = "qcom,gfxcc-sdm845-v2";
883};
884
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]885&clock_videocc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]886 compatible = "qcom,video_cc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]887};
Praneeth Paladugu55381212017-07-05 15:02:44 -0700[diff] [blame]888
889&msm_vidc {
890 qcom,allowed-clock-rates = <100000000 200000000 330000000
891 404000000 444000000 533000000>;
892};
Reut Zysman861fd6c2017-07-30 15:39:13 +0300[diff] [blame]893
David Collins113cc2772017-06-27 17:26:54 -0700[diff] [blame]894&refgen {
895 status = "ok";
David Collinsd388dd82017-08-15 16:23:21 -0700[diff] [blame]896 regulator-always-on;
David Collins113cc2772017-06-27 17:26:54 -0700[diff] [blame]897};
898
Reut Zysman861fd6c2017-07-30 15:39:13 +0300[diff] [blame]899&spss_utils {
900 qcom,spss-dev-firmware-name = "spss2d"; /* 8 chars max */
901 qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */
902 qcom,spss-prod-firmware-name = "spss2p"; /* 8 chars max */
903};
Narendra Muppalla4efd3442017-07-24 17:36:15 -0700[diff] [blame]904
905&mdss_mdp {
906 clock-max-rate = <0 0 0 0 430000000 19200000 0>;
907};
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]908
909&energy_costs {
910 CPU_COST_0: core-cost0 {
911 busy-cost-data = <
912 300000 11
913 403200 17
914 480000 21
915 576000 26
916 652800 31
917 748800 37
918 825600 42
919 902400 47
920 979200 52
921 1056000 57
922 1132800 62
923 1228800 69
924 1324800 78
925 1420800 89
926 1516800 103
927 1612800 122
928 1689600 140
929 1766400 159
930 >;
931 idle-cost-data = <
932 22 18 14 12
933 >;
934 };
935 CPU_COST_1: core-cost1 {
936 busy-cost-data = <
937 300000 130
938 403200 480
939 480000 730
940 576000 1030
941 652800 1260
942 748800 1530
943 825600 1740
944 902400 1930
945 979200 2110
946 1056000 2290
947 1132800 2460
948 1209600 2630
949 1286400 2800
950 1363200 2980
951 1459200 3240
952 1536000 3490
953 1612800 3780
954 1689600 4120
955 1766400 4530
956 1843200 5020
957 1920000 5590
958 1996800 6230
959 2092800 7120
960 2169600 7870
961 2246400 8620
962 2323200 9330
963 2400000 10030
964 2476800 10830
965 2553600 12080
966 2630400 14580
967 2707200 19960
968 >;
969 idle-cost-data = <
970 100 80 60 40
971 >;
972 };
973 CLUSTER_COST_0: cluster-cost0 {
974 busy-cost-data = <
975 300000 3
976 403200 4
977 480000 4
978 576000 4
979 652800 5
980 748800 5
981 825600 6
982 902400 7
983 979200 7
984 1056000 8
985 1132800 9
986 1228800 9
987 1324800 10
988 1420800 11
989 1516800 12
990 1612800 13
991 1689600 15
992 1766400 17
993 >;
994 idle-cost-data = <
995 4 3 2 1
996 >;
997 };
998 CLUSTER_COST_1: cluster-cost1 {
999 busy-cost-data = <
1000 300000 24
1001 403200 24
1002 480000 25
1003 576000 25
1004 652800 26
1005 748800 27
1006 825600 28
1007 902400 29
1008 979200 30
1009 1056000 32
1010 1132800 34
1011 1209600 37
1012 1286400 40
1013 1363200 45
1014 1459200 50
1015 1536000 57
1016 1612800 64
1017 1689600 74
1018 1766400 84
1019 1843200 96
1020 1920000 106
1021 1996800 113
1022 2092800 120
1023 2169600 125
1024 2246400 127
1025 2323200 130
1026 2400000 135
1027 2476800 140
1028 2553600 145
1029 2630400 150
1030 2707200 155
1031 >;
1032 idle-cost-data = <
1033 4 3 2 1
1034 >;
1035 };
1036};
Vicky Wallaceddf4fad2017-08-03 20:15:55 -0700[diff] [blame]1037
1038&gpu_gx_gdsc {
1039 domain-addr = <&gpu_gx_domain_addr>;
1040 sw-reset = <&gpu_gx_sw_reset>;
1041 qcom,reset-aon-logic;
1042};
Lokesh Batra835f0162017-08-01 11:55:53 -0700[diff] [blame]1043
1044/* GPU overrides */
1045&msm_gpu {
1046 /* Updated chip ID */
1047 qcom,chipid = <0x06030001>;
1048 qcom,initial-pwrlevel = <5>;
1049
1050 qcom,gpu-pwrlevels {
1051 #address-cells = <1>;
1052 #size-cells = <0>;
1053
1054 compatible = "qcom,gpu-pwrlevels";
1055
1056 qcom,gpu-pwrlevel@0 {
1057 reg = <0>;
1058 qcom,gpu-freq = <675000000>;
1059 qcom,bus-freq = <12>;
1060 qcom,bus-min = <10>;
1061 qcom,bus-max = <12>;
1062 };
1063
1064 qcom,gpu-pwrlevel@1 {
1065 reg = <1>;
1066 qcom,gpu-freq = <596000000>;
1067 qcom,bus-freq = <10>;
1068 qcom,bus-min = <9>;
1069 qcom,bus-max = <11>;
1070 };
1071
1072 qcom,gpu-pwrlevel@2 {
1073 reg = <2>;
1074 qcom,gpu-freq = <520000000>;
1075 qcom,bus-freq = <9>;
1076 qcom,bus-min = <8>;
1077 qcom,bus-max = <10>;
1078 };
1079
1080 qcom,gpu-pwrlevel@3 {
1081 reg = <3>;
1082 qcom,gpu-freq = <414000000>;
1083 qcom,bus-freq = <8>;
1084 qcom,bus-min = <7>;
1085 qcom,bus-max = <9>;
1086 };
1087
1088 qcom,gpu-pwrlevel@4 {
1089 reg = <4>;
1090 qcom,gpu-freq = <342000000>;
1091 qcom,bus-freq = <6>;
1092 qcom,bus-min = <5>;
1093 qcom,bus-max = <7>;
1094 };
1095
1096 qcom,gpu-pwrlevel@5 {
1097 reg = <5>;
1098 qcom,gpu-freq = <257000000>;
1099 qcom,bus-freq = <4>;
1100 qcom,bus-min = <3>;
1101 qcom,bus-max = <5>;
1102 };
1103
1104 qcom,gpu-pwrlevel@6 {
1105 reg = <6>;
1106 qcom,gpu-freq = <0>;
1107 qcom,bus-freq = <0>;
1108 qcom,bus-min = <0>;
1109 qcom,bus-max = <0>;
1110 };
1111 };
1112};
1113
1114&gmu {
1115 qcom,gmu-pwrlevels {
1116 #address-cells = <1>;
1117 #size-cells = <0>;
1118
1119 compatible = "qcom,gmu-pwrlevels";
1120
1121 qcom,gmu-pwrlevel@0 {
1122 reg = <0>;
1123 qcom,gmu-freq = <500000000>;
1124 };
1125
1126 qcom,gmu-pwrlevel@1 {
1127 reg = <1>;
1128 qcom,gmu-freq = <200000000>;
1129 };
1130
1131 qcom,gmu-pwrlevel@2 {
1132 reg = <2>;
1133 qcom,gmu-freq = <0>;
1134 };
1135 };
1136};