Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1 | /* |
| 2 | * ALSA SoC McASP Audio Layer for TI DAVINCI processor |
| 3 | * |
| 4 | * Multi-channel Audio Serial Port Driver |
| 5 | * |
| 6 | * Author: Nirmal Pandey <n-pandey@ti.com>, |
| 7 | * Suresh Rajashekara <suresh.r@ti.com> |
| 8 | * Steve Chen <schen@.mvista.com> |
| 9 | * |
| 10 | * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> |
| 11 | * Copyright: (C) 2009 Texas Instruments, India |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License version 2 as |
| 15 | * published by the Free Software Foundation. |
| 16 | */ |
| 17 | |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/device.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 21 | #include <linux/slab.h> |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 22 | #include <linux/delay.h> |
| 23 | #include <linux/io.h> |
Peter Ujfalusi | ae726e9 | 2013-11-14 11:35:35 +0200 | [diff] [blame] | 24 | #include <linux/clk.h> |
Hebbar, Gururaja | 1088434 | 2012-08-08 20:40:32 +0530 | [diff] [blame] | 25 | #include <linux/pm_runtime.h> |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 26 | #include <linux/of.h> |
| 27 | #include <linux/of_platform.h> |
| 28 | #include <linux/of_device.h> |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 29 | |
| 30 | #include <sound/core.h> |
| 31 | #include <sound/pcm.h> |
| 32 | #include <sound/pcm_params.h> |
| 33 | #include <sound/initval.h> |
| 34 | #include <sound/soc.h> |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 35 | #include <sound/dmaengine_pcm.h> |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 36 | |
| 37 | #include "davinci-pcm.h" |
| 38 | #include "davinci-mcasp.h" |
| 39 | |
Peter Ujfalusi | 0bf0e8a | 2014-04-01 15:55:09 +0300 | [diff] [blame] | 40 | #define MCASP_MAX_AFIFO_DEPTH 64 |
| 41 | |
Peter Ujfalusi | 790bb94 | 2014-02-03 14:51:52 +0200 | [diff] [blame] | 42 | struct davinci_mcasp_context { |
| 43 | u32 txfmtctl; |
| 44 | u32 rxfmtctl; |
| 45 | u32 txfmt; |
| 46 | u32 rxfmt; |
| 47 | u32 aclkxctl; |
| 48 | u32 aclkrctl; |
| 49 | u32 pdir; |
| 50 | }; |
| 51 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 52 | struct davinci_mcasp { |
Peter Ujfalusi | 21400a7 | 2013-11-14 11:35:26 +0200 | [diff] [blame] | 53 | struct davinci_pcm_dma_params dma_params[2]; |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 54 | struct snd_dmaengine_dai_dma_data dma_data[2]; |
Peter Ujfalusi | 21400a7 | 2013-11-14 11:35:26 +0200 | [diff] [blame] | 55 | void __iomem *base; |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 56 | u32 fifo_base; |
Peter Ujfalusi | 21400a7 | 2013-11-14 11:35:26 +0200 | [diff] [blame] | 57 | struct device *dev; |
| 58 | |
| 59 | /* McASP specific data */ |
| 60 | int tdm_slots; |
| 61 | u8 op_mode; |
| 62 | u8 num_serializer; |
| 63 | u8 *serial_dir; |
| 64 | u8 version; |
| 65 | u16 bclk_lrclk_ratio; |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 66 | int streams; |
Peter Ujfalusi | 21400a7 | 2013-11-14 11:35:26 +0200 | [diff] [blame] | 67 | |
Jyri Sarha | ab8b14b | 2014-01-27 17:37:52 +0200 | [diff] [blame] | 68 | int sysclk_freq; |
| 69 | bool bclk_master; |
| 70 | |
Peter Ujfalusi | 21400a7 | 2013-11-14 11:35:26 +0200 | [diff] [blame] | 71 | /* McASP FIFO related */ |
| 72 | u8 txnumevt; |
| 73 | u8 rxnumevt; |
| 74 | |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 75 | bool dat_port; |
| 76 | |
Peter Ujfalusi | 21400a7 | 2013-11-14 11:35:26 +0200 | [diff] [blame] | 77 | #ifdef CONFIG_PM_SLEEP |
Peter Ujfalusi | 790bb94 | 2014-02-03 14:51:52 +0200 | [diff] [blame] | 78 | struct davinci_mcasp_context context; |
Peter Ujfalusi | 21400a7 | 2013-11-14 11:35:26 +0200 | [diff] [blame] | 79 | #endif |
| 80 | }; |
| 81 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 82 | static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, |
| 83 | u32 val) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 84 | { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 85 | void __iomem *reg = mcasp->base + offset; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 86 | __raw_writel(__raw_readl(reg) | val, reg); |
| 87 | } |
| 88 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 89 | static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, |
| 90 | u32 val) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 91 | { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 92 | void __iomem *reg = mcasp->base + offset; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 93 | __raw_writel((__raw_readl(reg) & ~(val)), reg); |
| 94 | } |
| 95 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 96 | static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, |
| 97 | u32 val, u32 mask) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 98 | { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 99 | void __iomem *reg = mcasp->base + offset; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 100 | __raw_writel((__raw_readl(reg) & ~mask) | val, reg); |
| 101 | } |
| 102 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 103 | static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, |
| 104 | u32 val) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 105 | { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 106 | __raw_writel(val, mcasp->base + offset); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 107 | } |
| 108 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 109 | static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 110 | { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 111 | return (u32)__raw_readl(mcasp->base + offset); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 112 | } |
| 113 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 114 | static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 115 | { |
| 116 | int i = 0; |
| 117 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 118 | mcasp_set_bits(mcasp, ctl_reg, val); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 119 | |
| 120 | /* programming GBLCTL needs to read back from GBLCTL and verfiy */ |
| 121 | /* loop count is to avoid the lock-up */ |
| 122 | for (i = 0; i < 1000; i++) { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 123 | if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 124 | break; |
| 125 | } |
| 126 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 127 | if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 128 | printk(KERN_ERR "GBLCTL write error\n"); |
| 129 | } |
| 130 | |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 131 | static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) |
| 132 | { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 133 | u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); |
| 134 | u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 135 | |
| 136 | return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; |
| 137 | } |
| 138 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 139 | static void mcasp_start_rx(struct davinci_mcasp *mcasp) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 140 | { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 141 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); |
| 142 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 143 | |
| 144 | /* |
| 145 | * When ASYNC == 0 the transmit and receive sections operate |
| 146 | * synchronously from the transmit clock and frame sync. We need to make |
| 147 | * sure that the TX signlas are enabled when starting reception. |
| 148 | */ |
| 149 | if (mcasp_is_synchronous(mcasp)) { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 150 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
| 151 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 152 | } |
| 153 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 154 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); |
| 155 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 156 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 157 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
| 158 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); |
| 159 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 160 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 161 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
| 162 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 163 | |
| 164 | if (mcasp_is_synchronous(mcasp)) |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 165 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 166 | } |
| 167 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 168 | static void mcasp_start_tx(struct davinci_mcasp *mcasp) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 169 | { |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 170 | u8 offset = 0, i; |
| 171 | u32 cnt; |
| 172 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 173 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
| 174 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); |
| 175 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); |
| 176 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 177 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 178 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); |
| 179 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); |
| 180 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 181 | for (i = 0; i < mcasp->num_serializer; i++) { |
| 182 | if (mcasp->serial_dir[i] == TX_MODE) { |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 183 | offset = i; |
| 184 | break; |
| 185 | } |
| 186 | } |
| 187 | |
| 188 | /* wait for TX ready */ |
| 189 | cnt = 0; |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 190 | while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) & |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 191 | TXSTATE) && (cnt < 100000)) |
| 192 | cnt++; |
| 193 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 194 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 195 | } |
| 196 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 197 | static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 198 | { |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 199 | u32 reg; |
| 200 | |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 201 | mcasp->streams++; |
| 202 | |
Chaithrika U S | 539d3d8 | 2009-09-23 10:12:08 -0400 | [diff] [blame] | 203 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 204 | if (mcasp->txnumevt) { /* enable FIFO */ |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 205 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 206 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
| 207 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); |
Vaibhav Bedia | 0d62427 | 2012-08-08 20:40:31 +0530 | [diff] [blame] | 208 | } |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 209 | mcasp_start_tx(mcasp); |
Chaithrika U S | 539d3d8 | 2009-09-23 10:12:08 -0400 | [diff] [blame] | 210 | } else { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 211 | if (mcasp->rxnumevt) { /* enable FIFO */ |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 212 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 213 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
| 214 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); |
Vaibhav Bedia | 0d62427 | 2012-08-08 20:40:31 +0530 | [diff] [blame] | 215 | } |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 216 | mcasp_start_rx(mcasp); |
Chaithrika U S | 539d3d8 | 2009-09-23 10:12:08 -0400 | [diff] [blame] | 217 | } |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 218 | } |
| 219 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 220 | static void mcasp_stop_rx(struct davinci_mcasp *mcasp) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 221 | { |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 222 | /* |
| 223 | * In synchronous mode stop the TX clocks if no other stream is |
| 224 | * running |
| 225 | */ |
| 226 | if (mcasp_is_synchronous(mcasp) && !mcasp->streams) |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 227 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 228 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 229 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); |
| 230 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 231 | } |
| 232 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 233 | static void mcasp_stop_tx(struct davinci_mcasp *mcasp) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 234 | { |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 235 | u32 val = 0; |
| 236 | |
| 237 | /* |
| 238 | * In synchronous mode keep TX clocks running if the capture stream is |
| 239 | * still running. |
| 240 | */ |
| 241 | if (mcasp_is_synchronous(mcasp) && mcasp->streams) |
| 242 | val = TXHCLKRST | TXCLKRST | TXFSRST; |
| 243 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 244 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); |
| 245 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 246 | } |
| 247 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 248 | static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 249 | { |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 250 | u32 reg; |
| 251 | |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 252 | mcasp->streams--; |
| 253 | |
Chaithrika U S | 539d3d8 | 2009-09-23 10:12:08 -0400 | [diff] [blame] | 254 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 255 | if (mcasp->txnumevt) { /* disable FIFO */ |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 256 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 257 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
Hebbar, Gururaja | e5ec69d | 2012-09-03 13:40:40 +0530 | [diff] [blame] | 258 | } |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 259 | mcasp_stop_tx(mcasp); |
Chaithrika U S | 539d3d8 | 2009-09-23 10:12:08 -0400 | [diff] [blame] | 260 | } else { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 261 | if (mcasp->rxnumevt) { /* disable FIFO */ |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 262 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 263 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
Hebbar, Gururaja | e5ec69d | 2012-09-03 13:40:40 +0530 | [diff] [blame] | 264 | } |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 265 | mcasp_stop_rx(mcasp); |
Chaithrika U S | 539d3d8 | 2009-09-23 10:12:08 -0400 | [diff] [blame] | 266 | } |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 267 | } |
| 268 | |
| 269 | static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
| 270 | unsigned int fmt) |
| 271 | { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 272 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
Peter Ujfalusi | 1d17a04 | 2014-01-30 15:21:30 +0200 | [diff] [blame] | 273 | int ret = 0; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 274 | |
Peter Ujfalusi | 1d17a04 | 2014-01-30 15:21:30 +0200 | [diff] [blame] | 275 | pm_runtime_get_sync(mcasp->dev); |
Daniel Mack | 5296cf2 | 2012-10-04 15:08:42 +0200 | [diff] [blame] | 276 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 277 | case SND_SOC_DAIFMT_DSP_B: |
| 278 | case SND_SOC_DAIFMT_AC97: |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 279 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
| 280 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); |
Daniel Mack | 5296cf2 | 2012-10-04 15:08:42 +0200 | [diff] [blame] | 281 | break; |
| 282 | default: |
| 283 | /* configure a full-word SYNC pulse (LRCLK) */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 284 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
| 285 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); |
Daniel Mack | 5296cf2 | 2012-10-04 15:08:42 +0200 | [diff] [blame] | 286 | |
| 287 | /* make 1st data bit occur one ACLK cycle after the frame sync */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 288 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(1)); |
| 289 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(1)); |
Daniel Mack | 5296cf2 | 2012-10-04 15:08:42 +0200 | [diff] [blame] | 290 | break; |
| 291 | } |
| 292 | |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 293 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 294 | case SND_SOC_DAIFMT_CBS_CFS: |
| 295 | /* codec is clock and frame slave */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 296 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
| 297 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 298 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 299 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
| 300 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 301 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 302 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
| 303 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); |
Jyri Sarha | ab8b14b | 2014-01-27 17:37:52 +0200 | [diff] [blame] | 304 | mcasp->bclk_master = 1; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 305 | break; |
Chaithrika U S | 517ee6c | 2009-08-11 16:59:12 -0400 | [diff] [blame] | 306 | case SND_SOC_DAIFMT_CBM_CFS: |
| 307 | /* codec is clock master and frame slave */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 308 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
| 309 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); |
Chaithrika U S | 517ee6c | 2009-08-11 16:59:12 -0400 | [diff] [blame] | 310 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 311 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
| 312 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); |
Chaithrika U S | 517ee6c | 2009-08-11 16:59:12 -0400 | [diff] [blame] | 313 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 314 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
| 315 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); |
Jyri Sarha | ab8b14b | 2014-01-27 17:37:52 +0200 | [diff] [blame] | 316 | mcasp->bclk_master = 0; |
Chaithrika U S | 517ee6c | 2009-08-11 16:59:12 -0400 | [diff] [blame] | 317 | break; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 318 | case SND_SOC_DAIFMT_CBM_CFM: |
| 319 | /* codec is clock and frame master */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 320 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
| 321 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 322 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 323 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
| 324 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 325 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 326 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, |
| 327 | ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); |
Jyri Sarha | ab8b14b | 2014-01-27 17:37:52 +0200 | [diff] [blame] | 328 | mcasp->bclk_master = 0; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 329 | break; |
| 330 | |
| 331 | default: |
Peter Ujfalusi | 1d17a04 | 2014-01-30 15:21:30 +0200 | [diff] [blame] | 332 | ret = -EINVAL; |
| 333 | goto out; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 334 | } |
| 335 | |
| 336 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 337 | case SND_SOC_DAIFMT_IB_NF: |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 338 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
| 339 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 340 | |
Peter Ujfalusi | 74ddd8c | 2014-04-04 14:31:41 +0300 | [diff] [blame] | 341 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 342 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 343 | break; |
| 344 | |
| 345 | case SND_SOC_DAIFMT_NB_IF: |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 346 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
| 347 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 348 | |
Peter Ujfalusi | 74ddd8c | 2014-04-04 14:31:41 +0300 | [diff] [blame] | 349 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 350 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 351 | break; |
| 352 | |
| 353 | case SND_SOC_DAIFMT_IB_IF: |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 354 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
| 355 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 356 | |
Peter Ujfalusi | 74ddd8c | 2014-04-04 14:31:41 +0300 | [diff] [blame] | 357 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 358 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 359 | break; |
| 360 | |
| 361 | case SND_SOC_DAIFMT_NB_NF: |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 362 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
| 363 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 364 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 365 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
| 366 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 367 | break; |
| 368 | |
| 369 | default: |
Peter Ujfalusi | 1d17a04 | 2014-01-30 15:21:30 +0200 | [diff] [blame] | 370 | ret = -EINVAL; |
| 371 | break; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 372 | } |
Peter Ujfalusi | 1d17a04 | 2014-01-30 15:21:30 +0200 | [diff] [blame] | 373 | out: |
| 374 | pm_runtime_put_sync(mcasp->dev); |
| 375 | return ret; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 376 | } |
| 377 | |
Daniel Mack | 4ed8c9b | 2012-10-04 15:08:39 +0200 | [diff] [blame] | 378 | static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) |
| 379 | { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 380 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
Daniel Mack | 4ed8c9b | 2012-10-04 15:08:39 +0200 | [diff] [blame] | 381 | |
| 382 | switch (div_id) { |
| 383 | case 0: /* MCLK divider */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 384 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, |
Daniel Mack | 4ed8c9b | 2012-10-04 15:08:39 +0200 | [diff] [blame] | 385 | AHCLKXDIV(div - 1), AHCLKXDIV_MASK); |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 386 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, |
Daniel Mack | 4ed8c9b | 2012-10-04 15:08:39 +0200 | [diff] [blame] | 387 | AHCLKRDIV(div - 1), AHCLKRDIV_MASK); |
| 388 | break; |
| 389 | |
| 390 | case 1: /* BCLK divider */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 391 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, |
Daniel Mack | 4ed8c9b | 2012-10-04 15:08:39 +0200 | [diff] [blame] | 392 | ACLKXDIV(div - 1), ACLKXDIV_MASK); |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 393 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, |
Daniel Mack | 4ed8c9b | 2012-10-04 15:08:39 +0200 | [diff] [blame] | 394 | ACLKRDIV(div - 1), ACLKRDIV_MASK); |
| 395 | break; |
| 396 | |
Daniel Mack | 1b3bc06 | 2012-12-05 18:20:38 +0100 | [diff] [blame] | 397 | case 2: /* BCLK/LRCLK ratio */ |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 398 | mcasp->bclk_lrclk_ratio = div; |
Daniel Mack | 1b3bc06 | 2012-12-05 18:20:38 +0100 | [diff] [blame] | 399 | break; |
| 400 | |
Daniel Mack | 4ed8c9b | 2012-10-04 15:08:39 +0200 | [diff] [blame] | 401 | default: |
| 402 | return -EINVAL; |
| 403 | } |
| 404 | |
| 405 | return 0; |
| 406 | } |
| 407 | |
Daniel Mack | 5b66aa2 | 2012-10-04 15:08:41 +0200 | [diff] [blame] | 408 | static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
| 409 | unsigned int freq, int dir) |
| 410 | { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 411 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
Daniel Mack | 5b66aa2 | 2012-10-04 15:08:41 +0200 | [diff] [blame] | 412 | |
| 413 | if (dir == SND_SOC_CLOCK_OUT) { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 414 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
| 415 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); |
| 416 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); |
Daniel Mack | 5b66aa2 | 2012-10-04 15:08:41 +0200 | [diff] [blame] | 417 | } else { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 418 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
| 419 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); |
| 420 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); |
Daniel Mack | 5b66aa2 | 2012-10-04 15:08:41 +0200 | [diff] [blame] | 421 | } |
| 422 | |
Jyri Sarha | ab8b14b | 2014-01-27 17:37:52 +0200 | [diff] [blame] | 423 | mcasp->sysclk_freq = freq; |
| 424 | |
Daniel Mack | 5b66aa2 | 2012-10-04 15:08:41 +0200 | [diff] [blame] | 425 | return 0; |
| 426 | } |
| 427 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 428 | static int davinci_config_channel_size(struct davinci_mcasp *mcasp, |
Daniel Mack | ba764b3 | 2012-12-05 18:20:37 +0100 | [diff] [blame] | 429 | int word_length) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 430 | { |
Daniel Mack | ba764b3 | 2012-12-05 18:20:37 +0100 | [diff] [blame] | 431 | u32 fmt; |
Daniel Mack | 7967189 | 2013-05-16 15:25:01 +0200 | [diff] [blame] | 432 | u32 tx_rotate = (word_length / 4) & 0x7; |
| 433 | u32 rx_rotate = (32 - word_length) / 4; |
Daniel Mack | ba764b3 | 2012-12-05 18:20:37 +0100 | [diff] [blame] | 434 | u32 mask = (1ULL << word_length) - 1; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 435 | |
Daniel Mack | 1b3bc06 | 2012-12-05 18:20:38 +0100 | [diff] [blame] | 436 | /* |
| 437 | * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv() |
| 438 | * callback, take it into account here. That allows us to for example |
| 439 | * send 32 bits per channel to the codec, while only 16 of them carry |
| 440 | * audio payload. |
Michal Bachraty | d486fea | 2013-04-19 15:28:44 +0200 | [diff] [blame] | 441 | * The clock ratio is given for a full period of data (for I2S format |
| 442 | * both left and right channels), so it has to be divided by number of |
| 443 | * tdm-slots (for I2S - divided by 2). |
Daniel Mack | 1b3bc06 | 2012-12-05 18:20:38 +0100 | [diff] [blame] | 444 | */ |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 445 | if (mcasp->bclk_lrclk_ratio) |
| 446 | word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots; |
Daniel Mack | 1b3bc06 | 2012-12-05 18:20:38 +0100 | [diff] [blame] | 447 | |
Daniel Mack | ba764b3 | 2012-12-05 18:20:37 +0100 | [diff] [blame] | 448 | /* mapping of the XSSZ bit-field as described in the datasheet */ |
| 449 | fmt = (word_length >> 1) - 1; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 450 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 451 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 452 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), |
| 453 | RXSSZ(0x0F)); |
| 454 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), |
| 455 | TXSSZ(0x0F)); |
| 456 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), |
| 457 | TXROT(7)); |
| 458 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), |
| 459 | RXROT(7)); |
| 460 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); |
Yegor Yefremov | f5023af | 2013-04-04 16:13:20 +0200 | [diff] [blame] | 461 | } |
| 462 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 463 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); |
Chaithrika U S | 0c31cf3 | 2009-09-15 18:13:29 -0400 | [diff] [blame] | 464 | |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 465 | return 0; |
| 466 | } |
| 467 | |
Peter Ujfalusi | 662ffae | 2014-01-30 15:15:22 +0200 | [diff] [blame] | 468 | static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, |
Peter Ujfalusi | dd093a0 | 2014-04-01 15:55:11 +0300 | [diff] [blame] | 469 | int period_words, int channels) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 470 | { |
Peter Ujfalusi | 5f04c60 | 2014-04-01 15:55:10 +0300 | [diff] [blame] | 471 | struct davinci_pcm_dma_params *dma_params = &mcasp->dma_params[stream]; |
| 472 | struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 473 | int i; |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 474 | u8 tx_ser = 0; |
| 475 | u8 rx_ser = 0; |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 476 | u8 slots = mcasp->tdm_slots; |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 477 | u8 max_active_serializers = (channels + slots - 1) / slots; |
Peter Ujfalusi | dd093a0 | 2014-04-01 15:55:11 +0300 | [diff] [blame] | 478 | int active_serializers, numevt, n; |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 479 | u32 reg; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 480 | /* Default configuration */ |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 481 | if (mcasp->version != MCASP_VERSION_4) |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 482 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 483 | |
| 484 | /* All PINS as McASP */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 485 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 486 | |
| 487 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 488 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
| 489 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 490 | } else { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 491 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
| 492 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 493 | } |
| 494 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 495 | for (i = 0; i < mcasp->num_serializer; i++) { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 496 | mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
| 497 | mcasp->serial_dir[i]); |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 498 | if (mcasp->serial_dir[i] == TX_MODE && |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 499 | tx_ser < max_active_serializers) { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 500 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 501 | tx_ser++; |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 502 | } else if (mcasp->serial_dir[i] == RX_MODE && |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 503 | rx_ser < max_active_serializers) { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 504 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 505 | rx_ser++; |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 506 | } else { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 507 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
| 508 | SRMOD_INACTIVE, SRMOD_MASK); |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 509 | } |
| 510 | } |
| 511 | |
Peter Ujfalusi | 0bf0e8a | 2014-04-01 15:55:09 +0300 | [diff] [blame] | 512 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 513 | active_serializers = tx_ser; |
| 514 | numevt = mcasp->txnumevt; |
| 515 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
| 516 | } else { |
| 517 | active_serializers = rx_ser; |
| 518 | numevt = mcasp->rxnumevt; |
| 519 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; |
| 520 | } |
Daniel Mack | ecf327c | 2013-03-08 14:19:38 +0100 | [diff] [blame] | 521 | |
Peter Ujfalusi | 0bf0e8a | 2014-04-01 15:55:09 +0300 | [diff] [blame] | 522 | if (active_serializers < max_active_serializers) { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 523 | dev_warn(mcasp->dev, "stream has more channels (%d) than are " |
Peter Ujfalusi | 0bf0e8a | 2014-04-01 15:55:09 +0300 | [diff] [blame] | 524 | "enabled in mcasp (%d)\n", channels, |
| 525 | active_serializers * slots); |
Daniel Mack | ecf327c | 2013-03-08 14:19:38 +0100 | [diff] [blame] | 526 | return -EINVAL; |
| 527 | } |
| 528 | |
Peter Ujfalusi | 0bf0e8a | 2014-04-01 15:55:09 +0300 | [diff] [blame] | 529 | /* AFIFO is not in use */ |
Peter Ujfalusi | 5f04c60 | 2014-04-01 15:55:10 +0300 | [diff] [blame] | 530 | if (!numevt) { |
| 531 | /* Configure the burst size for platform drivers */ |
Peter Ujfalusi | 3344564 | 2014-04-01 15:55:12 +0300 | [diff] [blame^] | 532 | if (active_serializers > 1) { |
| 533 | /* |
| 534 | * If more than one serializers are in use we have one |
| 535 | * DMA request to provide data for all serializers. |
| 536 | * For example if three serializers are enabled the DMA |
| 537 | * need to transfer three words per DMA request. |
| 538 | */ |
| 539 | dma_params->fifo_level = active_serializers; |
| 540 | dma_data->maxburst = active_serializers; |
| 541 | } else { |
| 542 | dma_params->fifo_level = 0; |
| 543 | dma_data->maxburst = 0; |
| 544 | } |
Peter Ujfalusi | 0bf0e8a | 2014-04-01 15:55:09 +0300 | [diff] [blame] | 545 | return 0; |
Peter Ujfalusi | 5f04c60 | 2014-04-01 15:55:10 +0300 | [diff] [blame] | 546 | } |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 547 | |
Peter Ujfalusi | dd093a0 | 2014-04-01 15:55:11 +0300 | [diff] [blame] | 548 | if (period_words % active_serializers) { |
| 549 | dev_err(mcasp->dev, "Invalid combination of period words and " |
| 550 | "active serializers: %d, %d\n", period_words, |
| 551 | active_serializers); |
| 552 | return -EINVAL; |
| 553 | } |
| 554 | |
| 555 | /* |
| 556 | * Calculate the optimal AFIFO depth for platform side: |
| 557 | * The number of words for numevt need to be in steps of active |
| 558 | * serializers. |
| 559 | */ |
| 560 | n = numevt % active_serializers; |
| 561 | if (n) |
| 562 | numevt += (active_serializers - n); |
| 563 | while (period_words % numevt && numevt > 0) |
| 564 | numevt -= active_serializers; |
| 565 | if (numevt <= 0) |
Peter Ujfalusi | 0bf0e8a | 2014-04-01 15:55:09 +0300 | [diff] [blame] | 566 | numevt = active_serializers; |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 567 | |
Peter Ujfalusi | 0bf0e8a | 2014-04-01 15:55:09 +0300 | [diff] [blame] | 568 | mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); |
| 569 | mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 570 | |
Peter Ujfalusi | 5f04c60 | 2014-04-01 15:55:10 +0300 | [diff] [blame] | 571 | /* Configure the burst size for platform drivers */ |
Peter Ujfalusi | 3344564 | 2014-04-01 15:55:12 +0300 | [diff] [blame^] | 572 | if (numevt == 1) |
| 573 | numevt = 0; |
Peter Ujfalusi | 5f04c60 | 2014-04-01 15:55:10 +0300 | [diff] [blame] | 574 | dma_params->fifo_level = numevt; |
| 575 | dma_data->maxburst = numevt; |
| 576 | |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 577 | return 0; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 578 | } |
| 579 | |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 580 | static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 581 | { |
| 582 | int i, active_slots; |
| 583 | u32 mask = 0; |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 584 | u32 busel = 0; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 585 | |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 586 | if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) { |
| 587 | dev_err(mcasp->dev, "tdm slot %d not supported\n", |
| 588 | mcasp->tdm_slots); |
| 589 | return -EINVAL; |
| 590 | } |
| 591 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 592 | active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 593 | for (i = 0; i < active_slots; i++) |
| 594 | mask |= (1 << i); |
| 595 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 596 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 597 | |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 598 | if (!mcasp->dat_port) |
| 599 | busel = TXSEL; |
| 600 | |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 601 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); |
| 602 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); |
| 603 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, |
| 604 | FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF)); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 605 | |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 606 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); |
| 607 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); |
| 608 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, |
| 609 | FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF)); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 610 | |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 611 | return 0; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 612 | } |
| 613 | |
| 614 | /* S/PDIF */ |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 615 | static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 616 | { |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 617 | /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 |
| 618 | and LSB first */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 619 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 620 | |
| 621 | /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 622 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 623 | |
| 624 | /* Set the TX tdm : for all the slots */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 625 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 626 | |
| 627 | /* Set the TX clock controls : div = 1 and internal */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 628 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 629 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 630 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 631 | |
| 632 | /* Only 44100 and 48000 are valid, both have the same setting */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 633 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 634 | |
| 635 | /* Enable the DIT */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 636 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 637 | |
| 638 | return 0; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 639 | } |
| 640 | |
| 641 | static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, |
| 642 | struct snd_pcm_hw_params *params, |
| 643 | struct snd_soc_dai *cpu_dai) |
| 644 | { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 645 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 646 | struct davinci_pcm_dma_params *dma_params = |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 647 | &mcasp->dma_params[substream->stream]; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 648 | int word_length; |
Peter Ujfalusi | a7e46bd | 2014-02-03 14:51:50 +0200 | [diff] [blame] | 649 | int channels = params_channels(params); |
Peter Ujfalusi | dd093a0 | 2014-04-01 15:55:11 +0300 | [diff] [blame] | 650 | int period_size = params_period_size(params); |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 651 | int ret; |
Jyri Sarha | ab8b14b | 2014-01-27 17:37:52 +0200 | [diff] [blame] | 652 | |
| 653 | /* If mcasp is BCLK master we need to set BCLK divider */ |
| 654 | if (mcasp->bclk_master) { |
| 655 | unsigned int bclk_freq = snd_soc_params_to_bclk(params); |
| 656 | if (mcasp->sysclk_freq % bclk_freq != 0) { |
Peter Ujfalusi | f5b02b4 | 2014-04-01 15:55:08 +0300 | [diff] [blame] | 657 | dev_err(mcasp->dev, "Can't produce required BCLK\n"); |
Jyri Sarha | ab8b14b | 2014-01-27 17:37:52 +0200 | [diff] [blame] | 658 | return -EINVAL; |
| 659 | } |
| 660 | davinci_mcasp_set_clkdiv( |
| 661 | cpu_dai, 1, mcasp->sysclk_freq / bclk_freq); |
| 662 | } |
| 663 | |
Peter Ujfalusi | dd093a0 | 2014-04-01 15:55:11 +0300 | [diff] [blame] | 664 | ret = mcasp_common_hw_param(mcasp, substream->stream, |
| 665 | period_size * channels, channels); |
Peter Ujfalusi | 0f7d9a6 | 2014-01-30 15:15:24 +0200 | [diff] [blame] | 666 | if (ret) |
| 667 | return ret; |
| 668 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 669 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 670 | ret = mcasp_dit_hw_param(mcasp); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 671 | else |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 672 | ret = mcasp_i2s_hw_param(mcasp, substream->stream); |
| 673 | |
| 674 | if (ret) |
| 675 | return ret; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 676 | |
| 677 | switch (params_format(params)) { |
Ben Gardiner | 0a9d138 | 2011-08-26 12:02:44 -0400 | [diff] [blame] | 678 | case SNDRV_PCM_FORMAT_U8: |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 679 | case SNDRV_PCM_FORMAT_S8: |
| 680 | dma_params->data_type = 1; |
Daniel Mack | ba764b3 | 2012-12-05 18:20:37 +0100 | [diff] [blame] | 681 | word_length = 8; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 682 | break; |
| 683 | |
Ben Gardiner | 0a9d138 | 2011-08-26 12:02:44 -0400 | [diff] [blame] | 684 | case SNDRV_PCM_FORMAT_U16_LE: |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 685 | case SNDRV_PCM_FORMAT_S16_LE: |
| 686 | dma_params->data_type = 2; |
Daniel Mack | ba764b3 | 2012-12-05 18:20:37 +0100 | [diff] [blame] | 687 | word_length = 16; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 688 | break; |
| 689 | |
Daniel Mack | 21eb24d | 2012-10-09 09:35:16 +0200 | [diff] [blame] | 690 | case SNDRV_PCM_FORMAT_U24_3LE: |
| 691 | case SNDRV_PCM_FORMAT_S24_3LE: |
Daniel Mack | 21eb24d | 2012-10-09 09:35:16 +0200 | [diff] [blame] | 692 | dma_params->data_type = 3; |
Daniel Mack | ba764b3 | 2012-12-05 18:20:37 +0100 | [diff] [blame] | 693 | word_length = 24; |
Daniel Mack | 21eb24d | 2012-10-09 09:35:16 +0200 | [diff] [blame] | 694 | break; |
| 695 | |
Daniel Mack | 6b7fa01 | 2012-10-09 11:56:40 +0200 | [diff] [blame] | 696 | case SNDRV_PCM_FORMAT_U24_LE: |
| 697 | case SNDRV_PCM_FORMAT_S24_LE: |
Ben Gardiner | 0a9d138 | 2011-08-26 12:02:44 -0400 | [diff] [blame] | 698 | case SNDRV_PCM_FORMAT_U32_LE: |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 699 | case SNDRV_PCM_FORMAT_S32_LE: |
| 700 | dma_params->data_type = 4; |
Daniel Mack | ba764b3 | 2012-12-05 18:20:37 +0100 | [diff] [blame] | 701 | word_length = 32; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 702 | break; |
| 703 | |
| 704 | default: |
| 705 | printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); |
| 706 | return -EINVAL; |
| 707 | } |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 708 | |
Peter Ujfalusi | 5f04c60 | 2014-04-01 15:55:10 +0300 | [diff] [blame] | 709 | if (mcasp->version == MCASP_VERSION_2 && !dma_params->fifo_level) |
Chaithrika U S | 4fa9c1a | 2009-09-30 17:32:27 -0400 | [diff] [blame] | 710 | dma_params->acnt = 4; |
| 711 | else |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 712 | dma_params->acnt = dma_params->data_type; |
| 713 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 714 | davinci_config_channel_size(mcasp, word_length); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 715 | |
| 716 | return 0; |
| 717 | } |
| 718 | |
| 719 | static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, |
| 720 | int cmd, struct snd_soc_dai *cpu_dai) |
| 721 | { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 722 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 723 | int ret = 0; |
| 724 | |
| 725 | switch (cmd) { |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 726 | case SNDRV_PCM_TRIGGER_RESUME: |
Chaithrika U S | e473b84 | 2010-01-20 17:06:33 +0530 | [diff] [blame] | 727 | case SNDRV_PCM_TRIGGER_START: |
| 728 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 729 | davinci_mcasp_start(mcasp, substream->stream); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 730 | break; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 731 | case SNDRV_PCM_TRIGGER_SUSPEND: |
Chaithrika U S | a47979b | 2009-12-03 18:56:56 +0530 | [diff] [blame] | 732 | case SNDRV_PCM_TRIGGER_STOP: |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 733 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 734 | davinci_mcasp_stop(mcasp, substream->stream); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 735 | break; |
| 736 | |
| 737 | default: |
| 738 | ret = -EINVAL; |
| 739 | } |
| 740 | |
| 741 | return ret; |
| 742 | } |
| 743 | |
Lars-Peter Clausen | 85e7652 | 2011-11-23 11:40:40 +0100 | [diff] [blame] | 744 | static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 745 | .trigger = davinci_mcasp_trigger, |
| 746 | .hw_params = davinci_mcasp_hw_params, |
| 747 | .set_fmt = davinci_mcasp_set_dai_fmt, |
Daniel Mack | 4ed8c9b | 2012-10-04 15:08:39 +0200 | [diff] [blame] | 748 | .set_clkdiv = davinci_mcasp_set_clkdiv, |
Daniel Mack | 5b66aa2 | 2012-10-04 15:08:41 +0200 | [diff] [blame] | 749 | .set_sysclk = davinci_mcasp_set_sysclk, |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 750 | }; |
| 751 | |
Peter Ujfalusi | d5902f6 | 2014-04-01 15:55:07 +0300 | [diff] [blame] | 752 | static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) |
| 753 | { |
| 754 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
| 755 | |
| 756 | if (mcasp->version == MCASP_VERSION_4) { |
| 757 | /* Using dmaengine PCM */ |
| 758 | dai->playback_dma_data = |
| 759 | &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
| 760 | dai->capture_dma_data = |
| 761 | &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; |
| 762 | } else { |
| 763 | /* Using davinci-pcm */ |
| 764 | dai->playback_dma_data = mcasp->dma_params; |
| 765 | dai->capture_dma_data = mcasp->dma_params; |
| 766 | } |
| 767 | |
| 768 | return 0; |
| 769 | } |
| 770 | |
Peter Ujfalusi | 135014a | 2014-01-30 15:21:32 +0200 | [diff] [blame] | 771 | #ifdef CONFIG_PM_SLEEP |
| 772 | static int davinci_mcasp_suspend(struct snd_soc_dai *dai) |
| 773 | { |
| 774 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
Peter Ujfalusi | 790bb94 | 2014-02-03 14:51:52 +0200 | [diff] [blame] | 775 | struct davinci_mcasp_context *context = &mcasp->context; |
Peter Ujfalusi | 135014a | 2014-01-30 15:21:32 +0200 | [diff] [blame] | 776 | |
Peter Ujfalusi | 790bb94 | 2014-02-03 14:51:52 +0200 | [diff] [blame] | 777 | context->txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG); |
| 778 | context->rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); |
| 779 | context->txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG); |
| 780 | context->rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG); |
| 781 | context->aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); |
| 782 | context->aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG); |
| 783 | context->pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); |
Peter Ujfalusi | 135014a | 2014-01-30 15:21:32 +0200 | [diff] [blame] | 784 | |
| 785 | return 0; |
| 786 | } |
| 787 | |
| 788 | static int davinci_mcasp_resume(struct snd_soc_dai *dai) |
| 789 | { |
| 790 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
Peter Ujfalusi | 790bb94 | 2014-02-03 14:51:52 +0200 | [diff] [blame] | 791 | struct davinci_mcasp_context *context = &mcasp->context; |
Peter Ujfalusi | 135014a | 2014-01-30 15:21:32 +0200 | [diff] [blame] | 792 | |
Peter Ujfalusi | 790bb94 | 2014-02-03 14:51:52 +0200 | [diff] [blame] | 793 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, context->txfmtctl); |
| 794 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, context->rxfmtctl); |
| 795 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, context->txfmt); |
| 796 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, context->rxfmt); |
| 797 | mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, context->aclkxctl); |
| 798 | mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, context->aclkrctl); |
| 799 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, context->pdir); |
Peter Ujfalusi | 135014a | 2014-01-30 15:21:32 +0200 | [diff] [blame] | 800 | |
| 801 | return 0; |
| 802 | } |
| 803 | #else |
| 804 | #define davinci_mcasp_suspend NULL |
| 805 | #define davinci_mcasp_resume NULL |
| 806 | #endif |
| 807 | |
Peter Ujfalusi | ed29cd5 | 2013-11-14 11:35:22 +0200 | [diff] [blame] | 808 | #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 |
| 809 | |
Ben Gardiner | 0a9d138 | 2011-08-26 12:02:44 -0400 | [diff] [blame] | 810 | #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ |
| 811 | SNDRV_PCM_FMTBIT_U8 | \ |
| 812 | SNDRV_PCM_FMTBIT_S16_LE | \ |
| 813 | SNDRV_PCM_FMTBIT_U16_LE | \ |
Daniel Mack | 21eb24d | 2012-10-09 09:35:16 +0200 | [diff] [blame] | 814 | SNDRV_PCM_FMTBIT_S24_LE | \ |
| 815 | SNDRV_PCM_FMTBIT_U24_LE | \ |
| 816 | SNDRV_PCM_FMTBIT_S24_3LE | \ |
| 817 | SNDRV_PCM_FMTBIT_U24_3LE | \ |
Ben Gardiner | 0a9d138 | 2011-08-26 12:02:44 -0400 | [diff] [blame] | 818 | SNDRV_PCM_FMTBIT_S32_LE | \ |
| 819 | SNDRV_PCM_FMTBIT_U32_LE) |
| 820 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 821 | static struct snd_soc_dai_driver davinci_mcasp_dai[] = { |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 822 | { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 823 | .name = "davinci-mcasp.0", |
Peter Ujfalusi | d5902f6 | 2014-04-01 15:55:07 +0300 | [diff] [blame] | 824 | .probe = davinci_mcasp_dai_probe, |
Peter Ujfalusi | 135014a | 2014-01-30 15:21:32 +0200 | [diff] [blame] | 825 | .suspend = davinci_mcasp_suspend, |
| 826 | .resume = davinci_mcasp_resume, |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 827 | .playback = { |
| 828 | .channels_min = 2, |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 829 | .channels_max = 32 * 16, |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 830 | .rates = DAVINCI_MCASP_RATES, |
Ben Gardiner | 0a9d138 | 2011-08-26 12:02:44 -0400 | [diff] [blame] | 831 | .formats = DAVINCI_MCASP_PCM_FMTS, |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 832 | }, |
| 833 | .capture = { |
| 834 | .channels_min = 2, |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 835 | .channels_max = 32 * 16, |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 836 | .rates = DAVINCI_MCASP_RATES, |
Ben Gardiner | 0a9d138 | 2011-08-26 12:02:44 -0400 | [diff] [blame] | 837 | .formats = DAVINCI_MCASP_PCM_FMTS, |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 838 | }, |
| 839 | .ops = &davinci_mcasp_dai_ops, |
| 840 | |
| 841 | }, |
| 842 | { |
Peter Ujfalusi | 58e48d9 | 2013-11-14 11:35:24 +0200 | [diff] [blame] | 843 | .name = "davinci-mcasp.1", |
Peter Ujfalusi | d5902f6 | 2014-04-01 15:55:07 +0300 | [diff] [blame] | 844 | .probe = davinci_mcasp_dai_probe, |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 845 | .playback = { |
| 846 | .channels_min = 1, |
| 847 | .channels_max = 384, |
| 848 | .rates = DAVINCI_MCASP_RATES, |
Ben Gardiner | 0a9d138 | 2011-08-26 12:02:44 -0400 | [diff] [blame] | 849 | .formats = DAVINCI_MCASP_PCM_FMTS, |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 850 | }, |
| 851 | .ops = &davinci_mcasp_dai_ops, |
| 852 | }, |
| 853 | |
| 854 | }; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 855 | |
Kuninori Morimoto | eeef0ed | 2013-03-21 03:31:19 -0700 | [diff] [blame] | 856 | static const struct snd_soc_component_driver davinci_mcasp_component = { |
| 857 | .name = "davinci-mcasp", |
| 858 | }; |
| 859 | |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 860 | /* Some HW specific values and defaults. The rest is filled in from DT. */ |
Peter Ujfalusi | d1debaf | 2014-02-03 14:51:51 +0200 | [diff] [blame] | 861 | static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 862 | .tx_dma_offset = 0x400, |
| 863 | .rx_dma_offset = 0x400, |
| 864 | .asp_chan_q = EVENTQ_0, |
| 865 | .version = MCASP_VERSION_1, |
| 866 | }; |
| 867 | |
Peter Ujfalusi | d1debaf | 2014-02-03 14:51:51 +0200 | [diff] [blame] | 868 | static struct davinci_mcasp_pdata da830_mcasp_pdata = { |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 869 | .tx_dma_offset = 0x2000, |
| 870 | .rx_dma_offset = 0x2000, |
| 871 | .asp_chan_q = EVENTQ_0, |
| 872 | .version = MCASP_VERSION_2, |
| 873 | }; |
| 874 | |
Peter Ujfalusi | d1debaf | 2014-02-03 14:51:51 +0200 | [diff] [blame] | 875 | static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 876 | .tx_dma_offset = 0, |
| 877 | .rx_dma_offset = 0, |
| 878 | .asp_chan_q = EVENTQ_0, |
| 879 | .version = MCASP_VERSION_3, |
| 880 | }; |
| 881 | |
Peter Ujfalusi | d1debaf | 2014-02-03 14:51:51 +0200 | [diff] [blame] | 882 | static struct davinci_mcasp_pdata dra7_mcasp_pdata = { |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 883 | .tx_dma_offset = 0x200, |
| 884 | .rx_dma_offset = 0x284, |
| 885 | .asp_chan_q = EVENTQ_0, |
| 886 | .version = MCASP_VERSION_4, |
| 887 | }; |
| 888 | |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 889 | static const struct of_device_id mcasp_dt_ids[] = { |
| 890 | { |
| 891 | .compatible = "ti,dm646x-mcasp-audio", |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 892 | .data = &dm646x_mcasp_pdata, |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 893 | }, |
| 894 | { |
| 895 | .compatible = "ti,da830-mcasp-audio", |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 896 | .data = &da830_mcasp_pdata, |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 897 | }, |
Hebbar, Gururaja | e5ec69d | 2012-09-03 13:40:40 +0530 | [diff] [blame] | 898 | { |
Jyri Sarha | 3af9e03 | 2013-10-18 18:37:44 +0300 | [diff] [blame] | 899 | .compatible = "ti,am33xx-mcasp-audio", |
Peter Ujfalusi | b14899d | 2013-11-14 11:35:37 +0200 | [diff] [blame] | 900 | .data = &am33xx_mcasp_pdata, |
Hebbar, Gururaja | e5ec69d | 2012-09-03 13:40:40 +0530 | [diff] [blame] | 901 | }, |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 902 | { |
| 903 | .compatible = "ti,dra7-mcasp-audio", |
| 904 | .data = &dra7_mcasp_pdata, |
| 905 | }, |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 906 | { /* sentinel */ } |
| 907 | }; |
| 908 | MODULE_DEVICE_TABLE(of, mcasp_dt_ids); |
| 909 | |
Peter Ujfalusi | ae726e9 | 2013-11-14 11:35:35 +0200 | [diff] [blame] | 910 | static int mcasp_reparent_fck(struct platform_device *pdev) |
| 911 | { |
| 912 | struct device_node *node = pdev->dev.of_node; |
| 913 | struct clk *gfclk, *parent_clk; |
| 914 | const char *parent_name; |
| 915 | int ret; |
| 916 | |
| 917 | if (!node) |
| 918 | return 0; |
| 919 | |
| 920 | parent_name = of_get_property(node, "fck_parent", NULL); |
| 921 | if (!parent_name) |
| 922 | return 0; |
| 923 | |
| 924 | gfclk = clk_get(&pdev->dev, "fck"); |
| 925 | if (IS_ERR(gfclk)) { |
| 926 | dev_err(&pdev->dev, "failed to get fck\n"); |
| 927 | return PTR_ERR(gfclk); |
| 928 | } |
| 929 | |
| 930 | parent_clk = clk_get(NULL, parent_name); |
| 931 | if (IS_ERR(parent_clk)) { |
| 932 | dev_err(&pdev->dev, "failed to get parent clock\n"); |
| 933 | ret = PTR_ERR(parent_clk); |
| 934 | goto err1; |
| 935 | } |
| 936 | |
| 937 | ret = clk_set_parent(gfclk, parent_clk); |
| 938 | if (ret) { |
| 939 | dev_err(&pdev->dev, "failed to reparent fck\n"); |
| 940 | goto err2; |
| 941 | } |
| 942 | |
| 943 | err2: |
| 944 | clk_put(parent_clk); |
| 945 | err1: |
| 946 | clk_put(gfclk); |
| 947 | return ret; |
| 948 | } |
| 949 | |
Peter Ujfalusi | d1debaf | 2014-02-03 14:51:51 +0200 | [diff] [blame] | 950 | static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 951 | struct platform_device *pdev) |
| 952 | { |
| 953 | struct device_node *np = pdev->dev.of_node; |
Peter Ujfalusi | d1debaf | 2014-02-03 14:51:51 +0200 | [diff] [blame] | 954 | struct davinci_mcasp_pdata *pdata = NULL; |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 955 | const struct of_device_id *match = |
Sachin Kamat | ea421eb | 2013-05-22 16:53:37 +0530 | [diff] [blame] | 956 | of_match_device(mcasp_dt_ids, &pdev->dev); |
Jyri Sarha | 4023fe6 | 2013-10-18 18:37:43 +0300 | [diff] [blame] | 957 | struct of_phandle_args dma_spec; |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 958 | |
| 959 | const u32 *of_serial_dir32; |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 960 | u32 val; |
| 961 | int i, ret = 0; |
| 962 | |
| 963 | if (pdev->dev.platform_data) { |
| 964 | pdata = pdev->dev.platform_data; |
| 965 | return pdata; |
| 966 | } else if (match) { |
Peter Ujfalusi | d1debaf | 2014-02-03 14:51:51 +0200 | [diff] [blame] | 967 | pdata = (struct davinci_mcasp_pdata*) match->data; |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 968 | } else { |
| 969 | /* control shouldn't reach here. something is wrong */ |
| 970 | ret = -EINVAL; |
| 971 | goto nodata; |
| 972 | } |
| 973 | |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 974 | ret = of_property_read_u32(np, "op-mode", &val); |
| 975 | if (ret >= 0) |
| 976 | pdata->op_mode = val; |
| 977 | |
| 978 | ret = of_property_read_u32(np, "tdm-slots", &val); |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 979 | if (ret >= 0) { |
| 980 | if (val < 2 || val > 32) { |
| 981 | dev_err(&pdev->dev, |
| 982 | "tdm-slots must be in rage [2-32]\n"); |
| 983 | ret = -EINVAL; |
| 984 | goto nodata; |
| 985 | } |
| 986 | |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 987 | pdata->tdm_slots = val; |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 988 | } |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 989 | |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 990 | of_serial_dir32 = of_get_property(np, "serial-dir", &val); |
| 991 | val /= sizeof(u32); |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 992 | if (of_serial_dir32) { |
Peter Ujfalusi | 1427e66 | 2013-10-18 18:37:46 +0300 | [diff] [blame] | 993 | u8 *of_serial_dir = devm_kzalloc(&pdev->dev, |
| 994 | (sizeof(*of_serial_dir) * val), |
| 995 | GFP_KERNEL); |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 996 | if (!of_serial_dir) { |
| 997 | ret = -ENOMEM; |
| 998 | goto nodata; |
| 999 | } |
| 1000 | |
Peter Ujfalusi | 1427e66 | 2013-10-18 18:37:46 +0300 | [diff] [blame] | 1001 | for (i = 0; i < val; i++) |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 1002 | of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); |
| 1003 | |
Peter Ujfalusi | 1427e66 | 2013-10-18 18:37:46 +0300 | [diff] [blame] | 1004 | pdata->num_serializer = val; |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 1005 | pdata->serial_dir = of_serial_dir; |
| 1006 | } |
| 1007 | |
Jyri Sarha | 4023fe6 | 2013-10-18 18:37:43 +0300 | [diff] [blame] | 1008 | ret = of_property_match_string(np, "dma-names", "tx"); |
| 1009 | if (ret < 0) |
| 1010 | goto nodata; |
| 1011 | |
| 1012 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, |
| 1013 | &dma_spec); |
| 1014 | if (ret < 0) |
| 1015 | goto nodata; |
| 1016 | |
| 1017 | pdata->tx_dma_channel = dma_spec.args[0]; |
| 1018 | |
| 1019 | ret = of_property_match_string(np, "dma-names", "rx"); |
| 1020 | if (ret < 0) |
| 1021 | goto nodata; |
| 1022 | |
| 1023 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, |
| 1024 | &dma_spec); |
| 1025 | if (ret < 0) |
| 1026 | goto nodata; |
| 1027 | |
| 1028 | pdata->rx_dma_channel = dma_spec.args[0]; |
| 1029 | |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 1030 | ret = of_property_read_u32(np, "tx-num-evt", &val); |
| 1031 | if (ret >= 0) |
| 1032 | pdata->txnumevt = val; |
| 1033 | |
| 1034 | ret = of_property_read_u32(np, "rx-num-evt", &val); |
| 1035 | if (ret >= 0) |
| 1036 | pdata->rxnumevt = val; |
| 1037 | |
| 1038 | ret = of_property_read_u32(np, "sram-size-playback", &val); |
| 1039 | if (ret >= 0) |
| 1040 | pdata->sram_size_playback = val; |
| 1041 | |
| 1042 | ret = of_property_read_u32(np, "sram-size-capture", &val); |
| 1043 | if (ret >= 0) |
| 1044 | pdata->sram_size_capture = val; |
| 1045 | |
| 1046 | return pdata; |
| 1047 | |
| 1048 | nodata: |
| 1049 | if (ret < 0) { |
| 1050 | dev_err(&pdev->dev, "Error populating platform data, err %d\n", |
| 1051 | ret); |
| 1052 | pdata = NULL; |
| 1053 | } |
| 1054 | return pdata; |
| 1055 | } |
| 1056 | |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1057 | static int davinci_mcasp_probe(struct platform_device *pdev) |
| 1058 | { |
Peter Ujfalusi | 64ebdec | 2014-03-07 15:03:55 +0200 | [diff] [blame] | 1059 | struct davinci_pcm_dma_params *dma_params; |
Peter Ujfalusi | 8de131f | 2014-03-14 16:42:46 +0200 | [diff] [blame] | 1060 | struct snd_dmaengine_dai_dma_data *dma_data; |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 1061 | struct resource *mem, *ioarea, *res, *dat; |
Peter Ujfalusi | d1debaf | 2014-02-03 14:51:51 +0200 | [diff] [blame] | 1062 | struct davinci_mcasp_pdata *pdata; |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1063 | struct davinci_mcasp *mcasp; |
Julia Lawall | 96d31e2 | 2011-12-29 17:51:21 +0100 | [diff] [blame] | 1064 | int ret; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1065 | |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 1066 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
| 1067 | dev_err(&pdev->dev, "No platform data supplied\n"); |
| 1068 | return -EINVAL; |
| 1069 | } |
| 1070 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1071 | mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), |
Julia Lawall | 96d31e2 | 2011-12-29 17:51:21 +0100 | [diff] [blame] | 1072 | GFP_KERNEL); |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1073 | if (!mcasp) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1074 | return -ENOMEM; |
| 1075 | |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 1076 | pdata = davinci_mcasp_set_pdata_from_of(pdev); |
| 1077 | if (!pdata) { |
| 1078 | dev_err(&pdev->dev, "no platform data\n"); |
| 1079 | return -EINVAL; |
| 1080 | } |
| 1081 | |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 1082 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1083 | if (!mem) { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1084 | dev_warn(mcasp->dev, |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 1085 | "\"mpu\" mem resource not found, using index 0\n"); |
| 1086 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1087 | if (!mem) { |
| 1088 | dev_err(&pdev->dev, "no mem resource?\n"); |
| 1089 | return -ENODEV; |
| 1090 | } |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1091 | } |
| 1092 | |
Julia Lawall | 96d31e2 | 2011-12-29 17:51:21 +0100 | [diff] [blame] | 1093 | ioarea = devm_request_mem_region(&pdev->dev, mem->start, |
Vaibhav Bedia | d852f446 | 2011-02-09 18:39:52 +0530 | [diff] [blame] | 1094 | resource_size(mem), pdev->name); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1095 | if (!ioarea) { |
| 1096 | dev_err(&pdev->dev, "Audio region already claimed\n"); |
Julia Lawall | 96d31e2 | 2011-12-29 17:51:21 +0100 | [diff] [blame] | 1097 | return -EBUSY; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1098 | } |
| 1099 | |
Hebbar, Gururaja | 1088434 | 2012-08-08 20:40:32 +0530 | [diff] [blame] | 1100 | pm_runtime_enable(&pdev->dev); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1101 | |
Hebbar, Gururaja | 1088434 | 2012-08-08 20:40:32 +0530 | [diff] [blame] | 1102 | ret = pm_runtime_get_sync(&pdev->dev); |
| 1103 | if (IS_ERR_VALUE(ret)) { |
| 1104 | dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n"); |
| 1105 | return ret; |
| 1106 | } |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1107 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1108 | mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
| 1109 | if (!mcasp->base) { |
Vaibhav Bedia | 4f82f02 | 2011-02-09 18:39:54 +0530 | [diff] [blame] | 1110 | dev_err(&pdev->dev, "ioremap failed\n"); |
| 1111 | ret = -ENOMEM; |
| 1112 | goto err_release_clk; |
| 1113 | } |
| 1114 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1115 | mcasp->op_mode = pdata->op_mode; |
| 1116 | mcasp->tdm_slots = pdata->tdm_slots; |
| 1117 | mcasp->num_serializer = pdata->num_serializer; |
| 1118 | mcasp->serial_dir = pdata->serial_dir; |
| 1119 | mcasp->version = pdata->version; |
| 1120 | mcasp->txnumevt = pdata->txnumevt; |
| 1121 | mcasp->rxnumevt = pdata->rxnumevt; |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 1122 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1123 | mcasp->dev = &pdev->dev; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1124 | |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 1125 | dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 1126 | if (dat) |
| 1127 | mcasp->dat_port = true; |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 1128 | |
Peter Ujfalusi | 64ebdec | 2014-03-07 15:03:55 +0200 | [diff] [blame] | 1129 | dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; |
Peter Ujfalusi | 8de131f | 2014-03-14 16:42:46 +0200 | [diff] [blame] | 1130 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
Peter Ujfalusi | 64ebdec | 2014-03-07 15:03:55 +0200 | [diff] [blame] | 1131 | dma_params->asp_chan_q = pdata->asp_chan_q; |
| 1132 | dma_params->ram_chan_q = pdata->ram_chan_q; |
| 1133 | dma_params->sram_pool = pdata->sram_pool; |
| 1134 | dma_params->sram_size = pdata->sram_size_playback; |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 1135 | if (dat) |
Peter Ujfalusi | 64ebdec | 2014-03-07 15:03:55 +0200 | [diff] [blame] | 1136 | dma_params->dma_addr = dat->start; |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 1137 | else |
Peter Ujfalusi | 64ebdec | 2014-03-07 15:03:55 +0200 | [diff] [blame] | 1138 | dma_params->dma_addr = mem->start + pdata->tx_dma_offset; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1139 | |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 1140 | /* Unconditional dmaengine stuff */ |
Peter Ujfalusi | 8de131f | 2014-03-14 16:42:46 +0200 | [diff] [blame] | 1141 | dma_data->addr = dma_params->dma_addr; |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 1142 | |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1143 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
Jyri Sarha | 4023fe6 | 2013-10-18 18:37:43 +0300 | [diff] [blame] | 1144 | if (res) |
Peter Ujfalusi | 64ebdec | 2014-03-07 15:03:55 +0200 | [diff] [blame] | 1145 | dma_params->channel = res->start; |
Jyri Sarha | 4023fe6 | 2013-10-18 18:37:43 +0300 | [diff] [blame] | 1146 | else |
Peter Ujfalusi | 64ebdec | 2014-03-07 15:03:55 +0200 | [diff] [blame] | 1147 | dma_params->channel = pdata->tx_dma_channel; |
Troy Kisky | 92e2a6f | 2009-09-11 14:29:03 -0700 | [diff] [blame] | 1148 | |
Peter Ujfalusi | 8de131f | 2014-03-14 16:42:46 +0200 | [diff] [blame] | 1149 | /* dmaengine filter data for DT and non-DT boot */ |
| 1150 | if (pdev->dev.of_node) |
| 1151 | dma_data->filter_data = "tx"; |
| 1152 | else |
| 1153 | dma_data->filter_data = &dma_params->channel; |
| 1154 | |
Peter Ujfalusi | 64ebdec | 2014-03-07 15:03:55 +0200 | [diff] [blame] | 1155 | dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE]; |
Peter Ujfalusi | 8de131f | 2014-03-14 16:42:46 +0200 | [diff] [blame] | 1156 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; |
Peter Ujfalusi | 64ebdec | 2014-03-07 15:03:55 +0200 | [diff] [blame] | 1157 | dma_params->asp_chan_q = pdata->asp_chan_q; |
| 1158 | dma_params->ram_chan_q = pdata->ram_chan_q; |
| 1159 | dma_params->sram_pool = pdata->sram_pool; |
| 1160 | dma_params->sram_size = pdata->sram_size_capture; |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 1161 | if (dat) |
Peter Ujfalusi | 64ebdec | 2014-03-07 15:03:55 +0200 | [diff] [blame] | 1162 | dma_params->dma_addr = dat->start; |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 1163 | else |
Peter Ujfalusi | 64ebdec | 2014-03-07 15:03:55 +0200 | [diff] [blame] | 1164 | dma_params->dma_addr = mem->start + pdata->rx_dma_offset; |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 1165 | |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 1166 | /* Unconditional dmaengine stuff */ |
Peter Ujfalusi | 8de131f | 2014-03-14 16:42:46 +0200 | [diff] [blame] | 1167 | dma_data->addr = dma_params->dma_addr; |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 1168 | |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 1169 | if (mcasp->version < MCASP_VERSION_3) { |
| 1170 | mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; |
Peter Ujfalusi | 64ebdec | 2014-03-07 15:03:55 +0200 | [diff] [blame] | 1171 | /* dma_params->dma_addr is pointing to the data port address */ |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 1172 | mcasp->dat_port = true; |
| 1173 | } else { |
| 1174 | mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; |
| 1175 | } |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1176 | |
| 1177 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
Jyri Sarha | 4023fe6 | 2013-10-18 18:37:43 +0300 | [diff] [blame] | 1178 | if (res) |
Peter Ujfalusi | 64ebdec | 2014-03-07 15:03:55 +0200 | [diff] [blame] | 1179 | dma_params->channel = res->start; |
Jyri Sarha | 4023fe6 | 2013-10-18 18:37:43 +0300 | [diff] [blame] | 1180 | else |
Peter Ujfalusi | 64ebdec | 2014-03-07 15:03:55 +0200 | [diff] [blame] | 1181 | dma_params->channel = pdata->rx_dma_channel; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1182 | |
Peter Ujfalusi | 8de131f | 2014-03-14 16:42:46 +0200 | [diff] [blame] | 1183 | /* dmaengine filter data for DT and non-DT boot */ |
| 1184 | if (pdev->dev.of_node) |
| 1185 | dma_data->filter_data = "rx"; |
| 1186 | else |
| 1187 | dma_data->filter_data = &dma_params->channel; |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 1188 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1189 | dev_set_drvdata(&pdev->dev, mcasp); |
Peter Ujfalusi | ae726e9 | 2013-11-14 11:35:35 +0200 | [diff] [blame] | 1190 | |
| 1191 | mcasp_reparent_fck(pdev); |
| 1192 | |
Kuninori Morimoto | eeef0ed | 2013-03-21 03:31:19 -0700 | [diff] [blame] | 1193 | ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component, |
| 1194 | &davinci_mcasp_dai[pdata->op_mode], 1); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1195 | |
| 1196 | if (ret != 0) |
Julia Lawall | 96d31e2 | 2011-12-29 17:51:21 +0100 | [diff] [blame] | 1197 | goto err_release_clk; |
Hebbar, Gururaja | f08095a | 2012-08-27 18:56:39 +0530 | [diff] [blame] | 1198 | |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 1199 | if (mcasp->version != MCASP_VERSION_4) { |
| 1200 | ret = davinci_soc_platform_register(&pdev->dev); |
| 1201 | if (ret) { |
| 1202 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); |
| 1203 | goto err_unregister_component; |
| 1204 | } |
Hebbar, Gururaja | f08095a | 2012-08-27 18:56:39 +0530 | [diff] [blame] | 1205 | } |
| 1206 | |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1207 | return 0; |
| 1208 | |
Kuninori Morimoto | eeef0ed | 2013-03-21 03:31:19 -0700 | [diff] [blame] | 1209 | err_unregister_component: |
| 1210 | snd_soc_unregister_component(&pdev->dev); |
Vaibhav Bedia | eef6d7b | 2011-02-09 18:39:53 +0530 | [diff] [blame] | 1211 | err_release_clk: |
Hebbar, Gururaja | 1088434 | 2012-08-08 20:40:32 +0530 | [diff] [blame] | 1212 | pm_runtime_put_sync(&pdev->dev); |
| 1213 | pm_runtime_disable(&pdev->dev); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1214 | return ret; |
| 1215 | } |
| 1216 | |
| 1217 | static int davinci_mcasp_remove(struct platform_device *pdev) |
| 1218 | { |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 1219 | struct davinci_mcasp *mcasp = dev_get_drvdata(&pdev->dev); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1220 | |
Kuninori Morimoto | eeef0ed | 2013-03-21 03:31:19 -0700 | [diff] [blame] | 1221 | snd_soc_unregister_component(&pdev->dev); |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 1222 | if (mcasp->version != MCASP_VERSION_4) |
| 1223 | davinci_soc_platform_unregister(&pdev->dev); |
Hebbar, Gururaja | 1088434 | 2012-08-08 20:40:32 +0530 | [diff] [blame] | 1224 | |
| 1225 | pm_runtime_put_sync(&pdev->dev); |
| 1226 | pm_runtime_disable(&pdev->dev); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1227 | |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1228 | return 0; |
| 1229 | } |
| 1230 | |
| 1231 | static struct platform_driver davinci_mcasp_driver = { |
| 1232 | .probe = davinci_mcasp_probe, |
| 1233 | .remove = davinci_mcasp_remove, |
| 1234 | .driver = { |
| 1235 | .name = "davinci-mcasp", |
| 1236 | .owner = THIS_MODULE, |
Sachin Kamat | ea421eb | 2013-05-22 16:53:37 +0530 | [diff] [blame] | 1237 | .of_match_table = mcasp_dt_ids, |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1238 | }, |
| 1239 | }; |
| 1240 | |
Axel Lin | f9b8a51 | 2011-11-25 10:09:27 +0800 | [diff] [blame] | 1241 | module_platform_driver(davinci_mcasp_driver); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1242 | |
| 1243 | MODULE_AUTHOR("Steve Chen"); |
| 1244 | MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); |
| 1245 | MODULE_LICENSE("GPL"); |