Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 13 | #ifndef _SDE_HW_CTL_H |
| 14 | #define _SDE_HW_CTL_H |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 15 | |
| 16 | #include "sde_hw_mdss.h" |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 17 | #include "sde_hw_util.h" |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 18 | #include "sde_hw_catalog.h" |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 19 | #include "sde_hw_sspp.h" |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 20 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 21 | /** |
| 22 | * sde_ctl_mode_sel: Interface mode selection |
| 23 | * SDE_CTL_MODE_SEL_VID: Video mode interface |
| 24 | * SDE_CTL_MODE_SEL_CMD: Command mode interface |
| 25 | */ |
| 26 | enum sde_ctl_mode_sel { |
| 27 | SDE_CTL_MODE_SEL_VID = 0, |
| 28 | SDE_CTL_MODE_SEL_CMD |
| 29 | }; |
| 30 | |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame^] | 31 | /** |
| 32 | * sde_ctl_rot_op_mode - inline rotation mode |
| 33 | * SDE_CTL_ROT_OP_MODE_OFFLINE: offline rotation |
| 34 | * SDE_CTL_ROT_OP_MODE_RESERVED: reserved |
| 35 | * SDE_CTL_ROT_OP_MODE_INLINE_SYNC: inline rotation synchronous mode |
| 36 | * SDE_CTL_ROT_OP_MODE_INLINE_ASYNC: inline rotation asynchronous mode |
| 37 | */ |
| 38 | enum sde_ctl_rot_op_mode { |
| 39 | SDE_CTL_ROT_OP_MODE_OFFLINE, |
| 40 | SDE_CTL_ROT_OP_MODE_RESERVED, |
| 41 | SDE_CTL_ROT_OP_MODE_INLINE_SYNC, |
| 42 | SDE_CTL_ROT_OP_MODE_INLINE_ASYNC, |
| 43 | }; |
| 44 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 45 | struct sde_hw_ctl; |
| 46 | /** |
| 47 | * struct sde_hw_stage_cfg - blending stage cfg |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 48 | * @stage : SSPP_ID at each stage |
| 49 | * @multirect_index: index of the rectangle of SSPP. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 50 | */ |
| 51 | struct sde_hw_stage_cfg { |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 52 | enum sde_sspp stage[CRTC_DUAL_MIXERS][SDE_STAGE_MAX][PIPES_PER_STAGE]; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 53 | enum sde_sspp_multirect_index multirect_index[CRTC_DUAL_MIXERS] |
| 54 | [SDE_STAGE_MAX][PIPES_PER_STAGE]; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 55 | }; |
| 56 | |
| 57 | /** |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 58 | * struct sde_hw_intf_cfg :Describes how the SDE writes data to output interface |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 59 | * @intf : Interface id |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 60 | * @wb: Writeback id |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 61 | * @mode_3d: 3d mux configuration |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 62 | * @intf_mode_sel: Interface mode, cmd / vid |
| 63 | * @stream_sel: Stream selection for multi-stream interfaces |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 64 | */ |
| 65 | struct sde_hw_intf_cfg { |
| 66 | enum sde_intf intf; |
| 67 | enum sde_wb wb; |
| 68 | enum sde_3d_blend_mode mode_3d; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 69 | enum sde_ctl_mode_sel intf_mode_sel; |
| 70 | int stream_sel; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 71 | }; |
| 72 | |
| 73 | /** |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame^] | 74 | * struct sde_ctl_sbuf_cfg - control for stream buffer configuration |
| 75 | * @rot_op_mode: rotator operation mode |
| 76 | */ |
| 77 | struct sde_ctl_sbuf_cfg { |
| 78 | enum sde_ctl_rot_op_mode rot_op_mode; |
| 79 | }; |
| 80 | |
| 81 | /** |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 82 | * struct sde_hw_ctl_ops - Interface to the wb Hw driver functions |
| 83 | * Assumption is these functions will be called after clocks are enabled |
| 84 | */ |
| 85 | struct sde_hw_ctl_ops { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 86 | /** |
| 87 | * kickoff hw operation for Sw controlled interfaces |
| 88 | * DSI cmd mode and WB interface are SW controlled |
| 89 | * @ctx : ctl path ctx pointer |
| 90 | */ |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 91 | void (*trigger_start)(struct sde_hw_ctl *ctx); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 92 | |
| 93 | /** |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame^] | 94 | * kickoff rotator operation for Sw controlled interfaces |
| 95 | * DSI cmd mode and WB interface are SW controlled |
| 96 | * @ctx : ctl path ctx pointer |
| 97 | */ |
| 98 | void (*trigger_rot_start)(struct sde_hw_ctl *ctx); |
| 99 | |
| 100 | /** |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 101 | * Clear the value of the cached pending_flush_mask |
| 102 | * No effect on hardware |
| 103 | * @ctx : ctl path ctx pointer |
| 104 | */ |
| 105 | void (*clear_pending_flush)(struct sde_hw_ctl *ctx); |
| 106 | |
| 107 | /** |
Clarence Ip | 110d15c | 2016-08-16 14:44:41 -0400 | [diff] [blame] | 108 | * Query the value of the cached pending_flush_mask |
| 109 | * No effect on hardware |
| 110 | * @ctx : ctl path ctx pointer |
| 111 | */ |
| 112 | u32 (*get_pending_flush)(struct sde_hw_ctl *ctx); |
| 113 | |
| 114 | /** |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 115 | * OR in the given flushbits to the cached pending_flush_mask |
| 116 | * No effect on hardware |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 117 | * @ctx : ctl path ctx pointer |
| 118 | * @flushbits : module flushmask |
| 119 | */ |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 120 | void (*update_pending_flush)(struct sde_hw_ctl *ctx, |
| 121 | u32 flushbits); |
| 122 | |
| 123 | /** |
| 124 | * Write the value of the pending_flush_mask to hardware |
| 125 | * @ctx : ctl path ctx pointer |
| 126 | */ |
| 127 | void (*trigger_flush)(struct sde_hw_ctl *ctx); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 128 | |
| 129 | /** |
| 130 | * Setup ctl_path interface config |
| 131 | * @ctx |
| 132 | * @cfg : interface config structure pointer |
| 133 | */ |
| 134 | void (*setup_intf_cfg)(struct sde_hw_ctl *ctx, |
| 135 | struct sde_hw_intf_cfg *cfg); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 136 | |
| 137 | int (*reset)(struct sde_hw_ctl *c); |
| 138 | |
Lloyd Atkinson | 6cc9de3 | 2016-11-17 17:56:13 -0500 | [diff] [blame] | 139 | /* |
| 140 | * wait_reset_status - checks ctl reset status |
| 141 | * @ctx : ctl path ctx pointer |
| 142 | * |
| 143 | * This function checks the ctl reset status bit. |
| 144 | * If the reset bit is set, it keeps polling the status till the hw |
| 145 | * reset is complete. |
| 146 | * Returns: 0 on success or -error if reset incomplete within interval |
| 147 | */ |
| 148 | int (*wait_reset_status)(struct sde_hw_ctl *ctx); |
| 149 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 150 | uint32_t (*get_bitmask_sspp)(struct sde_hw_ctl *ctx, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 151 | enum sde_sspp blk); |
| 152 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 153 | uint32_t (*get_bitmask_mixer)(struct sde_hw_ctl *ctx, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 154 | enum sde_lm blk); |
| 155 | |
| 156 | int (*get_bitmask_dspp)(struct sde_hw_ctl *ctx, |
| 157 | u32 *flushbits, |
| 158 | enum sde_dspp blk); |
| 159 | |
| 160 | int (*get_bitmask_intf)(struct sde_hw_ctl *ctx, |
| 161 | u32 *flushbits, |
| 162 | enum sde_intf blk); |
| 163 | |
| 164 | int (*get_bitmask_cdm)(struct sde_hw_ctl *ctx, |
| 165 | u32 *flushbits, |
| 166 | enum sde_cdm blk); |
| 167 | |
Alan Kwong | 3232ca5 | 2016-07-29 02:27:47 -0400 | [diff] [blame] | 168 | int (*get_bitmask_wb)(struct sde_hw_ctl *ctx, |
| 169 | u32 *flushbits, |
| 170 | enum sde_wb blk); |
| 171 | |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame^] | 172 | int (*get_bitmask_rot)(struct sde_hw_ctl *ctx, |
| 173 | u32 *flushbits, |
| 174 | enum sde_rot blk); |
| 175 | |
Lloyd Atkinson | e5ec30d | 2016-08-23 14:32:32 -0400 | [diff] [blame] | 176 | /** |
| 177 | * Set all blend stages to disabled |
| 178 | * @ctx : ctl path ctx pointer |
| 179 | */ |
| 180 | void (*clear_all_blendstages)(struct sde_hw_ctl *ctx); |
| 181 | |
| 182 | /** |
| 183 | * Configure layer mixer to pipe configuration |
| 184 | * @ctx : ctl path ctx pointer |
| 185 | * @lm : layer mixer enumeration |
| 186 | * @cfg : blend stage configuration |
| 187 | */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 188 | void (*setup_blendstage)(struct sde_hw_ctl *ctx, |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 189 | enum sde_lm lm, struct sde_hw_stage_cfg *cfg, u32 index); |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame^] | 190 | |
| 191 | void (*setup_sbuf_cfg)(struct sde_hw_ctl *ctx, |
| 192 | struct sde_ctl_sbuf_cfg *cfg); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 193 | }; |
| 194 | |
| 195 | /** |
| 196 | * struct sde_hw_ctl : CTL PATH driver object |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 197 | * @hw: block register map object |
| 198 | * @idx: control path index |
| 199 | * @ctl_hw_caps: control path capabilities |
| 200 | * @mixer_count: number of mixers |
| 201 | * @mixer_hw_caps: mixer hardware capabilities |
| 202 | * @pending_flush_mask: storage for pending ctl_flush managed via ops |
| 203 | * @ops: operation list |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 204 | */ |
| 205 | struct sde_hw_ctl { |
| 206 | /* base */ |
| 207 | struct sde_hw_blk_reg_map hw; |
| 208 | |
| 209 | /* ctl path */ |
| 210 | int idx; |
| 211 | const struct sde_ctl_cfg *caps; |
| 212 | int mixer_count; |
| 213 | const struct sde_lm_cfg *mixer_hw_caps; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 214 | u32 pending_flush_mask; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 215 | |
| 216 | /* ops */ |
| 217 | struct sde_hw_ctl_ops ops; |
| 218 | }; |
| 219 | |
| 220 | /** |
| 221 | * sde_hw_ctl_init(): Initializes the ctl_path hw driver object. |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 222 | * should be called before accessing every ctl path registers. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 223 | * @idx: ctl_path index for which driver object is required |
| 224 | * @addr: mapped register io address of MDP |
| 225 | * @m : pointer to mdss catalog data |
| 226 | */ |
| 227 | struct sde_hw_ctl *sde_hw_ctl_init(enum sde_ctl idx, |
| 228 | void __iomem *addr, |
| 229 | struct sde_mdss_cfg *m); |
| 230 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 231 | /** |
| 232 | * sde_hw_ctl_destroy(): Destroys ctl driver context |
| 233 | * should be called to free the context |
| 234 | */ |
| 235 | void sde_hw_ctl_destroy(struct sde_hw_ctl *ctx); |
| 236 | |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 237 | #endif /*_SDE_HW_CTL_H */ |