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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
Ayaz Abdulla87046e52006-12-19 23:33:32 -05006 * and Andrew de Quincey.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
Manfred Spraul18360982005-12-24 14:19:24 +010012 * Copyright (C) 2003,4,5 Manfred Spraul
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
Ayaz Abdullaf1405d322009-01-09 11:03:54 +000016 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
Linus Torvalds1da177e2005-04-16 15:20:36 -070017 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 * Known bugs:
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
41 */
Joe Perches294a5542010-11-29 07:41:56 +000042
43#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
Ayaz Abdulla3e1a3ce2009-03-05 08:02:38 +000045#define FORCEDETH_VERSION "0.64"
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#define DRV_NAME "forcedeth"
47
48#include <linux/module.h>
49#include <linux/types.h>
50#include <linux/pci.h>
51#include <linux/interrupt.h>
52#include <linux/netdevice.h>
53#include <linux/etherdevice.h>
54#include <linux/delay.h>
Alexey Dobriyand43c36d2009-10-07 17:09:06 +040055#include <linux/sched.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070056#include <linux/spinlock.h>
57#include <linux/ethtool.h>
58#include <linux/timer.h>
59#include <linux/skbuff.h>
60#include <linux/mii.h>
61#include <linux/random.h>
62#include <linux/init.h>
Manfred Spraul22c6d142005-04-19 21:17:09 +020063#include <linux/if_vlan.h>
Matthias Gehre910638a2006-03-28 01:56:48 -080064#include <linux/dma-mapping.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090065#include <linux/slab.h>
Szymon Janc5504e132010-11-27 08:39:45 +000066#include <linux/uaccess.h>
67#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070068
69#include <asm/irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070070#include <asm/system.h>
71
Stephen Hemmingerbea33482007-10-03 16:41:36 -070072#define TX_WORK_PER_LOOP 64
73#define RX_WORK_PER_LOOP 64
Linus Torvalds1da177e2005-04-16 15:20:36 -070074
75/*
76 * Hardware access:
77 */
78
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +000079#define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
80#define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
81#define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
82#define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
83#define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
84#define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
85#define DEV_HAS_MSI 0x0000040 /* device supports MSI */
86#define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
87#define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
88#define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
Mike Ditto7b5e0782010-07-25 21:54:28 -070089#define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
90#define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
91#define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
92#define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +000093#define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
94#define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
95#define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
96#define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
97#define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
98#define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
99#define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
100#define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
101#define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
102#define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
103#define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
104#define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
105#define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106
107enum {
108 NvRegIrqStatus = 0x000,
109#define NVREG_IRQSTAT_MIIEVENT 0x040
Ayaz Abdulladaa91a92009-02-07 00:25:00 -0800110#define NVREG_IRQSTAT_MASK 0x83ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111 NvRegIrqMask = 0x004,
112#define NVREG_IRQ_RX_ERROR 0x0001
113#define NVREG_IRQ_RX 0x0002
114#define NVREG_IRQ_RX_NOBUF 0x0004
115#define NVREG_IRQ_TX_ERR 0x0008
Manfred Spraulc2dba062005-07-31 18:29:47 +0200116#define NVREG_IRQ_TX_OK 0x0010
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117#define NVREG_IRQ_TIMER 0x0020
118#define NVREG_IRQ_LINK 0x0040
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500119#define NVREG_IRQ_RX_FORCED 0x0080
120#define NVREG_IRQ_TX_FORCED 0x0100
Ayaz Abdulladaa91a92009-02-07 00:25:00 -0800121#define NVREG_IRQ_RECOVER_ERROR 0x8200
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500122#define NVREG_IRQMASK_THROUGHPUT 0x00df
Ayaz Abdulla096a4582007-05-21 20:23:11 -0400123#define NVREG_IRQMASK_CPU 0x0060
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500124#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
125#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500126#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200127
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128 NvRegUnknownSetupReg6 = 0x008,
129#define NVREG_UNKSETUP6_VAL 3
130
131/*
132 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
133 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
134 */
135 NvRegPollingInterval = 0x00c,
Ayaz Abdulla6cef67a2009-03-05 08:02:30 +0000136#define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500137#define NVREG_POLL_DEFAULT_CPU 13
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500138 NvRegMSIMap0 = 0x020,
139 NvRegMSIMap1 = 0x024,
140 NvRegMSIIrqMask = 0x030,
141#define NVREG_MSI_VECTOR_0_ENABLED 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142 NvRegMisc1 = 0x080,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400143#define NVREG_MISC1_PAUSE_TX 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144#define NVREG_MISC1_HD 0x02
145#define NVREG_MISC1_FORCE 0x3b0f3c
146
Ayaz Abdulla0a626772008-01-13 16:02:42 -0500147 NvRegMacReset = 0x34,
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400148#define NVREG_MAC_RESET_ASSERT 0x0F3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149 NvRegTransmitterControl = 0x084,
150#define NVREG_XMITCTL_START 0x01
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500151#define NVREG_XMITCTL_MGMT_ST 0x40000000
152#define NVREG_XMITCTL_SYNC_MASK 0x000f0000
153#define NVREG_XMITCTL_SYNC_NOT_READY 0x0
154#define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
155#define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
156#define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
157#define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
158#define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
159#define NVREG_XMITCTL_HOST_LOADED 0x00004000
Ayaz Abdullaf35723e2003-02-20 03:03:54 -0500160#define NVREG_XMITCTL_TX_PATH_EN 0x01000000
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800161#define NVREG_XMITCTL_DATA_START 0x00100000
162#define NVREG_XMITCTL_DATA_READY 0x00010000
163#define NVREG_XMITCTL_DATA_ERROR 0x00020000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164 NvRegTransmitterStatus = 0x088,
165#define NVREG_XMITSTAT_BUSY 0x01
166
167 NvRegPacketFilterFlags = 0x8c,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400168#define NVREG_PFF_PAUSE_RX 0x08
169#define NVREG_PFF_ALWAYS 0x7F0000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170#define NVREG_PFF_PROMISC 0x80
171#define NVREG_PFF_MYADDR 0x20
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400172#define NVREG_PFF_LOOPBACK 0x10
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173
174 NvRegOffloadConfig = 0x90,
175#define NVREG_OFFLOAD_HOMEPHY 0x601
176#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
177 NvRegReceiverControl = 0x094,
178#define NVREG_RCVCTL_START 0x01
Ayaz Abdullaf35723e2003-02-20 03:03:54 -0500179#define NVREG_RCVCTL_RX_PATH_EN 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180 NvRegReceiverStatus = 0x98,
181#define NVREG_RCVSTAT_BUSY 0x01
182
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700183 NvRegSlotTime = 0x9c,
184#define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
185#define NVREG_SLOTTIME_10_100_FULL 0x00007f00
Szymon Janc78aea4f2010-11-27 08:39:43 +0000186#define NVREG_SLOTTIME_1000_FULL 0x0003ff00
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700187#define NVREG_SLOTTIME_HALF 0x0000ff00
Szymon Janc78aea4f2010-11-27 08:39:43 +0000188#define NVREG_SLOTTIME_DEFAULT 0x00007f00
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700189#define NVREG_SLOTTIME_MASK 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190
Ayaz Abdulla9744e212006-07-06 16:45:58 -0400191 NvRegTxDeferral = 0xA0,
Ayaz Abdullafd9b5582008-02-05 12:29:49 -0500192#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
193#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
194#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
195#define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
196#define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
197#define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
Ayaz Abdulla9744e212006-07-06 16:45:58 -0400198 NvRegRxDeferral = 0xA4,
199#define NVREG_RX_DEFERRAL_DEFAULT 0x16
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200 NvRegMacAddrA = 0xA8,
201 NvRegMacAddrB = 0xAC,
202 NvRegMulticastAddrA = 0xB0,
203#define NVREG_MCASTADDRA_FORCE 0x01
204 NvRegMulticastAddrB = 0xB4,
205 NvRegMulticastMaskA = 0xB8,
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -0500206#define NVREG_MCASTMASKA_NONE 0xffffffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207 NvRegMulticastMaskB = 0xBC,
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -0500208#define NVREG_MCASTMASKB_NONE 0xffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209
210 NvRegPhyInterface = 0xC0,
211#define PHY_RGMII 0x10000000
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700212 NvRegBackOffControl = 0xC4,
213#define NVREG_BKOFFCTRL_DEFAULT 0x70000000
214#define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
215#define NVREG_BKOFFCTRL_SELECT 24
216#define NVREG_BKOFFCTRL_GEAR 12
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217
218 NvRegTxRingPhysAddr = 0x100,
219 NvRegRxRingPhysAddr = 0x104,
220 NvRegRingSizes = 0x108,
221#define NVREG_RINGSZ_TXSHIFT 0
222#define NVREG_RINGSZ_RXSHIFT 16
Ayaz Abdulla5070d342006-07-31 12:05:01 -0400223 NvRegTransmitPoll = 0x10c,
224#define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225 NvRegLinkSpeed = 0x110,
226#define NVREG_LINKSPEED_FORCE 0x10000
227#define NVREG_LINKSPEED_10 1000
228#define NVREG_LINKSPEED_100 100
229#define NVREG_LINKSPEED_1000 50
230#define NVREG_LINKSPEED_MASK (0xFFF)
231 NvRegUnknownSetupReg5 = 0x130,
232#define NVREG_UNKSETUP5_BIT31 (1<<31)
Ayaz Abdulla95d161c2006-07-06 16:46:25 -0400233 NvRegTxWatermark = 0x13c,
234#define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
235#define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
236#define NVREG_TX_WM_DESC2_3_1000 0xfe08000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237 NvRegTxRxControl = 0x144,
238#define NVREG_TXRXCTL_KICK 0x0001
239#define NVREG_TXRXCTL_BIT1 0x0002
240#define NVREG_TXRXCTL_BIT2 0x0004
241#define NVREG_TXRXCTL_IDLE 0x0008
242#define NVREG_TXRXCTL_RESET 0x0010
243#define NVREG_TXRXCTL_RXCHECK 0x0400
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400244#define NVREG_TXRXCTL_DESC_1 0
Ayaz Abdullad2f78412007-01-09 13:30:02 -0500245#define NVREG_TXRXCTL_DESC_2 0x002100
246#define NVREG_TXRXCTL_DESC_3 0xc02200
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500247#define NVREG_TXRXCTL_VLANSTRIP 0x00040
248#define NVREG_TXRXCTL_VLANINS 0x00080
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500249 NvRegTxRingPhysAddrHigh = 0x148,
250 NvRegRxRingPhysAddrHigh = 0x14C,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400251 NvRegTxPauseFrame = 0x170,
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -0500252#define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
253#define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
254#define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
255#define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
Ayaz Abdulla9a33e882008-08-06 12:12:34 -0400256 NvRegTxPauseFrameLimit = 0x174,
257#define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258 NvRegMIIStatus = 0x180,
259#define NVREG_MIISTAT_ERROR 0x0001
260#define NVREG_MIISTAT_LINKCHANGE 0x0008
Ayaz Abdullaeb798422008-02-04 15:14:04 -0500261#define NVREG_MIISTAT_MASK_RW 0x0007
262#define NVREG_MIISTAT_MASK_ALL 0x000f
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500263 NvRegMIIMask = 0x184,
264#define NVREG_MII_LINKCHANGE 0x0008
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265
266 NvRegAdapterControl = 0x188,
267#define NVREG_ADAPTCTL_START 0x02
268#define NVREG_ADAPTCTL_LINKUP 0x04
269#define NVREG_ADAPTCTL_PHYVALID 0x40000
270#define NVREG_ADAPTCTL_RUNNING 0x100000
271#define NVREG_ADAPTCTL_PHYSHIFT 24
272 NvRegMIISpeed = 0x18c,
273#define NVREG_MIISPEED_BIT8 (1<<8)
274#define NVREG_MIIDELAY 5
275 NvRegMIIControl = 0x190,
276#define NVREG_MIICTL_INUSE 0x08000
277#define NVREG_MIICTL_WRITE 0x00400
278#define NVREG_MIICTL_ADDRSHIFT 5
279 NvRegMIIData = 0x194,
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400280 NvRegTxUnicast = 0x1a0,
281 NvRegTxMulticast = 0x1a4,
282 NvRegTxBroadcast = 0x1a8,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283 NvRegWakeUpFlags = 0x200,
284#define NVREG_WAKEUPFLAGS_VAL 0x7770
285#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
286#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
287#define NVREG_WAKEUPFLAGS_D3SHIFT 12
288#define NVREG_WAKEUPFLAGS_D2SHIFT 8
289#define NVREG_WAKEUPFLAGS_D1SHIFT 4
290#define NVREG_WAKEUPFLAGS_D0SHIFT 0
291#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
292#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
293#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
294#define NVREG_WAKEUPFLAGS_ENABLE 0x1111
295
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800296 NvRegMgmtUnitGetVersion = 0x204,
Szymon Janc78aea4f2010-11-27 08:39:43 +0000297#define NVREG_MGMTUNITGETVERSION 0x01
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800298 NvRegMgmtUnitVersion = 0x208,
299#define NVREG_MGMTUNITVERSION 0x08
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300 NvRegPowerCap = 0x268,
301#define NVREG_POWERCAP_D3SUPP (1<<30)
302#define NVREG_POWERCAP_D2SUPP (1<<26)
303#define NVREG_POWERCAP_D1SUPP (1<<25)
304 NvRegPowerState = 0x26c,
305#define NVREG_POWERSTATE_POWEREDUP 0x8000
306#define NVREG_POWERSTATE_VALID 0x0100
307#define NVREG_POWERSTATE_MASK 0x0003
308#define NVREG_POWERSTATE_D0 0x0000
309#define NVREG_POWERSTATE_D1 0x0001
310#define NVREG_POWERSTATE_D2 0x0002
311#define NVREG_POWERSTATE_D3 0x0003
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800312 NvRegMgmtUnitControl = 0x278,
313#define NVREG_MGMTUNITCONTROL_INUSE 0x20000
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400314 NvRegTxCnt = 0x280,
315 NvRegTxZeroReXmt = 0x284,
316 NvRegTxOneReXmt = 0x288,
317 NvRegTxManyReXmt = 0x28c,
318 NvRegTxLateCol = 0x290,
319 NvRegTxUnderflow = 0x294,
320 NvRegTxLossCarrier = 0x298,
321 NvRegTxExcessDef = 0x29c,
322 NvRegTxRetryErr = 0x2a0,
323 NvRegRxFrameErr = 0x2a4,
324 NvRegRxExtraByte = 0x2a8,
325 NvRegRxLateCol = 0x2ac,
326 NvRegRxRunt = 0x2b0,
327 NvRegRxFrameTooLong = 0x2b4,
328 NvRegRxOverflow = 0x2b8,
329 NvRegRxFCSErr = 0x2bc,
330 NvRegRxFrameAlignErr = 0x2c0,
331 NvRegRxLenErr = 0x2c4,
332 NvRegRxUnicast = 0x2c8,
333 NvRegRxMulticast = 0x2cc,
334 NvRegRxBroadcast = 0x2d0,
335 NvRegTxDef = 0x2d4,
336 NvRegTxFrame = 0x2d8,
337 NvRegRxCnt = 0x2dc,
338 NvRegTxPause = 0x2e0,
339 NvRegRxPause = 0x2e4,
340 NvRegRxDropFrame = 0x2e8,
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500341 NvRegVlanControl = 0x300,
342#define NVREG_VLANCONTROL_ENABLE 0x2000
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500343 NvRegMSIXMap0 = 0x3e0,
344 NvRegMSIXMap1 = 0x3e4,
345 NvRegMSIXIrqStatus = 0x3f0,
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400346
347 NvRegPowerState2 = 0x600,
Ayaz Abdulla1545e202008-09-22 09:55:35 -0400348#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400349#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400350#define NVREG_POWERSTATE2_PHY_RESET 0x0004
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +0000351#define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352};
353
354/* Big endian: should work, but is untested */
355struct ring_desc {
Stephen Hemmingera8bed492006-07-27 18:50:09 -0700356 __le32 buf;
357 __le32 flaglen;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358};
359
Manfred Spraulee733622005-07-31 18:32:26 +0200360struct ring_desc_ex {
Stephen Hemmingera8bed492006-07-27 18:50:09 -0700361 __le32 bufhigh;
362 __le32 buflow;
363 __le32 txvlan;
364 __le32 flaglen;
Manfred Spraulee733622005-07-31 18:32:26 +0200365};
366
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700367union ring_type {
Szymon Janc78aea4f2010-11-27 08:39:43 +0000368 struct ring_desc *orig;
369 struct ring_desc_ex *ex;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700370};
Manfred Spraulee733622005-07-31 18:32:26 +0200371
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372#define FLAG_MASK_V1 0xffff0000
373#define FLAG_MASK_V2 0xffffc000
374#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
375#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
376
377#define NV_TX_LASTPACKET (1<<16)
378#define NV_TX_RETRYERROR (1<<19)
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700379#define NV_TX_RETRYCOUNT_MASK (0xF<<20)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200380#define NV_TX_FORCED_INTERRUPT (1<<24)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381#define NV_TX_DEFERRED (1<<26)
382#define NV_TX_CARRIERLOST (1<<27)
383#define NV_TX_LATECOLLISION (1<<28)
384#define NV_TX_UNDERFLOW (1<<29)
385#define NV_TX_ERROR (1<<30)
386#define NV_TX_VALID (1<<31)
387
388#define NV_TX2_LASTPACKET (1<<29)
389#define NV_TX2_RETRYERROR (1<<18)
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700390#define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200391#define NV_TX2_FORCED_INTERRUPT (1<<30)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392#define NV_TX2_DEFERRED (1<<25)
393#define NV_TX2_CARRIERLOST (1<<26)
394#define NV_TX2_LATECOLLISION (1<<27)
395#define NV_TX2_UNDERFLOW (1<<28)
396/* error and valid are the same for both */
397#define NV_TX2_ERROR (1<<30)
398#define NV_TX2_VALID (1<<31)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -0400399#define NV_TX2_TSO (1<<28)
400#define NV_TX2_TSO_SHIFT 14
Ayaz Abdullafa454592006-01-05 22:45:45 -0800401#define NV_TX2_TSO_MAX_SHIFT 14
402#define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400403#define NV_TX2_CHECKSUM_L3 (1<<27)
404#define NV_TX2_CHECKSUM_L4 (1<<26)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500406#define NV_TX3_VLAN_TAG_PRESENT (1<<18)
407
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408#define NV_RX_DESCRIPTORVALID (1<<16)
409#define NV_RX_MISSEDFRAME (1<<17)
410#define NV_RX_SUBSTRACT1 (1<<18)
411#define NV_RX_ERROR1 (1<<23)
412#define NV_RX_ERROR2 (1<<24)
413#define NV_RX_ERROR3 (1<<25)
414#define NV_RX_ERROR4 (1<<26)
415#define NV_RX_CRCERR (1<<27)
416#define NV_RX_OVERFLOW (1<<28)
417#define NV_RX_FRAMINGERR (1<<29)
418#define NV_RX_ERROR (1<<30)
419#define NV_RX_AVAIL (1<<31)
Ayaz Abdulla1ef68412008-08-06 12:11:03 -0400420#define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421
422#define NV_RX2_CHECKSUMMASK (0x1C000000)
Ayaz Abdullabfaffe82008-01-13 16:02:55 -0500423#define NV_RX2_CHECKSUM_IP (0x10000000)
424#define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
425#define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426#define NV_RX2_DESCRIPTORVALID (1<<29)
427#define NV_RX2_SUBSTRACT1 (1<<25)
428#define NV_RX2_ERROR1 (1<<18)
429#define NV_RX2_ERROR2 (1<<19)
430#define NV_RX2_ERROR3 (1<<20)
431#define NV_RX2_ERROR4 (1<<21)
432#define NV_RX2_CRCERR (1<<22)
433#define NV_RX2_OVERFLOW (1<<23)
434#define NV_RX2_FRAMINGERR (1<<24)
435/* error and avail are the same for both */
436#define NV_RX2_ERROR (1<<30)
437#define NV_RX2_AVAIL (1<<31)
Ayaz Abdulla1ef68412008-08-06 12:11:03 -0400438#define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700439
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500440#define NV_RX3_VLAN_TAG_PRESENT (1<<16)
441#define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
442
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300443/* Miscellaneous hardware related defines: */
Szymon Janc78aea4f2010-11-27 08:39:43 +0000444#define NV_PCI_REGSZ_VER1 0x270
445#define NV_PCI_REGSZ_VER2 0x2d4
446#define NV_PCI_REGSZ_VER3 0x604
447#define NV_PCI_REGSZ_MAX 0x604
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448
449/* various timeout delays: all in usec */
450#define NV_TXRX_RESET_DELAY 4
451#define NV_TXSTOP_DELAY1 10
452#define NV_TXSTOP_DELAY1MAX 500000
453#define NV_TXSTOP_DELAY2 100
454#define NV_RXSTOP_DELAY1 10
455#define NV_RXSTOP_DELAY1MAX 500000
456#define NV_RXSTOP_DELAY2 100
457#define NV_SETUP5_DELAY 5
458#define NV_SETUP5_DELAYMAX 50000
459#define NV_POWERUP_DELAY 5
460#define NV_POWERUP_DELAYMAX 5000
461#define NV_MIIBUSY_DELAY 50
462#define NV_MIIPHY_DELAY 10
463#define NV_MIIPHY_DELAYMAX 10000
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400464#define NV_MAC_RESET_DELAY 64
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465
466#define NV_WAKEUPPATTERNS 5
467#define NV_WAKEUPMASKENTRIES 4
468
469/* General driver defaults */
470#define NV_WATCHDOG_TIMEO (5*HZ)
471
Ayaz Abdulla6cef67a2009-03-05 08:02:30 +0000472#define RX_RING_DEFAULT 512
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400473#define TX_RING_DEFAULT 256
474#define RX_RING_MIN 128
475#define TX_RING_MIN 64
476#define RING_MAX_DESC_VER_1 1024
477#define RING_MAX_DESC_VER_2_3 16384
Linus Torvalds1da177e2005-04-16 15:20:36 -0700478
479/* rx/tx mac addr + type + vlan + align + slack*/
Manfred Sprauld81c0982005-07-31 18:20:30 +0200480#define NV_RX_HEADERS (64)
481/* even more slack. */
482#define NV_RX_ALLOC_PAD (64)
483
484/* maximum mtu size */
485#define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
486#define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487
488#define OOM_REFILL (1+HZ/20)
489#define POLL_WAIT (1+HZ/100)
490#define LINK_TIMEOUT (3*HZ)
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400491#define STATS_INTERVAL (10*HZ)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492
Jeff Garzikf3b197a2006-05-26 21:39:03 -0400493/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700494 * desc_ver values:
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400495 * The nic supports three different descriptor types:
496 * - DESC_VER_1: Original
497 * - DESC_VER_2: support for jumbo frames.
498 * - DESC_VER_3: 64-bit format.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499 */
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400500#define DESC_VER_1 1
501#define DESC_VER_2 2
502#define DESC_VER_3 3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503
504/* PHY defines */
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400505#define PHY_OUI_MARVELL 0x5043
506#define PHY_OUI_CICADA 0x03f1
507#define PHY_OUI_VITESSE 0x01c1
508#define PHY_OUI_REALTEK 0x0732
509#define PHY_OUI_REALTEK2 0x0020
Linus Torvalds1da177e2005-04-16 15:20:36 -0700510#define PHYID1_OUI_MASK 0x03ff
511#define PHYID1_OUI_SHFT 6
512#define PHYID2_OUI_MASK 0xfc00
513#define PHYID2_OUI_SHFT 10
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400514#define PHYID2_MODEL_MASK 0x03f0
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400515#define PHY_MODEL_REALTEK_8211 0x0110
516#define PHY_REV_MASK 0x0001
517#define PHY_REV_REALTEK_8211B 0x0000
518#define PHY_REV_REALTEK_8211C 0x0001
519#define PHY_MODEL_REALTEK_8201 0x0200
520#define PHY_MODEL_MARVELL_E3016 0x0220
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400521#define PHY_MARVELL_E3016_INITMASK 0x0300
Ayaz Abdulla14a67f32007-07-15 06:50:28 -0400522#define PHY_CICADA_INIT1 0x0f000
523#define PHY_CICADA_INIT2 0x0e00
524#define PHY_CICADA_INIT3 0x01000
525#define PHY_CICADA_INIT4 0x0200
526#define PHY_CICADA_INIT5 0x0004
527#define PHY_CICADA_INIT6 0x02000
Ayaz Abdullad215d8a2007-07-15 06:50:53 -0400528#define PHY_VITESSE_INIT_REG1 0x1f
529#define PHY_VITESSE_INIT_REG2 0x10
530#define PHY_VITESSE_INIT_REG3 0x11
531#define PHY_VITESSE_INIT_REG4 0x12
532#define PHY_VITESSE_INIT_MSK1 0xc
533#define PHY_VITESSE_INIT_MSK2 0x0180
534#define PHY_VITESSE_INIT1 0x52b5
535#define PHY_VITESSE_INIT2 0xaf8a
536#define PHY_VITESSE_INIT3 0x8
537#define PHY_VITESSE_INIT4 0x8f8a
538#define PHY_VITESSE_INIT5 0xaf86
539#define PHY_VITESSE_INIT6 0x8f86
540#define PHY_VITESSE_INIT7 0xaf82
541#define PHY_VITESSE_INIT8 0x0100
542#define PHY_VITESSE_INIT9 0x8f82
543#define PHY_VITESSE_INIT10 0x0
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -0400544#define PHY_REALTEK_INIT_REG1 0x1f
545#define PHY_REALTEK_INIT_REG2 0x19
546#define PHY_REALTEK_INIT_REG3 0x13
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400547#define PHY_REALTEK_INIT_REG4 0x14
548#define PHY_REALTEK_INIT_REG5 0x18
549#define PHY_REALTEK_INIT_REG6 0x11
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400550#define PHY_REALTEK_INIT_REG7 0x01
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -0400551#define PHY_REALTEK_INIT1 0x0000
552#define PHY_REALTEK_INIT2 0x8e00
553#define PHY_REALTEK_INIT3 0x0001
554#define PHY_REALTEK_INIT4 0xad17
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400555#define PHY_REALTEK_INIT5 0xfb54
556#define PHY_REALTEK_INIT6 0xf5c7
557#define PHY_REALTEK_INIT7 0x1000
558#define PHY_REALTEK_INIT8 0x0003
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400559#define PHY_REALTEK_INIT9 0x0008
560#define PHY_REALTEK_INIT10 0x0005
561#define PHY_REALTEK_INIT11 0x0200
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400562#define PHY_REALTEK_INIT_MSK1 0x0003
Ayaz Abdullad215d8a2007-07-15 06:50:53 -0400563
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564#define PHY_GIGABIT 0x0100
565
566#define PHY_TIMEOUT 0x1
567#define PHY_ERROR 0x2
568
569#define PHY_100 0x1
570#define PHY_1000 0x2
571#define PHY_HALF 0x100
572
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400573#define NV_PAUSEFRAME_RX_CAPABLE 0x0001
574#define NV_PAUSEFRAME_TX_CAPABLE 0x0002
575#define NV_PAUSEFRAME_RX_ENABLE 0x0004
576#define NV_PAUSEFRAME_TX_ENABLE 0x0008
Ayaz Abdullab6d07732006-06-10 22:47:42 -0400577#define NV_PAUSEFRAME_RX_REQ 0x0010
578#define NV_PAUSEFRAME_TX_REQ 0x0020
579#define NV_PAUSEFRAME_AUTONEG 0x0040
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500581/* MSI/MSI-X defines */
582#define NV_MSI_X_MAX_VECTORS 8
583#define NV_MSI_X_VECTORS_MASK 0x000f
584#define NV_MSI_CAPABLE 0x0010
585#define NV_MSI_X_CAPABLE 0x0020
586#define NV_MSI_ENABLED 0x0040
587#define NV_MSI_X_ENABLED 0x0080
588
589#define NV_MSI_X_VECTOR_ALL 0x0
590#define NV_MSI_X_VECTOR_RX 0x0
591#define NV_MSI_X_VECTOR_TX 0x1
592#define NV_MSI_X_VECTOR_OTHER 0x2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700593
Ayaz Abdullab6e44052009-02-07 00:24:15 -0800594#define NV_MSI_PRIV_OFFSET 0x68
595#define NV_MSI_PRIV_VALUE 0xffffffff
596
Ayaz Abdullab2976d22008-02-04 15:13:59 -0500597#define NV_RESTART_TX 0x1
598#define NV_RESTART_RX 0x2
599
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500600#define NV_TX_LIMIT_COUNT 16
601
Ayaz Abdulla4145ade2009-03-05 08:02:26 +0000602#define NV_DYNAMIC_THRESHOLD 4
603#define NV_DYNAMIC_MAX_QUIET_COUNT 2048
604
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400605/* statistics */
606struct nv_ethtool_str {
607 char name[ETH_GSTRING_LEN];
608};
609
610static const struct nv_ethtool_str nv_estats_str[] = {
611 { "tx_bytes" },
612 { "tx_zero_rexmt" },
613 { "tx_one_rexmt" },
614 { "tx_many_rexmt" },
615 { "tx_late_collision" },
616 { "tx_fifo_errors" },
617 { "tx_carrier_errors" },
618 { "tx_excess_deferral" },
619 { "tx_retry_error" },
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400620 { "rx_frame_error" },
621 { "rx_extra_byte" },
622 { "rx_late_collision" },
623 { "rx_runt" },
624 { "rx_frame_too_long" },
625 { "rx_over_errors" },
626 { "rx_crc_errors" },
627 { "rx_frame_align_error" },
628 { "rx_length_error" },
629 { "rx_unicast" },
630 { "rx_multicast" },
631 { "rx_broadcast" },
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400632 { "rx_packets" },
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500633 { "rx_errors_total" },
634 { "tx_errors_total" },
635
636 /* version 2 stats */
637 { "tx_deferral" },
638 { "tx_packets" },
639 { "rx_bytes" },
640 { "tx_pause" },
641 { "rx_pause" },
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400642 { "rx_drop_frame" },
643
644 /* version 3 stats */
645 { "tx_unicast" },
646 { "tx_multicast" },
647 { "tx_broadcast" }
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400648};
649
650struct nv_ethtool_stats {
651 u64 tx_bytes;
652 u64 tx_zero_rexmt;
653 u64 tx_one_rexmt;
654 u64 tx_many_rexmt;
655 u64 tx_late_collision;
656 u64 tx_fifo_errors;
657 u64 tx_carrier_errors;
658 u64 tx_excess_deferral;
659 u64 tx_retry_error;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400660 u64 rx_frame_error;
661 u64 rx_extra_byte;
662 u64 rx_late_collision;
663 u64 rx_runt;
664 u64 rx_frame_too_long;
665 u64 rx_over_errors;
666 u64 rx_crc_errors;
667 u64 rx_frame_align_error;
668 u64 rx_length_error;
669 u64 rx_unicast;
670 u64 rx_multicast;
671 u64 rx_broadcast;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400672 u64 rx_packets;
673 u64 rx_errors_total;
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500674 u64 tx_errors_total;
675
676 /* version 2 stats */
677 u64 tx_deferral;
678 u64 tx_packets;
679 u64 rx_bytes;
680 u64 tx_pause;
681 u64 rx_pause;
682 u64 rx_drop_frame;
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400683
684 /* version 3 stats */
685 u64 tx_unicast;
686 u64 tx_multicast;
687 u64 tx_broadcast;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400688};
689
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400690#define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
691#define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500692#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
693
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400694/* diagnostics */
695#define NV_TEST_COUNT_BASE 3
696#define NV_TEST_COUNT_EXTENDED 4
697
698static const struct nv_ethtool_str nv_etests_str[] = {
699 { "link (online/offline)" },
700 { "register (offline) " },
701 { "interrupt (offline) " },
702 { "loopback (offline) " }
703};
704
705struct register_test {
Al Viro5bb7ea22007-12-09 16:06:41 +0000706 __u32 reg;
707 __u32 mask;
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400708};
709
710static const struct register_test nv_registers_test[] = {
711 { NvRegUnknownSetupReg6, 0x01 },
712 { NvRegMisc1, 0x03c },
713 { NvRegOffloadConfig, 0x03ff },
714 { NvRegMulticastAddrA, 0xffffffff },
Ayaz Abdulla95d161c2006-07-06 16:46:25 -0400715 { NvRegTxWatermark, 0x0ff },
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400716 { NvRegWakeUpFlags, 0x07777 },
Szymon Janc78aea4f2010-11-27 08:39:43 +0000717 { 0, 0 }
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400718};
719
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500720struct nv_skb_map {
721 struct sk_buff *skb;
722 dma_addr_t dma;
Eric Dumazet73a37072009-06-17 21:17:59 +0000723 unsigned int dma_len:31;
724 unsigned int dma_single:1;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500725 struct ring_desc_ex *first_tx_desc;
726 struct nv_skb_map *next_tx_ctx;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500727};
728
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729/*
730 * SMP locking:
Wang Chenb74ca3a2008-12-08 01:14:16 -0800731 * All hardware access under netdev_priv(dev)->lock, except the performance
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732 * critical parts:
733 * - rx is (pseudo-) lockless: it relies on the single-threading provided
734 * by the arch code for interrupts.
Herbert Xu932ff272006-06-09 12:20:56 -0700735 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
Wang Chenb74ca3a2008-12-08 01:14:16 -0800736 * needs netdev_priv(dev)->lock :-(
Herbert Xu932ff272006-06-09 12:20:56 -0700737 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700738 */
739
740/* in dev: base, irq */
741struct fe_priv {
742 spinlock_t lock;
743
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700744 struct net_device *dev;
745 struct napi_struct napi;
746
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747 /* General data:
748 * Locking: spin_lock(&np->lock); */
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400749 struct nv_ethtool_stats estats;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750 int in_shutdown;
751 u32 linkspeed;
752 int duplex;
753 int autoneg;
754 int fixed_mode;
755 int phyaddr;
756 int wolenabled;
757 unsigned int phy_oui;
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400758 unsigned int phy_model;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400759 unsigned int phy_rev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700760 u16 gigabit;
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400761 int intr_test;
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500762 int recover_error;
Ayaz Abdulla4145ade2009-03-05 08:02:26 +0000763 int quiet_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700764
765 /* General data: RO fields */
766 dma_addr_t ring_addr;
767 struct pci_dev *pci_dev;
768 u32 orig_mac[2];
Ayaz Abdulla582806b2009-03-05 08:02:03 +0000769 u32 events;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770 u32 irqmask;
771 u32 desc_ver;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400772 u32 txrxctl_bits;
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500773 u32 vlanctl_bits;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400774 u32 driver_data;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400775 u32 device_id;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400776 u32 register_size;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500777 u32 mac_in_use;
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800778 int mgmt_version;
779 int mgmt_sema;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780
781 void __iomem *base;
782
783 /* rx specific fields.
784 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
785 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500786 union ring_type get_rx, put_rx, first_rx, last_rx;
787 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
788 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
789 struct nv_skb_map *rx_skb;
790
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700791 union ring_type rx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792 unsigned int rx_buf_sz;
Manfred Sprauld81c0982005-07-31 18:20:30 +0200793 unsigned int pkt_limit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794 struct timer_list oom_kick;
795 struct timer_list nic_poll;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400796 struct timer_list stats_poll;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500797 u32 nic_poll_irq;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400798 int rx_ring_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700799
800 /* media detection workaround.
801 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
802 */
803 int need_linktimer;
804 unsigned long link_timeout;
805 /*
806 * tx specific fields.
807 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500808 union ring_type get_tx, put_tx, first_tx, last_tx;
809 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
810 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
811 struct nv_skb_map *tx_skb;
812
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700813 union ring_type tx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814 u32 tx_flags;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400815 int tx_ring_size;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500816 int tx_limit;
817 u32 tx_pkts_in_progress;
818 struct nv_skb_map *tx_change_owner;
819 struct nv_skb_map *tx_end_flip;
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -0500820 int tx_stop;
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500821
822 /* vlan fields */
823 struct vlan_group *vlangrp;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500824
825 /* msi/msi-x fields */
826 u32 msi_flags;
827 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400828
829 /* flow control */
830 u32 pause_flags;
Tobias Diedrich1a1ca862008-05-18 15:03:44 +0200831
832 /* power saved state */
833 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
Yinghai Luddb213f2009-02-06 01:29:23 -0800834
835 /* for different msi-x irq type */
836 char name_rx[IFNAMSIZ + 3]; /* -rx */
837 char name_tx[IFNAMSIZ + 3]; /* -tx */
838 char name_other[IFNAMSIZ + 6]; /* -other */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700839};
840
841/*
842 * Maximum number of loops until we assume that a bit in the irq mask
843 * is stuck. Overridable with module param.
844 */
Ayaz Abdulla4145ade2009-03-05 08:02:26 +0000845static int max_interrupt_work = 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700846
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500847/*
848 * Optimization can be either throuput mode or cpu mode
Jeff Garzikf3b197a2006-05-26 21:39:03 -0400849 *
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500850 * Throughput Mode: Every tx and rx packet will generate an interrupt.
851 * CPU Mode: Interrupts are controlled by a timer.
852 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400853enum {
854 NV_OPTIMIZATION_MODE_THROUGHPUT,
Ayaz Abdulla9e184762009-03-05 08:02:18 +0000855 NV_OPTIMIZATION_MODE_CPU,
856 NV_OPTIMIZATION_MODE_DYNAMIC
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400857};
Ayaz Abdulla9e184762009-03-05 08:02:18 +0000858static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500859
860/*
861 * Poll interval for timer irq
862 *
863 * This interval determines how frequent an interrupt is generated.
864 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
865 * Min = 0, and Max = 65535
866 */
867static int poll_interval = -1;
868
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500869/*
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400870 * MSI interrupts
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500871 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400872enum {
873 NV_MSI_INT_DISABLED,
874 NV_MSI_INT_ENABLED
875};
876static int msi = NV_MSI_INT_ENABLED;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500877
878/*
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400879 * MSIX interrupts
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500880 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400881enum {
882 NV_MSIX_INT_DISABLED,
883 NV_MSIX_INT_ENABLED
884};
Yinghai Lu39482792009-02-06 01:31:12 -0800885static int msix = NV_MSIX_INT_ENABLED;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400886
887/*
888 * DMA 64bit
889 */
890enum {
891 NV_DMA_64BIT_DISABLED,
892 NV_DMA_64BIT_ENABLED
893};
894static int dma_64bit = NV_DMA_64BIT_ENABLED;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500895
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400896/*
897 * Crossover Detection
898 * Realtek 8201 phy + some OEM boards do not work properly.
899 */
900enum {
901 NV_CROSSOVER_DETECTION_DISABLED,
902 NV_CROSSOVER_DETECTION_ENABLED
903};
904static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
905
Ed Swierk5a9a8e32009-06-02 00:19:52 -0700906/*
907 * Power down phy when interface is down (persists through reboot;
908 * older Linux and other OSes may not power it up again)
909 */
Szymon Janc78aea4f2010-11-27 08:39:43 +0000910static int phy_power_down;
Ed Swierk5a9a8e32009-06-02 00:19:52 -0700911
Linus Torvalds1da177e2005-04-16 15:20:36 -0700912static inline struct fe_priv *get_nvpriv(struct net_device *dev)
913{
914 return netdev_priv(dev);
915}
916
917static inline u8 __iomem *get_hwbase(struct net_device *dev)
918{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -0400919 return ((struct fe_priv *)netdev_priv(dev))->base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700920}
921
922static inline void pci_push(u8 __iomem *base)
923{
924 /* force out pending posted writes */
925 readl(base);
926}
927
928static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
929{
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700930 return le32_to_cpu(prd->flaglen)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700931 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
932}
933
Manfred Spraulee733622005-07-31 18:32:26 +0200934static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
935{
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700936 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
Manfred Spraulee733622005-07-31 18:32:26 +0200937}
938
Jeff Garzik36b30ea2007-10-16 01:40:30 -0400939static bool nv_optimized(struct fe_priv *np)
940{
941 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
942 return false;
943 return true;
944}
945
Linus Torvalds1da177e2005-04-16 15:20:36 -0700946static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
Joe Perches344d0dc2010-11-29 07:41:52 +0000947 int delay, int delaymax)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700948{
949 u8 __iomem *base = get_hwbase(dev);
950
951 pci_push(base);
952 do {
953 udelay(delay);
954 delaymax -= delay;
Joe Perches344d0dc2010-11-29 07:41:52 +0000955 if (delaymax < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700956 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700957 } while ((readl(base + offset) & mask) != target);
958 return 0;
959}
960
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500961#define NV_SETUP_RX_RING 0x01
962#define NV_SETUP_TX_RING 0x02
963
Al Viro5bb7ea22007-12-09 16:06:41 +0000964static inline u32 dma_low(dma_addr_t addr)
965{
966 return addr;
967}
968
969static inline u32 dma_high(dma_addr_t addr)
970{
971 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
972}
973
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500974static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
975{
976 struct fe_priv *np = get_nvpriv(dev);
977 u8 __iomem *base = get_hwbase(dev);
978
Jeff Garzik36b30ea2007-10-16 01:40:30 -0400979 if (!nv_optimized(np)) {
Szymon Janc78aea4f2010-11-27 08:39:43 +0000980 if (rxtx_flags & NV_SETUP_RX_RING)
Al Viro5bb7ea22007-12-09 16:06:41 +0000981 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
Szymon Janc78aea4f2010-11-27 08:39:43 +0000982 if (rxtx_flags & NV_SETUP_TX_RING)
Al Viro5bb7ea22007-12-09 16:06:41 +0000983 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500984 } else {
985 if (rxtx_flags & NV_SETUP_RX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000986 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
987 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500988 }
989 if (rxtx_flags & NV_SETUP_TX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000990 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
991 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500992 }
993 }
994}
995
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400996static void free_rings(struct net_device *dev)
997{
998 struct fe_priv *np = get_nvpriv(dev);
999
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001000 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001001 if (np->rx_ring.orig)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001002 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1003 np->rx_ring.orig, np->ring_addr);
1004 } else {
1005 if (np->rx_ring.ex)
1006 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1007 np->rx_ring.ex, np->ring_addr);
1008 }
Szymon Janc9b03b062010-11-27 08:39:44 +00001009 kfree(np->rx_skb);
1010 kfree(np->tx_skb);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001011}
1012
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001013static int using_multi_irqs(struct net_device *dev)
1014{
1015 struct fe_priv *np = get_nvpriv(dev);
1016
1017 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1018 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1019 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1020 return 0;
1021 else
1022 return 1;
1023}
1024
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00001025static void nv_txrx_gate(struct net_device *dev, bool gate)
1026{
1027 struct fe_priv *np = get_nvpriv(dev);
1028 u8 __iomem *base = get_hwbase(dev);
1029 u32 powerstate;
1030
1031 if (!np->mac_in_use &&
1032 (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1033 powerstate = readl(base + NvRegPowerState2);
1034 if (gate)
1035 powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1036 else
1037 powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1038 writel(powerstate, base + NvRegPowerState2);
1039 }
1040}
1041
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001042static void nv_enable_irq(struct net_device *dev)
1043{
1044 struct fe_priv *np = get_nvpriv(dev);
1045
1046 if (!using_multi_irqs(dev)) {
1047 if (np->msi_flags & NV_MSI_X_ENABLED)
1048 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1049 else
Manfred Spraula7475902007-10-17 21:52:33 +02001050 enable_irq(np->pci_dev->irq);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001051 } else {
1052 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1053 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1054 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1055 }
1056}
1057
1058static void nv_disable_irq(struct net_device *dev)
1059{
1060 struct fe_priv *np = get_nvpriv(dev);
1061
1062 if (!using_multi_irqs(dev)) {
1063 if (np->msi_flags & NV_MSI_X_ENABLED)
1064 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1065 else
Manfred Spraula7475902007-10-17 21:52:33 +02001066 disable_irq(np->pci_dev->irq);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001067 } else {
1068 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1069 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1070 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1071 }
1072}
1073
1074/* In MSIX mode, a write to irqmask behaves as XOR */
1075static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1076{
1077 u8 __iomem *base = get_hwbase(dev);
1078
1079 writel(mask, base + NvRegIrqMask);
1080}
1081
1082static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1083{
1084 struct fe_priv *np = get_nvpriv(dev);
1085 u8 __iomem *base = get_hwbase(dev);
1086
1087 if (np->msi_flags & NV_MSI_X_ENABLED) {
1088 writel(mask, base + NvRegIrqMask);
1089 } else {
1090 if (np->msi_flags & NV_MSI_ENABLED)
1091 writel(0, base + NvRegMSIIrqMask);
1092 writel(0, base + NvRegIrqMask);
1093 }
1094}
1095
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001096static void nv_napi_enable(struct net_device *dev)
1097{
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001098 struct fe_priv *np = get_nvpriv(dev);
1099
1100 napi_enable(&np->napi);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001101}
1102
1103static void nv_napi_disable(struct net_device *dev)
1104{
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001105 struct fe_priv *np = get_nvpriv(dev);
1106
1107 napi_disable(&np->napi);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001108}
1109
Linus Torvalds1da177e2005-04-16 15:20:36 -07001110#define MII_READ (-1)
1111/* mii_rw: read/write a register on the PHY.
1112 *
1113 * Caller must guarantee serialization
1114 */
1115static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1116{
1117 u8 __iomem *base = get_hwbase(dev);
1118 u32 reg;
1119 int retval;
1120
Ayaz Abdullaeb798422008-02-04 15:14:04 -05001121 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001122
1123 reg = readl(base + NvRegMIIControl);
1124 if (reg & NVREG_MIICTL_INUSE) {
1125 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1126 udelay(NV_MIIBUSY_DELAY);
1127 }
1128
1129 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1130 if (value != MII_READ) {
1131 writel(value, base + NvRegMIIData);
1132 reg |= NVREG_MIICTL_WRITE;
1133 }
1134 writel(reg, base + NvRegMIIControl);
1135
1136 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
Joe Perches344d0dc2010-11-29 07:41:52 +00001137 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001138 retval = -1;
1139 } else if (value != MII_READ) {
1140 /* it was a write operation - fewer failures are detectable */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001141 retval = 0;
1142 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001143 retval = -1;
1144 } else {
1145 retval = readl(base + NvRegMIIData);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001146 }
1147
1148 return retval;
1149}
1150
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001151static int phy_reset(struct net_device *dev, u32 bmcr_setup)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001152{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001153 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001154 u32 miicontrol;
1155 unsigned int tries = 0;
1156
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001157 miicontrol = BMCR_RESET | bmcr_setup;
Szymon Janc78aea4f2010-11-27 08:39:43 +00001158 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001159 return -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001160
1161 /* wait for 500ms */
1162 msleep(500);
1163
1164 /* must wait till reset is deasserted */
1165 while (miicontrol & BMCR_RESET) {
Szymon Jancde855b92010-11-27 08:39:48 +00001166 usleep_range(10000, 20000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001167 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1168 /* FIXME: 100 tries seem excessive */
1169 if (tries++ > 100)
1170 return -1;
1171 }
1172 return 0;
1173}
1174
Joe Perchesc41d41e2010-11-29 07:41:58 +00001175static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1176{
1177 static const struct {
1178 int reg;
1179 int init;
1180 } ri[] = {
1181 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1182 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1183 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1184 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1185 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1186 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1187 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1188 };
1189 int i;
1190
1191 for (i = 0; i < ARRAY_SIZE(ri); i++) {
Joe Perchescd663282010-11-29 07:41:59 +00001192 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
Joe Perchesc41d41e2010-11-29 07:41:58 +00001193 return PHY_ERROR;
Joe Perchesc41d41e2010-11-29 07:41:58 +00001194 }
1195
1196 return 0;
1197}
1198
Joe Perchescd663282010-11-29 07:41:59 +00001199static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1200{
1201 u32 reg;
1202 u8 __iomem *base = get_hwbase(dev);
1203 u32 powerstate = readl(base + NvRegPowerState2);
1204
1205 /* need to perform hw phy reset */
1206 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1207 writel(powerstate, base + NvRegPowerState2);
1208 msleep(25);
1209
1210 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1211 writel(powerstate, base + NvRegPowerState2);
1212 msleep(25);
1213
1214 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1215 reg |= PHY_REALTEK_INIT9;
1216 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1217 return PHY_ERROR;
1218 if (mii_rw(dev, np->phyaddr,
1219 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1220 return PHY_ERROR;
1221 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1222 if (!(reg & PHY_REALTEK_INIT11)) {
1223 reg |= PHY_REALTEK_INIT11;
1224 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1225 return PHY_ERROR;
1226 }
1227 if (mii_rw(dev, np->phyaddr,
1228 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1229 return PHY_ERROR;
1230
1231 return 0;
1232}
1233
1234static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1235{
1236 u32 phy_reserved;
1237
1238 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1239 phy_reserved = mii_rw(dev, np->phyaddr,
1240 PHY_REALTEK_INIT_REG6, MII_READ);
1241 phy_reserved |= PHY_REALTEK_INIT7;
1242 if (mii_rw(dev, np->phyaddr,
1243 PHY_REALTEK_INIT_REG6, phy_reserved))
1244 return PHY_ERROR;
1245 }
1246
1247 return 0;
1248}
1249
1250static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1251{
1252 u32 phy_reserved;
1253
1254 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1255 if (mii_rw(dev, np->phyaddr,
1256 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1257 return PHY_ERROR;
1258 phy_reserved = mii_rw(dev, np->phyaddr,
1259 PHY_REALTEK_INIT_REG2, MII_READ);
1260 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1261 phy_reserved |= PHY_REALTEK_INIT3;
1262 if (mii_rw(dev, np->phyaddr,
1263 PHY_REALTEK_INIT_REG2, phy_reserved))
1264 return PHY_ERROR;
1265 if (mii_rw(dev, np->phyaddr,
1266 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1267 return PHY_ERROR;
1268 }
1269
1270 return 0;
1271}
1272
1273static int init_cicada(struct net_device *dev, struct fe_priv *np,
1274 u32 phyinterface)
1275{
1276 u32 phy_reserved;
1277
1278 if (phyinterface & PHY_RGMII) {
1279 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1280 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1281 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1282 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1283 return PHY_ERROR;
1284 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1285 phy_reserved |= PHY_CICADA_INIT5;
1286 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1287 return PHY_ERROR;
1288 }
1289 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1290 phy_reserved |= PHY_CICADA_INIT6;
1291 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1292 return PHY_ERROR;
1293
1294 return 0;
1295}
1296
1297static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1298{
1299 u32 phy_reserved;
1300
1301 if (mii_rw(dev, np->phyaddr,
1302 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1303 return PHY_ERROR;
1304 if (mii_rw(dev, np->phyaddr,
1305 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1306 return PHY_ERROR;
1307 phy_reserved = mii_rw(dev, np->phyaddr,
1308 PHY_VITESSE_INIT_REG4, MII_READ);
1309 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1310 return PHY_ERROR;
1311 phy_reserved = mii_rw(dev, np->phyaddr,
1312 PHY_VITESSE_INIT_REG3, MII_READ);
1313 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1314 phy_reserved |= PHY_VITESSE_INIT3;
1315 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1316 return PHY_ERROR;
1317 if (mii_rw(dev, np->phyaddr,
1318 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1319 return PHY_ERROR;
1320 if (mii_rw(dev, np->phyaddr,
1321 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1322 return PHY_ERROR;
1323 phy_reserved = mii_rw(dev, np->phyaddr,
1324 PHY_VITESSE_INIT_REG4, MII_READ);
1325 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1326 phy_reserved |= PHY_VITESSE_INIT3;
1327 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1328 return PHY_ERROR;
1329 phy_reserved = mii_rw(dev, np->phyaddr,
1330 PHY_VITESSE_INIT_REG3, MII_READ);
1331 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1332 return PHY_ERROR;
1333 if (mii_rw(dev, np->phyaddr,
1334 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1335 return PHY_ERROR;
1336 if (mii_rw(dev, np->phyaddr,
1337 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1338 return PHY_ERROR;
1339 phy_reserved = mii_rw(dev, np->phyaddr,
1340 PHY_VITESSE_INIT_REG4, MII_READ);
1341 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1342 return PHY_ERROR;
1343 phy_reserved = mii_rw(dev, np->phyaddr,
1344 PHY_VITESSE_INIT_REG3, MII_READ);
1345 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1346 phy_reserved |= PHY_VITESSE_INIT8;
1347 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1348 return PHY_ERROR;
1349 if (mii_rw(dev, np->phyaddr,
1350 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1351 return PHY_ERROR;
1352 if (mii_rw(dev, np->phyaddr,
1353 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1354 return PHY_ERROR;
1355
1356 return 0;
1357}
1358
Linus Torvalds1da177e2005-04-16 15:20:36 -07001359static int phy_init(struct net_device *dev)
1360{
1361 struct fe_priv *np = get_nvpriv(dev);
1362 u8 __iomem *base = get_hwbase(dev);
Joe Perchescd663282010-11-29 07:41:59 +00001363 u32 phyinterface;
1364 u32 mii_status, mii_control, mii_control_1000, reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001365
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001366 /* phy errata for E3016 phy */
1367 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1368 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1369 reg &= ~PHY_MARVELL_E3016_INITMASK;
1370 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001371 netdev_info(dev, "%s: phy write to errata reg failed\n",
1372 pci_name(np->pci_dev));
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001373 return PHY_ERROR;
1374 }
1375 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001376 if (np->phy_oui == PHY_OUI_REALTEK) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001377 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1378 np->phy_rev == PHY_REV_REALTEK_8211B) {
Joe Perchescd663282010-11-29 07:41:59 +00001379 if (init_realtek_8211b(dev, np)) {
1380 netdev_info(dev, "%s: phy init failed\n",
1381 pci_name(np->pci_dev));
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001382 return PHY_ERROR;
Joe Perchescd663282010-11-29 07:41:59 +00001383 }
Joe Perchesc41d41e2010-11-29 07:41:58 +00001384 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1385 np->phy_rev == PHY_REV_REALTEK_8211C) {
Joe Perchescd663282010-11-29 07:41:59 +00001386 if (init_realtek_8211c(dev, np)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001387 netdev_info(dev, "%s: phy init failed\n",
1388 pci_name(np->pci_dev));
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001389 return PHY_ERROR;
1390 }
Joe Perchescd663282010-11-29 07:41:59 +00001391 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1392 if (init_realtek_8201(dev, np)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001393 netdev_info(dev, "%s: phy init failed\n",
1394 pci_name(np->pci_dev));
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001395 return PHY_ERROR;
1396 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001397 }
1398 }
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001399
Linus Torvalds1da177e2005-04-16 15:20:36 -07001400 /* set advertise register */
1401 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Joe Perchescd663282010-11-29 07:41:59 +00001402 reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1403 ADVERTISE_100HALF | ADVERTISE_100FULL |
1404 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001405 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001406 netdev_info(dev, "%s: phy write to advertise failed\n",
1407 pci_name(np->pci_dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001408 return PHY_ERROR;
1409 }
1410
1411 /* get phy interface type */
1412 phyinterface = readl(base + NvRegPhyInterface);
1413
1414 /* see if gigabit phy */
1415 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1416 if (mii_status & PHY_GIGABIT) {
1417 np->gigabit = PHY_GIGABIT;
Joe Perchescd663282010-11-29 07:41:59 +00001418 mii_control_1000 = mii_rw(dev, np->phyaddr,
1419 MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001420 mii_control_1000 &= ~ADVERTISE_1000HALF;
1421 if (phyinterface & PHY_RGMII)
1422 mii_control_1000 |= ADVERTISE_1000FULL;
1423 else
1424 mii_control_1000 &= ~ADVERTISE_1000FULL;
1425
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001426 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001427 netdev_info(dev, "%s: phy init failed\n",
1428 pci_name(np->pci_dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001429 return PHY_ERROR;
1430 }
Szymon Janc78aea4f2010-11-27 08:39:43 +00001431 } else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001432 np->gigabit = 0;
1433
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001434 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1435 mii_control |= BMCR_ANENABLE;
1436
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001437 if (np->phy_oui == PHY_OUI_REALTEK &&
1438 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1439 np->phy_rev == PHY_REV_REALTEK_8211C) {
1440 /* start autoneg since we already performed hw reset above */
1441 mii_control |= BMCR_ANRESTART;
1442 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001443 netdev_info(dev, "%s: phy init failed\n",
1444 pci_name(np->pci_dev));
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001445 return PHY_ERROR;
1446 }
1447 } else {
1448 /* reset the phy
1449 * (certain phys need bmcr to be setup with reset)
1450 */
1451 if (phy_reset(dev, mii_control)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001452 netdev_info(dev, "%s: phy reset failed\n",
1453 pci_name(np->pci_dev));
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001454 return PHY_ERROR;
1455 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001456 }
1457
1458 /* phy vendor specific configuration */
Joe Perchescd663282010-11-29 07:41:59 +00001459 if ((np->phy_oui == PHY_OUI_CICADA)) {
1460 if (init_cicada(dev, np, phyinterface)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001461 netdev_info(dev, "%s: phy init failed\n",
1462 pci_name(np->pci_dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001463 return PHY_ERROR;
1464 }
Joe Perchescd663282010-11-29 07:41:59 +00001465 } else if (np->phy_oui == PHY_OUI_VITESSE) {
1466 if (init_vitesse(dev, np)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001467 netdev_info(dev, "%s: phy init failed\n",
1468 pci_name(np->pci_dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001469 return PHY_ERROR;
1470 }
Joe Perchescd663282010-11-29 07:41:59 +00001471 } else if (np->phy_oui == PHY_OUI_REALTEK) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001472 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1473 np->phy_rev == PHY_REV_REALTEK_8211B) {
1474 /* reset could have cleared these out, set them back */
Joe Perchescd663282010-11-29 07:41:59 +00001475 if (init_realtek_8211b(dev, np)) {
1476 netdev_info(dev, "%s: phy init failed\n",
1477 pci_name(np->pci_dev));
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001478 return PHY_ERROR;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001479 }
Joe Perchescd663282010-11-29 07:41:59 +00001480 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1481 if (init_realtek_8201(dev, np) ||
1482 init_realtek_8201_cross(dev, np)) {
1483 netdev_info(dev, "%s: phy init failed\n",
1484 pci_name(np->pci_dev));
1485 return PHY_ERROR;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001486 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001487 }
1488 }
1489
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001490 /* some phys clear out pause advertisement on reset, set it back */
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001491 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001492
Ed Swierkcb52deb2008-12-01 12:24:43 +00001493 /* restart auto negotiation, power down phy */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001494 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ed Swierk5a9a8e32009-06-02 00:19:52 -07001495 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001496 if (phy_power_down)
Ed Swierk5a9a8e32009-06-02 00:19:52 -07001497 mii_control |= BMCR_PDOWN;
Szymon Janc78aea4f2010-11-27 08:39:43 +00001498 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001499 return PHY_ERROR;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001500
1501 return 0;
1502}
1503
1504static void nv_start_rx(struct net_device *dev)
1505{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001506 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001507 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001508 u32 rx_ctrl = readl(base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001509
Linus Torvalds1da177e2005-04-16 15:20:36 -07001510 /* Already running? Stop it. */
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001511 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1512 rx_ctrl &= ~NVREG_RCVCTL_START;
1513 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001514 pci_push(base);
1515 }
1516 writel(np->linkspeed, base + NvRegLinkSpeed);
1517 pci_push(base);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001518 rx_ctrl |= NVREG_RCVCTL_START;
1519 if (np->mac_in_use)
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001520 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1521 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001522 pci_push(base);
1523}
1524
1525static void nv_stop_rx(struct net_device *dev)
1526{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001527 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001528 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001529 u32 rx_ctrl = readl(base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001530
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001531 if (!np->mac_in_use)
1532 rx_ctrl &= ~NVREG_RCVCTL_START;
1533 else
1534 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1535 writel(rx_ctrl, base + NvRegReceiverControl);
Joe Perches344d0dc2010-11-29 07:41:52 +00001536 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1537 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
Joe Perches1d397f32010-11-29 07:41:57 +00001538 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1539 __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001540
1541 udelay(NV_RXSTOP_DELAY2);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001542 if (!np->mac_in_use)
1543 writel(0, base + NvRegLinkSpeed);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001544}
1545
1546static void nv_start_tx(struct net_device *dev)
1547{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001548 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001549 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001550 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001551
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001552 tx_ctrl |= NVREG_XMITCTL_START;
1553 if (np->mac_in_use)
1554 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1555 writel(tx_ctrl, base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001556 pci_push(base);
1557}
1558
1559static void nv_stop_tx(struct net_device *dev)
1560{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001561 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001562 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001563 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001564
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001565 if (!np->mac_in_use)
1566 tx_ctrl &= ~NVREG_XMITCTL_START;
1567 else
1568 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1569 writel(tx_ctrl, base + NvRegTransmitterControl);
Joe Perches344d0dc2010-11-29 07:41:52 +00001570 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1571 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
Joe Perches1d397f32010-11-29 07:41:57 +00001572 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1573 __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001574
1575 udelay(NV_TXSTOP_DELAY2);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001576 if (!np->mac_in_use)
1577 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1578 base + NvRegTransmitPoll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001579}
1580
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001581static void nv_start_rxtx(struct net_device *dev)
1582{
1583 nv_start_rx(dev);
1584 nv_start_tx(dev);
1585}
1586
1587static void nv_stop_rxtx(struct net_device *dev)
1588{
1589 nv_stop_rx(dev);
1590 nv_stop_tx(dev);
1591}
1592
Linus Torvalds1da177e2005-04-16 15:20:36 -07001593static void nv_txrx_reset(struct net_device *dev)
1594{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001595 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001596 u8 __iomem *base = get_hwbase(dev);
1597
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001598 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001599 pci_push(base);
1600 udelay(NV_TXRX_RESET_DELAY);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001601 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001602 pci_push(base);
1603}
1604
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001605static void nv_mac_reset(struct net_device *dev)
1606{
1607 struct fe_priv *np = netdev_priv(dev);
1608 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001609 u32 temp1, temp2, temp3;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001610
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001611 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1612 pci_push(base);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001613
1614 /* save registers since they will be cleared on reset */
1615 temp1 = readl(base + NvRegMacAddrA);
1616 temp2 = readl(base + NvRegMacAddrB);
1617 temp3 = readl(base + NvRegTransmitPoll);
1618
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001619 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1620 pci_push(base);
1621 udelay(NV_MAC_RESET_DELAY);
1622 writel(0, base + NvRegMacReset);
1623 pci_push(base);
1624 udelay(NV_MAC_RESET_DELAY);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001625
1626 /* restore saved registers */
1627 writel(temp1, base + NvRegMacAddrA);
1628 writel(temp2, base + NvRegMacAddrB);
1629 writel(temp3, base + NvRegTransmitPoll);
1630
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001631 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1632 pci_push(base);
1633}
1634
Ayaz Abdulla57fff692007-01-23 12:27:00 -05001635static void nv_get_hw_stats(struct net_device *dev)
1636{
1637 struct fe_priv *np = netdev_priv(dev);
1638 u8 __iomem *base = get_hwbase(dev);
1639
1640 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1641 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1642 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1643 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1644 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1645 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1646 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1647 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1648 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1649 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1650 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1651 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1652 np->estats.rx_runt += readl(base + NvRegRxRunt);
1653 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1654 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1655 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1656 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1657 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1658 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1659 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1660 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1661 np->estats.rx_packets =
1662 np->estats.rx_unicast +
1663 np->estats.rx_multicast +
1664 np->estats.rx_broadcast;
1665 np->estats.rx_errors_total =
1666 np->estats.rx_crc_errors +
1667 np->estats.rx_over_errors +
1668 np->estats.rx_frame_error +
1669 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1670 np->estats.rx_late_collision +
1671 np->estats.rx_runt +
1672 np->estats.rx_frame_too_long;
1673 np->estats.tx_errors_total =
1674 np->estats.tx_late_collision +
1675 np->estats.tx_fifo_errors +
1676 np->estats.tx_carrier_errors +
1677 np->estats.tx_excess_deferral +
1678 np->estats.tx_retry_error;
1679
1680 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1681 np->estats.tx_deferral += readl(base + NvRegTxDef);
1682 np->estats.tx_packets += readl(base + NvRegTxFrame);
1683 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1684 np->estats.tx_pause += readl(base + NvRegTxPause);
1685 np->estats.rx_pause += readl(base + NvRegRxPause);
1686 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1687 }
Ayaz Abdulla9c662432008-08-06 12:11:42 -04001688
1689 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1690 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1691 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1692 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1693 }
Ayaz Abdulla57fff692007-01-23 12:27:00 -05001694}
1695
Linus Torvalds1da177e2005-04-16 15:20:36 -07001696/*
1697 * nv_get_stats: dev->get_stats function
1698 * Get latest stats value from the nic.
1699 * Called with read_lock(&dev_base_lock) held for read -
1700 * only synchronized against unregister_netdevice.
1701 */
1702static struct net_device_stats *nv_get_stats(struct net_device *dev)
1703{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001704 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001705
Ayaz Abdulla21828162007-01-23 12:27:21 -05001706 /* If the nic supports hw counters then retrieve latest values */
Ayaz Abdulla9c662432008-08-06 12:11:42 -04001707 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
Ayaz Abdulla21828162007-01-23 12:27:21 -05001708 nv_get_hw_stats(dev);
1709
1710 /* copy to net_device stats */
Jeff Garzik8148ff42007-10-16 20:56:09 -04001711 dev->stats.tx_bytes = np->estats.tx_bytes;
1712 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1713 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1714 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1715 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1716 dev->stats.rx_errors = np->estats.rx_errors_total;
1717 dev->stats.tx_errors = np->estats.tx_errors_total;
Ayaz Abdulla21828162007-01-23 12:27:21 -05001718 }
Jeff Garzik8148ff42007-10-16 20:56:09 -04001719
1720 return &dev->stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001721}
1722
1723/*
1724 * nv_alloc_rx: fill rx ring entries.
1725 * Return 1 if the allocations for the skbs failed and the
1726 * rx engine is without Available descriptors
1727 */
1728static int nv_alloc_rx(struct net_device *dev)
1729{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001730 struct fe_priv *np = netdev_priv(dev);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001731 struct ring_desc *less_rx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001732
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001733 less_rx = np->get_rx.orig;
1734 if (less_rx-- == np->first_rx.orig)
1735 less_rx = np->last_rx.orig;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001736
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001737 while (np->put_rx.orig != less_rx) {
1738 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001739 if (skb) {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001740 np->put_rx_ctx->skb = skb;
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001741 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1742 skb->data,
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001743 skb_tailroom(skb),
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001744 PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001745 np->put_rx_ctx->dma_len = skb_tailroom(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001746 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1747 wmb();
1748 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001749 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001750 np->put_rx.orig = np->first_rx.orig;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001751 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001752 np->put_rx_ctx = np->first_rx_ctx;
Szymon Janc78aea4f2010-11-27 08:39:43 +00001753 } else
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001754 return 1;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001755 }
1756 return 0;
1757}
1758
1759static int nv_alloc_rx_optimized(struct net_device *dev)
1760{
1761 struct fe_priv *np = netdev_priv(dev);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001762 struct ring_desc_ex *less_rx;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001763
1764 less_rx = np->get_rx.ex;
1765 if (less_rx-- == np->first_rx.ex)
1766 less_rx = np->last_rx.ex;
1767
1768 while (np->put_rx.ex != less_rx) {
1769 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1770 if (skb) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001771 np->put_rx_ctx->skb = skb;
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001772 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1773 skb->data,
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001774 skb_tailroom(skb),
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001775 PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001776 np->put_rx_ctx->dma_len = skb_tailroom(skb);
Al Viro5bb7ea22007-12-09 16:06:41 +00001777 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1778 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001779 wmb();
1780 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001781 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001782 np->put_rx.ex = np->first_rx.ex;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001783 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001784 np->put_rx_ctx = np->first_rx_ctx;
Szymon Janc78aea4f2010-11-27 08:39:43 +00001785 } else
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001786 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001787 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001788 return 0;
1789}
1790
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001791/* If rx bufs are exhausted called after 50ms to attempt to refresh */
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001792static void nv_do_rx_refill(unsigned long data)
1793{
1794 struct net_device *dev = (struct net_device *) data;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001795 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001796
1797 /* Just reschedule NAPI rx processing */
Ben Hutchings288379f2009-01-19 16:43:59 -08001798 napi_schedule(&np->napi);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001799}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001800
Jeff Garzikf3b197a2006-05-26 21:39:03 -04001801static void nv_init_rx(struct net_device *dev)
Manfred Sprauld81c0982005-07-31 18:20:30 +02001802{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001803 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02001804 int i;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001805
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001806 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001807
1808 if (!nv_optimized(np))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001809 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1810 else
1811 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1812 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1813 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
Manfred Sprauld81c0982005-07-31 18:20:30 +02001814
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001815 for (i = 0; i < np->rx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001816 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001817 np->rx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001818 np->rx_ring.orig[i].buf = 0;
1819 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001820 np->rx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001821 np->rx_ring.ex[i].txvlan = 0;
1822 np->rx_ring.ex[i].bufhigh = 0;
1823 np->rx_ring.ex[i].buflow = 0;
1824 }
1825 np->rx_skb[i].skb = NULL;
1826 np->rx_skb[i].dma = 0;
1827 }
Manfred Sprauld81c0982005-07-31 18:20:30 +02001828}
1829
1830static void nv_init_tx(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001831{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001832 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001833 int i;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001834
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001835 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001836
1837 if (!nv_optimized(np))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001838 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1839 else
1840 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1841 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1842 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001843 np->tx_pkts_in_progress = 0;
1844 np->tx_change_owner = NULL;
1845 np->tx_end_flip = NULL;
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00001846 np->tx_stop = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001847
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001848 for (i = 0; i < np->tx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001849 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001850 np->tx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001851 np->tx_ring.orig[i].buf = 0;
1852 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001853 np->tx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001854 np->tx_ring.ex[i].txvlan = 0;
1855 np->tx_ring.ex[i].bufhigh = 0;
1856 np->tx_ring.ex[i].buflow = 0;
1857 }
1858 np->tx_skb[i].skb = NULL;
1859 np->tx_skb[i].dma = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001860 np->tx_skb[i].dma_len = 0;
Eric Dumazet73a37072009-06-17 21:17:59 +00001861 np->tx_skb[i].dma_single = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001862 np->tx_skb[i].first_tx_desc = NULL;
1863 np->tx_skb[i].next_tx_ctx = NULL;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001864 }
Manfred Sprauld81c0982005-07-31 18:20:30 +02001865}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001866
Manfred Sprauld81c0982005-07-31 18:20:30 +02001867static int nv_init_ring(struct net_device *dev)
1868{
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001869 struct fe_priv *np = netdev_priv(dev);
1870
Manfred Sprauld81c0982005-07-31 18:20:30 +02001871 nv_init_tx(dev);
1872 nv_init_rx(dev);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001873
1874 if (!nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001875 return nv_alloc_rx(dev);
1876 else
1877 return nv_alloc_rx_optimized(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001878}
1879
Eric Dumazet73a37072009-06-17 21:17:59 +00001880static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001881{
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001882 if (tx_skb->dma) {
Eric Dumazet73a37072009-06-17 21:17:59 +00001883 if (tx_skb->dma_single)
1884 pci_unmap_single(np->pci_dev, tx_skb->dma,
1885 tx_skb->dma_len,
1886 PCI_DMA_TODEVICE);
1887 else
1888 pci_unmap_page(np->pci_dev, tx_skb->dma,
1889 tx_skb->dma_len,
1890 PCI_DMA_TODEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001891 tx_skb->dma = 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001892 }
Eric Dumazet73a37072009-06-17 21:17:59 +00001893}
1894
1895static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1896{
1897 nv_unmap_txskb(np, tx_skb);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001898 if (tx_skb->skb) {
1899 dev_kfree_skb_any(tx_skb->skb);
1900 tx_skb->skb = NULL;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001901 return 1;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001902 }
Eric Dumazet73a37072009-06-17 21:17:59 +00001903 return 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001904}
1905
Linus Torvalds1da177e2005-04-16 15:20:36 -07001906static void nv_drain_tx(struct net_device *dev)
1907{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001908 struct fe_priv *np = netdev_priv(dev);
1909 unsigned int i;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04001910
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001911 for (i = 0; i < np->tx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001912 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001913 np->tx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001914 np->tx_ring.orig[i].buf = 0;
1915 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001916 np->tx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001917 np->tx_ring.ex[i].txvlan = 0;
1918 np->tx_ring.ex[i].bufhigh = 0;
1919 np->tx_ring.ex[i].buflow = 0;
1920 }
Eric Dumazet73a37072009-06-17 21:17:59 +00001921 if (nv_release_txskb(np, &np->tx_skb[i]))
Jeff Garzik8148ff42007-10-16 20:56:09 -04001922 dev->stats.tx_dropped++;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001923 np->tx_skb[i].dma = 0;
1924 np->tx_skb[i].dma_len = 0;
Eric Dumazet73a37072009-06-17 21:17:59 +00001925 np->tx_skb[i].dma_single = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001926 np->tx_skb[i].first_tx_desc = NULL;
1927 np->tx_skb[i].next_tx_ctx = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001928 }
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001929 np->tx_pkts_in_progress = 0;
1930 np->tx_change_owner = NULL;
1931 np->tx_end_flip = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001932}
1933
1934static void nv_drain_rx(struct net_device *dev)
1935{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001936 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001937 int i;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001938
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001939 for (i = 0; i < np->rx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001940 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001941 np->rx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001942 np->rx_ring.orig[i].buf = 0;
1943 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001944 np->rx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001945 np->rx_ring.ex[i].txvlan = 0;
1946 np->rx_ring.ex[i].bufhigh = 0;
1947 np->rx_ring.ex[i].buflow = 0;
1948 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001949 wmb();
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001950 if (np->rx_skb[i].skb) {
1951 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001952 (skb_end_pointer(np->rx_skb[i].skb) -
1953 np->rx_skb[i].skb->data),
1954 PCI_DMA_FROMDEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001955 dev_kfree_skb(np->rx_skb[i].skb);
1956 np->rx_skb[i].skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001957 }
1958 }
1959}
1960
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001961static void nv_drain_rxtx(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001962{
1963 nv_drain_tx(dev);
1964 nv_drain_rx(dev);
1965}
1966
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001967static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1968{
1969 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1970}
1971
Ayaz Abdullaa4336862008-04-18 13:50:43 -07001972static void nv_legacybackoff_reseed(struct net_device *dev)
1973{
1974 u8 __iomem *base = get_hwbase(dev);
1975 u32 reg;
1976 u32 low;
1977 int tx_status = 0;
1978
1979 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1980 get_random_bytes(&low, sizeof(low));
1981 reg |= low & NVREG_SLOTTIME_MASK;
1982
1983 /* Need to stop tx before change takes effect.
1984 * Caller has already gained np->lock.
1985 */
1986 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1987 if (tx_status)
1988 nv_stop_tx(dev);
1989 nv_stop_rx(dev);
1990 writel(reg, base + NvRegSlotTime);
1991 if (tx_status)
1992 nv_start_tx(dev);
1993 nv_start_rx(dev);
1994}
1995
1996/* Gear Backoff Seeds */
1997#define BACKOFF_SEEDSET_ROWS 8
1998#define BACKOFF_SEEDSET_LFSRS 15
1999
2000/* Known Good seed sets */
2001static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002002 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2003 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2004 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2005 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2006 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2007 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2008 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2009 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002010
2011static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002012 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2013 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2014 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2015 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2016 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2017 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2018 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2019 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002020
2021static void nv_gear_backoff_reseed(struct net_device *dev)
2022{
2023 u8 __iomem *base = get_hwbase(dev);
2024 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2025 u32 temp, seedset, combinedSeed;
2026 int i;
2027
2028 /* Setup seed for free running LFSR */
2029 /* We are going to read the time stamp counter 3 times
2030 and swizzle bits around to increase randomness */
2031 get_random_bytes(&miniseed1, sizeof(miniseed1));
2032 miniseed1 &= 0x0fff;
2033 if (miniseed1 == 0)
2034 miniseed1 = 0xabc;
2035
2036 get_random_bytes(&miniseed2, sizeof(miniseed2));
2037 miniseed2 &= 0x0fff;
2038 if (miniseed2 == 0)
2039 miniseed2 = 0xabc;
2040 miniseed2_reversed =
2041 ((miniseed2 & 0xF00) >> 8) |
2042 (miniseed2 & 0x0F0) |
2043 ((miniseed2 & 0x00F) << 8);
2044
2045 get_random_bytes(&miniseed3, sizeof(miniseed3));
2046 miniseed3 &= 0x0fff;
2047 if (miniseed3 == 0)
2048 miniseed3 = 0xabc;
2049 miniseed3_reversed =
2050 ((miniseed3 & 0xF00) >> 8) |
2051 (miniseed3 & 0x0F0) |
2052 ((miniseed3 & 0x00F) << 8);
2053
2054 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2055 (miniseed2 ^ miniseed3_reversed);
2056
2057 /* Seeds can not be zero */
2058 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2059 combinedSeed |= 0x08;
2060 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2061 combinedSeed |= 0x8000;
2062
2063 /* No need to disable tx here */
2064 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2065 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2066 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002067 writel(temp, base + NvRegBackOffControl);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002068
Szymon Janc78aea4f2010-11-27 08:39:43 +00002069 /* Setup seeds for all gear LFSRs. */
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002070 get_random_bytes(&seedset, sizeof(seedset));
2071 seedset = seedset % BACKOFF_SEEDSET_ROWS;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002072 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002073 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2074 temp |= main_seedset[seedset][i-1] & 0x3ff;
2075 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2076 writel(temp, base + NvRegBackOffControl);
2077 }
2078}
2079
Linus Torvalds1da177e2005-04-16 15:20:36 -07002080/*
2081 * nv_start_xmit: dev->hard_start_xmit function
Herbert Xu932ff272006-06-09 12:20:56 -07002082 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002083 */
Stephen Hemminger613573252009-08-31 19:50:58 +00002084static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002085{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002086 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002087 u32 tx_flags = 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002088 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2089 unsigned int fragments = skb_shinfo(skb)->nr_frags;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002090 unsigned int i;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002091 u32 offset = 0;
2092 u32 bcnt;
Eric Dumazete743d312010-04-14 15:59:40 -07002093 u32 size = skb_headlen(skb);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002094 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002095 u32 empty_slots;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002096 struct ring_desc *put_tx;
2097 struct ring_desc *start_tx;
2098 struct ring_desc *prev_tx;
2099 struct nv_skb_map *prev_tx_ctx;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002100 unsigned long flags;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002101
2102 /* add fragments to entries count */
2103 for (i = 0; i < fragments; i++) {
2104 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2105 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2106 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002107
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002108 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002109 empty_slots = nv_get_empty_tx_slots(np);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002110 if (unlikely(empty_slots <= entries)) {
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002111 netif_stop_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002112 np->tx_stop = 1;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002113 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002114 return NETDEV_TX_BUSY;
2115 }
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002116 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002117
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002118 start_tx = put_tx = np->put_tx.orig;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002119
Ayaz Abdullafa454592006-01-05 22:45:45 -08002120 /* setup the header buffer */
2121 do {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002122 prev_tx = put_tx;
2123 prev_tx_ctx = np->put_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002124 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002125 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
Ayaz Abdullafa454592006-01-05 22:45:45 -08002126 PCI_DMA_TODEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002127 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002128 np->put_tx_ctx->dma_single = 1;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002129 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2130 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002131
Ayaz Abdullafa454592006-01-05 22:45:45 -08002132 tx_flags = np->tx_flags;
2133 offset += bcnt;
2134 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002135 if (unlikely(put_tx++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002136 put_tx = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002137 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002138 np->put_tx_ctx = np->first_tx_ctx;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002139 } while (size);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002140
2141 /* setup the fragments */
2142 for (i = 0; i < fragments; i++) {
2143 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2144 u32 size = frag->size;
2145 offset = 0;
2146
2147 do {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002148 prev_tx = put_tx;
2149 prev_tx_ctx = np->put_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002150 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002151 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2152 PCI_DMA_TODEVICE);
2153 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002154 np->put_tx_ctx->dma_single = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002155 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2156 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002157
Ayaz Abdullafa454592006-01-05 22:45:45 -08002158 offset += bcnt;
2159 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002160 if (unlikely(put_tx++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002161 put_tx = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002162 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002163 np->put_tx_ctx = np->first_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002164 } while (size);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002165 }
2166
Ayaz Abdullafa454592006-01-05 22:45:45 -08002167 /* set last fragment flag */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002168 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002169
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002170 /* save skb in this slot's context area */
2171 prev_tx_ctx->skb = skb;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002172
Herbert Xu89114af2006-07-08 13:34:32 -07002173 if (skb_is_gso(skb))
Herbert Xu79671682006-06-22 02:40:14 -07002174 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
Manfred Spraulee733622005-07-31 18:32:26 +02002175 else
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01002176 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
Patrick McHardy84fa7932006-08-29 16:44:56 -07002177 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002178
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002179 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla164a86e2007-01-09 13:30:10 -05002180
Ayaz Abdullafa454592006-01-05 22:45:45 -08002181 /* set tx flags */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002182 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2183 np->put_tx.orig = put_tx;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002184
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002185 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002186
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002187 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002188 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002189}
2190
Stephen Hemminger613573252009-08-31 19:50:58 +00002191static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2192 struct net_device *dev)
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002193{
2194 struct fe_priv *np = netdev_priv(dev);
2195 u32 tx_flags = 0;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002196 u32 tx_flags_extra;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002197 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2198 unsigned int i;
2199 u32 offset = 0;
2200 u32 bcnt;
Eric Dumazete743d312010-04-14 15:59:40 -07002201 u32 size = skb_headlen(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002202 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2203 u32 empty_slots;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002204 struct ring_desc_ex *put_tx;
2205 struct ring_desc_ex *start_tx;
2206 struct ring_desc_ex *prev_tx;
2207 struct nv_skb_map *prev_tx_ctx;
2208 struct nv_skb_map *start_tx_ctx;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002209 unsigned long flags;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002210
2211 /* add fragments to entries count */
2212 for (i = 0; i < fragments; i++) {
2213 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2214 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2215 }
2216
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002217 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002218 empty_slots = nv_get_empty_tx_slots(np);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002219 if (unlikely(empty_slots <= entries)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002220 netif_stop_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002221 np->tx_stop = 1;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002222 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002223 return NETDEV_TX_BUSY;
2224 }
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002225 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002226
2227 start_tx = put_tx = np->put_tx.ex;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002228 start_tx_ctx = np->put_tx_ctx;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002229
2230 /* setup the header buffer */
2231 do {
2232 prev_tx = put_tx;
2233 prev_tx_ctx = np->put_tx_ctx;
2234 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2235 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2236 PCI_DMA_TODEVICE);
2237 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002238 np->put_tx_ctx->dma_single = 1;
Al Viro5bb7ea22007-12-09 16:06:41 +00002239 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2240 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002241 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002242
2243 tx_flags = NV_TX2_VALID;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002244 offset += bcnt;
2245 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002246 if (unlikely(put_tx++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002247 put_tx = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002248 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002249 np->put_tx_ctx = np->first_tx_ctx;
2250 } while (size);
2251
2252 /* setup the fragments */
2253 for (i = 0; i < fragments; i++) {
2254 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2255 u32 size = frag->size;
2256 offset = 0;
2257
2258 do {
2259 prev_tx = put_tx;
2260 prev_tx_ctx = np->put_tx_ctx;
2261 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2262 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2263 PCI_DMA_TODEVICE);
2264 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002265 np->put_tx_ctx->dma_single = 0;
Al Viro5bb7ea22007-12-09 16:06:41 +00002266 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2267 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002268 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002269
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002270 offset += bcnt;
2271 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002272 if (unlikely(put_tx++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002273 put_tx = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002274 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002275 np->put_tx_ctx = np->first_tx_ctx;
2276 } while (size);
2277 }
2278
2279 /* set last fragment flag */
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002280 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002281
2282 /* save skb in this slot's context area */
2283 prev_tx_ctx->skb = skb;
2284
2285 if (skb_is_gso(skb))
2286 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2287 else
2288 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2289 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2290
2291 /* vlan tag */
Jesse Grosseab6d182010-10-20 13:56:03 +00002292 if (vlan_tx_tag_present(skb))
2293 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2294 vlan_tx_tag_get(skb));
2295 else
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002296 start_tx->txvlan = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002297
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002298 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002299
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002300 if (np->tx_limit) {
2301 /* Limit the number of outstanding tx. Setup all fragments, but
2302 * do not set the VALID bit on the first descriptor. Save a pointer
2303 * to that descriptor and also for next skb_map element.
2304 */
2305
2306 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2307 if (!np->tx_change_owner)
2308 np->tx_change_owner = start_tx_ctx;
2309
2310 /* remove VALID bit */
2311 tx_flags &= ~NV_TX2_VALID;
2312 start_tx_ctx->first_tx_desc = start_tx;
2313 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2314 np->tx_end_flip = np->put_tx_ctx;
2315 } else {
2316 np->tx_pkts_in_progress++;
2317 }
2318 }
2319
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002320 /* set tx flags */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002321 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2322 np->put_tx.ex = put_tx;
2323
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002324 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002325
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002326 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002327 return NETDEV_TX_OK;
2328}
2329
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002330static inline void nv_tx_flip_ownership(struct net_device *dev)
2331{
2332 struct fe_priv *np = netdev_priv(dev);
2333
2334 np->tx_pkts_in_progress--;
2335 if (np->tx_change_owner) {
Al Viro30ecce92008-03-26 05:57:12 +00002336 np->tx_change_owner->first_tx_desc->flaglen |=
2337 cpu_to_le32(NV_TX2_VALID);
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002338 np->tx_pkts_in_progress++;
2339
2340 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2341 if (np->tx_change_owner == np->tx_end_flip)
2342 np->tx_change_owner = NULL;
2343
2344 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2345 }
2346}
2347
Linus Torvalds1da177e2005-04-16 15:20:36 -07002348/*
2349 * nv_tx_done: check for completed packets, release the skbs.
2350 *
2351 * Caller must own np->lock.
2352 */
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002353static int nv_tx_done(struct net_device *dev, int limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002354{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002355 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002356 u32 flags;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002357 int tx_work = 0;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002358 struct ring_desc *orig_get_tx = np->get_tx.orig;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002359
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002360 while ((np->get_tx.orig != np->put_tx.orig) &&
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002361 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2362 (tx_work < limit)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002363
Eric Dumazet73a37072009-06-17 21:17:59 +00002364 nv_unmap_txskb(np, np->get_tx_ctx);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002365
Linus Torvalds1da177e2005-04-16 15:20:36 -07002366 if (np->desc_ver == DESC_VER_1) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002367 if (flags & NV_TX_LASTPACKET) {
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002368 if (flags & NV_TX_ERROR) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002369 if (flags & NV_TX_UNDERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002370 dev->stats.tx_fifo_errors++;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002371 if (flags & NV_TX_CARRIERLOST)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002372 dev->stats.tx_carrier_errors++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002373 if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2374 nv_legacybackoff_reseed(dev);
Jeff Garzik8148ff42007-10-16 20:56:09 -04002375 dev->stats.tx_errors++;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002376 } else {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002377 dev->stats.tx_packets++;
2378 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002379 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002380 dev_kfree_skb_any(np->get_tx_ctx->skb);
2381 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002382 tx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002383 }
2384 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002385 if (flags & NV_TX2_LASTPACKET) {
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002386 if (flags & NV_TX2_ERROR) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002387 if (flags & NV_TX2_UNDERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002388 dev->stats.tx_fifo_errors++;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002389 if (flags & NV_TX2_CARRIERLOST)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002390 dev->stats.tx_carrier_errors++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002391 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2392 nv_legacybackoff_reseed(dev);
Jeff Garzik8148ff42007-10-16 20:56:09 -04002393 dev->stats.tx_errors++;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002394 } else {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002395 dev->stats.tx_packets++;
2396 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002397 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002398 dev_kfree_skb_any(np->get_tx_ctx->skb);
2399 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002400 tx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002401 }
2402 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002403 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002404 np->get_tx.orig = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002405 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002406 np->get_tx_ctx = np->first_tx_ctx;
2407 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002408 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002409 np->tx_stop = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002410 netif_wake_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002411 }
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002412 return tx_work;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002413}
2414
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002415static int nv_tx_done_optimized(struct net_device *dev, int limit)
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002416{
2417 struct fe_priv *np = netdev_priv(dev);
2418 u32 flags;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002419 int tx_work = 0;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002420 struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002421
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002422 while ((np->get_tx.ex != np->put_tx.ex) &&
Julia Lawall217d32d2010-07-05 22:15:47 -07002423 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002424 (tx_work < limit)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002425
Eric Dumazet73a37072009-06-17 21:17:59 +00002426 nv_unmap_txskb(np, np->get_tx_ctx);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002427
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002428 if (flags & NV_TX2_LASTPACKET) {
Ayaz Abdulla21828162007-01-23 12:27:21 -05002429 if (!(flags & NV_TX2_ERROR))
Jeff Garzik8148ff42007-10-16 20:56:09 -04002430 dev->stats.tx_packets++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002431 else {
2432 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2433 if (np->driver_data & DEV_HAS_GEAR_MODE)
2434 nv_gear_backoff_reseed(dev);
2435 else
2436 nv_legacybackoff_reseed(dev);
2437 }
2438 }
2439
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002440 dev_kfree_skb_any(np->get_tx_ctx->skb);
2441 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002442 tx_work++;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002443
Szymon Janc78aea4f2010-11-27 08:39:43 +00002444 if (np->tx_limit)
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002445 nv_tx_flip_ownership(dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002446 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002447 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002448 np->get_tx.ex = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002449 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002450 np->get_tx_ctx = np->first_tx_ctx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002451 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002452 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002453 np->tx_stop = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002454 netif_wake_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002455 }
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002456 return tx_work;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002457}
2458
2459/*
2460 * nv_tx_timeout: dev->tx_timeout function
Herbert Xu932ff272006-06-09 12:20:56 -07002461 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002462 */
2463static void nv_tx_timeout(struct net_device *dev)
2464{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002465 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002466 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05002467 u32 status;
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002468 union ring_type put_tx;
2469 int saved_tx_limit;
Joe Perches294a5542010-11-29 07:41:56 +00002470 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002471
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05002472 if (np->msi_flags & NV_MSI_X_ENABLED)
2473 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2474 else
2475 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2476
Joe Perches1d397f32010-11-29 07:41:57 +00002477 netdev_info(dev, "Got tx_timeout. irq: %08x\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002478
Joe Perches1d397f32010-11-29 07:41:57 +00002479 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2480 netdev_info(dev, "Dumping tx registers\n");
Joe Perches294a5542010-11-29 07:41:56 +00002481 for (i = 0; i <= np->register_size; i += 32) {
Joe Perches1d397f32010-11-29 07:41:57 +00002482 netdev_info(dev,
2483 "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2484 i,
2485 readl(base + i + 0), readl(base + i + 4),
2486 readl(base + i + 8), readl(base + i + 12),
2487 readl(base + i + 16), readl(base + i + 20),
2488 readl(base + i + 24), readl(base + i + 28));
Joe Perches294a5542010-11-29 07:41:56 +00002489 }
Joe Perches1d397f32010-11-29 07:41:57 +00002490 netdev_info(dev, "Dumping tx ring\n");
Joe Perches294a5542010-11-29 07:41:56 +00002491 for (i = 0; i < np->tx_ring_size; i += 4) {
2492 if (!nv_optimized(np)) {
Joe Perches1d397f32010-11-29 07:41:57 +00002493 netdev_info(dev,
2494 "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2495 i,
2496 le32_to_cpu(np->tx_ring.orig[i].buf),
2497 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2498 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2499 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2500 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2501 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2502 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2503 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
Joe Perches294a5542010-11-29 07:41:56 +00002504 } else {
Joe Perches1d397f32010-11-29 07:41:57 +00002505 netdev_info(dev,
2506 "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2507 i,
2508 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2509 le32_to_cpu(np->tx_ring.ex[i].buflow),
2510 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2511 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2512 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2513 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2514 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2515 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2516 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2517 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2518 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2519 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
Manfred Spraulc2dba062005-07-31 18:29:47 +02002520 }
2521 }
2522
Linus Torvalds1da177e2005-04-16 15:20:36 -07002523 spin_lock_irq(&np->lock);
2524
2525 /* 1) stop tx engine */
2526 nv_stop_tx(dev);
2527
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002528 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2529 saved_tx_limit = np->tx_limit;
2530 np->tx_limit = 0; /* prevent giving HW any limited pkts */
2531 np->tx_stop = 0; /* prevent waking tx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002532 if (!nv_optimized(np))
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002533 nv_tx_done(dev, np->tx_ring_size);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002534 else
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05002535 nv_tx_done_optimized(dev, np->tx_ring_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002536
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002537 /* save current HW position */
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002538 if (np->tx_change_owner)
2539 put_tx.ex = np->tx_change_owner->first_tx_desc;
2540 else
2541 put_tx = np->put_tx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002542
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002543 /* 3) clear all tx state */
2544 nv_drain_tx(dev);
2545 nv_init_tx(dev);
Ayaz Abdulla3ba4d092007-03-23 05:50:02 -05002546
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002547 /* 4) restore state to current HW position */
2548 np->get_tx = np->put_tx = put_tx;
2549 np->tx_limit = saved_tx_limit;
2550
2551 /* 5) restart tx engine */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002552 nv_start_tx(dev);
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002553 netif_wake_queue(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002554 spin_unlock_irq(&np->lock);
2555}
2556
Manfred Spraul22c6d142005-04-19 21:17:09 +02002557/*
2558 * Called when the nic notices a mismatch between the actual data len on the
2559 * wire and the len indicated in the 802 header
2560 */
2561static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2562{
2563 int hdrlen; /* length of the 802 header */
2564 int protolen; /* length as stored in the proto field */
2565
2566 /* 1) calculate len according to header */
Szymon Janc78aea4f2010-11-27 08:39:43 +00002567 if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2568 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002569 hdrlen = VLAN_HLEN;
2570 } else {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002571 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002572 hdrlen = ETH_HLEN;
2573 }
Manfred Spraul22c6d142005-04-19 21:17:09 +02002574 if (protolen > ETH_DATA_LEN)
2575 return datalen; /* Value in proto field not a len, no checks possible */
2576
2577 protolen += hdrlen;
2578 /* consistency checks: */
2579 if (datalen > ETH_ZLEN) {
2580 if (datalen >= protolen) {
2581 /* more data on wire than in 802 header, trim of
2582 * additional data.
2583 */
Manfred Spraul22c6d142005-04-19 21:17:09 +02002584 return protolen;
2585 } else {
2586 /* less data on wire than mentioned in header.
2587 * Discard the packet.
2588 */
Manfred Spraul22c6d142005-04-19 21:17:09 +02002589 return -1;
2590 }
2591 } else {
2592 /* short packet. Accept only if 802 values are also short */
2593 if (protolen > ETH_ZLEN) {
Manfred Spraul22c6d142005-04-19 21:17:09 +02002594 return -1;
2595 }
Manfred Spraul22c6d142005-04-19 21:17:09 +02002596 return datalen;
2597 }
2598}
2599
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002600static int nv_rx_process(struct net_device *dev, int limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002601{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002602 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002603 u32 flags;
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002604 int rx_work = 0;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002605 struct sk_buff *skb;
2606 int len;
Ayaz Abdullaee407b02006-02-04 13:13:17 -05002607
Szymon Janc78aea4f2010-11-27 08:39:43 +00002608 while ((np->get_rx.orig != np->put_rx.orig) &&
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002609 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002610 (rx_work < limit)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002611
Linus Torvalds1da177e2005-04-16 15:20:36 -07002612 /*
2613 * the packet is for us - immediately tear down the pci mapping.
2614 * TODO: check if a prefetch of the first cacheline improves
2615 * the performance.
2616 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002617 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2618 np->get_rx_ctx->dma_len,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002619 PCI_DMA_FROMDEVICE);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002620 skb = np->get_rx_ctx->skb;
2621 np->get_rx_ctx->skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002622
Linus Torvalds1da177e2005-04-16 15:20:36 -07002623 /* look at what we actually got: */
2624 if (np->desc_ver == DESC_VER_1) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002625 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2626 len = flags & LEN_MASK_V1;
2627 if (unlikely(flags & NV_RX_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002628 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002629 len = nv_getlen(dev, skb->data, len);
2630 if (len < 0) {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002631 dev->stats.rx_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002632 dev_kfree_skb(skb);
2633 goto next_pkt;
2634 }
2635 }
2636 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002637 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002638 if (flags & NV_RX_SUBSTRACT1)
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002639 len--;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002640 }
2641 /* the rest are hard errors */
2642 else {
2643 if (flags & NV_RX_MISSEDFRAME)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002644 dev->stats.rx_missed_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002645 if (flags & NV_RX_CRCERR)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002646 dev->stats.rx_crc_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002647 if (flags & NV_RX_OVERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002648 dev->stats.rx_over_errors++;
2649 dev->stats.rx_errors++;
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002650 dev_kfree_skb(skb);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05002651 goto next_pkt;
2652 }
2653 }
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002654 } else {
2655 dev_kfree_skb(skb);
2656 goto next_pkt;
Manfred Spraul22c6d142005-04-19 21:17:09 +02002657 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002658 } else {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002659 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2660 len = flags & LEN_MASK_V2;
2661 if (unlikely(flags & NV_RX2_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002662 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002663 len = nv_getlen(dev, skb->data, len);
2664 if (len < 0) {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002665 dev->stats.rx_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002666 dev_kfree_skb(skb);
2667 goto next_pkt;
2668 }
2669 }
2670 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002671 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002672 if (flags & NV_RX2_SUBSTRACT1)
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002673 len--;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002674 }
2675 /* the rest are hard errors */
2676 else {
2677 if (flags & NV_RX2_CRCERR)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002678 dev->stats.rx_crc_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002679 if (flags & NV_RX2_OVERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002680 dev->stats.rx_over_errors++;
2681 dev->stats.rx_errors++;
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002682 dev_kfree_skb(skb);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05002683 goto next_pkt;
2684 }
2685 }
Ayaz Abdullabfaffe82008-01-13 16:02:55 -05002686 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2687 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002688 skb->ip_summed = CHECKSUM_UNNECESSARY;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002689 } else {
2690 dev_kfree_skb(skb);
2691 goto next_pkt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002692 }
2693 }
2694 /* got a valid packet - forward it to the network core */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002695 skb_put(skb, len);
2696 skb->protocol = eth_type_trans(skb, dev);
Tom Herbert53f224c2010-05-03 19:08:45 +00002697 napi_gro_receive(&np->napi, skb);
Jeff Garzik8148ff42007-10-16 20:56:09 -04002698 dev->stats.rx_packets++;
2699 dev->stats.rx_bytes += len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002700next_pkt:
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002701 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002702 np->get_rx.orig = np->first_rx.orig;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002703 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002704 np->get_rx_ctx = np->first_rx_ctx;
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002705
2706 rx_work++;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002707 }
2708
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002709 return rx_work;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002710}
2711
2712static int nv_rx_process_optimized(struct net_device *dev, int limit)
2713{
2714 struct fe_priv *np = netdev_priv(dev);
2715 u32 flags;
2716 u32 vlanflags = 0;
Ingo Molnarc1b71512007-10-17 12:18:23 +02002717 int rx_work = 0;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002718 struct sk_buff *skb;
2719 int len;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002720
Szymon Janc78aea4f2010-11-27 08:39:43 +00002721 while ((np->get_rx.ex != np->put_rx.ex) &&
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002722 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
Ingo Molnarc1b71512007-10-17 12:18:23 +02002723 (rx_work < limit)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002724
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002725 /*
2726 * the packet is for us - immediately tear down the pci mapping.
2727 * TODO: check if a prefetch of the first cacheline improves
2728 * the performance.
2729 */
2730 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2731 np->get_rx_ctx->dma_len,
2732 PCI_DMA_FROMDEVICE);
2733 skb = np->get_rx_ctx->skb;
2734 np->get_rx_ctx->skb = NULL;
2735
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002736 /* look at what we actually got: */
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002737 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2738 len = flags & LEN_MASK_V2;
2739 if (unlikely(flags & NV_RX2_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002740 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002741 len = nv_getlen(dev, skb->data, len);
2742 if (len < 0) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002743 dev_kfree_skb(skb);
2744 goto next_pkt;
2745 }
2746 }
2747 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002748 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002749 if (flags & NV_RX2_SUBSTRACT1)
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002750 len--;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002751 }
2752 /* the rest are hard errors */
2753 else {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002754 dev_kfree_skb(skb);
2755 goto next_pkt;
2756 }
2757 }
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002758
Ayaz Abdullabfaffe82008-01-13 16:02:55 -05002759 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2760 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002761 skb->ip_summed = CHECKSUM_UNNECESSARY;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002762
2763 /* got a valid packet - forward it to the network core */
2764 skb_put(skb, len);
2765 skb->protocol = eth_type_trans(skb, dev);
2766 prefetch(skb->data);
2767
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002768 if (likely(!np->vlangrp)) {
Tom Herbert53f224c2010-05-03 19:08:45 +00002769 napi_gro_receive(&np->napi, skb);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002770 } else {
2771 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2772 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
Tom Herbert53f224c2010-05-03 19:08:45 +00002773 vlan_gro_receive(&np->napi, np->vlangrp,
2774 vlanflags & NV_RX3_VLAN_TAG_MASK, skb);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002775 } else {
Tom Herbert53f224c2010-05-03 19:08:45 +00002776 napi_gro_receive(&np->napi, skb);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002777 }
2778 }
2779
Jeff Garzik8148ff42007-10-16 20:56:09 -04002780 dev->stats.rx_packets++;
2781 dev->stats.rx_bytes += len;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002782 } else {
2783 dev_kfree_skb(skb);
2784 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002785next_pkt:
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002786 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002787 np->get_rx.ex = np->first_rx.ex;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002788 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002789 np->get_rx_ctx = np->first_rx_ctx;
Ingo Molnarc1b71512007-10-17 12:18:23 +02002790
2791 rx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002792 }
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002793
Ingo Molnarc1b71512007-10-17 12:18:23 +02002794 return rx_work;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002795}
2796
Manfred Sprauld81c0982005-07-31 18:20:30 +02002797static void set_bufsize(struct net_device *dev)
2798{
2799 struct fe_priv *np = netdev_priv(dev);
2800
2801 if (dev->mtu <= ETH_DATA_LEN)
2802 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2803 else
2804 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2805}
2806
Linus Torvalds1da177e2005-04-16 15:20:36 -07002807/*
2808 * nv_change_mtu: dev->change_mtu function
2809 * Called with dev_base_lock held for read.
2810 */
2811static int nv_change_mtu(struct net_device *dev, int new_mtu)
2812{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002813 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002814 int old_mtu;
2815
2816 if (new_mtu < 64 || new_mtu > np->pkt_limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002817 return -EINVAL;
Manfred Sprauld81c0982005-07-31 18:20:30 +02002818
2819 old_mtu = dev->mtu;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002820 dev->mtu = new_mtu;
Manfred Sprauld81c0982005-07-31 18:20:30 +02002821
2822 /* return early if the buffer sizes will not change */
2823 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2824 return 0;
2825 if (old_mtu == new_mtu)
2826 return 0;
2827
2828 /* synchronized against open : rtnl_lock() held by caller */
2829 if (netif_running(dev)) {
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01002830 u8 __iomem *base = get_hwbase(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002831 /*
2832 * It seems that the nic preloads valid ring entries into an
2833 * internal buffer. The procedure for flushing everything is
2834 * guessed, there is probably a simpler approach.
2835 * Changing the MTU is a rare event, it shouldn't matter.
2836 */
Ayaz Abdulla84b39322006-05-20 14:59:48 -07002837 nv_disable_irq(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00002838 nv_napi_disable(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07002839 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07002840 netif_addr_lock(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002841 spin_lock(&np->lock);
2842 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002843 nv_stop_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002844 nv_txrx_reset(dev);
2845 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002846 nv_drain_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002847 /* reinit driver view of the rx queue */
Manfred Sprauld81c0982005-07-31 18:20:30 +02002848 set_bufsize(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04002849 if (nv_init_ring(dev)) {
Manfred Sprauld81c0982005-07-31 18:20:30 +02002850 if (!np->in_shutdown)
2851 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2852 }
2853 /* reinit nic view of the rx queue */
2854 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
Ayaz Abdulla0832b252006-02-04 13:13:26 -05002855 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00002856 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Manfred Sprauld81c0982005-07-31 18:20:30 +02002857 base + NvRegRingSizes);
2858 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002859 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002860 pci_push(base);
2861
2862 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002863 nv_start_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002864 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07002865 netif_addr_unlock(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07002866 netif_tx_unlock_bh(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00002867 nv_napi_enable(dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07002868 nv_enable_irq(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002869 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002870 return 0;
2871}
2872
Manfred Spraul72b31782005-07-31 18:33:34 +02002873static void nv_copy_mac_to_hw(struct net_device *dev)
2874{
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01002875 u8 __iomem *base = get_hwbase(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002876 u32 mac[2];
2877
2878 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2879 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2880 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2881
2882 writel(mac[0], base + NvRegMacAddrA);
2883 writel(mac[1], base + NvRegMacAddrB);
2884}
2885
2886/*
2887 * nv_set_mac_address: dev->set_mac_address function
2888 * Called with rtnl_lock() held.
2889 */
2890static int nv_set_mac_address(struct net_device *dev, void *addr)
2891{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002892 struct fe_priv *np = netdev_priv(dev);
Szymon Janc78aea4f2010-11-27 08:39:43 +00002893 struct sockaddr *macaddr = (struct sockaddr *)addr;
Manfred Spraul72b31782005-07-31 18:33:34 +02002894
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002895 if (!is_valid_ether_addr(macaddr->sa_data))
Manfred Spraul72b31782005-07-31 18:33:34 +02002896 return -EADDRNOTAVAIL;
2897
2898 /* synchronized against open : rtnl_lock() held by caller */
2899 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2900
2901 if (netif_running(dev)) {
Herbert Xu932ff272006-06-09 12:20:56 -07002902 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07002903 netif_addr_lock(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002904 spin_lock_irq(&np->lock);
2905
2906 /* stop rx engine */
2907 nv_stop_rx(dev);
2908
2909 /* set mac address */
2910 nv_copy_mac_to_hw(dev);
2911
2912 /* restart rx engine */
2913 nv_start_rx(dev);
2914 spin_unlock_irq(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07002915 netif_addr_unlock(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07002916 netif_tx_unlock_bh(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002917 } else {
2918 nv_copy_mac_to_hw(dev);
2919 }
2920 return 0;
2921}
2922
Linus Torvalds1da177e2005-04-16 15:20:36 -07002923/*
2924 * nv_set_multicast: dev->set_multicast function
Herbert Xu932ff272006-06-09 12:20:56 -07002925 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002926 */
2927static void nv_set_multicast(struct net_device *dev)
2928{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002929 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002930 u8 __iomem *base = get_hwbase(dev);
2931 u32 addr[2];
2932 u32 mask[2];
Ayaz Abdullab6d07732006-06-10 22:47:42 -04002933 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002934
2935 memset(addr, 0, sizeof(addr));
2936 memset(mask, 0, sizeof(mask));
2937
2938 if (dev->flags & IFF_PROMISC) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04002939 pff |= NVREG_PFF_PROMISC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002940 } else {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04002941 pff |= NVREG_PFF_MYADDR;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002942
Jiri Pirko48e2f182010-02-22 09:22:26 +00002943 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002944 u32 alwaysOff[2];
2945 u32 alwaysOn[2];
2946
2947 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2948 if (dev->flags & IFF_ALLMULTI) {
2949 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2950 } else {
Jiri Pirko22bedad32010-04-01 21:22:57 +00002951 struct netdev_hw_addr *ha;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002952
Jiri Pirko22bedad32010-04-01 21:22:57 +00002953 netdev_for_each_mc_addr(ha, dev) {
2954 unsigned char *addr = ha->addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002955 u32 a, b;
Jiri Pirko22bedad32010-04-01 21:22:57 +00002956
2957 a = le32_to_cpu(*(__le32 *) addr);
2958 b = le16_to_cpu(*(__le16 *) (&addr[4]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002959 alwaysOn[0] &= a;
2960 alwaysOff[0] &= ~a;
2961 alwaysOn[1] &= b;
2962 alwaysOff[1] &= ~b;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002963 }
2964 }
2965 addr[0] = alwaysOn[0];
2966 addr[1] = alwaysOn[1];
2967 mask[0] = alwaysOn[0] | alwaysOff[0];
2968 mask[1] = alwaysOn[1] | alwaysOff[1];
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05002969 } else {
2970 mask[0] = NVREG_MCASTMASKA_NONE;
2971 mask[1] = NVREG_MCASTMASKB_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002972 }
2973 }
2974 addr[0] |= NVREG_MCASTADDRA_FORCE;
2975 pff |= NVREG_PFF_ALWAYS;
2976 spin_lock_irq(&np->lock);
2977 nv_stop_rx(dev);
2978 writel(addr[0], base + NvRegMulticastAddrA);
2979 writel(addr[1], base + NvRegMulticastAddrB);
2980 writel(mask[0], base + NvRegMulticastMaskA);
2981 writel(mask[1], base + NvRegMulticastMaskB);
2982 writel(pff, base + NvRegPacketFilterFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002983 nv_start_rx(dev);
2984 spin_unlock_irq(&np->lock);
2985}
2986
Adrian Bunkc7985052006-06-22 12:03:29 +02002987static void nv_update_pause(struct net_device *dev, u32 pause_flags)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04002988{
2989 struct fe_priv *np = netdev_priv(dev);
2990 u8 __iomem *base = get_hwbase(dev);
2991
2992 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2993
2994 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2995 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2996 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2997 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2998 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2999 } else {
3000 writel(pff, base + NvRegPacketFilterFlags);
3001 }
3002 }
3003 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3004 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3005 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003006 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3007 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3008 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
Ayaz Abdulla9a33e882008-08-06 12:12:34 -04003009 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003010 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
Ayaz Abdulla9a33e882008-08-06 12:12:34 -04003011 /* limit the number of tx pause frames to a default of 8 */
3012 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3013 }
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003014 writel(pause_enable, base + NvRegTxPauseFrame);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003015 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3016 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3017 } else {
3018 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3019 writel(regmisc, base + NvRegMisc1);
3020 }
3021 }
3022}
3023
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003024/**
3025 * nv_update_linkspeed: Setup the MAC according to the link partner
3026 * @dev: Network device to be configured
3027 *
3028 * The function queries the PHY and checks if there is a link partner.
3029 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3030 * set to 10 MBit HD.
3031 *
3032 * The function returns 0 if there is no link partner and 1 if there is
3033 * a good link partner.
3034 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003035static int nv_update_linkspeed(struct net_device *dev)
3036{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003037 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003038 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003039 int adv = 0;
3040 int lpa = 0;
3041 int adv_lpa, adv_pause, lpa_pause;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003042 int newls = np->linkspeed;
3043 int newdup = np->duplex;
3044 int mii_status;
3045 int retval = 0;
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003046 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003047 u32 txrxFlags = 0;
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003048 u32 phy_exp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003049
3050 /* BMSR_LSTATUS is latched, read it twice:
3051 * we want the current value.
3052 */
3053 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3054 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3055
3056 if (!(mii_status & BMSR_LSTATUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003057 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3058 newdup = 0;
3059 retval = 0;
3060 goto set_speed;
3061 }
3062
3063 if (np->autoneg == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003064 if (np->fixed_mode & LPA_100FULL) {
3065 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3066 newdup = 1;
3067 } else if (np->fixed_mode & LPA_100HALF) {
3068 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3069 newdup = 0;
3070 } else if (np->fixed_mode & LPA_10FULL) {
3071 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3072 newdup = 1;
3073 } else {
3074 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3075 newdup = 0;
3076 }
3077 retval = 1;
3078 goto set_speed;
3079 }
3080 /* check auto negotiation is complete */
3081 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3082 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3083 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3084 newdup = 0;
3085 retval = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003086 goto set_speed;
3087 }
3088
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003089 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3090 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003091
Linus Torvalds1da177e2005-04-16 15:20:36 -07003092 retval = 1;
3093 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003094 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3095 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003096
3097 if ((control_1000 & ADVERTISE_1000FULL) &&
3098 (status_1000 & LPA_1000FULL)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003099 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3100 newdup = 1;
3101 goto set_speed;
3102 }
3103 }
3104
Linus Torvalds1da177e2005-04-16 15:20:36 -07003105 /* FIXME: handle parallel detection properly */
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003106 adv_lpa = lpa & adv;
3107 if (adv_lpa & LPA_100FULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003108 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3109 newdup = 1;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003110 } else if (adv_lpa & LPA_100HALF) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003111 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3112 newdup = 0;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003113 } else if (adv_lpa & LPA_10FULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003114 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3115 newdup = 1;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003116 } else if (adv_lpa & LPA_10HALF) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003117 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3118 newdup = 0;
3119 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003120 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3121 newdup = 0;
3122 }
3123
3124set_speed:
3125 if (np->duplex == newdup && np->linkspeed == newls)
3126 return retval;
3127
Linus Torvalds1da177e2005-04-16 15:20:36 -07003128 np->duplex = newdup;
3129 np->linkspeed = newls;
3130
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003131 /* The transmitter and receiver must be restarted for safe update */
3132 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3133 txrxFlags |= NV_RESTART_TX;
3134 nv_stop_tx(dev);
3135 }
3136 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3137 txrxFlags |= NV_RESTART_RX;
3138 nv_stop_rx(dev);
3139 }
3140
Linus Torvalds1da177e2005-04-16 15:20:36 -07003141 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003142 phyreg = readl(base + NvRegSlotTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003143 phyreg &= ~(0x3FF00);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003144 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3145 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3146 phyreg |= NVREG_SLOTTIME_10_100_FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003147 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003148 phyreg |= NVREG_SLOTTIME_1000_FULL;
3149 writel(phyreg, base + NvRegSlotTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003150 }
3151
3152 phyreg = readl(base + NvRegPhyInterface);
3153 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3154 if (np->duplex == 0)
3155 phyreg |= PHY_HALF;
3156 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3157 phyreg |= PHY_100;
3158 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3159 phyreg |= PHY_1000;
3160 writel(phyreg, base + NvRegPhyInterface);
3161
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003162 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003163 if (phyreg & PHY_RGMII) {
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003164 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003165 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003166 } else {
3167 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3168 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3169 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3170 else
3171 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3172 } else {
3173 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3174 }
3175 }
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003176 } else {
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003177 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3178 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3179 else
3180 txreg = NVREG_TX_DEFERRAL_DEFAULT;
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003181 }
3182 writel(txreg, base + NvRegTxDeferral);
3183
Ayaz Abdulla95d161c2006-07-06 16:46:25 -04003184 if (np->desc_ver == DESC_VER_1) {
3185 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3186 } else {
3187 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3188 txreg = NVREG_TX_WM_DESC2_3_1000;
3189 else
3190 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3191 }
3192 writel(txreg, base + NvRegTxWatermark);
3193
Szymon Janc78aea4f2010-11-27 08:39:43 +00003194 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
Linus Torvalds1da177e2005-04-16 15:20:36 -07003195 base + NvRegMisc1);
3196 pci_push(base);
3197 writel(np->linkspeed, base + NvRegLinkSpeed);
3198 pci_push(base);
3199
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003200 pause_flags = 0;
3201 /* setup pause frame */
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003202 if (np->duplex != 0) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003203 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003204 adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3205 lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003206
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003207 switch (adv_pause) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003208 case ADVERTISE_PAUSE_CAP:
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003209 if (lpa_pause & LPA_PAUSE_CAP) {
3210 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3211 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3212 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3213 }
3214 break;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003215 case ADVERTISE_PAUSE_ASYM:
Szymon Janc78aea4f2010-11-27 08:39:43 +00003216 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003217 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003218 break;
Szymon Janc78aea4f2010-11-27 08:39:43 +00003219 case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3220 if (lpa_pause & LPA_PAUSE_CAP) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003221 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3222 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3223 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3224 }
3225 if (lpa_pause == LPA_PAUSE_ASYM)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003226 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003227 break;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003228 }
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003229 } else {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003230 pause_flags = np->pause_flags;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003231 }
3232 }
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003233 nv_update_pause(dev, pause_flags);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003234
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003235 if (txrxFlags & NV_RESTART_TX)
3236 nv_start_tx(dev);
3237 if (txrxFlags & NV_RESTART_RX)
3238 nv_start_rx(dev);
3239
Linus Torvalds1da177e2005-04-16 15:20:36 -07003240 return retval;
3241}
3242
3243static void nv_linkchange(struct net_device *dev)
3244{
3245 if (nv_update_linkspeed(dev)) {
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003246 if (!netif_carrier_ok(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003247 netif_carrier_on(dev);
Joe Perches1d397f32010-11-29 07:41:57 +00003248 netdev_info(dev, "link up\n");
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00003249 nv_txrx_gate(dev, false);
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003250 nv_start_rx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003251 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003252 } else {
3253 if (netif_carrier_ok(dev)) {
3254 netif_carrier_off(dev);
Joe Perches1d397f32010-11-29 07:41:57 +00003255 netdev_info(dev, "link down\n");
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00003256 nv_txrx_gate(dev, true);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003257 nv_stop_rx(dev);
3258 }
3259 }
3260}
3261
3262static void nv_link_irq(struct net_device *dev)
3263{
3264 u8 __iomem *base = get_hwbase(dev);
3265 u32 miistat;
3266
3267 miistat = readl(base + NvRegMIIStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05003268 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003269
3270 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3271 nv_linkchange(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003272}
3273
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003274static void nv_msi_workaround(struct fe_priv *np)
3275{
3276
3277 /* Need to toggle the msi irq mask within the ethernet device,
3278 * otherwise, future interrupts will not be detected.
3279 */
3280 if (np->msi_flags & NV_MSI_ENABLED) {
3281 u8 __iomem *base = np->base;
3282
3283 writel(0, base + NvRegMSIIrqMask);
3284 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3285 }
3286}
3287
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003288static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3289{
3290 struct fe_priv *np = netdev_priv(dev);
3291
3292 if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3293 if (total_work > NV_DYNAMIC_THRESHOLD) {
3294 /* transition to poll based interrupts */
3295 np->quiet_count = 0;
3296 if (np->irqmask != NVREG_IRQMASK_CPU) {
3297 np->irqmask = NVREG_IRQMASK_CPU;
3298 return 1;
3299 }
3300 } else {
3301 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3302 np->quiet_count++;
3303 } else {
3304 /* reached a period of low activity, switch
3305 to per tx/rx packet interrupts */
3306 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3307 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3308 return 1;
3309 }
3310 }
3311 }
3312 }
3313 return 0;
3314}
3315
David Howells7d12e782006-10-05 14:55:46 +01003316static irqreturn_t nv_nic_irq(int foo, void *data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003317{
3318 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003319 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003320 u8 __iomem *base = get_hwbase(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003321
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003322 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3323 np->events = readl(base + NvRegIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003324 writel(np->events, base + NvRegIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003325 } else {
3326 np->events = readl(base + NvRegMSIXIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003327 writel(np->events, base + NvRegMSIXIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003328 }
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003329 if (!(np->events & np->irqmask))
3330 return IRQ_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003331
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003332 nv_msi_workaround(np);
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003333
Eric Dumazet78c29bd2009-07-02 04:04:45 +00003334 if (napi_schedule_prep(&np->napi)) {
3335 /*
3336 * Disable further irq's (msix not enabled with napi)
3337 */
3338 writel(0, base + NvRegIrqMask);
3339 __napi_schedule(&np->napi);
3340 }
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003341
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003342 return IRQ_HANDLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003343}
3344
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003345/**
3346 * All _optimized functions are used to help increase performance
3347 * (reduce CPU and increase throughput). They use descripter version 3,
3348 * compiler directives, and reduce memory accesses.
3349 */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003350static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3351{
3352 struct net_device *dev = (struct net_device *) data;
3353 struct fe_priv *np = netdev_priv(dev);
3354 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003355
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003356 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3357 np->events = readl(base + NvRegIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003358 writel(np->events, base + NvRegIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003359 } else {
3360 np->events = readl(base + NvRegMSIXIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003361 writel(np->events, base + NvRegMSIXIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003362 }
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003363 if (!(np->events & np->irqmask))
3364 return IRQ_NONE;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003365
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003366 nv_msi_workaround(np);
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003367
Eric Dumazet78c29bd2009-07-02 04:04:45 +00003368 if (napi_schedule_prep(&np->napi)) {
3369 /*
3370 * Disable further irq's (msix not enabled with napi)
3371 */
3372 writel(0, base + NvRegIrqMask);
3373 __napi_schedule(&np->napi);
3374 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003375
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003376 return IRQ_HANDLED;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003377}
3378
David Howells7d12e782006-10-05 14:55:46 +01003379static irqreturn_t nv_nic_irq_tx(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003380{
3381 struct net_device *dev = (struct net_device *) data;
3382 struct fe_priv *np = netdev_priv(dev);
3383 u8 __iomem *base = get_hwbase(dev);
3384 u32 events;
3385 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003386 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003387
Szymon Janc78aea4f2010-11-27 08:39:43 +00003388 for (i = 0;; i++) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003389 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3390 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003391 if (!(events & np->irqmask))
3392 break;
3393
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003394 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003395 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003396 spin_unlock_irqrestore(&np->lock, flags);
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003397
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003398 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003399 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003400 /* disable interrupts on the nic */
3401 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3402 pci_push(base);
3403
3404 if (!np->in_shutdown) {
3405 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3406 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3407 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003408 spin_unlock_irqrestore(&np->lock, flags);
Joe Perchesc20ec762010-11-29 07:42:02 +00003409 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3410 __func__, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003411 break;
3412 }
3413
3414 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003415
3416 return IRQ_RETVAL(i);
3417}
3418
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003419static int nv_napi_poll(struct napi_struct *napi, int budget)
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003420{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003421 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3422 struct net_device *dev = np->dev;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003423 u8 __iomem *base = get_hwbase(dev);
Francois Romieud15e9c42006-12-17 23:03:15 +01003424 unsigned long flags;
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003425 int retcode;
Szymon Janc78aea4f2010-11-27 08:39:43 +00003426 int rx_count, tx_work = 0, rx_work = 0;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003427
stephen hemminger81a2e362010-04-28 08:25:28 +00003428 do {
3429 if (!nv_optimized(np)) {
3430 spin_lock_irqsave(&np->lock, flags);
3431 tx_work += nv_tx_done(dev, np->tx_ring_size);
3432 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003433
Tom Herbertd951f722010-05-05 18:15:21 +00003434 rx_count = nv_rx_process(dev, budget - rx_work);
stephen hemminger81a2e362010-04-28 08:25:28 +00003435 retcode = nv_alloc_rx(dev);
3436 } else {
3437 spin_lock_irqsave(&np->lock, flags);
3438 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3439 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003440
Tom Herbertd951f722010-05-05 18:15:21 +00003441 rx_count = nv_rx_process_optimized(dev,
3442 budget - rx_work);
stephen hemminger81a2e362010-04-28 08:25:28 +00003443 retcode = nv_alloc_rx_optimized(dev);
3444 }
3445 } while (retcode == 0 &&
3446 rx_count > 0 && (rx_work += rx_count) < budget);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003447
Ayaz Abdullae0379a12007-02-20 03:34:30 -05003448 if (retcode) {
Francois Romieud15e9c42006-12-17 23:03:15 +01003449 spin_lock_irqsave(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003450 if (!np->in_shutdown)
3451 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Francois Romieud15e9c42006-12-17 23:03:15 +01003452 spin_unlock_irqrestore(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003453 }
3454
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003455 nv_change_interrupt_mode(dev, tx_work + rx_work);
3456
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003457 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3458 spin_lock_irqsave(&np->lock, flags);
3459 nv_link_irq(dev);
3460 spin_unlock_irqrestore(&np->lock, flags);
3461 }
3462 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3463 spin_lock_irqsave(&np->lock, flags);
3464 nv_linkchange(dev);
3465 spin_unlock_irqrestore(&np->lock, flags);
3466 np->link_timeout = jiffies + LINK_TIMEOUT;
3467 }
3468 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3469 spin_lock_irqsave(&np->lock, flags);
3470 if (!np->in_shutdown) {
3471 np->nic_poll_irq = np->irqmask;
3472 np->recover_error = 1;
3473 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3474 }
3475 spin_unlock_irqrestore(&np->lock, flags);
David S. Miller6c2da9c2009-04-09 01:09:33 -07003476 napi_complete(napi);
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003477 return rx_work;
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003478 }
3479
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003480 if (rx_work < budget) {
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003481 /* re-enable interrupts
3482 (msix not enabled in napi) */
David S. Miller6c2da9c2009-04-09 01:09:33 -07003483 napi_complete(napi);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003484
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003485 writel(np->irqmask, base + NvRegIrqMask);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003486 }
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003487 return rx_work;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003488}
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003489
David Howells7d12e782006-10-05 14:55:46 +01003490static irqreturn_t nv_nic_irq_rx(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003491{
3492 struct net_device *dev = (struct net_device *) data;
3493 struct fe_priv *np = netdev_priv(dev);
3494 u8 __iomem *base = get_hwbase(dev);
3495 u32 events;
3496 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003497 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003498
Szymon Janc78aea4f2010-11-27 08:39:43 +00003499 for (i = 0;; i++) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003500 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3501 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003502 if (!(events & np->irqmask))
3503 break;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003504
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003505 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003506 if (unlikely(nv_alloc_rx_optimized(dev))) {
3507 spin_lock_irqsave(&np->lock, flags);
3508 if (!np->in_shutdown)
3509 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3510 spin_unlock_irqrestore(&np->lock, flags);
3511 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003512 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003513
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003514 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003515 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003516 /* disable interrupts on the nic */
3517 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3518 pci_push(base);
3519
3520 if (!np->in_shutdown) {
3521 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3522 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3523 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003524 spin_unlock_irqrestore(&np->lock, flags);
Joe Perchesc20ec762010-11-29 07:42:02 +00003525 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3526 __func__, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003527 break;
3528 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003529 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003530
3531 return IRQ_RETVAL(i);
3532}
3533
David Howells7d12e782006-10-05 14:55:46 +01003534static irqreturn_t nv_nic_irq_other(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003535{
3536 struct net_device *dev = (struct net_device *) data;
3537 struct fe_priv *np = netdev_priv(dev);
3538 u8 __iomem *base = get_hwbase(dev);
3539 u32 events;
3540 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003541 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003542
Szymon Janc78aea4f2010-11-27 08:39:43 +00003543 for (i = 0;; i++) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003544 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3545 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003546 if (!(events & np->irqmask))
3547 break;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003548
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003549 /* check tx in case we reached max loop limit in tx isr */
3550 spin_lock_irqsave(&np->lock, flags);
3551 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3552 spin_unlock_irqrestore(&np->lock, flags);
3553
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003554 if (events & NVREG_IRQ_LINK) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003555 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003556 nv_link_irq(dev);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003557 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003558 }
3559 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003560 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003561 nv_linkchange(dev);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003562 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003563 np->link_timeout = jiffies + LINK_TIMEOUT;
3564 }
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003565 if (events & NVREG_IRQ_RECOVER_ERROR) {
3566 spin_lock_irq(&np->lock);
3567 /* disable interrupts on the nic */
3568 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3569 pci_push(base);
3570
3571 if (!np->in_shutdown) {
3572 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3573 np->recover_error = 1;
3574 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3575 }
3576 spin_unlock_irq(&np->lock);
3577 break;
3578 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003579 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003580 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003581 /* disable interrupts on the nic */
3582 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3583 pci_push(base);
3584
3585 if (!np->in_shutdown) {
3586 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3587 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3588 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003589 spin_unlock_irqrestore(&np->lock, flags);
Joe Perchesc20ec762010-11-29 07:42:02 +00003590 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3591 __func__, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003592 break;
3593 }
3594
3595 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003596
3597 return IRQ_RETVAL(i);
3598}
3599
David Howells7d12e782006-10-05 14:55:46 +01003600static irqreturn_t nv_nic_irq_test(int foo, void *data)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003601{
3602 struct net_device *dev = (struct net_device *) data;
3603 struct fe_priv *np = netdev_priv(dev);
3604 u8 __iomem *base = get_hwbase(dev);
3605 u32 events;
3606
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003607 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3608 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3609 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3610 } else {
3611 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3612 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3613 }
3614 pci_push(base);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003615 if (!(events & NVREG_IRQ_TIMER))
3616 return IRQ_RETVAL(0);
3617
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003618 nv_msi_workaround(np);
3619
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003620 spin_lock(&np->lock);
3621 np->intr_test = 1;
3622 spin_unlock(&np->lock);
3623
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003624 return IRQ_RETVAL(1);
3625}
3626
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003627static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3628{
3629 u8 __iomem *base = get_hwbase(dev);
3630 int i;
3631 u32 msixmap = 0;
3632
3633 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3634 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3635 * the remaining 8 interrupts.
3636 */
3637 for (i = 0; i < 8; i++) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003638 if ((irqmask >> i) & 0x1)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003639 msixmap |= vector << (i << 2);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003640 }
3641 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3642
3643 msixmap = 0;
3644 for (i = 0; i < 8; i++) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003645 if ((irqmask >> (i + 8)) & 0x1)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003646 msixmap |= vector << (i << 2);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003647 }
3648 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3649}
3650
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003651static int nv_request_irq(struct net_device *dev, int intr_test)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003652{
3653 struct fe_priv *np = get_nvpriv(dev);
3654 u8 __iomem *base = get_hwbase(dev);
3655 int ret = 1;
3656 int i;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003657 irqreturn_t (*handler)(int foo, void *data);
3658
3659 if (intr_test) {
3660 handler = nv_nic_irq_test;
3661 } else {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003662 if (nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003663 handler = nv_nic_irq_optimized;
3664 else
3665 handler = nv_nic_irq;
3666 }
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003667
3668 if (np->msi_flags & NV_MSI_X_CAPABLE) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003669 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003670 np->msi_x_entry[i].entry = i;
Szymon Janc34cf97e2010-11-27 08:39:46 +00003671 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3672 if (ret == 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003673 np->msi_flags |= NV_MSI_X_ENABLED;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003674 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003675 /* Request irq for rx handling */
Yinghai Luddb213f2009-02-06 01:29:23 -08003676 sprintf(np->name_rx, "%s-rx", dev->name);
3677 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
Joe Perchesa0607fd2009-11-18 23:29:17 -08003678 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
Joe Perches1d397f32010-11-29 07:41:57 +00003679 netdev_info(dev,
3680 "request_irq failed for rx %d\n",
3681 ret);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003682 pci_disable_msix(np->pci_dev);
3683 np->msi_flags &= ~NV_MSI_X_ENABLED;
3684 goto out_err;
3685 }
3686 /* Request irq for tx handling */
Yinghai Luddb213f2009-02-06 01:29:23 -08003687 sprintf(np->name_tx, "%s-tx", dev->name);
3688 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
Joe Perchesa0607fd2009-11-18 23:29:17 -08003689 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
Joe Perches1d397f32010-11-29 07:41:57 +00003690 netdev_info(dev,
3691 "request_irq failed for tx %d\n",
3692 ret);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003693 pci_disable_msix(np->pci_dev);
3694 np->msi_flags &= ~NV_MSI_X_ENABLED;
3695 goto out_free_rx;
3696 }
3697 /* Request irq for link and timer handling */
Yinghai Luddb213f2009-02-06 01:29:23 -08003698 sprintf(np->name_other, "%s-other", dev->name);
3699 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
Joe Perchesa0607fd2009-11-18 23:29:17 -08003700 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
Joe Perches1d397f32010-11-29 07:41:57 +00003701 netdev_info(dev,
3702 "request_irq failed for link %d\n",
3703 ret);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003704 pci_disable_msix(np->pci_dev);
3705 np->msi_flags &= ~NV_MSI_X_ENABLED;
3706 goto out_free_tx;
3707 }
3708 /* map interrupts to their respective vector */
3709 writel(0, base + NvRegMSIXMap0);
3710 writel(0, base + NvRegMSIXMap1);
3711 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3712 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3713 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3714 } else {
3715 /* Request irq for all interrupts */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003716 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
Joe Perches1d397f32010-11-29 07:41:57 +00003717 netdev_info(dev,
3718 "request_irq failed %d\n",
3719 ret);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003720 pci_disable_msix(np->pci_dev);
3721 np->msi_flags &= ~NV_MSI_X_ENABLED;
3722 goto out_err;
3723 }
3724
3725 /* map interrupts to vector 0 */
3726 writel(0, base + NvRegMSIXMap0);
3727 writel(0, base + NvRegMSIXMap1);
3728 }
3729 }
3730 }
3731 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
Szymon Janc34cf97e2010-11-27 08:39:46 +00003732 ret = pci_enable_msi(np->pci_dev);
3733 if (ret == 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003734 np->msi_flags |= NV_MSI_ENABLED;
Manfred Spraula7475902007-10-17 21:52:33 +02003735 dev->irq = np->pci_dev->irq;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003736 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
Joe Perches1d397f32010-11-29 07:41:57 +00003737 netdev_info(dev, "request_irq failed %d\n",
3738 ret);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003739 pci_disable_msi(np->pci_dev);
3740 np->msi_flags &= ~NV_MSI_ENABLED;
Manfred Spraula7475902007-10-17 21:52:33 +02003741 dev->irq = np->pci_dev->irq;
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003742 goto out_err;
3743 }
3744
3745 /* map interrupts to vector 0 */
3746 writel(0, base + NvRegMSIMap0);
3747 writel(0, base + NvRegMSIMap1);
3748 /* enable msi vector 0 */
3749 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3750 }
3751 }
3752 if (ret != 0) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003753 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003754 goto out_err;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003755
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003756 }
3757
3758 return 0;
3759out_free_tx:
3760 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3761out_free_rx:
3762 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3763out_err:
3764 return 1;
3765}
3766
3767static void nv_free_irq(struct net_device *dev)
3768{
3769 struct fe_priv *np = get_nvpriv(dev);
3770 int i;
3771
3772 if (np->msi_flags & NV_MSI_X_ENABLED) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003773 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003774 free_irq(np->msi_x_entry[i].vector, dev);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003775 pci_disable_msix(np->pci_dev);
3776 np->msi_flags &= ~NV_MSI_X_ENABLED;
3777 } else {
3778 free_irq(np->pci_dev->irq, dev);
3779 if (np->msi_flags & NV_MSI_ENABLED) {
3780 pci_disable_msi(np->pci_dev);
3781 np->msi_flags &= ~NV_MSI_ENABLED;
3782 }
3783 }
3784}
3785
Linus Torvalds1da177e2005-04-16 15:20:36 -07003786static void nv_do_nic_poll(unsigned long data)
3787{
3788 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003789 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003790 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003791 u32 mask = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003792
Linus Torvalds1da177e2005-04-16 15:20:36 -07003793 /*
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003794 * First disable irq(s) and then
Linus Torvalds1da177e2005-04-16 15:20:36 -07003795 * reenable interrupts on the nic, we have to do this before calling
3796 * nv_nic_irq because that may decide to do otherwise
3797 */
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003798
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003799 if (!using_multi_irqs(dev)) {
3800 if (np->msi_flags & NV_MSI_X_ENABLED)
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003801 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003802 else
Manfred Spraula7475902007-10-17 21:52:33 +02003803 disable_irq_lockdep(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003804 mask = np->irqmask;
3805 } else {
3806 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003807 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003808 mask |= NVREG_IRQ_RX_ALL;
3809 }
3810 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003811 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003812 mask |= NVREG_IRQ_TX_ALL;
3813 }
3814 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003815 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003816 mask |= NVREG_IRQ_OTHER;
3817 }
3818 }
Manfred Spraula7475902007-10-17 21:52:33 +02003819 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3820
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003821 if (np->recover_error) {
3822 np->recover_error = 0;
Joe Perches1d397f32010-11-29 07:41:57 +00003823 netdev_info(dev, "MAC in recoverable error state\n");
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003824 if (netif_running(dev)) {
3825 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07003826 netif_addr_lock(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003827 spin_lock(&np->lock);
3828 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003829 nv_stop_rxtx(dev);
Ayaz Abdulladaa91a92009-02-07 00:25:00 -08003830 if (np->driver_data & DEV_HAS_POWER_CNTRL)
3831 nv_mac_reset(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003832 nv_txrx_reset(dev);
3833 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003834 nv_drain_rxtx(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003835 /* reinit driver view of the rx queue */
3836 set_bufsize(dev);
3837 if (nv_init_ring(dev)) {
3838 if (!np->in_shutdown)
3839 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3840 }
3841 /* reinit nic view of the rx queue */
3842 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3843 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00003844 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003845 base + NvRegRingSizes);
3846 pci_push(base);
3847 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3848 pci_push(base);
Ayaz Abdulladaa91a92009-02-07 00:25:00 -08003849 /* clear interrupts */
3850 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3851 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3852 else
3853 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003854
3855 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003856 nv_start_rxtx(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003857 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07003858 netif_addr_unlock(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003859 netif_tx_unlock_bh(dev);
3860 }
3861 }
3862
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003863 writel(mask, base + NvRegIrqMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003864 pci_push(base);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003865
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003866 if (!using_multi_irqs(dev)) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08003867 np->nic_poll_irq = 0;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003868 if (nv_optimized(np))
Ayaz Abdullafcc5f262007-03-23 05:49:37 -05003869 nv_nic_irq_optimized(0, dev);
3870 else
3871 nv_nic_irq(0, dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003872 if (np->msi_flags & NV_MSI_X_ENABLED)
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003873 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003874 else
Manfred Spraula7475902007-10-17 21:52:33 +02003875 enable_irq_lockdep(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003876 } else {
3877 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08003878 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
David Howells7d12e782006-10-05 14:55:46 +01003879 nv_nic_irq_rx(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003880 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003881 }
3882 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08003883 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
David Howells7d12e782006-10-05 14:55:46 +01003884 nv_nic_irq_tx(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003885 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003886 }
3887 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08003888 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
David Howells7d12e782006-10-05 14:55:46 +01003889 nv_nic_irq_other(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003890 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003891 }
3892 }
Yinghai Lu79d30a52009-02-06 01:30:01 -08003893
Linus Torvalds1da177e2005-04-16 15:20:36 -07003894}
3895
Michal Schmidt2918c352005-05-12 19:42:06 -04003896#ifdef CONFIG_NET_POLL_CONTROLLER
3897static void nv_poll_controller(struct net_device *dev)
3898{
3899 nv_do_nic_poll((unsigned long) dev);
3900}
3901#endif
3902
Ayaz Abdulla52da3572006-06-10 22:48:04 -04003903static void nv_do_stats_poll(unsigned long data)
3904{
3905 struct net_device *dev = (struct net_device *) data;
3906 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04003907
Ayaz Abdulla57fff692007-01-23 12:27:00 -05003908 nv_get_hw_stats(dev);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04003909
3910 if (!np->in_shutdown)
Daniel Drakebfebbb82008-03-18 11:07:18 +00003911 mod_timer(&np->stats_poll,
3912 round_jiffies(jiffies + STATS_INTERVAL));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04003913}
3914
Linus Torvalds1da177e2005-04-16 15:20:36 -07003915static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3916{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003917 struct fe_priv *np = netdev_priv(dev);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04003918 strcpy(info->driver, DRV_NAME);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003919 strcpy(info->version, FORCEDETH_VERSION);
3920 strcpy(info->bus_info, pci_name(np->pci_dev));
3921}
3922
3923static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3924{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003925 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003926 wolinfo->supported = WAKE_MAGIC;
3927
3928 spin_lock_irq(&np->lock);
3929 if (np->wolenabled)
3930 wolinfo->wolopts = WAKE_MAGIC;
3931 spin_unlock_irq(&np->lock);
3932}
3933
3934static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3935{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003936 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003937 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04003938 u32 flags = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003939
Linus Torvalds1da177e2005-04-16 15:20:36 -07003940 if (wolinfo->wolopts == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003941 np->wolenabled = 0;
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04003942 } else if (wolinfo->wolopts & WAKE_MAGIC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003943 np->wolenabled = 1;
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04003944 flags = NVREG_WAKEUPFLAGS_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003945 }
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04003946 if (netif_running(dev)) {
3947 spin_lock_irq(&np->lock);
3948 writel(flags, base + NvRegWakeUpFlags);
3949 spin_unlock_irq(&np->lock);
3950 }
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00003951 device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003952 return 0;
3953}
3954
3955static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3956{
3957 struct fe_priv *np = netdev_priv(dev);
3958 int adv;
3959
3960 spin_lock_irq(&np->lock);
3961 ecmd->port = PORT_MII;
3962 if (!netif_running(dev)) {
3963 /* We do not track link speed / duplex setting if the
3964 * interface is disabled. Force a link check */
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04003965 if (nv_update_linkspeed(dev)) {
3966 if (!netif_carrier_ok(dev))
3967 netif_carrier_on(dev);
3968 } else {
3969 if (netif_carrier_ok(dev))
3970 netif_carrier_off(dev);
3971 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003972 }
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04003973
3974 if (netif_carrier_ok(dev)) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003975 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003976 case NVREG_LINKSPEED_10:
3977 ecmd->speed = SPEED_10;
3978 break;
3979 case NVREG_LINKSPEED_100:
3980 ecmd->speed = SPEED_100;
3981 break;
3982 case NVREG_LINKSPEED_1000:
3983 ecmd->speed = SPEED_1000;
3984 break;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04003985 }
3986 ecmd->duplex = DUPLEX_HALF;
3987 if (np->duplex)
3988 ecmd->duplex = DUPLEX_FULL;
3989 } else {
3990 ecmd->speed = -1;
3991 ecmd->duplex = -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003992 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003993
3994 ecmd->autoneg = np->autoneg;
3995
3996 ecmd->advertising = ADVERTISED_MII;
3997 if (np->autoneg) {
3998 ecmd->advertising |= ADVERTISED_Autoneg;
3999 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004000 if (adv & ADVERTISE_10HALF)
4001 ecmd->advertising |= ADVERTISED_10baseT_Half;
4002 if (adv & ADVERTISE_10FULL)
4003 ecmd->advertising |= ADVERTISED_10baseT_Full;
4004 if (adv & ADVERTISE_100HALF)
4005 ecmd->advertising |= ADVERTISED_100baseT_Half;
4006 if (adv & ADVERTISE_100FULL)
4007 ecmd->advertising |= ADVERTISED_100baseT_Full;
4008 if (np->gigabit == PHY_GIGABIT) {
4009 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4010 if (adv & ADVERTISE_1000FULL)
4011 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4012 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004013 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004014 ecmd->supported = (SUPPORTED_Autoneg |
4015 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4016 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4017 SUPPORTED_MII);
4018 if (np->gigabit == PHY_GIGABIT)
4019 ecmd->supported |= SUPPORTED_1000baseT_Full;
4020
4021 ecmd->phy_address = np->phyaddr;
4022 ecmd->transceiver = XCVR_EXTERNAL;
4023
4024 /* ignore maxtxpkt, maxrxpkt for now */
4025 spin_unlock_irq(&np->lock);
4026 return 0;
4027}
4028
4029static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4030{
4031 struct fe_priv *np = netdev_priv(dev);
4032
4033 if (ecmd->port != PORT_MII)
4034 return -EINVAL;
4035 if (ecmd->transceiver != XCVR_EXTERNAL)
4036 return -EINVAL;
4037 if (ecmd->phy_address != np->phyaddr) {
4038 /* TODO: support switching between multiple phys. Should be
4039 * trivial, but not enabled due to lack of test hardware. */
4040 return -EINVAL;
4041 }
4042 if (ecmd->autoneg == AUTONEG_ENABLE) {
4043 u32 mask;
4044
4045 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4046 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4047 if (np->gigabit == PHY_GIGABIT)
4048 mask |= ADVERTISED_1000baseT_Full;
4049
4050 if ((ecmd->advertising & mask) == 0)
4051 return -EINVAL;
4052
4053 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4054 /* Note: autonegotiation disable, speed 1000 intentionally
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004055 * forbidden - no one should need that. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07004056
4057 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4058 return -EINVAL;
4059 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4060 return -EINVAL;
4061 } else {
4062 return -EINVAL;
4063 }
4064
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004065 netif_carrier_off(dev);
4066 if (netif_running(dev)) {
Tobias Diedrich97bff092008-07-03 23:54:56 -07004067 unsigned long flags;
4068
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004069 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004070 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004071 netif_addr_lock(dev);
Tobias Diedrich97bff092008-07-03 23:54:56 -07004072 /* with plain spinlock lockdep complains */
4073 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004074 /* stop engines */
Tobias Diedrich97bff092008-07-03 23:54:56 -07004075 /* FIXME:
4076 * this can take some time, and interrupts are disabled
4077 * due to spin_lock_irqsave, but let's hope no daemon
4078 * is going to change the settings very often...
4079 * Worst case:
4080 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4081 * + some minor delays, which is up to a second approximately
4082 */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004083 nv_stop_rxtx(dev);
Tobias Diedrich97bff092008-07-03 23:54:56 -07004084 spin_unlock_irqrestore(&np->lock, flags);
David S. Millere308a5d2008-07-15 00:13:44 -07004085 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004086 netif_tx_unlock_bh(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004087 }
4088
Linus Torvalds1da177e2005-04-16 15:20:36 -07004089 if (ecmd->autoneg == AUTONEG_ENABLE) {
4090 int adv, bmcr;
4091
4092 np->autoneg = 1;
4093
4094 /* advertise only what has been requested */
4095 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004096 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004097 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4098 adv |= ADVERTISE_10HALF;
4099 if (ecmd->advertising & ADVERTISED_10baseT_Full)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004100 adv |= ADVERTISE_10FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004101 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4102 adv |= ADVERTISE_100HALF;
4103 if (ecmd->advertising & ADVERTISED_100baseT_Full)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004104 adv |= ADVERTISE_100FULL;
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004105 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004106 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4107 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4108 adv |= ADVERTISE_PAUSE_ASYM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004109 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4110
4111 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004112 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004113 adv &= ~ADVERTISE_1000FULL;
4114 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4115 adv |= ADVERTISE_1000FULL;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004116 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004117 }
4118
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004119 if (netif_running(dev))
Joe Perches1d397f32010-11-29 07:41:57 +00004120 netdev_info(dev, "link down\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07004121 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004122 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4123 bmcr |= BMCR_ANENABLE;
4124 /* reset the phy in order for settings to stick,
4125 * and cause autoneg to start */
4126 if (phy_reset(dev, bmcr)) {
Joe Perches1d397f32010-11-29 07:41:57 +00004127 netdev_info(dev, "phy reset failed\n");
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004128 return -EINVAL;
4129 }
4130 } else {
4131 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4132 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4133 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004134 } else {
4135 int adv, bmcr;
4136
4137 np->autoneg = 0;
4138
4139 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004140 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004141 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4142 adv |= ADVERTISE_10HALF;
4143 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004144 adv |= ADVERTISE_10FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004145 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4146 adv |= ADVERTISE_100HALF;
4147 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004148 adv |= ADVERTISE_100FULL;
4149 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004150 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004151 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4152 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4153 }
4154 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4155 adv |= ADVERTISE_PAUSE_ASYM;
4156 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4157 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004158 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4159 np->fixed_mode = adv;
4160
4161 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004162 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004163 adv &= ~ADVERTISE_1000FULL;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004164 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004165 }
4166
4167 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004168 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4169 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004170 bmcr |= BMCR_FULLDPLX;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004171 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004172 bmcr |= BMCR_SPEED100;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004173 if (np->phy_oui == PHY_OUI_MARVELL) {
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004174 /* reset the phy in order for forced mode settings to stick */
4175 if (phy_reset(dev, bmcr)) {
Joe Perches1d397f32010-11-29 07:41:57 +00004176 netdev_info(dev, "phy reset failed\n");
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004177 return -EINVAL;
4178 }
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004179 } else {
4180 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4181 if (netif_running(dev)) {
4182 /* Wait a bit and then reconfigure the nic. */
4183 udelay(10);
4184 nv_linkchange(dev);
4185 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004186 }
4187 }
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004188
4189 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004190 nv_start_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004191 nv_enable_irq(dev);
4192 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004193
4194 return 0;
4195}
4196
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004197#define FORCEDETH_REGS_VER 1
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004198
4199static int nv_get_regs_len(struct net_device *dev)
4200{
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04004201 struct fe_priv *np = netdev_priv(dev);
4202 return np->register_size;
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004203}
4204
4205static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4206{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004207 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004208 u8 __iomem *base = get_hwbase(dev);
4209 u32 *rbuf = buf;
4210 int i;
4211
4212 regs->version = FORCEDETH_REGS_VER;
4213 spin_lock_irq(&np->lock);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004214 for (i = 0; i <= np->register_size/sizeof(u32); i++)
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004215 rbuf[i] = readl(base + i*sizeof(u32));
4216 spin_unlock_irq(&np->lock);
4217}
4218
4219static int nv_nway_reset(struct net_device *dev)
4220{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004221 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004222 int ret;
4223
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004224 if (np->autoneg) {
4225 int bmcr;
4226
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004227 netif_carrier_off(dev);
4228 if (netif_running(dev)) {
4229 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004230 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004231 netif_addr_lock(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004232 spin_lock(&np->lock);
4233 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004234 nv_stop_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004235 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004236 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004237 netif_tx_unlock_bh(dev);
Joe Perches1d397f32010-11-29 07:41:57 +00004238 netdev_info(dev, "link down\n");
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004239 }
4240
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004241 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004242 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4243 bmcr |= BMCR_ANENABLE;
4244 /* reset the phy in order for settings to stick*/
4245 if (phy_reset(dev, bmcr)) {
Joe Perches1d397f32010-11-29 07:41:57 +00004246 netdev_info(dev, "phy reset failed\n");
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004247 return -EINVAL;
4248 }
4249 } else {
4250 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4251 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4252 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004253
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004254 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004255 nv_start_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004256 nv_enable_irq(dev);
4257 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004258 ret = 0;
4259 } else {
4260 ret = -EINVAL;
4261 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004262
4263 return ret;
4264}
4265
Zachary Amsden0674d592006-06-04 02:51:38 -07004266static int nv_set_tso(struct net_device *dev, u32 value)
4267{
4268 struct fe_priv *np = netdev_priv(dev);
4269
4270 if ((np->driver_data & DEV_HAS_CHECKSUM))
4271 return ethtool_op_set_tso(dev, value);
4272 else
Ayaz Abdulla6a788142006-06-10 22:47:26 -04004273 return -EOPNOTSUPP;
Zachary Amsden0674d592006-06-04 02:51:38 -07004274}
Zachary Amsden0674d592006-06-04 02:51:38 -07004275
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004276static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4277{
4278 struct fe_priv *np = netdev_priv(dev);
4279
4280 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4281 ring->rx_mini_max_pending = 0;
4282 ring->rx_jumbo_max_pending = 0;
4283 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4284
4285 ring->rx_pending = np->rx_ring_size;
4286 ring->rx_mini_pending = 0;
4287 ring->rx_jumbo_pending = 0;
4288 ring->tx_pending = np->tx_ring_size;
4289}
4290
4291static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4292{
4293 struct fe_priv *np = netdev_priv(dev);
4294 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004295 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004296 dma_addr_t ring_addr;
4297
4298 if (ring->rx_pending < RX_RING_MIN ||
4299 ring->tx_pending < TX_RING_MIN ||
4300 ring->rx_mini_pending != 0 ||
4301 ring->rx_jumbo_pending != 0 ||
4302 (np->desc_ver == DESC_VER_1 &&
4303 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4304 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4305 (np->desc_ver != DESC_VER_1 &&
4306 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4307 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4308 return -EINVAL;
4309 }
4310
4311 /* allocate new rings */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004312 if (!nv_optimized(np)) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004313 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4314 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4315 &ring_addr);
4316 } else {
4317 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4318 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4319 &ring_addr);
4320 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004321 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4322 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4323 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004324 /* fall back to old rings */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004325 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004326 if (rxtx_ring)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004327 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4328 rxtx_ring, ring_addr);
4329 } else {
4330 if (rxtx_ring)
4331 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4332 rxtx_ring, ring_addr);
4333 }
Szymon Janc9b03b062010-11-27 08:39:44 +00004334
4335 kfree(rx_skbuff);
4336 kfree(tx_skbuff);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004337 goto exit;
4338 }
4339
4340 if (netif_running(dev)) {
4341 nv_disable_irq(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00004342 nv_napi_disable(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004343 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004344 netif_addr_lock(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004345 spin_lock(&np->lock);
4346 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004347 nv_stop_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004348 nv_txrx_reset(dev);
4349 /* drain queues */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004350 nv_drain_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004351 /* delete queues */
4352 free_rings(dev);
4353 }
4354
4355 /* set new values */
4356 np->rx_ring_size = ring->rx_pending;
4357 np->tx_ring_size = ring->tx_pending;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004358
4359 if (!nv_optimized(np)) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00004360 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004361 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4362 } else {
Szymon Janc78aea4f2010-11-27 08:39:43 +00004363 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004364 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4365 }
Szymon Janc78aea4f2010-11-27 08:39:43 +00004366 np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4367 np->tx_skb = (struct nv_skb_map *)tx_skbuff;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004368 np->ring_addr = ring_addr;
4369
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004370 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4371 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004372
4373 if (netif_running(dev)) {
4374 /* reinit driver view of the queues */
4375 set_bufsize(dev);
4376 if (nv_init_ring(dev)) {
4377 if (!np->in_shutdown)
4378 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4379 }
4380
4381 /* reinit nic view of the queues */
4382 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4383 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004384 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004385 base + NvRegRingSizes);
4386 pci_push(base);
4387 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4388 pci_push(base);
4389
4390 /* restart engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004391 nv_start_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004392 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004393 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004394 netif_tx_unlock_bh(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00004395 nv_napi_enable(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004396 nv_enable_irq(dev);
4397 }
4398 return 0;
4399exit:
4400 return -ENOMEM;
4401}
4402
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004403static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4404{
4405 struct fe_priv *np = netdev_priv(dev);
4406
4407 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4408 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4409 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4410}
4411
4412static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4413{
4414 struct fe_priv *np = netdev_priv(dev);
4415 int adv, bmcr;
4416
4417 if ((!np->autoneg && np->duplex == 0) ||
4418 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
Joe Perches1d397f32010-11-29 07:41:57 +00004419 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004420 return -EINVAL;
4421 }
4422 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
Joe Perches1d397f32010-11-29 07:41:57 +00004423 netdev_info(dev, "hardware does not support tx pause frames\n");
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004424 return -EINVAL;
4425 }
4426
4427 netif_carrier_off(dev);
4428 if (netif_running(dev)) {
4429 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004430 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004431 netif_addr_lock(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004432 spin_lock(&np->lock);
4433 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004434 nv_stop_rxtx(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004435 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004436 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004437 netif_tx_unlock_bh(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004438 }
4439
4440 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4441 if (pause->rx_pause)
4442 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4443 if (pause->tx_pause)
4444 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4445
4446 if (np->autoneg && pause->autoneg) {
4447 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4448
4449 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4450 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004451 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004452 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4453 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4454 adv |= ADVERTISE_PAUSE_ASYM;
4455 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4456
4457 if (netif_running(dev))
Joe Perches1d397f32010-11-29 07:41:57 +00004458 netdev_info(dev, "link down\n");
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004459 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4460 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4461 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4462 } else {
4463 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4464 if (pause->rx_pause)
4465 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4466 if (pause->tx_pause)
4467 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4468
4469 if (!netif_running(dev))
4470 nv_update_linkspeed(dev);
4471 else
4472 nv_update_pause(dev, np->pause_flags);
4473 }
4474
4475 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004476 nv_start_rxtx(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004477 nv_enable_irq(dev);
4478 }
4479 return 0;
4480}
4481
Michał Mirosław569e1462011-04-15 04:50:49 +00004482static u32 nv_fix_features(struct net_device *dev, u32 features)
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004483{
Michał Mirosław569e1462011-04-15 04:50:49 +00004484 /* vlan is dependent on rx checksum offload */
4485 if (features & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4486 features |= NETIF_F_RXCSUM;
4487
4488 return features;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004489}
4490
Michał Mirosław569e1462011-04-15 04:50:49 +00004491static int nv_set_features(struct net_device *dev, u32 features)
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004492{
4493 struct fe_priv *np = netdev_priv(dev);
4494 u8 __iomem *base = get_hwbase(dev);
Michał Mirosław569e1462011-04-15 04:50:49 +00004495 u32 changed = dev->features ^ features;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004496
Michał Mirosław569e1462011-04-15 04:50:49 +00004497 if (changed & NETIF_F_RXCSUM) {
4498 spin_lock_irq(&np->lock);
4499
4500 if (features & NETIF_F_RXCSUM)
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004501 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
Michał Mirosław569e1462011-04-15 04:50:49 +00004502 else
4503 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4504
4505 if (netif_running(dev))
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004506 writel(np->txrxctl_bits, base + NvRegTxRxControl);
Michał Mirosław569e1462011-04-15 04:50:49 +00004507
4508 spin_unlock_irq(&np->lock);
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004509 }
4510
Michał Mirosław569e1462011-04-15 04:50:49 +00004511 return 0;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004512}
4513
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004514static int nv_get_sset_count(struct net_device *dev, int sset)
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004515{
4516 struct fe_priv *np = netdev_priv(dev);
4517
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004518 switch (sset) {
4519 case ETH_SS_TEST:
4520 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4521 return NV_TEST_COUNT_EXTENDED;
4522 else
4523 return NV_TEST_COUNT_BASE;
4524 case ETH_SS_STATS:
Ayaz Abdulla8ed14542009-03-05 08:01:49 +00004525 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4526 return NV_DEV_STATISTICS_V3_COUNT;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004527 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4528 return NV_DEV_STATISTICS_V2_COUNT;
Ayaz Abdulla8ed14542009-03-05 08:01:49 +00004529 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4530 return NV_DEV_STATISTICS_V1_COUNT;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004531 else
4532 return 0;
4533 default:
4534 return -EOPNOTSUPP;
4535 }
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004536}
4537
4538static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4539{
4540 struct fe_priv *np = netdev_priv(dev);
4541
4542 /* update stats */
4543 nv_do_stats_poll((unsigned long)dev);
4544
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004545 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004546}
4547
4548static int nv_link_test(struct net_device *dev)
4549{
4550 struct fe_priv *np = netdev_priv(dev);
4551 int mii_status;
4552
4553 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4554 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4555
4556 /* check phy link status */
4557 if (!(mii_status & BMSR_LSTATUS))
4558 return 0;
4559 else
4560 return 1;
4561}
4562
4563static int nv_register_test(struct net_device *dev)
4564{
4565 u8 __iomem *base = get_hwbase(dev);
4566 int i = 0;
4567 u32 orig_read, new_read;
4568
4569 do {
4570 orig_read = readl(base + nv_registers_test[i].reg);
4571
4572 /* xor with mask to toggle bits */
4573 orig_read ^= nv_registers_test[i].mask;
4574
4575 writel(orig_read, base + nv_registers_test[i].reg);
4576
4577 new_read = readl(base + nv_registers_test[i].reg);
4578
4579 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4580 return 0;
4581
4582 /* restore original value */
4583 orig_read ^= nv_registers_test[i].mask;
4584 writel(orig_read, base + nv_registers_test[i].reg);
4585
4586 } while (nv_registers_test[++i].reg != 0);
4587
4588 return 1;
4589}
4590
4591static int nv_interrupt_test(struct net_device *dev)
4592{
4593 struct fe_priv *np = netdev_priv(dev);
4594 u8 __iomem *base = get_hwbase(dev);
4595 int ret = 1;
4596 int testcnt;
4597 u32 save_msi_flags, save_poll_interval = 0;
4598
4599 if (netif_running(dev)) {
4600 /* free current irq */
4601 nv_free_irq(dev);
4602 save_poll_interval = readl(base+NvRegPollingInterval);
4603 }
4604
4605 /* flag to test interrupt handler */
4606 np->intr_test = 0;
4607
4608 /* setup test irq */
4609 save_msi_flags = np->msi_flags;
4610 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4611 np->msi_flags |= 0x001; /* setup 1 vector */
4612 if (nv_request_irq(dev, 1))
4613 return 0;
4614
4615 /* setup timer interrupt */
4616 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4617 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4618
4619 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4620
4621 /* wait for at least one interrupt */
4622 msleep(100);
4623
4624 spin_lock_irq(&np->lock);
4625
4626 /* flag should be set within ISR */
4627 testcnt = np->intr_test;
4628 if (!testcnt)
4629 ret = 2;
4630
4631 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4632 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4633 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4634 else
4635 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4636
4637 spin_unlock_irq(&np->lock);
4638
4639 nv_free_irq(dev);
4640
4641 np->msi_flags = save_msi_flags;
4642
4643 if (netif_running(dev)) {
4644 writel(save_poll_interval, base + NvRegPollingInterval);
4645 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4646 /* restore original irq */
4647 if (nv_request_irq(dev, 0))
4648 return 0;
4649 }
4650
4651 return ret;
4652}
4653
4654static int nv_loopback_test(struct net_device *dev)
4655{
4656 struct fe_priv *np = netdev_priv(dev);
4657 u8 __iomem *base = get_hwbase(dev);
4658 struct sk_buff *tx_skb, *rx_skb;
4659 dma_addr_t test_dma_addr;
4660 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004661 u32 flags;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004662 int len, i, pkt_len;
4663 u8 *pkt_data;
4664 u32 filter_flags = 0;
4665 u32 misc1_flags = 0;
4666 int ret = 1;
4667
4668 if (netif_running(dev)) {
4669 nv_disable_irq(dev);
4670 filter_flags = readl(base + NvRegPacketFilterFlags);
4671 misc1_flags = readl(base + NvRegMisc1);
4672 } else {
4673 nv_txrx_reset(dev);
4674 }
4675
4676 /* reinit driver view of the rx queue */
4677 set_bufsize(dev);
4678 nv_init_ring(dev);
4679
4680 /* setup hardware for loopback */
4681 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4682 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4683
4684 /* reinit nic view of the rx queue */
4685 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4686 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004687 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004688 base + NvRegRingSizes);
4689 pci_push(base);
4690
4691 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004692 nv_start_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004693
4694 /* setup packet for tx */
4695 pkt_len = ETH_DATA_LEN;
4696 tx_skb = dev_alloc_skb(pkt_len);
Jesper Juhl46798c82006-09-25 16:39:24 -07004697 if (!tx_skb) {
Joe Perches1d397f32010-11-29 07:41:57 +00004698 netdev_err(dev, "dev_alloc_skb() failed during loopback test\n");
Jesper Juhl46798c82006-09-25 16:39:24 -07004699 ret = 0;
4700 goto out;
4701 }
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03004702 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4703 skb_tailroom(tx_skb),
4704 PCI_DMA_FROMDEVICE);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004705 pkt_data = skb_put(tx_skb, pkt_len);
4706 for (i = 0; i < pkt_len; i++)
4707 pkt_data[i] = (u8)(i & 0xff);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004708
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004709 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004710 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4711 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004712 } else {
Al Viro5bb7ea22007-12-09 16:06:41 +00004713 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4714 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004715 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004716 }
4717 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4718 pci_push(get_hwbase(dev));
4719
4720 msleep(500);
4721
4722 /* check for rx of the packet */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004723 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004724 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004725 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4726
4727 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004728 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004729 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4730 }
4731
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004732 if (flags & NV_RX_AVAIL) {
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004733 ret = 0;
4734 } else if (np->desc_ver == DESC_VER_1) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004735 if (flags & NV_RX_ERROR)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004736 ret = 0;
4737 } else {
Szymon Janc78aea4f2010-11-27 08:39:43 +00004738 if (flags & NV_RX2_ERROR)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004739 ret = 0;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004740 }
4741
4742 if (ret) {
4743 if (len != pkt_len) {
4744 ret = 0;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004745 } else {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004746 rx_skb = np->rx_skb[0].skb;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004747 for (i = 0; i < pkt_len; i++) {
4748 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4749 ret = 0;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004750 break;
4751 }
4752 }
4753 }
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004754 }
4755
Eric Dumazet73a37072009-06-17 21:17:59 +00004756 pci_unmap_single(np->pci_dev, test_dma_addr,
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07004757 (skb_end_pointer(tx_skb) - tx_skb->data),
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004758 PCI_DMA_TODEVICE);
4759 dev_kfree_skb_any(tx_skb);
Jesper Juhl46798c82006-09-25 16:39:24 -07004760 out:
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004761 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004762 nv_stop_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004763 nv_txrx_reset(dev);
4764 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004765 nv_drain_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004766
4767 if (netif_running(dev)) {
4768 writel(misc1_flags, base + NvRegMisc1);
4769 writel(filter_flags, base + NvRegPacketFilterFlags);
4770 nv_enable_irq(dev);
4771 }
4772
4773 return ret;
4774}
4775
4776static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4777{
4778 struct fe_priv *np = netdev_priv(dev);
4779 u8 __iomem *base = get_hwbase(dev);
4780 int result;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004781 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004782
4783 if (!nv_link_test(dev)) {
4784 test->flags |= ETH_TEST_FL_FAILED;
4785 buffer[0] = 1;
4786 }
4787
4788 if (test->flags & ETH_TEST_FL_OFFLINE) {
4789 if (netif_running(dev)) {
4790 netif_stop_queue(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00004791 nv_napi_disable(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004792 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004793 netif_addr_lock(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004794 spin_lock_irq(&np->lock);
4795 nv_disable_hw_interrupts(dev, np->irqmask);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004796 if (!(np->msi_flags & NV_MSI_X_ENABLED))
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004797 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004798 else
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004799 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004800 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004801 nv_stop_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004802 nv_txrx_reset(dev);
4803 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004804 nv_drain_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004805 spin_unlock_irq(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004806 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004807 netif_tx_unlock_bh(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004808 }
4809
4810 if (!nv_register_test(dev)) {
4811 test->flags |= ETH_TEST_FL_FAILED;
4812 buffer[1] = 1;
4813 }
4814
4815 result = nv_interrupt_test(dev);
4816 if (result != 1) {
4817 test->flags |= ETH_TEST_FL_FAILED;
4818 buffer[2] = 1;
4819 }
4820 if (result == 0) {
4821 /* bail out */
4822 return;
4823 }
4824
4825 if (!nv_loopback_test(dev)) {
4826 test->flags |= ETH_TEST_FL_FAILED;
4827 buffer[3] = 1;
4828 }
4829
4830 if (netif_running(dev)) {
4831 /* reinit driver view of the rx queue */
4832 set_bufsize(dev);
4833 if (nv_init_ring(dev)) {
4834 if (!np->in_shutdown)
4835 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4836 }
4837 /* reinit nic view of the rx queue */
4838 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4839 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004840 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004841 base + NvRegRingSizes);
4842 pci_push(base);
4843 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4844 pci_push(base);
4845 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004846 nv_start_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004847 netif_start_queue(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00004848 nv_napi_enable(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004849 nv_enable_hw_interrupts(dev, np->irqmask);
4850 }
4851 }
4852}
4853
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004854static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4855{
4856 switch (stringset) {
4857 case ETH_SS_STATS:
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004858 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004859 break;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004860 case ETH_SS_TEST:
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004861 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004862 break;
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004863 }
4864}
4865
Jeff Garzik7282d492006-09-13 14:30:00 -04004866static const struct ethtool_ops ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004867 .get_drvinfo = nv_get_drvinfo,
4868 .get_link = ethtool_op_get_link,
4869 .get_wol = nv_get_wol,
4870 .set_wol = nv_set_wol,
4871 .get_settings = nv_get_settings,
4872 .set_settings = nv_set_settings,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004873 .get_regs_len = nv_get_regs_len,
4874 .get_regs = nv_get_regs,
4875 .nway_reset = nv_nway_reset,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004876 .get_ringparam = nv_get_ringparam,
4877 .set_ringparam = nv_set_ringparam,
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004878 .get_pauseparam = nv_get_pauseparam,
4879 .set_pauseparam = nv_set_pauseparam,
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004880 .get_strings = nv_get_strings,
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004881 .get_ethtool_stats = nv_get_ethtool_stats,
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004882 .get_sset_count = nv_get_sset_count,
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004883 .self_test = nv_self_test,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004884};
4885
Ayaz Abdullaee407b02006-02-04 13:13:17 -05004886static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4887{
4888 struct fe_priv *np = get_nvpriv(dev);
4889
4890 spin_lock_irq(&np->lock);
4891
4892 /* save vlan group */
4893 np->vlangrp = grp;
4894
4895 if (grp) {
4896 /* enable vlan on MAC */
4897 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4898 } else {
4899 /* disable vlan on MAC */
4900 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4901 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4902 }
4903
4904 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4905
4906 spin_unlock_irq(&np->lock);
Stephen Hemminger25805dc2007-06-01 09:44:01 -07004907}
Ayaz Abdullaee407b02006-02-04 13:13:17 -05004908
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05004909/* The mgmt unit and driver use a semaphore to access the phy during init */
4910static int nv_mgmt_acquire_sema(struct net_device *dev)
4911{
Ayaz Abdullacac1c522009-02-07 00:23:57 -08004912 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05004913 u8 __iomem *base = get_hwbase(dev);
4914 int i;
4915 u32 tx_ctrl, mgmt_sema;
4916
4917 for (i = 0; i < 10; i++) {
4918 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4919 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4920 break;
4921 msleep(500);
4922 }
4923
4924 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4925 return 0;
4926
4927 for (i = 0; i < 2; i++) {
4928 tx_ctrl = readl(base + NvRegTransmitterControl);
4929 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4930 writel(tx_ctrl, base + NvRegTransmitterControl);
4931
4932 /* verify that semaphore was acquired */
4933 tx_ctrl = readl(base + NvRegTransmitterControl);
4934 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
Ayaz Abdullacac1c522009-02-07 00:23:57 -08004935 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
4936 np->mgmt_sema = 1;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05004937 return 1;
Szymon Janc78aea4f2010-11-27 08:39:43 +00004938 } else
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05004939 udelay(50);
4940 }
4941
4942 return 0;
4943}
4944
Ayaz Abdullacac1c522009-02-07 00:23:57 -08004945static void nv_mgmt_release_sema(struct net_device *dev)
4946{
4947 struct fe_priv *np = netdev_priv(dev);
4948 u8 __iomem *base = get_hwbase(dev);
4949 u32 tx_ctrl;
4950
4951 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
4952 if (np->mgmt_sema) {
4953 tx_ctrl = readl(base + NvRegTransmitterControl);
4954 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
4955 writel(tx_ctrl, base + NvRegTransmitterControl);
4956 }
4957 }
4958}
4959
4960
4961static int nv_mgmt_get_version(struct net_device *dev)
4962{
4963 struct fe_priv *np = netdev_priv(dev);
4964 u8 __iomem *base = get_hwbase(dev);
4965 u32 data_ready = readl(base + NvRegTransmitterControl);
4966 u32 data_ready2 = 0;
4967 unsigned long start;
4968 int ready = 0;
4969
4970 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
4971 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
4972 start = jiffies;
4973 while (time_before(jiffies, start + 5*HZ)) {
4974 data_ready2 = readl(base + NvRegTransmitterControl);
4975 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
4976 ready = 1;
4977 break;
4978 }
4979 schedule_timeout_uninterruptible(1);
4980 }
4981
4982 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
4983 return 0;
4984
4985 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
4986
4987 return 1;
4988}
4989
Linus Torvalds1da177e2005-04-16 15:20:36 -07004990static int nv_open(struct net_device *dev)
4991{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004992 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004993 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004994 int ret = 1;
4995 int oom, i;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07004996 u32 low;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004997
Ed Swierkcb52deb2008-12-01 12:24:43 +00004998 /* power up phy */
4999 mii_rw(dev, np->phyaddr, MII_BMCR,
5000 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5001
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00005002 nv_txrx_gate(dev, false);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005003 /* erase previous misconfiguration */
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005004 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5005 nv_mac_reset(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005006 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5007 writel(0, base + NvRegMulticastAddrB);
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05005008 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5009 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005010 writel(0, base + NvRegPacketFilterFlags);
5011
5012 writel(0, base + NvRegTransmitterControl);
5013 writel(0, base + NvRegReceiverControl);
5014
5015 writel(0, base + NvRegAdapterControl);
5016
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005017 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5018 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5019
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005020 /* initialize descriptor rings */
Manfred Sprauld81c0982005-07-31 18:20:30 +02005021 set_bufsize(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005022 oom = nv_init_ring(dev);
5023
5024 writel(0, base + NvRegLinkSpeed);
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005025 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005026 nv_txrx_reset(dev);
5027 writel(0, base + NvRegUnknownSetupReg6);
5028
5029 np->in_shutdown = 0;
5030
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005031 /* give hw rings */
Ayaz Abdulla0832b252006-02-04 13:13:26 -05005032 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005033 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Linus Torvalds1da177e2005-04-16 15:20:36 -07005034 base + NvRegRingSizes);
5035
Linus Torvalds1da177e2005-04-16 15:20:36 -07005036 writel(np->linkspeed, base + NvRegLinkSpeed);
Ayaz Abdulla95d161c2006-07-06 16:46:25 -04005037 if (np->desc_ver == DESC_VER_1)
5038 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5039 else
5040 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005041 writel(np->txrxctl_bits, base + NvRegTxRxControl);
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005042 writel(np->vlanctl_bits, base + NvRegVlanControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005043 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005044 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
Joe Perches344d0dc2010-11-29 07:41:52 +00005045 if (reg_delay(dev, NvRegUnknownSetupReg5,
5046 NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5047 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
Joe Perches1d397f32010-11-29 07:41:57 +00005048 netdev_info(dev,
5049 "%s: SetupReg5, Bit 31 remained off\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005050
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005051 writel(0, base + NvRegMIIMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005052 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005053 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005054
Linus Torvalds1da177e2005-04-16 15:20:36 -07005055 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5056 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5057 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
Manfred Sprauld81c0982005-07-31 18:20:30 +02005058 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005059
5060 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07005061
5062 get_random_bytes(&low, sizeof(low));
5063 low &= NVREG_SLOTTIME_MASK;
5064 if (np->desc_ver == DESC_VER_1) {
5065 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5066 } else {
5067 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5068 /* setup legacy backoff */
5069 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5070 } else {
5071 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5072 nv_gear_backoff_reseed(dev);
5073 }
5074 }
Ayaz Abdulla9744e212006-07-06 16:45:58 -04005075 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5076 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005077 if (poll_interval == -1) {
5078 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5079 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5080 else
5081 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005082 } else
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005083 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005084 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5085 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5086 base + NvRegAdapterControl);
5087 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005088 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04005089 if (np->wolenabled)
5090 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005091
5092 i = readl(base + NvRegPowerState);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005093 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005094 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5095
5096 pci_push(base);
5097 udelay(10);
5098 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5099
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005100 nv_disable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005101 pci_push(base);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005102 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005103 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5104 pci_push(base);
5105
Szymon Janc78aea4f2010-11-27 08:39:43 +00005106 if (nv_request_irq(dev, 0))
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005107 goto out_drain;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005108
5109 /* ask for interrupts */
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005110 nv_enable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005111
5112 spin_lock_irq(&np->lock);
5113 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5114 writel(0, base + NvRegMulticastAddrB);
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05005115 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5116 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005117 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5118 /* One manual link speed update: Interrupts are enabled, future link
5119 * speed changes cause interrupts and are handled by nv_link_irq().
5120 */
5121 {
5122 u32 miistat;
5123 miistat = readl(base + NvRegMIIStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005124 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005125 }
Manfred Spraul1b1b3c92005-08-06 23:47:55 +02005126 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5127 * to init hw */
5128 np->linkspeed = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005129 ret = nv_update_linkspeed(dev);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005130 nv_start_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005131 netif_start_queue(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00005132 nv_napi_enable(dev);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07005133
Linus Torvalds1da177e2005-04-16 15:20:36 -07005134 if (ret) {
5135 netif_carrier_on(dev);
5136 } else {
Joe Perches1d397f32010-11-29 07:41:57 +00005137 netdev_info(dev, "no link during initialization\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005138 netif_carrier_off(dev);
5139 }
5140 if (oom)
5141 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005142
5143 /* start statistics timer */
Ayaz Abdulla9c662432008-08-06 12:11:42 -04005144 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
Daniel Drakebfebbb82008-03-18 11:07:18 +00005145 mod_timer(&np->stats_poll,
5146 round_jiffies(jiffies + STATS_INTERVAL));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005147
Linus Torvalds1da177e2005-04-16 15:20:36 -07005148 spin_unlock_irq(&np->lock);
5149
5150 return 0;
5151out_drain:
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005152 nv_drain_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005153 return ret;
5154}
5155
5156static int nv_close(struct net_device *dev)
5157{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005158 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005159 u8 __iomem *base;
5160
5161 spin_lock_irq(&np->lock);
5162 np->in_shutdown = 1;
5163 spin_unlock_irq(&np->lock);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00005164 nv_napi_disable(dev);
Manfred Spraula7475902007-10-17 21:52:33 +02005165 synchronize_irq(np->pci_dev->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005166
5167 del_timer_sync(&np->oom_kick);
5168 del_timer_sync(&np->nic_poll);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005169 del_timer_sync(&np->stats_poll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005170
5171 netif_stop_queue(dev);
5172 spin_lock_irq(&np->lock);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005173 nv_stop_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005174 nv_txrx_reset(dev);
5175
5176 /* disable interrupts on the nic or we will lock up */
5177 base = get_hwbase(dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005178 nv_disable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005179 pci_push(base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005180
5181 spin_unlock_irq(&np->lock);
5182
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005183 nv_free_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005184
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005185 nv_drain_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005186
Ed Swierk5a9a8e32009-06-02 00:19:52 -07005187 if (np->wolenabled || !phy_power_down) {
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00005188 nv_txrx_gate(dev, false);
Tim Mann2cc49a52007-06-14 13:16:38 -07005189 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005190 nv_start_rx(dev);
Ed Swierkcb52deb2008-12-01 12:24:43 +00005191 } else {
5192 /* power down phy */
5193 mii_rw(dev, np->phyaddr, MII_BMCR,
5194 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00005195 nv_txrx_gate(dev, true);
Tim Mann2cc49a52007-06-14 13:16:38 -07005196 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005197
5198 /* FIXME: power down nic */
5199
5200 return 0;
5201}
5202
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005203static const struct net_device_ops nv_netdev_ops = {
5204 .ndo_open = nv_open,
5205 .ndo_stop = nv_close,
5206 .ndo_get_stats = nv_get_stats,
Stephen Hemminger00829822008-11-20 20:14:53 -08005207 .ndo_start_xmit = nv_start_xmit,
5208 .ndo_tx_timeout = nv_tx_timeout,
5209 .ndo_change_mtu = nv_change_mtu,
Michał Mirosław569e1462011-04-15 04:50:49 +00005210 .ndo_fix_features = nv_fix_features,
5211 .ndo_set_features = nv_set_features,
Stephen Hemminger00829822008-11-20 20:14:53 -08005212 .ndo_validate_addr = eth_validate_addr,
5213 .ndo_set_mac_address = nv_set_mac_address,
5214 .ndo_set_multicast_list = nv_set_multicast,
5215 .ndo_vlan_rx_register = nv_vlan_rx_register,
5216#ifdef CONFIG_NET_POLL_CONTROLLER
5217 .ndo_poll_controller = nv_poll_controller,
5218#endif
5219};
5220
5221static const struct net_device_ops nv_netdev_ops_optimized = {
5222 .ndo_open = nv_open,
5223 .ndo_stop = nv_close,
5224 .ndo_get_stats = nv_get_stats,
5225 .ndo_start_xmit = nv_start_xmit_optimized,
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005226 .ndo_tx_timeout = nv_tx_timeout,
5227 .ndo_change_mtu = nv_change_mtu,
Michał Mirosław569e1462011-04-15 04:50:49 +00005228 .ndo_fix_features = nv_fix_features,
5229 .ndo_set_features = nv_set_features,
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005230 .ndo_validate_addr = eth_validate_addr,
5231 .ndo_set_mac_address = nv_set_mac_address,
5232 .ndo_set_multicast_list = nv_set_multicast,
5233 .ndo_vlan_rx_register = nv_vlan_rx_register,
5234#ifdef CONFIG_NET_POLL_CONTROLLER
5235 .ndo_poll_controller = nv_poll_controller,
5236#endif
5237};
5238
Linus Torvalds1da177e2005-04-16 15:20:36 -07005239static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5240{
5241 struct net_device *dev;
5242 struct fe_priv *np;
5243 unsigned long addr;
5244 u8 __iomem *base;
5245 int err, i;
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005246 u32 powerstate, txreg;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005247 u32 phystate_orig = 0, phystate;
5248 int phyinitialized = 0;
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005249 static int printed_version;
5250
5251 if (!printed_version++)
Joe Perches294a5542010-11-29 07:41:56 +00005252 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5253 FORCEDETH_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005254
5255 dev = alloc_etherdev(sizeof(struct fe_priv));
5256 err = -ENOMEM;
5257 if (!dev)
5258 goto out;
5259
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005260 np = netdev_priv(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005261 np->dev = dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005262 np->pci_dev = pci_dev;
5263 spin_lock_init(&np->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005264 SET_NETDEV_DEV(dev, &pci_dev->dev);
5265
5266 init_timer(&np->oom_kick);
5267 np->oom_kick.data = (unsigned long) dev;
Joe Perchesc061b182010-08-23 18:20:03 +00005268 np->oom_kick.function = nv_do_rx_refill; /* timer handler */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005269 init_timer(&np->nic_poll);
5270 np->nic_poll.data = (unsigned long) dev;
Joe Perchesc061b182010-08-23 18:20:03 +00005271 np->nic_poll.function = nv_do_nic_poll; /* timer handler */
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005272 init_timer(&np->stats_poll);
5273 np->stats_poll.data = (unsigned long) dev;
Joe Perchesc061b182010-08-23 18:20:03 +00005274 np->stats_poll.function = nv_do_stats_poll; /* timer handler */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005275
5276 err = pci_enable_device(pci_dev);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005277 if (err)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005278 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005279
5280 pci_set_master(pci_dev);
5281
5282 err = pci_request_regions(pci_dev, DRV_NAME);
5283 if (err < 0)
5284 goto out_disable;
5285
Ayaz Abdulla9c662432008-08-06 12:11:42 -04005286 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
Ayaz Abdulla57fff692007-01-23 12:27:00 -05005287 np->register_size = NV_PCI_REGSZ_VER3;
5288 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005289 np->register_size = NV_PCI_REGSZ_VER2;
5290 else
5291 np->register_size = NV_PCI_REGSZ_VER1;
5292
Linus Torvalds1da177e2005-04-16 15:20:36 -07005293 err = -EINVAL;
5294 addr = 0;
5295 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005296 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005297 pci_resource_len(pci_dev, i) >= np->register_size) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005298 addr = pci_resource_start(pci_dev, i);
5299 break;
5300 }
5301 }
5302 if (i == DEVICE_COUNT_RESOURCE) {
Joe Perchesb2ba08e2010-11-29 07:42:00 +00005303 dev_info(&pci_dev->dev, "Couldn't find register window\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005304 goto out_relreg;
5305 }
5306
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005307 /* copy of driver data */
5308 np->driver_data = id->driver_data;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005309 /* copy of device id */
5310 np->device_id = id->device;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005311
Linus Torvalds1da177e2005-04-16 15:20:36 -07005312 /* handle different descriptor versions */
Manfred Spraulee733622005-07-31 18:32:26 +02005313 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5314 /* packet format 3: supports 40-bit addressing */
5315 np->desc_ver = DESC_VER_3;
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005316 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005317 if (dma_64bit) {
Yang Hongyang6afd1422009-04-06 19:01:15 -07005318 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
Joe Perchesb2ba08e2010-11-29 07:42:00 +00005319 dev_info(&pci_dev->dev,
5320 "64-bit DMA failed, using 32-bit addressing\n");
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005321 else
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005322 dev->features |= NETIF_F_HIGHDMA;
Yang Hongyang6afd1422009-04-06 19:01:15 -07005323 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
Joe Perchesb2ba08e2010-11-29 07:42:00 +00005324 dev_info(&pci_dev->dev,
5325 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005326 }
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005327 }
Manfred Spraulee733622005-07-31 18:32:26 +02005328 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5329 /* packet format 2: supports jumbo frames */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005330 np->desc_ver = DESC_VER_2;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005331 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
Manfred Spraulee733622005-07-31 18:32:26 +02005332 } else {
5333 /* original packet format */
5334 np->desc_ver = DESC_VER_1;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005335 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
Manfred Sprauld81c0982005-07-31 18:20:30 +02005336 }
Manfred Spraulee733622005-07-31 18:32:26 +02005337
5338 np->pkt_limit = NV_PKTLIMIT_1;
5339 if (id->driver_data & DEV_HAS_LARGEDESC)
5340 np->pkt_limit = NV_PKTLIMIT_2;
5341
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005342 if (id->driver_data & DEV_HAS_CHECKSUM) {
5343 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
Michał Mirosław569e1462011-04-15 04:50:49 +00005344 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5345 NETIF_F_TSO | NETIF_F_RXCSUM;
5346 dev->features |= dev->hw_features;
Ayaz Abdulla21828162007-01-23 12:27:21 -05005347 }
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005348
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005349 np->vlanctl_bits = 0;
5350 if (id->driver_data & DEV_HAS_VLAN) {
5351 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5352 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005353 }
5354
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005355 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005356 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5357 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5358 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005359 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005360 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04005361
Linus Torvalds1da177e2005-04-16 15:20:36 -07005362 err = -ENOMEM;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005363 np->base = ioremap(addr, np->register_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005364 if (!np->base)
5365 goto out_relreg;
5366 dev->base_addr = (unsigned long)np->base;
Manfred Spraulee733622005-07-31 18:32:26 +02005367
Linus Torvalds1da177e2005-04-16 15:20:36 -07005368 dev->irq = pci_dev->irq;
Manfred Spraulee733622005-07-31 18:32:26 +02005369
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005370 np->rx_ring_size = RX_RING_DEFAULT;
5371 np->tx_ring_size = TX_RING_DEFAULT;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005372
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005373 if (!nv_optimized(np)) {
Manfred Spraulee733622005-07-31 18:32:26 +02005374 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005375 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
Manfred Spraulee733622005-07-31 18:32:26 +02005376 &np->ring_addr);
5377 if (!np->rx_ring.orig)
5378 goto out_unmap;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005379 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
Manfred Spraulee733622005-07-31 18:32:26 +02005380 } else {
5381 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005382 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
Manfred Spraulee733622005-07-31 18:32:26 +02005383 &np->ring_addr);
5384 if (!np->rx_ring.ex)
5385 goto out_unmap;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005386 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
Manfred Spraulee733622005-07-31 18:32:26 +02005387 }
Yoann Padioleaudd00cc42007-07-19 01:49:03 -07005388 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5389 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05005390 if (!np->rx_skb || !np->tx_skb)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005391 goto out_freering;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005392
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005393 if (!nv_optimized(np))
Stephen Hemminger00829822008-11-20 20:14:53 -08005394 dev->netdev_ops = &nv_netdev_ops;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05005395 else
Stephen Hemminger00829822008-11-20 20:14:53 -08005396 dev->netdev_ops = &nv_netdev_ops_optimized;
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005397
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005398 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005399 SET_ETHTOOL_OPS(dev, &ops);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005400 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5401
5402 pci_set_drvdata(pci_dev, dev);
5403
5404 /* read the mac address */
5405 base = get_hwbase(dev);
5406 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5407 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5408
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005409 /* check the workaround bit for correct mac address order */
5410 txreg = readl(base + NvRegTransmitPoll);
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005411 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005412 /* mac address is already in correct order */
5413 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5414 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5415 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5416 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5417 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5418 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005419 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5420 /* mac address is already in correct order */
5421 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5422 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5423 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5424 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5425 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5426 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5427 /*
5428 * Set orig mac address back to the reversed version.
5429 * This flag will be cleared during low power transition.
5430 * Therefore, we should always put back the reversed address.
5431 */
5432 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5433 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5434 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005435 } else {
5436 /* need to reverse mac address to correct order */
5437 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5438 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5439 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5440 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5441 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5442 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005443 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
Joe Perchesc20ec762010-11-29 07:42:02 +00005444 dev_dbg(&pci_dev->dev,
5445 "%s: set workaround bit for reversed mac addr\n",
5446 __func__);
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005447 }
John W. Linvillec704b852005-09-12 10:48:56 -04005448 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005449
John W. Linvillec704b852005-09-12 10:48:56 -04005450 if (!is_valid_ether_addr(dev->perm_addr)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005451 /*
5452 * Bad mac address. At least one bios sets the mac address
5453 * to 01:23:45:67:89:ab
5454 */
Joe Perchesb2ba08e2010-11-29 07:42:00 +00005455 dev_err(&pci_dev->dev,
Joe Perchesc20ec762010-11-29 07:42:02 +00005456 "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
Szymon Janc78aea4f2010-11-27 08:39:43 +00005457 dev->dev_addr);
Stanislav O. Bezzubtsev655a6592009-11-15 21:17:02 -08005458 random_ether_addr(dev->dev_addr);
Joe Perchesc20ec762010-11-29 07:42:02 +00005459 dev_err(&pci_dev->dev,
5460 "Using random MAC address: %pM\n", dev->dev_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005461 }
5462
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005463 /* set mac address */
5464 nv_copy_mac_to_hw(dev);
5465
Linus Torvalds1da177e2005-04-16 15:20:36 -07005466 /* disable WOL */
5467 writel(0, base + NvRegWakeUpFlags);
5468 np->wolenabled = 0;
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00005469 device_set_wakeup_enable(&pci_dev->dev, false);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005470
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005471 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005472
5473 /* take phy and nic out of low power mode */
5474 powerstate = readl(base + NvRegPowerState2);
5475 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005476 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
Auke Kok44c10132007-06-08 15:46:36 -07005477 pci_dev->revision >= 0xA3)
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005478 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5479 writel(powerstate, base + NvRegPowerState2);
5480 }
5481
Szymon Janc78aea4f2010-11-27 08:39:43 +00005482 if (np->desc_ver == DESC_VER_1)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005483 np->tx_flags = NV_TX_VALID;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005484 else
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005485 np->tx_flags = NV_TX2_VALID;
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005486
5487 np->msi_flags = 0;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005488 if ((id->driver_data & DEV_HAS_MSI) && msi)
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005489 np->msi_flags |= NV_MSI_CAPABLE;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005490
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005491 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5492 /* msix has had reported issues when modifying irqmask
5493 as in the case of napi, therefore, disable for now
5494 */
David S. Miller0a127612010-05-03 23:33:05 -07005495#if 0
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005496 np->msi_flags |= NV_MSI_X_CAPABLE;
5497#endif
5498 }
5499
5500 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005501 np->irqmask = NVREG_IRQMASK_CPU;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005502 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5503 np->msi_flags |= 0x0001;
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005504 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5505 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5506 /* start off in throughput mode */
5507 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5508 /* remove support for msix mode */
5509 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5510 } else {
5511 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5512 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5513 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5514 np->msi_flags |= 0x0003;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005515 }
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005516
Linus Torvalds1da177e2005-04-16 15:20:36 -07005517 if (id->driver_data & DEV_NEED_TIMERIRQ)
5518 np->irqmask |= NVREG_IRQ_TIMER;
5519 if (id->driver_data & DEV_NEED_LINKTIMER) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005520 np->need_linktimer = 1;
5521 np->link_timeout = jiffies + LINK_TIMEOUT;
5522 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005523 np->need_linktimer = 0;
5524 }
5525
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005526 /* Limit the number of tx's outstanding for hw bug */
5527 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5528 np->tx_limit = 1;
Ayaz Abdulla5c659322010-04-13 18:49:51 -07005529 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005530 pci_dev->revision >= 0xA2)
5531 np->tx_limit = 0;
5532 }
5533
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005534 /* clear phy state and temporarily halt phy interrupts */
5535 writel(0, base + NvRegMIIMask);
5536 phystate = readl(base + NvRegAdapterControl);
5537 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5538 phystate_orig = 1;
5539 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5540 writel(phystate, base + NvRegAdapterControl);
5541 }
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005542 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005543
5544 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005545 /* management unit running on the mac? */
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005546 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5547 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5548 nv_mgmt_acquire_sema(dev) &&
5549 nv_mgmt_get_version(dev)) {
5550 np->mac_in_use = 1;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005551 if (np->mgmt_version > 0)
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005552 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005553 /* management unit setup the phy already? */
5554 if (np->mac_in_use &&
5555 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5556 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5557 /* phy is inited by mgmt unit */
5558 phyinitialized = 1;
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005559 } else {
5560 /* we need to init the phy */
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005561 }
5562 }
5563 }
5564
Linus Torvalds1da177e2005-04-16 15:20:36 -07005565 /* find a suitable phy */
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005566 for (i = 1; i <= 32; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005567 int id1, id2;
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005568 int phyaddr = i & 0x1F;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005569
5570 spin_lock_irq(&np->lock);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005571 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005572 spin_unlock_irq(&np->lock);
5573 if (id1 < 0 || id1 == 0xffff)
5574 continue;
5575 spin_lock_irq(&np->lock);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005576 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005577 spin_unlock_irq(&np->lock);
5578 if (id2 < 0 || id2 == 0xffff)
5579 continue;
5580
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04005581 np->phy_model = id2 & PHYID2_MODEL_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005582 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5583 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005584 np->phyaddr = phyaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005585 np->phy_oui = id1 | id2;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005586
5587 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5588 if (np->phy_oui == PHY_OUI_REALTEK2)
5589 np->phy_oui = PHY_OUI_REALTEK;
5590 /* Setup phy revision for Realtek */
5591 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5592 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5593
Linus Torvalds1da177e2005-04-16 15:20:36 -07005594 break;
5595 }
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005596 if (i == 33) {
Joe Perchesb2ba08e2010-11-29 07:42:00 +00005597 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005598 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005599 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04005600
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005601 if (!phyinitialized) {
5602 /* reset it */
5603 phy_init(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05005604 } else {
5605 /* see if it is a gigabit phy */
5606 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005607 if (mii_status & PHY_GIGABIT)
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05005608 np->gigabit = PHY_GIGABIT;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005609 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005610
5611 /* set default link speed settings */
5612 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5613 np->duplex = 0;
5614 np->autoneg = 1;
5615
5616 err = register_netdev(dev);
5617 if (err) {
Joe Perchesb2ba08e2010-11-29 07:42:00 +00005618 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005619 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005620 }
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005621
Ivan Vecera0d672e92011-02-15 02:08:39 +00005622 netif_carrier_off(dev);
5623
Joe Perchesb2ba08e2010-11-29 07:42:00 +00005624 dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
5625 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005626
Joe Perchesb2ba08e2010-11-29 07:42:00 +00005627 dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5628 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5629 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
Szymon Janc78aea4f2010-11-27 08:39:43 +00005630 "csum " : "",
Joe Perchesb2ba08e2010-11-29 07:42:00 +00005631 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
Szymon Janc78aea4f2010-11-27 08:39:43 +00005632 "vlan " : "",
Joe Perchesb2ba08e2010-11-29 07:42:00 +00005633 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5634 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5635 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5636 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5637 np->need_linktimer ? "lnktim " : "",
5638 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5639 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5640 np->desc_ver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005641
5642 return 0;
5643
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005644out_error:
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005645 if (phystate_orig)
5646 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005647 pci_set_drvdata(pci_dev, NULL);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005648out_freering:
5649 free_rings(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005650out_unmap:
5651 iounmap(get_hwbase(dev));
5652out_relreg:
5653 pci_release_regions(pci_dev);
5654out_disable:
5655 pci_disable_device(pci_dev);
5656out_free:
5657 free_netdev(dev);
5658out:
5659 return err;
5660}
5661
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005662static void nv_restore_phy(struct net_device *dev)
5663{
5664 struct fe_priv *np = netdev_priv(dev);
5665 u16 phy_reserved, mii_control;
5666
5667 if (np->phy_oui == PHY_OUI_REALTEK &&
5668 np->phy_model == PHY_MODEL_REALTEK_8201 &&
5669 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5670 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5671 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5672 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5673 phy_reserved |= PHY_REALTEK_INIT8;
5674 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5675 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5676
5677 /* restart auto negotiation */
5678 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5679 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5680 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5681 }
5682}
5683
Yinghai Luf55c21f2008-09-13 13:10:31 -07005684static void nv_restore_mac_addr(struct pci_dev *pci_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005685{
5686 struct net_device *dev = pci_get_drvdata(pci_dev);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005687 struct fe_priv *np = netdev_priv(dev);
5688 u8 __iomem *base = get_hwbase(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005689
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005690 /* special op: write back the misordered MAC address - otherwise
5691 * the next nv_probe would see a wrong address.
5692 */
5693 writel(np->orig_mac[0], base + NvRegMacAddrA);
5694 writel(np->orig_mac[1], base + NvRegMacAddrB);
Björn Steinbrink2e3884b2008-01-07 23:22:53 -08005695 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5696 base + NvRegTransmitPoll);
Yinghai Luf55c21f2008-09-13 13:10:31 -07005697}
5698
5699static void __devexit nv_remove(struct pci_dev *pci_dev)
5700{
5701 struct net_device *dev = pci_get_drvdata(pci_dev);
5702
5703 unregister_netdev(dev);
5704
5705 nv_restore_mac_addr(pci_dev);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005706
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005707 /* restore any phy related changes */
5708 nv_restore_phy(dev);
5709
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005710 nv_mgmt_release_sema(dev);
5711
Linus Torvalds1da177e2005-04-16 15:20:36 -07005712 /* free all structures */
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005713 free_rings(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005714 iounmap(get_hwbase(dev));
5715 pci_release_regions(pci_dev);
5716 pci_disable_device(pci_dev);
5717 free_netdev(dev);
5718 pci_set_drvdata(pci_dev, NULL);
5719}
5720
Michel Lespinasse94252762011-03-06 16:14:50 +00005721#ifdef CONFIG_PM_SLEEP
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00005722static int nv_suspend(struct device *device)
Francois Romieua1893172006-10-10 14:33:27 -07005723{
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00005724 struct pci_dev *pdev = to_pci_dev(device);
Francois Romieua1893172006-10-10 14:33:27 -07005725 struct net_device *dev = pci_get_drvdata(pdev);
5726 struct fe_priv *np = netdev_priv(dev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005727 u8 __iomem *base = get_hwbase(dev);
5728 int i;
Francois Romieua1893172006-10-10 14:33:27 -07005729
Tobias Diedrich25d90812008-05-18 15:04:29 +02005730 if (netif_running(dev)) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00005731 /* Gross. */
Tobias Diedrich25d90812008-05-18 15:04:29 +02005732 nv_close(dev);
5733 }
Francois Romieua1893172006-10-10 14:33:27 -07005734 netif_device_detach(dev);
5735
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005736 /* save non-pci configuration space */
Szymon Janc78aea4f2010-11-27 08:39:43 +00005737 for (i = 0; i <= np->register_size/sizeof(u32); i++)
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005738 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5739
Francois Romieua1893172006-10-10 14:33:27 -07005740 return 0;
5741}
5742
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00005743static int nv_resume(struct device *device)
Francois Romieua1893172006-10-10 14:33:27 -07005744{
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00005745 struct pci_dev *pdev = to_pci_dev(device);
Francois Romieua1893172006-10-10 14:33:27 -07005746 struct net_device *dev = pci_get_drvdata(pdev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005747 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005748 u8 __iomem *base = get_hwbase(dev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005749 int i, rc = 0;
Francois Romieua1893172006-10-10 14:33:27 -07005750
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005751 /* restore non-pci configuration space */
Szymon Janc78aea4f2010-11-27 08:39:43 +00005752 for (i = 0; i <= np->register_size/sizeof(u32); i++)
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005753 writel(np->saved_config_space[i], base+i*sizeof(u32));
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005754
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005755 if (np->driver_data & DEV_NEED_MSI_FIX)
5756 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
Ayaz Abdullab6e44052009-02-07 00:24:15 -08005757
Ed Swierk35a74332009-04-06 17:49:12 -07005758 /* restore phy state, including autoneg */
5759 phy_init(dev);
5760
Tobias Diedrich25d90812008-05-18 15:04:29 +02005761 netif_device_attach(dev);
5762 if (netif_running(dev)) {
5763 rc = nv_open(dev);
5764 nv_set_multicast(dev);
5765 }
Francois Romieua1893172006-10-10 14:33:27 -07005766 return rc;
5767}
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005768
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00005769static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
5770#define NV_PM_OPS (&nv_pm_ops)
5771
Michel Lespinasse94252762011-03-06 16:14:50 +00005772#else
5773#define NV_PM_OPS NULL
5774#endif /* CONFIG_PM_SLEEP */
5775
5776#ifdef CONFIG_PM
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005777static void nv_shutdown(struct pci_dev *pdev)
5778{
5779 struct net_device *dev = pci_get_drvdata(pdev);
5780 struct fe_priv *np = netdev_priv(dev);
5781
5782 if (netif_running(dev))
5783 nv_close(dev);
5784
Tobias Diedrich34edaa82009-02-16 00:13:20 -08005785 /*
5786 * Restore the MAC so a kernel started by kexec won't get confused.
5787 * If we really go for poweroff, we must not restore the MAC,
5788 * otherwise the MAC for WOL will be reversed at least on some boards.
5789 */
Szymon Janc78aea4f2010-11-27 08:39:43 +00005790 if (system_state != SYSTEM_POWER_OFF)
Tobias Diedrich34edaa82009-02-16 00:13:20 -08005791 nv_restore_mac_addr(pdev);
Yinghai Luf55c21f2008-09-13 13:10:31 -07005792
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005793 pci_disable_device(pdev);
Tobias Diedrich34edaa82009-02-16 00:13:20 -08005794 /*
5795 * Apparently it is not possible to reinitialise from D3 hot,
5796 * only put the device into D3 if we really go for poweroff.
5797 */
Rafael J. Wysocki3cb55992008-09-05 14:00:19 -07005798 if (system_state == SYSTEM_POWER_OFF) {
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00005799 pci_wake_from_d3(pdev, np->wolenabled);
Rafael J. Wysocki3cb55992008-09-05 14:00:19 -07005800 pci_set_power_state(pdev, PCI_D3hot);
5801 }
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005802}
Francois Romieua1893172006-10-10 14:33:27 -07005803#else
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005804#define nv_shutdown NULL
Francois Romieua1893172006-10-10 14:33:27 -07005805#endif /* CONFIG_PM */
5806
Alexey Dobriyana3aa1882010-01-07 11:58:11 +00005807static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005808 { /* nForce Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005809 PCI_DEVICE(0x10DE, 0x01C3),
Manfred Spraulc2dba062005-07-31 18:29:47 +02005810 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005811 },
5812 { /* nForce2 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005813 PCI_DEVICE(0x10DE, 0x0066),
Manfred Spraulc2dba062005-07-31 18:29:47 +02005814 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005815 },
5816 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005817 PCI_DEVICE(0x10DE, 0x00D6),
Manfred Spraulc2dba062005-07-31 18:29:47 +02005818 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005819 },
5820 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005821 PCI_DEVICE(0x10DE, 0x0086),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005822 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005823 },
5824 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005825 PCI_DEVICE(0x10DE, 0x008C),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005826 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005827 },
5828 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005829 PCI_DEVICE(0x10DE, 0x00E6),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005830 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005831 },
5832 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005833 PCI_DEVICE(0x10DE, 0x00DF),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005834 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005835 },
5836 { /* CK804 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005837 PCI_DEVICE(0x10DE, 0x0056),
Yinghai Lu033e97b2009-02-06 01:30:56 -08005838 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005839 },
5840 { /* CK804 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005841 PCI_DEVICE(0x10DE, 0x0057),
Yinghai Lu033e97b2009-02-06 01:30:56 -08005842 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005843 },
5844 { /* MCP04 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005845 PCI_DEVICE(0x10DE, 0x0037),
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005846 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005847 },
5848 { /* MCP04 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005849 PCI_DEVICE(0x10DE, 0x0038),
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005850 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005851 },
5852 { /* MCP51 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005853 PCI_DEVICE(0x10DE, 0x0268),
5854 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005855 },
Manfred Spraul9992d4a2005-06-05 17:36:11 +02005856 { /* MCP51 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005857 PCI_DEVICE(0x10DE, 0x0269),
5858 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
Manfred Spraul9992d4a2005-06-05 17:36:11 +02005859 },
Manfred Spraulf49d16e2005-06-26 11:36:52 +02005860 { /* MCP55 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005861 PCI_DEVICE(0x10DE, 0x0372),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005862 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02005863 },
5864 { /* MCP55 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005865 PCI_DEVICE(0x10DE, 0x0373),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005866 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02005867 },
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005868 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005869 PCI_DEVICE(0x10DE, 0x03E5),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005870 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005871 },
5872 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005873 PCI_DEVICE(0x10DE, 0x03E6),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005874 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005875 },
5876 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005877 PCI_DEVICE(0x10DE, 0x03EE),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005878 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005879 },
5880 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005881 PCI_DEVICE(0x10DE, 0x03EF),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005882 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005883 },
5884 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005885 PCI_DEVICE(0x10DE, 0x0450),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005886 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005887 },
5888 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005889 PCI_DEVICE(0x10DE, 0x0451),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005890 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005891 },
5892 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005893 PCI_DEVICE(0x10DE, 0x0452),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005894 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005895 },
5896 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005897 PCI_DEVICE(0x10DE, 0x0453),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005898 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005899 },
Ayaz Abdullaf4344842006-11-06 00:43:40 -08005900 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005901 PCI_DEVICE(0x10DE, 0x054C),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005902 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08005903 },
5904 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005905 PCI_DEVICE(0x10DE, 0x054D),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005906 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08005907 },
5908 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005909 PCI_DEVICE(0x10DE, 0x054E),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005910 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08005911 },
5912 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005913 PCI_DEVICE(0x10DE, 0x054F),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005914 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08005915 },
Ayaz Abdulla13986612007-07-22 20:43:26 -04005916 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005917 PCI_DEVICE(0x10DE, 0x07DC),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005918 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04005919 },
5920 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005921 PCI_DEVICE(0x10DE, 0x07DD),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005922 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04005923 },
5924 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005925 PCI_DEVICE(0x10DE, 0x07DE),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005926 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04005927 },
5928 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005929 PCI_DEVICE(0x10DE, 0x07DF),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005930 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04005931 },
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04005932 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005933 PCI_DEVICE(0x10DE, 0x0760),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005934 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04005935 },
5936 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005937 PCI_DEVICE(0x10DE, 0x0761),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005938 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04005939 },
5940 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005941 PCI_DEVICE(0x10DE, 0x0762),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005942 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04005943 },
5944 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005945 PCI_DEVICE(0x10DE, 0x0763),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005946 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04005947 },
Ayaz Abdulla490dde82007-11-23 20:54:01 -05005948 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005949 PCI_DEVICE(0x10DE, 0x0AB0),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005950 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05005951 },
5952 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005953 PCI_DEVICE(0x10DE, 0x0AB1),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005954 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05005955 },
5956 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005957 PCI_DEVICE(0x10DE, 0x0AB2),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005958 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05005959 },
5960 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005961 PCI_DEVICE(0x10DE, 0x0AB3),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005962 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05005963 },
Ayaz Abdulla3df81c42009-06-03 15:05:35 +00005964 { /* MCP89 Ethernet Controller */
5965 PCI_DEVICE(0x10DE, 0x0D7D),
Mike Ditto7b5e0782010-07-25 21:54:28 -07005966 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
Ayaz Abdulla3df81c42009-06-03 15:05:35 +00005967 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07005968 {0,},
5969};
5970
5971static struct pci_driver driver = {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005972 .name = DRV_NAME,
5973 .id_table = pci_tbl,
5974 .probe = nv_probe,
5975 .remove = __devexit_p(nv_remove),
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005976 .shutdown = nv_shutdown,
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00005977 .driver.pm = NV_PM_OPS,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005978};
5979
Linus Torvalds1da177e2005-04-16 15:20:36 -07005980static int __init init_nic(void)
5981{
Jeff Garzik29917622006-08-19 17:48:59 -04005982 return pci_register_driver(&driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005983}
5984
5985static void __exit exit_nic(void)
5986{
5987 pci_unregister_driver(&driver);
5988}
5989
5990module_param(max_interrupt_work, int, 0);
5991MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005992module_param(optimization_mode, int, 0);
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005993MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005994module_param(poll_interval, int, 0);
5995MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005996module_param(msi, int, 0);
5997MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5998module_param(msix, int, 0);
5999MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6000module_param(dma_64bit, int, 0);
6001MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04006002module_param(phy_cross, int, 0);
6003MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
Ed Swierk5a9a8e32009-06-02 00:19:52 -07006004module_param(phy_power_down, int, 0);
6005MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
Linus Torvalds1da177e2005-04-16 15:20:36 -07006006
6007MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6008MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6009MODULE_LICENSE("GPL");
6010
6011MODULE_DEVICE_TABLE(pci, pci_tbl);
6012
6013module_init(init_nic);
6014module_exit(exit_nic);