Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1 | /* |
Pierre Ossman | 70f1048 | 2007-07-11 20:04:50 +0200 | [diff] [blame] | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3 | * |
Pierre Ossman | b69c905 | 2008-03-08 23:44:25 +0100 | [diff] [blame] | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
Pierre Ossman | 643f720 | 2006-09-30 23:27:52 -0700 | [diff] [blame] | 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or (at |
| 9 | * your option) any later version. |
Pierre Ossman | 84c46a5 | 2007-12-02 19:58:16 +0100 | [diff] [blame] | 10 | * |
| 11 | * Thanks to the following companies for their support: |
| 12 | * |
| 13 | * - JMicron (hardware and technical support) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 14 | */ |
| 15 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 16 | #include <linux/delay.h> |
| 17 | #include <linux/highmem.h> |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 18 | #include <linux/io.h> |
Paul Gortmaker | 88b4767 | 2011-07-03 15:15:51 -0400 | [diff] [blame] | 19 | #include <linux/module.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 20 | #include <linux/dma-mapping.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 21 | #include <linux/slab.h> |
Ralf Baechle | 1176360 | 2007-10-23 20:42:11 +0200 | [diff] [blame] | 22 | #include <linux/scatterlist.h> |
Marek Szyprowski | 9bea3c8 | 2010-08-10 18:01:59 -0700 | [diff] [blame] | 23 | #include <linux/regulator/consumer.h> |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 24 | #include <linux/pm_runtime.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 25 | |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 26 | #include <linux/leds.h> |
| 27 | |
Aries Lee | 22113ef | 2010-12-15 08:14:24 +0100 | [diff] [blame] | 28 | #include <linux/mmc/mmc.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 29 | #include <linux/mmc/host.h> |
Aaron Lu | 473b095a | 2012-07-03 17:27:49 +0800 | [diff] [blame] | 30 | #include <linux/mmc/card.h> |
Corneliu Doban | 85cc1c3 | 2015-02-09 16:06:29 -0800 | [diff] [blame] | 31 | #include <linux/mmc/sdio.h> |
Guennadi Liakhovetski | bec9d4e | 2012-09-17 16:45:10 +0800 | [diff] [blame] | 32 | #include <linux/mmc/slot-gpio.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 33 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 34 | #include "sdhci.h" |
| 35 | |
| 36 | #define DRIVER_NAME "sdhci" |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 37 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 38 | #define DBG(f, x...) \ |
Russell King | c656317 | 2006-03-29 09:30:20 +0100 | [diff] [blame] | 39 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 40 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 41 | #define MAX_TUNING_LOOP 40 |
| 42 | |
Pierre Ossman | df673b2 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 43 | static unsigned int debug_quirks = 0; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 44 | static unsigned int debug_quirks2; |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 45 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 46 | static void sdhci_finish_data(struct sdhci_host *); |
| 47 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 48 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 49 | |
| 50 | static void sdhci_dumpregs(struct sdhci_host *host) |
| 51 | { |
Chuanxiao Dong | a7c5367 | 2016-06-22 14:40:01 +0300 | [diff] [blame] | 52 | pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", |
| 53 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 54 | |
Chuanxiao Dong | a7c5367 | 2016-06-22 14:40:01 +0300 | [diff] [blame] | 55 | pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", |
| 56 | sdhci_readl(host, SDHCI_DMA_ADDRESS), |
| 57 | sdhci_readw(host, SDHCI_HOST_VERSION)); |
| 58 | pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", |
| 59 | sdhci_readw(host, SDHCI_BLOCK_SIZE), |
| 60 | sdhci_readw(host, SDHCI_BLOCK_COUNT)); |
| 61 | pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", |
| 62 | sdhci_readl(host, SDHCI_ARGUMENT), |
| 63 | sdhci_readw(host, SDHCI_TRANSFER_MODE)); |
| 64 | pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", |
| 65 | sdhci_readl(host, SDHCI_PRESENT_STATE), |
| 66 | sdhci_readb(host, SDHCI_HOST_CONTROL)); |
| 67 | pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", |
| 68 | sdhci_readb(host, SDHCI_POWER_CONTROL), |
| 69 | sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); |
| 70 | pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", |
| 71 | sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), |
| 72 | sdhci_readw(host, SDHCI_CLOCK_CONTROL)); |
| 73 | pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", |
| 74 | sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), |
| 75 | sdhci_readl(host, SDHCI_INT_STATUS)); |
| 76 | pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", |
| 77 | sdhci_readl(host, SDHCI_INT_ENABLE), |
| 78 | sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); |
| 79 | pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", |
| 80 | sdhci_readw(host, SDHCI_ACMD12_ERR), |
| 81 | sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); |
| 82 | pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", |
| 83 | sdhci_readl(host, SDHCI_CAPABILITIES), |
| 84 | sdhci_readl(host, SDHCI_CAPABILITIES_1)); |
| 85 | pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", |
| 86 | sdhci_readw(host, SDHCI_COMMAND), |
| 87 | sdhci_readl(host, SDHCI_MAX_CURRENT)); |
| 88 | pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n", |
| 89 | sdhci_readw(host, SDHCI_HOST_CONTROL2)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 90 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 91 | if (host->flags & SDHCI_USE_ADMA) { |
| 92 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
Chuanxiao Dong | a7c5367 | 2016-06-22 14:40:01 +0300 | [diff] [blame] | 93 | pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", |
| 94 | readl(host->ioaddr + SDHCI_ADMA_ERROR), |
| 95 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI), |
| 96 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 97 | else |
Chuanxiao Dong | a7c5367 | 2016-06-22 14:40:01 +0300 | [diff] [blame] | 98 | pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", |
| 99 | readl(host->ioaddr + SDHCI_ADMA_ERROR), |
| 100 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 101 | } |
Ben Dooks | be3f4ae | 2009-06-08 23:33:52 +0100 | [diff] [blame] | 102 | |
Chuanxiao Dong | a7c5367 | 2016-06-22 14:40:01 +0300 | [diff] [blame] | 103 | pr_err(DRIVER_NAME ": ===========================================\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | /*****************************************************************************\ |
| 107 | * * |
| 108 | * Low level functions * |
| 109 | * * |
| 110 | \*****************************************************************************/ |
| 111 | |
Adrian Hunter | 56a590d | 2016-06-29 16:24:32 +0300 | [diff] [blame^] | 112 | static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) |
| 113 | { |
| 114 | return cmd->data || cmd->flags & MMC_RSP_BUSY; |
| 115 | } |
| 116 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 117 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) |
| 118 | { |
Russell King | 5b4f1f6 | 2014-04-25 12:57:02 +0100 | [diff] [blame] | 119 | u32 present; |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 120 | |
Adrian Hunter | c79396c | 2011-12-27 15:48:42 +0200 | [diff] [blame] | 121 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || |
Jaehoon Chung | 860951c | 2016-06-21 10:13:26 +0900 | [diff] [blame] | 122 | !mmc_card_is_removable(host->mmc)) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 123 | return; |
| 124 | |
Russell King | 5b4f1f6 | 2014-04-25 12:57:02 +0100 | [diff] [blame] | 125 | if (enable) { |
| 126 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & |
| 127 | SDHCI_CARD_PRESENT; |
Shawn Guo | d25928d | 2011-06-21 22:41:48 +0800 | [diff] [blame] | 128 | |
Russell King | 5b4f1f6 | 2014-04-25 12:57:02 +0100 | [diff] [blame] | 129 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : |
| 130 | SDHCI_INT_CARD_INSERT; |
| 131 | } else { |
| 132 | host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); |
| 133 | } |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 134 | |
| 135 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 136 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | static void sdhci_enable_card_detection(struct sdhci_host *host) |
| 140 | { |
| 141 | sdhci_set_card_detection(host, true); |
| 142 | } |
| 143 | |
| 144 | static void sdhci_disable_card_detection(struct sdhci_host *host) |
| 145 | { |
| 146 | sdhci_set_card_detection(host, false); |
| 147 | } |
| 148 | |
Ulf Hansson | 02d0b68 | 2016-04-11 15:32:41 +0200 | [diff] [blame] | 149 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) |
| 150 | { |
| 151 | if (host->bus_on) |
| 152 | return; |
| 153 | host->bus_on = true; |
| 154 | pm_runtime_get_noresume(host->mmc->parent); |
| 155 | } |
| 156 | |
| 157 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) |
| 158 | { |
| 159 | if (!host->bus_on) |
| 160 | return; |
| 161 | host->bus_on = false; |
| 162 | pm_runtime_put_noidle(host->mmc->parent); |
| 163 | } |
| 164 | |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 165 | void sdhci_reset(struct sdhci_host *host, u8 mask) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 166 | { |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 167 | unsigned long timeout; |
Philip Rakity | 393c1a3 | 2011-01-21 11:26:40 -0800 | [diff] [blame] | 168 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 169 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 170 | |
Adrian Hunter | f0710a5 | 2013-05-06 12:17:32 +0300 | [diff] [blame] | 171 | if (mask & SDHCI_RESET_ALL) { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 172 | host->clock = 0; |
Adrian Hunter | f0710a5 | 2013-05-06 12:17:32 +0300 | [diff] [blame] | 173 | /* Reset-all turns off SD Bus Power */ |
| 174 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
| 175 | sdhci_runtime_pm_bus_off(host); |
| 176 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 177 | |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 178 | /* Wait max 100 ms */ |
| 179 | timeout = 100; |
| 180 | |
| 181 | /* hw clears the bit when it's done */ |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 182 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 183 | if (timeout == 0) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 184 | pr_err("%s: Reset 0x%x never completed.\n", |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 185 | mmc_hostname(host->mmc), (int)mask); |
| 186 | sdhci_dumpregs(host); |
| 187 | return; |
| 188 | } |
| 189 | timeout--; |
| 190 | mdelay(1); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 191 | } |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 192 | } |
| 193 | EXPORT_SYMBOL_GPL(sdhci_reset); |
Anton Vorontsov | 063a9db | 2009-03-17 00:14:02 +0300 | [diff] [blame] | 194 | |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 195 | static void sdhci_do_reset(struct sdhci_host *host, u8 mask) |
| 196 | { |
| 197 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 198 | struct mmc_host *mmc = host->mmc; |
| 199 | |
| 200 | if (!mmc->ops->get_cd(mmc)) |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 201 | return; |
| 202 | } |
| 203 | |
| 204 | host->ops->reset(host, mask); |
Philip Rakity | 393c1a3 | 2011-01-21 11:26:40 -0800 | [diff] [blame] | 205 | |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 206 | if (mask & SDHCI_RESET_ALL) { |
| 207 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
| 208 | if (host->ops->enable_dma) |
| 209 | host->ops->enable_dma(host); |
| 210 | } |
| 211 | |
| 212 | /* Resetting the controller clears many */ |
| 213 | host->preset_enabled = false; |
Shaohui Xie | 3abc1e80 | 2011-12-29 16:33:00 +0800 | [diff] [blame] | 214 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 215 | } |
| 216 | |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 217 | static void sdhci_init(struct sdhci_host *host, int soft) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 218 | { |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 219 | struct mmc_host *mmc = host->mmc; |
| 220 | |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 221 | if (soft) |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 222 | sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 223 | else |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 224 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 225 | |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 226 | host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | |
| 227 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | |
| 228 | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | |
| 229 | SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | |
| 230 | SDHCI_INT_RESPONSE; |
| 231 | |
| 232 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 233 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 234 | |
| 235 | if (soft) { |
| 236 | /* force clock reconfiguration */ |
| 237 | host->clock = 0; |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 238 | mmc->ops->set_ios(mmc, &mmc->ios); |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 239 | } |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 240 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 241 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 242 | static void sdhci_reinit(struct sdhci_host *host) |
| 243 | { |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 244 | sdhci_init(host, 0); |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 245 | sdhci_enable_card_detection(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 246 | } |
| 247 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 248 | static void __sdhci_led_activate(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 249 | { |
| 250 | u8 ctrl; |
| 251 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 252 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 253 | ctrl |= SDHCI_CTRL_LED; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 254 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 255 | } |
| 256 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 257 | static void __sdhci_led_deactivate(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 258 | { |
| 259 | u8 ctrl; |
| 260 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 261 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 262 | ctrl &= ~SDHCI_CTRL_LED; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 263 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 264 | } |
| 265 | |
Masahiro Yamada | 4f78230 | 2016-04-14 13:19:39 +0900 | [diff] [blame] | 266 | #if IS_REACHABLE(CONFIG_LEDS_CLASS) |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 267 | static void sdhci_led_control(struct led_classdev *led, |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 268 | enum led_brightness brightness) |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 269 | { |
| 270 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); |
| 271 | unsigned long flags; |
| 272 | |
| 273 | spin_lock_irqsave(&host->lock, flags); |
| 274 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 275 | if (host->runtime_suspended) |
| 276 | goto out; |
| 277 | |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 278 | if (brightness == LED_OFF) |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 279 | __sdhci_led_deactivate(host); |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 280 | else |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 281 | __sdhci_led_activate(host); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 282 | out: |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 283 | spin_unlock_irqrestore(&host->lock, flags); |
| 284 | } |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 285 | |
| 286 | static int sdhci_led_register(struct sdhci_host *host) |
| 287 | { |
| 288 | struct mmc_host *mmc = host->mmc; |
| 289 | |
| 290 | snprintf(host->led_name, sizeof(host->led_name), |
| 291 | "%s::", mmc_hostname(mmc)); |
| 292 | |
| 293 | host->led.name = host->led_name; |
| 294 | host->led.brightness = LED_OFF; |
| 295 | host->led.default_trigger = mmc_hostname(mmc); |
| 296 | host->led.brightness_set = sdhci_led_control; |
| 297 | |
| 298 | return led_classdev_register(mmc_dev(mmc), &host->led); |
| 299 | } |
| 300 | |
| 301 | static void sdhci_led_unregister(struct sdhci_host *host) |
| 302 | { |
| 303 | led_classdev_unregister(&host->led); |
| 304 | } |
| 305 | |
| 306 | static inline void sdhci_led_activate(struct sdhci_host *host) |
| 307 | { |
| 308 | } |
| 309 | |
| 310 | static inline void sdhci_led_deactivate(struct sdhci_host *host) |
| 311 | { |
| 312 | } |
| 313 | |
| 314 | #else |
| 315 | |
| 316 | static inline int sdhci_led_register(struct sdhci_host *host) |
| 317 | { |
| 318 | return 0; |
| 319 | } |
| 320 | |
| 321 | static inline void sdhci_led_unregister(struct sdhci_host *host) |
| 322 | { |
| 323 | } |
| 324 | |
| 325 | static inline void sdhci_led_activate(struct sdhci_host *host) |
| 326 | { |
| 327 | __sdhci_led_activate(host); |
| 328 | } |
| 329 | |
| 330 | static inline void sdhci_led_deactivate(struct sdhci_host *host) |
| 331 | { |
| 332 | __sdhci_led_deactivate(host); |
| 333 | } |
| 334 | |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 335 | #endif |
| 336 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 337 | /*****************************************************************************\ |
| 338 | * * |
| 339 | * Core functions * |
| 340 | * * |
| 341 | \*****************************************************************************/ |
| 342 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 343 | static void sdhci_read_block_pio(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 344 | { |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 345 | unsigned long flags; |
| 346 | size_t blksize, len, chunk; |
Steven Noonan | 7244b85 | 2008-10-01 01:50:25 -0700 | [diff] [blame] | 347 | u32 uninitialized_var(scratch); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 348 | u8 *buf; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 349 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 350 | DBG("PIO reading\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 351 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 352 | blksize = host->data->blksz; |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 353 | chunk = 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 354 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 355 | local_irq_save(flags); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 356 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 357 | while (blksize) { |
Fabio Estevam | bf3a35a | 2015-05-09 18:44:51 -0300 | [diff] [blame] | 358 | BUG_ON(!sg_miter_next(&host->sg_miter)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 359 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 360 | len = min(host->sg_miter.length, blksize); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 361 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 362 | blksize -= len; |
| 363 | host->sg_miter.consumed = len; |
Alex Dubov | 14d836e | 2007-04-13 19:04:38 +0200 | [diff] [blame] | 364 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 365 | buf = host->sg_miter.addr; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 366 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 367 | while (len) { |
| 368 | if (chunk == 0) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 369 | scratch = sdhci_readl(host, SDHCI_BUFFER); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 370 | chunk = 4; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 371 | } |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 372 | |
| 373 | *buf = scratch & 0xFF; |
| 374 | |
| 375 | buf++; |
| 376 | scratch >>= 8; |
| 377 | chunk--; |
| 378 | len--; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 379 | } |
| 380 | } |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 381 | |
| 382 | sg_miter_stop(&host->sg_miter); |
| 383 | |
| 384 | local_irq_restore(flags); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 385 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 386 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 387 | static void sdhci_write_block_pio(struct sdhci_host *host) |
| 388 | { |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 389 | unsigned long flags; |
| 390 | size_t blksize, len, chunk; |
| 391 | u32 scratch; |
| 392 | u8 *buf; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 393 | |
| 394 | DBG("PIO writing\n"); |
| 395 | |
| 396 | blksize = host->data->blksz; |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 397 | chunk = 0; |
| 398 | scratch = 0; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 399 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 400 | local_irq_save(flags); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 401 | |
| 402 | while (blksize) { |
Fabio Estevam | bf3a35a | 2015-05-09 18:44:51 -0300 | [diff] [blame] | 403 | BUG_ON(!sg_miter_next(&host->sg_miter)); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 404 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 405 | len = min(host->sg_miter.length, blksize); |
Alex Dubov | 14d836e | 2007-04-13 19:04:38 +0200 | [diff] [blame] | 406 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 407 | blksize -= len; |
| 408 | host->sg_miter.consumed = len; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 409 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 410 | buf = host->sg_miter.addr; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 411 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 412 | while (len) { |
| 413 | scratch |= (u32)*buf << (chunk * 8); |
| 414 | |
| 415 | buf++; |
| 416 | chunk++; |
| 417 | len--; |
| 418 | |
| 419 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 420 | sdhci_writel(host, scratch, SDHCI_BUFFER); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 421 | chunk = 0; |
| 422 | scratch = 0; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 423 | } |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 424 | } |
| 425 | } |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 426 | |
| 427 | sg_miter_stop(&host->sg_miter); |
| 428 | |
| 429 | local_irq_restore(flags); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 430 | } |
| 431 | |
| 432 | static void sdhci_transfer_pio(struct sdhci_host *host) |
| 433 | { |
| 434 | u32 mask; |
| 435 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 436 | if (host->blocks == 0) |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 437 | return; |
| 438 | |
| 439 | if (host->data->flags & MMC_DATA_READ) |
| 440 | mask = SDHCI_DATA_AVAILABLE; |
| 441 | else |
| 442 | mask = SDHCI_SPACE_AVAILABLE; |
| 443 | |
Pierre Ossman | 4a3cba3 | 2008-07-29 00:11:16 +0200 | [diff] [blame] | 444 | /* |
| 445 | * Some controllers (JMicron JMB38x) mess up the buffer bits |
| 446 | * for transfers < 4 bytes. As long as it is just one block, |
| 447 | * we can ignore the bits. |
| 448 | */ |
| 449 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && |
| 450 | (host->data->blocks == 1)) |
| 451 | mask = ~0; |
| 452 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 453 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
Anton Vorontsov | 3e3bf20 | 2009-03-17 00:14:00 +0300 | [diff] [blame] | 454 | if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) |
| 455 | udelay(100); |
| 456 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 457 | if (host->data->flags & MMC_DATA_READ) |
| 458 | sdhci_read_block_pio(host); |
| 459 | else |
| 460 | sdhci_write_block_pio(host); |
| 461 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 462 | host->blocks--; |
| 463 | if (host->blocks == 0) |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 464 | break; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 465 | } |
| 466 | |
| 467 | DBG("PIO transfer complete.\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 468 | } |
| 469 | |
Russell King | 48857d9 | 2016-01-26 13:40:16 +0000 | [diff] [blame] | 470 | static int sdhci_pre_dma_transfer(struct sdhci_host *host, |
Russell King | c0999b7 | 2016-01-26 13:40:27 +0000 | [diff] [blame] | 471 | struct mmc_data *data, int cookie) |
Russell King | 48857d9 | 2016-01-26 13:40:16 +0000 | [diff] [blame] | 472 | { |
| 473 | int sg_count; |
| 474 | |
Russell King | 94538e5 | 2016-01-26 13:40:37 +0000 | [diff] [blame] | 475 | /* |
| 476 | * If the data buffers are already mapped, return the previous |
| 477 | * dma_map_sg() result. |
| 478 | */ |
| 479 | if (data->host_cookie == COOKIE_PRE_MAPPED) |
Russell King | 48857d9 | 2016-01-26 13:40:16 +0000 | [diff] [blame] | 480 | return data->sg_count; |
Russell King | 48857d9 | 2016-01-26 13:40:16 +0000 | [diff] [blame] | 481 | |
| 482 | sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, |
| 483 | data->flags & MMC_DATA_WRITE ? |
| 484 | DMA_TO_DEVICE : DMA_FROM_DEVICE); |
| 485 | |
| 486 | if (sg_count == 0) |
| 487 | return -ENOSPC; |
| 488 | |
| 489 | data->sg_count = sg_count; |
Russell King | c0999b7 | 2016-01-26 13:40:27 +0000 | [diff] [blame] | 490 | data->host_cookie = cookie; |
Russell King | 48857d9 | 2016-01-26 13:40:16 +0000 | [diff] [blame] | 491 | |
| 492 | return sg_count; |
| 493 | } |
| 494 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 495 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
| 496 | { |
| 497 | local_irq_save(*flags); |
Cong Wang | 482fce9 | 2011-11-27 13:27:00 +0800 | [diff] [blame] | 498 | return kmap_atomic(sg_page(sg)) + sg->offset; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 499 | } |
| 500 | |
| 501 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) |
| 502 | { |
Cong Wang | 482fce9 | 2011-11-27 13:27:00 +0800 | [diff] [blame] | 503 | kunmap_atomic(buffer); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 504 | local_irq_restore(*flags); |
| 505 | } |
| 506 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 507 | static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc, |
| 508 | dma_addr_t addr, int len, unsigned cmd) |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 509 | { |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 510 | struct sdhci_adma2_64_desc *dma_desc = desc; |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 511 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 512 | /* 32-bit and 64-bit descriptors have these members in same position */ |
Adrian Hunter | 0545230 | 2014-11-04 12:42:45 +0200 | [diff] [blame] | 513 | dma_desc->cmd = cpu_to_le16(cmd); |
| 514 | dma_desc->len = cpu_to_le16(len); |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 515 | dma_desc->addr_lo = cpu_to_le32((u32)addr); |
| 516 | |
| 517 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
| 518 | dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 519 | } |
| 520 | |
Adrian Hunter | b5ffa67 | 2014-11-04 12:42:40 +0200 | [diff] [blame] | 521 | static void sdhci_adma_mark_end(void *desc) |
| 522 | { |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 523 | struct sdhci_adma2_64_desc *dma_desc = desc; |
Adrian Hunter | b5ffa67 | 2014-11-04 12:42:40 +0200 | [diff] [blame] | 524 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 525 | /* 32-bit and 64-bit descriptors have 'cmd' in same position */ |
Adrian Hunter | 0545230 | 2014-11-04 12:42:45 +0200 | [diff] [blame] | 526 | dma_desc->cmd |= cpu_to_le16(ADMA2_END); |
Adrian Hunter | b5ffa67 | 2014-11-04 12:42:40 +0200 | [diff] [blame] | 527 | } |
| 528 | |
Russell King | 60c6476 | 2016-01-26 13:40:22 +0000 | [diff] [blame] | 529 | static void sdhci_adma_table_pre(struct sdhci_host *host, |
| 530 | struct mmc_data *data, int sg_count) |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 531 | { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 532 | struct scatterlist *sg; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 533 | unsigned long flags; |
Russell King | acc3ad1 | 2016-01-26 13:40:00 +0000 | [diff] [blame] | 534 | dma_addr_t addr, align_addr; |
| 535 | void *desc, *align; |
| 536 | char *buffer; |
| 537 | int len, offset, i; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 538 | |
| 539 | /* |
| 540 | * The spec does not specify endianness of descriptor table. |
| 541 | * We currently guess that it is LE. |
| 542 | */ |
| 543 | |
Russell King | 60c6476 | 2016-01-26 13:40:22 +0000 | [diff] [blame] | 544 | host->sg_count = sg_count; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 545 | |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 546 | desc = host->adma_table; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 547 | align = host->align_buffer; |
| 548 | |
| 549 | align_addr = host->align_addr; |
| 550 | |
| 551 | for_each_sg(data->sg, sg, host->sg_count, i) { |
| 552 | addr = sg_dma_address(sg); |
| 553 | len = sg_dma_len(sg); |
| 554 | |
| 555 | /* |
Russell King | acc3ad1 | 2016-01-26 13:40:00 +0000 | [diff] [blame] | 556 | * The SDHCI specification states that ADMA addresses must |
| 557 | * be 32-bit aligned. If they aren't, then we use a bounce |
| 558 | * buffer for the (up to three) bytes that screw up the |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 559 | * alignment. |
| 560 | */ |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 561 | offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & |
| 562 | SDHCI_ADMA2_MASK; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 563 | if (offset) { |
| 564 | if (data->flags & MMC_DATA_WRITE) { |
| 565 | buffer = sdhci_kmap_atomic(sg, &flags); |
| 566 | memcpy(align, buffer, offset); |
| 567 | sdhci_kunmap_atomic(buffer, &flags); |
| 568 | } |
| 569 | |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 570 | /* tran, valid */ |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 571 | sdhci_adma_write_desc(host, desc, align_addr, offset, |
Adrian Hunter | 739d46d | 2014-11-04 12:42:44 +0200 | [diff] [blame] | 572 | ADMA2_TRAN_VALID); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 573 | |
| 574 | BUG_ON(offset > 65536); |
| 575 | |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 576 | align += SDHCI_ADMA2_ALIGN; |
| 577 | align_addr += SDHCI_ADMA2_ALIGN; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 578 | |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 579 | desc += host->desc_sz; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 580 | |
| 581 | addr += offset; |
| 582 | len -= offset; |
| 583 | } |
| 584 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 585 | BUG_ON(len > 65536); |
| 586 | |
Adrian Hunter | 347ea32 | 2015-11-26 14:00:48 +0200 | [diff] [blame] | 587 | if (len) { |
| 588 | /* tran, valid */ |
| 589 | sdhci_adma_write_desc(host, desc, addr, len, |
| 590 | ADMA2_TRAN_VALID); |
| 591 | desc += host->desc_sz; |
| 592 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 593 | |
| 594 | /* |
| 595 | * If this triggers then we have a calculation bug |
| 596 | * somewhere. :/ |
| 597 | */ |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 598 | WARN_ON((desc - host->adma_table) >= host->adma_table_sz); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 599 | } |
| 600 | |
Thomas Abraham | 70764a9 | 2010-05-26 14:42:04 -0700 | [diff] [blame] | 601 | if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { |
Russell King | acc3ad1 | 2016-01-26 13:40:00 +0000 | [diff] [blame] | 602 | /* Mark the last descriptor as the terminating descriptor */ |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 603 | if (desc != host->adma_table) { |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 604 | desc -= host->desc_sz; |
Adrian Hunter | b5ffa67 | 2014-11-04 12:42:40 +0200 | [diff] [blame] | 605 | sdhci_adma_mark_end(desc); |
Thomas Abraham | 70764a9 | 2010-05-26 14:42:04 -0700 | [diff] [blame] | 606 | } |
| 607 | } else { |
Russell King | acc3ad1 | 2016-01-26 13:40:00 +0000 | [diff] [blame] | 608 | /* Add a terminating entry - nop, end, valid */ |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 609 | sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID); |
Thomas Abraham | 70764a9 | 2010-05-26 14:42:04 -0700 | [diff] [blame] | 610 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 611 | } |
| 612 | |
| 613 | static void sdhci_adma_table_post(struct sdhci_host *host, |
| 614 | struct mmc_data *data) |
| 615 | { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 616 | struct scatterlist *sg; |
| 617 | int i, size; |
Adrian Hunter | 1c3d5f6 | 2014-11-04 12:42:41 +0200 | [diff] [blame] | 618 | void *align; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 619 | char *buffer; |
| 620 | unsigned long flags; |
| 621 | |
Russell King | 47fa961 | 2016-01-26 13:40:06 +0000 | [diff] [blame] | 622 | if (data->flags & MMC_DATA_READ) { |
| 623 | bool has_unaligned = false; |
Russell King | de0b65a | 2014-04-25 12:58:29 +0100 | [diff] [blame] | 624 | |
Russell King | 47fa961 | 2016-01-26 13:40:06 +0000 | [diff] [blame] | 625 | /* Do a quick scan of the SG list for any unaligned mappings */ |
| 626 | for_each_sg(data->sg, sg, host->sg_count, i) |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 627 | if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { |
Russell King | 47fa961 | 2016-01-26 13:40:06 +0000 | [diff] [blame] | 628 | has_unaligned = true; |
| 629 | break; |
| 630 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 631 | |
Russell King | 47fa961 | 2016-01-26 13:40:06 +0000 | [diff] [blame] | 632 | if (has_unaligned) { |
| 633 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, |
Russell King | f55c98f | 2016-01-26 13:40:11 +0000 | [diff] [blame] | 634 | data->sg_len, DMA_FROM_DEVICE); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 635 | |
Russell King | 47fa961 | 2016-01-26 13:40:06 +0000 | [diff] [blame] | 636 | align = host->align_buffer; |
| 637 | |
| 638 | for_each_sg(data->sg, sg, host->sg_count, i) { |
| 639 | if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { |
| 640 | size = SDHCI_ADMA2_ALIGN - |
| 641 | (sg_dma_address(sg) & SDHCI_ADMA2_MASK); |
| 642 | |
| 643 | buffer = sdhci_kmap_atomic(sg, &flags); |
| 644 | memcpy(buffer, align, size); |
| 645 | sdhci_kunmap_atomic(buffer, &flags); |
| 646 | |
| 647 | align += SDHCI_ADMA2_ALIGN; |
| 648 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 649 | } |
| 650 | } |
| 651 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 652 | } |
| 653 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 654 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 655 | { |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 656 | u8 count; |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 657 | struct mmc_data *data = cmd->data; |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 658 | unsigned target_timeout, current_timeout; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 659 | |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 660 | /* |
| 661 | * If the host controller provides us with an incorrect timeout |
| 662 | * value, just skip the check and use 0xE. The hardware may take |
| 663 | * longer to time out, but that's much better than having a too-short |
| 664 | * timeout value. |
| 665 | */ |
Pierre Ossman | 11a2f1b | 2009-06-21 20:59:33 +0200 | [diff] [blame] | 666 | if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 667 | return 0xE; |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 668 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 669 | /* Unspecified timeout, assume max */ |
Ulf Hansson | 1d4d774 | 2014-01-08 15:06:08 +0100 | [diff] [blame] | 670 | if (!data && !cmd->busy_timeout) |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 671 | return 0xE; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 672 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 673 | /* timeout in us */ |
| 674 | if (!data) |
Ulf Hansson | 1d4d774 | 2014-01-08 15:06:08 +0100 | [diff] [blame] | 675 | target_timeout = cmd->busy_timeout * 1000; |
Andy Shevchenko | 78a2ca2 | 2011-08-03 18:35:59 +0300 | [diff] [blame] | 676 | else { |
Russell King | fafcfda | 2016-01-26 13:40:58 +0000 | [diff] [blame] | 677 | target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000); |
Russell King | 7f05538 | 2016-01-26 13:41:04 +0000 | [diff] [blame] | 678 | if (host->clock && data->timeout_clks) { |
| 679 | unsigned long long val; |
| 680 | |
| 681 | /* |
| 682 | * data->timeout_clks is in units of clock cycles. |
| 683 | * host->clock is in Hz. target_timeout is in us. |
| 684 | * Hence, us = 1000000 * cycles / Hz. Round up. |
| 685 | */ |
| 686 | val = 1000000 * data->timeout_clks; |
| 687 | if (do_div(val, host->clock)) |
| 688 | target_timeout++; |
| 689 | target_timeout += val; |
| 690 | } |
Andy Shevchenko | 78a2ca2 | 2011-08-03 18:35:59 +0300 | [diff] [blame] | 691 | } |
Anton Vorontsov | 81b3980 | 2009-09-22 16:45:13 -0700 | [diff] [blame] | 692 | |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 693 | /* |
| 694 | * Figure out needed cycles. |
| 695 | * We do this in steps in order to fit inside a 32 bit int. |
| 696 | * The first step is the minimum timeout, which will have a |
| 697 | * minimum resolution of 6 bits: |
| 698 | * (1) 2^13*1000 > 2^22, |
| 699 | * (2) host->timeout_clk < 2^16 |
| 700 | * => |
| 701 | * (1) / (2) > 2^6 |
| 702 | */ |
| 703 | count = 0; |
| 704 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; |
| 705 | while (current_timeout < target_timeout) { |
| 706 | count++; |
| 707 | current_timeout <<= 1; |
| 708 | if (count >= 0xF) |
| 709 | break; |
| 710 | } |
| 711 | |
| 712 | if (count >= 0xF) { |
Chris Ball | 09eeff5 | 2012-06-01 10:39:45 -0400 | [diff] [blame] | 713 | DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", |
| 714 | mmc_hostname(host->mmc), count, cmd->opcode); |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 715 | count = 0xE; |
| 716 | } |
| 717 | |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 718 | return count; |
| 719 | } |
| 720 | |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 721 | static void sdhci_set_transfer_irqs(struct sdhci_host *host) |
| 722 | { |
| 723 | u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; |
| 724 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; |
| 725 | |
| 726 | if (host->flags & SDHCI_REQ_USE_DMA) |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 727 | host->ier = (host->ier & ~pio_irqs) | dma_irqs; |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 728 | else |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 729 | host->ier = (host->ier & ~dma_irqs) | pio_irqs; |
| 730 | |
| 731 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 732 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 733 | } |
| 734 | |
Aisheng Dong | b45e668 | 2014-08-27 15:26:29 +0800 | [diff] [blame] | 735 | static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 736 | { |
| 737 | u8 count; |
Aisheng Dong | b45e668 | 2014-08-27 15:26:29 +0800 | [diff] [blame] | 738 | |
| 739 | if (host->ops->set_timeout) { |
| 740 | host->ops->set_timeout(host, cmd); |
| 741 | } else { |
| 742 | count = sdhci_calc_timeout(host, cmd); |
| 743 | sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); |
| 744 | } |
| 745 | } |
| 746 | |
| 747 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) |
| 748 | { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 749 | u8 ctrl; |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 750 | struct mmc_data *data = cmd->data; |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 751 | |
Adrian Hunter | 56a590d | 2016-06-29 16:24:32 +0300 | [diff] [blame^] | 752 | if (sdhci_data_line_cmd(cmd)) |
Aisheng Dong | b45e668 | 2014-08-27 15:26:29 +0800 | [diff] [blame] | 753 | sdhci_set_timeout(host, cmd); |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 754 | |
| 755 | if (!data) |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 756 | return; |
| 757 | |
Adrian Hunter | 43dea09 | 2016-06-29 16:24:26 +0300 | [diff] [blame] | 758 | WARN_ON(host->data); |
| 759 | |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 760 | /* Sanity checks */ |
| 761 | BUG_ON(data->blksz * data->blocks > 524288); |
| 762 | BUG_ON(data->blksz > host->mmc->max_blk_size); |
| 763 | BUG_ON(data->blocks > 65535); |
| 764 | |
| 765 | host->data = data; |
| 766 | host->data_early = 0; |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 767 | host->data->bytes_xfered = 0; |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 768 | |
Russell King | fce1442 | 2016-01-26 13:41:20 +0000 | [diff] [blame] | 769 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 770 | struct scatterlist *sg; |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 771 | unsigned int length_mask, offset_mask; |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 772 | int i; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 773 | |
Russell King | fce1442 | 2016-01-26 13:41:20 +0000 | [diff] [blame] | 774 | host->flags |= SDHCI_REQ_USE_DMA; |
| 775 | |
| 776 | /* |
| 777 | * FIXME: This doesn't account for merging when mapping the |
| 778 | * scatterlist. |
| 779 | * |
| 780 | * The assumption here being that alignment and lengths are |
| 781 | * the same after DMA mapping to device address space. |
| 782 | */ |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 783 | length_mask = 0; |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 784 | offset_mask = 0; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 785 | if (host->flags & SDHCI_USE_ADMA) { |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 786 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) { |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 787 | length_mask = 3; |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 788 | /* |
| 789 | * As we use up to 3 byte chunks to work |
| 790 | * around alignment problems, we need to |
| 791 | * check the offset as well. |
| 792 | */ |
| 793 | offset_mask = 3; |
| 794 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 795 | } else { |
| 796 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 797 | length_mask = 3; |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 798 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) |
| 799 | offset_mask = 3; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 800 | } |
| 801 | |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 802 | if (unlikely(length_mask | offset_mask)) { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 803 | for_each_sg(data->sg, sg, data->sg_len, i) { |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 804 | if (sg->length & length_mask) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 805 | DBG("Reverting to PIO because of transfer size (%d)\n", |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 806 | sg->length); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 807 | host->flags &= ~SDHCI_REQ_USE_DMA; |
| 808 | break; |
| 809 | } |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 810 | if (sg->offset & offset_mask) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 811 | DBG("Reverting to PIO because of bad alignment\n"); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 812 | host->flags &= ~SDHCI_REQ_USE_DMA; |
| 813 | break; |
| 814 | } |
| 815 | } |
| 816 | } |
| 817 | } |
| 818 | |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 819 | if (host->flags & SDHCI_REQ_USE_DMA) { |
Russell King | c0999b7 | 2016-01-26 13:40:27 +0000 | [diff] [blame] | 820 | int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED); |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 821 | |
Russell King | 60c6476 | 2016-01-26 13:40:22 +0000 | [diff] [blame] | 822 | if (sg_cnt <= 0) { |
| 823 | /* |
| 824 | * This only happens when someone fed |
| 825 | * us an invalid request. |
| 826 | */ |
| 827 | WARN_ON(1); |
| 828 | host->flags &= ~SDHCI_REQ_USE_DMA; |
| 829 | } else if (host->flags & SDHCI_USE_ADMA) { |
| 830 | sdhci_adma_table_pre(host, data, sg_cnt); |
| 831 | |
| 832 | sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS); |
| 833 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
| 834 | sdhci_writel(host, |
| 835 | (u64)host->adma_addr >> 32, |
| 836 | SDHCI_ADMA_ADDRESS_HI); |
| 837 | } else { |
| 838 | WARN_ON(sg_cnt != 1); |
| 839 | sdhci_writel(host, sg_dma_address(data->sg), |
| 840 | SDHCI_DMA_ADDRESS); |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 841 | } |
| 842 | } |
| 843 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 844 | /* |
| 845 | * Always adjust the DMA selection as some controllers |
| 846 | * (e.g. JMicron) can't do PIO properly when the selection |
| 847 | * is ADMA. |
| 848 | */ |
| 849 | if (host->version >= SDHCI_SPEC_200) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 850 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 851 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
| 852 | if ((host->flags & SDHCI_REQ_USE_DMA) && |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 853 | (host->flags & SDHCI_USE_ADMA)) { |
| 854 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
| 855 | ctrl |= SDHCI_CTRL_ADMA64; |
| 856 | else |
| 857 | ctrl |= SDHCI_CTRL_ADMA32; |
| 858 | } else { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 859 | ctrl |= SDHCI_CTRL_SDMA; |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 860 | } |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 861 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Pierre Ossman | c9fddbc | 2007-12-02 19:52:11 +0100 | [diff] [blame] | 862 | } |
| 863 | |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 864 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
Sebastian Andrzej Siewior | da60a91 | 2009-06-18 09:33:32 +0200 | [diff] [blame] | 865 | int flags; |
| 866 | |
| 867 | flags = SG_MITER_ATOMIC; |
| 868 | if (host->data->flags & MMC_DATA_READ) |
| 869 | flags |= SG_MITER_TO_SG; |
| 870 | else |
| 871 | flags |= SG_MITER_FROM_SG; |
| 872 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 873 | host->blocks = data->blocks; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 874 | } |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 875 | |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 876 | sdhci_set_transfer_irqs(host); |
| 877 | |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 878 | /* Set the DMA boundary value and block size */ |
| 879 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, |
| 880 | data->blksz), SDHCI_BLOCK_SIZE); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 881 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 882 | } |
| 883 | |
| 884 | static void sdhci_set_transfer_mode(struct sdhci_host *host, |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 885 | struct mmc_command *cmd) |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 886 | { |
Vincent Yang | d3fc5d7 | 2015-01-20 16:05:17 +0800 | [diff] [blame] | 887 | u16 mode = 0; |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 888 | struct mmc_data *data = cmd->data; |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 889 | |
Dong Aisheng | 2b558c1 | 2013-10-30 22:09:48 +0800 | [diff] [blame] | 890 | if (data == NULL) { |
Vincent Wan | 9b8ffea | 2014-11-05 14:09:00 +0800 | [diff] [blame] | 891 | if (host->quirks2 & |
| 892 | SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { |
| 893 | sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); |
| 894 | } else { |
Dong Aisheng | 2b558c1 | 2013-10-30 22:09:48 +0800 | [diff] [blame] | 895 | /* clear Auto CMD settings for no data CMDs */ |
Vincent Wan | 9b8ffea | 2014-11-05 14:09:00 +0800 | [diff] [blame] | 896 | mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); |
| 897 | sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | |
Dong Aisheng | 2b558c1 | 2013-10-30 22:09:48 +0800 | [diff] [blame] | 898 | SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); |
Vincent Wan | 9b8ffea | 2014-11-05 14:09:00 +0800 | [diff] [blame] | 899 | } |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 900 | return; |
Dong Aisheng | 2b558c1 | 2013-10-30 22:09:48 +0800 | [diff] [blame] | 901 | } |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 902 | |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 903 | WARN_ON(!host->data); |
| 904 | |
Vincent Yang | d3fc5d7 | 2015-01-20 16:05:17 +0800 | [diff] [blame] | 905 | if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) |
| 906 | mode = SDHCI_TRNS_BLK_CNT_EN; |
| 907 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 908 | if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { |
Vincent Yang | d3fc5d7 | 2015-01-20 16:05:17 +0800 | [diff] [blame] | 909 | mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 910 | /* |
| 911 | * If we are sending CMD23, CMD12 never gets sent |
| 912 | * on successful completion (so no Auto-CMD12). |
| 913 | */ |
Adrian Hunter | a4c73ab | 2016-06-29 16:24:25 +0300 | [diff] [blame] | 914 | if (!cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) && |
Corneliu Doban | 85cc1c3 | 2015-02-09 16:06:29 -0800 | [diff] [blame] | 915 | (cmd->opcode != SD_IO_RW_EXTENDED)) |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 916 | mode |= SDHCI_TRNS_AUTO_CMD12; |
Adrian Hunter | a4c73ab | 2016-06-29 16:24:25 +0300 | [diff] [blame] | 917 | else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 918 | mode |= SDHCI_TRNS_AUTO_CMD23; |
Adrian Hunter | a4c73ab | 2016-06-29 16:24:25 +0300 | [diff] [blame] | 919 | sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 920 | } |
Jerry Huang | c4512f7 | 2010-08-10 18:01:59 -0700 | [diff] [blame] | 921 | } |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 922 | |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 923 | if (data->flags & MMC_DATA_READ) |
| 924 | mode |= SDHCI_TRNS_READ; |
Pierre Ossman | c9fddbc | 2007-12-02 19:52:11 +0100 | [diff] [blame] | 925 | if (host->flags & SDHCI_REQ_USE_DMA) |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 926 | mode |= SDHCI_TRNS_DMA; |
| 927 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 928 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 929 | } |
| 930 | |
Adrian Hunter | 0cc563c | 2016-06-29 16:24:28 +0300 | [diff] [blame] | 931 | static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq) |
| 932 | { |
| 933 | return (!(host->flags & SDHCI_DEVICE_DEAD) && |
| 934 | ((mrq->cmd && mrq->cmd->error) || |
| 935 | (mrq->sbc && mrq->sbc->error) || |
| 936 | (mrq->data && ((mrq->data->error && !mrq->data->stop) || |
| 937 | (mrq->data->stop && mrq->data->stop->error))) || |
| 938 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))); |
| 939 | } |
| 940 | |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 941 | static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) |
| 942 | { |
Adrian Hunter | 5a8a3fe | 2016-06-29 16:24:30 +0300 | [diff] [blame] | 943 | if (host->cmd && host->cmd->mrq == mrq) |
| 944 | host->cmd = NULL; |
| 945 | |
| 946 | if (host->data_cmd && host->data_cmd->mrq == mrq) |
| 947 | host->data_cmd = NULL; |
| 948 | |
| 949 | if (host->data && host->data->mrq == mrq) |
| 950 | host->data = NULL; |
| 951 | |
Adrian Hunter | ed1563d | 2016-06-29 16:24:29 +0300 | [diff] [blame] | 952 | if (sdhci_needs_reset(host, mrq)) |
| 953 | host->pending_reset = true; |
| 954 | |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 955 | tasklet_schedule(&host->finish_tasklet); |
| 956 | } |
| 957 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 958 | static void sdhci_finish_data(struct sdhci_host *host) |
| 959 | { |
| 960 | struct mmc_data *data; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 961 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 962 | data = host->data; |
| 963 | host->data = NULL; |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 964 | host->data_cmd = NULL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 965 | |
Russell King | add8913 | 2016-01-26 13:40:42 +0000 | [diff] [blame] | 966 | if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) == |
| 967 | (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) |
| 968 | sdhci_adma_table_post(host, data); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 969 | |
| 970 | /* |
Pierre Ossman | c9b74c5 | 2008-04-18 20:41:49 +0200 | [diff] [blame] | 971 | * The specification states that the block count register must |
| 972 | * be updated, but it does not specify at what point in the |
| 973 | * data flow. That makes the register entirely useless to read |
| 974 | * back so we have to assume that nothing made it to the card |
| 975 | * in the event of an error. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 976 | */ |
Pierre Ossman | c9b74c5 | 2008-04-18 20:41:49 +0200 | [diff] [blame] | 977 | if (data->error) |
| 978 | data->bytes_xfered = 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 979 | else |
Pierre Ossman | c9b74c5 | 2008-04-18 20:41:49 +0200 | [diff] [blame] | 980 | data->bytes_xfered = data->blksz * data->blocks; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 981 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 982 | /* |
| 983 | * Need to send CMD12 if - |
| 984 | * a) open-ended multiblock transfer (no CMD23) |
| 985 | * b) error in multiblock transfer |
| 986 | */ |
| 987 | if (data->stop && |
| 988 | (data->error || |
Adrian Hunter | a4c73ab | 2016-06-29 16:24:25 +0300 | [diff] [blame] | 989 | !data->mrq->sbc)) { |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 990 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 991 | /* |
| 992 | * The controller needs a reset of internal state machines |
| 993 | * upon error conditions. |
| 994 | */ |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 995 | if (data->error) { |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 996 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
| 997 | sdhci_do_reset(host, SDHCI_RESET_DATA); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 998 | } |
| 999 | |
| 1000 | sdhci_send_command(host, data->stop); |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 1001 | } else { |
| 1002 | sdhci_finish_mrq(host, data->mrq); |
| 1003 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1004 | } |
| 1005 | |
Dong Aisheng | c0e55129 | 2013-09-13 19:11:31 +0800 | [diff] [blame] | 1006 | void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1007 | { |
| 1008 | int flags; |
Pierre Ossman | fd2208d | 2006-06-30 02:22:28 -0700 | [diff] [blame] | 1009 | u32 mask; |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1010 | unsigned long timeout; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1011 | |
| 1012 | WARN_ON(host->cmd); |
| 1013 | |
Russell King | 9677620 | 2016-01-26 13:39:34 +0000 | [diff] [blame] | 1014 | /* Initially, a command has no error */ |
| 1015 | cmd->error = 0; |
| 1016 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1017 | /* Wait max 10 ms */ |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1018 | timeout = 10; |
Pierre Ossman | fd2208d | 2006-06-30 02:22:28 -0700 | [diff] [blame] | 1019 | |
| 1020 | mask = SDHCI_CMD_INHIBIT; |
Adrian Hunter | 56a590d | 2016-06-29 16:24:32 +0300 | [diff] [blame^] | 1021 | if (sdhci_data_line_cmd(cmd)) |
Pierre Ossman | fd2208d | 2006-06-30 02:22:28 -0700 | [diff] [blame] | 1022 | mask |= SDHCI_DATA_INHIBIT; |
| 1023 | |
| 1024 | /* We shouldn't wait for data inihibit for stop commands, even |
| 1025 | though they might use busy signaling */ |
Adrian Hunter | a4c73ab | 2016-06-29 16:24:25 +0300 | [diff] [blame] | 1026 | if (cmd->mrq->data && (cmd == cmd->mrq->data->stop)) |
Pierre Ossman | fd2208d | 2006-06-30 02:22:28 -0700 | [diff] [blame] | 1027 | mask &= ~SDHCI_DATA_INHIBIT; |
| 1028 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1029 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1030 | if (timeout == 0) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 1031 | pr_err("%s: Controller never released inhibit bit(s).\n", |
| 1032 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1033 | sdhci_dumpregs(host); |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1034 | cmd->error = -EIO; |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 1035 | sdhci_finish_mrq(host, cmd->mrq); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1036 | return; |
| 1037 | } |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1038 | timeout--; |
| 1039 | mdelay(1); |
| 1040 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1041 | |
Adrian Hunter | 3e1a689 | 2013-11-14 10:16:20 +0200 | [diff] [blame] | 1042 | timeout = jiffies; |
Ulf Hansson | 1d4d774 | 2014-01-08 15:06:08 +0100 | [diff] [blame] | 1043 | if (!cmd->data && cmd->busy_timeout > 9000) |
| 1044 | timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; |
Adrian Hunter | 3e1a689 | 2013-11-14 10:16:20 +0200 | [diff] [blame] | 1045 | else |
| 1046 | timeout += 10 * HZ; |
| 1047 | mod_timer(&host->timer, timeout); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1048 | |
| 1049 | host->cmd = cmd; |
Adrian Hunter | 56a590d | 2016-06-29 16:24:32 +0300 | [diff] [blame^] | 1050 | if (sdhci_data_line_cmd(cmd)) { |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 1051 | WARN_ON(host->data_cmd); |
| 1052 | host->data_cmd = cmd; |
| 1053 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1054 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 1055 | sdhci_prepare_data(host, cmd); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1056 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1057 | sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1058 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1059 | sdhci_set_transfer_mode(host, cmd); |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 1060 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1061 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 1062 | pr_err("%s: Unsupported response type!\n", |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1063 | mmc_hostname(host->mmc)); |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1064 | cmd->error = -EINVAL; |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 1065 | sdhci_finish_mrq(host, cmd->mrq); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1066 | return; |
| 1067 | } |
| 1068 | |
| 1069 | if (!(cmd->flags & MMC_RSP_PRESENT)) |
| 1070 | flags = SDHCI_CMD_RESP_NONE; |
| 1071 | else if (cmd->flags & MMC_RSP_136) |
| 1072 | flags = SDHCI_CMD_RESP_LONG; |
| 1073 | else if (cmd->flags & MMC_RSP_BUSY) |
| 1074 | flags = SDHCI_CMD_RESP_SHORT_BUSY; |
| 1075 | else |
| 1076 | flags = SDHCI_CMD_RESP_SHORT; |
| 1077 | |
| 1078 | if (cmd->flags & MMC_RSP_CRC) |
| 1079 | flags |= SDHCI_CMD_CRC; |
| 1080 | if (cmd->flags & MMC_RSP_OPCODE) |
| 1081 | flags |= SDHCI_CMD_INDEX; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1082 | |
| 1083 | /* CMD19 is special in that the Data Present Select should be set */ |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1084 | if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || |
| 1085 | cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1086 | flags |= SDHCI_CMD_DATA; |
| 1087 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1088 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1089 | } |
Dong Aisheng | c0e55129 | 2013-09-13 19:11:31 +0800 | [diff] [blame] | 1090 | EXPORT_SYMBOL_GPL(sdhci_send_command); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1091 | |
| 1092 | static void sdhci_finish_command(struct sdhci_host *host) |
| 1093 | { |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1094 | struct mmc_command *cmd = host->cmd; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1095 | int i; |
| 1096 | |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1097 | host->cmd = NULL; |
| 1098 | |
| 1099 | if (cmd->flags & MMC_RSP_PRESENT) { |
| 1100 | if (cmd->flags & MMC_RSP_136) { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1101 | /* CRC is stripped so we need to do some shifting. */ |
| 1102 | for (i = 0;i < 4;i++) { |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1103 | cmd->resp[i] = sdhci_readl(host, |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1104 | SDHCI_RESPONSE + (3-i)*4) << 8; |
| 1105 | if (i != 3) |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1106 | cmd->resp[i] |= |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1107 | sdhci_readb(host, |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1108 | SDHCI_RESPONSE + (3-i)*4-1); |
| 1109 | } |
| 1110 | } else { |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1111 | cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1112 | } |
| 1113 | } |
| 1114 | |
Adrian Hunter | 6bde868 | 2016-06-29 16:24:20 +0300 | [diff] [blame] | 1115 | /* |
| 1116 | * The host can send and interrupt when the busy state has |
| 1117 | * ended, allowing us to wait without wasting CPU cycles. |
| 1118 | * The busy signal uses DAT0 so this is similar to waiting |
| 1119 | * for data to complete. |
| 1120 | * |
| 1121 | * Note: The 1.0 specification is a bit ambiguous about this |
| 1122 | * feature so there might be some problems with older |
| 1123 | * controllers. |
| 1124 | */ |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1125 | if (cmd->flags & MMC_RSP_BUSY) { |
| 1126 | if (cmd->data) { |
Adrian Hunter | 6bde868 | 2016-06-29 16:24:20 +0300 | [diff] [blame] | 1127 | DBG("Cannot wait for busy signal when also doing a data transfer"); |
| 1128 | } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && |
Adrian Hunter | ea96802 | 2016-06-29 16:24:24 +0300 | [diff] [blame] | 1129 | cmd == host->data_cmd) { |
| 1130 | /* Command complete before busy is ended */ |
Adrian Hunter | 6bde868 | 2016-06-29 16:24:20 +0300 | [diff] [blame] | 1131 | return; |
| 1132 | } |
| 1133 | } |
| 1134 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1135 | /* Finished CMD23, now send actual command. */ |
Adrian Hunter | a4c73ab | 2016-06-29 16:24:25 +0300 | [diff] [blame] | 1136 | if (cmd == cmd->mrq->sbc) { |
| 1137 | sdhci_send_command(host, cmd->mrq->cmd); |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1138 | } else { |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 1139 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1140 | /* Processed actual command. */ |
| 1141 | if (host->data && host->data_early) |
| 1142 | sdhci_finish_data(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1143 | |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1144 | if (!cmd->data) |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 1145 | sdhci_finish_mrq(host, cmd->mrq); |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1146 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1147 | } |
| 1148 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1149 | static u16 sdhci_get_preset_value(struct sdhci_host *host) |
| 1150 | { |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1151 | u16 preset = 0; |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1152 | |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1153 | switch (host->timing) { |
| 1154 | case MMC_TIMING_UHS_SDR12: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1155 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); |
| 1156 | break; |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1157 | case MMC_TIMING_UHS_SDR25: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1158 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); |
| 1159 | break; |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1160 | case MMC_TIMING_UHS_SDR50: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1161 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); |
| 1162 | break; |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1163 | case MMC_TIMING_UHS_SDR104: |
| 1164 | case MMC_TIMING_MMC_HS200: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1165 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); |
| 1166 | break; |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1167 | case MMC_TIMING_UHS_DDR50: |
Jisheng Zhang | 0dafa60 | 2015-08-18 16:21:39 +0800 | [diff] [blame] | 1168 | case MMC_TIMING_MMC_DDR52: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1169 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); |
| 1170 | break; |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 1171 | case MMC_TIMING_MMC_HS400: |
| 1172 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); |
| 1173 | break; |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1174 | default: |
| 1175 | pr_warn("%s: Invalid UHS-I mode selected\n", |
| 1176 | mmc_hostname(host->mmc)); |
| 1177 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); |
| 1178 | break; |
| 1179 | } |
| 1180 | return preset; |
| 1181 | } |
| 1182 | |
Ludovic Desroches | fb9ee04 | 2016-04-07 11:13:08 +0200 | [diff] [blame] | 1183 | u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, |
| 1184 | unsigned int *actual_clock) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1185 | { |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1186 | int div = 0; /* Initialized for compiler warning */ |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1187 | int real_div = div, clk_mul = 1; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1188 | u16 clk = 0; |
ludovic.desroches@atmel.com | 5497159 | 2015-07-29 16:22:46 +0200 | [diff] [blame] | 1189 | bool switch_base_clk = false; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1190 | |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1191 | if (host->version >= SDHCI_SPEC_300) { |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 1192 | if (host->preset_enabled) { |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1193 | u16 pre_val; |
| 1194 | |
| 1195 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 1196 | pre_val = sdhci_get_preset_value(host); |
| 1197 | div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) |
| 1198 | >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; |
| 1199 | if (host->clk_mul && |
| 1200 | (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { |
| 1201 | clk = SDHCI_PROG_CLOCK_MODE; |
| 1202 | real_div = div + 1; |
| 1203 | clk_mul = host->clk_mul; |
| 1204 | } else { |
| 1205 | real_div = max_t(int, 1, div << 1); |
| 1206 | } |
| 1207 | goto clock_set; |
| 1208 | } |
| 1209 | |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1210 | /* |
| 1211 | * Check if the Host Controller supports Programmable Clock |
| 1212 | * Mode. |
| 1213 | */ |
| 1214 | if (host->clk_mul) { |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1215 | for (div = 1; div <= 1024; div++) { |
| 1216 | if ((host->max_clk * host->clk_mul / div) |
| 1217 | <= clock) |
| 1218 | break; |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1219 | } |
ludovic.desroches@atmel.com | 5497159 | 2015-07-29 16:22:46 +0200 | [diff] [blame] | 1220 | if ((host->max_clk * host->clk_mul / div) <= clock) { |
| 1221 | /* |
| 1222 | * Set Programmable Clock Mode in the Clock |
| 1223 | * Control register. |
| 1224 | */ |
| 1225 | clk = SDHCI_PROG_CLOCK_MODE; |
| 1226 | real_div = div; |
| 1227 | clk_mul = host->clk_mul; |
| 1228 | div--; |
| 1229 | } else { |
| 1230 | /* |
| 1231 | * Divisor can be too small to reach clock |
| 1232 | * speed requirement. Then use the base clock. |
| 1233 | */ |
| 1234 | switch_base_clk = true; |
| 1235 | } |
| 1236 | } |
| 1237 | |
| 1238 | if (!host->clk_mul || switch_base_clk) { |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1239 | /* Version 3.00 divisors must be a multiple of 2. */ |
| 1240 | if (host->max_clk <= clock) |
| 1241 | div = 1; |
| 1242 | else { |
| 1243 | for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; |
| 1244 | div += 2) { |
| 1245 | if ((host->max_clk / div) <= clock) |
| 1246 | break; |
| 1247 | } |
| 1248 | } |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1249 | real_div = div; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1250 | div >>= 1; |
Suneel Garapati | d1955c3 | 2015-06-09 13:01:50 +0530 | [diff] [blame] | 1251 | if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) |
| 1252 | && !div && host->max_clk <= 25000000) |
| 1253 | div = 1; |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1254 | } |
| 1255 | } else { |
| 1256 | /* Version 2.00 divisors must be a power of 2. */ |
Zhangfei Gao | 0397526 | 2010-09-20 15:15:18 -0400 | [diff] [blame] | 1257 | for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1258 | if ((host->max_clk / div) <= clock) |
| 1259 | break; |
| 1260 | } |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1261 | real_div = div; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1262 | div >>= 1; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1263 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1264 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1265 | clock_set: |
Aisheng Dong | 03d6f5f | 2014-08-27 15:26:32 +0800 | [diff] [blame] | 1266 | if (real_div) |
Ludovic Desroches | fb9ee04 | 2016-04-07 11:13:08 +0200 | [diff] [blame] | 1267 | *actual_clock = (host->max_clk * clk_mul) / real_div; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1268 | clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1269 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) |
| 1270 | << SDHCI_DIVIDER_HI_SHIFT; |
Ludovic Desroches | fb9ee04 | 2016-04-07 11:13:08 +0200 | [diff] [blame] | 1271 | |
| 1272 | return clk; |
| 1273 | } |
| 1274 | EXPORT_SYMBOL_GPL(sdhci_calc_clk); |
| 1275 | |
| 1276 | void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) |
| 1277 | { |
| 1278 | u16 clk; |
| 1279 | unsigned long timeout; |
| 1280 | |
| 1281 | host->mmc->actual_clock = 0; |
| 1282 | |
| 1283 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
Ludovic Desroches | fb9ee04 | 2016-04-07 11:13:08 +0200 | [diff] [blame] | 1284 | |
| 1285 | if (clock == 0) |
| 1286 | return; |
| 1287 | |
| 1288 | clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); |
| 1289 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1290 | clk |= SDHCI_CLOCK_INT_EN; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1291 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1292 | |
Chris Ball | 27f6cb1 | 2009-09-22 16:45:31 -0700 | [diff] [blame] | 1293 | /* Wait max 20 ms */ |
| 1294 | timeout = 20; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1295 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1296 | & SDHCI_CLOCK_INT_STABLE)) { |
| 1297 | if (timeout == 0) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 1298 | pr_err("%s: Internal clock never stabilised.\n", |
| 1299 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1300 | sdhci_dumpregs(host); |
| 1301 | return; |
| 1302 | } |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1303 | timeout--; |
| 1304 | mdelay(1); |
| 1305 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1306 | |
| 1307 | clk |= SDHCI_CLOCK_CARD_EN; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1308 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1309 | } |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 1310 | EXPORT_SYMBOL_GPL(sdhci_set_clock); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1311 | |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 1312 | static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode, |
| 1313 | unsigned short vdd) |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1314 | { |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 1315 | struct mmc_host *mmc = host->mmc; |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 1316 | |
| 1317 | spin_unlock_irq(&host->lock); |
| 1318 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); |
| 1319 | spin_lock_irq(&host->lock); |
| 1320 | |
| 1321 | if (mode != MMC_POWER_OFF) |
| 1322 | sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL); |
| 1323 | else |
| 1324 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
| 1325 | } |
| 1326 | |
| 1327 | void sdhci_set_power(struct sdhci_host *host, unsigned char mode, |
| 1328 | unsigned short vdd) |
| 1329 | { |
Giuseppe Cavallaro | 8364248 | 2010-09-28 10:41:28 +0200 | [diff] [blame] | 1330 | u8 pwr = 0; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1331 | |
Russell King | 24fbb3c | 2014-04-25 13:00:06 +0100 | [diff] [blame] | 1332 | if (mode != MMC_POWER_OFF) { |
| 1333 | switch (1 << vdd) { |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 1334 | case MMC_VDD_165_195: |
| 1335 | pwr = SDHCI_POWER_180; |
| 1336 | break; |
| 1337 | case MMC_VDD_29_30: |
| 1338 | case MMC_VDD_30_31: |
| 1339 | pwr = SDHCI_POWER_300; |
| 1340 | break; |
| 1341 | case MMC_VDD_32_33: |
| 1342 | case MMC_VDD_33_34: |
| 1343 | pwr = SDHCI_POWER_330; |
| 1344 | break; |
| 1345 | default: |
Adrian Hunter | 9d5de93 | 2015-11-26 14:00:46 +0200 | [diff] [blame] | 1346 | WARN(1, "%s: Invalid vdd %#x\n", |
| 1347 | mmc_hostname(host->mmc), vdd); |
| 1348 | break; |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 1349 | } |
| 1350 | } |
| 1351 | |
| 1352 | if (host->pwr == pwr) |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1353 | return; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1354 | |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 1355 | host->pwr = pwr; |
| 1356 | |
| 1357 | if (pwr == 0) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1358 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
Adrian Hunter | f0710a5 | 2013-05-06 12:17:32 +0300 | [diff] [blame] | 1359 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
| 1360 | sdhci_runtime_pm_bus_off(host); |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1361 | } else { |
| 1362 | /* |
| 1363 | * Spec says that we should clear the power reg before setting |
| 1364 | * a new value. Some controllers don't seem to like this though. |
| 1365 | */ |
| 1366 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) |
| 1367 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
Darren Salt | 9e9dc5f | 2007-01-27 15:32:31 +0100 | [diff] [blame] | 1368 | |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1369 | /* |
| 1370 | * At least the Marvell CaFe chip gets confused if we set the |
| 1371 | * voltage and set turn on power at the same time, so set the |
| 1372 | * voltage first. |
| 1373 | */ |
| 1374 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) |
| 1375 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1376 | |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1377 | pwr |= SDHCI_POWER_ON; |
| 1378 | |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 1379 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
| 1380 | |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1381 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
| 1382 | sdhci_runtime_pm_bus_on(host); |
Andres Salomon | e08c169 | 2008-07-04 10:00:03 -0700 | [diff] [blame] | 1383 | |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1384 | /* |
| 1385 | * Some controllers need an extra 10ms delay of 10ms before |
| 1386 | * they can apply clock after applying power |
| 1387 | */ |
| 1388 | if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) |
| 1389 | mdelay(10); |
| 1390 | } |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 1391 | } |
| 1392 | EXPORT_SYMBOL_GPL(sdhci_set_power); |
Jisheng Zhang | 918f4cb | 2015-12-11 21:36:29 +0800 | [diff] [blame] | 1393 | |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 1394 | static void __sdhci_set_power(struct sdhci_host *host, unsigned char mode, |
| 1395 | unsigned short vdd) |
| 1396 | { |
| 1397 | struct mmc_host *mmc = host->mmc; |
| 1398 | |
| 1399 | if (host->ops->set_power) |
| 1400 | host->ops->set_power(host, mode, vdd); |
| 1401 | else if (!IS_ERR(mmc->supply.vmmc)) |
| 1402 | sdhci_set_power_reg(host, mode, vdd); |
| 1403 | else |
| 1404 | sdhci_set_power(host, mode, vdd); |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1405 | } |
| 1406 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1407 | /*****************************************************************************\ |
| 1408 | * * |
| 1409 | * MMC callbacks * |
| 1410 | * * |
| 1411 | \*****************************************************************************/ |
| 1412 | |
| 1413 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
| 1414 | { |
| 1415 | struct sdhci_host *host; |
Shawn Guo | 505a868 | 2012-12-11 15:23:42 +0800 | [diff] [blame] | 1416 | int present; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1417 | unsigned long flags; |
| 1418 | |
| 1419 | host = mmc_priv(mmc); |
| 1420 | |
Scott Branden | 04e079c | 2015-03-10 11:35:10 -0700 | [diff] [blame] | 1421 | /* Firstly check card presence */ |
Adrian Hunter | 8d28b7a | 2016-02-09 16:12:36 +0200 | [diff] [blame] | 1422 | present = mmc->ops->get_cd(mmc); |
Krzysztof Kozlowski | 2836766 | 2015-01-05 10:50:15 +0100 | [diff] [blame] | 1423 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1424 | spin_lock_irqsave(&host->lock, flags); |
| 1425 | |
| 1426 | WARN_ON(host->mrq != NULL); |
| 1427 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 1428 | sdhci_led_activate(host); |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1429 | |
| 1430 | /* |
| 1431 | * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED |
| 1432 | * requests if Auto-CMD12 is enabled. |
| 1433 | */ |
| 1434 | if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { |
Jerry Huang | c4512f7 | 2010-08-10 18:01:59 -0700 | [diff] [blame] | 1435 | if (mrq->stop) { |
| 1436 | mrq->data->stop = NULL; |
| 1437 | mrq->stop = NULL; |
| 1438 | } |
| 1439 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1440 | |
| 1441 | host->mrq = mrq; |
| 1442 | |
Anton Vorontsov | 68d1fb7 | 2009-03-17 00:13:52 +0300 | [diff] [blame] | 1443 | if (!present || host->flags & SDHCI_DEVICE_DEAD) { |
Adrian Hunter | a4c73ab | 2016-06-29 16:24:25 +0300 | [diff] [blame] | 1444 | mrq->cmd->error = -ENOMEDIUM; |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 1445 | sdhci_finish_mrq(host, mrq); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 1446 | } else { |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 1447 | if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1448 | sdhci_send_command(host, mrq->sbc); |
| 1449 | else |
| 1450 | sdhci_send_command(host, mrq->cmd); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 1451 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1452 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 1453 | mmiowb(); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1454 | spin_unlock_irqrestore(&host->lock, flags); |
| 1455 | } |
| 1456 | |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 1457 | void sdhci_set_bus_width(struct sdhci_host *host, int width) |
| 1458 | { |
| 1459 | u8 ctrl; |
| 1460 | |
| 1461 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
| 1462 | if (width == MMC_BUS_WIDTH_8) { |
| 1463 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
| 1464 | if (host->version >= SDHCI_SPEC_300) |
| 1465 | ctrl |= SDHCI_CTRL_8BITBUS; |
| 1466 | } else { |
| 1467 | if (host->version >= SDHCI_SPEC_300) |
| 1468 | ctrl &= ~SDHCI_CTRL_8BITBUS; |
| 1469 | if (width == MMC_BUS_WIDTH_4) |
| 1470 | ctrl |= SDHCI_CTRL_4BITBUS; |
| 1471 | else |
| 1472 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
| 1473 | } |
| 1474 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
| 1475 | } |
| 1476 | EXPORT_SYMBOL_GPL(sdhci_set_bus_width); |
| 1477 | |
Russell King | 96d7b78 | 2014-04-25 12:59:26 +0100 | [diff] [blame] | 1478 | void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) |
| 1479 | { |
| 1480 | u16 ctrl_2; |
| 1481 | |
| 1482 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1483 | /* Select Bus Speed Mode for host */ |
| 1484 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; |
| 1485 | if ((timing == MMC_TIMING_MMC_HS200) || |
| 1486 | (timing == MMC_TIMING_UHS_SDR104)) |
| 1487 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; |
| 1488 | else if (timing == MMC_TIMING_UHS_SDR12) |
| 1489 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; |
| 1490 | else if (timing == MMC_TIMING_UHS_SDR25) |
| 1491 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; |
| 1492 | else if (timing == MMC_TIMING_UHS_SDR50) |
| 1493 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; |
| 1494 | else if ((timing == MMC_TIMING_UHS_DDR50) || |
| 1495 | (timing == MMC_TIMING_MMC_DDR52)) |
| 1496 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 1497 | else if (timing == MMC_TIMING_MMC_HS400) |
| 1498 | ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ |
Russell King | 96d7b78 | 2014-04-25 12:59:26 +0100 | [diff] [blame] | 1499 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
| 1500 | } |
| 1501 | EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); |
| 1502 | |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 1503 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1504 | { |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 1505 | struct sdhci_host *host = mmc_priv(mmc); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1506 | unsigned long flags; |
| 1507 | u8 ctrl; |
| 1508 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1509 | spin_lock_irqsave(&host->lock, flags); |
| 1510 | |
Adrian Hunter | ceb6143 | 2011-12-27 15:48:41 +0200 | [diff] [blame] | 1511 | if (host->flags & SDHCI_DEVICE_DEAD) { |
| 1512 | spin_unlock_irqrestore(&host->lock, flags); |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 1513 | if (!IS_ERR(mmc->supply.vmmc) && |
| 1514 | ios->power_mode == MMC_POWER_OFF) |
Markus Mayer | 4e743f1 | 2014-07-03 13:27:42 -0700 | [diff] [blame] | 1515 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); |
Adrian Hunter | ceb6143 | 2011-12-27 15:48:41 +0200 | [diff] [blame] | 1516 | return; |
| 1517 | } |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 1518 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1519 | /* |
| 1520 | * Reset the chip on each power off. |
| 1521 | * Should clear out any weird states. |
| 1522 | */ |
| 1523 | if (ios->power_mode == MMC_POWER_OFF) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1524 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 1525 | sdhci_reinit(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1526 | } |
| 1527 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1528 | if (host->version >= SDHCI_SPEC_300 && |
Dong Aisheng | 372c463 | 2013-10-18 19:48:50 +0800 | [diff] [blame] | 1529 | (ios->power_mode == MMC_POWER_UP) && |
| 1530 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1531 | sdhci_enable_preset_value(host, false); |
| 1532 | |
Russell King | 373073e | 2014-04-25 12:58:45 +0100 | [diff] [blame] | 1533 | if (!ios->clock || ios->clock != host->clock) { |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 1534 | host->ops->set_clock(host, ios->clock); |
Russell King | 373073e | 2014-04-25 12:58:45 +0100 | [diff] [blame] | 1535 | host->clock = ios->clock; |
Aisheng Dong | 03d6f5f | 2014-08-27 15:26:32 +0800 | [diff] [blame] | 1536 | |
| 1537 | if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && |
| 1538 | host->clock) { |
| 1539 | host->timeout_clk = host->mmc->actual_clock ? |
| 1540 | host->mmc->actual_clock / 1000 : |
| 1541 | host->clock / 1000; |
| 1542 | host->mmc->max_busy_timeout = |
| 1543 | host->ops->get_max_timeout_count ? |
| 1544 | host->ops->get_max_timeout_count(host) : |
| 1545 | 1 << 27; |
| 1546 | host->mmc->max_busy_timeout /= host->timeout_clk; |
| 1547 | } |
Russell King | 373073e | 2014-04-25 12:58:45 +0100 | [diff] [blame] | 1548 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1549 | |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 1550 | __sdhci_set_power(host, ios->power_mode, ios->vdd); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1551 | |
Philip Rakity | 643a81f | 2010-09-23 08:24:32 -0700 | [diff] [blame] | 1552 | if (host->ops->platform_send_init_74_clocks) |
| 1553 | host->ops->platform_send_init_74_clocks(host, ios->power_mode); |
| 1554 | |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 1555 | host->ops->set_bus_width(host, ios->bus_width); |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 1556 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1557 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | cd9277c | 2007-02-18 12:07:47 +0100 | [diff] [blame] | 1558 | |
Philip Rakity | 3ab9c8d | 2010-10-06 11:57:23 -0700 | [diff] [blame] | 1559 | if ((ios->timing == MMC_TIMING_SD_HS || |
| 1560 | ios->timing == MMC_TIMING_MMC_HS) |
| 1561 | && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) |
Pierre Ossman | cd9277c | 2007-02-18 12:07:47 +0100 | [diff] [blame] | 1562 | ctrl |= SDHCI_CTRL_HISPD; |
| 1563 | else |
| 1564 | ctrl &= ~SDHCI_CTRL_HISPD; |
| 1565 | |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1566 | if (host->version >= SDHCI_SPEC_300) { |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1567 | u16 clk, ctrl_2; |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1568 | |
| 1569 | /* In case of UHS-I modes, set High Speed Enable */ |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 1570 | if ((ios->timing == MMC_TIMING_MMC_HS400) || |
| 1571 | (ios->timing == MMC_TIMING_MMC_HS200) || |
Seungwon Jeon | bb8175a | 2014-03-14 21:12:48 +0900 | [diff] [blame] | 1572 | (ios->timing == MMC_TIMING_MMC_DDR52) || |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1573 | (ios->timing == MMC_TIMING_UHS_SDR50) || |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1574 | (ios->timing == MMC_TIMING_UHS_SDR104) || |
| 1575 | (ios->timing == MMC_TIMING_UHS_DDR50) || |
Alexander Elbs | dd8df17 | 2012-01-03 23:26:53 -0500 | [diff] [blame] | 1576 | (ios->timing == MMC_TIMING_UHS_SDR25)) |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1577 | ctrl |= SDHCI_CTRL_HISPD; |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1578 | |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 1579 | if (!host->preset_enabled) { |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 1580 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1581 | /* |
| 1582 | * We only need to set Driver Strength if the |
| 1583 | * preset value enable is not set. |
| 1584 | */ |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 1585 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1586 | ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; |
| 1587 | if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) |
| 1588 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; |
Petri Gynther | 43e943a | 2015-05-20 14:35:00 -0700 | [diff] [blame] | 1589 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B) |
| 1590 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1591 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) |
| 1592 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; |
Petri Gynther | 43e943a | 2015-05-20 14:35:00 -0700 | [diff] [blame] | 1593 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D) |
| 1594 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D; |
| 1595 | else { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 1596 | pr_warn("%s: invalid driver type, default to driver type B\n", |
| 1597 | mmc_hostname(mmc)); |
Petri Gynther | 43e943a | 2015-05-20 14:35:00 -0700 | [diff] [blame] | 1598 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; |
| 1599 | } |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1600 | |
| 1601 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 1602 | } else { |
| 1603 | /* |
| 1604 | * According to SDHC Spec v3.00, if the Preset Value |
| 1605 | * Enable in the Host Control 2 register is set, we |
| 1606 | * need to reset SD Clock Enable before changing High |
| 1607 | * Speed Enable to avoid generating clock gliches. |
| 1608 | */ |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 1609 | |
| 1610 | /* Reset SD Clock Enable */ |
| 1611 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 1612 | clk &= ~SDHCI_CLOCK_CARD_EN; |
| 1613 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
| 1614 | |
| 1615 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
| 1616 | |
| 1617 | /* Re-enable SD Clock */ |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 1618 | host->ops->set_clock(host, host->clock); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1619 | } |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1620 | |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1621 | /* Reset SD Clock Enable */ |
| 1622 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 1623 | clk &= ~SDHCI_CLOCK_CARD_EN; |
| 1624 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
| 1625 | |
Russell King | 96d7b78 | 2014-04-25 12:59:26 +0100 | [diff] [blame] | 1626 | host->ops->set_uhs_signaling(host, ios->timing); |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1627 | host->timing = ios->timing; |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1628 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1629 | if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && |
| 1630 | ((ios->timing == MMC_TIMING_UHS_SDR12) || |
| 1631 | (ios->timing == MMC_TIMING_UHS_SDR25) || |
| 1632 | (ios->timing == MMC_TIMING_UHS_SDR50) || |
| 1633 | (ios->timing == MMC_TIMING_UHS_SDR104) || |
Jisheng Zhang | 0dafa60 | 2015-08-18 16:21:39 +0800 | [diff] [blame] | 1634 | (ios->timing == MMC_TIMING_UHS_DDR50) || |
| 1635 | (ios->timing == MMC_TIMING_MMC_DDR52))) { |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1636 | u16 preset; |
| 1637 | |
| 1638 | sdhci_enable_preset_value(host, true); |
| 1639 | preset = sdhci_get_preset_value(host); |
| 1640 | ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) |
| 1641 | >> SDHCI_PRESET_DRV_SHIFT; |
| 1642 | } |
| 1643 | |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1644 | /* Re-enable SD Clock */ |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 1645 | host->ops->set_clock(host, host->clock); |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 1646 | } else |
| 1647 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1648 | |
Leandro Dorileo | b835226 | 2007-07-25 23:47:04 +0200 | [diff] [blame] | 1649 | /* |
| 1650 | * Some (ENE) controllers go apeshit on some ios operation, |
| 1651 | * signalling timeout and CRC errors even on CMD0. Resetting |
| 1652 | * it on each ios seems to solve the problem. |
| 1653 | */ |
Mohammad Jamal | c63705e | 2015-01-13 20:47:24 +0530 | [diff] [blame] | 1654 | if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 1655 | sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
Leandro Dorileo | b835226 | 2007-07-25 23:47:04 +0200 | [diff] [blame] | 1656 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 1657 | mmiowb(); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1658 | spin_unlock_irqrestore(&host->lock, flags); |
| 1659 | } |
| 1660 | |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 1661 | static int sdhci_get_cd(struct mmc_host *mmc) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1662 | { |
| 1663 | struct sdhci_host *host = mmc_priv(mmc); |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 1664 | int gpio_cd = mmc_gpio_get_cd(mmc); |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 1665 | |
| 1666 | if (host->flags & SDHCI_DEVICE_DEAD) |
| 1667 | return 0; |
| 1668 | |
Ivan T. Ivanov | 88af565 | 2015-07-06 15:16:19 +0300 | [diff] [blame] | 1669 | /* If nonremovable, assume that the card is always present. */ |
Jaehoon Chung | 860951c | 2016-06-21 10:13:26 +0900 | [diff] [blame] | 1670 | if (!mmc_card_is_removable(host->mmc)) |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 1671 | return 1; |
| 1672 | |
Ivan T. Ivanov | 88af565 | 2015-07-06 15:16:19 +0300 | [diff] [blame] | 1673 | /* |
| 1674 | * Try slot gpio detect, if defined it take precedence |
| 1675 | * over build in controller functionality |
| 1676 | */ |
Arnd Bergmann | 287980e | 2016-05-27 23:23:25 +0200 | [diff] [blame] | 1677 | if (gpio_cd >= 0) |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 1678 | return !!gpio_cd; |
| 1679 | |
Ivan T. Ivanov | 88af565 | 2015-07-06 15:16:19 +0300 | [diff] [blame] | 1680 | /* If polling, assume that the card is always present. */ |
| 1681 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) |
| 1682 | return 1; |
| 1683 | |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 1684 | /* Host native card detect */ |
| 1685 | return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); |
| 1686 | } |
| 1687 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1688 | static int sdhci_check_ro(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1689 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1690 | unsigned long flags; |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 1691 | int is_readonly; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1692 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1693 | spin_lock_irqsave(&host->lock, flags); |
| 1694 | |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 1695 | if (host->flags & SDHCI_DEVICE_DEAD) |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 1696 | is_readonly = 0; |
| 1697 | else if (host->ops->get_ro) |
| 1698 | is_readonly = host->ops->get_ro(host); |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 1699 | else |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 1700 | is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) |
| 1701 | & SDHCI_WRITE_PROTECT); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1702 | |
| 1703 | spin_unlock_irqrestore(&host->lock, flags); |
| 1704 | |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 1705 | /* This quirk needs to be replaced by a callback-function later */ |
| 1706 | return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? |
| 1707 | !is_readonly : is_readonly; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1708 | } |
| 1709 | |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1710 | #define SAMPLE_COUNT 5 |
| 1711 | |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 1712 | static int sdhci_get_ro(struct mmc_host *mmc) |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1713 | { |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 1714 | struct sdhci_host *host = mmc_priv(mmc); |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1715 | int i, ro_count; |
| 1716 | |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1717 | if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1718 | return sdhci_check_ro(host); |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1719 | |
| 1720 | ro_count = 0; |
| 1721 | for (i = 0; i < SAMPLE_COUNT; i++) { |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1722 | if (sdhci_check_ro(host)) { |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1723 | if (++ro_count > SAMPLE_COUNT / 2) |
| 1724 | return 1; |
| 1725 | } |
| 1726 | msleep(30); |
| 1727 | } |
| 1728 | return 0; |
| 1729 | } |
| 1730 | |
Adrian Hunter | 20758b6 | 2011-08-29 16:42:12 +0300 | [diff] [blame] | 1731 | static void sdhci_hw_reset(struct mmc_host *mmc) |
| 1732 | { |
| 1733 | struct sdhci_host *host = mmc_priv(mmc); |
| 1734 | |
| 1735 | if (host->ops && host->ops->hw_reset) |
| 1736 | host->ops->hw_reset(host); |
| 1737 | } |
| 1738 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1739 | static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) |
| 1740 | { |
Russell King | be13855 | 2014-04-25 12:55:56 +0100 | [diff] [blame] | 1741 | if (!(host->flags & SDHCI_DEVICE_DEAD)) { |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 1742 | if (enable) |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 1743 | host->ier |= SDHCI_INT_CARD_INT; |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 1744 | else |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 1745 | host->ier &= ~SDHCI_INT_CARD_INT; |
| 1746 | |
| 1747 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 1748 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 1749 | mmiowb(); |
| 1750 | } |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1751 | } |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1752 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1753 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
| 1754 | { |
| 1755 | struct sdhci_host *host = mmc_priv(mmc); |
| 1756 | unsigned long flags; |
| 1757 | |
| 1758 | spin_lock_irqsave(&host->lock, flags); |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 1759 | if (enable) |
| 1760 | host->flags |= SDHCI_SDIO_IRQ_ENABLED; |
| 1761 | else |
| 1762 | host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; |
| 1763 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1764 | sdhci_enable_sdio_irq_nolock(host, enable); |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1765 | spin_unlock_irqrestore(&host->lock, flags); |
| 1766 | } |
| 1767 | |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 1768 | static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, |
| 1769 | struct mmc_ios *ios) |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 1770 | { |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 1771 | struct sdhci_host *host = mmc_priv(mmc); |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 1772 | u16 ctrl; |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1773 | int ret; |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 1774 | |
| 1775 | /* |
| 1776 | * Signal Voltage Switching is only applicable for Host Controllers |
| 1777 | * v3.00 and above. |
| 1778 | */ |
| 1779 | if (host->version < SDHCI_SPEC_300) |
| 1780 | return 0; |
| 1781 | |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 1782 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1783 | |
Fabio Estevam | 21f5998 | 2013-02-14 10:35:03 -0200 | [diff] [blame] | 1784 | switch (ios->signal_voltage) { |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1785 | case MMC_SIGNAL_VOLTAGE_330: |
Adrian Hunter | 8cb851a | 2016-06-29 16:24:16 +0300 | [diff] [blame] | 1786 | if (!(host->flags & SDHCI_SIGNALING_330)) |
| 1787 | return -EINVAL; |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1788 | /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ |
| 1789 | ctrl &= ~SDHCI_CTRL_VDD_180; |
| 1790 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 1791 | |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 1792 | if (!IS_ERR(mmc->supply.vqmmc)) { |
| 1793 | ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000, |
| 1794 | 3600000); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1795 | if (ret) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 1796 | pr_warn("%s: Switching to 3.3V signalling voltage failed\n", |
| 1797 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1798 | return -EIO; |
| 1799 | } |
| 1800 | } |
| 1801 | /* Wait for 5ms */ |
| 1802 | usleep_range(5000, 5500); |
| 1803 | |
| 1804 | /* 3.3V regulator output should be stable within 5 ms */ |
| 1805 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1806 | if (!(ctrl & SDHCI_CTRL_VDD_180)) |
| 1807 | return 0; |
| 1808 | |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 1809 | pr_warn("%s: 3.3V regulator output did not became stable\n", |
| 1810 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1811 | |
| 1812 | return -EAGAIN; |
| 1813 | case MMC_SIGNAL_VOLTAGE_180: |
Adrian Hunter | 8cb851a | 2016-06-29 16:24:16 +0300 | [diff] [blame] | 1814 | if (!(host->flags & SDHCI_SIGNALING_180)) |
| 1815 | return -EINVAL; |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 1816 | if (!IS_ERR(mmc->supply.vqmmc)) { |
| 1817 | ret = regulator_set_voltage(mmc->supply.vqmmc, |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1818 | 1700000, 1950000); |
| 1819 | if (ret) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 1820 | pr_warn("%s: Switching to 1.8V signalling voltage failed\n", |
| 1821 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1822 | return -EIO; |
| 1823 | } |
| 1824 | } |
| 1825 | |
| 1826 | /* |
| 1827 | * Enable 1.8V Signal Enable in the Host Control2 |
| 1828 | * register |
| 1829 | */ |
| 1830 | ctrl |= SDHCI_CTRL_VDD_180; |
| 1831 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 1832 | |
Vincent Yang | 9d967a6 | 2015-01-20 16:05:15 +0800 | [diff] [blame] | 1833 | /* Some controller need to do more when switching */ |
| 1834 | if (host->ops->voltage_switch) |
| 1835 | host->ops->voltage_switch(host); |
| 1836 | |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1837 | /* 1.8V regulator output should be stable within 5 ms */ |
| 1838 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1839 | if (ctrl & SDHCI_CTRL_VDD_180) |
| 1840 | return 0; |
| 1841 | |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 1842 | pr_warn("%s: 1.8V regulator output did not became stable\n", |
| 1843 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1844 | |
| 1845 | return -EAGAIN; |
| 1846 | case MMC_SIGNAL_VOLTAGE_120: |
Adrian Hunter | 8cb851a | 2016-06-29 16:24:16 +0300 | [diff] [blame] | 1847 | if (!(host->flags & SDHCI_SIGNALING_120)) |
| 1848 | return -EINVAL; |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 1849 | if (!IS_ERR(mmc->supply.vqmmc)) { |
| 1850 | ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000, |
| 1851 | 1300000); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1852 | if (ret) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 1853 | pr_warn("%s: Switching to 1.2V signalling voltage failed\n", |
| 1854 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1855 | return -EIO; |
| 1856 | } |
| 1857 | } |
| 1858 | return 0; |
| 1859 | default: |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 1860 | /* No signal voltage switch required */ |
| 1861 | return 0; |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1862 | } |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 1863 | } |
| 1864 | |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1865 | static int sdhci_card_busy(struct mmc_host *mmc) |
| 1866 | { |
| 1867 | struct sdhci_host *host = mmc_priv(mmc); |
| 1868 | u32 present_state; |
| 1869 | |
Adrian Hunter | e613cc4 | 2016-06-23 14:00:58 +0300 | [diff] [blame] | 1870 | /* Check whether DAT[0] is 0 */ |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1871 | present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1872 | |
Adrian Hunter | e613cc4 | 2016-06-23 14:00:58 +0300 | [diff] [blame] | 1873 | return !(present_state & SDHCI_DATA_0_LVL_MASK); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1874 | } |
| 1875 | |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1876 | static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) |
| 1877 | { |
| 1878 | struct sdhci_host *host = mmc_priv(mmc); |
| 1879 | unsigned long flags; |
| 1880 | |
| 1881 | spin_lock_irqsave(&host->lock, flags); |
| 1882 | host->flags |= SDHCI_HS400_TUNING; |
| 1883 | spin_unlock_irqrestore(&host->lock, flags); |
| 1884 | |
| 1885 | return 0; |
| 1886 | } |
| 1887 | |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1888 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1889 | { |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1890 | struct sdhci_host *host = mmc_priv(mmc); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1891 | u16 ctrl; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1892 | int tuning_loop_counter = MAX_TUNING_LOOP; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1893 | int err = 0; |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 1894 | unsigned long flags; |
Adrian Hunter | 38e40bf | 2014-12-05 19:25:30 +0200 | [diff] [blame] | 1895 | unsigned int tuning_count = 0; |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1896 | bool hs400_tuning; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1897 | |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 1898 | spin_lock_irqsave(&host->lock, flags); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1899 | |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1900 | hs400_tuning = host->flags & SDHCI_HS400_TUNING; |
| 1901 | host->flags &= ~SDHCI_HS400_TUNING; |
| 1902 | |
Adrian Hunter | 38e40bf | 2014-12-05 19:25:30 +0200 | [diff] [blame] | 1903 | if (host->tuning_mode == SDHCI_TUNING_MODE_1) |
| 1904 | tuning_count = host->tuning_count; |
| 1905 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1906 | /* |
Weijun Yang | 9faac7b | 2015-10-04 12:04:12 +0000 | [diff] [blame] | 1907 | * The Host Controller needs tuning in case of SDR104 and DDR50 |
| 1908 | * mode, and for SDR50 mode when Use Tuning for SDR50 is set in |
| 1909 | * the Capabilities register. |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1910 | * If the Host Controller supports the HS200 mode then the |
| 1911 | * tuning function has to be executed. |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1912 | */ |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1913 | switch (host->timing) { |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1914 | /* HS400 tuning is done in HS200 mode */ |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 1915 | case MMC_TIMING_MMC_HS400: |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1916 | err = -EINVAL; |
| 1917 | goto out_unlock; |
| 1918 | |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1919 | case MMC_TIMING_MMC_HS200: |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1920 | /* |
| 1921 | * Periodic re-tuning for HS400 is not expected to be needed, so |
| 1922 | * disable it here. |
| 1923 | */ |
| 1924 | if (hs400_tuning) |
| 1925 | tuning_count = 0; |
| 1926 | break; |
| 1927 | |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1928 | case MMC_TIMING_UHS_SDR104: |
Weijun Yang | 9faac7b | 2015-10-04 12:04:12 +0000 | [diff] [blame] | 1929 | case MMC_TIMING_UHS_DDR50: |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1930 | break; |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1931 | |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1932 | case MMC_TIMING_UHS_SDR50: |
Adrian Hunter | 4228b21 | 2016-04-20 09:24:03 +0300 | [diff] [blame] | 1933 | if (host->flags & SDHCI_SDR50_NEEDS_TUNING) |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1934 | break; |
| 1935 | /* FALLTHROUGH */ |
| 1936 | |
| 1937 | default: |
Adrian Hunter | d519c86 | 2014-12-05 19:25:29 +0200 | [diff] [blame] | 1938 | goto out_unlock; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1939 | } |
| 1940 | |
Dong Aisheng | 4525181 | 2013-09-13 19:11:30 +0800 | [diff] [blame] | 1941 | if (host->ops->platform_execute_tuning) { |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 1942 | spin_unlock_irqrestore(&host->lock, flags); |
Dong Aisheng | 4525181 | 2013-09-13 19:11:30 +0800 | [diff] [blame] | 1943 | err = host->ops->platform_execute_tuning(host, opcode); |
Dong Aisheng | 4525181 | 2013-09-13 19:11:30 +0800 | [diff] [blame] | 1944 | return err; |
| 1945 | } |
| 1946 | |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1947 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1948 | ctrl |= SDHCI_CTRL_EXEC_TUNING; |
Vincent Yang | 67d0d04 | 2015-01-20 16:05:16 +0800 | [diff] [blame] | 1949 | if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND) |
| 1950 | ctrl |= SDHCI_CTRL_TUNED_CLK; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1951 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 1952 | |
| 1953 | /* |
| 1954 | * As per the Host Controller spec v3.00, tuning command |
| 1955 | * generates Buffer Read Ready interrupt, so enable that. |
| 1956 | * |
| 1957 | * Note: The spec clearly says that when tuning sequence |
| 1958 | * is being performed, the controller does not generate |
| 1959 | * interrupts other than Buffer Read Ready interrupt. But |
| 1960 | * to make sure we don't hit a controller bug, we _only_ |
| 1961 | * enable Buffer Read Ready interrupt here. |
| 1962 | */ |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 1963 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); |
| 1964 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1965 | |
| 1966 | /* |
| 1967 | * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number |
Simon Horman | 1473bdd | 2016-05-13 13:24:31 +0900 | [diff] [blame] | 1968 | * of loops reaches 40 times. |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1969 | */ |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1970 | do { |
| 1971 | struct mmc_command cmd = {0}; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1972 | struct mmc_request mrq = {NULL}; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1973 | |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1974 | cmd.opcode = opcode; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1975 | cmd.arg = 0; |
| 1976 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; |
| 1977 | cmd.retries = 0; |
| 1978 | cmd.data = NULL; |
| 1979 | cmd.error = 0; |
| 1980 | |
Al Cooper | 7ce45e9 | 2014-05-09 11:34:07 -0400 | [diff] [blame] | 1981 | if (tuning_loop_counter-- == 0) |
| 1982 | break; |
| 1983 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1984 | mrq.cmd = &cmd; |
| 1985 | host->mrq = &mrq; |
| 1986 | |
| 1987 | /* |
| 1988 | * In response to CMD19, the card sends 64 bytes of tuning |
| 1989 | * block to the Host Controller. So we set the block size |
| 1990 | * to 64 here. |
| 1991 | */ |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1992 | if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { |
| 1993 | if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) |
| 1994 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), |
| 1995 | SDHCI_BLOCK_SIZE); |
| 1996 | else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
| 1997 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), |
| 1998 | SDHCI_BLOCK_SIZE); |
| 1999 | } else { |
| 2000 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), |
| 2001 | SDHCI_BLOCK_SIZE); |
| 2002 | } |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2003 | |
| 2004 | /* |
| 2005 | * The tuning block is sent by the card to the host controller. |
| 2006 | * So we set the TRNS_READ bit in the Transfer Mode register. |
| 2007 | * This also takes care of setting DMA Enable and Multi Block |
| 2008 | * Select in the same register to 0. |
| 2009 | */ |
| 2010 | sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); |
| 2011 | |
| 2012 | sdhci_send_command(host, &cmd); |
| 2013 | |
| 2014 | host->cmd = NULL; |
| 2015 | host->mrq = NULL; |
| 2016 | |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 2017 | spin_unlock_irqrestore(&host->lock, flags); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2018 | /* Wait for Buffer Read Ready interrupt */ |
| 2019 | wait_event_interruptible_timeout(host->buf_ready_int, |
| 2020 | (host->tuning_done == 1), |
| 2021 | msecs_to_jiffies(50)); |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 2022 | spin_lock_irqsave(&host->lock, flags); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2023 | |
| 2024 | if (!host->tuning_done) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2025 | pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n"); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2026 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 2027 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; |
| 2028 | ctrl &= ~SDHCI_CTRL_EXEC_TUNING; |
| 2029 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 2030 | |
| 2031 | err = -EIO; |
| 2032 | goto out; |
| 2033 | } |
| 2034 | |
| 2035 | host->tuning_done = 0; |
| 2036 | |
| 2037 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
Nick Sanders | 197160d | 2014-05-06 18:52:38 -0700 | [diff] [blame] | 2038 | |
| 2039 | /* eMMC spec does not require a delay between tuning cycles */ |
| 2040 | if (opcode == MMC_SEND_TUNING_BLOCK) |
| 2041 | mdelay(1); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2042 | } while (ctrl & SDHCI_CTRL_EXEC_TUNING); |
| 2043 | |
| 2044 | /* |
| 2045 | * The Host Driver has exhausted the maximum number of loops allowed, |
| 2046 | * so use fixed sampling frequency. |
| 2047 | */ |
Al Cooper | 7ce45e9 | 2014-05-09 11:34:07 -0400 | [diff] [blame] | 2048 | if (tuning_loop_counter < 0) { |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2049 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; |
| 2050 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
Al Cooper | 7ce45e9 | 2014-05-09 11:34:07 -0400 | [diff] [blame] | 2051 | } |
| 2052 | if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2053 | pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n"); |
Dong Aisheng | 114f2bf | 2013-10-18 19:48:45 +0800 | [diff] [blame] | 2054 | err = -EIO; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2055 | } |
| 2056 | |
| 2057 | out: |
Adrian Hunter | 38e40bf | 2014-12-05 19:25:30 +0200 | [diff] [blame] | 2058 | if (tuning_count) { |
Adrian Hunter | 66c39dfc | 2015-05-07 13:10:21 +0300 | [diff] [blame] | 2059 | /* |
| 2060 | * In case tuning fails, host controllers which support |
| 2061 | * re-tuning can try tuning again at a later time, when the |
| 2062 | * re-tuning timer expires. So for these controllers, we |
| 2063 | * return 0. Since there might be other controllers who do not |
| 2064 | * have this capability, we return error for them. |
| 2065 | */ |
| 2066 | err = 0; |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 2067 | } |
| 2068 | |
Adrian Hunter | 66c39dfc | 2015-05-07 13:10:21 +0300 | [diff] [blame] | 2069 | host->mmc->retune_period = err ? 0 : tuning_count; |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 2070 | |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 2071 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 2072 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Adrian Hunter | d519c86 | 2014-12-05 19:25:29 +0200 | [diff] [blame] | 2073 | out_unlock: |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 2074 | spin_unlock_irqrestore(&host->lock, flags); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2075 | return err; |
| 2076 | } |
| 2077 | |
Adrian Hunter | cb84964 | 2015-02-06 14:12:59 +0200 | [diff] [blame] | 2078 | static int sdhci_select_drive_strength(struct mmc_card *card, |
| 2079 | unsigned int max_dtr, int host_drv, |
| 2080 | int card_drv, int *drv_type) |
| 2081 | { |
| 2082 | struct sdhci_host *host = mmc_priv(card->host); |
| 2083 | |
| 2084 | if (!host->ops->select_drive_strength) |
| 2085 | return 0; |
| 2086 | |
| 2087 | return host->ops->select_drive_strength(host, card, max_dtr, host_drv, |
| 2088 | card_drv, drv_type); |
| 2089 | } |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 2090 | |
| 2091 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2092 | { |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2093 | /* Host Controller v3.00 defines preset value registers */ |
| 2094 | if (host->version < SDHCI_SPEC_300) |
| 2095 | return; |
| 2096 | |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2097 | /* |
| 2098 | * We only enable or disable Preset Value if they are not already |
| 2099 | * enabled or disabled respectively. Otherwise, we bail out. |
| 2100 | */ |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 2101 | if (host->preset_enabled != enable) { |
| 2102 | u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 2103 | |
| 2104 | if (enable) |
| 2105 | ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; |
| 2106 | else |
| 2107 | ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; |
| 2108 | |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2109 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 2110 | |
| 2111 | if (enable) |
| 2112 | host->flags |= SDHCI_PV_ENABLED; |
| 2113 | else |
| 2114 | host->flags &= ~SDHCI_PV_ENABLED; |
| 2115 | |
| 2116 | host->preset_enabled = enable; |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2117 | } |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2118 | } |
| 2119 | |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2120 | static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, |
| 2121 | int err) |
| 2122 | { |
| 2123 | struct sdhci_host *host = mmc_priv(mmc); |
| 2124 | struct mmc_data *data = mrq->data; |
| 2125 | |
Russell King | f48f039 | 2016-01-26 13:40:32 +0000 | [diff] [blame] | 2126 | if (data->host_cookie != COOKIE_UNMAPPED) |
Russell King | 771a3dc | 2016-01-26 13:40:53 +0000 | [diff] [blame] | 2127 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, |
| 2128 | data->flags & MMC_DATA_WRITE ? |
| 2129 | DMA_TO_DEVICE : DMA_FROM_DEVICE); |
| 2130 | |
| 2131 | data->host_cookie = COOKIE_UNMAPPED; |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2132 | } |
| 2133 | |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2134 | static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, |
| 2135 | bool is_first_req) |
| 2136 | { |
| 2137 | struct sdhci_host *host = mmc_priv(mmc); |
| 2138 | |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 2139 | mrq->data->host_cookie = COOKIE_UNMAPPED; |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2140 | |
| 2141 | if (host->flags & SDHCI_REQ_USE_DMA) |
Russell King | 94538e5 | 2016-01-26 13:40:37 +0000 | [diff] [blame] | 2142 | sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED); |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2143 | } |
| 2144 | |
Adrian Hunter | 5d0d11c | 2016-06-29 16:24:31 +0300 | [diff] [blame] | 2145 | static inline bool sdhci_has_requests(struct sdhci_host *host) |
| 2146 | { |
| 2147 | return host->cmd || host->data_cmd; |
| 2148 | } |
| 2149 | |
| 2150 | static void sdhci_error_out_mrqs(struct sdhci_host *host, int err) |
| 2151 | { |
| 2152 | if (host->data_cmd) { |
| 2153 | host->data_cmd->error = err; |
| 2154 | sdhci_finish_mrq(host, host->data_cmd->mrq); |
| 2155 | } |
| 2156 | |
| 2157 | if (host->cmd) { |
| 2158 | host->cmd->error = err; |
| 2159 | sdhci_finish_mrq(host, host->cmd->mrq); |
| 2160 | } |
| 2161 | } |
| 2162 | |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2163 | static void sdhci_card_event(struct mmc_host *mmc) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2164 | { |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2165 | struct sdhci_host *host = mmc_priv(mmc); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2166 | unsigned long flags; |
Krzysztof Kozlowski | 2836766 | 2015-01-05 10:50:15 +0100 | [diff] [blame] | 2167 | int present; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2168 | |
Christian Daudt | 722e128 | 2013-06-20 14:26:36 -0700 | [diff] [blame] | 2169 | /* First check if client has provided their own card event */ |
| 2170 | if (host->ops->card_event) |
| 2171 | host->ops->card_event(host); |
| 2172 | |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 2173 | present = mmc->ops->get_cd(mmc); |
Krzysztof Kozlowski | 2836766 | 2015-01-05 10:50:15 +0100 | [diff] [blame] | 2174 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2175 | spin_lock_irqsave(&host->lock, flags); |
| 2176 | |
Adrian Hunter | 5d0d11c | 2016-06-29 16:24:31 +0300 | [diff] [blame] | 2177 | /* Check sdhci_has_requests() first in case we are runtime suspended */ |
| 2178 | if (sdhci_has_requests(host) && !present) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2179 | pr_err("%s: Card removed during transfer!\n", |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2180 | mmc_hostname(host->mmc)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2181 | pr_err("%s: Resetting controller.\n", |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2182 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2183 | |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 2184 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
| 2185 | sdhci_do_reset(host, SDHCI_RESET_DATA); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2186 | |
Adrian Hunter | 5d0d11c | 2016-06-29 16:24:31 +0300 | [diff] [blame] | 2187 | sdhci_error_out_mrqs(host, -ENOMEDIUM); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2188 | } |
| 2189 | |
| 2190 | spin_unlock_irqrestore(&host->lock, flags); |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2191 | } |
| 2192 | |
| 2193 | static const struct mmc_host_ops sdhci_ops = { |
| 2194 | .request = sdhci_request, |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2195 | .post_req = sdhci_post_req, |
| 2196 | .pre_req = sdhci_pre_req, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2197 | .set_ios = sdhci_set_ios, |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 2198 | .get_cd = sdhci_get_cd, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2199 | .get_ro = sdhci_get_ro, |
| 2200 | .hw_reset = sdhci_hw_reset, |
| 2201 | .enable_sdio_irq = sdhci_enable_sdio_irq, |
| 2202 | .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 2203 | .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2204 | .execute_tuning = sdhci_execute_tuning, |
Adrian Hunter | cb84964 | 2015-02-06 14:12:59 +0200 | [diff] [blame] | 2205 | .select_drive_strength = sdhci_select_drive_strength, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2206 | .card_event = sdhci_card_event, |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2207 | .card_busy = sdhci_card_busy, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2208 | }; |
| 2209 | |
| 2210 | /*****************************************************************************\ |
| 2211 | * * |
| 2212 | * Tasklets * |
| 2213 | * * |
| 2214 | \*****************************************************************************/ |
| 2215 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2216 | static void sdhci_tasklet_finish(unsigned long param) |
| 2217 | { |
| 2218 | struct sdhci_host *host; |
| 2219 | unsigned long flags; |
| 2220 | struct mmc_request *mrq; |
| 2221 | |
| 2222 | host = (struct sdhci_host*)param; |
| 2223 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2224 | spin_lock_irqsave(&host->lock, flags); |
| 2225 | |
Chris Ball | 0c9c99a | 2011-04-27 17:35:31 -0400 | [diff] [blame] | 2226 | /* |
| 2227 | * If this tasklet gets rescheduled while running, it will |
| 2228 | * be run again afterwards but without any active request. |
| 2229 | */ |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2230 | if (!host->mrq) { |
| 2231 | spin_unlock_irqrestore(&host->lock, flags); |
Chris Ball | 0c9c99a | 2011-04-27 17:35:31 -0400 | [diff] [blame] | 2232 | return; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2233 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2234 | |
| 2235 | del_timer(&host->timer); |
| 2236 | |
| 2237 | mrq = host->mrq; |
| 2238 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2239 | /* |
Russell King | 054cedf | 2016-01-26 13:40:42 +0000 | [diff] [blame] | 2240 | * Always unmap the data buffers if they were mapped by |
| 2241 | * sdhci_prepare_data() whenever we finish with a request. |
| 2242 | * This avoids leaking DMA mappings on error. |
| 2243 | */ |
| 2244 | if (host->flags & SDHCI_REQ_USE_DMA) { |
| 2245 | struct mmc_data *data = mrq->data; |
| 2246 | |
| 2247 | if (data && data->host_cookie == COOKIE_MAPPED) { |
| 2248 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, |
| 2249 | (data->flags & MMC_DATA_READ) ? |
| 2250 | DMA_FROM_DEVICE : DMA_TO_DEVICE); |
| 2251 | data->host_cookie = COOKIE_UNMAPPED; |
| 2252 | } |
| 2253 | } |
| 2254 | |
| 2255 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2256 | * The controller needs a reset of internal state machines |
| 2257 | * upon error conditions. |
| 2258 | */ |
Adrian Hunter | 0cc563c | 2016-06-29 16:24:28 +0300 | [diff] [blame] | 2259 | if (sdhci_needs_reset(host, mrq)) { |
Pierre Ossman | 645289d | 2006-06-30 02:22:33 -0700 | [diff] [blame] | 2260 | /* Some controllers need this kick or reset won't work here */ |
Andy Shevchenko | 8213af3 | 2013-01-07 16:31:08 +0200 | [diff] [blame] | 2261 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) |
Pierre Ossman | 645289d | 2006-06-30 02:22:33 -0700 | [diff] [blame] | 2262 | /* This is to force an update */ |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 2263 | host->ops->set_clock(host, host->clock); |
Pierre Ossman | 645289d | 2006-06-30 02:22:33 -0700 | [diff] [blame] | 2264 | |
| 2265 | /* Spec says we should do both at the same time, but Ricoh |
| 2266 | controllers do not like that. */ |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 2267 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
| 2268 | sdhci_do_reset(host, SDHCI_RESET_DATA); |
Adrian Hunter | ed1563d | 2016-06-29 16:24:29 +0300 | [diff] [blame] | 2269 | |
| 2270 | host->pending_reset = false; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2271 | } |
| 2272 | |
| 2273 | host->mrq = NULL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2274 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 2275 | sdhci_led_deactivate(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2276 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 2277 | mmiowb(); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2278 | spin_unlock_irqrestore(&host->lock, flags); |
| 2279 | |
| 2280 | mmc_request_done(host->mmc, mrq); |
| 2281 | } |
| 2282 | |
| 2283 | static void sdhci_timeout_timer(unsigned long data) |
| 2284 | { |
| 2285 | struct sdhci_host *host; |
| 2286 | unsigned long flags; |
| 2287 | |
| 2288 | host = (struct sdhci_host*)data; |
| 2289 | |
| 2290 | spin_lock_irqsave(&host->lock, flags); |
| 2291 | |
| 2292 | if (host->mrq) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2293 | pr_err("%s: Timeout waiting for hardware interrupt.\n", |
| 2294 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2295 | sdhci_dumpregs(host); |
| 2296 | |
| 2297 | if (host->data) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2298 | host->data->error = -ETIMEDOUT; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2299 | sdhci_finish_data(host); |
| 2300 | } else { |
| 2301 | if (host->cmd) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2302 | host->cmd->error = -ETIMEDOUT; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2303 | else |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2304 | host->mrq->cmd->error = -ETIMEDOUT; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2305 | |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 2306 | sdhci_finish_mrq(host, host->mrq); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2307 | } |
| 2308 | } |
| 2309 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 2310 | mmiowb(); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2311 | spin_unlock_irqrestore(&host->lock, flags); |
| 2312 | } |
| 2313 | |
| 2314 | /*****************************************************************************\ |
| 2315 | * * |
| 2316 | * Interrupt handling * |
| 2317 | * * |
| 2318 | \*****************************************************************************/ |
| 2319 | |
Adrian Hunter | 6154139 | 2014-09-24 10:27:27 +0300 | [diff] [blame] | 2320 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2321 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2322 | if (!host->cmd) { |
Adrian Hunter | ed1563d | 2016-06-29 16:24:29 +0300 | [diff] [blame] | 2323 | /* |
| 2324 | * SDHCI recovers from errors by resetting the cmd and data |
| 2325 | * circuits. Until that is done, there very well might be more |
| 2326 | * interrupts, so ignore them in that case. |
| 2327 | */ |
| 2328 | if (host->pending_reset) |
| 2329 | return; |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2330 | pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", |
| 2331 | mmc_hostname(host->mmc), (unsigned)intmask); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2332 | sdhci_dumpregs(host); |
| 2333 | return; |
| 2334 | } |
| 2335 | |
Russell King | ec014cb | 2016-01-26 13:39:39 +0000 | [diff] [blame] | 2336 | if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | |
| 2337 | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) { |
| 2338 | if (intmask & SDHCI_INT_TIMEOUT) |
| 2339 | host->cmd->error = -ETIMEDOUT; |
| 2340 | else |
| 2341 | host->cmd->error = -EILSEQ; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2342 | |
Russell King | 71fcbda | 2016-01-26 13:39:45 +0000 | [diff] [blame] | 2343 | /* |
| 2344 | * If this command initiates a data phase and a response |
| 2345 | * CRC error is signalled, the card can start transferring |
| 2346 | * data - the card may have received the command without |
| 2347 | * error. We must not terminate the mmc_request early. |
| 2348 | * |
| 2349 | * If the card did not receive the command or returned an |
| 2350 | * error which prevented it sending data, the data phase |
| 2351 | * will time out. |
| 2352 | */ |
| 2353 | if (host->cmd->data && |
| 2354 | (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) == |
| 2355 | SDHCI_INT_CRC) { |
| 2356 | host->cmd = NULL; |
| 2357 | return; |
| 2358 | } |
| 2359 | |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 2360 | sdhci_finish_mrq(host, host->cmd->mrq); |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2361 | return; |
| 2362 | } |
| 2363 | |
Adrian Hunter | 6bde868 | 2016-06-29 16:24:20 +0300 | [diff] [blame] | 2364 | if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && |
| 2365 | !(host->cmd->flags & MMC_RSP_BUSY) && !host->data && |
| 2366 | host->cmd->opcode == MMC_STOP_TRANSMISSION) |
Adrian Hunter | 6154139 | 2014-09-24 10:27:27 +0300 | [diff] [blame] | 2367 | *mask &= ~SDHCI_INT_DATA_END; |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2368 | |
| 2369 | if (intmask & SDHCI_INT_RESPONSE) |
Pierre Ossman | 43b58b3 | 2007-07-25 23:15:27 +0200 | [diff] [blame] | 2370 | sdhci_finish_command(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2371 | } |
| 2372 | |
George G. Davis | 0957c33 | 2010-02-18 12:32:12 -0500 | [diff] [blame] | 2373 | #ifdef CONFIG_MMC_DEBUG |
Adrian Hunter | 08621b1 | 2014-11-04 12:42:38 +0200 | [diff] [blame] | 2374 | static void sdhci_adma_show_error(struct sdhci_host *host) |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2375 | { |
| 2376 | const char *name = mmc_hostname(host->mmc); |
Adrian Hunter | 1c3d5f6 | 2014-11-04 12:42:41 +0200 | [diff] [blame] | 2377 | void *desc = host->adma_table; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2378 | |
| 2379 | sdhci_dumpregs(host); |
| 2380 | |
| 2381 | while (true) { |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 2382 | struct sdhci_adma2_64_desc *dma_desc = desc; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2383 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 2384 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
| 2385 | DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", |
| 2386 | name, desc, le32_to_cpu(dma_desc->addr_hi), |
| 2387 | le32_to_cpu(dma_desc->addr_lo), |
| 2388 | le16_to_cpu(dma_desc->len), |
| 2389 | le16_to_cpu(dma_desc->cmd)); |
| 2390 | else |
| 2391 | DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", |
| 2392 | name, desc, le32_to_cpu(dma_desc->addr_lo), |
| 2393 | le16_to_cpu(dma_desc->len), |
| 2394 | le16_to_cpu(dma_desc->cmd)); |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2395 | |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 2396 | desc += host->desc_sz; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2397 | |
Adrian Hunter | 0545230 | 2014-11-04 12:42:45 +0200 | [diff] [blame] | 2398 | if (dma_desc->cmd & cpu_to_le16(ADMA2_END)) |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2399 | break; |
| 2400 | } |
| 2401 | } |
| 2402 | #else |
Adrian Hunter | 08621b1 | 2014-11-04 12:42:38 +0200 | [diff] [blame] | 2403 | static void sdhci_adma_show_error(struct sdhci_host *host) { } |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2404 | #endif |
| 2405 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2406 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) |
| 2407 | { |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 2408 | u32 command; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2409 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2410 | /* CMD19 generates _only_ Buffer Read Ready interrupt */ |
| 2411 | if (intmask & SDHCI_INT_DATA_AVAIL) { |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 2412 | command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); |
| 2413 | if (command == MMC_SEND_TUNING_BLOCK || |
| 2414 | command == MMC_SEND_TUNING_BLOCK_HS200) { |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2415 | host->tuning_done = 1; |
| 2416 | wake_up(&host->buf_ready_int); |
| 2417 | return; |
| 2418 | } |
| 2419 | } |
| 2420 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2421 | if (!host->data) { |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 2422 | struct mmc_command *data_cmd = host->data_cmd; |
| 2423 | |
| 2424 | if (data_cmd) |
| 2425 | host->data_cmd = NULL; |
| 2426 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2427 | /* |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2428 | * The "data complete" interrupt is also used to |
| 2429 | * indicate that a busy state has ended. See comment |
| 2430 | * above in sdhci_cmd_irq(). |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2431 | */ |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 2432 | if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) { |
Matthieu CASTET | c5abd5e | 2014-08-14 16:03:17 +0200 | [diff] [blame] | 2433 | if (intmask & SDHCI_INT_DATA_TIMEOUT) { |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 2434 | data_cmd->error = -ETIMEDOUT; |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 2435 | sdhci_finish_mrq(host, data_cmd->mrq); |
Matthieu CASTET | c5abd5e | 2014-08-14 16:03:17 +0200 | [diff] [blame] | 2436 | return; |
| 2437 | } |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2438 | if (intmask & SDHCI_INT_DATA_END) { |
Chanho Min | e99783a | 2014-08-30 12:40:40 +0900 | [diff] [blame] | 2439 | /* |
| 2440 | * Some cards handle busy-end interrupt |
| 2441 | * before the command completed, so make |
| 2442 | * sure we do things in the proper order. |
| 2443 | */ |
Adrian Hunter | ea96802 | 2016-06-29 16:24:24 +0300 | [diff] [blame] | 2444 | if (host->cmd == data_cmd) |
| 2445 | return; |
| 2446 | |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 2447 | sdhci_finish_mrq(host, data_cmd->mrq); |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2448 | return; |
| 2449 | } |
| 2450 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2451 | |
Adrian Hunter | ed1563d | 2016-06-29 16:24:29 +0300 | [diff] [blame] | 2452 | /* |
| 2453 | * SDHCI recovers from errors by resetting the cmd and data |
| 2454 | * circuits. Until that is done, there very well might be more |
| 2455 | * interrupts, so ignore them in that case. |
| 2456 | */ |
| 2457 | if (host->pending_reset) |
| 2458 | return; |
| 2459 | |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2460 | pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", |
| 2461 | mmc_hostname(host->mmc), (unsigned)intmask); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2462 | sdhci_dumpregs(host); |
| 2463 | |
| 2464 | return; |
| 2465 | } |
| 2466 | |
| 2467 | if (intmask & SDHCI_INT_DATA_TIMEOUT) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2468 | host->data->error = -ETIMEDOUT; |
Aries Lee | 22113ef | 2010-12-15 08:14:24 +0100 | [diff] [blame] | 2469 | else if (intmask & SDHCI_INT_DATA_END_BIT) |
| 2470 | host->data->error = -EILSEQ; |
| 2471 | else if ((intmask & SDHCI_INT_DATA_CRC) && |
| 2472 | SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) |
| 2473 | != MMC_BUS_TEST_R) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2474 | host->data->error = -EILSEQ; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2475 | else if (intmask & SDHCI_INT_ADMA_ERROR) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2476 | pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); |
Adrian Hunter | 08621b1 | 2014-11-04 12:42:38 +0200 | [diff] [blame] | 2477 | sdhci_adma_show_error(host); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2478 | host->data->error = -EIO; |
Haijun Zhang | a4071fb | 2012-12-04 10:41:28 +0800 | [diff] [blame] | 2479 | if (host->ops->adma_workaround) |
| 2480 | host->ops->adma_workaround(host, intmask); |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2481 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2482 | |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2483 | if (host->data->error) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2484 | sdhci_finish_data(host); |
| 2485 | else { |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 2486 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2487 | sdhci_transfer_pio(host); |
| 2488 | |
Pierre Ossman | 6ba736a | 2007-05-13 22:39:23 +0200 | [diff] [blame] | 2489 | /* |
| 2490 | * We currently don't do anything fancy with DMA |
| 2491 | * boundaries, but as we can't disable the feature |
| 2492 | * we need to at least restart the transfer. |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 2493 | * |
| 2494 | * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) |
| 2495 | * should return a valid address to continue from, but as |
| 2496 | * some controllers are faulty, don't trust them. |
Pierre Ossman | 6ba736a | 2007-05-13 22:39:23 +0200 | [diff] [blame] | 2497 | */ |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 2498 | if (intmask & SDHCI_INT_DMA_END) { |
| 2499 | u32 dmastart, dmanow; |
| 2500 | dmastart = sg_dma_address(host->data->sg); |
| 2501 | dmanow = dmastart + host->data->bytes_xfered; |
| 2502 | /* |
| 2503 | * Force update to the next DMA block boundary. |
| 2504 | */ |
| 2505 | dmanow = (dmanow & |
| 2506 | ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + |
| 2507 | SDHCI_DEFAULT_BOUNDARY_SIZE; |
| 2508 | host->data->bytes_xfered = dmanow - dmastart; |
| 2509 | DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," |
| 2510 | " next 0x%08x\n", |
| 2511 | mmc_hostname(host->mmc), dmastart, |
| 2512 | host->data->bytes_xfered, dmanow); |
| 2513 | sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); |
| 2514 | } |
Pierre Ossman | 6ba736a | 2007-05-13 22:39:23 +0200 | [diff] [blame] | 2515 | |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 2516 | if (intmask & SDHCI_INT_DATA_END) { |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 2517 | if (host->cmd == host->data_cmd) { |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 2518 | /* |
| 2519 | * Data managed to finish before the |
| 2520 | * command completed. Make sure we do |
| 2521 | * things in the proper order. |
| 2522 | */ |
| 2523 | host->data_early = 1; |
| 2524 | } else { |
| 2525 | sdhci_finish_data(host); |
| 2526 | } |
| 2527 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2528 | } |
| 2529 | } |
| 2530 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 2531 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2532 | { |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2533 | irqreturn_t result = IRQ_NONE; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2534 | struct sdhci_host *host = dev_id; |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2535 | u32 intmask, mask, unexpected = 0; |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2536 | int max_loops = 16; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2537 | |
| 2538 | spin_lock(&host->lock); |
| 2539 | |
Russell King | be13855 | 2014-04-25 12:55:56 +0100 | [diff] [blame] | 2540 | if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2541 | spin_unlock(&host->lock); |
Adrian Hunter | 655bca7 | 2014-03-11 10:09:36 +0200 | [diff] [blame] | 2542 | return IRQ_NONE; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2543 | } |
| 2544 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 2545 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
Mark Lord | 62df67a5 | 2007-03-06 13:30:13 +0100 | [diff] [blame] | 2546 | if (!intmask || intmask == 0xffffffff) { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2547 | result = IRQ_NONE; |
| 2548 | goto out; |
| 2549 | } |
| 2550 | |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2551 | do { |
| 2552 | /* Clear selected interrupts. */ |
| 2553 | mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | |
| 2554 | SDHCI_INT_BUS_POWER); |
| 2555 | sdhci_writel(host, mask, SDHCI_INT_STATUS); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2556 | |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2557 | DBG("*** %s got interrupt: 0x%08x\n", |
| 2558 | mmc_hostname(host->mmc), intmask); |
| 2559 | |
| 2560 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
| 2561 | u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & |
| 2562 | SDHCI_CARD_PRESENT; |
| 2563 | |
| 2564 | /* |
| 2565 | * There is a observation on i.mx esdhc. INSERT |
| 2566 | * bit will be immediately set again when it gets |
| 2567 | * cleared, if a card is inserted. We have to mask |
| 2568 | * the irq to prevent interrupt storm which will |
| 2569 | * freeze the system. And the REMOVE gets the |
| 2570 | * same situation. |
| 2571 | * |
| 2572 | * More testing are needed here to ensure it works |
| 2573 | * for other platforms though. |
| 2574 | */ |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 2575 | host->ier &= ~(SDHCI_INT_CARD_INSERT | |
| 2576 | SDHCI_INT_CARD_REMOVE); |
| 2577 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : |
| 2578 | SDHCI_INT_CARD_INSERT; |
| 2579 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 2580 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2581 | |
| 2582 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | |
| 2583 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); |
Russell King | 3560db8 | 2014-04-25 12:55:51 +0100 | [diff] [blame] | 2584 | |
| 2585 | host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | |
| 2586 | SDHCI_INT_CARD_REMOVE); |
| 2587 | result = IRQ_WAKE_THREAD; |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2588 | } |
| 2589 | |
| 2590 | if (intmask & SDHCI_INT_CMD_MASK) |
Adrian Hunter | 6154139 | 2014-09-24 10:27:27 +0300 | [diff] [blame] | 2591 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, |
| 2592 | &intmask); |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2593 | |
| 2594 | if (intmask & SDHCI_INT_DATA_MASK) |
| 2595 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
| 2596 | |
| 2597 | if (intmask & SDHCI_INT_BUS_POWER) |
| 2598 | pr_err("%s: Card is consuming too much power!\n", |
| 2599 | mmc_hostname(host->mmc)); |
| 2600 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2601 | if (intmask & SDHCI_INT_CARD_INT) { |
| 2602 | sdhci_enable_sdio_irq_nolock(host, false); |
| 2603 | host->thread_isr |= SDHCI_INT_CARD_INT; |
| 2604 | result = IRQ_WAKE_THREAD; |
| 2605 | } |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2606 | |
| 2607 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | |
| 2608 | SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | |
| 2609 | SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | |
| 2610 | SDHCI_INT_CARD_INT); |
| 2611 | |
| 2612 | if (intmask) { |
| 2613 | unexpected |= intmask; |
| 2614 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); |
| 2615 | } |
| 2616 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2617 | if (result == IRQ_NONE) |
| 2618 | result = IRQ_HANDLED; |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2619 | |
| 2620 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2621 | } while (intmask && --max_loops); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2622 | out: |
| 2623 | spin_unlock(&host->lock); |
| 2624 | |
Alexander Stein | 6379b23 | 2012-03-14 09:52:10 +0100 | [diff] [blame] | 2625 | if (unexpected) { |
| 2626 | pr_err("%s: Unexpected interrupt 0x%08x.\n", |
| 2627 | mmc_hostname(host->mmc), unexpected); |
| 2628 | sdhci_dumpregs(host); |
| 2629 | } |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 2630 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2631 | return result; |
| 2632 | } |
| 2633 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2634 | static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) |
| 2635 | { |
| 2636 | struct sdhci_host *host = dev_id; |
| 2637 | unsigned long flags; |
| 2638 | u32 isr; |
| 2639 | |
| 2640 | spin_lock_irqsave(&host->lock, flags); |
| 2641 | isr = host->thread_isr; |
| 2642 | host->thread_isr = 0; |
| 2643 | spin_unlock_irqrestore(&host->lock, flags); |
| 2644 | |
Russell King | 3560db8 | 2014-04-25 12:55:51 +0100 | [diff] [blame] | 2645 | if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 2646 | struct mmc_host *mmc = host->mmc; |
| 2647 | |
| 2648 | mmc->ops->card_event(mmc); |
| 2649 | mmc_detect_change(mmc, msecs_to_jiffies(200)); |
Russell King | 3560db8 | 2014-04-25 12:55:51 +0100 | [diff] [blame] | 2650 | } |
| 2651 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2652 | if (isr & SDHCI_INT_CARD_INT) { |
| 2653 | sdio_run_irqs(host->mmc); |
| 2654 | |
| 2655 | spin_lock_irqsave(&host->lock, flags); |
| 2656 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) |
| 2657 | sdhci_enable_sdio_irq_nolock(host, true); |
| 2658 | spin_unlock_irqrestore(&host->lock, flags); |
| 2659 | } |
| 2660 | |
| 2661 | return isr ? IRQ_HANDLED : IRQ_NONE; |
| 2662 | } |
| 2663 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2664 | /*****************************************************************************\ |
| 2665 | * * |
| 2666 | * Suspend/resume * |
| 2667 | * * |
| 2668 | \*****************************************************************************/ |
| 2669 | |
| 2670 | #ifdef CONFIG_PM |
Ludovic Desroches | 84d6260 | 2016-05-13 15:16:02 +0200 | [diff] [blame] | 2671 | /* |
| 2672 | * To enable wakeup events, the corresponding events have to be enabled in |
| 2673 | * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal |
| 2674 | * Table' in the SD Host Controller Standard Specification. |
| 2675 | * It is useless to restore SDHCI_INT_ENABLE state in |
| 2676 | * sdhci_disable_irq_wakeups() since it will be set by |
| 2677 | * sdhci_enable_card_detection() or sdhci_init(). |
| 2678 | */ |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2679 | void sdhci_enable_irq_wakeups(struct sdhci_host *host) |
| 2680 | { |
| 2681 | u8 val; |
| 2682 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
| 2683 | | SDHCI_WAKE_ON_INT; |
Ludovic Desroches | 84d6260 | 2016-05-13 15:16:02 +0200 | [diff] [blame] | 2684 | u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | |
| 2685 | SDHCI_INT_CARD_INT; |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2686 | |
| 2687 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); |
| 2688 | val |= mask ; |
| 2689 | /* Avoid fake wake up */ |
Ludovic Desroches | 84d6260 | 2016-05-13 15:16:02 +0200 | [diff] [blame] | 2690 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) { |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2691 | val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); |
Ludovic Desroches | 84d6260 | 2016-05-13 15:16:02 +0200 | [diff] [blame] | 2692 | irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); |
| 2693 | } |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2694 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); |
Ludovic Desroches | 84d6260 | 2016-05-13 15:16:02 +0200 | [diff] [blame] | 2695 | sdhci_writel(host, irq_val, SDHCI_INT_ENABLE); |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2696 | } |
| 2697 | EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); |
| 2698 | |
Fabio Estevam | 0b10f47 | 2014-08-30 14:53:13 -0300 | [diff] [blame] | 2699 | static void sdhci_disable_irq_wakeups(struct sdhci_host *host) |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2700 | { |
| 2701 | u8 val; |
| 2702 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
| 2703 | | SDHCI_WAKE_ON_INT; |
| 2704 | |
| 2705 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); |
| 2706 | val &= ~mask; |
| 2707 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); |
| 2708 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2709 | |
Manuel Lauss | 29495aa | 2011-11-03 11:09:45 +0100 | [diff] [blame] | 2710 | int sdhci_suspend_host(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2711 | { |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 2712 | sdhci_disable_card_detection(host); |
| 2713 | |
Adrian Hunter | 66c39dfc | 2015-05-07 13:10:21 +0300 | [diff] [blame] | 2714 | mmc_retune_timer_stop(host->mmc); |
| 2715 | mmc_retune_needed(host->mmc); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 2716 | |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2717 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 2718 | host->ier = 0; |
| 2719 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
| 2720 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2721 | free_irq(host->irq, host); |
| 2722 | } else { |
| 2723 | sdhci_enable_irq_wakeups(host); |
| 2724 | enable_irq_wake(host->irq); |
| 2725 | } |
Ulf Hansson | 4ee14ec | 2013-09-25 14:15:24 +0200 | [diff] [blame] | 2726 | return 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2727 | } |
| 2728 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2729 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2730 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2731 | int sdhci_resume_host(struct sdhci_host *host) |
| 2732 | { |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 2733 | struct mmc_host *mmc = host->mmc; |
Ulf Hansson | 4ee14ec | 2013-09-25 14:15:24 +0200 | [diff] [blame] | 2734 | int ret = 0; |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2735 | |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2736 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2737 | if (host->ops->enable_dma) |
| 2738 | host->ops->enable_dma(host); |
| 2739 | } |
| 2740 | |
Adrian Hunter | 6308d29 | 2012-02-07 14:48:54 +0200 | [diff] [blame] | 2741 | if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && |
| 2742 | (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { |
| 2743 | /* Card keeps power but host controller does not */ |
| 2744 | sdhci_init(host, 0); |
| 2745 | host->pwr = 0; |
| 2746 | host->clock = 0; |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 2747 | mmc->ops->set_ios(mmc, &mmc->ios); |
Adrian Hunter | 6308d29 | 2012-02-07 14:48:54 +0200 | [diff] [blame] | 2748 | } else { |
| 2749 | sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); |
| 2750 | mmiowb(); |
| 2751 | } |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2752 | |
Haibo Chen | 14a7b4164 | 2015-09-15 18:32:58 +0800 | [diff] [blame] | 2753 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
| 2754 | ret = request_threaded_irq(host->irq, sdhci_irq, |
| 2755 | sdhci_thread_irq, IRQF_SHARED, |
| 2756 | mmc_hostname(host->mmc), host); |
| 2757 | if (ret) |
| 2758 | return ret; |
| 2759 | } else { |
| 2760 | sdhci_disable_irq_wakeups(host); |
| 2761 | disable_irq_wake(host->irq); |
| 2762 | } |
| 2763 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 2764 | sdhci_enable_card_detection(host); |
| 2765 | |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 2766 | return ret; |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2767 | } |
| 2768 | |
| 2769 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2770 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2771 | int sdhci_runtime_suspend_host(struct sdhci_host *host) |
| 2772 | { |
| 2773 | unsigned long flags; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2774 | |
Adrian Hunter | 66c39dfc | 2015-05-07 13:10:21 +0300 | [diff] [blame] | 2775 | mmc_retune_timer_stop(host->mmc); |
| 2776 | mmc_retune_needed(host->mmc); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2777 | |
| 2778 | spin_lock_irqsave(&host->lock, flags); |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 2779 | host->ier &= SDHCI_INT_CARD_INT; |
| 2780 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 2781 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2782 | spin_unlock_irqrestore(&host->lock, flags); |
| 2783 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2784 | synchronize_hardirq(host->irq); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2785 | |
| 2786 | spin_lock_irqsave(&host->lock, flags); |
| 2787 | host->runtime_suspended = true; |
| 2788 | spin_unlock_irqrestore(&host->lock, flags); |
| 2789 | |
Markus Pargmann | 8a125ba | 2014-06-04 15:24:29 +0200 | [diff] [blame] | 2790 | return 0; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2791 | } |
| 2792 | EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); |
| 2793 | |
| 2794 | int sdhci_runtime_resume_host(struct sdhci_host *host) |
| 2795 | { |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 2796 | struct mmc_host *mmc = host->mmc; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2797 | unsigned long flags; |
Markus Pargmann | 8a125ba | 2014-06-04 15:24:29 +0200 | [diff] [blame] | 2798 | int host_flags = host->flags; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2799 | |
| 2800 | if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
| 2801 | if (host->ops->enable_dma) |
| 2802 | host->ops->enable_dma(host); |
| 2803 | } |
| 2804 | |
| 2805 | sdhci_init(host, 0); |
| 2806 | |
| 2807 | /* Force clock and power re-program */ |
| 2808 | host->pwr = 0; |
| 2809 | host->clock = 0; |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 2810 | mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios); |
| 2811 | mmc->ops->set_ios(mmc, &mmc->ios); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2812 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 2813 | if ((host_flags & SDHCI_PV_ENABLED) && |
| 2814 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { |
| 2815 | spin_lock_irqsave(&host->lock, flags); |
| 2816 | sdhci_enable_preset_value(host, true); |
| 2817 | spin_unlock_irqrestore(&host->lock, flags); |
| 2818 | } |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2819 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2820 | spin_lock_irqsave(&host->lock, flags); |
| 2821 | |
| 2822 | host->runtime_suspended = false; |
| 2823 | |
| 2824 | /* Enable SDIO IRQ */ |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 2825 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2826 | sdhci_enable_sdio_irq_nolock(host, true); |
| 2827 | |
| 2828 | /* Enable Card Detection */ |
| 2829 | sdhci_enable_card_detection(host); |
| 2830 | |
| 2831 | spin_unlock_irqrestore(&host->lock, flags); |
| 2832 | |
Markus Pargmann | 8a125ba | 2014-06-04 15:24:29 +0200 | [diff] [blame] | 2833 | return 0; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2834 | } |
| 2835 | EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); |
| 2836 | |
Rafael J. Wysocki | 162d6f9 | 2014-12-05 03:05:33 +0100 | [diff] [blame] | 2837 | #endif /* CONFIG_PM */ |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2838 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2839 | /*****************************************************************************\ |
| 2840 | * * |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2841 | * Device allocation/registration * |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2842 | * * |
| 2843 | \*****************************************************************************/ |
| 2844 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2845 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
| 2846 | size_t priv_size) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2847 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2848 | struct mmc_host *mmc; |
| 2849 | struct sdhci_host *host; |
| 2850 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2851 | WARN_ON(dev == NULL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2852 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2853 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2854 | if (!mmc) |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2855 | return ERR_PTR(-ENOMEM); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2856 | |
| 2857 | host = mmc_priv(mmc); |
| 2858 | host->mmc = mmc; |
Adrian Hunter | bf60e59 | 2016-02-09 16:12:35 +0200 | [diff] [blame] | 2859 | host->mmc_host_ops = sdhci_ops; |
| 2860 | mmc->ops = &host->mmc_host_ops; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2861 | |
Adrian Hunter | 8cb851a | 2016-06-29 16:24:16 +0300 | [diff] [blame] | 2862 | host->flags = SDHCI_SIGNALING_330; |
| 2863 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2864 | return host; |
| 2865 | } |
Pierre Ossman | 8a4da14 | 2006-10-04 02:15:40 -0700 | [diff] [blame] | 2866 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2867 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2868 | |
Alexandre Courbot | 7b91369 | 2016-03-07 11:07:55 +0900 | [diff] [blame] | 2869 | static int sdhci_set_dma_mask(struct sdhci_host *host) |
| 2870 | { |
| 2871 | struct mmc_host *mmc = host->mmc; |
| 2872 | struct device *dev = mmc_dev(mmc); |
| 2873 | int ret = -EINVAL; |
| 2874 | |
| 2875 | if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) |
| 2876 | host->flags &= ~SDHCI_USE_64_BIT_DMA; |
| 2877 | |
| 2878 | /* Try 64-bit mask if hardware is capable of it */ |
| 2879 | if (host->flags & SDHCI_USE_64_BIT_DMA) { |
| 2880 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); |
| 2881 | if (ret) { |
| 2882 | pr_warn("%s: Failed to set 64-bit DMA mask.\n", |
| 2883 | mmc_hostname(mmc)); |
| 2884 | host->flags &= ~SDHCI_USE_64_BIT_DMA; |
| 2885 | } |
| 2886 | } |
| 2887 | |
| 2888 | /* 32-bit mask as default & fallback */ |
| 2889 | if (ret) { |
| 2890 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); |
| 2891 | if (ret) |
| 2892 | pr_warn("%s: Failed to set 32-bit DMA mask.\n", |
| 2893 | mmc_hostname(mmc)); |
| 2894 | } |
| 2895 | |
| 2896 | return ret; |
| 2897 | } |
| 2898 | |
Adrian Hunter | 6132a3b | 2016-06-29 16:24:18 +0300 | [diff] [blame] | 2899 | void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) |
| 2900 | { |
| 2901 | u16 v; |
| 2902 | |
| 2903 | if (host->read_caps) |
| 2904 | return; |
| 2905 | |
| 2906 | host->read_caps = true; |
| 2907 | |
| 2908 | if (debug_quirks) |
| 2909 | host->quirks = debug_quirks; |
| 2910 | |
| 2911 | if (debug_quirks2) |
| 2912 | host->quirks2 = debug_quirks2; |
| 2913 | |
| 2914 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
| 2915 | |
| 2916 | v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION); |
| 2917 | host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; |
| 2918 | |
| 2919 | if (host->quirks & SDHCI_QUIRK_MISSING_CAPS) |
| 2920 | return; |
| 2921 | |
| 2922 | host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES); |
| 2923 | |
| 2924 | if (host->version < SDHCI_SPEC_300) |
| 2925 | return; |
| 2926 | |
| 2927 | host->caps1 = caps1 ? *caps1 : sdhci_readl(host, SDHCI_CAPABILITIES_1); |
| 2928 | } |
| 2929 | EXPORT_SYMBOL_GPL(__sdhci_read_caps); |
| 2930 | |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 2931 | int sdhci_setup_host(struct sdhci_host *host) |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2932 | { |
| 2933 | struct mmc_host *mmc; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2934 | u32 max_current_caps; |
| 2935 | unsigned int ocr_avail; |
Adrian Hunter | f5fa92e | 2014-09-24 10:27:32 +0300 | [diff] [blame] | 2936 | unsigned int override_timeout_clk; |
Dong Aisheng | 5924175 | 2015-07-22 20:53:07 +0800 | [diff] [blame] | 2937 | u32 max_clk; |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2938 | int ret; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2939 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2940 | WARN_ON(host == NULL); |
| 2941 | if (host == NULL) |
| 2942 | return -EINVAL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2943 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2944 | mmc = host->mmc; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2945 | |
Adrian Hunter | 6132a3b | 2016-06-29 16:24:18 +0300 | [diff] [blame] | 2946 | sdhci_read_caps(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2947 | |
Adrian Hunter | f5fa92e | 2014-09-24 10:27:32 +0300 | [diff] [blame] | 2948 | override_timeout_clk = host->timeout_clk; |
| 2949 | |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 2950 | if (host->version > SDHCI_SPEC_300) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2951 | pr_err("%s: Unknown controller version (%d). You may experience problems.\n", |
| 2952 | mmc_hostname(mmc), host->version); |
Pierre Ossman | 4a96550 | 2006-06-30 02:22:29 -0700 | [diff] [blame] | 2953 | } |
| 2954 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2955 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2956 | host->flags |= SDHCI_USE_SDMA; |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 2957 | else if (!(host->caps & SDHCI_CAN_DO_SDMA)) |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2958 | DBG("Controller doesn't have SDMA capability\n"); |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 2959 | else |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2960 | host->flags |= SDHCI_USE_SDMA; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2961 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2962 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2963 | (host->flags & SDHCI_USE_SDMA)) { |
Rolf Eike Beer | cee687c | 2007-11-02 15:22:30 +0100 | [diff] [blame] | 2964 | DBG("Disabling DMA as it is marked broken\n"); |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2965 | host->flags &= ~SDHCI_USE_SDMA; |
Feng Tang | 7c168e3 | 2007-09-30 12:44:18 +0200 | [diff] [blame] | 2966 | } |
| 2967 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2968 | if ((host->version >= SDHCI_SPEC_200) && |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 2969 | (host->caps & SDHCI_CAN_DO_ADMA2)) |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2970 | host->flags |= SDHCI_USE_ADMA; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2971 | |
| 2972 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && |
| 2973 | (host->flags & SDHCI_USE_ADMA)) { |
| 2974 | DBG("Disabling ADMA as it is marked broken\n"); |
| 2975 | host->flags &= ~SDHCI_USE_ADMA; |
| 2976 | } |
| 2977 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 2978 | /* |
| 2979 | * It is assumed that a 64-bit capable device has set a 64-bit DMA mask |
| 2980 | * and *must* do 64-bit DMA. A driver has the opportunity to change |
| 2981 | * that during the first call to ->enable_dma(). Similarly |
| 2982 | * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to |
| 2983 | * implement. |
| 2984 | */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 2985 | if (host->caps & SDHCI_CAN_64BIT) |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 2986 | host->flags |= SDHCI_USE_64_BIT_DMA; |
| 2987 | |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2988 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
Alexandre Courbot | 7b91369 | 2016-03-07 11:07:55 +0900 | [diff] [blame] | 2989 | ret = sdhci_set_dma_mask(host); |
| 2990 | |
| 2991 | if (!ret && host->ops->enable_dma) |
| 2992 | ret = host->ops->enable_dma(host); |
| 2993 | |
| 2994 | if (ret) { |
| 2995 | pr_warn("%s: No suitable DMA available - falling back to PIO\n", |
| 2996 | mmc_hostname(mmc)); |
| 2997 | host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); |
| 2998 | |
| 2999 | ret = 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3000 | } |
| 3001 | } |
| 3002 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3003 | /* SDMA does not support 64-bit DMA */ |
| 3004 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
| 3005 | host->flags &= ~SDHCI_USE_SDMA; |
| 3006 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3007 | if (host->flags & SDHCI_USE_ADMA) { |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 3008 | dma_addr_t dma; |
| 3009 | void *buf; |
| 3010 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3011 | /* |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 3012 | * The DMA descriptor table size is calculated as the maximum |
| 3013 | * number of segments times 2, to allow for an alignment |
| 3014 | * descriptor for each segment, plus 1 for a nop end descriptor, |
| 3015 | * all multipled by the descriptor size. |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3016 | */ |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3017 | if (host->flags & SDHCI_USE_64_BIT_DMA) { |
| 3018 | host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * |
| 3019 | SDHCI_ADMA2_64_DESC_SZ; |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3020 | host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3021 | } else { |
| 3022 | host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * |
| 3023 | SDHCI_ADMA2_32_DESC_SZ; |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3024 | host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3025 | } |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 3026 | |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 3027 | host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 3028 | buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + |
| 3029 | host->adma_table_sz, &dma, GFP_KERNEL); |
| 3030 | if (!buf) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 3031 | pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3032 | mmc_hostname(mmc)); |
| 3033 | host->flags &= ~SDHCI_USE_ADMA; |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 3034 | } else if ((dma + host->align_buffer_sz) & |
| 3035 | (SDHCI_ADMA2_DESC_ALIGN - 1)) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 3036 | pr_warn("%s: unable to allocate aligned ADMA descriptor\n", |
| 3037 | mmc_hostname(mmc)); |
Russell King | d1e49f7 | 2014-04-25 12:58:34 +0100 | [diff] [blame] | 3038 | host->flags &= ~SDHCI_USE_ADMA; |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 3039 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + |
| 3040 | host->adma_table_sz, buf, dma); |
| 3041 | } else { |
| 3042 | host->align_buffer = buf; |
| 3043 | host->align_addr = dma; |
Russell King | edd63fc | 2016-01-26 13:39:50 +0000 | [diff] [blame] | 3044 | |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 3045 | host->adma_table = buf + host->align_buffer_sz; |
| 3046 | host->adma_addr = dma + host->align_buffer_sz; |
| 3047 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3048 | } |
| 3049 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 3050 | /* |
| 3051 | * If we use DMA, then it's up to the caller to set the DMA |
| 3052 | * mask, but PIO does not need the hw shim so we set a new |
| 3053 | * mask here in that case. |
| 3054 | */ |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3055 | if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 3056 | host->dma_mask = DMA_BIT_MASK(64); |
Markus Mayer | 4e743f1 | 2014-07-03 13:27:42 -0700 | [diff] [blame] | 3057 | mmc_dev(mmc)->dma_mask = &host->dma_mask; |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 3058 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3059 | |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 3060 | if (host->version >= SDHCI_SPEC_300) |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3061 | host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK) |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 3062 | >> SDHCI_CLOCK_BASE_SHIFT; |
| 3063 | else |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3064 | host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK) |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 3065 | >> SDHCI_CLOCK_BASE_SHIFT; |
| 3066 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3067 | host->max_clk *= 1000000; |
Anton Vorontsov | f27f47e | 2010-05-26 14:41:53 -0700 | [diff] [blame] | 3068 | if (host->max_clk == 0 || host->quirks & |
| 3069 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 3070 | if (!host->ops->get_max_clock) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 3071 | pr_err("%s: Hardware doesn't specify base clock frequency.\n", |
| 3072 | mmc_hostname(mmc)); |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3073 | ret = -ENODEV; |
| 3074 | goto undma; |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 3075 | } |
| 3076 | host->max_clk = host->ops->get_max_clock(host); |
| 3077 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3078 | |
| 3079 | /* |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 3080 | * In case of Host Controller v3.00, find out whether clock |
| 3081 | * multiplier is supported. |
| 3082 | */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3083 | host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >> |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 3084 | SDHCI_CLOCK_MUL_SHIFT; |
| 3085 | |
| 3086 | /* |
| 3087 | * In case the value in Clock Multiplier is 0, then programmable |
| 3088 | * clock mode is not supported, otherwise the actual clock |
| 3089 | * multiplier is one more than the value of Clock Multiplier |
| 3090 | * in the Capabilities Register. |
| 3091 | */ |
| 3092 | if (host->clk_mul) |
| 3093 | host->clk_mul += 1; |
| 3094 | |
| 3095 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3096 | * Set host parameters. |
| 3097 | */ |
Dong Aisheng | 5924175 | 2015-07-22 20:53:07 +0800 | [diff] [blame] | 3098 | max_clk = host->max_clk; |
| 3099 | |
Marek Szyprowski | ce5f036 | 2010-08-10 18:01:56 -0700 | [diff] [blame] | 3100 | if (host->ops->get_min_clock) |
Anton Vorontsov | a9e58f2 | 2009-07-29 15:04:16 -0700 | [diff] [blame] | 3101 | mmc->f_min = host->ops->get_min_clock(host); |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 3102 | else if (host->version >= SDHCI_SPEC_300) { |
| 3103 | if (host->clk_mul) { |
| 3104 | mmc->f_min = (host->max_clk * host->clk_mul) / 1024; |
Dong Aisheng | 5924175 | 2015-07-22 20:53:07 +0800 | [diff] [blame] | 3105 | max_clk = host->max_clk * host->clk_mul; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 3106 | } else |
| 3107 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; |
| 3108 | } else |
Zhangfei Gao | 0397526 | 2010-09-20 15:15:18 -0400 | [diff] [blame] | 3109 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 3110 | |
Adrian Hunter | d310ae4 | 2016-04-12 14:25:07 +0300 | [diff] [blame] | 3111 | if (!mmc->f_max || mmc->f_max > max_clk) |
Dong Aisheng | 5924175 | 2015-07-22 20:53:07 +0800 | [diff] [blame] | 3112 | mmc->f_max = max_clk; |
| 3113 | |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 3114 | if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3115 | host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >> |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 3116 | SDHCI_TIMEOUT_CLK_SHIFT; |
| 3117 | if (host->timeout_clk == 0) { |
| 3118 | if (host->ops->get_timeout_clock) { |
| 3119 | host->timeout_clk = |
| 3120 | host->ops->get_timeout_clock(host); |
| 3121 | } else { |
| 3122 | pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", |
| 3123 | mmc_hostname(mmc)); |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3124 | ret = -ENODEV; |
| 3125 | goto undma; |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 3126 | } |
Andy Shevchenko | 272308c | 2011-08-03 18:36:00 +0300 | [diff] [blame] | 3127 | } |
Andy Shevchenko | 272308c | 2011-08-03 18:36:00 +0300 | [diff] [blame] | 3128 | |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3129 | if (host->caps & SDHCI_TIMEOUT_CLK_UNIT) |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 3130 | host->timeout_clk *= 1000; |
Andy Shevchenko | 272308c | 2011-08-03 18:36:00 +0300 | [diff] [blame] | 3131 | |
Adrian Hunter | 9951362 | 2016-03-07 13:33:55 +0200 | [diff] [blame] | 3132 | if (override_timeout_clk) |
| 3133 | host->timeout_clk = override_timeout_clk; |
| 3134 | |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 3135 | mmc->max_busy_timeout = host->ops->get_max_timeout_count ? |
Aisheng Dong | a6ff5ae | 2014-08-27 15:26:27 +0800 | [diff] [blame] | 3136 | host->ops->get_max_timeout_count(host) : 1 << 27; |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 3137 | mmc->max_busy_timeout /= host->timeout_clk; |
| 3138 | } |
Adrian Hunter | 58d1246 | 2011-06-28 17:16:03 +0300 | [diff] [blame] | 3139 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 3140 | mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3141 | mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 3142 | |
| 3143 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) |
| 3144 | host->flags |= SDHCI_AUTO_CMD12; |
Anton Vorontsov | 5fe23c7 | 2009-06-18 00:14:08 +0400 | [diff] [blame] | 3145 | |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 3146 | /* Auto-CMD23 stuff only works in ADMA or PIO. */ |
Andrei Warkentin | 4f3d3e9 | 2011-05-25 10:42:50 -0400 | [diff] [blame] | 3147 | if ((host->version >= SDHCI_SPEC_300) && |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 3148 | ((host->flags & SDHCI_USE_ADMA) || |
Scott Branden | 3bfa6f0 | 2015-02-09 16:06:28 -0800 | [diff] [blame] | 3149 | !(host->flags & SDHCI_USE_SDMA)) && |
| 3150 | !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 3151 | host->flags |= SDHCI_AUTO_CMD23; |
| 3152 | DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); |
| 3153 | } else { |
| 3154 | DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); |
| 3155 | } |
| 3156 | |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 3157 | /* |
| 3158 | * A controller may support 8-bit width, but the board itself |
| 3159 | * might not have the pins brought out. Boards that support |
| 3160 | * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in |
| 3161 | * their platform code before calling sdhci_add_host(), and we |
| 3162 | * won't assume 8-bit width for hosts without that CAP. |
| 3163 | */ |
Anton Vorontsov | 5fe23c7 | 2009-06-18 00:14:08 +0400 | [diff] [blame] | 3164 | if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 3165 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3166 | |
Jerry Huang | 63ef5d8 | 2012-10-25 13:47:19 +0800 | [diff] [blame] | 3167 | if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) |
| 3168 | mmc->caps &= ~MMC_CAP_CMD23; |
| 3169 | |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3170 | if (host->caps & SDHCI_CAN_DO_HISPD) |
Zhangfei Gao | a29e7e1 | 2010-08-16 21:15:32 -0400 | [diff] [blame] | 3171 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
Pierre Ossman | cd9277c | 2007-02-18 12:07:47 +0100 | [diff] [blame] | 3172 | |
Jaehoon Chung | 176d1ed | 2010-09-27 09:42:20 +0100 | [diff] [blame] | 3173 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && |
Jaehoon Chung | 860951c | 2016-06-21 10:13:26 +0900 | [diff] [blame] | 3174 | mmc_card_is_removable(mmc) && |
Arnd Bergmann | 287980e | 2016-05-27 23:23:25 +0200 | [diff] [blame] | 3175 | mmc_gpio_get_cd(host->mmc) < 0) |
Anton Vorontsov | 68d1fb7 | 2009-03-17 00:13:52 +0300 | [diff] [blame] | 3176 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
| 3177 | |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3178 | /* If there are external regulators, get them */ |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3179 | ret = mmc_regulator_get_supply(mmc); |
| 3180 | if (ret == -EPROBE_DEFER) |
| 3181 | goto undma; |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3182 | |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 3183 | /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3184 | if (!IS_ERR(mmc->supply.vqmmc)) { |
| 3185 | ret = regulator_enable(mmc->supply.vqmmc); |
| 3186 | if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, |
| 3187 | 1950000)) |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3188 | host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | |
| 3189 | SDHCI_SUPPORT_SDR50 | |
| 3190 | SDHCI_SUPPORT_DDR50); |
Chris Ball | a3361ab | 2013-03-11 17:51:53 -0400 | [diff] [blame] | 3191 | if (ret) { |
| 3192 | pr_warn("%s: Failed to enable vqmmc regulator: %d\n", |
| 3193 | mmc_hostname(mmc), ret); |
Adrian Hunter | 4bb7431 | 2014-11-06 15:19:04 +0200 | [diff] [blame] | 3194 | mmc->supply.vqmmc = ERR_PTR(-EINVAL); |
Chris Ball | a3361ab | 2013-03-11 17:51:53 -0400 | [diff] [blame] | 3195 | } |
Kevin Liu | 8363c37 | 2012-11-17 17:55:51 -0500 | [diff] [blame] | 3196 | } |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 3197 | |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3198 | if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) { |
| 3199 | host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | |
| 3200 | SDHCI_SUPPORT_DDR50); |
| 3201 | } |
Daniel Drake | 6a66180 | 2012-11-25 13:01:19 -0500 | [diff] [blame] | 3202 | |
Al Cooper | 4188bba | 2012-03-16 15:54:17 -0400 | [diff] [blame] | 3203 | /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3204 | if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | |
| 3205 | SDHCI_SUPPORT_DDR50)) |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3206 | mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; |
| 3207 | |
| 3208 | /* SDR104 supports also implies SDR50 support */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3209 | if (host->caps1 & SDHCI_SUPPORT_SDR104) { |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3210 | mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; |
Giuseppe CAVALLARO | 156e14b | 2013-06-12 08:16:38 +0200 | [diff] [blame] | 3211 | /* SD3.0: SDR104 is supported so (for eMMC) the caps2 |
| 3212 | * field can be promoted to support HS200. |
| 3213 | */ |
Adrian Hunter | 549c0b1 | 2014-11-06 15:19:05 +0200 | [diff] [blame] | 3214 | if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) |
David Cohen | 13868bf | 2013-10-29 10:58:26 -0700 | [diff] [blame] | 3215 | mmc->caps2 |= MMC_CAP2_HS200; |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3216 | } else if (host->caps1 & SDHCI_SUPPORT_SDR50) { |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3217 | mmc->caps |= MMC_CAP_UHS_SDR50; |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3218 | } |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3219 | |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 3220 | if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3221 | (host->caps1 & SDHCI_SUPPORT_HS400)) |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 3222 | mmc->caps2 |= MMC_CAP2_HS400; |
| 3223 | |
Adrian Hunter | 549c0b1 | 2014-11-06 15:19:05 +0200 | [diff] [blame] | 3224 | if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && |
| 3225 | (IS_ERR(mmc->supply.vqmmc) || |
| 3226 | !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, |
| 3227 | 1300000))) |
| 3228 | mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; |
| 3229 | |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3230 | if ((host->caps1 & SDHCI_SUPPORT_DDR50) && |
| 3231 | !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3232 | mmc->caps |= MMC_CAP_UHS_DDR50; |
| 3233 | |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 3234 | /* Does the host need tuning for SDR50? */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3235 | if (host->caps1 & SDHCI_USE_SDR50_TUNING) |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 3236 | host->flags |= SDHCI_SDR50_NEEDS_TUNING; |
| 3237 | |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 3238 | /* Driver Type(s) (A, C, D) supported by the host */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3239 | if (host->caps1 & SDHCI_DRIVER_TYPE_A) |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 3240 | mmc->caps |= MMC_CAP_DRIVER_TYPE_A; |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3241 | if (host->caps1 & SDHCI_DRIVER_TYPE_C) |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 3242 | mmc->caps |= MMC_CAP_DRIVER_TYPE_C; |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3243 | if (host->caps1 & SDHCI_DRIVER_TYPE_D) |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 3244 | mmc->caps |= MMC_CAP_DRIVER_TYPE_D; |
| 3245 | |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 3246 | /* Initial value for re-tuning timer count */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3247 | host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >> |
| 3248 | SDHCI_RETUNING_TIMER_COUNT_SHIFT; |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 3249 | |
| 3250 | /* |
| 3251 | * In case Re-tuning Timer is not disabled, the actual value of |
| 3252 | * re-tuning timer will be 2 ^ (n - 1). |
| 3253 | */ |
| 3254 | if (host->tuning_count) |
| 3255 | host->tuning_count = 1 << (host->tuning_count - 1); |
| 3256 | |
| 3257 | /* Re-tuning mode supported by the Host Controller */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3258 | host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >> |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 3259 | SDHCI_RETUNING_MODE_SHIFT; |
| 3260 | |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 3261 | ocr_avail = 0; |
Philip Rakity | bad37e1 | 2012-05-27 18:36:44 -0700 | [diff] [blame] | 3262 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3263 | /* |
| 3264 | * According to SD Host Controller spec v3.00, if the Host System |
| 3265 | * can afford more than 150mA, Host Driver should set XPC to 1. Also |
| 3266 | * the value is meaningful only if Voltage Support in the Capabilities |
| 3267 | * register is set. The actual current value is 4 times the register |
| 3268 | * value. |
| 3269 | */ |
| 3270 | max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3271 | if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { |
Chuanxiao.Dong | ae90603 | 2014-08-01 14:00:13 +0800 | [diff] [blame] | 3272 | int curr = regulator_get_current_limit(mmc->supply.vmmc); |
Philip Rakity | bad37e1 | 2012-05-27 18:36:44 -0700 | [diff] [blame] | 3273 | if (curr > 0) { |
| 3274 | |
| 3275 | /* convert to SDHCI_MAX_CURRENT format */ |
| 3276 | curr = curr/1000; /* convert to mA */ |
| 3277 | curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; |
| 3278 | |
| 3279 | curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); |
| 3280 | max_current_caps = |
| 3281 | (curr << SDHCI_MAX_CURRENT_330_SHIFT) | |
| 3282 | (curr << SDHCI_MAX_CURRENT_300_SHIFT) | |
| 3283 | (curr << SDHCI_MAX_CURRENT_180_SHIFT); |
| 3284 | } |
| 3285 | } |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3286 | |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3287 | if (host->caps & SDHCI_CAN_VDD_330) { |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 3288 | ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3289 | |
Aaron Lu | 55c4665 | 2012-07-04 13:31:48 +0800 | [diff] [blame] | 3290 | mmc->max_current_330 = ((max_current_caps & |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3291 | SDHCI_MAX_CURRENT_330_MASK) >> |
| 3292 | SDHCI_MAX_CURRENT_330_SHIFT) * |
| 3293 | SDHCI_MAX_CURRENT_MULTIPLIER; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3294 | } |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3295 | if (host->caps & SDHCI_CAN_VDD_300) { |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 3296 | ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3297 | |
Aaron Lu | 55c4665 | 2012-07-04 13:31:48 +0800 | [diff] [blame] | 3298 | mmc->max_current_300 = ((max_current_caps & |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3299 | SDHCI_MAX_CURRENT_300_MASK) >> |
| 3300 | SDHCI_MAX_CURRENT_300_SHIFT) * |
| 3301 | SDHCI_MAX_CURRENT_MULTIPLIER; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3302 | } |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3303 | if (host->caps & SDHCI_CAN_VDD_180) { |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 3304 | ocr_avail |= MMC_VDD_165_195; |
| 3305 | |
Aaron Lu | 55c4665 | 2012-07-04 13:31:48 +0800 | [diff] [blame] | 3306 | mmc->max_current_180 = ((max_current_caps & |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3307 | SDHCI_MAX_CURRENT_180_MASK) >> |
| 3308 | SDHCI_MAX_CURRENT_180_SHIFT) * |
| 3309 | SDHCI_MAX_CURRENT_MULTIPLIER; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3310 | } |
| 3311 | |
Ulf Hansson | 5fd26c7 | 2015-06-05 11:40:08 +0200 | [diff] [blame] | 3312 | /* If OCR set by host, use it instead. */ |
| 3313 | if (host->ocr_mask) |
| 3314 | ocr_avail = host->ocr_mask; |
| 3315 | |
| 3316 | /* If OCR set by external regulators, give it highest prio. */ |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3317 | if (mmc->ocr_avail) |
Tim Kryger | 5222161 | 2014-06-25 00:25:34 -0700 | [diff] [blame] | 3318 | ocr_avail = mmc->ocr_avail; |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3319 | |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 3320 | mmc->ocr_avail = ocr_avail; |
| 3321 | mmc->ocr_avail_sdio = ocr_avail; |
| 3322 | if (host->ocr_avail_sdio) |
| 3323 | mmc->ocr_avail_sdio &= host->ocr_avail_sdio; |
| 3324 | mmc->ocr_avail_sd = ocr_avail; |
| 3325 | if (host->ocr_avail_sd) |
| 3326 | mmc->ocr_avail_sd &= host->ocr_avail_sd; |
| 3327 | else /* normal SD controllers don't support 1.8V */ |
| 3328 | mmc->ocr_avail_sd &= ~MMC_VDD_165_195; |
| 3329 | mmc->ocr_avail_mmc = ocr_avail; |
| 3330 | if (host->ocr_avail_mmc) |
| 3331 | mmc->ocr_avail_mmc &= host->ocr_avail_mmc; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 3332 | |
| 3333 | if (mmc->ocr_avail == 0) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 3334 | pr_err("%s: Hardware doesn't report any support voltages.\n", |
| 3335 | mmc_hostname(mmc)); |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3336 | ret = -ENODEV; |
| 3337 | goto unreg; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 3338 | } |
| 3339 | |
Adrian Hunter | 8cb851a | 2016-06-29 16:24:16 +0300 | [diff] [blame] | 3340 | if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | |
| 3341 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | |
| 3342 | MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) || |
| 3343 | (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V))) |
| 3344 | host->flags |= SDHCI_SIGNALING_180; |
| 3345 | |
| 3346 | if (mmc->caps2 & MMC_CAP2_HSX00_1_2V) |
| 3347 | host->flags |= SDHCI_SIGNALING_120; |
| 3348 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3349 | spin_lock_init(&host->lock); |
| 3350 | |
| 3351 | /* |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3352 | * Maximum number of segments. Depends on if the hardware |
| 3353 | * can do scatter/gather or not. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3354 | */ |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3355 | if (host->flags & SDHCI_USE_ADMA) |
Adrian Hunter | 4fb213f | 2014-11-04 12:42:43 +0200 | [diff] [blame] | 3356 | mmc->max_segs = SDHCI_MAX_SEGS; |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3357 | else if (host->flags & SDHCI_USE_SDMA) |
Martin K. Petersen | a36274e | 2010-09-10 01:33:59 -0400 | [diff] [blame] | 3358 | mmc->max_segs = 1; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3359 | else /* PIO */ |
Adrian Hunter | 4fb213f | 2014-11-04 12:42:43 +0200 | [diff] [blame] | 3360 | mmc->max_segs = SDHCI_MAX_SEGS; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3361 | |
| 3362 | /* |
Adrian Hunter | ac00531 | 2014-12-05 19:25:28 +0200 | [diff] [blame] | 3363 | * Maximum number of sectors in one transfer. Limited by SDMA boundary |
| 3364 | * size (512KiB). Note some tuning modes impose a 4MiB limit, but this |
| 3365 | * is less anyway. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3366 | */ |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 3367 | mmc->max_req_size = 524288; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3368 | |
| 3369 | /* |
| 3370 | * Maximum segment size. Could be one segment with the maximum number |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3371 | * of bytes. When doing hardware scatter/gather, each entry cannot |
| 3372 | * be larger than 64 KiB though. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3373 | */ |
Olof Johansson | 30652aa | 2011-01-01 18:37:32 -0600 | [diff] [blame] | 3374 | if (host->flags & SDHCI_USE_ADMA) { |
| 3375 | if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) |
| 3376 | mmc->max_seg_size = 65535; |
| 3377 | else |
| 3378 | mmc->max_seg_size = 65536; |
| 3379 | } else { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3380 | mmc->max_seg_size = mmc->max_req_size; |
Olof Johansson | 30652aa | 2011-01-01 18:37:32 -0600 | [diff] [blame] | 3381 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3382 | |
| 3383 | /* |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 3384 | * Maximum block size. This varies from controller to controller and |
| 3385 | * is specified in the capabilities register. |
| 3386 | */ |
Anton Vorontsov | 0633f65 | 2009-03-17 00:14:03 +0300 | [diff] [blame] | 3387 | if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { |
| 3388 | mmc->max_blk_size = 2; |
| 3389 | } else { |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3390 | mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >> |
Anton Vorontsov | 0633f65 | 2009-03-17 00:14:03 +0300 | [diff] [blame] | 3391 | SDHCI_MAX_BLOCK_SHIFT; |
| 3392 | if (mmc->max_blk_size >= 3) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 3393 | pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", |
| 3394 | mmc_hostname(mmc)); |
Anton Vorontsov | 0633f65 | 2009-03-17 00:14:03 +0300 | [diff] [blame] | 3395 | mmc->max_blk_size = 0; |
| 3396 | } |
| 3397 | } |
| 3398 | |
| 3399 | mmc->max_blk_size = 512 << mmc->max_blk_size; |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 3400 | |
| 3401 | /* |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 3402 | * Maximum block count. |
| 3403 | */ |
Ben Dooks | 1388eef | 2009-06-14 12:40:53 +0100 | [diff] [blame] | 3404 | mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 3405 | |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 3406 | return 0; |
| 3407 | |
| 3408 | unreg: |
| 3409 | if (!IS_ERR(mmc->supply.vqmmc)) |
| 3410 | regulator_disable(mmc->supply.vqmmc); |
| 3411 | undma: |
| 3412 | if (host->align_buffer) |
| 3413 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + |
| 3414 | host->adma_table_sz, host->align_buffer, |
| 3415 | host->align_addr); |
| 3416 | host->adma_table = NULL; |
| 3417 | host->align_buffer = NULL; |
| 3418 | |
| 3419 | return ret; |
| 3420 | } |
| 3421 | EXPORT_SYMBOL_GPL(sdhci_setup_host); |
| 3422 | |
| 3423 | int __sdhci_add_host(struct sdhci_host *host) |
| 3424 | { |
| 3425 | struct mmc_host *mmc = host->mmc; |
| 3426 | int ret; |
| 3427 | |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 3428 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3429 | * Init tasklets. |
| 3430 | */ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3431 | tasklet_init(&host->finish_tasklet, |
| 3432 | sdhci_tasklet_finish, (unsigned long)host); |
| 3433 | |
Al Viro | e4cad1b | 2006-10-10 22:47:07 +0100 | [diff] [blame] | 3434 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3435 | |
Adrian Hunter | 250fb7b4 | 2014-12-05 19:41:10 +0200 | [diff] [blame] | 3436 | init_waitqueue_head(&host->buf_ready_int); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 3437 | |
Shawn Guo | 2af502c | 2013-07-05 14:38:55 +0800 | [diff] [blame] | 3438 | sdhci_init(host, 0); |
| 3439 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3440 | ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, |
| 3441 | IRQF_SHARED, mmc_hostname(mmc), host); |
Mark Brown | 0fc81ee | 2012-07-02 14:26:15 +0100 | [diff] [blame] | 3442 | if (ret) { |
| 3443 | pr_err("%s: Failed to request IRQ %d: %d\n", |
| 3444 | mmc_hostname(mmc), host->irq, ret); |
Pierre Ossman | 8ef1a14 | 2006-06-30 02:22:21 -0700 | [diff] [blame] | 3445 | goto untasklet; |
Mark Brown | 0fc81ee | 2012-07-02 14:26:15 +0100 | [diff] [blame] | 3446 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3447 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3448 | #ifdef CONFIG_MMC_DEBUG |
| 3449 | sdhci_dumpregs(host); |
| 3450 | #endif |
| 3451 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 3452 | ret = sdhci_led_register(host); |
Mark Brown | 0fc81ee | 2012-07-02 14:26:15 +0100 | [diff] [blame] | 3453 | if (ret) { |
| 3454 | pr_err("%s: Failed to register LED device: %d\n", |
| 3455 | mmc_hostname(mmc), ret); |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3456 | goto unirq; |
Mark Brown | 0fc81ee | 2012-07-02 14:26:15 +0100 | [diff] [blame] | 3457 | } |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 3458 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 3459 | mmiowb(); |
| 3460 | |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3461 | ret = mmc_add_host(mmc); |
| 3462 | if (ret) |
| 3463 | goto unled; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3464 | |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 3465 | pr_info("%s: SDHCI controller on %s [%s] using %s\n", |
Kay Sievers | d1b2686 | 2008-11-08 21:37:46 +0100 | [diff] [blame] | 3466 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3467 | (host->flags & SDHCI_USE_ADMA) ? |
| 3468 | (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3469 | (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3470 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 3471 | sdhci_enable_card_detection(host); |
| 3472 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3473 | return 0; |
| 3474 | |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3475 | unled: |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 3476 | sdhci_led_unregister(host); |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3477 | unirq: |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 3478 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 3479 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
| 3480 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 3481 | free_irq(host->irq, host); |
Pierre Ossman | 8ef1a14 | 2006-06-30 02:22:21 -0700 | [diff] [blame] | 3482 | untasklet: |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3483 | tasklet_kill(&host->finish_tasklet); |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 3484 | |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3485 | if (!IS_ERR(mmc->supply.vqmmc)) |
| 3486 | regulator_disable(mmc->supply.vqmmc); |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 3487 | |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3488 | if (host->align_buffer) |
| 3489 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + |
| 3490 | host->adma_table_sz, host->align_buffer, |
| 3491 | host->align_addr); |
| 3492 | host->adma_table = NULL; |
| 3493 | host->align_buffer = NULL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3494 | |
| 3495 | return ret; |
| 3496 | } |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 3497 | EXPORT_SYMBOL_GPL(__sdhci_add_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3498 | |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 3499 | int sdhci_add_host(struct sdhci_host *host) |
| 3500 | { |
| 3501 | int ret; |
| 3502 | |
| 3503 | ret = sdhci_setup_host(host); |
| 3504 | if (ret) |
| 3505 | return ret; |
| 3506 | |
| 3507 | return __sdhci_add_host(host); |
| 3508 | } |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3509 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
| 3510 | |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 3511 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3512 | { |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3513 | struct mmc_host *mmc = host->mmc; |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 3514 | unsigned long flags; |
| 3515 | |
| 3516 | if (dead) { |
| 3517 | spin_lock_irqsave(&host->lock, flags); |
| 3518 | |
| 3519 | host->flags |= SDHCI_DEVICE_DEAD; |
| 3520 | |
Adrian Hunter | 5d0d11c | 2016-06-29 16:24:31 +0300 | [diff] [blame] | 3521 | if (sdhci_has_requests(host)) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 3522 | pr_err("%s: Controller removed during " |
Markus Mayer | 4e743f1 | 2014-07-03 13:27:42 -0700 | [diff] [blame] | 3523 | " transfer!\n", mmc_hostname(mmc)); |
Adrian Hunter | 5d0d11c | 2016-06-29 16:24:31 +0300 | [diff] [blame] | 3524 | sdhci_error_out_mrqs(host, -ENOMEDIUM); |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 3525 | } |
| 3526 | |
| 3527 | spin_unlock_irqrestore(&host->lock, flags); |
| 3528 | } |
| 3529 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 3530 | sdhci_disable_card_detection(host); |
| 3531 | |
Markus Mayer | 4e743f1 | 2014-07-03 13:27:42 -0700 | [diff] [blame] | 3532 | mmc_remove_host(mmc); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3533 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 3534 | sdhci_led_unregister(host); |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 3535 | |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 3536 | if (!dead) |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 3537 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3538 | |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 3539 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
| 3540 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3541 | free_irq(host->irq, host); |
| 3542 | |
| 3543 | del_timer_sync(&host->timer); |
| 3544 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3545 | tasklet_kill(&host->finish_tasklet); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3546 | |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3547 | if (!IS_ERR(mmc->supply.vqmmc)) |
| 3548 | regulator_disable(mmc->supply.vqmmc); |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 3549 | |
Russell King | edd63fc | 2016-01-26 13:39:50 +0000 | [diff] [blame] | 3550 | if (host->align_buffer) |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 3551 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + |
| 3552 | host->adma_table_sz, host->align_buffer, |
| 3553 | host->align_addr); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3554 | |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 3555 | host->adma_table = NULL; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3556 | host->align_buffer = NULL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3557 | } |
| 3558 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3559 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
| 3560 | |
| 3561 | void sdhci_free_host(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3562 | { |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3563 | mmc_free_host(host->mmc); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3564 | } |
| 3565 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3566 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3567 | |
| 3568 | /*****************************************************************************\ |
| 3569 | * * |
| 3570 | * Driver init/exit * |
| 3571 | * * |
| 3572 | \*****************************************************************************/ |
| 3573 | |
| 3574 | static int __init sdhci_drv_init(void) |
| 3575 | { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 3576 | pr_info(DRIVER_NAME |
Pierre Ossman | 52fbf9c | 2007-02-09 08:23:41 +0100 | [diff] [blame] | 3577 | ": Secure Digital Host Controller Interface driver\n"); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 3578 | pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3579 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3580 | return 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3581 | } |
| 3582 | |
| 3583 | static void __exit sdhci_drv_exit(void) |
| 3584 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3585 | } |
| 3586 | |
| 3587 | module_init(sdhci_drv_init); |
| 3588 | module_exit(sdhci_drv_exit); |
| 3589 | |
Pierre Ossman | df673b2 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 3590 | module_param(debug_quirks, uint, 0444); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3591 | module_param(debug_quirks2, uint, 0444); |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 3592 | |
Pierre Ossman | 32710e8 | 2009-04-08 20:14:54 +0200 | [diff] [blame] | 3593 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3594 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3595 | MODULE_LICENSE("GPL"); |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 3596 | |
Pierre Ossman | df673b2 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 3597 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3598 | MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); |