Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Emilio López |
| 3 | * |
| 4 | * Emilio López <emilio@elopez.com.ar> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/clk-provider.h> |
| 18 | #include <linux/clkdev.h> |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 19 | #include <linux/of.h> |
| 20 | #include <linux/of_address.h> |
Hans de Goede | cfb0086 | 2014-02-07 16:21:49 +0100 | [diff] [blame] | 21 | #include <linux/reset-controller.h> |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 22 | |
| 23 | #include "clk-factors.h" |
| 24 | |
| 25 | static DEFINE_SPINLOCK(clk_lock); |
| 26 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 27 | /* Maximum number of parents our clocks have */ |
| 28 | #define SUNXI_MAX_PARENTS 5 |
| 29 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 30 | /** |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 31 | * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1 |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 32 | * PLL1 rate is calculated as follows |
| 33 | * rate = (parent_rate * n * (k + 1) >> p) / (m + 1); |
| 34 | * parent_rate is always 24Mhz |
| 35 | */ |
| 36 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 37 | static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 38 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 39 | { |
| 40 | u8 div; |
| 41 | |
| 42 | /* Normalize value to a 6M multiple */ |
| 43 | div = *freq / 6000000; |
| 44 | *freq = 6000000 * div; |
| 45 | |
| 46 | /* we were called to round the frequency, we can now return */ |
| 47 | if (n == NULL) |
| 48 | return; |
| 49 | |
| 50 | /* m is always zero for pll1 */ |
| 51 | *m = 0; |
| 52 | |
| 53 | /* k is 1 only on these cases */ |
| 54 | if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000) |
| 55 | *k = 1; |
| 56 | else |
| 57 | *k = 0; |
| 58 | |
| 59 | /* p will be 3 for divs under 10 */ |
| 60 | if (div < 10) |
| 61 | *p = 3; |
| 62 | |
| 63 | /* p will be 2 for divs between 10 - 20 and odd divs under 32 */ |
| 64 | else if (div < 20 || (div < 32 && (div & 1))) |
| 65 | *p = 2; |
| 66 | |
| 67 | /* p will be 1 for even divs under 32, divs under 40 and odd pairs |
| 68 | * of divs between 40-62 */ |
| 69 | else if (div < 40 || (div < 64 && (div & 2))) |
| 70 | *p = 1; |
| 71 | |
| 72 | /* any other entries have p = 0 */ |
| 73 | else |
| 74 | *p = 0; |
| 75 | |
| 76 | /* calculate a suitable n based on k and p */ |
| 77 | div <<= *p; |
| 78 | div /= (*k + 1); |
| 79 | *n = div / 4; |
| 80 | } |
| 81 | |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 82 | /** |
| 83 | * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1 |
| 84 | * PLL1 rate is calculated as follows |
| 85 | * rate = parent_rate * (n + 1) * (k + 1) / (m + 1); |
| 86 | * parent_rate should always be 24MHz |
| 87 | */ |
| 88 | static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate, |
| 89 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 90 | { |
| 91 | /* |
| 92 | * We can operate only on MHz, this will make our life easier |
| 93 | * later. |
| 94 | */ |
| 95 | u32 freq_mhz = *freq / 1000000; |
| 96 | u32 parent_freq_mhz = parent_rate / 1000000; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 97 | |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 98 | /* |
| 99 | * Round down the frequency to the closest multiple of either |
| 100 | * 6 or 16 |
| 101 | */ |
| 102 | u32 round_freq_6 = round_down(freq_mhz, 6); |
| 103 | u32 round_freq_16 = round_down(freq_mhz, 16); |
| 104 | |
| 105 | if (round_freq_6 > round_freq_16) |
| 106 | freq_mhz = round_freq_6; |
| 107 | else |
| 108 | freq_mhz = round_freq_16; |
| 109 | |
| 110 | *freq = freq_mhz * 1000000; |
| 111 | |
| 112 | /* |
| 113 | * If the factors pointer are null, we were just called to |
| 114 | * round down the frequency. |
| 115 | * Exit. |
| 116 | */ |
| 117 | if (n == NULL) |
| 118 | return; |
| 119 | |
| 120 | /* If the frequency is a multiple of 32 MHz, k is always 3 */ |
| 121 | if (!(freq_mhz % 32)) |
| 122 | *k = 3; |
| 123 | /* If the frequency is a multiple of 9 MHz, k is always 2 */ |
| 124 | else if (!(freq_mhz % 9)) |
| 125 | *k = 2; |
| 126 | /* If the frequency is a multiple of 8 MHz, k is always 1 */ |
| 127 | else if (!(freq_mhz % 8)) |
| 128 | *k = 1; |
| 129 | /* Otherwise, we don't use the k factor */ |
| 130 | else |
| 131 | *k = 0; |
| 132 | |
| 133 | /* |
| 134 | * If the frequency is a multiple of 2 but not a multiple of |
| 135 | * 3, m is 3. This is the first time we use 6 here, yet we |
| 136 | * will use it on several other places. |
| 137 | * We use this number because it's the lowest frequency we can |
| 138 | * generate (with n = 0, k = 0, m = 3), so every other frequency |
| 139 | * somehow relates to this frequency. |
| 140 | */ |
| 141 | if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4) |
| 142 | *m = 2; |
| 143 | /* |
| 144 | * If the frequency is a multiple of 6MHz, but the factor is |
| 145 | * odd, m will be 3 |
| 146 | */ |
| 147 | else if ((freq_mhz / 6) & 1) |
| 148 | *m = 3; |
| 149 | /* Otherwise, we end up with m = 1 */ |
| 150 | else |
| 151 | *m = 1; |
| 152 | |
| 153 | /* Calculate n thanks to the above factors we already got */ |
| 154 | *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1; |
| 155 | |
| 156 | /* |
| 157 | * If n end up being outbound, and that we can still decrease |
| 158 | * m, do it. |
| 159 | */ |
| 160 | if ((*n + 1) > 31 && (*m + 1) > 1) { |
| 161 | *n = (*n + 1) / 2 - 1; |
| 162 | *m = (*m + 1) / 2 - 1; |
| 163 | } |
| 164 | } |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 165 | |
| 166 | /** |
Chen-Yu Tsai | 515c1a4 | 2014-06-26 23:55:43 +0800 | [diff] [blame] | 167 | * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1 |
| 168 | * PLL1 rate is calculated as follows |
| 169 | * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1); |
| 170 | * parent_rate is always 24Mhz |
| 171 | */ |
| 172 | |
| 173 | static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate, |
| 174 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 175 | { |
| 176 | u8 div; |
| 177 | |
| 178 | /* Normalize value to a 6M multiple */ |
| 179 | div = *freq / 6000000; |
| 180 | *freq = 6000000 * div; |
| 181 | |
| 182 | /* we were called to round the frequency, we can now return */ |
| 183 | if (n == NULL) |
| 184 | return; |
| 185 | |
| 186 | /* m is always zero for pll1 */ |
| 187 | *m = 0; |
| 188 | |
| 189 | /* k is 1 only on these cases */ |
| 190 | if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000) |
| 191 | *k = 1; |
| 192 | else |
| 193 | *k = 0; |
| 194 | |
| 195 | /* p will be 2 for divs under 20 and odd divs under 32 */ |
| 196 | if (div < 20 || (div < 32 && (div & 1))) |
| 197 | *p = 2; |
| 198 | |
| 199 | /* p will be 1 for even divs under 32, divs under 40 and odd pairs |
| 200 | * of divs between 40-62 */ |
| 201 | else if (div < 40 || (div < 64 && (div & 2))) |
| 202 | *p = 1; |
| 203 | |
| 204 | /* any other entries have p = 0 */ |
| 205 | else |
| 206 | *p = 0; |
| 207 | |
| 208 | /* calculate a suitable n based on k and p */ |
| 209 | div <<= *p; |
| 210 | div /= (*k + 1); |
| 211 | *n = div / 4 - 1; |
| 212 | } |
| 213 | |
| 214 | /** |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 215 | * sun4i_get_pll5_factors() - calculates n, k factors for PLL5 |
| 216 | * PLL5 rate is calculated as follows |
| 217 | * rate = parent_rate * n * (k + 1) |
| 218 | * parent_rate is always 24Mhz |
| 219 | */ |
| 220 | |
| 221 | static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate, |
| 222 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 223 | { |
| 224 | u8 div; |
| 225 | |
| 226 | /* Normalize value to a parent_rate multiple (24M) */ |
| 227 | div = *freq / parent_rate; |
| 228 | *freq = parent_rate * div; |
| 229 | |
| 230 | /* we were called to round the frequency, we can now return */ |
| 231 | if (n == NULL) |
| 232 | return; |
| 233 | |
| 234 | if (div < 31) |
| 235 | *k = 0; |
| 236 | else if (div / 2 < 31) |
| 237 | *k = 1; |
| 238 | else if (div / 3 < 31) |
| 239 | *k = 2; |
| 240 | else |
| 241 | *k = 3; |
| 242 | |
| 243 | *n = DIV_ROUND_UP(div, (*k+1)); |
| 244 | } |
| 245 | |
Maxime Ripard | 92ef67c | 2014-02-05 14:05:03 +0100 | [diff] [blame] | 246 | /** |
| 247 | * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6 |
| 248 | * PLL6 rate is calculated as follows |
| 249 | * rate = parent_rate * n * (k + 1) / 2 |
| 250 | * parent_rate is always 24Mhz |
| 251 | */ |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 252 | |
Maxime Ripard | 92ef67c | 2014-02-05 14:05:03 +0100 | [diff] [blame] | 253 | static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate, |
| 254 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 255 | { |
| 256 | u8 div; |
| 257 | |
| 258 | /* |
| 259 | * We always have 24MHz / 2, so we can just say that our |
| 260 | * parent clock is 12MHz. |
| 261 | */ |
| 262 | parent_rate = parent_rate / 2; |
| 263 | |
| 264 | /* Normalize value to a parent_rate multiple (24M / 2) */ |
| 265 | div = *freq / parent_rate; |
| 266 | *freq = parent_rate * div; |
| 267 | |
| 268 | /* we were called to round the frequency, we can now return */ |
| 269 | if (n == NULL) |
| 270 | return; |
| 271 | |
| 272 | *k = div / 32; |
| 273 | if (*k > 3) |
| 274 | *k = 3; |
| 275 | |
| 276 | *n = DIV_ROUND_UP(div, (*k+1)); |
| 277 | } |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 278 | |
| 279 | /** |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 280 | * sun4i_get_apb1_factors() - calculates m, p factors for APB1 |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 281 | * APB1 rate is calculated as follows |
| 282 | * rate = (parent_rate >> p) / (m + 1); |
| 283 | */ |
| 284 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 285 | static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 286 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 287 | { |
| 288 | u8 calcm, calcp; |
| 289 | |
| 290 | if (parent_rate < *freq) |
| 291 | *freq = parent_rate; |
| 292 | |
Emilio López | 2226013 | 2014-03-19 15:19:32 -0300 | [diff] [blame] | 293 | parent_rate = DIV_ROUND_UP(parent_rate, *freq); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 294 | |
| 295 | /* Invalid rate! */ |
| 296 | if (parent_rate > 32) |
| 297 | return; |
| 298 | |
| 299 | if (parent_rate <= 4) |
| 300 | calcp = 0; |
| 301 | else if (parent_rate <= 8) |
| 302 | calcp = 1; |
| 303 | else if (parent_rate <= 16) |
| 304 | calcp = 2; |
| 305 | else |
| 306 | calcp = 3; |
| 307 | |
| 308 | calcm = (parent_rate >> calcp) - 1; |
| 309 | |
| 310 | *freq = (parent_rate >> calcp) / (calcm + 1); |
| 311 | |
| 312 | /* we were called to round the frequency, we can now return */ |
| 313 | if (n == NULL) |
| 314 | return; |
| 315 | |
| 316 | *m = calcm; |
| 317 | *p = calcp; |
| 318 | } |
| 319 | |
| 320 | |
| 321 | |
| 322 | /** |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 323 | * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks |
Emilio López | 9ce71ca | 2014-03-19 15:19:33 -0300 | [diff] [blame] | 324 | * MOD0 rate is calculated as follows |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 325 | * rate = (parent_rate >> p) / (m + 1); |
| 326 | */ |
| 327 | |
| 328 | static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate, |
| 329 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 330 | { |
| 331 | u8 div, calcm, calcp; |
| 332 | |
| 333 | /* These clocks can only divide, so we will never be able to achieve |
| 334 | * frequencies higher than the parent frequency */ |
| 335 | if (*freq > parent_rate) |
| 336 | *freq = parent_rate; |
| 337 | |
Emilio López | 2226013 | 2014-03-19 15:19:32 -0300 | [diff] [blame] | 338 | div = DIV_ROUND_UP(parent_rate, *freq); |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 339 | |
| 340 | if (div < 16) |
| 341 | calcp = 0; |
| 342 | else if (div / 2 < 16) |
| 343 | calcp = 1; |
| 344 | else if (div / 4 < 16) |
| 345 | calcp = 2; |
| 346 | else |
| 347 | calcp = 3; |
| 348 | |
| 349 | calcm = DIV_ROUND_UP(div, 1 << calcp); |
| 350 | |
| 351 | *freq = (parent_rate >> calcp) / calcm; |
| 352 | |
| 353 | /* we were called to round the frequency, we can now return */ |
| 354 | if (n == NULL) |
| 355 | return; |
| 356 | |
| 357 | *m = calcm - 1; |
| 358 | *p = calcp; |
| 359 | } |
| 360 | |
| 361 | |
| 362 | |
| 363 | /** |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 364 | * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B |
| 365 | * CLK_OUT rate is calculated as follows |
| 366 | * rate = (parent_rate >> p) / (m + 1); |
| 367 | */ |
| 368 | |
| 369 | static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate, |
| 370 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 371 | { |
| 372 | u8 div, calcm, calcp; |
| 373 | |
| 374 | /* These clocks can only divide, so we will never be able to achieve |
| 375 | * frequencies higher than the parent frequency */ |
| 376 | if (*freq > parent_rate) |
| 377 | *freq = parent_rate; |
| 378 | |
Emilio López | 2226013 | 2014-03-19 15:19:32 -0300 | [diff] [blame] | 379 | div = DIV_ROUND_UP(parent_rate, *freq); |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 380 | |
| 381 | if (div < 32) |
| 382 | calcp = 0; |
| 383 | else if (div / 2 < 32) |
| 384 | calcp = 1; |
| 385 | else if (div / 4 < 32) |
| 386 | calcp = 2; |
| 387 | else |
| 388 | calcp = 3; |
| 389 | |
| 390 | calcm = DIV_ROUND_UP(div, 1 << calcp); |
| 391 | |
| 392 | *freq = (parent_rate >> calcp) / calcm; |
| 393 | |
| 394 | /* we were called to round the frequency, we can now return */ |
| 395 | if (n == NULL) |
| 396 | return; |
| 397 | |
| 398 | *m = calcm - 1; |
| 399 | *p = calcp; |
| 400 | } |
| 401 | |
Chen-Yu Tsai | e4c6d6c | 2014-02-10 18:35:47 +0800 | [diff] [blame] | 402 | /** |
Emilio López | 9571397 | 2014-05-02 17:57:16 +0200 | [diff] [blame] | 403 | * clk_sunxi_mmc_phase_control() - configures MMC clock phase control |
| 404 | */ |
| 405 | |
Hans de Goede | a97181a | 2014-05-12 14:04:47 +0200 | [diff] [blame] | 406 | void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output) |
Emilio López | 9571397 | 2014-05-02 17:57:16 +0200 | [diff] [blame] | 407 | { |
| 408 | #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) |
| 409 | #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw) |
| 410 | |
Hans de Goede | a97181a | 2014-05-12 14:04:47 +0200 | [diff] [blame] | 411 | struct clk_hw *hw = __clk_get_hw(clk); |
Emilio López | 9571397 | 2014-05-02 17:57:16 +0200 | [diff] [blame] | 412 | struct clk_composite *composite = to_clk_composite(hw); |
| 413 | struct clk_hw *rate_hw = composite->rate_hw; |
| 414 | struct clk_factors *factors = to_clk_factors(rate_hw); |
| 415 | unsigned long flags = 0; |
| 416 | u32 reg; |
| 417 | |
| 418 | if (factors->lock) |
| 419 | spin_lock_irqsave(factors->lock, flags); |
| 420 | |
| 421 | reg = readl(factors->reg); |
| 422 | |
| 423 | /* set sample clock phase control */ |
| 424 | reg &= ~(0x7 << 20); |
| 425 | reg |= ((sample & 0x7) << 20); |
| 426 | |
| 427 | /* set output clock phase control */ |
| 428 | reg &= ~(0x7 << 8); |
| 429 | reg |= ((output & 0x7) << 8); |
| 430 | |
| 431 | writel(reg, factors->reg); |
| 432 | |
| 433 | if (factors->lock) |
| 434 | spin_unlock_irqrestore(factors->lock, flags); |
| 435 | } |
| 436 | EXPORT_SYMBOL(clk_sunxi_mmc_phase_control); |
| 437 | |
| 438 | |
| 439 | /** |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 440 | * sunxi_factors_clk_setup() - Setup function for factor clocks |
| 441 | */ |
| 442 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 443 | #define SUNXI_FACTORS_MUX_MASK 0x3 |
| 444 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 445 | struct factors_data { |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 446 | int enable; |
| 447 | int mux; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 448 | struct clk_factors_config *table; |
| 449 | void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p); |
Chen-Yu Tsai | 667f542 | 2014-02-03 09:51:39 +0800 | [diff] [blame] | 450 | const char *name; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 451 | }; |
| 452 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 453 | static struct clk_factors_config sun4i_pll1_config = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 454 | .nshift = 8, |
| 455 | .nwidth = 5, |
| 456 | .kshift = 4, |
| 457 | .kwidth = 2, |
| 458 | .mshift = 0, |
| 459 | .mwidth = 2, |
| 460 | .pshift = 16, |
| 461 | .pwidth = 2, |
| 462 | }; |
| 463 | |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 464 | static struct clk_factors_config sun6i_a31_pll1_config = { |
| 465 | .nshift = 8, |
| 466 | .nwidth = 5, |
| 467 | .kshift = 4, |
| 468 | .kwidth = 2, |
| 469 | .mshift = 0, |
| 470 | .mwidth = 2, |
| 471 | }; |
| 472 | |
Chen-Yu Tsai | 515c1a4 | 2014-06-26 23:55:43 +0800 | [diff] [blame] | 473 | static struct clk_factors_config sun8i_a23_pll1_config = { |
| 474 | .nshift = 8, |
| 475 | .nwidth = 5, |
| 476 | .kshift = 4, |
| 477 | .kwidth = 2, |
| 478 | .mshift = 0, |
| 479 | .mwidth = 2, |
| 480 | .pshift = 16, |
| 481 | .pwidth = 2, |
| 482 | .n_start = 1, |
| 483 | }; |
| 484 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 485 | static struct clk_factors_config sun4i_pll5_config = { |
| 486 | .nshift = 8, |
| 487 | .nwidth = 5, |
| 488 | .kshift = 4, |
| 489 | .kwidth = 2, |
| 490 | }; |
| 491 | |
Maxime Ripard | 92ef67c | 2014-02-05 14:05:03 +0100 | [diff] [blame] | 492 | static struct clk_factors_config sun6i_a31_pll6_config = { |
| 493 | .nshift = 8, |
| 494 | .nwidth = 5, |
| 495 | .kshift = 4, |
| 496 | .kwidth = 2, |
| 497 | }; |
| 498 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 499 | static struct clk_factors_config sun4i_apb1_config = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 500 | .mshift = 0, |
| 501 | .mwidth = 5, |
| 502 | .pshift = 16, |
| 503 | .pwidth = 2, |
| 504 | }; |
| 505 | |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 506 | /* user manual says "n" but it's really "p" */ |
| 507 | static struct clk_factors_config sun4i_mod0_config = { |
| 508 | .mshift = 0, |
| 509 | .mwidth = 4, |
| 510 | .pshift = 16, |
| 511 | .pwidth = 2, |
| 512 | }; |
| 513 | |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 514 | /* user manual says "n" but it's really "p" */ |
| 515 | static struct clk_factors_config sun7i_a20_out_config = { |
| 516 | .mshift = 8, |
| 517 | .mwidth = 5, |
| 518 | .pshift = 20, |
| 519 | .pwidth = 2, |
| 520 | }; |
| 521 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 522 | static const struct factors_data sun4i_pll1_data __initconst = { |
Emilio López | d838ff3 | 2013-12-23 00:32:34 -0300 | [diff] [blame] | 523 | .enable = 31, |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 524 | .table = &sun4i_pll1_config, |
| 525 | .getter = sun4i_get_pll1_factors, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 526 | }; |
| 527 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 528 | static const struct factors_data sun6i_a31_pll1_data __initconst = { |
Emilio López | d838ff3 | 2013-12-23 00:32:34 -0300 | [diff] [blame] | 529 | .enable = 31, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 530 | .table = &sun6i_a31_pll1_config, |
| 531 | .getter = sun6i_a31_get_pll1_factors, |
| 532 | }; |
| 533 | |
Chen-Yu Tsai | 515c1a4 | 2014-06-26 23:55:43 +0800 | [diff] [blame] | 534 | static const struct factors_data sun8i_a23_pll1_data __initconst = { |
| 535 | .enable = 31, |
| 536 | .table = &sun8i_a23_pll1_config, |
| 537 | .getter = sun8i_a23_get_pll1_factors, |
| 538 | }; |
| 539 | |
Emilio López | 5a8ddf2 | 2014-03-19 15:19:30 -0300 | [diff] [blame] | 540 | static const struct factors_data sun7i_a20_pll4_data __initconst = { |
| 541 | .enable = 31, |
| 542 | .table = &sun4i_pll5_config, |
| 543 | .getter = sun4i_get_pll5_factors, |
| 544 | }; |
| 545 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 546 | static const struct factors_data sun4i_pll5_data __initconst = { |
| 547 | .enable = 31, |
| 548 | .table = &sun4i_pll5_config, |
| 549 | .getter = sun4i_get_pll5_factors, |
Chen-Yu Tsai | 667f542 | 2014-02-03 09:51:39 +0800 | [diff] [blame] | 550 | .name = "pll5", |
| 551 | }; |
| 552 | |
| 553 | static const struct factors_data sun4i_pll6_data __initconst = { |
| 554 | .enable = 31, |
| 555 | .table = &sun4i_pll5_config, |
| 556 | .getter = sun4i_get_pll5_factors, |
| 557 | .name = "pll6", |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 558 | }; |
| 559 | |
Maxime Ripard | 92ef67c | 2014-02-05 14:05:03 +0100 | [diff] [blame] | 560 | static const struct factors_data sun6i_a31_pll6_data __initconst = { |
| 561 | .enable = 31, |
| 562 | .table = &sun6i_a31_pll6_config, |
| 563 | .getter = sun6i_a31_get_pll6_factors, |
| 564 | }; |
| 565 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 566 | static const struct factors_data sun4i_apb1_data __initconst = { |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 567 | .table = &sun4i_apb1_config, |
| 568 | .getter = sun4i_get_apb1_factors, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 569 | }; |
| 570 | |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 571 | static const struct factors_data sun4i_mod0_data __initconst = { |
| 572 | .enable = 31, |
| 573 | .mux = 24, |
| 574 | .table = &sun4i_mod0_config, |
| 575 | .getter = sun4i_get_mod0_factors, |
| 576 | }; |
| 577 | |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 578 | static const struct factors_data sun7i_a20_out_data __initconst = { |
| 579 | .enable = 31, |
| 580 | .mux = 24, |
| 581 | .table = &sun7i_a20_out_config, |
| 582 | .getter = sun7i_a20_get_out_factors, |
| 583 | }; |
| 584 | |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 585 | static struct clk * __init sunxi_factors_clk_setup(struct device_node *node, |
| 586 | const struct factors_data *data) |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 587 | { |
| 588 | struct clk *clk; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 589 | struct clk_factors *factors; |
| 590 | struct clk_gate *gate = NULL; |
| 591 | struct clk_mux *mux = NULL; |
| 592 | struct clk_hw *gate_hw = NULL; |
| 593 | struct clk_hw *mux_hw = NULL; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 594 | const char *clk_name = node->name; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 595 | const char *parents[SUNXI_MAX_PARENTS]; |
Emilio López | 89a9456 | 2014-07-28 00:49:42 -0300 | [diff] [blame] | 596 | void __iomem *reg; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 597 | int i = 0; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 598 | |
| 599 | reg = of_iomap(node, 0); |
| 600 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 601 | /* if we have a mux, we will have >1 parents */ |
| 602 | while (i < SUNXI_MAX_PARENTS && |
| 603 | (parents[i] = of_clk_get_parent_name(node, i)) != NULL) |
| 604 | i++; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 605 | |
Chen-Yu Tsai | 667f542 | 2014-02-03 09:51:39 +0800 | [diff] [blame] | 606 | /* |
| 607 | * some factor clocks, such as pll5 and pll6, may have multiple |
| 608 | * outputs, and have their name designated in factors_data |
| 609 | */ |
| 610 | if (data->name) |
| 611 | clk_name = data->name; |
| 612 | else |
| 613 | of_property_read_string(node, "clock-output-names", &clk_name); |
Emilio López | 76192dc | 2013-12-23 00:32:40 -0300 | [diff] [blame] | 614 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 615 | factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL); |
| 616 | if (!factors) |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 617 | return NULL; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 618 | |
| 619 | /* Add a gate if this factor clock can be gated */ |
| 620 | if (data->enable) { |
| 621 | gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); |
| 622 | if (!gate) { |
| 623 | kfree(factors); |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 624 | return NULL; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 625 | } |
| 626 | |
| 627 | /* set up gate properties */ |
| 628 | gate->reg = reg; |
| 629 | gate->bit_idx = data->enable; |
| 630 | gate->lock = &clk_lock; |
| 631 | gate_hw = &gate->hw; |
| 632 | } |
| 633 | |
| 634 | /* Add a mux if this factor clock can be muxed */ |
| 635 | if (data->mux) { |
| 636 | mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); |
| 637 | if (!mux) { |
| 638 | kfree(factors); |
| 639 | kfree(gate); |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 640 | return NULL; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 641 | } |
| 642 | |
| 643 | /* set up gate properties */ |
| 644 | mux->reg = reg; |
| 645 | mux->shift = data->mux; |
| 646 | mux->mask = SUNXI_FACTORS_MUX_MASK; |
| 647 | mux->lock = &clk_lock; |
| 648 | mux_hw = &mux->hw; |
| 649 | } |
| 650 | |
| 651 | /* set up factors properties */ |
| 652 | factors->reg = reg; |
| 653 | factors->config = data->table; |
| 654 | factors->get_factors = data->getter; |
| 655 | factors->lock = &clk_lock; |
| 656 | |
| 657 | clk = clk_register_composite(NULL, clk_name, |
| 658 | parents, i, |
| 659 | mux_hw, &clk_mux_ops, |
| 660 | &factors->hw, &clk_factors_ops, |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 661 | gate_hw, &clk_gate_ops, 0); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 662 | |
Axel Lin | ee85e9b | 2013-07-12 16:15:15 +0800 | [diff] [blame] | 663 | if (!IS_ERR(clk)) { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 664 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 665 | clk_register_clkdev(clk, clk_name, NULL); |
| 666 | } |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 667 | |
| 668 | return clk; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 669 | } |
| 670 | |
| 671 | |
| 672 | |
| 673 | /** |
| 674 | * sunxi_mux_clk_setup() - Setup function for muxes |
| 675 | */ |
| 676 | |
| 677 | #define SUNXI_MUX_GATE_WIDTH 2 |
| 678 | |
| 679 | struct mux_data { |
| 680 | u8 shift; |
| 681 | }; |
| 682 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 683 | static const struct mux_data sun4i_cpu_mux_data __initconst = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 684 | .shift = 16, |
| 685 | }; |
| 686 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 687 | static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 688 | .shift = 12, |
| 689 | }; |
| 690 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 691 | static const struct mux_data sun4i_apb1_mux_data __initconst = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 692 | .shift = 24, |
| 693 | }; |
| 694 | |
| 695 | static void __init sunxi_mux_clk_setup(struct device_node *node, |
| 696 | struct mux_data *data) |
| 697 | { |
| 698 | struct clk *clk; |
| 699 | const char *clk_name = node->name; |
Emilio López | edaf3fb | 2013-12-23 00:32:33 -0300 | [diff] [blame] | 700 | const char *parents[SUNXI_MAX_PARENTS]; |
Emilio López | 89a9456 | 2014-07-28 00:49:42 -0300 | [diff] [blame] | 701 | void __iomem *reg; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 702 | int i = 0; |
| 703 | |
| 704 | reg = of_iomap(node, 0); |
| 705 | |
Emilio López | edaf3fb | 2013-12-23 00:32:33 -0300 | [diff] [blame] | 706 | while (i < SUNXI_MAX_PARENTS && |
| 707 | (parents[i] = of_clk_get_parent_name(node, i)) != NULL) |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 708 | i++; |
| 709 | |
Chen-Yu Tsai | f64111e | 2014-02-03 09:51:37 +0800 | [diff] [blame] | 710 | of_property_read_string(node, "clock-output-names", &clk_name); |
| 711 | |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 712 | clk = clk_register_mux(NULL, clk_name, parents, i, |
| 713 | CLK_SET_RATE_NO_REPARENT, reg, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 714 | data->shift, SUNXI_MUX_GATE_WIDTH, |
| 715 | 0, &clk_lock); |
| 716 | |
| 717 | if (clk) { |
| 718 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 719 | clk_register_clkdev(clk, clk_name, NULL); |
| 720 | } |
| 721 | } |
| 722 | |
| 723 | |
| 724 | |
| 725 | /** |
| 726 | * sunxi_divider_clk_setup() - Setup function for simple divider clocks |
| 727 | */ |
| 728 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 729 | struct div_data { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 730 | u8 shift; |
| 731 | u8 pow; |
| 732 | u8 width; |
Chen-Yu Tsai | ea5671b | 2014-06-26 23:55:42 +0800 | [diff] [blame] | 733 | const struct clk_div_table *table; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 734 | }; |
| 735 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 736 | static const struct div_data sun4i_axi_data __initconst = { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 737 | .shift = 0, |
| 738 | .pow = 0, |
| 739 | .width = 2, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 740 | }; |
| 741 | |
Chen-Yu Tsai | 515c1a4 | 2014-06-26 23:55:43 +0800 | [diff] [blame] | 742 | static const struct clk_div_table sun8i_a23_axi_table[] __initconst = { |
| 743 | { .val = 0, .div = 1 }, |
| 744 | { .val = 1, .div = 2 }, |
| 745 | { .val = 2, .div = 3 }, |
| 746 | { .val = 3, .div = 4 }, |
| 747 | { .val = 4, .div = 4 }, |
| 748 | { .val = 5, .div = 4 }, |
| 749 | { .val = 6, .div = 4 }, |
| 750 | { .val = 7, .div = 4 }, |
| 751 | { } /* sentinel */ |
| 752 | }; |
| 753 | |
| 754 | static const struct div_data sun8i_a23_axi_data __initconst = { |
| 755 | .width = 3, |
| 756 | .table = sun8i_a23_axi_table, |
| 757 | }; |
| 758 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 759 | static const struct div_data sun4i_ahb_data __initconst = { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 760 | .shift = 4, |
| 761 | .pow = 1, |
| 762 | .width = 2, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 763 | }; |
| 764 | |
Chen-Yu Tsai | cfe4c93 | 2014-09-06 14:45:10 +0800 | [diff] [blame] | 765 | static const struct clk_div_table sun4i_apb0_table[] __initconst = { |
| 766 | { .val = 0, .div = 2 }, |
| 767 | { .val = 1, .div = 2 }, |
| 768 | { .val = 2, .div = 4 }, |
| 769 | { .val = 3, .div = 8 }, |
| 770 | { } /* sentinel */ |
| 771 | }; |
| 772 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 773 | static const struct div_data sun4i_apb0_data __initconst = { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 774 | .shift = 8, |
| 775 | .pow = 1, |
| 776 | .width = 2, |
Chen-Yu Tsai | cfe4c93 | 2014-09-06 14:45:10 +0800 | [diff] [blame] | 777 | .table = sun4i_apb0_table, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 778 | }; |
| 779 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 780 | static const struct div_data sun6i_a31_apb2_div_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 781 | .shift = 0, |
| 782 | .pow = 0, |
| 783 | .width = 4, |
| 784 | }; |
| 785 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 786 | static void __init sunxi_divider_clk_setup(struct device_node *node, |
| 787 | struct div_data *data) |
| 788 | { |
| 789 | struct clk *clk; |
| 790 | const char *clk_name = node->name; |
| 791 | const char *clk_parent; |
Emilio López | 89a9456 | 2014-07-28 00:49:42 -0300 | [diff] [blame] | 792 | void __iomem *reg; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 793 | |
| 794 | reg = of_iomap(node, 0); |
| 795 | |
| 796 | clk_parent = of_clk_get_parent_name(node, 0); |
| 797 | |
Chen-Yu Tsai | f64111e | 2014-02-03 09:51:37 +0800 | [diff] [blame] | 798 | of_property_read_string(node, "clock-output-names", &clk_name); |
| 799 | |
Chen-Yu Tsai | ea5671b | 2014-06-26 23:55:42 +0800 | [diff] [blame] | 800 | clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0, |
| 801 | reg, data->shift, data->width, |
| 802 | data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0, |
| 803 | data->table, &clk_lock); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 804 | if (clk) { |
| 805 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 806 | clk_register_clkdev(clk, clk_name, NULL); |
| 807 | } |
| 808 | } |
| 809 | |
| 810 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 811 | |
| 812 | /** |
Hans de Goede | cfb0086 | 2014-02-07 16:21:49 +0100 | [diff] [blame] | 813 | * sunxi_gates_reset... - reset bits in leaf gate clk registers handling |
| 814 | */ |
| 815 | |
| 816 | struct gates_reset_data { |
| 817 | void __iomem *reg; |
| 818 | spinlock_t *lock; |
| 819 | struct reset_controller_dev rcdev; |
| 820 | }; |
| 821 | |
| 822 | static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev, |
| 823 | unsigned long id) |
| 824 | { |
| 825 | struct gates_reset_data *data = container_of(rcdev, |
| 826 | struct gates_reset_data, |
| 827 | rcdev); |
| 828 | unsigned long flags; |
| 829 | u32 reg; |
| 830 | |
| 831 | spin_lock_irqsave(data->lock, flags); |
| 832 | |
| 833 | reg = readl(data->reg); |
| 834 | writel(reg & ~BIT(id), data->reg); |
| 835 | |
| 836 | spin_unlock_irqrestore(data->lock, flags); |
| 837 | |
| 838 | return 0; |
| 839 | } |
| 840 | |
| 841 | static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev, |
| 842 | unsigned long id) |
| 843 | { |
| 844 | struct gates_reset_data *data = container_of(rcdev, |
| 845 | struct gates_reset_data, |
| 846 | rcdev); |
| 847 | unsigned long flags; |
| 848 | u32 reg; |
| 849 | |
| 850 | spin_lock_irqsave(data->lock, flags); |
| 851 | |
| 852 | reg = readl(data->reg); |
| 853 | writel(reg | BIT(id), data->reg); |
| 854 | |
| 855 | spin_unlock_irqrestore(data->lock, flags); |
| 856 | |
| 857 | return 0; |
| 858 | } |
| 859 | |
| 860 | static struct reset_control_ops sunxi_gates_reset_ops = { |
| 861 | .assert = sunxi_gates_reset_assert, |
| 862 | .deassert = sunxi_gates_reset_deassert, |
| 863 | }; |
| 864 | |
| 865 | /** |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 866 | * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks |
| 867 | */ |
| 868 | |
| 869 | #define SUNXI_GATES_MAX_SIZE 64 |
| 870 | |
| 871 | struct gates_data { |
| 872 | DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE); |
Hans de Goede | cfb0086 | 2014-02-07 16:21:49 +0100 | [diff] [blame] | 873 | u32 reset_mask; |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 874 | }; |
| 875 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 876 | static const struct gates_data sun4i_axi_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 877 | .mask = {1}, |
| 878 | }; |
| 879 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 880 | static const struct gates_data sun4i_ahb_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 881 | .mask = {0x7F77FFF, 0x14FB3F}, |
| 882 | }; |
| 883 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 884 | static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = { |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 885 | .mask = {0x147667e7, 0x185915}, |
| 886 | }; |
| 887 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 888 | static const struct gates_data sun5i_a13_ahb_gates_data __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 889 | .mask = {0x107067e7, 0x185111}, |
| 890 | }; |
| 891 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 892 | static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 893 | .mask = {0xEDFE7F62, 0x794F931}, |
| 894 | }; |
| 895 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 896 | static const struct gates_data sun7i_a20_ahb_gates_data __initconst = { |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 897 | .mask = { 0x12f77fff, 0x16ff3f }, |
| 898 | }; |
| 899 | |
Chen-Yu Tsai | 515c1a4 | 2014-06-26 23:55:43 +0800 | [diff] [blame] | 900 | static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = { |
| 901 | .mask = {0x25386742, 0x2505111}, |
| 902 | }; |
| 903 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 904 | static const struct gates_data sun4i_apb0_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 905 | .mask = {0x4EF}, |
| 906 | }; |
| 907 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 908 | static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = { |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 909 | .mask = {0x469}, |
| 910 | }; |
| 911 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 912 | static const struct gates_data sun5i_a13_apb0_gates_data __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 913 | .mask = {0x61}, |
| 914 | }; |
| 915 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 916 | static const struct gates_data sun7i_a20_apb0_gates_data __initconst = { |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 917 | .mask = { 0x4ff }, |
| 918 | }; |
| 919 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 920 | static const struct gates_data sun4i_apb1_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 921 | .mask = {0xFF00F7}, |
| 922 | }; |
| 923 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 924 | static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = { |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 925 | .mask = {0xf0007}, |
| 926 | }; |
| 927 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 928 | static const struct gates_data sun5i_a13_apb1_gates_data __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 929 | .mask = {0xa0007}, |
| 930 | }; |
| 931 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 932 | static const struct gates_data sun6i_a31_apb1_gates_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 933 | .mask = {0x3031}, |
| 934 | }; |
| 935 | |
Chen-Yu Tsai | 515c1a4 | 2014-06-26 23:55:43 +0800 | [diff] [blame] | 936 | static const struct gates_data sun8i_a23_apb1_gates_data __initconst = { |
| 937 | .mask = {0x3021}, |
| 938 | }; |
| 939 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 940 | static const struct gates_data sun6i_a31_apb2_gates_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 941 | .mask = {0x3F000F}, |
| 942 | }; |
| 943 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 944 | static const struct gates_data sun7i_a20_apb1_gates_data __initconst = { |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 945 | .mask = { 0xff80ff }, |
| 946 | }; |
| 947 | |
Chen-Yu Tsai | 515c1a4 | 2014-06-26 23:55:43 +0800 | [diff] [blame] | 948 | static const struct gates_data sun8i_a23_apb2_gates_data __initconst = { |
| 949 | .mask = {0x1F0007}, |
| 950 | }; |
| 951 | |
Roman Byshko | 5abdbf2 | 2014-02-07 16:21:50 +0100 | [diff] [blame] | 952 | static const struct gates_data sun4i_a10_usb_gates_data __initconst = { |
| 953 | .mask = {0x1C0}, |
| 954 | .reset_mask = 0x07, |
| 955 | }; |
| 956 | |
| 957 | static const struct gates_data sun5i_a13_usb_gates_data __initconst = { |
| 958 | .mask = {0x140}, |
| 959 | .reset_mask = 0x03, |
| 960 | }; |
| 961 | |
Maxime Ripard | e0e7943 | 2014-05-13 17:44:15 +0200 | [diff] [blame] | 962 | static const struct gates_data sun6i_a31_usb_gates_data __initconst = { |
| 963 | .mask = { BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8) }, |
| 964 | .reset_mask = BIT(2) | BIT(1) | BIT(0), |
| 965 | }; |
| 966 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 967 | static void __init sunxi_gates_clk_setup(struct device_node *node, |
| 968 | struct gates_data *data) |
| 969 | { |
| 970 | struct clk_onecell_data *clk_data; |
Hans de Goede | cfb0086 | 2014-02-07 16:21:49 +0100 | [diff] [blame] | 971 | struct gates_reset_data *reset_data; |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 972 | const char *clk_parent; |
| 973 | const char *clk_name; |
Emilio López | 89a9456 | 2014-07-28 00:49:42 -0300 | [diff] [blame] | 974 | void __iomem *reg; |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 975 | int qty; |
| 976 | int i = 0; |
| 977 | int j = 0; |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 978 | |
| 979 | reg = of_iomap(node, 0); |
| 980 | |
| 981 | clk_parent = of_clk_get_parent_name(node, 0); |
| 982 | |
| 983 | /* Worst-case size approximation and memory allocation */ |
| 984 | qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE); |
| 985 | clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); |
| 986 | if (!clk_data) |
| 987 | return; |
| 988 | clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL); |
| 989 | if (!clk_data->clks) { |
| 990 | kfree(clk_data); |
| 991 | return; |
| 992 | } |
| 993 | |
| 994 | for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) { |
| 995 | of_property_read_string_index(node, "clock-output-names", |
| 996 | j, &clk_name); |
| 997 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 998 | clk_data->clks[i] = clk_register_gate(NULL, clk_name, |
Chen-Yu Tsai | 70eab19 | 2014-06-26 23:55:40 +0800 | [diff] [blame] | 999 | clk_parent, 0, |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 1000 | reg + 4 * (i/32), i % 32, |
| 1001 | 0, &clk_lock); |
| 1002 | WARN_ON(IS_ERR(clk_data->clks[i])); |
Chen-Yu Tsai | d14e470 | 2014-06-26 23:55:39 +0800 | [diff] [blame] | 1003 | clk_register_clkdev(clk_data->clks[i], clk_name, NULL); |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 1004 | |
| 1005 | j++; |
| 1006 | } |
| 1007 | |
| 1008 | /* Adjust to the real max */ |
| 1009 | clk_data->clk_num = i; |
| 1010 | |
| 1011 | of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
Hans de Goede | cfb0086 | 2014-02-07 16:21:49 +0100 | [diff] [blame] | 1012 | |
| 1013 | /* Register a reset controler for gates with reset bits */ |
| 1014 | if (data->reset_mask == 0) |
| 1015 | return; |
| 1016 | |
| 1017 | reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL); |
| 1018 | if (!reset_data) |
| 1019 | return; |
| 1020 | |
| 1021 | reset_data->reg = reg; |
| 1022 | reset_data->lock = &clk_lock; |
| 1023 | reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1; |
| 1024 | reset_data->rcdev.ops = &sunxi_gates_reset_ops; |
| 1025 | reset_data->rcdev.of_node = node; |
| 1026 | reset_controller_register(&reset_data->rcdev); |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 1027 | } |
| 1028 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1029 | |
| 1030 | |
| 1031 | /** |
| 1032 | * sunxi_divs_clk_setup() helper data |
| 1033 | */ |
| 1034 | |
| 1035 | #define SUNXI_DIVS_MAX_QTY 2 |
| 1036 | #define SUNXI_DIVISOR_WIDTH 2 |
| 1037 | |
| 1038 | struct divs_data { |
| 1039 | const struct factors_data *factors; /* data for the factor clock */ |
| 1040 | struct { |
| 1041 | u8 fixed; /* is it a fixed divisor? if not... */ |
| 1042 | struct clk_div_table *table; /* is it a table based divisor? */ |
| 1043 | u8 shift; /* otherwise it's a normal divisor with this shift */ |
| 1044 | u8 pow; /* is it power-of-two based? */ |
| 1045 | u8 gate; /* is it independently gateable? */ |
| 1046 | } div[SUNXI_DIVS_MAX_QTY]; |
| 1047 | }; |
| 1048 | |
| 1049 | static struct clk_div_table pll6_sata_tbl[] = { |
| 1050 | { .val = 0, .div = 6, }, |
| 1051 | { .val = 1, .div = 12, }, |
| 1052 | { .val = 2, .div = 18, }, |
| 1053 | { .val = 3, .div = 24, }, |
| 1054 | { } /* sentinel */ |
| 1055 | }; |
| 1056 | |
| 1057 | static const struct divs_data pll5_divs_data __initconst = { |
| 1058 | .factors = &sun4i_pll5_data, |
| 1059 | .div = { |
| 1060 | { .shift = 0, .pow = 0, }, /* M, DDR */ |
| 1061 | { .shift = 16, .pow = 1, }, /* P, other */ |
| 1062 | } |
| 1063 | }; |
| 1064 | |
| 1065 | static const struct divs_data pll6_divs_data __initconst = { |
Chen-Yu Tsai | 667f542 | 2014-02-03 09:51:39 +0800 | [diff] [blame] | 1066 | .factors = &sun4i_pll6_data, |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1067 | .div = { |
| 1068 | { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */ |
| 1069 | { .fixed = 2 }, /* P, other */ |
| 1070 | } |
| 1071 | }; |
| 1072 | |
| 1073 | /** |
| 1074 | * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks |
| 1075 | * |
| 1076 | * These clocks look something like this |
| 1077 | * ________________________ |
| 1078 | * | ___divisor 1---|----> to consumer |
| 1079 | * parent >--| pll___/___divisor 2---|----> to consumer |
| 1080 | * | \_______________|____> to consumer |
| 1081 | * |________________________| |
| 1082 | */ |
| 1083 | |
| 1084 | static void __init sunxi_divs_clk_setup(struct device_node *node, |
| 1085 | struct divs_data *data) |
| 1086 | { |
| 1087 | struct clk_onecell_data *clk_data; |
Chen-Yu Tsai | 97e36b3 | 2014-02-03 09:51:40 +0800 | [diff] [blame] | 1088 | const char *parent; |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1089 | const char *clk_name; |
| 1090 | struct clk **clks, *pclk; |
| 1091 | struct clk_hw *gate_hw, *rate_hw; |
| 1092 | const struct clk_ops *rate_ops; |
| 1093 | struct clk_gate *gate = NULL; |
| 1094 | struct clk_fixed_factor *fix_factor; |
| 1095 | struct clk_divider *divider; |
Emilio López | 89a9456 | 2014-07-28 00:49:42 -0300 | [diff] [blame] | 1096 | void __iomem *reg; |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1097 | int i = 0; |
| 1098 | int flags, clkflags; |
| 1099 | |
| 1100 | /* Set up factor clock that we will be dividing */ |
| 1101 | pclk = sunxi_factors_clk_setup(node, data->factors); |
Chen-Yu Tsai | 97e36b3 | 2014-02-03 09:51:40 +0800 | [diff] [blame] | 1102 | parent = __clk_get_name(pclk); |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1103 | |
| 1104 | reg = of_iomap(node, 0); |
| 1105 | |
| 1106 | clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); |
| 1107 | if (!clk_data) |
| 1108 | return; |
| 1109 | |
Emilio López | d193368 | 2014-01-24 22:32:41 -0300 | [diff] [blame] | 1110 | clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL); |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1111 | if (!clks) |
| 1112 | goto free_clkdata; |
| 1113 | |
| 1114 | clk_data->clks = clks; |
| 1115 | |
| 1116 | /* It's not a good idea to have automatic reparenting changing |
| 1117 | * our RAM clock! */ |
| 1118 | clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; |
| 1119 | |
| 1120 | for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) { |
| 1121 | if (of_property_read_string_index(node, "clock-output-names", |
| 1122 | i, &clk_name) != 0) |
| 1123 | break; |
| 1124 | |
| 1125 | gate_hw = NULL; |
| 1126 | rate_hw = NULL; |
| 1127 | rate_ops = NULL; |
| 1128 | |
| 1129 | /* If this leaf clock can be gated, create a gate */ |
| 1130 | if (data->div[i].gate) { |
| 1131 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); |
| 1132 | if (!gate) |
| 1133 | goto free_clks; |
| 1134 | |
| 1135 | gate->reg = reg; |
| 1136 | gate->bit_idx = data->div[i].gate; |
| 1137 | gate->lock = &clk_lock; |
| 1138 | |
| 1139 | gate_hw = &gate->hw; |
| 1140 | } |
| 1141 | |
| 1142 | /* Leaves can be fixed or configurable divisors */ |
| 1143 | if (data->div[i].fixed) { |
| 1144 | fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL); |
| 1145 | if (!fix_factor) |
| 1146 | goto free_gate; |
| 1147 | |
| 1148 | fix_factor->mult = 1; |
| 1149 | fix_factor->div = data->div[i].fixed; |
| 1150 | |
| 1151 | rate_hw = &fix_factor->hw; |
| 1152 | rate_ops = &clk_fixed_factor_ops; |
| 1153 | } else { |
| 1154 | divider = kzalloc(sizeof(*divider), GFP_KERNEL); |
| 1155 | if (!divider) |
| 1156 | goto free_gate; |
| 1157 | |
| 1158 | flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0; |
| 1159 | |
| 1160 | divider->reg = reg; |
| 1161 | divider->shift = data->div[i].shift; |
| 1162 | divider->width = SUNXI_DIVISOR_WIDTH; |
| 1163 | divider->flags = flags; |
| 1164 | divider->lock = &clk_lock; |
| 1165 | divider->table = data->div[i].table; |
| 1166 | |
| 1167 | rate_hw = ÷r->hw; |
| 1168 | rate_ops = &clk_divider_ops; |
| 1169 | } |
| 1170 | |
| 1171 | /* Wrap the (potential) gate and the divisor on a composite |
| 1172 | * clock to unify them */ |
| 1173 | clks[i] = clk_register_composite(NULL, clk_name, &parent, 1, |
| 1174 | NULL, NULL, |
| 1175 | rate_hw, rate_ops, |
| 1176 | gate_hw, &clk_gate_ops, |
| 1177 | clkflags); |
| 1178 | |
| 1179 | WARN_ON(IS_ERR(clk_data->clks[i])); |
| 1180 | clk_register_clkdev(clks[i], clk_name, NULL); |
| 1181 | } |
| 1182 | |
| 1183 | /* The last clock available on the getter is the parent */ |
| 1184 | clks[i++] = pclk; |
| 1185 | |
| 1186 | /* Adjust to the real max */ |
| 1187 | clk_data->clk_num = i; |
| 1188 | |
| 1189 | of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| 1190 | |
| 1191 | return; |
| 1192 | |
| 1193 | free_gate: |
| 1194 | kfree(gate); |
| 1195 | free_clks: |
| 1196 | kfree(clks); |
| 1197 | free_clkdata: |
| 1198 | kfree(clk_data); |
| 1199 | } |
| 1200 | |
| 1201 | |
| 1202 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1203 | /* Matches for factors clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 1204 | static const struct of_device_id clk_factors_match[] __initconst = { |
Maxime Ripard | fd1b22f | 2014-02-06 09:55:57 +0100 | [diff] [blame] | 1205 | {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1206 | {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,}, |
Chen-Yu Tsai | 515c1a4 | 2014-06-26 23:55:43 +0800 | [diff] [blame] | 1207 | {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,}, |
Emilio López | 5a8ddf2 | 2014-03-19 15:19:30 -0300 | [diff] [blame] | 1208 | {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,}, |
Maxime Ripard | 92ef67c | 2014-02-05 14:05:03 +0100 | [diff] [blame] | 1209 | {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,}, |
Maxime Ripard | fd1b22f | 2014-02-06 09:55:57 +0100 | [diff] [blame] | 1210 | {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,}, |
| 1211 | {.compatible = "allwinner,sun4i-a10-mod0-clk", .data = &sun4i_mod0_data,}, |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 1212 | {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1213 | {} |
| 1214 | }; |
| 1215 | |
| 1216 | /* Matches for divider clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 1217 | static const struct of_device_id clk_div_match[] __initconst = { |
Maxime Ripard | fd1b22f | 2014-02-06 09:55:57 +0100 | [diff] [blame] | 1218 | {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,}, |
Chen-Yu Tsai | 515c1a4 | 2014-06-26 23:55:43 +0800 | [diff] [blame] | 1219 | {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,}, |
Maxime Ripard | fd1b22f | 2014-02-06 09:55:57 +0100 | [diff] [blame] | 1220 | {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,}, |
| 1221 | {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1222 | {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1223 | {} |
| 1224 | }; |
| 1225 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1226 | /* Matches for divided outputs */ |
| 1227 | static const struct of_device_id clk_divs_match[] __initconst = { |
Maxime Ripard | fd1b22f | 2014-02-06 09:55:57 +0100 | [diff] [blame] | 1228 | {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,}, |
| 1229 | {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,}, |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1230 | {} |
| 1231 | }; |
| 1232 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1233 | /* Matches for mux clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 1234 | static const struct of_device_id clk_mux_match[] __initconst = { |
Maxime Ripard | fd1b22f | 2014-02-06 09:55:57 +0100 | [diff] [blame] | 1235 | {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,}, |
| 1236 | {.compatible = "allwinner,sun4i-a10-apb1-mux-clk", .data = &sun4i_apb1_mux_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1237 | {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1238 | {} |
| 1239 | }; |
| 1240 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 1241 | /* Matches for gate clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 1242 | static const struct of_device_id clk_gates_match[] __initconst = { |
Maxime Ripard | fd1b22f | 2014-02-06 09:55:57 +0100 | [diff] [blame] | 1243 | {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,}, |
| 1244 | {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,}, |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 1245 | {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1246 | {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1247 | {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,}, |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 1248 | {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,}, |
Chen-Yu Tsai | 515c1a4 | 2014-06-26 23:55:43 +0800 | [diff] [blame] | 1249 | {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,}, |
Maxime Ripard | fd1b22f | 2014-02-06 09:55:57 +0100 | [diff] [blame] | 1250 | {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,}, |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 1251 | {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1252 | {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,}, |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 1253 | {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,}, |
Maxime Ripard | fd1b22f | 2014-02-06 09:55:57 +0100 | [diff] [blame] | 1254 | {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,}, |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 1255 | {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1256 | {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1257 | {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,}, |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 1258 | {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,}, |
Chen-Yu Tsai | 515c1a4 | 2014-06-26 23:55:43 +0800 | [diff] [blame] | 1259 | {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1260 | {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,}, |
Chen-Yu Tsai | 515c1a4 | 2014-06-26 23:55:43 +0800 | [diff] [blame] | 1261 | {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,}, |
Roman Byshko | 5abdbf2 | 2014-02-07 16:21:50 +0100 | [diff] [blame] | 1262 | {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,}, |
| 1263 | {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,}, |
Maxime Ripard | e0e7943 | 2014-05-13 17:44:15 +0200 | [diff] [blame] | 1264 | {.compatible = "allwinner,sun6i-a31-usb-clk", .data = &sun6i_a31_usb_gates_data,}, |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 1265 | {} |
| 1266 | }; |
| 1267 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1268 | static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match, |
| 1269 | void *function) |
| 1270 | { |
| 1271 | struct device_node *np; |
| 1272 | const struct div_data *data; |
| 1273 | const struct of_device_id *match; |
| 1274 | void (*setup_function)(struct device_node *, const void *) = function; |
| 1275 | |
Rob Herring | cb7d5f4 | 2014-05-12 11:24:31 -0500 | [diff] [blame] | 1276 | for_each_matching_node_and_match(np, clk_match, &match) { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1277 | data = match->data; |
| 1278 | setup_function(np, data); |
| 1279 | } |
| 1280 | } |
| 1281 | |
Maxime Ripard | 134a669 | 2014-05-09 22:33:39 -0500 | [diff] [blame] | 1282 | static void __init sunxi_init_clocks(const char *clocks[], int nclocks) |
Emilio López | 8e6a4c4 | 2013-09-20 22:03:12 -0300 | [diff] [blame] | 1283 | { |
Maxime Ripard | 134a669 | 2014-05-09 22:33:39 -0500 | [diff] [blame] | 1284 | unsigned int i; |
Emilio López | 8e6a4c4 | 2013-09-20 22:03:12 -0300 | [diff] [blame] | 1285 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1286 | /* Register factor clocks */ |
| 1287 | of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup); |
| 1288 | |
| 1289 | /* Register divider clocks */ |
| 1290 | of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup); |
| 1291 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1292 | /* Register divided output clocks */ |
| 1293 | of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup); |
| 1294 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1295 | /* Register mux clocks */ |
| 1296 | of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup); |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 1297 | |
| 1298 | /* Register gate clocks */ |
| 1299 | of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup); |
Emilio López | 8e6a4c4 | 2013-09-20 22:03:12 -0300 | [diff] [blame] | 1300 | |
Maxime Ripard | 134a669 | 2014-05-09 22:33:39 -0500 | [diff] [blame] | 1301 | /* Protect the clocks that needs to stay on */ |
| 1302 | for (i = 0; i < nclocks; i++) { |
| 1303 | struct clk *clk = clk_get(NULL, clocks[i]); |
| 1304 | |
| 1305 | if (!IS_ERR(clk)) |
| 1306 | clk_prepare_enable(clk); |
| 1307 | } |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1308 | } |
Maxime Ripard | 134a669 | 2014-05-09 22:33:39 -0500 | [diff] [blame] | 1309 | |
| 1310 | static const char *sun4i_a10_critical_clocks[] __initdata = { |
| 1311 | "pll5_ddr", |
Chen-Yu Tsai | 70eab19 | 2014-06-26 23:55:40 +0800 | [diff] [blame] | 1312 | "ahb_sdram", |
Maxime Ripard | 134a669 | 2014-05-09 22:33:39 -0500 | [diff] [blame] | 1313 | }; |
| 1314 | |
| 1315 | static void __init sun4i_a10_init_clocks(struct device_node *node) |
| 1316 | { |
| 1317 | sunxi_init_clocks(sun4i_a10_critical_clocks, |
| 1318 | ARRAY_SIZE(sun4i_a10_critical_clocks)); |
| 1319 | } |
| 1320 | CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks); |
| 1321 | |
| 1322 | static const char *sun5i_critical_clocks[] __initdata = { |
| 1323 | "mbus", |
| 1324 | "pll5_ddr", |
Chen-Yu Tsai | 70eab19 | 2014-06-26 23:55:40 +0800 | [diff] [blame] | 1325 | "ahb_sdram", |
Maxime Ripard | 134a669 | 2014-05-09 22:33:39 -0500 | [diff] [blame] | 1326 | }; |
| 1327 | |
| 1328 | static void __init sun5i_init_clocks(struct device_node *node) |
| 1329 | { |
| 1330 | sunxi_init_clocks(sun5i_critical_clocks, |
| 1331 | ARRAY_SIZE(sun5i_critical_clocks)); |
| 1332 | } |
| 1333 | CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks); |
| 1334 | CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks); |
| 1335 | CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks); |
| 1336 | |
| 1337 | static const char *sun6i_critical_clocks[] __initdata = { |
Maxime Ripard | 2df73f4 | 2014-05-09 22:33:40 -0500 | [diff] [blame] | 1338 | "cpu", |
Maxime Ripard | efb3184 | 2014-05-09 22:33:41 -0500 | [diff] [blame] | 1339 | "ahb1_sdram", |
Maxime Ripard | 134a669 | 2014-05-09 22:33:39 -0500 | [diff] [blame] | 1340 | }; |
| 1341 | |
| 1342 | static void __init sun6i_init_clocks(struct device_node *node) |
| 1343 | { |
| 1344 | sunxi_init_clocks(sun6i_critical_clocks, |
| 1345 | ARRAY_SIZE(sun6i_critical_clocks)); |
| 1346 | } |
| 1347 | CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks); |
Chen-Yu Tsai | 515c1a4 | 2014-06-26 23:55:43 +0800 | [diff] [blame] | 1348 | CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks); |