blob: 9409ae36951708fbfeaf4638d52d3744360f7807 [file] [log] [blame]
Bryan Wu1394f032007-05-06 14:50:22 -07001#
2# For a description of the syntax of this configuration file,
3# see Documentation/kbuild/kconfig-language.txt.
4#
5
Mike Frysinger53f8a252007-11-15 15:48:01 +08006mainmenu "Blackfin Kernel Configuration"
Bryan Wu1394f032007-05-06 14:50:22 -07007
Alan Jenkins9e1b9b82009-11-07 21:03:54 +00008config SYMBOL_PREFIX
9 string
10 default "_"
11
Bryan Wu1394f032007-05-06 14:50:22 -070012config MMU
Mike Frysingerbac7d892009-06-07 03:46:06 -040013 def_bool n
Bryan Wu1394f032007-05-06 14:50:22 -070014
15config FPU
Mike Frysingerbac7d892009-06-07 03:46:06 -040016 def_bool n
Bryan Wu1394f032007-05-06 14:50:22 -070017
18config RWSEM_GENERIC_SPINLOCK
Mike Frysingerbac7d892009-06-07 03:46:06 -040019 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070020
21config RWSEM_XCHGADD_ALGORITHM
Mike Frysingerbac7d892009-06-07 03:46:06 -040022 def_bool n
Bryan Wu1394f032007-05-06 14:50:22 -070023
24config BLACKFIN
Mike Frysingerbac7d892009-06-07 03:46:06 -040025 def_bool y
Mike Frysinger1ee76d72009-06-10 04:45:29 -040026 select HAVE_FUNCTION_GRAPH_TRACER
Mike Frysinger1c873be2009-06-09 07:25:09 -040027 select HAVE_FUNCTION_TRACER
Sam Ravnborgec7748b2008-02-09 10:46:40 +010028 select HAVE_IDE
Mike Frysinger538067c2009-06-07 03:47:01 -040029 select HAVE_KERNEL_GZIP
30 select HAVE_KERNEL_BZIP2
31 select HAVE_KERNEL_LZMA
Mathieu Desnoyers42d4b832008-02-02 15:10:34 -050032 select HAVE_OPROFILE
Michael Hennericha4f0b32c2008-11-18 17:48:22 +080033 select ARCH_WANT_OPTIONAL_GPIOLIB
Bryan Wu1394f032007-05-06 14:50:22 -070034
Mike Frysingerddf9dda2009-06-13 07:42:58 -040035config GENERIC_CSUM
36 def_bool y
37
Mike Frysinger70f12562009-06-07 17:18:25 -040038config GENERIC_BUG
39 def_bool y
40 depends on BUG
41
Aubrey Lie3defff2007-05-21 18:09:11 +080042config ZONE_DMA
Mike Frysingerbac7d892009-06-07 03:46:06 -040043 def_bool y
Aubrey Lie3defff2007-05-21 18:09:11 +080044
Bryan Wu1394f032007-05-06 14:50:22 -070045config GENERIC_FIND_NEXT_BIT
Mike Frysingerbac7d892009-06-07 03:46:06 -040046 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070047
48config GENERIC_HWEIGHT
Mike Frysingerbac7d892009-06-07 03:46:06 -040049 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070050
51config GENERIC_HARDIRQS
Mike Frysingerbac7d892009-06-07 03:46:06 -040052 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070053
54config GENERIC_IRQ_PROBE
Mike Frysingerbac7d892009-06-07 03:46:06 -040055 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070056
Michael Hennerich796dada2009-09-30 07:54:40 +000057config GENERIC_HARDIRQS_NO__DO_IRQ
58 def_bool y
59
Michael Hennerichb2d15832007-07-24 15:46:36 +080060config GENERIC_GPIO
Mike Frysingerbac7d892009-06-07 03:46:06 -040061 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070062
63config FORCE_MAX_ZONEORDER
64 int
65 default "14"
66
67config GENERIC_CALIBRATE_DELAY
Mike Frysingerbac7d892009-06-07 03:46:06 -040068 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070069
Mike Frysinger6fa68e72009-06-08 18:45:01 -040070config LOCKDEP_SUPPORT
71 def_bool y
72
Mike Frysingerc7b412f2009-06-08 18:44:45 -040073config STACKTRACE_SUPPORT
74 def_bool y
75
Mike Frysinger8f860012009-06-08 12:49:48 -040076config TRACE_IRQFLAGS_SUPPORT
77 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070078
Bryan Wu1394f032007-05-06 14:50:22 -070079source "init/Kconfig"
Matt Helsleydc52ddc2008-10-18 20:27:21 -070080
Bryan Wu1394f032007-05-06 14:50:22 -070081source "kernel/Kconfig.preempt"
82
Matt Helsleydc52ddc2008-10-18 20:27:21 -070083source "kernel/Kconfig.freezer"
84
Bryan Wu1394f032007-05-06 14:50:22 -070085menu "Blackfin Processor Options"
86
87comment "Processor and Board Settings"
88
89choice
90 prompt "CPU"
91 default BF533
92
Bryan Wu2f6f4bc2008-11-18 17:48:21 +080093config BF512
94 bool "BF512"
95 help
96 BF512 Processor Support.
97
98config BF514
99 bool "BF514"
100 help
101 BF514 Processor Support.
102
103config BF516
104 bool "BF516"
105 help
106 BF516 Processor Support.
107
108config BF518
109 bool "BF518"
110 help
111 BF518 Processor Support.
112
Michael Hennerich59003142007-10-21 16:54:27 +0800113config BF522
114 bool "BF522"
115 help
116 BF522 Processor Support.
117
Mike Frysinger1545a112007-12-24 16:54:48 +0800118config BF523
119 bool "BF523"
120 help
121 BF523 Processor Support.
122
123config BF524
124 bool "BF524"
125 help
126 BF524 Processor Support.
127
Michael Hennerich59003142007-10-21 16:54:27 +0800128config BF525
129 bool "BF525"
130 help
131 BF525 Processor Support.
132
Mike Frysinger1545a112007-12-24 16:54:48 +0800133config BF526
134 bool "BF526"
135 help
136 BF526 Processor Support.
137
Michael Hennerich59003142007-10-21 16:54:27 +0800138config BF527
139 bool "BF527"
140 help
141 BF527 Processor Support.
142
Bryan Wu1394f032007-05-06 14:50:22 -0700143config BF531
144 bool "BF531"
145 help
146 BF531 Processor Support.
147
148config BF532
149 bool "BF532"
150 help
151 BF532 Processor Support.
152
153config BF533
154 bool "BF533"
155 help
156 BF533 Processor Support.
157
158config BF534
159 bool "BF534"
160 help
161 BF534 Processor Support.
162
163config BF536
164 bool "BF536"
165 help
166 BF536 Processor Support.
167
168config BF537
169 bool "BF537"
170 help
171 BF537 Processor Support.
172
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800173config BF538
174 bool "BF538"
175 help
176 BF538 Processor Support.
177
178config BF539
179 bool "BF539"
180 help
181 BF539 Processor Support.
182
Mike Frysinger5df326a2009-11-16 23:49:41 +0000183config BF542_std
Roy Huang24a07a12007-07-12 22:41:45 +0800184 bool "BF542"
185 help
186 BF542 Processor Support.
187
Mike Frysinger2f89c062009-02-04 16:49:45 +0800188config BF542M
189 bool "BF542m"
190 help
191 BF542 Processor Support.
192
Mike Frysinger5df326a2009-11-16 23:49:41 +0000193config BF544_std
Roy Huang24a07a12007-07-12 22:41:45 +0800194 bool "BF544"
195 help
196 BF544 Processor Support.
197
Mike Frysinger2f89c062009-02-04 16:49:45 +0800198config BF544M
199 bool "BF544m"
200 help
201 BF544 Processor Support.
202
Mike Frysinger5df326a2009-11-16 23:49:41 +0000203config BF547_std
Mike Frysinger7c7fd172007-11-15 21:10:21 +0800204 bool "BF547"
205 help
206 BF547 Processor Support.
207
Mike Frysinger2f89c062009-02-04 16:49:45 +0800208config BF547M
209 bool "BF547m"
210 help
211 BF547 Processor Support.
212
Mike Frysinger5df326a2009-11-16 23:49:41 +0000213config BF548_std
Roy Huang24a07a12007-07-12 22:41:45 +0800214 bool "BF548"
215 help
216 BF548 Processor Support.
217
Mike Frysinger2f89c062009-02-04 16:49:45 +0800218config BF548M
219 bool "BF548m"
220 help
221 BF548 Processor Support.
222
Mike Frysinger5df326a2009-11-16 23:49:41 +0000223config BF549_std
Roy Huang24a07a12007-07-12 22:41:45 +0800224 bool "BF549"
225 help
226 BF549 Processor Support.
227
Mike Frysinger2f89c062009-02-04 16:49:45 +0800228config BF549M
229 bool "BF549m"
230 help
231 BF549 Processor Support.
232
Bryan Wu1394f032007-05-06 14:50:22 -0700233config BF561
234 bool "BF561"
235 help
Mike Frysingercd88b4d2008-10-09 12:03:22 +0800236 BF561 Processor Support.
Bryan Wu1394f032007-05-06 14:50:22 -0700237
238endchoice
239
Graf Yang46fa5ee2009-01-07 23:14:39 +0800240config SMP
241 depends on BF561
john stultz10f03f12009-09-15 21:17:19 -0700242 select GENERIC_CLOCKEVENTS
Graf Yang46fa5ee2009-01-07 23:14:39 +0800243 bool "Symmetric multi-processing support"
244 ---help---
245 This enables support for systems with more than one CPU,
246 like the dual core BF561. If you have a system with only one
247 CPU, say N. If you have a system with more than one CPU, say Y.
248
249 If you don't know what to do here, say N.
250
251config NR_CPUS
252 int
253 depends on SMP
254 default 2 if BF561
255
256config IRQ_PER_CPU
257 bool
258 depends on SMP
259 default y
260
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800261config BF_REV_MIN
262 int
Mike Frysinger2f89c062009-02-04 16:49:45 +0800263 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800264 default 2 if (BF537 || BF536 || BF534)
Mike Frysinger2f89c062009-02-04 16:49:45 +0800265 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800266 default 4 if (BF538 || BF539)
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800267
268config BF_REV_MAX
269 int
Mike Frysinger2f89c062009-02-04 16:49:45 +0800270 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
271 default 3 if (BF537 || BF536 || BF534 || BF54xM)
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800272 default 5 if (BF561 || BF538 || BF539)
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800273 default 6 if (BF533 || BF532 || BF531)
274
Bryan Wu1394f032007-05-06 14:50:22 -0700275choice
276 prompt "Silicon Rev"
Mike Frysingerf8b55652009-04-13 21:58:34 +0000277 default BF_REV_0_0 if (BF51x || BF52x)
278 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
Mike Frysinger2f89c062009-02-04 16:49:45 +0800279 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
Roy Huang24a07a12007-07-12 22:41:45 +0800280
281config BF_REV_0_0
282 bool "0.0"
Mike Frysinger2f89c062009-02-04 16:49:45 +0800283 depends on (BF51x || BF52x || (BF54x && !BF54xM))
Michael Hennerich59003142007-10-21 16:54:27 +0800284
285config BF_REV_0_1
Mike Frysingerd07f4382007-11-15 15:49:17 +0800286 bool "0.1"
Mike Frysinger3d15f302009-06-15 16:21:44 +0000287 depends on (BF51x || BF52x || (BF54x && !BF54xM))
Bryan Wu1394f032007-05-06 14:50:22 -0700288
289config BF_REV_0_2
290 bool "0.2"
Mike Frysinger2f89c062009-02-04 16:49:45 +0800291 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
Bryan Wu1394f032007-05-06 14:50:22 -0700292
293config BF_REV_0_3
294 bool "0.3"
Mike Frysinger2f89c062009-02-04 16:49:45 +0800295 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
Bryan Wu1394f032007-05-06 14:50:22 -0700296
297config BF_REV_0_4
298 bool "0.4"
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800299 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
Bryan Wu1394f032007-05-06 14:50:22 -0700300
301config BF_REV_0_5
302 bool "0.5"
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800303 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
Bryan Wu1394f032007-05-06 14:50:22 -0700304
Mike Frysinger49f72532008-10-09 12:06:27 +0800305config BF_REV_0_6
306 bool "0.6"
307 depends on (BF533 || BF532 || BF531)
308
Jie Zhangde3025f2007-06-25 18:04:12 +0800309config BF_REV_ANY
310 bool "any"
311
312config BF_REV_NONE
313 bool "none"
314
Bryan Wu1394f032007-05-06 14:50:22 -0700315endchoice
316
Roy Huang24a07a12007-07-12 22:41:45 +0800317config BF53x
318 bool
319 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
320 default y
321
Bryan Wu1394f032007-05-06 14:50:22 -0700322config MEM_GENERIC_BOARD
323 bool
324 depends on GENERIC_BOARD
325 default y
326
327config MEM_MT48LC64M4A2FB_7E
328 bool
329 depends on (BFIN533_STAMP)
330 default y
331
332config MEM_MT48LC16M16A2TG_75
333 bool
334 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
Harald Krapfenbauer60584342009-09-10 15:12:08 +0000335 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
336 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
337 || BFIN527_BLUETECHNIX_CM)
Bryan Wu1394f032007-05-06 14:50:22 -0700338 default y
339
340config MEM_MT48LC32M8A2_75
341 bool
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800342 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
Bryan Wu1394f032007-05-06 14:50:22 -0700343 default y
344
345config MEM_MT48LC8M32B2B5_7
346 bool
347 depends on (BFIN561_BLUETECHNIX_CM)
348 default y
349
Michael Hennerich59003142007-10-21 16:54:27 +0800350config MEM_MT48LC32M16A2TG_75
351 bool
Michael Hennerich6924dfb2009-12-07 13:41:28 +0000352 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)
Michael Hennerich59003142007-10-21 16:54:27 +0800353 default y
354
Sonic Zhang49345402009-01-07 23:14:38 +0800355config MEM_MT48LC32M8A2_75
356 bool
357 depends on (BFIN518F_EZBRD)
358 default y
359
Graf Yangee48efb2009-06-18 04:32:04 +0000360config MEM_MT48H32M16LFCJ_75
361 bool
362 depends on (BFIN526_EZBRD)
363 default y
364
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800365source "arch/blackfin/mach-bf518/Kconfig"
Michael Hennerich59003142007-10-21 16:54:27 +0800366source "arch/blackfin/mach-bf527/Kconfig"
Bryan Wu1394f032007-05-06 14:50:22 -0700367source "arch/blackfin/mach-bf533/Kconfig"
368source "arch/blackfin/mach-bf561/Kconfig"
369source "arch/blackfin/mach-bf537/Kconfig"
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800370source "arch/blackfin/mach-bf538/Kconfig"
Roy Huang24a07a12007-07-12 22:41:45 +0800371source "arch/blackfin/mach-bf548/Kconfig"
Bryan Wu1394f032007-05-06 14:50:22 -0700372
373menu "Board customizations"
374
375config CMDLINE_BOOL
376 bool "Default bootloader kernel arguments"
377
378config CMDLINE
379 string "Initial kernel command string"
380 depends on CMDLINE_BOOL
381 default "console=ttyBF0,57600"
382 help
383 If you don't have a boot loader capable of passing a command line string
384 to the kernel, you may specify one here. As a minimum, you should specify
385 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
386
Mike Frysinger5f004c22008-04-25 02:11:24 +0800387config BOOT_LOAD
388 hex "Kernel load address for booting"
389 default "0x1000"
390 range 0x1000 0x20000000
391 help
392 This option allows you to set the load address of the kernel.
393 This can be useful if you are on a board which has a small amount
394 of memory or you wish to reserve some memory at the beginning of
395 the address space.
396
397 Note that you need to keep this value above 4k (0x1000) as this
398 memory region is used to capture NULL pointer references as well
399 as some core kernel functions.
400
Michael Hennerich8cc71172008-10-13 14:45:06 +0800401config ROM_BASE
402 hex "Kernel ROM Base"
Mike Frysinger86249912008-11-18 17:48:22 +0800403 depends on ROMKERNEL
Michael Hennerich8cc71172008-10-13 14:45:06 +0800404 default "0x20040000"
405 range 0x20000000 0x20400000 if !(BF54x || BF561)
406 range 0x20000000 0x30000000 if (BF54x || BF561)
407 help
408
Robin Getzf16295e2007-08-03 18:07:17 +0800409comment "Clock/PLL Setup"
Bryan Wu1394f032007-05-06 14:50:22 -0700410
411config CLKIN_HZ
Sonic Zhang2fb6cb42008-04-25 04:39:28 +0800412 int "Frequency of the crystal on the board in Hz"
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800413 default "10000000" if BFIN532_IP0X
Mike Frysingerd0cb9b42009-06-11 21:52:35 +0000414 default "11059200" if BFIN533_STAMP
415 default "24576000" if PNAV10
416 default "25000000" # most people use this
417 default "27000000" if BFIN533_EZKIT
418 default "30000000" if BFIN561_EZKIT
Bryan Wu1394f032007-05-06 14:50:22 -0700419 help
420 The frequency of CLKIN crystal oscillator on the board in Hz.
Sonic Zhang2fb6cb42008-04-25 04:39:28 +0800421 Warning: This value should match the crystal on the board. Otherwise,
422 peripherals won't work properly.
Bryan Wu1394f032007-05-06 14:50:22 -0700423
Robin Getzf16295e2007-08-03 18:07:17 +0800424config BFIN_KERNEL_CLOCK
425 bool "Re-program Clocks while Kernel boots?"
426 default n
427 help
428 This option decides if kernel clocks are re-programed from the
429 bootloader settings. If the clocks are not set, the SDRAM settings
430 are also not changed, and the Bootloader does 100% of the hardware
431 configuration.
432
433config PLL_BYPASS
Mike Frysingere4e9a7a2007-11-15 20:39:34 +0800434 bool "Bypass PLL"
435 depends on BFIN_KERNEL_CLOCK
436 default n
Robin Getzf16295e2007-08-03 18:07:17 +0800437
438config CLKIN_HALF
439 bool "Half Clock In"
440 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
441 default n
442 help
443 If this is set the clock will be divided by 2, before it goes to the PLL.
444
445config VCO_MULT
446 int "VCO Multiplier"
447 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
448 range 1 64
449 default "22" if BFIN533_EZKIT
450 default "45" if BFIN533_STAMP
Michael Hennerich6924dfb2009-12-07 13:41:28 +0000451 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
Robin Getzf16295e2007-08-03 18:07:17 +0800452 default "22" if BFIN533_BLUETECHNIX_CM
Harald Krapfenbauer60584342009-09-10 15:12:08 +0000453 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
Robin Getzf16295e2007-08-03 18:07:17 +0800454 default "20" if BFIN561_EZKIT
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800455 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
Robin Getzf16295e2007-08-03 18:07:17 +0800456 help
457 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
458 PLL Frequency = (Crystal Frequency) * (this setting)
459
460choice
461 prompt "Core Clock Divider"
462 depends on BFIN_KERNEL_CLOCK
463 default CCLK_DIV_1
464 help
465 This sets the frequency of the core. It can be 1, 2, 4 or 8
466 Core Frequency = (PLL frequency) / (this setting)
467
468config CCLK_DIV_1
469 bool "1"
470
471config CCLK_DIV_2
472 bool "2"
473
474config CCLK_DIV_4
475 bool "4"
476
477config CCLK_DIV_8
478 bool "8"
479endchoice
480
481config SCLK_DIV
482 int "System Clock Divider"
483 depends on BFIN_KERNEL_CLOCK
484 range 1 15
Mike Frysinger5f004c22008-04-25 02:11:24 +0800485 default 5
Robin Getzf16295e2007-08-03 18:07:17 +0800486 help
487 This sets the frequency of the system clock (including SDRAM or DDR).
488 This can be between 1 and 15
489 System Clock = (PLL frequency) / (this setting)
490
Mike Frysinger5f004c22008-04-25 02:11:24 +0800491choice
492 prompt "DDR SDRAM Chip Type"
493 depends on BFIN_KERNEL_CLOCK
494 depends on BF54x
495 default MEM_MT46V32M16_5B
496
497config MEM_MT46V32M16_6T
498 bool "MT46V32M16_6T"
499
500config MEM_MT46V32M16_5B
501 bool "MT46V32M16_5B"
502endchoice
503
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800504choice
505 prompt "DDR/SDRAM Timing"
506 depends on BFIN_KERNEL_CLOCK
507 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
508 help
509 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
510 The calculated SDRAM timing parameters may not be 100%
511 accurate - This option is therefore marked experimental.
512
513config BFIN_KERNEL_CLOCK_MEMINIT_CALC
514 bool "Calculate Timings (EXPERIMENTAL)"
515 depends on EXPERIMENTAL
516
517config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
518 bool "Provide accurate Timings based on target SCLK"
519 help
520 Please consult the Blackfin Hardware Reference Manuals as well
521 as the memory device datasheet.
522 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
523endchoice
524
525menu "Memory Init Control"
526 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
527
528config MEM_DDRCTL0
529 depends on BF54x
530 hex "DDRCTL0"
531 default 0x0
532
533config MEM_DDRCTL1
534 depends on BF54x
535 hex "DDRCTL1"
536 default 0x0
537
538config MEM_DDRCTL2
539 depends on BF54x
540 hex "DDRCTL2"
541 default 0x0
542
543config MEM_EBIU_DDRQUE
544 depends on BF54x
545 hex "DDRQUE"
546 default 0x0
547
548config MEM_SDRRC
549 depends on !BF54x
550 hex "SDRRC"
551 default 0x0
552
553config MEM_SDGCTL
554 depends on !BF54x
555 hex "SDGCTL"
556 default 0x0
557endmenu
558
Robin Getzf16295e2007-08-03 18:07:17 +0800559#
560# Max & Min Speeds for various Chips
561#
562config MAX_VCO_HZ
563 int
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800564 default 400000000 if BF512
565 default 400000000 if BF514
566 default 400000000 if BF516
567 default 400000000 if BF518
Mike Frysinger7b062632009-08-11 21:27:09 +0000568 default 400000000 if BF522
569 default 600000000 if BF523
Mike Frysinger1545a112007-12-24 16:54:48 +0800570 default 400000000 if BF524
Robin Getzf16295e2007-08-03 18:07:17 +0800571 default 600000000 if BF525
Mike Frysinger1545a112007-12-24 16:54:48 +0800572 default 400000000 if BF526
Robin Getzf16295e2007-08-03 18:07:17 +0800573 default 600000000 if BF527
574 default 400000000 if BF531
575 default 400000000 if BF532
576 default 750000000 if BF533
577 default 500000000 if BF534
578 default 400000000 if BF536
579 default 600000000 if BF537
Robin Getzf72eecb2007-11-21 16:29:20 +0800580 default 533333333 if BF538
581 default 533333333 if BF539
Robin Getzf16295e2007-08-03 18:07:17 +0800582 default 600000000 if BF542
Robin Getzf72eecb2007-11-21 16:29:20 +0800583 default 533333333 if BF544
Mike Frysinger1545a112007-12-24 16:54:48 +0800584 default 600000000 if BF547
585 default 600000000 if BF548
Robin Getzf72eecb2007-11-21 16:29:20 +0800586 default 533333333 if BF549
Robin Getzf16295e2007-08-03 18:07:17 +0800587 default 600000000 if BF561
588
589config MIN_VCO_HZ
590 int
591 default 50000000
592
593config MAX_SCLK_HZ
594 int
Robin Getzf72eecb2007-11-21 16:29:20 +0800595 default 133333333
Robin Getzf16295e2007-08-03 18:07:17 +0800596
597config MIN_SCLK_HZ
598 int
599 default 27000000
600
601comment "Kernel Timer/Scheduler"
602
603source kernel/Kconfig.hz
604
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800605config GENERIC_TIME
john stultz10f03f12009-09-15 21:17:19 -0700606 def_bool y
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800607
608config GENERIC_CLOCKEVENTS
609 bool "Generic clock events"
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800610 default y
611
Graf Yang1fa9be72009-05-15 11:01:59 +0000612choice
613 prompt "Kernel Tick Source"
614 depends on GENERIC_CLOCKEVENTS
615 default TICKSOURCE_CORETMR
616
617config TICKSOURCE_GPTMR0
618 bool "Gptimer0 (SCLK domain)"
619 select BFIN_GPTIMERS
Graf Yang1fa9be72009-05-15 11:01:59 +0000620
621config TICKSOURCE_CORETMR
622 bool "Core timer (CCLK domain)"
623
624endchoice
625
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800626config CYCLES_CLOCKSOURCE
Graf Yang1fa9be72009-05-15 11:01:59 +0000627 bool "Use 'CYCLES' as a clocksource"
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800628 depends on GENERIC_CLOCKEVENTS
629 depends on !BFIN_SCRATCH_REG_CYCLES
Graf Yang1fa9be72009-05-15 11:01:59 +0000630 depends on !SMP
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800631 help
632 If you say Y here, you will enable support for using the 'cycles'
633 registers as a clock source. Doing so means you will be unable to
634 safely write to the 'cycles' register during runtime. You will
635 still be able to read it (such as for performance monitoring), but
636 writing the registers will most likely crash the kernel.
637
Graf Yang1fa9be72009-05-15 11:01:59 +0000638config GPTMR0_CLOCKSOURCE
Graf Yange78feaa2009-09-14 04:41:00 +0000639 bool "Use GPTimer0 as a clocksource"
Mike Frysinger3aca47c2009-06-18 19:40:47 +0000640 select BFIN_GPTIMERS
Graf Yang1fa9be72009-05-15 11:01:59 +0000641 depends on GENERIC_CLOCKEVENTS
642 depends on !TICKSOURCE_GPTMR0
643
john stultz10f03f12009-09-15 21:17:19 -0700644config ARCH_USES_GETTIMEOFFSET
645 depends on !GENERIC_CLOCKEVENTS
646 def_bool y
647
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800648source kernel/time/Kconfig
649
Mike Frysinger5f004c22008-04-25 02:11:24 +0800650comment "Misc"
Sonic Zhang971d5bc2008-01-27 16:32:31 +0800651
Mike Frysingerf0b5d122007-08-05 17:03:59 +0800652choice
653 prompt "Blackfin Exception Scratch Register"
654 default BFIN_SCRATCH_REG_RETN
655 help
656 Select the resource to reserve for the Exception handler:
657 - RETN: Non-Maskable Interrupt (NMI)
658 - RETE: Exception Return (JTAG/ICE)
659 - CYCLES: Performance counter
660
661 If you are unsure, please select "RETN".
662
663config BFIN_SCRATCH_REG_RETN
664 bool "RETN"
665 help
666 Use the RETN register in the Blackfin exception handler
667 as a stack scratch register. This means you cannot
668 safely use NMI on the Blackfin while running Linux, but
669 you can debug the system with a JTAG ICE and use the
670 CYCLES performance registers.
671
672 If you are unsure, please select "RETN".
673
674config BFIN_SCRATCH_REG_RETE
675 bool "RETE"
676 help
677 Use the RETE register in the Blackfin exception handler
678 as a stack scratch register. This means you cannot
679 safely use a JTAG ICE while debugging a Blackfin board,
680 but you can safely use the CYCLES performance registers
681 and the NMI.
682
683 If you are unsure, please select "RETN".
684
685config BFIN_SCRATCH_REG_CYCLES
686 bool "CYCLES"
687 help
688 Use the CYCLES register in the Blackfin exception handler
689 as a stack scratch register. This means you cannot
690 safely use the CYCLES performance registers on a Blackfin
691 board at anytime, but you can debug the system with a JTAG
692 ICE and use the NMI.
693
694 If you are unsure, please select "RETN".
695
696endchoice
697
Bryan Wu1394f032007-05-06 14:50:22 -0700698endmenu
699
700
701menu "Blackfin Kernel Optimizations"
Graf Yang46fa5ee2009-01-07 23:14:39 +0800702 depends on !SMP
Bryan Wu1394f032007-05-06 14:50:22 -0700703
Bryan Wu1394f032007-05-06 14:50:22 -0700704comment "Memory Optimizations"
705
706config I_ENTRY_L1
707 bool "Locate interrupt entry code in L1 Memory"
708 default y
709 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200710 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
711 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700712
713config EXCPT_IRQ_SYSC_L1
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200714 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
Bryan Wu1394f032007-05-06 14:50:22 -0700715 default y
716 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200717 If enabled, the entire ASM lowlevel exception and interrupt entry code
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800718 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200719 (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700720
721config DO_IRQ_L1
722 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
723 default y
724 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200725 If enabled, the frequently called do_irq dispatcher function is linked
726 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700727
728config CORE_TIMER_IRQ_L1
729 bool "Locate frequently called timer_interrupt() function in L1 Memory"
730 default y
731 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200732 If enabled, the frequently called timer_interrupt() function is linked
733 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700734
735config IDLE_L1
736 bool "Locate frequently idle function in L1 Memory"
737 default y
738 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200739 If enabled, the frequently called idle function is linked
740 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700741
742config SCHEDULE_L1
743 bool "Locate kernel schedule function in L1 Memory"
744 default y
745 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200746 If enabled, the frequently called kernel schedule is linked
747 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700748
749config ARITHMETIC_OPS_L1
750 bool "Locate kernel owned arithmetic functions in L1 Memory"
751 default y
752 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200753 If enabled, arithmetic functions are linked
754 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700755
756config ACCESS_OK_L1
757 bool "Locate access_ok function in L1 Memory"
758 default y
759 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200760 If enabled, the access_ok function is linked
761 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700762
763config MEMSET_L1
764 bool "Locate memset function in L1 Memory"
765 default y
766 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200767 If enabled, the memset function is linked
768 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700769
770config MEMCPY_L1
771 bool "Locate memcpy function in L1 Memory"
772 default y
773 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200774 If enabled, the memcpy function is linked
775 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700776
777config SYS_BFIN_SPINLOCK_L1
778 bool "Locate sys_bfin_spinlock function in L1 Memory"
779 default y
780 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200781 If enabled, sys_bfin_spinlock function is linked
782 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700783
784config IP_CHECKSUM_L1
785 bool "Locate IP Checksum function in L1 Memory"
786 default n
787 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200788 If enabled, the IP Checksum function is linked
789 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700790
791config CACHELINE_ALIGNED_L1
792 bool "Locate cacheline_aligned data to L1 Data Memory"
Michael Hennerich157cc5a2007-07-12 16:20:21 +0800793 default y if !BF54x
794 default n if BF54x
Bryan Wu1394f032007-05-06 14:50:22 -0700795 depends on !BF531
796 help
Matt LaPlante692105b2009-01-26 11:12:25 +0100797 If enabled, cacheline_aligned data is linked
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200798 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700799
800config SYSCALL_TAB_L1
801 bool "Locate Syscall Table L1 Data Memory"
802 default n
803 depends on !BF531
804 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200805 If enabled, the Syscall LUT is linked
806 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700807
808config CPLB_SWITCH_TAB_L1
809 bool "Locate CPLB Switch Tables L1 Data Memory"
810 default n
811 depends on !BF531
812 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200813 If enabled, the CPLB Switch Tables are linked
814 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700815
Graf Yangca87b7a2008-10-08 17:30:01 +0800816config APP_STACK_L1
817 bool "Support locating application stack in L1 Scratch Memory"
818 default y
819 help
820 If enabled the application stack can be located in L1
821 scratch memory (less latency).
822
823 Currently only works with FLAT binaries.
824
Mike Frysinger6ad2b842008-10-28 11:03:09 +0800825config EXCEPTION_L1_SCRATCH
826 bool "Locate exception stack in L1 Scratch Memory"
827 default n
Graf Yangf82e0a02009-04-08 08:30:22 +0000828 depends on !APP_STACK_L1
Mike Frysinger6ad2b842008-10-28 11:03:09 +0800829 help
830 Whenever an exception occurs, use the L1 Scratch memory for
831 stack storage. You cannot place the stacks of FLAT binaries
832 in L1 when using this option.
833
834 If you don't use L1 Scratch, then you should say Y here.
835
Robin Getz251383c2008-08-14 15:12:55 +0800836comment "Speed Optimizations"
837config BFIN_INS_LOWOVERHEAD
838 bool "ins[bwl] low overhead, higher interrupt latency"
839 default y
840 help
841 Reads on the Blackfin are speculative. In Blackfin terms, this means
842 they can be interrupted at any time (even after they have been issued
843 on to the external bus), and re-issued after the interrupt occurs.
844 For memory - this is not a big deal, since memory does not change if
845 it sees a read.
846
847 If a FIFO is sitting on the end of the read, it will see two reads,
848 when the core only sees one since the FIFO receives both the read
849 which is cancelled (and not delivered to the core) and the one which
850 is re-issued (which is delivered to the core).
851
852 To solve this, interrupts are turned off before reads occur to
853 I/O space. This option controls which the overhead/latency of
854 controlling interrupts during this time
855 "n" turns interrupts off every read
856 (higher overhead, but lower interrupt latency)
857 "y" turns interrupts off every loop
858 (low overhead, but longer interrupt latency)
859
860 default behavior is to leave this set to on (type "Y"). If you are experiencing
861 interrupt latency issues, it is safe and OK to turn this off.
862
Bryan Wu1394f032007-05-06 14:50:22 -0700863endmenu
864
Bryan Wu1394f032007-05-06 14:50:22 -0700865choice
866 prompt "Kernel executes from"
867 help
868 Choose the memory type that the kernel will be running in.
869
870config RAMKERNEL
871 bool "RAM"
872 help
873 The kernel will be resident in RAM when running.
874
875config ROMKERNEL
876 bool "ROM"
877 help
878 The kernel will be resident in FLASH/ROM when running.
879
880endchoice
881
882source "mm/Kconfig"
883
Mike Frysinger780431e2007-10-21 23:37:54 +0800884config BFIN_GPTIMERS
885 tristate "Enable Blackfin General Purpose Timers API"
886 default n
887 help
888 Enable support for the General Purpose Timers API. If you
889 are unsure, say N.
890
891 To compile this driver as a module, choose M here: the module
Pavel Machek4737f092009-06-05 00:44:53 +0200892 will be called gptimers.
Mike Frysinger780431e2007-10-21 23:37:54 +0800893
Bryan Wu1394f032007-05-06 14:50:22 -0700894choice
Mike Frysingerd292b002008-10-28 11:15:36 +0800895 prompt "Uncached DMA region"
Bryan Wu1394f032007-05-06 14:50:22 -0700896 default DMA_UNCACHED_1M
Cliff Cai86ad7932008-05-17 16:36:52 +0800897config DMA_UNCACHED_4M
898 bool "Enable 4M DMA region"
Bryan Wu1394f032007-05-06 14:50:22 -0700899config DMA_UNCACHED_2M
900 bool "Enable 2M DMA region"
901config DMA_UNCACHED_1M
902 bool "Enable 1M DMA region"
Barry Songc45c0652009-12-02 09:13:36 +0000903config DMA_UNCACHED_512K
904 bool "Enable 512K DMA region"
905config DMA_UNCACHED_256K
906 bool "Enable 256K DMA region"
907config DMA_UNCACHED_128K
908 bool "Enable 128K DMA region"
Bryan Wu1394f032007-05-06 14:50:22 -0700909config DMA_UNCACHED_NONE
910 bool "Disable DMA region"
911endchoice
912
913
914comment "Cache Support"
Jie Zhang41ba6532009-06-16 09:48:33 +0000915
Robin Getz3bebca22007-10-10 23:55:26 +0800916config BFIN_ICACHE
Bryan Wu1394f032007-05-06 14:50:22 -0700917 bool "Enable ICACHE"
Jie Zhang41ba6532009-06-16 09:48:33 +0000918 default y
Jie Zhang41ba6532009-06-16 09:48:33 +0000919config BFIN_EXTMEM_ICACHEABLE
920 bool "Enable ICACHE for external memory"
921 depends on BFIN_ICACHE
922 default y
923config BFIN_L2_ICACHEABLE
924 bool "Enable ICACHE for L2 SRAM"
925 depends on BFIN_ICACHE
926 depends on BF54x || BF561
927 default n
928
Robin Getz3bebca22007-10-10 23:55:26 +0800929config BFIN_DCACHE
Bryan Wu1394f032007-05-06 14:50:22 -0700930 bool "Enable DCACHE"
Jie Zhang41ba6532009-06-16 09:48:33 +0000931 default y
Robin Getz3bebca22007-10-10 23:55:26 +0800932config BFIN_DCACHE_BANKA
Bryan Wu1394f032007-05-06 14:50:22 -0700933 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
Robin Getz3bebca22007-10-10 23:55:26 +0800934 depends on BFIN_DCACHE && !BF531
Bryan Wu1394f032007-05-06 14:50:22 -0700935 default n
Jie Zhang41ba6532009-06-16 09:48:33 +0000936config BFIN_EXTMEM_DCACHEABLE
937 bool "Enable DCACHE for external memory"
Robin Getz3bebca22007-10-10 23:55:26 +0800938 depends on BFIN_DCACHE
Jie Zhang41ba6532009-06-16 09:48:33 +0000939 default y
Graf Yang5ba76672009-05-07 04:09:15 +0000940choice
Jie Zhang41ba6532009-06-16 09:48:33 +0000941 prompt "External memory DCACHE policy"
942 depends on BFIN_EXTMEM_DCACHEABLE
943 default BFIN_EXTMEM_WRITEBACK if !SMP
944 default BFIN_EXTMEM_WRITETHROUGH if SMP
945config BFIN_EXTMEM_WRITEBACK
Graf Yang5ba76672009-05-07 04:09:15 +0000946 bool "Write back"
947 depends on !SMP
Jie Zhang41ba6532009-06-16 09:48:33 +0000948 help
949 Write Back Policy:
950 Cached data will be written back to SDRAM only when needed.
951 This can give a nice increase in performance, but beware of
952 broken drivers that do not properly invalidate/flush their
953 cache.
Graf Yang5ba76672009-05-07 04:09:15 +0000954
Jie Zhang41ba6532009-06-16 09:48:33 +0000955 Write Through Policy:
956 Cached data will always be written back to SDRAM when the
957 cache is updated. This is a completely safe setting, but
958 performance is worse than Write Back.
959
960 If you are unsure of the options and you want to be safe,
961 then go with Write Through.
962
963config BFIN_EXTMEM_WRITETHROUGH
Graf Yang5ba76672009-05-07 04:09:15 +0000964 bool "Write through"
Jie Zhang41ba6532009-06-16 09:48:33 +0000965 help
966 Write Back Policy:
967 Cached data will be written back to SDRAM only when needed.
968 This can give a nice increase in performance, but beware of
969 broken drivers that do not properly invalidate/flush their
970 cache.
Graf Yang5ba76672009-05-07 04:09:15 +0000971
Jie Zhang41ba6532009-06-16 09:48:33 +0000972 Write Through Policy:
973 Cached data will always be written back to SDRAM when the
974 cache is updated. This is a completely safe setting, but
975 performance is worse than Write Back.
976
977 If you are unsure of the options and you want to be safe,
978 then go with Write Through.
Graf Yang5ba76672009-05-07 04:09:15 +0000979
980endchoice
Sonic Zhangf099f392008-10-09 14:11:57 +0800981
Jie Zhang41ba6532009-06-16 09:48:33 +0000982config BFIN_L2_DCACHEABLE
983 bool "Enable DCACHE for L2 SRAM"
984 depends on BFIN_DCACHE
Sonic Zhang9c954f82009-06-30 09:48:03 +0000985 depends on (BF54x || BF561) && !SMP
Jie Zhang41ba6532009-06-16 09:48:33 +0000986 default n
987choice
988 prompt "L2 SRAM DCACHE policy"
989 depends on BFIN_L2_DCACHEABLE
990 default BFIN_L2_WRITEBACK
991config BFIN_L2_WRITEBACK
992 bool "Write back"
Jie Zhang41ba6532009-06-16 09:48:33 +0000993
994config BFIN_L2_WRITETHROUGH
995 bool "Write through"
Jie Zhang41ba6532009-06-16 09:48:33 +0000996endchoice
997
998
999comment "Memory Protection Unit"
Bernd Schmidtb97b8a92008-01-27 18:39:16 +08001000config MPU
1001 bool "Enable the memory protection unit (EXPERIMENTAL)"
1002 default n
1003 help
1004 Use the processor's MPU to protect applications from accessing
1005 memory they do not own. This comes at a performance penalty
1006 and is recommended only for debugging.
1007
Matt LaPlante692105b2009-01-26 11:12:25 +01001008comment "Asynchronous Memory Configuration"
Bryan Wu1394f032007-05-06 14:50:22 -07001009
Mike Frysingerddf416b2007-10-10 18:06:47 +08001010menu "EBIU_AMGCTL Global Control"
Bryan Wu1394f032007-05-06 14:50:22 -07001011config C_AMCKEN
1012 bool "Enable CLKOUT"
1013 default y
1014
1015config C_CDPRIO
1016 bool "DMA has priority over core for ext. accesses"
1017 default n
1018
1019config C_B0PEN
1020 depends on BF561
1021 bool "Bank 0 16 bit packing enable"
1022 default y
1023
1024config C_B1PEN
1025 depends on BF561
1026 bool "Bank 1 16 bit packing enable"
1027 default y
1028
1029config C_B2PEN
1030 depends on BF561
1031 bool "Bank 2 16 bit packing enable"
1032 default y
1033
1034config C_B3PEN
1035 depends on BF561
1036 bool "Bank 3 16 bit packing enable"
1037 default n
1038
1039choice
Matt LaPlante692105b2009-01-26 11:12:25 +01001040 prompt "Enable Asynchronous Memory Banks"
Bryan Wu1394f032007-05-06 14:50:22 -07001041 default C_AMBEN_ALL
1042
1043config C_AMBEN
1044 bool "Disable All Banks"
1045
1046config C_AMBEN_B0
1047 bool "Enable Bank 0"
1048
1049config C_AMBEN_B0_B1
1050 bool "Enable Bank 0 & 1"
1051
1052config C_AMBEN_B0_B1_B2
1053 bool "Enable Bank 0 & 1 & 2"
1054
1055config C_AMBEN_ALL
1056 bool "Enable All Banks"
1057endchoice
1058endmenu
1059
1060menu "EBIU_AMBCTL Control"
1061config BANK_0
Mike Frysingerc8342f82009-03-31 00:18:35 +00001062 hex "Bank 0 (AMBCTL0.L)"
Bryan Wu1394f032007-05-06 14:50:22 -07001063 default 0x7BB0
Mike Frysingerc8342f82009-03-31 00:18:35 +00001064 help
1065 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1066 used to control the Asynchronous Memory Bank 0 settings.
Bryan Wu1394f032007-05-06 14:50:22 -07001067
1068config BANK_1
Mike Frysingerc8342f82009-03-31 00:18:35 +00001069 hex "Bank 1 (AMBCTL0.H)"
Bryan Wu1394f032007-05-06 14:50:22 -07001070 default 0x7BB0
Michael Hennerich197fba52008-05-07 17:03:27 +08001071 default 0x5558 if BF54x
Mike Frysingerc8342f82009-03-31 00:18:35 +00001072 help
1073 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1074 used to control the Asynchronous Memory Bank 1 settings.
Bryan Wu1394f032007-05-06 14:50:22 -07001075
1076config BANK_2
Mike Frysingerc8342f82009-03-31 00:18:35 +00001077 hex "Bank 2 (AMBCTL1.L)"
Bryan Wu1394f032007-05-06 14:50:22 -07001078 default 0x7BB0
Mike Frysingerc8342f82009-03-31 00:18:35 +00001079 help
1080 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1081 used to control the Asynchronous Memory Bank 2 settings.
Bryan Wu1394f032007-05-06 14:50:22 -07001082
1083config BANK_3
Mike Frysingerc8342f82009-03-31 00:18:35 +00001084 hex "Bank 3 (AMBCTL1.H)"
Bryan Wu1394f032007-05-06 14:50:22 -07001085 default 0x99B3
Mike Frysingerc8342f82009-03-31 00:18:35 +00001086 help
1087 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1088 used to control the Asynchronous Memory Bank 3 settings.
1089
Bryan Wu1394f032007-05-06 14:50:22 -07001090endmenu
1091
Sonic Zhange40540b2007-11-21 23:49:52 +08001092config EBIU_MBSCTLVAL
1093 hex "EBIU Bank Select Control Register"
1094 depends on BF54x
1095 default 0
1096
1097config EBIU_MODEVAL
1098 hex "Flash Memory Mode Control Register"
1099 depends on BF54x
1100 default 1
1101
1102config EBIU_FCTLVAL
1103 hex "Flash Memory Bank Control Register"
1104 depends on BF54x
1105 default 6
Bryan Wu1394f032007-05-06 14:50:22 -07001106endmenu
1107
1108#############################################################################
1109menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1110
1111config PCI
1112 bool "PCI support"
Adrian Bunka95ca3b2008-08-27 10:55:05 +08001113 depends on BROKEN
Bryan Wu1394f032007-05-06 14:50:22 -07001114 help
1115 Support for PCI bus.
1116
1117source "drivers/pci/Kconfig"
1118
1119config HOTPLUG
1120 bool "Support for hot-pluggable device"
1121 help
1122 Say Y here if you want to plug devices into your computer while
1123 the system is running, and be able to use them quickly. In many
1124 cases, the devices can likewise be unplugged at any time too.
1125
1126 One well known example of this is PCMCIA- or PC-cards, credit-card
1127 size devices such as network cards, modems or hard drives which are
1128 plugged into slots found on all modern laptop computers. Another
1129 example, used on modern desktops as well as laptops, is USB.
1130
Johannes Berga81792f2008-07-08 19:00:25 +02001131 Enable HOTPLUG and build a modular kernel. Get agent software
1132 (from <http://linux-hotplug.sourceforge.net/>) and install it.
Bryan Wu1394f032007-05-06 14:50:22 -07001133 Then your kernel will automatically call out to a user mode "policy
1134 agent" (/sbin/hotplug) to load modules and set up software needed
1135 to use devices as you hotplug them.
1136
1137source "drivers/pcmcia/Kconfig"
1138
1139source "drivers/pci/hotplug/Kconfig"
1140
1141endmenu
1142
1143menu "Executable file formats"
1144
1145source "fs/Kconfig.binfmt"
1146
1147endmenu
1148
1149menu "Power management options"
Graf Yangad461632009-08-07 03:52:54 +00001150 depends on !SMP
1151
Bryan Wu1394f032007-05-06 14:50:22 -07001152source "kernel/power/Kconfig"
1153
Johannes Bergf4cb5702007-12-08 02:14:00 +01001154config ARCH_SUSPEND_POSSIBLE
1155 def_bool y
Johannes Bergf4cb5702007-12-08 02:14:00 +01001156
Bryan Wu1394f032007-05-06 14:50:22 -07001157choice
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001158 prompt "Standby Power Saving Mode"
Bryan Wu1394f032007-05-06 14:50:22 -07001159 depends on PM
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001160 default PM_BFIN_SLEEP_DEEPER
1161config PM_BFIN_SLEEP_DEEPER
1162 bool "Sleep Deeper"
Bryan Wu1394f032007-05-06 14:50:22 -07001163 help
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001164 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1165 power dissipation by disabling the clock to the processor core (CCLK).
1166 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1167 to 0.85 V to provide the greatest power savings, while preserving the
1168 processor state.
1169 The PLL and system clock (SCLK) continue to operate at a very low
1170 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1171 the SDRAM is put into Self Refresh Mode. Typically an external event
1172 such as GPIO interrupt or RTC activity wakes up the processor.
1173 Various Peripherals such as UART, SPORT, PPI may not function as
1174 normal during Sleep Deeper, due to the reduced SCLK frequency.
1175 When in the sleep mode, system DMA access to L1 memory is not supported.
Bryan Wu1394f032007-05-06 14:50:22 -07001176
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001177 If unsure, select "Sleep Deeper".
1178
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001179config PM_BFIN_SLEEP
1180 bool "Sleep"
1181 help
1182 Sleep Mode (High Power Savings) - The sleep mode reduces power
1183 dissipation by disabling the clock to the processor core (CCLK).
1184 The PLL and system clock (SCLK), however, continue to operate in
1185 this mode. Typically an external event or RTC activity will wake
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001186 up the processor. When in the sleep mode, system DMA access to L1
1187 memory is not supported.
1188
1189 If unsure, select "Sleep Deeper".
Bryan Wu1394f032007-05-06 14:50:22 -07001190endchoice
1191
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001192config PM_WAKEUP_BY_GPIO
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001193 bool "Allow Wakeup from Standby by GPIO"
Michael Hennerichff19fed2009-03-04 17:35:51 +08001194 depends on PM && !BF54x
Bryan Wu1394f032007-05-06 14:50:22 -07001195
1196config PM_WAKEUP_GPIO_NUMBER
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001197 int "GPIO number"
Bryan Wu1394f032007-05-06 14:50:22 -07001198 range 0 47
1199 depends on PM_WAKEUP_BY_GPIO
Mike Frysingerd1a33362008-11-18 17:48:22 +08001200 default 2
Bryan Wu1394f032007-05-06 14:50:22 -07001201
1202choice
1203 prompt "GPIO Polarity"
1204 depends on PM_WAKEUP_BY_GPIO
1205 default PM_WAKEUP_GPIO_POLAR_H
1206config PM_WAKEUP_GPIO_POLAR_H
1207 bool "Active High"
1208config PM_WAKEUP_GPIO_POLAR_L
1209 bool "Active Low"
1210config PM_WAKEUP_GPIO_POLAR_EDGE_F
1211 bool "Falling EDGE"
1212config PM_WAKEUP_GPIO_POLAR_EDGE_R
1213 bool "Rising EDGE"
1214config PM_WAKEUP_GPIO_POLAR_EDGE_B
1215 bool "Both EDGE"
1216endchoice
1217
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001218comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1219 depends on PM
1220
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001221config PM_BFIN_WAKE_PH6
1222 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
Bryan Wu2f6f4bc2008-11-18 17:48:21 +08001223 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001224 default n
1225 help
1226 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1227
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001228config PM_BFIN_WAKE_GP
1229 bool "Allow Wake-Up from GPIOs"
1230 depends on PM && BF54x
1231 default n
1232 help
1233 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
Michael Hennerich19986282009-03-05 16:45:55 +08001234 (all processors, except ADSP-BF549). This option sets
1235 the general-purpose wake-up enable (GPWE) control bit to enable
1236 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1237 On ADSP-BF549 this option enables the the same functionality on the
1238 /MRXON pin also PH7.
1239
Bryan Wu1394f032007-05-06 14:50:22 -07001240endmenu
1241
Bryan Wu1394f032007-05-06 14:50:22 -07001242menu "CPU Frequency scaling"
Graf Yangad461632009-08-07 03:52:54 +00001243 depends on !SMP
Bryan Wu1394f032007-05-06 14:50:22 -07001244
1245source "drivers/cpufreq/Kconfig"
1246
Michael Hennerich5ad2ca52008-11-18 17:48:22 +08001247config BFIN_CPU_FREQ
1248 bool
1249 depends on CPU_FREQ
1250 select CPU_FREQ_TABLE
1251 default y
1252
Michael Hennerich14b03202008-05-07 11:41:26 +08001253config CPU_VOLTAGE
1254 bool "CPU Voltage scaling"
Michael Hennerich73feb5c2009-01-07 23:14:39 +08001255 depends on EXPERIMENTAL
Michael Hennerich14b03202008-05-07 11:41:26 +08001256 depends on CPU_FREQ
1257 default n
1258 help
1259 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1260 This option violates the PLL BYPASS recommendation in the Blackfin Processor
Michael Hennerich73feb5c2009-01-07 23:14:39 +08001261 manuals. There is a theoretical risk that during VDDINT transitions
Michael Hennerich14b03202008-05-07 11:41:26 +08001262 the PLL may unlock.
1263
Bryan Wu1394f032007-05-06 14:50:22 -07001264endmenu
1265
Bryan Wu1394f032007-05-06 14:50:22 -07001266source "net/Kconfig"
1267
1268source "drivers/Kconfig"
1269
Mike Frysinger872d0242009-10-06 04:49:07 +00001270source "drivers/firmware/Kconfig"
1271
Bryan Wu1394f032007-05-06 14:50:22 -07001272source "fs/Kconfig"
1273
Mike Frysinger74ce8322007-11-21 23:50:49 +08001274source "arch/blackfin/Kconfig.debug"
Bryan Wu1394f032007-05-06 14:50:22 -07001275
1276source "security/Kconfig"
1277
1278source "crypto/Kconfig"
1279
1280source "lib/Kconfig"