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Paul Walmsleyb045d082008-03-18 11:24:28 +02001/*
2 * OMAP3 clock framework
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley
Paul Walmsley542313c2008-07-03 12:24:45 +03008 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
10 *
11 */
12
13/*
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
Paul Walmsleyb045d082008-03-18 11:24:28 +020017 */
18
19#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
20#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
21
Russell Kinga09e64f2008-08-05 16:14:15 +010022#include <mach/control.h>
Paul Walmsleyb045d082008-03-18 11:24:28 +020023
24#include "clock.h"
25#include "cm.h"
26#include "cm-regbits-34xx.h"
27#include "prm.h"
28#include "prm-regbits-34xx.h"
29
Russell King8b9dbc12009-02-12 10:12:59 +000030static unsigned long omap3_dpll_recalc(struct clk *clk);
31static unsigned long omap3_clkoutx2_recalc(struct clk *clk);
Paul Walmsley542313c2008-07-03 12:24:45 +030032static void omap3_dpll_allow_idle(struct clk *clk);
33static void omap3_dpll_deny_idle(struct clk *clk);
34static u32 omap3_dpll_autoidle_read(struct clk *clk);
Paul Walmsley16c90f02009-01-27 19:12:47 -070035static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
36static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
Paul Walmsley0eafd472009-01-28 12:27:42 -070037static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
Paul Walmsleyb045d082008-03-18 11:24:28 +020038
Paul Walmsley88b8ba92008-07-03 12:24:46 +030039/* Maximum DPLL multiplier, divider values for OMAP3 */
40#define OMAP3_MAX_DPLL_MULT 2048
41#define OMAP3_MAX_DPLL_DIV 128
42
Paul Walmsleyb045d082008-03-18 11:24:28 +020043/*
44 * DPLL1 supplies clock to the MPU.
45 * DPLL2 supplies clock to the IVA2.
46 * DPLL3 supplies CORE domain clocks.
47 * DPLL4 supplies peripheral clocks.
48 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
49 */
50
Russell Kingc0bf3132009-02-19 13:29:22 +000051/* Forward declarations for DPLL bypass clocks */
52static struct clk dpll1_fck;
53static struct clk dpll2_fck;
54
Paul Walmsley542313c2008-07-03 12:24:45 +030055/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
56#define DPLL_LOW_POWER_STOP 0x1
57#define DPLL_LOW_POWER_BYPASS 0x5
58#define DPLL_LOCKED 0x7
59
Paul Walmsleyb045d082008-03-18 11:24:28 +020060/* PRM CLOCKS */
61
62/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
63static struct clk omap_32k_fck = {
64 .name = "omap_32k_fck",
Russell King897dcde2008-11-04 16:35:03 +000065 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +020066 .rate = 32768,
Russell King3f0a8202009-01-31 10:05:51 +000067 .flags = RATE_FIXED,
Paul Walmsleyb045d082008-03-18 11:24:28 +020068};
69
70static struct clk secure_32k_fck = {
71 .name = "secure_32k_fck",
Russell King897dcde2008-11-04 16:35:03 +000072 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +020073 .rate = 32768,
Russell King3f0a8202009-01-31 10:05:51 +000074 .flags = RATE_FIXED,
Paul Walmsleyb045d082008-03-18 11:24:28 +020075};
76
77/* Virtual source clocks for osc_sys_ck */
78static struct clk virt_12m_ck = {
79 .name = "virt_12m_ck",
Russell King897dcde2008-11-04 16:35:03 +000080 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +020081 .rate = 12000000,
Russell King3f0a8202009-01-31 10:05:51 +000082 .flags = RATE_FIXED,
Paul Walmsleyb045d082008-03-18 11:24:28 +020083};
84
85static struct clk virt_13m_ck = {
86 .name = "virt_13m_ck",
Russell King897dcde2008-11-04 16:35:03 +000087 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +020088 .rate = 13000000,
Russell King3f0a8202009-01-31 10:05:51 +000089 .flags = RATE_FIXED,
Paul Walmsleyb045d082008-03-18 11:24:28 +020090};
91
92static struct clk virt_16_8m_ck = {
93 .name = "virt_16_8m_ck",
Russell King897dcde2008-11-04 16:35:03 +000094 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +020095 .rate = 16800000,
Russell King3f0a8202009-01-31 10:05:51 +000096 .flags = RATE_FIXED,
Paul Walmsleyb045d082008-03-18 11:24:28 +020097};
98
99static struct clk virt_19_2m_ck = {
100 .name = "virt_19_2m_ck",
Russell King897dcde2008-11-04 16:35:03 +0000101 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200102 .rate = 19200000,
Russell King3f0a8202009-01-31 10:05:51 +0000103 .flags = RATE_FIXED,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200104};
105
106static struct clk virt_26m_ck = {
107 .name = "virt_26m_ck",
Russell King897dcde2008-11-04 16:35:03 +0000108 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200109 .rate = 26000000,
Russell King3f0a8202009-01-31 10:05:51 +0000110 .flags = RATE_FIXED,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200111};
112
113static struct clk virt_38_4m_ck = {
114 .name = "virt_38_4m_ck",
Russell King897dcde2008-11-04 16:35:03 +0000115 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200116 .rate = 38400000,
Russell King3f0a8202009-01-31 10:05:51 +0000117 .flags = RATE_FIXED,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200118};
119
120static const struct clksel_rate osc_sys_12m_rates[] = {
121 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
122 { .div = 0 }
123};
124
125static const struct clksel_rate osc_sys_13m_rates[] = {
126 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
127 { .div = 0 }
128};
129
130static const struct clksel_rate osc_sys_16_8m_rates[] = {
131 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
132 { .div = 0 }
133};
134
135static const struct clksel_rate osc_sys_19_2m_rates[] = {
136 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
137 { .div = 0 }
138};
139
140static const struct clksel_rate osc_sys_26m_rates[] = {
141 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
142 { .div = 0 }
143};
144
145static const struct clksel_rate osc_sys_38_4m_rates[] = {
146 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
147 { .div = 0 }
148};
149
150static const struct clksel osc_sys_clksel[] = {
151 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
152 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
153 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
154 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
155 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
156 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
157 { .parent = NULL },
158};
159
160/* Oscillator clock */
161/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
162static struct clk osc_sys_ck = {
163 .name = "osc_sys_ck",
Russell King897dcde2008-11-04 16:35:03 +0000164 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200165 .init = &omap2_init_clksel_parent,
166 .clksel_reg = OMAP3430_PRM_CLKSEL,
167 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
168 .clksel = osc_sys_clksel,
169 /* REVISIT: deal with autoextclkmode? */
Russell King3f0a8202009-01-31 10:05:51 +0000170 .flags = RATE_FIXED,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200171 .recalc = &omap2_clksel_recalc,
172};
173
174static const struct clksel_rate div2_rates[] = {
175 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
176 { .div = 2, .val = 2, .flags = RATE_IN_343X },
177 { .div = 0 }
178};
179
180static const struct clksel sys_clksel[] = {
181 { .parent = &osc_sys_ck, .rates = div2_rates },
182 { .parent = NULL }
183};
184
185/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
186/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
187static struct clk sys_ck = {
188 .name = "sys_ck",
Russell King897dcde2008-11-04 16:35:03 +0000189 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200190 .parent = &osc_sys_ck,
191 .init = &omap2_init_clksel_parent,
192 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
193 .clksel_mask = OMAP_SYSCLKDIV_MASK,
194 .clksel = sys_clksel,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200195 .recalc = &omap2_clksel_recalc,
196};
197
198static struct clk sys_altclk = {
199 .name = "sys_altclk",
Russell King897dcde2008-11-04 16:35:03 +0000200 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200201};
202
203/* Optional external clock input for some McBSPs */
204static struct clk mcbsp_clks = {
205 .name = "mcbsp_clks",
Russell King897dcde2008-11-04 16:35:03 +0000206 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200207};
208
209/* PRM EXTERNAL CLOCK OUTPUT */
210
211static struct clk sys_clkout1 = {
212 .name = "sys_clkout1",
Russell Kingc1168dc2008-11-04 21:24:00 +0000213 .ops = &clkops_omap2_dflt,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200214 .parent = &osc_sys_ck,
215 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
216 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200217 .recalc = &followparent_recalc,
218};
219
220/* DPLLS */
221
222/* CM CLOCKS */
223
Paul Walmsleyb045d082008-03-18 11:24:28 +0200224static const struct clksel_rate div16_dpll_rates[] = {
225 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
226 { .div = 2, .val = 2, .flags = RATE_IN_343X },
227 { .div = 3, .val = 3, .flags = RATE_IN_343X },
228 { .div = 4, .val = 4, .flags = RATE_IN_343X },
229 { .div = 5, .val = 5, .flags = RATE_IN_343X },
230 { .div = 6, .val = 6, .flags = RATE_IN_343X },
231 { .div = 7, .val = 7, .flags = RATE_IN_343X },
232 { .div = 8, .val = 8, .flags = RATE_IN_343X },
233 { .div = 9, .val = 9, .flags = RATE_IN_343X },
234 { .div = 10, .val = 10, .flags = RATE_IN_343X },
235 { .div = 11, .val = 11, .flags = RATE_IN_343X },
236 { .div = 12, .val = 12, .flags = RATE_IN_343X },
237 { .div = 13, .val = 13, .flags = RATE_IN_343X },
238 { .div = 14, .val = 14, .flags = RATE_IN_343X },
239 { .div = 15, .val = 15, .flags = RATE_IN_343X },
240 { .div = 16, .val = 16, .flags = RATE_IN_343X },
241 { .div = 0 }
242};
243
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200244/* DPLL1 */
245/* MPU clock source */
246/* Type: DPLL */
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300247static struct dpll_data dpll1_dd = {
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200248 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
249 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
250 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
Russell Kingc0bf3132009-02-19 13:29:22 +0000251 .clk_bypass = &dpll1_fck,
252 .clk_ref = &sys_ck,
Paul Walmsley16c90f02009-01-27 19:12:47 -0700253 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200254 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
255 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
Paul Walmsley542313c2008-07-03 12:24:45 +0300256 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200257 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
258 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
259 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
Paul Walmsley542313c2008-07-03 12:24:45 +0300260 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
261 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
262 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
Paul Walmsleyc1bd7aa2009-01-28 12:08:17 -0700263 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300264 .max_multiplier = OMAP3_MAX_DPLL_MULT,
Paul Walmsley95f538a2009-01-28 12:08:44 -0700265 .min_divider = 1,
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300266 .max_divider = OMAP3_MAX_DPLL_DIV,
267 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200268};
269
270static struct clk dpll1_ck = {
271 .name = "dpll1_ck",
Russell King897dcde2008-11-04 16:35:03 +0000272 .ops = &clkops_null,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200273 .parent = &sys_ck,
274 .dpll_data = &dpll1_dd,
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300275 .round_rate = &omap2_dpll_round_rate,
Paul Walmsley16c90f02009-01-27 19:12:47 -0700276 .set_rate = &omap3_noncore_dpll_set_rate,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700277 .clkdm_name = "dpll1_clkdm",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200278 .recalc = &omap3_dpll_recalc,
279};
280
281/*
282 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
283 * DPLL isn't bypassed.
284 */
285static struct clk dpll1_x2_ck = {
286 .name = "dpll1_x2_ck",
Russell King57137182008-11-04 16:48:35 +0000287 .ops = &clkops_null,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200288 .parent = &dpll1_ck,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700289 .clkdm_name = "dpll1_clkdm",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200290 .recalc = &omap3_clkoutx2_recalc,
291};
292
293/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
294static const struct clksel div16_dpll1_x2m2_clksel[] = {
295 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
296 { .parent = NULL }
297};
298
299/*
300 * Does not exist in the TRM - needed to separate the M2 divider from
301 * bypass selection in mpu_ck
302 */
303static struct clk dpll1_x2m2_ck = {
304 .name = "dpll1_x2m2_ck",
Russell King57137182008-11-04 16:48:35 +0000305 .ops = &clkops_null,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200306 .parent = &dpll1_x2_ck,
307 .init = &omap2_init_clksel_parent,
308 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
309 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
310 .clksel = div16_dpll1_x2m2_clksel,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700311 .clkdm_name = "dpll1_clkdm",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200312 .recalc = &omap2_clksel_recalc,
313};
314
315/* DPLL2 */
316/* IVA2 clock source */
317/* Type: DPLL */
318
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300319static struct dpll_data dpll2_dd = {
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200320 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
321 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
322 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
Russell Kingc0bf3132009-02-19 13:29:22 +0000323 .clk_bypass = &dpll2_fck,
324 .clk_ref = &sys_ck,
Paul Walmsley16c90f02009-01-27 19:12:47 -0700325 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200326 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
327 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
Paul Walmsley542313c2008-07-03 12:24:45 +0300328 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
329 (1 << DPLL_LOW_POWER_BYPASS),
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200330 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
331 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
332 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
Paul Walmsley542313c2008-07-03 12:24:45 +0300333 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
334 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
335 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
Paul Walmsleyc1bd7aa2009-01-28 12:08:17 -0700336 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300337 .max_multiplier = OMAP3_MAX_DPLL_MULT,
Paul Walmsley95f538a2009-01-28 12:08:44 -0700338 .min_divider = 1,
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300339 .max_divider = OMAP3_MAX_DPLL_DIV,
340 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200341};
342
343static struct clk dpll2_ck = {
344 .name = "dpll2_ck",
Russell King548d8492008-11-04 14:02:46 +0000345 .ops = &clkops_noncore_dpll_ops,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200346 .parent = &sys_ck,
347 .dpll_data = &dpll2_dd,
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300348 .round_rate = &omap2_dpll_round_rate,
Paul Walmsley16c90f02009-01-27 19:12:47 -0700349 .set_rate = &omap3_noncore_dpll_set_rate,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700350 .clkdm_name = "dpll2_clkdm",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200351 .recalc = &omap3_dpll_recalc,
352};
353
354static const struct clksel div16_dpll2_m2x2_clksel[] = {
355 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
356 { .parent = NULL }
357};
358
359/*
360 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
361 * or CLKOUTX2. CLKOUT seems most plausible.
362 */
363static struct clk dpll2_m2_ck = {
364 .name = "dpll2_m2_ck",
Russell King57137182008-11-04 16:48:35 +0000365 .ops = &clkops_null,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200366 .parent = &dpll2_ck,
367 .init = &omap2_init_clksel_parent,
368 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
369 OMAP3430_CM_CLKSEL2_PLL),
370 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
371 .clksel = div16_dpll2_m2x2_clksel,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700372 .clkdm_name = "dpll2_clkdm",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200373 .recalc = &omap2_clksel_recalc,
374};
375
Paul Walmsley542313c2008-07-03 12:24:45 +0300376/*
377 * DPLL3
378 * Source clock for all interfaces and for some device fclks
379 * REVISIT: Also supports fast relock bypass - not included below
380 */
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300381static struct dpll_data dpll3_dd = {
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200382 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
383 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
384 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
Russell Kingc0bf3132009-02-19 13:29:22 +0000385 .clk_bypass = &sys_ck,
386 .clk_ref = &sys_ck,
Paul Walmsley16c90f02009-01-27 19:12:47 -0700387 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200388 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
389 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
390 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
391 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
392 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
Paul Walmsley542313c2008-07-03 12:24:45 +0300393 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
394 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
Paul Walmsleyc1bd7aa2009-01-28 12:08:17 -0700395 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
396 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300397 .max_multiplier = OMAP3_MAX_DPLL_MULT,
Paul Walmsley95f538a2009-01-28 12:08:44 -0700398 .min_divider = 1,
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300399 .max_divider = OMAP3_MAX_DPLL_DIV,
400 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200401};
402
403static struct clk dpll3_ck = {
404 .name = "dpll3_ck",
Russell King897dcde2008-11-04 16:35:03 +0000405 .ops = &clkops_null,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200406 .parent = &sys_ck,
407 .dpll_data = &dpll3_dd,
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300408 .round_rate = &omap2_dpll_round_rate,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700409 .clkdm_name = "dpll3_clkdm",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200410 .recalc = &omap3_dpll_recalc,
411};
412
413/*
414 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
415 * DPLL isn't bypassed
416 */
417static struct clk dpll3_x2_ck = {
418 .name = "dpll3_x2_ck",
Russell King57137182008-11-04 16:48:35 +0000419 .ops = &clkops_null,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200420 .parent = &dpll3_ck,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700421 .clkdm_name = "dpll3_clkdm",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200422 .recalc = &omap3_clkoutx2_recalc,
423};
424
Paul Walmsleyb045d082008-03-18 11:24:28 +0200425static const struct clksel_rate div31_dpll3_rates[] = {
426 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
427 { .div = 2, .val = 2, .flags = RATE_IN_343X },
428 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
429 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
430 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
431 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
432 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
433 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
434 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
435 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
436 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
437 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
438 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
439 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
440 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
441 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
442 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
443 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
444 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
445 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
446 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
447 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
448 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
449 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
450 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
451 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
452 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
453 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
454 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
455 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
456 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
457 { .div = 0 },
458};
459
460static const struct clksel div31_dpll3m2_clksel[] = {
461 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
462 { .parent = NULL }
463};
464
Paul Walmsley0eafd472009-01-28 12:27:42 -0700465/* DPLL3 output M2 - primary control point for CORE speed */
Paul Walmsleyb045d082008-03-18 11:24:28 +0200466static struct clk dpll3_m2_ck = {
467 .name = "dpll3_m2_ck",
Russell King57137182008-11-04 16:48:35 +0000468 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200469 .parent = &dpll3_ck,
470 .init = &omap2_init_clksel_parent,
471 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
472 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
473 .clksel = div31_dpll3m2_clksel,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700474 .clkdm_name = "dpll3_clkdm",
Paul Walmsley0eafd472009-01-28 12:27:42 -0700475 .round_rate = &omap2_clksel_round_rate,
476 .set_rate = &omap3_core_dpll_m2_set_rate,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200477 .recalc = &omap2_clksel_recalc,
478};
479
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200480static struct clk core_ck = {
481 .name = "core_ck",
Russell King57137182008-11-04 16:48:35 +0000482 .ops = &clkops_null,
Russell Kingc0bf3132009-02-19 13:29:22 +0000483 .parent = &dpll3_m2_ck,
484 .recalc = &followparent_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200485};
486
487static struct clk dpll3_m2x2_ck = {
488 .name = "dpll3_m2x2_ck",
Russell King57137182008-11-04 16:48:35 +0000489 .ops = &clkops_null,
Russell Kingc0bf3132009-02-19 13:29:22 +0000490 .parent = &dpll3_x2_ck,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700491 .clkdm_name = "dpll3_clkdm",
Russell Kingc0bf3132009-02-19 13:29:22 +0000492 .recalc = &followparent_recalc,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200493};
494
495/* The PWRDN bit is apparently only available on 3430ES2 and above */
496static const struct clksel div16_dpll3_clksel[] = {
497 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
498 { .parent = NULL }
499};
500
501/* This virtual clock is the source for dpll3_m3x2_ck */
502static struct clk dpll3_m3_ck = {
503 .name = "dpll3_m3_ck",
Russell King57137182008-11-04 16:48:35 +0000504 .ops = &clkops_null,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200505 .parent = &dpll3_ck,
506 .init = &omap2_init_clksel_parent,
507 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
508 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
509 .clksel = div16_dpll3_clksel,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700510 .clkdm_name = "dpll3_clkdm",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200511 .recalc = &omap2_clksel_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200512};
513
514/* The PWRDN bit is apparently only available on 3430ES2 and above */
515static struct clk dpll3_m3x2_ck = {
516 .name = "dpll3_m3x2_ck",
Russell Kingb36ee722008-11-04 17:59:52 +0000517 .ops = &clkops_omap2_dflt_wait,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200518 .parent = &dpll3_m3_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200519 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
520 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
Russell King3f0a8202009-01-31 10:05:51 +0000521 .flags = INVERT_ENABLE,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700522 .clkdm_name = "dpll3_clkdm",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200523 .recalc = &omap3_clkoutx2_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200524};
525
Paul Walmsleyb045d082008-03-18 11:24:28 +0200526static struct clk emu_core_alwon_ck = {
527 .name = "emu_core_alwon_ck",
Russell King57137182008-11-04 16:48:35 +0000528 .ops = &clkops_null,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200529 .parent = &dpll3_m3x2_ck,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700530 .clkdm_name = "dpll3_clkdm",
Russell Kingc0bf3132009-02-19 13:29:22 +0000531 .recalc = &followparent_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200532};
533
534/* DPLL4 */
535/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
536/* Type: DPLL */
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300537static struct dpll_data dpll4_dd = {
Paul Walmsleyb045d082008-03-18 11:24:28 +0200538 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
539 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
540 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
Russell Kingc0bf3132009-02-19 13:29:22 +0000541 .clk_bypass = &sys_ck,
542 .clk_ref = &sys_ck,
Paul Walmsley16c90f02009-01-27 19:12:47 -0700543 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200544 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
545 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
Paul Walmsley542313c2008-07-03 12:24:45 +0300546 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
Paul Walmsleyb045d082008-03-18 11:24:28 +0200547 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
548 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
549 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
Paul Walmsley542313c2008-07-03 12:24:45 +0300550 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
551 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
552 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
Paul Walmsleyc1bd7aa2009-01-28 12:08:17 -0700553 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300554 .max_multiplier = OMAP3_MAX_DPLL_MULT,
Paul Walmsley95f538a2009-01-28 12:08:44 -0700555 .min_divider = 1,
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300556 .max_divider = OMAP3_MAX_DPLL_DIV,
557 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
Paul Walmsleyb045d082008-03-18 11:24:28 +0200558};
559
560static struct clk dpll4_ck = {
561 .name = "dpll4_ck",
Russell King548d8492008-11-04 14:02:46 +0000562 .ops = &clkops_noncore_dpll_ops,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200563 .parent = &sys_ck,
564 .dpll_data = &dpll4_dd,
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300565 .round_rate = &omap2_dpll_round_rate,
Paul Walmsley16c90f02009-01-27 19:12:47 -0700566 .set_rate = &omap3_dpll4_set_rate,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700567 .clkdm_name = "dpll4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +0200568 .recalc = &omap3_dpll_recalc,
569};
570
571/*
572 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200573 * DPLL isn't bypassed --
574 * XXX does this serve any downstream clocks?
Paul Walmsleyb045d082008-03-18 11:24:28 +0200575 */
576static struct clk dpll4_x2_ck = {
577 .name = "dpll4_x2_ck",
Russell King57137182008-11-04 16:48:35 +0000578 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200579 .parent = &dpll4_ck,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700580 .clkdm_name = "dpll4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +0200581 .recalc = &omap3_clkoutx2_recalc,
582};
583
584static const struct clksel div16_dpll4_clksel[] = {
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200585 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
Paul Walmsleyb045d082008-03-18 11:24:28 +0200586 { .parent = NULL }
587};
588
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200589/* This virtual clock is the source for dpll4_m2x2_ck */
590static struct clk dpll4_m2_ck = {
591 .name = "dpll4_m2_ck",
Russell King57137182008-11-04 16:48:35 +0000592 .ops = &clkops_null,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200593 .parent = &dpll4_ck,
594 .init = &omap2_init_clksel_parent,
595 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
596 .clksel_mask = OMAP3430_DIV_96M_MASK,
597 .clksel = div16_dpll4_clksel,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700598 .clkdm_name = "dpll4_clkdm",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200599 .recalc = &omap2_clksel_recalc,
600};
601
Paul Walmsleyb045d082008-03-18 11:24:28 +0200602/* The PWRDN bit is apparently only available on 3430ES2 and above */
603static struct clk dpll4_m2x2_ck = {
604 .name = "dpll4_m2x2_ck",
Russell Kingb36ee722008-11-04 17:59:52 +0000605 .ops = &clkops_omap2_dflt_wait,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200606 .parent = &dpll4_m2_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200607 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
608 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
Russell King3f0a8202009-01-31 10:05:51 +0000609 .flags = INVERT_ENABLE,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700610 .clkdm_name = "dpll4_clkdm",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200611 .recalc = &omap3_clkoutx2_recalc,
612};
613
Paul Walmsley9cfd9852009-01-27 19:13:02 -0700614/*
615 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
616 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
617 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
618 * CM_96K_(F)CLK.
619 */
Paul Walmsleyb045d082008-03-18 11:24:28 +0200620static struct clk omap_96m_alwon_fck = {
621 .name = "omap_96m_alwon_fck",
Russell King57137182008-11-04 16:48:35 +0000622 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200623 .parent = &dpll4_m2x2_ck,
Russell Kingc0bf3132009-02-19 13:29:22 +0000624 .recalc = &followparent_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200625};
626
Paul Walmsley9cfd9852009-01-27 19:13:02 -0700627static struct clk cm_96m_fck = {
628 .name = "cm_96m_fck",
Russell King57137182008-11-04 16:48:35 +0000629 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200630 .parent = &omap_96m_alwon_fck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200631 .recalc = &followparent_recalc,
632};
633
Paul Walmsley9cfd9852009-01-27 19:13:02 -0700634static const struct clksel_rate omap_96m_dpll_rates[] = {
635 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
636 { .div = 0 }
637};
638
639static const struct clksel_rate omap_96m_sys_rates[] = {
640 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
641 { .div = 0 }
642};
643
644static const struct clksel omap_96m_fck_clksel[] = {
645 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
646 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200647 { .parent = NULL }
648};
649
Paul Walmsley9cfd9852009-01-27 19:13:02 -0700650static struct clk omap_96m_fck = {
651 .name = "omap_96m_fck",
Russell King57137182008-11-04 16:48:35 +0000652 .ops = &clkops_null,
Paul Walmsley9cfd9852009-01-27 19:13:02 -0700653 .parent = &sys_ck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200654 .init = &omap2_init_clksel_parent,
Paul Walmsley9cfd9852009-01-27 19:13:02 -0700655 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
656 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
657 .clksel = omap_96m_fck_clksel,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200658 .recalc = &omap2_clksel_recalc,
659};
660
661/* This virtual clock is the source for dpll4_m3x2_ck */
662static struct clk dpll4_m3_ck = {
663 .name = "dpll4_m3_ck",
Russell King57137182008-11-04 16:48:35 +0000664 .ops = &clkops_null,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200665 .parent = &dpll4_ck,
666 .init = &omap2_init_clksel_parent,
667 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
668 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
669 .clksel = div16_dpll4_clksel,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700670 .clkdm_name = "dpll4_clkdm",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200671 .recalc = &omap2_clksel_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200672};
673
674/* The PWRDN bit is apparently only available on 3430ES2 and above */
675static struct clk dpll4_m3x2_ck = {
676 .name = "dpll4_m3x2_ck",
Russell Kingb36ee722008-11-04 17:59:52 +0000677 .ops = &clkops_omap2_dflt_wait,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200678 .parent = &dpll4_m3_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200679 .init = &omap2_init_clksel_parent,
680 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
681 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
Russell King3f0a8202009-01-31 10:05:51 +0000682 .flags = INVERT_ENABLE,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700683 .clkdm_name = "dpll4_clkdm",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200684 .recalc = &omap3_clkoutx2_recalc,
685};
686
Paul Walmsleyb045d082008-03-18 11:24:28 +0200687static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
688 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
689 { .div = 0 }
690};
691
692static const struct clksel_rate omap_54m_alt_rates[] = {
693 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
694 { .div = 0 }
695};
696
697static const struct clksel omap_54m_clksel[] = {
Russell Kingc0bf3132009-02-19 13:29:22 +0000698 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
Paul Walmsleyb045d082008-03-18 11:24:28 +0200699 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
700 { .parent = NULL }
701};
702
703static struct clk omap_54m_fck = {
704 .name = "omap_54m_fck",
Russell King57137182008-11-04 16:48:35 +0000705 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200706 .init = &omap2_init_clksel_parent,
707 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
Paul Walmsley9cfd9852009-01-27 19:13:02 -0700708 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200709 .clksel = omap_54m_clksel,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200710 .recalc = &omap2_clksel_recalc,
711};
712
Paul Walmsley9cfd9852009-01-27 19:13:02 -0700713static const struct clksel_rate omap_48m_cm96m_rates[] = {
Paul Walmsleyb045d082008-03-18 11:24:28 +0200714 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
715 { .div = 0 }
716};
717
718static const struct clksel_rate omap_48m_alt_rates[] = {
719 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
720 { .div = 0 }
721};
722
723static const struct clksel omap_48m_clksel[] = {
Paul Walmsley9cfd9852009-01-27 19:13:02 -0700724 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
Paul Walmsleyb045d082008-03-18 11:24:28 +0200725 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
726 { .parent = NULL }
727};
728
729static struct clk omap_48m_fck = {
730 .name = "omap_48m_fck",
Russell King57137182008-11-04 16:48:35 +0000731 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200732 .init = &omap2_init_clksel_parent,
733 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
Paul Walmsley9cfd9852009-01-27 19:13:02 -0700734 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200735 .clksel = omap_48m_clksel,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200736 .recalc = &omap2_clksel_recalc,
737};
738
739static struct clk omap_12m_fck = {
740 .name = "omap_12m_fck",
Russell King57137182008-11-04 16:48:35 +0000741 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200742 .parent = &omap_48m_fck,
743 .fixed_div = 4,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200744 .recalc = &omap2_fixed_divisor_recalc,
745};
746
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200747/* This virstual clock is the source for dpll4_m4x2_ck */
748static struct clk dpll4_m4_ck = {
749 .name = "dpll4_m4_ck",
Russell King57137182008-11-04 16:48:35 +0000750 .ops = &clkops_null,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200751 .parent = &dpll4_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200752 .init = &omap2_init_clksel_parent,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200753 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
754 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
755 .clksel = div16_dpll4_clksel,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700756 .clkdm_name = "dpll4_clkdm",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200757 .recalc = &omap2_clksel_recalc,
Paul Walmsleyae8578c2009-01-27 19:13:12 -0700758 .set_rate = &omap2_clksel_set_rate,
759 .round_rate = &omap2_clksel_round_rate,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200760};
761
762/* The PWRDN bit is apparently only available on 3430ES2 and above */
763static struct clk dpll4_m4x2_ck = {
764 .name = "dpll4_m4x2_ck",
Russell Kingb36ee722008-11-04 17:59:52 +0000765 .ops = &clkops_omap2_dflt_wait,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200766 .parent = &dpll4_m4_ck,
767 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
768 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
Russell King3f0a8202009-01-31 10:05:51 +0000769 .flags = INVERT_ENABLE,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700770 .clkdm_name = "dpll4_clkdm",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200771 .recalc = &omap3_clkoutx2_recalc,
772};
773
774/* This virtual clock is the source for dpll4_m5x2_ck */
775static struct clk dpll4_m5_ck = {
776 .name = "dpll4_m5_ck",
Russell King57137182008-11-04 16:48:35 +0000777 .ops = &clkops_null,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200778 .parent = &dpll4_ck,
779 .init = &omap2_init_clksel_parent,
780 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
781 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
782 .clksel = div16_dpll4_clksel,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700783 .clkdm_name = "dpll4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +0200784 .recalc = &omap2_clksel_recalc,
785};
786
787/* The PWRDN bit is apparently only available on 3430ES2 and above */
788static struct clk dpll4_m5x2_ck = {
789 .name = "dpll4_m5x2_ck",
Russell Kingb36ee722008-11-04 17:59:52 +0000790 .ops = &clkops_omap2_dflt_wait,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200791 .parent = &dpll4_m5_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200792 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
793 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
Russell King3f0a8202009-01-31 10:05:51 +0000794 .flags = INVERT_ENABLE,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700795 .clkdm_name = "dpll4_clkdm",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200796 .recalc = &omap3_clkoutx2_recalc,
797};
798
799/* This virtual clock is the source for dpll4_m6x2_ck */
800static struct clk dpll4_m6_ck = {
801 .name = "dpll4_m6_ck",
Russell King57137182008-11-04 16:48:35 +0000802 .ops = &clkops_null,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200803 .parent = &dpll4_ck,
804 .init = &omap2_init_clksel_parent,
805 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
806 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
807 .clksel = div16_dpll4_clksel,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700808 .clkdm_name = "dpll4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +0200809 .recalc = &omap2_clksel_recalc,
810};
811
812/* The PWRDN bit is apparently only available on 3430ES2 and above */
813static struct clk dpll4_m6x2_ck = {
814 .name = "dpll4_m6x2_ck",
Russell Kingb36ee722008-11-04 17:59:52 +0000815 .ops = &clkops_omap2_dflt_wait,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200816 .parent = &dpll4_m6_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200817 .init = &omap2_init_clksel_parent,
818 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
819 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
Russell King3f0a8202009-01-31 10:05:51 +0000820 .flags = INVERT_ENABLE,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700821 .clkdm_name = "dpll4_clkdm",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200822 .recalc = &omap3_clkoutx2_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200823};
824
825static struct clk emu_per_alwon_ck = {
826 .name = "emu_per_alwon_ck",
Russell King57137182008-11-04 16:48:35 +0000827 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200828 .parent = &dpll4_m6x2_ck,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700829 .clkdm_name = "dpll4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +0200830 .recalc = &followparent_recalc,
831};
832
833/* DPLL5 */
834/* Supplies 120MHz clock, USIM source clock */
835/* Type: DPLL */
836/* 3430ES2 only */
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300837static struct dpll_data dpll5_dd = {
Paul Walmsleyb045d082008-03-18 11:24:28 +0200838 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
839 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
840 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
Russell Kingc0bf3132009-02-19 13:29:22 +0000841 .clk_bypass = &sys_ck,
842 .clk_ref = &sys_ck,
Paul Walmsley16c90f02009-01-27 19:12:47 -0700843 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200844 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
845 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
Paul Walmsley542313c2008-07-03 12:24:45 +0300846 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
Paul Walmsleyb045d082008-03-18 11:24:28 +0200847 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
848 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
849 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
Paul Walmsley542313c2008-07-03 12:24:45 +0300850 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
851 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
852 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
Paul Walmsleyc1bd7aa2009-01-28 12:08:17 -0700853 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300854 .max_multiplier = OMAP3_MAX_DPLL_MULT,
Paul Walmsley95f538a2009-01-28 12:08:44 -0700855 .min_divider = 1,
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300856 .max_divider = OMAP3_MAX_DPLL_DIV,
857 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
Paul Walmsleyb045d082008-03-18 11:24:28 +0200858};
859
860static struct clk dpll5_ck = {
861 .name = "dpll5_ck",
Russell King548d8492008-11-04 14:02:46 +0000862 .ops = &clkops_noncore_dpll_ops,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200863 .parent = &sys_ck,
864 .dpll_data = &dpll5_dd,
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300865 .round_rate = &omap2_dpll_round_rate,
Paul Walmsley16c90f02009-01-27 19:12:47 -0700866 .set_rate = &omap3_noncore_dpll_set_rate,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700867 .clkdm_name = "dpll5_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +0200868 .recalc = &omap3_dpll_recalc,
869};
870
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200871static const struct clksel div16_dpll5_clksel[] = {
Paul Walmsleyb045d082008-03-18 11:24:28 +0200872 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
873 { .parent = NULL }
874};
875
876static struct clk dpll5_m2_ck = {
877 .name = "dpll5_m2_ck",
Russell King57137182008-11-04 16:48:35 +0000878 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200879 .parent = &dpll5_ck,
880 .init = &omap2_init_clksel_parent,
881 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
882 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200883 .clksel = div16_dpll5_clksel,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700884 .clkdm_name = "dpll5_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +0200885 .recalc = &omap2_clksel_recalc,
886};
887
Paul Walmsleyb045d082008-03-18 11:24:28 +0200888/* CM EXTERNAL CLOCK OUTPUTS */
889
890static const struct clksel_rate clkout2_src_core_rates[] = {
891 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
892 { .div = 0 }
893};
894
895static const struct clksel_rate clkout2_src_sys_rates[] = {
896 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
897 { .div = 0 }
898};
899
900static const struct clksel_rate clkout2_src_96m_rates[] = {
901 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
902 { .div = 0 }
903};
904
905static const struct clksel_rate clkout2_src_54m_rates[] = {
906 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
907 { .div = 0 }
908};
909
910static const struct clksel clkout2_src_clksel[] = {
Paul Walmsley9cfd9852009-01-27 19:13:02 -0700911 { .parent = &core_ck, .rates = clkout2_src_core_rates },
912 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
913 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
914 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
Paul Walmsleyb045d082008-03-18 11:24:28 +0200915 { .parent = NULL }
916};
917
918static struct clk clkout2_src_ck = {
919 .name = "clkout2_src_ck",
Russell Kingc1168dc2008-11-04 21:24:00 +0000920 .ops = &clkops_omap2_dflt,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200921 .init = &omap2_init_clksel_parent,
922 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
923 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
924 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
925 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
926 .clksel = clkout2_src_clksel,
Paul Walmsley15b52bc2008-05-07 19:19:07 -0600927 .clkdm_name = "core_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +0200928 .recalc = &omap2_clksel_recalc,
929};
930
931static const struct clksel_rate sys_clkout2_rates[] = {
932 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
933 { .div = 2, .val = 1, .flags = RATE_IN_343X },
934 { .div = 4, .val = 2, .flags = RATE_IN_343X },
935 { .div = 8, .val = 3, .flags = RATE_IN_343X },
936 { .div = 16, .val = 4, .flags = RATE_IN_343X },
937 { .div = 0 },
938};
939
940static const struct clksel sys_clkout2_clksel[] = {
941 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
942 { .parent = NULL },
943};
944
945static struct clk sys_clkout2 = {
946 .name = "sys_clkout2",
Russell King57137182008-11-04 16:48:35 +0000947 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200948 .init = &omap2_init_clksel_parent,
949 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
950 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
951 .clksel = sys_clkout2_clksel,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200952 .recalc = &omap2_clksel_recalc,
953};
954
955/* CM OUTPUT CLOCKS */
956
957static struct clk corex2_fck = {
958 .name = "corex2_fck",
Russell King57137182008-11-04 16:48:35 +0000959 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200960 .parent = &dpll3_m2x2_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200961 .recalc = &followparent_recalc,
962};
963
964/* DPLL power domain clock controls */
965
Paul Walmsleyb8168d12009-01-28 12:08:14 -0700966static const struct clksel_rate div4_rates[] = {
967 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
968 { .div = 2, .val = 2, .flags = RATE_IN_343X },
969 { .div = 4, .val = 4, .flags = RATE_IN_343X },
970 { .div = 0 }
971};
972
973static const struct clksel div4_core_clksel[] = {
974 { .parent = &core_ck, .rates = div4_rates },
Paul Walmsleyb045d082008-03-18 11:24:28 +0200975 { .parent = NULL }
976};
977
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200978/*
979 * REVISIT: Are these in DPLL power domain or CM power domain? docs
980 * may be inconsistent here?
981 */
Paul Walmsleyb045d082008-03-18 11:24:28 +0200982static struct clk dpll1_fck = {
983 .name = "dpll1_fck",
Russell King57137182008-11-04 16:48:35 +0000984 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200985 .parent = &core_ck,
986 .init = &omap2_init_clksel_parent,
987 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
988 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
Paul Walmsleyb8168d12009-01-28 12:08:14 -0700989 .clksel = div4_core_clksel,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200990 .recalc = &omap2_clksel_recalc,
991};
992
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200993static struct clk mpu_ck = {
994 .name = "mpu_ck",
Russell King57137182008-11-04 16:48:35 +0000995 .ops = &clkops_null,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200996 .parent = &dpll1_x2m2_ck,
Paul Walmsley333943b2008-08-19 11:08:45 +0300997 .clkdm_name = "mpu_clkdm",
Russell Kingc0bf3132009-02-19 13:29:22 +0000998 .recalc = &followparent_recalc,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200999};
1000
1001/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1002static const struct clksel_rate arm_fck_rates[] = {
1003 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1004 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1005 { .div = 0 },
1006};
1007
1008static const struct clksel arm_fck_clksel[] = {
1009 { .parent = &mpu_ck, .rates = arm_fck_rates },
1010 { .parent = NULL }
1011};
1012
1013static struct clk arm_fck = {
1014 .name = "arm_fck",
Russell King57137182008-11-04 16:48:35 +00001015 .ops = &clkops_null,
Roman Tereshonkov3760d312008-03-13 21:35:09 +02001016 .parent = &mpu_ck,
1017 .init = &omap2_init_clksel_parent,
1018 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1019 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1020 .clksel = arm_fck_clksel,
Roman Tereshonkov3760d312008-03-13 21:35:09 +02001021 .recalc = &omap2_clksel_recalc,
1022};
1023
Paul Walmsley333943b2008-08-19 11:08:45 +03001024/* XXX What about neon_clkdm ? */
1025
Roman Tereshonkov3760d312008-03-13 21:35:09 +02001026/*
1027 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1028 * although it is referenced - so this is a guess
1029 */
1030static struct clk emu_mpu_alwon_ck = {
1031 .name = "emu_mpu_alwon_ck",
Russell King57137182008-11-04 16:48:35 +00001032 .ops = &clkops_null,
Roman Tereshonkov3760d312008-03-13 21:35:09 +02001033 .parent = &mpu_ck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +02001034 .recalc = &followparent_recalc,
1035};
1036
Paul Walmsleyb045d082008-03-18 11:24:28 +02001037static struct clk dpll2_fck = {
1038 .name = "dpll2_fck",
Russell King57137182008-11-04 16:48:35 +00001039 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001040 .parent = &core_ck,
1041 .init = &omap2_init_clksel_parent,
1042 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1043 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
Paul Walmsleyb8168d12009-01-28 12:08:14 -07001044 .clksel = div4_core_clksel,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001045 .recalc = &omap2_clksel_recalc,
1046};
1047
Roman Tereshonkov3760d312008-03-13 21:35:09 +02001048static struct clk iva2_ck = {
1049 .name = "iva2_ck",
Russell Kingb36ee722008-11-04 17:59:52 +00001050 .ops = &clkops_omap2_dflt_wait,
Roman Tereshonkov3760d312008-03-13 21:35:09 +02001051 .parent = &dpll2_m2_ck,
1052 .init = &omap2_init_clksel_parent,
Hiroshi DOYU31c203d2008-04-01 10:11:22 +03001053 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1054 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001055 .clkdm_name = "iva2_clkdm",
Russell Kingc0bf3132009-02-19 13:29:22 +00001056 .recalc = &followparent_recalc,
Roman Tereshonkov3760d312008-03-13 21:35:09 +02001057};
1058
Paul Walmsleyb045d082008-03-18 11:24:28 +02001059/* Common interface clocks */
1060
Paul Walmsleyb8168d12009-01-28 12:08:14 -07001061static const struct clksel div2_core_clksel[] = {
1062 { .parent = &core_ck, .rates = div2_rates },
1063 { .parent = NULL }
1064};
1065
Paul Walmsleyb045d082008-03-18 11:24:28 +02001066static struct clk l3_ick = {
1067 .name = "l3_ick",
Russell King57137182008-11-04 16:48:35 +00001068 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001069 .parent = &core_ck,
1070 .init = &omap2_init_clksel_parent,
1071 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1072 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1073 .clksel = div2_core_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03001074 .clkdm_name = "core_l3_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001075 .recalc = &omap2_clksel_recalc,
1076};
1077
1078static const struct clksel div2_l3_clksel[] = {
1079 { .parent = &l3_ick, .rates = div2_rates },
1080 { .parent = NULL }
1081};
1082
1083static struct clk l4_ick = {
1084 .name = "l4_ick",
Russell King57137182008-11-04 16:48:35 +00001085 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001086 .parent = &l3_ick,
1087 .init = &omap2_init_clksel_parent,
1088 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1089 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1090 .clksel = div2_l3_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03001091 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001092 .recalc = &omap2_clksel_recalc,
1093
1094};
1095
1096static const struct clksel div2_l4_clksel[] = {
1097 { .parent = &l4_ick, .rates = div2_rates },
1098 { .parent = NULL }
1099};
1100
1101static struct clk rm_ick = {
1102 .name = "rm_ick",
Russell King57137182008-11-04 16:48:35 +00001103 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001104 .parent = &l4_ick,
1105 .init = &omap2_init_clksel_parent,
1106 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1107 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1108 .clksel = div2_l4_clksel,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001109 .recalc = &omap2_clksel_recalc,
1110};
1111
1112/* GFX power domain */
1113
Roman Tereshonkov3760d312008-03-13 21:35:09 +02001114/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
Paul Walmsleyb045d082008-03-18 11:24:28 +02001115
1116static const struct clksel gfx_l3_clksel[] = {
1117 { .parent = &l3_ick, .rates = gfx_l3_rates },
1118 { .parent = NULL }
1119};
1120
Högander Jouni59559022008-08-19 11:08:45 +03001121/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1122static struct clk gfx_l3_ck = {
1123 .name = "gfx_l3_ck",
Russell Kingb36ee722008-11-04 17:59:52 +00001124 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001125 .parent = &l3_ick,
1126 .init = &omap2_init_clksel_parent,
1127 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1128 .enable_bit = OMAP_EN_GFX_SHIFT,
Högander Jouni59559022008-08-19 11:08:45 +03001129 .recalc = &followparent_recalc,
1130};
1131
1132static struct clk gfx_l3_fck = {
1133 .name = "gfx_l3_fck",
Russell King57137182008-11-04 16:48:35 +00001134 .ops = &clkops_null,
Högander Jouni59559022008-08-19 11:08:45 +03001135 .parent = &gfx_l3_ck,
1136 .init = &omap2_init_clksel_parent,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001137 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1138 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1139 .clksel = gfx_l3_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03001140 .clkdm_name = "gfx_3430es1_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001141 .recalc = &omap2_clksel_recalc,
1142};
1143
1144static struct clk gfx_l3_ick = {
1145 .name = "gfx_l3_ick",
Russell King57137182008-11-04 16:48:35 +00001146 .ops = &clkops_null,
Högander Jouni59559022008-08-19 11:08:45 +03001147 .parent = &gfx_l3_ck,
Paul Walmsley333943b2008-08-19 11:08:45 +03001148 .clkdm_name = "gfx_3430es1_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001149 .recalc = &followparent_recalc,
1150};
1151
1152static struct clk gfx_cg1_ck = {
1153 .name = "gfx_cg1_ck",
Russell Kingb36ee722008-11-04 17:59:52 +00001154 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001155 .parent = &gfx_l3_fck, /* REVISIT: correct? */
Paul Walmsley333943b2008-08-19 11:08:45 +03001156 .init = &omap2_init_clk_clkdm,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001157 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1158 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001159 .clkdm_name = "gfx_3430es1_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001160 .recalc = &followparent_recalc,
1161};
1162
1163static struct clk gfx_cg2_ck = {
1164 .name = "gfx_cg2_ck",
Russell Kingb36ee722008-11-04 17:59:52 +00001165 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001166 .parent = &gfx_l3_fck, /* REVISIT: correct? */
Paul Walmsley333943b2008-08-19 11:08:45 +03001167 .init = &omap2_init_clk_clkdm,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001168 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1169 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001170 .clkdm_name = "gfx_3430es1_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001171 .recalc = &followparent_recalc,
1172};
1173
1174/* SGX power domain - 3430ES2 only */
1175
1176static const struct clksel_rate sgx_core_rates[] = {
1177 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1178 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1179 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1180 { .div = 0 },
1181};
1182
1183static const struct clksel_rate sgx_96m_rates[] = {
1184 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1185 { .div = 0 },
1186};
1187
1188static const struct clksel sgx_clksel[] = {
1189 { .parent = &core_ck, .rates = sgx_core_rates },
1190 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1191 { .parent = NULL },
1192};
1193
1194static struct clk sgx_fck = {
1195 .name = "sgx_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001196 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001197 .init = &omap2_init_clksel_parent,
1198 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
Daniel Stone712d7c82009-01-27 19:13:05 -07001199 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001200 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1201 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1202 .clksel = sgx_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03001203 .clkdm_name = "sgx_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001204 .recalc = &omap2_clksel_recalc,
1205};
1206
1207static struct clk sgx_ick = {
1208 .name = "sgx_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001209 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001210 .parent = &l3_ick,
Paul Walmsley333943b2008-08-19 11:08:45 +03001211 .init = &omap2_init_clk_clkdm,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001212 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
Daniel Stone712d7c82009-01-27 19:13:05 -07001213 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001214 .clkdm_name = "sgx_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001215 .recalc = &followparent_recalc,
1216};
1217
1218/* CORE power domain */
1219
1220static struct clk d2d_26m_fck = {
1221 .name = "d2d_26m_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001222 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001223 .parent = &sys_ck,
Paul Walmsley333943b2008-08-19 11:08:45 +03001224 .init = &omap2_init_clk_clkdm,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001225 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1226 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001227 .clkdm_name = "d2d_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001228 .recalc = &followparent_recalc,
1229};
1230
1231static const struct clksel omap343x_gpt_clksel[] = {
1232 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1233 { .parent = &sys_ck, .rates = gpt_sys_rates },
1234 { .parent = NULL}
1235};
1236
1237static struct clk gpt10_fck = {
1238 .name = "gpt10_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001239 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001240 .parent = &sys_ck,
1241 .init = &omap2_init_clksel_parent,
1242 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1243 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1244 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1245 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1246 .clksel = omap343x_gpt_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03001247 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001248 .recalc = &omap2_clksel_recalc,
1249};
1250
1251static struct clk gpt11_fck = {
1252 .name = "gpt11_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001253 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001254 .parent = &sys_ck,
1255 .init = &omap2_init_clksel_parent,
1256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1257 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1258 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1259 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1260 .clksel = omap343x_gpt_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03001261 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001262 .recalc = &omap2_clksel_recalc,
1263};
1264
1265static struct clk cpefuse_fck = {
1266 .name = "cpefuse_fck",
Russell Kingc1168dc2008-11-04 21:24:00 +00001267 .ops = &clkops_omap2_dflt,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001268 .parent = &sys_ck,
1269 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1270 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001271 .recalc = &followparent_recalc,
1272};
1273
1274static struct clk ts_fck = {
1275 .name = "ts_fck",
Russell Kingc1168dc2008-11-04 21:24:00 +00001276 .ops = &clkops_omap2_dflt,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001277 .parent = &omap_32k_fck,
1278 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1279 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001280 .recalc = &followparent_recalc,
1281};
1282
1283static struct clk usbtll_fck = {
1284 .name = "usbtll_fck",
Russell Kingc1168dc2008-11-04 21:24:00 +00001285 .ops = &clkops_omap2_dflt,
Russell Kingc0bf3132009-02-19 13:29:22 +00001286 .parent = &dpll5_m2_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001287 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1288 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001289 .recalc = &followparent_recalc,
1290};
1291
1292/* CORE 96M FCLK-derived clocks */
1293
1294static struct clk core_96m_fck = {
1295 .name = "core_96m_fck",
Russell King57137182008-11-04 16:48:35 +00001296 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001297 .parent = &omap_96m_fck,
Paul Walmsley333943b2008-08-19 11:08:45 +03001298 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001299 .recalc = &followparent_recalc,
1300};
1301
1302static struct clk mmchs3_fck = {
1303 .name = "mmchs_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001304 .ops = &clkops_omap2_dflt_wait,
Tony Lindgrend8874662008-12-10 17:37:16 -08001305 .id = 2,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001306 .parent = &core_96m_fck,
1307 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1308 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001309 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001310 .recalc = &followparent_recalc,
1311};
1312
1313static struct clk mmchs2_fck = {
1314 .name = "mmchs_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001315 .ops = &clkops_omap2_dflt_wait,
Tony Lindgrend8874662008-12-10 17:37:16 -08001316 .id = 1,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001317 .parent = &core_96m_fck,
1318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1319 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001320 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001321 .recalc = &followparent_recalc,
1322};
1323
1324static struct clk mspro_fck = {
1325 .name = "mspro_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001326 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001327 .parent = &core_96m_fck,
1328 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1329 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001330 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001331 .recalc = &followparent_recalc,
1332};
1333
1334static struct clk mmchs1_fck = {
1335 .name = "mmchs_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001336 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001337 .parent = &core_96m_fck,
1338 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1339 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001340 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001341 .recalc = &followparent_recalc,
1342};
1343
1344static struct clk i2c3_fck = {
1345 .name = "i2c_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001346 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001347 .id = 3,
1348 .parent = &core_96m_fck,
1349 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1350 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001351 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001352 .recalc = &followparent_recalc,
1353};
1354
1355static struct clk i2c2_fck = {
1356 .name = "i2c_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001357 .ops = &clkops_omap2_dflt_wait,
Paul Walmsley333943b2008-08-19 11:08:45 +03001358 .id = 2,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001359 .parent = &core_96m_fck,
1360 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1361 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001362 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001363 .recalc = &followparent_recalc,
1364};
1365
1366static struct clk i2c1_fck = {
1367 .name = "i2c_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001368 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001369 .id = 1,
1370 .parent = &core_96m_fck,
1371 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1372 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001373 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001374 .recalc = &followparent_recalc,
1375};
1376
1377/*
1378 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1379 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1380 */
1381static const struct clksel_rate common_mcbsp_96m_rates[] = {
1382 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1383 { .div = 0 }
1384};
1385
1386static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1387 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1388 { .div = 0 }
1389};
1390
1391static const struct clksel mcbsp_15_clksel[] = {
1392 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1393 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1394 { .parent = NULL }
1395};
1396
1397static struct clk mcbsp5_fck = {
Eduardo Valentin78673bc2008-07-03 12:24:40 +03001398 .name = "mcbsp_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001399 .ops = &clkops_omap2_dflt_wait,
Eduardo Valentin78673bc2008-07-03 12:24:40 +03001400 .id = 5,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001401 .init = &omap2_init_clksel_parent,
1402 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1403 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1404 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1405 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1406 .clksel = mcbsp_15_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03001407 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001408 .recalc = &omap2_clksel_recalc,
1409};
1410
1411static struct clk mcbsp1_fck = {
Eduardo Valentin78673bc2008-07-03 12:24:40 +03001412 .name = "mcbsp_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001413 .ops = &clkops_omap2_dflt_wait,
Eduardo Valentin78673bc2008-07-03 12:24:40 +03001414 .id = 1,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001415 .init = &omap2_init_clksel_parent,
1416 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1417 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1418 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1419 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1420 .clksel = mcbsp_15_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03001421 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001422 .recalc = &omap2_clksel_recalc,
1423};
1424
1425/* CORE_48M_FCK-derived clocks */
1426
1427static struct clk core_48m_fck = {
1428 .name = "core_48m_fck",
Russell King57137182008-11-04 16:48:35 +00001429 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001430 .parent = &omap_48m_fck,
Paul Walmsley333943b2008-08-19 11:08:45 +03001431 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001432 .recalc = &followparent_recalc,
1433};
1434
1435static struct clk mcspi4_fck = {
1436 .name = "mcspi_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001437 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001438 .id = 4,
1439 .parent = &core_48m_fck,
1440 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1441 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001442 .recalc = &followparent_recalc,
1443};
1444
1445static struct clk mcspi3_fck = {
1446 .name = "mcspi_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001447 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001448 .id = 3,
1449 .parent = &core_48m_fck,
1450 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1451 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001452 .recalc = &followparent_recalc,
1453};
1454
1455static struct clk mcspi2_fck = {
1456 .name = "mcspi_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001457 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001458 .id = 2,
1459 .parent = &core_48m_fck,
1460 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1461 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001462 .recalc = &followparent_recalc,
1463};
1464
1465static struct clk mcspi1_fck = {
1466 .name = "mcspi_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001467 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001468 .id = 1,
1469 .parent = &core_48m_fck,
1470 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1471 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001472 .recalc = &followparent_recalc,
1473};
1474
1475static struct clk uart2_fck = {
1476 .name = "uart2_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001477 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001478 .parent = &core_48m_fck,
1479 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1480 .enable_bit = OMAP3430_EN_UART2_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001481 .recalc = &followparent_recalc,
1482};
1483
1484static struct clk uart1_fck = {
1485 .name = "uart1_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001486 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001487 .parent = &core_48m_fck,
1488 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1489 .enable_bit = OMAP3430_EN_UART1_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001490 .recalc = &followparent_recalc,
1491};
1492
1493static struct clk fshostusb_fck = {
1494 .name = "fshostusb_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001495 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001496 .parent = &core_48m_fck,
1497 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1498 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001499 .recalc = &followparent_recalc,
1500};
1501
1502/* CORE_12M_FCK based clocks */
1503
1504static struct clk core_12m_fck = {
1505 .name = "core_12m_fck",
Russell King57137182008-11-04 16:48:35 +00001506 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001507 .parent = &omap_12m_fck,
Paul Walmsley333943b2008-08-19 11:08:45 +03001508 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001509 .recalc = &followparent_recalc,
1510};
1511
1512static struct clk hdq_fck = {
1513 .name = "hdq_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001514 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001515 .parent = &core_12m_fck,
1516 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1517 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001518 .recalc = &followparent_recalc,
1519};
1520
1521/* DPLL3-derived clock */
1522
1523static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1524 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1525 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1526 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1527 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1528 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1529 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1530 { .div = 0 }
1531};
1532
1533static const struct clksel ssi_ssr_clksel[] = {
1534 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1535 { .parent = NULL }
1536};
1537
1538static struct clk ssi_ssr_fck = {
1539 .name = "ssi_ssr_fck",
Russell Kingbc51da42008-11-04 18:59:32 +00001540 .ops = &clkops_omap2_dflt,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001541 .init = &omap2_init_clksel_parent,
1542 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1543 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1544 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1545 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1546 .clksel = ssi_ssr_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03001547 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001548 .recalc = &omap2_clksel_recalc,
1549};
1550
1551static struct clk ssi_sst_fck = {
1552 .name = "ssi_sst_fck",
Russell King57137182008-11-04 16:48:35 +00001553 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001554 .parent = &ssi_ssr_fck,
1555 .fixed_div = 2,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001556 .recalc = &omap2_fixed_divisor_recalc,
1557};
1558
1559
1560
1561/* CORE_L3_ICK based clocks */
1562
Paul Walmsley333943b2008-08-19 11:08:45 +03001563/*
1564 * XXX must add clk_enable/clk_disable for these if standard code won't
1565 * handle it
1566 */
Paul Walmsleyb045d082008-03-18 11:24:28 +02001567static struct clk core_l3_ick = {
1568 .name = "core_l3_ick",
Russell King57137182008-11-04 16:48:35 +00001569 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001570 .parent = &l3_ick,
Paul Walmsley333943b2008-08-19 11:08:45 +03001571 .init = &omap2_init_clk_clkdm,
Paul Walmsley333943b2008-08-19 11:08:45 +03001572 .clkdm_name = "core_l3_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001573 .recalc = &followparent_recalc,
1574};
1575
1576static struct clk hsotgusb_ick = {
1577 .name = "hsotgusb_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001578 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001579 .parent = &core_l3_ick,
1580 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1581 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001582 .clkdm_name = "core_l3_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001583 .recalc = &followparent_recalc,
1584};
1585
1586static struct clk sdrc_ick = {
1587 .name = "sdrc_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001588 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001589 .parent = &core_l3_ick,
1590 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1591 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
Russell King44dc9d02009-01-19 15:51:11 +00001592 .flags = ENABLE_ON_INIT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001593 .clkdm_name = "core_l3_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001594 .recalc = &followparent_recalc,
1595};
1596
1597static struct clk gpmc_fck = {
1598 .name = "gpmc_fck",
Russell King57137182008-11-04 16:48:35 +00001599 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001600 .parent = &core_l3_ick,
Russell King44dc9d02009-01-19 15:51:11 +00001601 .flags = ENABLE_ON_INIT, /* huh? */
Paul Walmsley333943b2008-08-19 11:08:45 +03001602 .clkdm_name = "core_l3_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001603 .recalc = &followparent_recalc,
1604};
1605
1606/* SECURITY_L3_ICK based clocks */
1607
1608static struct clk security_l3_ick = {
1609 .name = "security_l3_ick",
Russell King57137182008-11-04 16:48:35 +00001610 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001611 .parent = &l3_ick,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001612 .recalc = &followparent_recalc,
1613};
1614
1615static struct clk pka_ick = {
1616 .name = "pka_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001617 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001618 .parent = &security_l3_ick,
1619 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1620 .enable_bit = OMAP3430_EN_PKA_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001621 .recalc = &followparent_recalc,
1622};
1623
1624/* CORE_L4_ICK based clocks */
1625
1626static struct clk core_l4_ick = {
1627 .name = "core_l4_ick",
Russell King57137182008-11-04 16:48:35 +00001628 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001629 .parent = &l4_ick,
Paul Walmsley333943b2008-08-19 11:08:45 +03001630 .init = &omap2_init_clk_clkdm,
Paul Walmsley333943b2008-08-19 11:08:45 +03001631 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001632 .recalc = &followparent_recalc,
1633};
1634
1635static struct clk usbtll_ick = {
1636 .name = "usbtll_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001637 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001638 .parent = &core_l4_ick,
1639 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1640 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001641 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001642 .recalc = &followparent_recalc,
1643};
1644
1645static struct clk mmchs3_ick = {
1646 .name = "mmchs_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001647 .ops = &clkops_omap2_dflt_wait,
Tony Lindgrend8874662008-12-10 17:37:16 -08001648 .id = 2,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001649 .parent = &core_l4_ick,
1650 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1651 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001652 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001653 .recalc = &followparent_recalc,
1654};
1655
1656/* Intersystem Communication Registers - chassis mode only */
1657static struct clk icr_ick = {
1658 .name = "icr_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001659 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001660 .parent = &core_l4_ick,
1661 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1662 .enable_bit = OMAP3430_EN_ICR_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001663 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001664 .recalc = &followparent_recalc,
1665};
1666
1667static struct clk aes2_ick = {
1668 .name = "aes2_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001669 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001670 .parent = &core_l4_ick,
1671 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1672 .enable_bit = OMAP3430_EN_AES2_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001673 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001674 .recalc = &followparent_recalc,
1675};
1676
1677static struct clk sha12_ick = {
1678 .name = "sha12_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001679 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001680 .parent = &core_l4_ick,
1681 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1682 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001683 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001684 .recalc = &followparent_recalc,
1685};
1686
1687static struct clk des2_ick = {
1688 .name = "des2_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001689 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001690 .parent = &core_l4_ick,
1691 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1692 .enable_bit = OMAP3430_EN_DES2_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001693 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001694 .recalc = &followparent_recalc,
1695};
1696
1697static struct clk mmchs2_ick = {
1698 .name = "mmchs_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001699 .ops = &clkops_omap2_dflt_wait,
Tony Lindgrend8874662008-12-10 17:37:16 -08001700 .id = 1,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001701 .parent = &core_l4_ick,
1702 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1703 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001704 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001705 .recalc = &followparent_recalc,
1706};
1707
1708static struct clk mmchs1_ick = {
1709 .name = "mmchs_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001710 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001711 .parent = &core_l4_ick,
1712 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1713 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001714 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001715 .recalc = &followparent_recalc,
1716};
1717
1718static struct clk mspro_ick = {
1719 .name = "mspro_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001720 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001721 .parent = &core_l4_ick,
1722 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1723 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001724 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001725 .recalc = &followparent_recalc,
1726};
1727
1728static struct clk hdq_ick = {
1729 .name = "hdq_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001730 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001731 .parent = &core_l4_ick,
1732 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1733 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001734 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001735 .recalc = &followparent_recalc,
1736};
1737
1738static struct clk mcspi4_ick = {
1739 .name = "mcspi_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001740 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001741 .id = 4,
1742 .parent = &core_l4_ick,
1743 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1744 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001745 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001746 .recalc = &followparent_recalc,
1747};
1748
1749static struct clk mcspi3_ick = {
1750 .name = "mcspi_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001751 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001752 .id = 3,
1753 .parent = &core_l4_ick,
1754 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1755 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001756 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001757 .recalc = &followparent_recalc,
1758};
1759
1760static struct clk mcspi2_ick = {
1761 .name = "mcspi_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001762 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001763 .id = 2,
1764 .parent = &core_l4_ick,
1765 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1766 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001767 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001768 .recalc = &followparent_recalc,
1769};
1770
1771static struct clk mcspi1_ick = {
1772 .name = "mcspi_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001773 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001774 .id = 1,
1775 .parent = &core_l4_ick,
1776 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1777 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001778 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001779 .recalc = &followparent_recalc,
1780};
1781
1782static struct clk i2c3_ick = {
1783 .name = "i2c_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001784 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001785 .id = 3,
1786 .parent = &core_l4_ick,
1787 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1788 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001789 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001790 .recalc = &followparent_recalc,
1791};
1792
1793static struct clk i2c2_ick = {
1794 .name = "i2c_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001795 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001796 .id = 2,
1797 .parent = &core_l4_ick,
1798 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1799 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001800 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001801 .recalc = &followparent_recalc,
1802};
1803
1804static struct clk i2c1_ick = {
1805 .name = "i2c_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001806 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001807 .id = 1,
1808 .parent = &core_l4_ick,
1809 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1810 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001811 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001812 .recalc = &followparent_recalc,
1813};
1814
1815static struct clk uart2_ick = {
1816 .name = "uart2_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001817 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001818 .parent = &core_l4_ick,
1819 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1820 .enable_bit = OMAP3430_EN_UART2_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001821 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001822 .recalc = &followparent_recalc,
1823};
1824
1825static struct clk uart1_ick = {
1826 .name = "uart1_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001827 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001828 .parent = &core_l4_ick,
1829 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1830 .enable_bit = OMAP3430_EN_UART1_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001831 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001832 .recalc = &followparent_recalc,
1833};
1834
1835static struct clk gpt11_ick = {
1836 .name = "gpt11_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001837 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001838 .parent = &core_l4_ick,
1839 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1840 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001841 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001842 .recalc = &followparent_recalc,
1843};
1844
1845static struct clk gpt10_ick = {
1846 .name = "gpt10_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001847 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001848 .parent = &core_l4_ick,
1849 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1850 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001851 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001852 .recalc = &followparent_recalc,
1853};
1854
1855static struct clk mcbsp5_ick = {
Eduardo Valentin78673bc2008-07-03 12:24:40 +03001856 .name = "mcbsp_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001857 .ops = &clkops_omap2_dflt_wait,
Eduardo Valentin78673bc2008-07-03 12:24:40 +03001858 .id = 5,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001859 .parent = &core_l4_ick,
1860 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1861 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001862 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001863 .recalc = &followparent_recalc,
1864};
1865
1866static struct clk mcbsp1_ick = {
Eduardo Valentin78673bc2008-07-03 12:24:40 +03001867 .name = "mcbsp_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001868 .ops = &clkops_omap2_dflt_wait,
Eduardo Valentin78673bc2008-07-03 12:24:40 +03001869 .id = 1,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001870 .parent = &core_l4_ick,
1871 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1872 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001873 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001874 .recalc = &followparent_recalc,
1875};
1876
1877static struct clk fac_ick = {
1878 .name = "fac_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001879 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001880 .parent = &core_l4_ick,
1881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1882 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001883 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001884 .recalc = &followparent_recalc,
1885};
1886
1887static struct clk mailboxes_ick = {
1888 .name = "mailboxes_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001889 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001890 .parent = &core_l4_ick,
1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1892 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001893 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001894 .recalc = &followparent_recalc,
1895};
1896
1897static struct clk omapctrl_ick = {
1898 .name = "omapctrl_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001899 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001900 .parent = &core_l4_ick,
1901 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1902 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
Russell King44dc9d02009-01-19 15:51:11 +00001903 .flags = ENABLE_ON_INIT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001904 .recalc = &followparent_recalc,
1905};
1906
1907/* SSI_L4_ICK based clocks */
1908
1909static struct clk ssi_l4_ick = {
1910 .name = "ssi_l4_ick",
Russell King57137182008-11-04 16:48:35 +00001911 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001912 .parent = &l4_ick,
Paul Walmsley333943b2008-08-19 11:08:45 +03001913 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001914 .recalc = &followparent_recalc,
1915};
1916
1917static struct clk ssi_ick = {
1918 .name = "ssi_ick",
Russell Kingbc51da42008-11-04 18:59:32 +00001919 .ops = &clkops_omap2_dflt,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001920 .parent = &ssi_l4_ick,
1921 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1922 .enable_bit = OMAP3430_EN_SSI_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03001923 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02001924 .recalc = &followparent_recalc,
1925};
1926
1927/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1928 * but l4_ick makes more sense to me */
1929
1930static const struct clksel usb_l4_clksel[] = {
1931 { .parent = &l4_ick, .rates = div2_rates },
1932 { .parent = NULL },
1933};
1934
1935static struct clk usb_l4_ick = {
1936 .name = "usb_l4_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001937 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001938 .parent = &l4_ick,
1939 .init = &omap2_init_clksel_parent,
1940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1941 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1942 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1943 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
1944 .clksel = usb_l4_clksel,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001945 .recalc = &omap2_clksel_recalc,
1946};
1947
1948/* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
1949
1950/* SECURITY_L4_ICK2 based clocks */
1951
1952static struct clk security_l4_ick2 = {
1953 .name = "security_l4_ick2",
Russell King57137182008-11-04 16:48:35 +00001954 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001955 .parent = &l4_ick,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001956 .recalc = &followparent_recalc,
1957};
1958
1959static struct clk aes1_ick = {
1960 .name = "aes1_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001961 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001962 .parent = &security_l4_ick2,
1963 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1964 .enable_bit = OMAP3430_EN_AES1_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001965 .recalc = &followparent_recalc,
1966};
1967
1968static struct clk rng_ick = {
1969 .name = "rng_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001970 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001971 .parent = &security_l4_ick2,
1972 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1973 .enable_bit = OMAP3430_EN_RNG_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001974 .recalc = &followparent_recalc,
1975};
1976
1977static struct clk sha11_ick = {
1978 .name = "sha11_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001979 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001980 .parent = &security_l4_ick2,
1981 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1982 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001983 .recalc = &followparent_recalc,
1984};
1985
1986static struct clk des1_ick = {
1987 .name = "des1_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00001988 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001989 .parent = &security_l4_ick2,
1990 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1991 .enable_bit = OMAP3430_EN_DES1_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001992 .recalc = &followparent_recalc,
1993};
1994
1995/* DSS */
Paul Walmsleyb045d082008-03-18 11:24:28 +02001996static struct clk dss1_alwon_fck = {
1997 .name = "dss1_alwon_fck",
Russell Kingbc51da42008-11-04 18:59:32 +00001998 .ops = &clkops_omap2_dflt,
Paul Walmsleyb045d082008-03-18 11:24:28 +02001999 .parent = &dpll4_m4x2_ck,
2000 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2001 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002002 .clkdm_name = "dss_clkdm",
Russell Kingc0bf3132009-02-19 13:29:22 +00002003 .recalc = &followparent_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002004};
2005
2006static struct clk dss_tv_fck = {
2007 .name = "dss_tv_fck",
Russell Kingbc51da42008-11-04 18:59:32 +00002008 .ops = &clkops_omap2_dflt,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002009 .parent = &omap_54m_fck,
Paul Walmsley333943b2008-08-19 11:08:45 +03002010 .init = &omap2_init_clk_clkdm,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002011 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2012 .enable_bit = OMAP3430_EN_TV_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002013 .clkdm_name = "dss_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002014 .recalc = &followparent_recalc,
2015};
2016
2017static struct clk dss_96m_fck = {
2018 .name = "dss_96m_fck",
Russell Kingbc51da42008-11-04 18:59:32 +00002019 .ops = &clkops_omap2_dflt,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002020 .parent = &omap_96m_fck,
Paul Walmsley333943b2008-08-19 11:08:45 +03002021 .init = &omap2_init_clk_clkdm,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002022 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2023 .enable_bit = OMAP3430_EN_TV_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002024 .clkdm_name = "dss_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002025 .recalc = &followparent_recalc,
2026};
2027
2028static struct clk dss2_alwon_fck = {
2029 .name = "dss2_alwon_fck",
Russell Kingbc51da42008-11-04 18:59:32 +00002030 .ops = &clkops_omap2_dflt,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002031 .parent = &sys_ck,
Paul Walmsley333943b2008-08-19 11:08:45 +03002032 .init = &omap2_init_clk_clkdm,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002033 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2034 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002035 .clkdm_name = "dss_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002036 .recalc = &followparent_recalc,
2037};
2038
2039static struct clk dss_ick = {
2040 /* Handles both L3 and L4 clocks */
2041 .name = "dss_ick",
Russell Kingbc51da42008-11-04 18:59:32 +00002042 .ops = &clkops_omap2_dflt,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002043 .parent = &l4_ick,
Paul Walmsley333943b2008-08-19 11:08:45 +03002044 .init = &omap2_init_clk_clkdm,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002045 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2046 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002047 .clkdm_name = "dss_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002048 .recalc = &followparent_recalc,
2049};
2050
2051/* CAM */
2052
2053static struct clk cam_mclk = {
2054 .name = "cam_mclk",
Sergio Aguirre9e53dd72009-04-23 21:11:07 -06002055 .ops = &clkops_omap2_dflt,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002056 .parent = &dpll4_m5x2_ck,
2057 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2058 .enable_bit = OMAP3430_EN_CAM_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002059 .clkdm_name = "cam_clkdm",
Russell Kingc0bf3132009-02-19 13:29:22 +00002060 .recalc = &followparent_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002061};
2062
Högander Jouni59559022008-08-19 11:08:45 +03002063static struct clk cam_ick = {
2064 /* Handles both L3 and L4 clocks */
2065 .name = "cam_ick",
Sergio Aguirre9e53dd72009-04-23 21:11:07 -06002066 .ops = &clkops_omap2_dflt,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002067 .parent = &l4_ick,
Paul Walmsley333943b2008-08-19 11:08:45 +03002068 .init = &omap2_init_clk_clkdm,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002069 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2070 .enable_bit = OMAP3430_EN_CAM_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002071 .clkdm_name = "cam_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002072 .recalc = &followparent_recalc,
2073};
2074
Sergio Aguirre6c8fe0b2009-01-27 19:13:09 -07002075static struct clk csi2_96m_fck = {
2076 .name = "csi2_96m_fck",
Sergio Aguirre9e53dd72009-04-23 21:11:07 -06002077 .ops = &clkops_omap2_dflt,
Sergio Aguirre6c8fe0b2009-01-27 19:13:09 -07002078 .parent = &core_96m_fck,
2079 .init = &omap2_init_clk_clkdm,
2080 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2081 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2082 .clkdm_name = "cam_clkdm",
2083 .recalc = &followparent_recalc,
2084};
2085
Paul Walmsleyb045d082008-03-18 11:24:28 +02002086/* USBHOST - 3430ES2 only */
2087
2088static struct clk usbhost_120m_fck = {
2089 .name = "usbhost_120m_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002090 .ops = &clkops_omap2_dflt_wait,
Russell Kingc0bf3132009-02-19 13:29:22 +00002091 .parent = &dpll5_m2_ck,
Paul Walmsley333943b2008-08-19 11:08:45 +03002092 .init = &omap2_init_clk_clkdm,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002093 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2094 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002095 .clkdm_name = "usbhost_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002096 .recalc = &followparent_recalc,
2097};
2098
2099static struct clk usbhost_48m_fck = {
2100 .name = "usbhost_48m_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002101 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002102 .parent = &omap_48m_fck,
Paul Walmsley333943b2008-08-19 11:08:45 +03002103 .init = &omap2_init_clk_clkdm,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002104 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2105 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002106 .clkdm_name = "usbhost_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002107 .recalc = &followparent_recalc,
2108};
2109
Högander Jouni59559022008-08-19 11:08:45 +03002110static struct clk usbhost_ick = {
2111 /* Handles both L3 and L4 clocks */
2112 .name = "usbhost_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002113 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002114 .parent = &l4_ick,
Paul Walmsley333943b2008-08-19 11:08:45 +03002115 .init = &omap2_init_clk_clkdm,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002116 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2117 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002118 .clkdm_name = "usbhost_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002119 .recalc = &followparent_recalc,
2120};
2121
Paul Walmsleyb045d082008-03-18 11:24:28 +02002122/* WKUP */
2123
2124static const struct clksel_rate usim_96m_rates[] = {
2125 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2126 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2127 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2128 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2129 { .div = 0 },
2130};
2131
2132static const struct clksel_rate usim_120m_rates[] = {
2133 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2134 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2135 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2136 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2137 { .div = 0 },
2138};
2139
2140static const struct clksel usim_clksel[] = {
2141 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
Russell Kingc0bf3132009-02-19 13:29:22 +00002142 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
Paul Walmsleyb045d082008-03-18 11:24:28 +02002143 { .parent = &sys_ck, .rates = div2_rates },
2144 { .parent = NULL },
2145};
2146
2147/* 3430ES2 only */
2148static struct clk usim_fck = {
2149 .name = "usim_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002150 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002151 .init = &omap2_init_clksel_parent,
2152 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2153 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2154 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2155 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2156 .clksel = usim_clksel,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002157 .recalc = &omap2_clksel_recalc,
2158};
2159
Paul Walmsley333943b2008-08-19 11:08:45 +03002160/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
Paul Walmsleyb045d082008-03-18 11:24:28 +02002161static struct clk gpt1_fck = {
2162 .name = "gpt1_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002163 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002164 .init = &omap2_init_clksel_parent,
2165 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2166 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2167 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2168 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2169 .clksel = omap343x_gpt_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002170 .clkdm_name = "wkup_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002171 .recalc = &omap2_clksel_recalc,
2172};
2173
2174static struct clk wkup_32k_fck = {
2175 .name = "wkup_32k_fck",
Russell King897dcde2008-11-04 16:35:03 +00002176 .ops = &clkops_null,
Paul Walmsley333943b2008-08-19 11:08:45 +03002177 .init = &omap2_init_clk_clkdm,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002178 .parent = &omap_32k_fck,
Paul Walmsley333943b2008-08-19 11:08:45 +03002179 .clkdm_name = "wkup_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002180 .recalc = &followparent_recalc,
2181};
2182
Jouni Hogander89db9482008-12-10 17:35:24 -08002183static struct clk gpio1_dbck = {
2184 .name = "gpio1_dbck",
Russell Kingb36ee722008-11-04 17:59:52 +00002185 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002186 .parent = &wkup_32k_fck,
2187 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2188 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002189 .clkdm_name = "wkup_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002190 .recalc = &followparent_recalc,
2191};
2192
2193static struct clk wdt2_fck = {
2194 .name = "wdt2_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002195 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002196 .parent = &wkup_32k_fck,
2197 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2198 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002199 .clkdm_name = "wkup_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002200 .recalc = &followparent_recalc,
2201};
2202
2203static struct clk wkup_l4_ick = {
2204 .name = "wkup_l4_ick",
Russell King897dcde2008-11-04 16:35:03 +00002205 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002206 .parent = &sys_ck,
Paul Walmsley333943b2008-08-19 11:08:45 +03002207 .clkdm_name = "wkup_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002208 .recalc = &followparent_recalc,
2209};
2210
2211/* 3430ES2 only */
2212/* Never specifically named in the TRM, so we have to infer a likely name */
2213static struct clk usim_ick = {
2214 .name = "usim_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002215 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002216 .parent = &wkup_l4_ick,
2217 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2218 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002219 .clkdm_name = "wkup_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002220 .recalc = &followparent_recalc,
2221};
2222
2223static struct clk wdt2_ick = {
2224 .name = "wdt2_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002225 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002226 .parent = &wkup_l4_ick,
2227 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2228 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002229 .clkdm_name = "wkup_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002230 .recalc = &followparent_recalc,
2231};
2232
2233static struct clk wdt1_ick = {
2234 .name = "wdt1_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002235 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002236 .parent = &wkup_l4_ick,
2237 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2238 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002239 .clkdm_name = "wkup_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002240 .recalc = &followparent_recalc,
2241};
2242
2243static struct clk gpio1_ick = {
2244 .name = "gpio1_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002245 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002246 .parent = &wkup_l4_ick,
2247 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2248 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002249 .clkdm_name = "wkup_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002250 .recalc = &followparent_recalc,
2251};
2252
2253static struct clk omap_32ksync_ick = {
2254 .name = "omap_32ksync_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002255 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002256 .parent = &wkup_l4_ick,
2257 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2258 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002259 .clkdm_name = "wkup_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002260 .recalc = &followparent_recalc,
2261};
2262
Paul Walmsley333943b2008-08-19 11:08:45 +03002263/* XXX This clock no longer exists in 3430 TRM rev F */
Paul Walmsleyb045d082008-03-18 11:24:28 +02002264static struct clk gpt12_ick = {
2265 .name = "gpt12_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002266 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002267 .parent = &wkup_l4_ick,
2268 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2269 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002270 .clkdm_name = "wkup_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002271 .recalc = &followparent_recalc,
2272};
2273
2274static struct clk gpt1_ick = {
2275 .name = "gpt1_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002276 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002277 .parent = &wkup_l4_ick,
2278 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2279 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002280 .clkdm_name = "wkup_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002281 .recalc = &followparent_recalc,
2282};
2283
2284
2285
2286/* PER clock domain */
2287
2288static struct clk per_96m_fck = {
2289 .name = "per_96m_fck",
Russell King57137182008-11-04 16:48:35 +00002290 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002291 .parent = &omap_96m_alwon_fck,
Paul Walmsley333943b2008-08-19 11:08:45 +03002292 .init = &omap2_init_clk_clkdm,
Paul Walmsley333943b2008-08-19 11:08:45 +03002293 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002294 .recalc = &followparent_recalc,
2295};
2296
2297static struct clk per_48m_fck = {
2298 .name = "per_48m_fck",
Russell King57137182008-11-04 16:48:35 +00002299 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002300 .parent = &omap_48m_fck,
Paul Walmsley333943b2008-08-19 11:08:45 +03002301 .init = &omap2_init_clk_clkdm,
Paul Walmsley333943b2008-08-19 11:08:45 +03002302 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002303 .recalc = &followparent_recalc,
2304};
2305
2306static struct clk uart3_fck = {
2307 .name = "uart3_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002308 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002309 .parent = &per_48m_fck,
2310 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2311 .enable_bit = OMAP3430_EN_UART3_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002312 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002313 .recalc = &followparent_recalc,
2314};
2315
2316static struct clk gpt2_fck = {
2317 .name = "gpt2_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002318 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002319 .init = &omap2_init_clksel_parent,
2320 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2321 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2322 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2323 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2324 .clksel = omap343x_gpt_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002325 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002326 .recalc = &omap2_clksel_recalc,
2327};
2328
2329static struct clk gpt3_fck = {
2330 .name = "gpt3_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002331 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002332 .init = &omap2_init_clksel_parent,
2333 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2334 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2335 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2336 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2337 .clksel = omap343x_gpt_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002338 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002339 .recalc = &omap2_clksel_recalc,
2340};
2341
2342static struct clk gpt4_fck = {
2343 .name = "gpt4_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002344 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002345 .init = &omap2_init_clksel_parent,
2346 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2347 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2348 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2349 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2350 .clksel = omap343x_gpt_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002351 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002352 .recalc = &omap2_clksel_recalc,
2353};
2354
2355static struct clk gpt5_fck = {
2356 .name = "gpt5_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002357 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002358 .init = &omap2_init_clksel_parent,
2359 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2360 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2361 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2362 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2363 .clksel = omap343x_gpt_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002364 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002365 .recalc = &omap2_clksel_recalc,
2366};
2367
2368static struct clk gpt6_fck = {
2369 .name = "gpt6_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002370 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002371 .init = &omap2_init_clksel_parent,
2372 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2373 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2374 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2375 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2376 .clksel = omap343x_gpt_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002377 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002378 .recalc = &omap2_clksel_recalc,
2379};
2380
2381static struct clk gpt7_fck = {
2382 .name = "gpt7_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002383 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002384 .init = &omap2_init_clksel_parent,
2385 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2386 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2387 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2388 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2389 .clksel = omap343x_gpt_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002390 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002391 .recalc = &omap2_clksel_recalc,
2392};
2393
2394static struct clk gpt8_fck = {
2395 .name = "gpt8_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002396 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002397 .init = &omap2_init_clksel_parent,
2398 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2399 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2400 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2401 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2402 .clksel = omap343x_gpt_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002403 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002404 .recalc = &omap2_clksel_recalc,
2405};
2406
2407static struct clk gpt9_fck = {
2408 .name = "gpt9_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002409 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002410 .init = &omap2_init_clksel_parent,
2411 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2412 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2413 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2414 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2415 .clksel = omap343x_gpt_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002416 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002417 .recalc = &omap2_clksel_recalc,
2418};
2419
2420static struct clk per_32k_alwon_fck = {
2421 .name = "per_32k_alwon_fck",
Russell King897dcde2008-11-04 16:35:03 +00002422 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002423 .parent = &omap_32k_fck,
Paul Walmsley333943b2008-08-19 11:08:45 +03002424 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002425 .recalc = &followparent_recalc,
2426};
2427
Jouni Hogander89db9482008-12-10 17:35:24 -08002428static struct clk gpio6_dbck = {
2429 .name = "gpio6_dbck",
Russell Kingb36ee722008-11-04 17:59:52 +00002430 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002431 .parent = &per_32k_alwon_fck,
2432 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
Jouni Höganderc3aa044a2008-03-28 14:57:50 +02002433 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002434 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002435 .recalc = &followparent_recalc,
2436};
2437
Jouni Hogander89db9482008-12-10 17:35:24 -08002438static struct clk gpio5_dbck = {
2439 .name = "gpio5_dbck",
Russell Kingb36ee722008-11-04 17:59:52 +00002440 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002441 .parent = &per_32k_alwon_fck,
2442 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
Jouni Höganderc3aa044a2008-03-28 14:57:50 +02002443 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002444 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002445 .recalc = &followparent_recalc,
2446};
2447
Jouni Hogander89db9482008-12-10 17:35:24 -08002448static struct clk gpio4_dbck = {
2449 .name = "gpio4_dbck",
Russell Kingb36ee722008-11-04 17:59:52 +00002450 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002451 .parent = &per_32k_alwon_fck,
2452 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
Jouni Höganderc3aa044a2008-03-28 14:57:50 +02002453 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002454 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002455 .recalc = &followparent_recalc,
2456};
2457
Jouni Hogander89db9482008-12-10 17:35:24 -08002458static struct clk gpio3_dbck = {
2459 .name = "gpio3_dbck",
Russell Kingb36ee722008-11-04 17:59:52 +00002460 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002461 .parent = &per_32k_alwon_fck,
2462 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
Jouni Höganderc3aa044a2008-03-28 14:57:50 +02002463 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002464 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002465 .recalc = &followparent_recalc,
2466};
2467
Jouni Hogander89db9482008-12-10 17:35:24 -08002468static struct clk gpio2_dbck = {
2469 .name = "gpio2_dbck",
Russell Kingb36ee722008-11-04 17:59:52 +00002470 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002471 .parent = &per_32k_alwon_fck,
2472 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
Jouni Höganderc3aa044a2008-03-28 14:57:50 +02002473 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002474 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002475 .recalc = &followparent_recalc,
2476};
2477
2478static struct clk wdt3_fck = {
2479 .name = "wdt3_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002480 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002481 .parent = &per_32k_alwon_fck,
2482 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2483 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002484 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002485 .recalc = &followparent_recalc,
2486};
2487
2488static struct clk per_l4_ick = {
2489 .name = "per_l4_ick",
Russell King57137182008-11-04 16:48:35 +00002490 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002491 .parent = &l4_ick,
Paul Walmsley333943b2008-08-19 11:08:45 +03002492 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002493 .recalc = &followparent_recalc,
2494};
2495
2496static struct clk gpio6_ick = {
2497 .name = "gpio6_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002498 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002499 .parent = &per_l4_ick,
2500 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2501 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002502 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002503 .recalc = &followparent_recalc,
2504};
2505
2506static struct clk gpio5_ick = {
2507 .name = "gpio5_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002508 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002509 .parent = &per_l4_ick,
2510 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2511 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002512 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002513 .recalc = &followparent_recalc,
2514};
2515
2516static struct clk gpio4_ick = {
2517 .name = "gpio4_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002518 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002519 .parent = &per_l4_ick,
2520 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2521 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002522 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002523 .recalc = &followparent_recalc,
2524};
2525
2526static struct clk gpio3_ick = {
2527 .name = "gpio3_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002528 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002529 .parent = &per_l4_ick,
2530 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2531 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002532 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002533 .recalc = &followparent_recalc,
2534};
2535
2536static struct clk gpio2_ick = {
2537 .name = "gpio2_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002538 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002539 .parent = &per_l4_ick,
2540 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2541 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002542 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002543 .recalc = &followparent_recalc,
2544};
2545
2546static struct clk wdt3_ick = {
2547 .name = "wdt3_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002548 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002549 .parent = &per_l4_ick,
2550 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2551 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002552 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002553 .recalc = &followparent_recalc,
2554};
2555
2556static struct clk uart3_ick = {
2557 .name = "uart3_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002558 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002559 .parent = &per_l4_ick,
2560 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2561 .enable_bit = OMAP3430_EN_UART3_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002562 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002563 .recalc = &followparent_recalc,
2564};
2565
2566static struct clk gpt9_ick = {
2567 .name = "gpt9_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002568 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002569 .parent = &per_l4_ick,
2570 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2571 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002572 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002573 .recalc = &followparent_recalc,
2574};
2575
2576static struct clk gpt8_ick = {
2577 .name = "gpt8_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002578 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002579 .parent = &per_l4_ick,
2580 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2581 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002582 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002583 .recalc = &followparent_recalc,
2584};
2585
2586static struct clk gpt7_ick = {
2587 .name = "gpt7_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002588 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002589 .parent = &per_l4_ick,
2590 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2591 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002592 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002593 .recalc = &followparent_recalc,
2594};
2595
2596static struct clk gpt6_ick = {
2597 .name = "gpt6_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002598 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002599 .parent = &per_l4_ick,
2600 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2601 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002602 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002603 .recalc = &followparent_recalc,
2604};
2605
2606static struct clk gpt5_ick = {
2607 .name = "gpt5_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002608 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002609 .parent = &per_l4_ick,
2610 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2611 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002612 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002613 .recalc = &followparent_recalc,
2614};
2615
2616static struct clk gpt4_ick = {
2617 .name = "gpt4_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002618 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002619 .parent = &per_l4_ick,
2620 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2621 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002622 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002623 .recalc = &followparent_recalc,
2624};
2625
2626static struct clk gpt3_ick = {
2627 .name = "gpt3_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002628 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002629 .parent = &per_l4_ick,
2630 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2631 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002632 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002633 .recalc = &followparent_recalc,
2634};
2635
2636static struct clk gpt2_ick = {
2637 .name = "gpt2_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002638 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002639 .parent = &per_l4_ick,
2640 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2641 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002642 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002643 .recalc = &followparent_recalc,
2644};
2645
2646static struct clk mcbsp2_ick = {
Eduardo Valentin78673bc2008-07-03 12:24:40 +03002647 .name = "mcbsp_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002648 .ops = &clkops_omap2_dflt_wait,
Eduardo Valentin78673bc2008-07-03 12:24:40 +03002649 .id = 2,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002650 .parent = &per_l4_ick,
2651 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2652 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002653 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002654 .recalc = &followparent_recalc,
2655};
2656
2657static struct clk mcbsp3_ick = {
Eduardo Valentin78673bc2008-07-03 12:24:40 +03002658 .name = "mcbsp_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002659 .ops = &clkops_omap2_dflt_wait,
Eduardo Valentin78673bc2008-07-03 12:24:40 +03002660 .id = 3,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002661 .parent = &per_l4_ick,
2662 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2663 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002664 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002665 .recalc = &followparent_recalc,
2666};
2667
2668static struct clk mcbsp4_ick = {
Eduardo Valentin78673bc2008-07-03 12:24:40 +03002669 .name = "mcbsp_ick",
Russell Kingb36ee722008-11-04 17:59:52 +00002670 .ops = &clkops_omap2_dflt_wait,
Eduardo Valentin78673bc2008-07-03 12:24:40 +03002671 .id = 4,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002672 .parent = &per_l4_ick,
2673 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2674 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
Paul Walmsley333943b2008-08-19 11:08:45 +03002675 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002676 .recalc = &followparent_recalc,
2677};
2678
2679static const struct clksel mcbsp_234_clksel[] = {
Paul Walmsley9cfd9852009-01-27 19:13:02 -07002680 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2681 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
Paul Walmsleyb045d082008-03-18 11:24:28 +02002682 { .parent = NULL }
2683};
2684
2685static struct clk mcbsp2_fck = {
Eduardo Valentin78673bc2008-07-03 12:24:40 +03002686 .name = "mcbsp_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002687 .ops = &clkops_omap2_dflt_wait,
Eduardo Valentin78673bc2008-07-03 12:24:40 +03002688 .id = 2,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002689 .init = &omap2_init_clksel_parent,
2690 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2691 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2692 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2693 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2694 .clksel = mcbsp_234_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002695 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002696 .recalc = &omap2_clksel_recalc,
2697};
2698
2699static struct clk mcbsp3_fck = {
Eduardo Valentin78673bc2008-07-03 12:24:40 +03002700 .name = "mcbsp_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002701 .ops = &clkops_omap2_dflt_wait,
Eduardo Valentin78673bc2008-07-03 12:24:40 +03002702 .id = 3,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002703 .init = &omap2_init_clksel_parent,
2704 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2705 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2706 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2707 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2708 .clksel = mcbsp_234_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002709 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002710 .recalc = &omap2_clksel_recalc,
2711};
2712
2713static struct clk mcbsp4_fck = {
Eduardo Valentin78673bc2008-07-03 12:24:40 +03002714 .name = "mcbsp_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002715 .ops = &clkops_omap2_dflt_wait,
Eduardo Valentin78673bc2008-07-03 12:24:40 +03002716 .id = 4,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002717 .init = &omap2_init_clksel_parent,
2718 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2719 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2720 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2721 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2722 .clksel = mcbsp_234_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002723 .clkdm_name = "per_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002724 .recalc = &omap2_clksel_recalc,
2725};
2726
2727/* EMU clocks */
2728
2729/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2730
2731static const struct clksel_rate emu_src_sys_rates[] = {
2732 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2733 { .div = 0 },
2734};
2735
2736static const struct clksel_rate emu_src_core_rates[] = {
2737 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2738 { .div = 0 },
2739};
2740
2741static const struct clksel_rate emu_src_per_rates[] = {
2742 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2743 { .div = 0 },
2744};
2745
2746static const struct clksel_rate emu_src_mpu_rates[] = {
2747 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2748 { .div = 0 },
2749};
2750
2751static const struct clksel emu_src_clksel[] = {
2752 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2753 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2754 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2755 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2756 { .parent = NULL },
2757};
2758
2759/*
2760 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2761 * to switch the source of some of the EMU clocks.
2762 * XXX Are there CLKEN bits for these EMU clks?
2763 */
2764static struct clk emu_src_ck = {
2765 .name = "emu_src_ck",
Russell King897dcde2008-11-04 16:35:03 +00002766 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002767 .init = &omap2_init_clksel_parent,
2768 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2769 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2770 .clksel = emu_src_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002771 .clkdm_name = "emu_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002772 .recalc = &omap2_clksel_recalc,
2773};
2774
2775static const struct clksel_rate pclk_emu_rates[] = {
2776 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2777 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2778 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2779 { .div = 6, .val = 6, .flags = RATE_IN_343X },
2780 { .div = 0 },
2781};
2782
2783static const struct clksel pclk_emu_clksel[] = {
2784 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2785 { .parent = NULL },
2786};
2787
2788static struct clk pclk_fck = {
2789 .name = "pclk_fck",
Russell King897dcde2008-11-04 16:35:03 +00002790 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002791 .init = &omap2_init_clksel_parent,
2792 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2793 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2794 .clksel = pclk_emu_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002795 .clkdm_name = "emu_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002796 .recalc = &omap2_clksel_recalc,
2797};
2798
2799static const struct clksel_rate pclkx2_emu_rates[] = {
2800 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2801 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2802 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2803 { .div = 0 },
2804};
2805
2806static const struct clksel pclkx2_emu_clksel[] = {
2807 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2808 { .parent = NULL },
2809};
2810
2811static struct clk pclkx2_fck = {
2812 .name = "pclkx2_fck",
Russell King897dcde2008-11-04 16:35:03 +00002813 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002814 .init = &omap2_init_clksel_parent,
2815 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2816 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2817 .clksel = pclkx2_emu_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002818 .clkdm_name = "emu_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002819 .recalc = &omap2_clksel_recalc,
2820};
2821
2822static const struct clksel atclk_emu_clksel[] = {
2823 { .parent = &emu_src_ck, .rates = div2_rates },
2824 { .parent = NULL },
2825};
2826
2827static struct clk atclk_fck = {
2828 .name = "atclk_fck",
Russell King897dcde2008-11-04 16:35:03 +00002829 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002830 .init = &omap2_init_clksel_parent,
2831 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2832 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2833 .clksel = atclk_emu_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002834 .clkdm_name = "emu_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002835 .recalc = &omap2_clksel_recalc,
2836};
2837
2838static struct clk traceclk_src_fck = {
2839 .name = "traceclk_src_fck",
Russell King897dcde2008-11-04 16:35:03 +00002840 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002841 .init = &omap2_init_clksel_parent,
2842 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2843 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2844 .clksel = emu_src_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002845 .clkdm_name = "emu_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002846 .recalc = &omap2_clksel_recalc,
2847};
2848
2849static const struct clksel_rate traceclk_rates[] = {
2850 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2851 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2852 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2853 { .div = 0 },
2854};
2855
2856static const struct clksel traceclk_clksel[] = {
2857 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2858 { .parent = NULL },
2859};
2860
2861static struct clk traceclk_fck = {
2862 .name = "traceclk_fck",
Russell King897dcde2008-11-04 16:35:03 +00002863 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002864 .init = &omap2_init_clksel_parent,
2865 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2866 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
2867 .clksel = traceclk_clksel,
Paul Walmsley333943b2008-08-19 11:08:45 +03002868 .clkdm_name = "emu_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002869 .recalc = &omap2_clksel_recalc,
2870};
2871
2872/* SR clocks */
2873
2874/* SmartReflex fclk (VDD1) */
2875static struct clk sr1_fck = {
2876 .name = "sr1_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002877 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002878 .parent = &sys_ck,
2879 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2880 .enable_bit = OMAP3430_EN_SR1_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002881 .recalc = &followparent_recalc,
2882};
2883
2884/* SmartReflex fclk (VDD2) */
2885static struct clk sr2_fck = {
2886 .name = "sr2_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00002887 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002888 .parent = &sys_ck,
2889 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2890 .enable_bit = OMAP3430_EN_SR2_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002891 .recalc = &followparent_recalc,
2892};
2893
2894static struct clk sr_l4_ick = {
2895 .name = "sr_l4_ick",
Russell King897dcde2008-11-04 16:35:03 +00002896 .ops = &clkops_null, /* RMK: missing? */
Paul Walmsleyb045d082008-03-18 11:24:28 +02002897 .parent = &l4_ick,
Paul Walmsley333943b2008-08-19 11:08:45 +03002898 .clkdm_name = "core_l4_clkdm",
Paul Walmsleyb045d082008-03-18 11:24:28 +02002899 .recalc = &followparent_recalc,
2900};
2901
2902/* SECURE_32K_FCK clocks */
2903
2904static struct clk gpt12_fck = {
2905 .name = "gpt12_fck",
Russell King897dcde2008-11-04 16:35:03 +00002906 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002907 .parent = &secure_32k_fck,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002908 .recalc = &followparent_recalc,
2909};
2910
2911static struct clk wdt1_fck = {
2912 .name = "wdt1_fck",
Russell King897dcde2008-11-04 16:35:03 +00002913 .ops = &clkops_null,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002914 .parent = &secure_32k_fck,
Paul Walmsleyb045d082008-03-18 11:24:28 +02002915 .recalc = &followparent_recalc,
2916};
2917
Paul Walmsleyb045d082008-03-18 11:24:28 +02002918#endif