Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 1 | /* |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 2 | * Synopsys DesignWare I2C adapter driver (master only). |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 3 | * |
| 4 | * Based on the TI DAVINCI I2C adapter driver. |
| 5 | * |
| 6 | * Copyright (C) 2006 Texas Instruments. |
| 7 | * Copyright (C) 2007 MontaVista Software Inc. |
| 8 | * Copyright (C) 2009 Provigent Ltd. |
| 9 | * |
| 10 | * ---------------------------------------------------------------------------- |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License as published by |
| 14 | * the Free Software Foundation; either version 2 of the License, or |
| 15 | * (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 25 | * ---------------------------------------------------------------------------- |
| 26 | * |
| 27 | */ |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 28 | #include <linux/export.h> |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 29 | #include <linux/clk.h> |
| 30 | #include <linux/errno.h> |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 31 | #include <linux/err.h> |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 32 | #include <linux/i2c.h> |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 33 | #include <linux/interrupt.h> |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 34 | #include <linux/io.h> |
Dirk Brandewie | 18dbdda | 2011-10-06 11:26:36 -0700 | [diff] [blame] | 35 | #include <linux/pm_runtime.h> |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 36 | #include <linux/delay.h> |
| 37 | #include "i2c-designware-core.h" |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 38 | |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 39 | /* |
| 40 | * Registers offset |
| 41 | */ |
| 42 | #define DW_IC_CON 0x0 |
| 43 | #define DW_IC_TAR 0x4 |
| 44 | #define DW_IC_DATA_CMD 0x10 |
| 45 | #define DW_IC_SS_SCL_HCNT 0x14 |
| 46 | #define DW_IC_SS_SCL_LCNT 0x18 |
| 47 | #define DW_IC_FS_SCL_HCNT 0x1c |
| 48 | #define DW_IC_FS_SCL_LCNT 0x20 |
| 49 | #define DW_IC_INTR_STAT 0x2c |
| 50 | #define DW_IC_INTR_MASK 0x30 |
| 51 | #define DW_IC_RAW_INTR_STAT 0x34 |
| 52 | #define DW_IC_RX_TL 0x38 |
| 53 | #define DW_IC_TX_TL 0x3c |
| 54 | #define DW_IC_CLR_INTR 0x40 |
| 55 | #define DW_IC_CLR_RX_UNDER 0x44 |
| 56 | #define DW_IC_CLR_RX_OVER 0x48 |
| 57 | #define DW_IC_CLR_TX_OVER 0x4c |
| 58 | #define DW_IC_CLR_RD_REQ 0x50 |
| 59 | #define DW_IC_CLR_TX_ABRT 0x54 |
| 60 | #define DW_IC_CLR_RX_DONE 0x58 |
| 61 | #define DW_IC_CLR_ACTIVITY 0x5c |
| 62 | #define DW_IC_CLR_STOP_DET 0x60 |
| 63 | #define DW_IC_CLR_START_DET 0x64 |
| 64 | #define DW_IC_CLR_GEN_CALL 0x68 |
| 65 | #define DW_IC_ENABLE 0x6c |
| 66 | #define DW_IC_STATUS 0x70 |
| 67 | #define DW_IC_TXFLR 0x74 |
| 68 | #define DW_IC_RXFLR 0x78 |
| 69 | #define DW_IC_TX_ABRT_SOURCE 0x80 |
| 70 | #define DW_IC_COMP_PARAM_1 0xf4 |
| 71 | #define DW_IC_COMP_TYPE 0xfc |
| 72 | #define DW_IC_COMP_TYPE_VALUE 0x44570140 |
| 73 | |
| 74 | #define DW_IC_INTR_RX_UNDER 0x001 |
| 75 | #define DW_IC_INTR_RX_OVER 0x002 |
| 76 | #define DW_IC_INTR_RX_FULL 0x004 |
| 77 | #define DW_IC_INTR_TX_OVER 0x008 |
| 78 | #define DW_IC_INTR_TX_EMPTY 0x010 |
| 79 | #define DW_IC_INTR_RD_REQ 0x020 |
| 80 | #define DW_IC_INTR_TX_ABRT 0x040 |
| 81 | #define DW_IC_INTR_RX_DONE 0x080 |
| 82 | #define DW_IC_INTR_ACTIVITY 0x100 |
| 83 | #define DW_IC_INTR_STOP_DET 0x200 |
| 84 | #define DW_IC_INTR_START_DET 0x400 |
| 85 | #define DW_IC_INTR_GEN_CALL 0x800 |
| 86 | |
| 87 | #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ |
| 88 | DW_IC_INTR_TX_EMPTY | \ |
| 89 | DW_IC_INTR_TX_ABRT | \ |
| 90 | DW_IC_INTR_STOP_DET) |
| 91 | |
| 92 | #define DW_IC_STATUS_ACTIVITY 0x1 |
| 93 | |
| 94 | #define DW_IC_ERR_TX_ABRT 0x1 |
| 95 | |
| 96 | /* |
| 97 | * status codes |
| 98 | */ |
| 99 | #define STATUS_IDLE 0x0 |
| 100 | #define STATUS_WRITE_IN_PROGRESS 0x1 |
| 101 | #define STATUS_READ_IN_PROGRESS 0x2 |
| 102 | |
| 103 | #define TIMEOUT 20 /* ms */ |
| 104 | |
| 105 | /* |
| 106 | * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register |
| 107 | * |
| 108 | * only expected abort codes are listed here |
| 109 | * refer to the datasheet for the full list |
| 110 | */ |
| 111 | #define ABRT_7B_ADDR_NOACK 0 |
| 112 | #define ABRT_10ADDR1_NOACK 1 |
| 113 | #define ABRT_10ADDR2_NOACK 2 |
| 114 | #define ABRT_TXDATA_NOACK 3 |
| 115 | #define ABRT_GCALL_NOACK 4 |
| 116 | #define ABRT_GCALL_READ 5 |
| 117 | #define ABRT_SBYTE_ACKDET 7 |
| 118 | #define ABRT_SBYTE_NORSTRT 9 |
| 119 | #define ABRT_10B_RD_NORSTRT 10 |
| 120 | #define ABRT_MASTER_DIS 11 |
| 121 | #define ARB_LOST 12 |
| 122 | |
| 123 | #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) |
| 124 | #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) |
| 125 | #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) |
| 126 | #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) |
| 127 | #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) |
| 128 | #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) |
| 129 | #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) |
| 130 | #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) |
| 131 | #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) |
| 132 | #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) |
| 133 | #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) |
| 134 | |
| 135 | #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ |
| 136 | DW_IC_TX_ABRT_10ADDR1_NOACK | \ |
| 137 | DW_IC_TX_ABRT_10ADDR2_NOACK | \ |
| 138 | DW_IC_TX_ABRT_TXDATA_NOACK | \ |
| 139 | DW_IC_TX_ABRT_GCALL_NOACK) |
| 140 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 141 | static char *abort_sources[] = { |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 142 | [ABRT_7B_ADDR_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 143 | "slave address not acknowledged (7bit mode)", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 144 | [ABRT_10ADDR1_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 145 | "first address byte not acknowledged (10bit mode)", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 146 | [ABRT_10ADDR2_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 147 | "second address byte not acknowledged (10bit mode)", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 148 | [ABRT_TXDATA_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 149 | "data not acknowledged", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 150 | [ABRT_GCALL_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 151 | "no acknowledgement for a general call", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 152 | [ABRT_GCALL_READ] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 153 | "read after general call", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 154 | [ABRT_SBYTE_ACKDET] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 155 | "start byte acknowledged", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 156 | [ABRT_SBYTE_NORSTRT] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 157 | "trying to send start byte when restart is disabled", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 158 | [ABRT_10B_RD_NORSTRT] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 159 | "trying to read when restart is disabled (10bit mode)", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 160 | [ABRT_MASTER_DIS] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 161 | "trying to use disabled adapter", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 162 | [ARB_LOST] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 163 | "lost arbitration", |
| 164 | }; |
| 165 | |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 166 | u32 dw_readl(struct dw_i2c_dev *dev, int offset) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 167 | { |
Stefan Roese | a8a9f3f | 2012-04-18 15:01:41 +0200 | [diff] [blame] | 168 | u32 value; |
Jean-Hugues Deschenes | 18c4089 | 2011-10-06 11:26:27 -0700 | [diff] [blame] | 169 | |
Stefan Roese | a8a9f3f | 2012-04-18 15:01:41 +0200 | [diff] [blame] | 170 | if (dev->accessor_flags & ACCESS_16BIT) |
| 171 | value = readw(dev->base + offset) | |
| 172 | (readw(dev->base + offset + 2) << 16); |
| 173 | else |
| 174 | value = readl(dev->base + offset); |
| 175 | |
| 176 | if (dev->accessor_flags & ACCESS_SWAP) |
Jean-Hugues Deschenes | 18c4089 | 2011-10-06 11:26:27 -0700 | [diff] [blame] | 177 | return swab32(value); |
| 178 | else |
| 179 | return value; |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 180 | } |
| 181 | |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 182 | void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 183 | { |
Stefan Roese | a8a9f3f | 2012-04-18 15:01:41 +0200 | [diff] [blame] | 184 | if (dev->accessor_flags & ACCESS_SWAP) |
Jean-Hugues Deschenes | 18c4089 | 2011-10-06 11:26:27 -0700 | [diff] [blame] | 185 | b = swab32(b); |
| 186 | |
Stefan Roese | a8a9f3f | 2012-04-18 15:01:41 +0200 | [diff] [blame] | 187 | if (dev->accessor_flags & ACCESS_16BIT) { |
| 188 | writew((u16)b, dev->base + offset); |
| 189 | writew((u16)(b >> 16), dev->base + offset + 2); |
| 190 | } else { |
| 191 | writel(b, dev->base + offset); |
| 192 | } |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 193 | } |
| 194 | |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 195 | static u32 |
| 196 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) |
| 197 | { |
| 198 | /* |
| 199 | * DesignWare I2C core doesn't seem to have solid strategy to meet |
| 200 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec |
| 201 | * will result in violation of the tHD;STA spec. |
| 202 | */ |
| 203 | if (cond) |
| 204 | /* |
| 205 | * Conditional expression: |
| 206 | * |
| 207 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH |
| 208 | * |
| 209 | * This is based on the DW manuals, and represents an ideal |
| 210 | * configuration. The resulting I2C bus speed will be |
| 211 | * faster than any of the others. |
| 212 | * |
| 213 | * If your hardware is free from tHD;STA issue, try this one. |
| 214 | */ |
| 215 | return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset; |
| 216 | else |
| 217 | /* |
| 218 | * Conditional expression: |
| 219 | * |
| 220 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) |
| 221 | * |
| 222 | * This is just experimental rule; the tHD;STA period turned |
| 223 | * out to be proportinal to (_HCNT + 3). With this setting, |
| 224 | * we could meet both tHIGH and tHD;STA timing specs. |
| 225 | * |
| 226 | * If unsure, you'd better to take this alternative. |
| 227 | * |
| 228 | * The reason why we need to take into account "tf" here, |
| 229 | * is the same as described in i2c_dw_scl_lcnt(). |
| 230 | */ |
| 231 | return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset; |
| 232 | } |
| 233 | |
| 234 | static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) |
| 235 | { |
| 236 | /* |
| 237 | * Conditional expression: |
| 238 | * |
| 239 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) |
| 240 | * |
| 241 | * DW I2C core starts counting the SCL CNTs for the LOW period |
| 242 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. |
| 243 | * In order to meet the tLOW timing spec, we need to take into |
| 244 | * account the fall time of SCL signal (tf). Default tf value |
| 245 | * should be 0.3 us, for safety. |
| 246 | */ |
| 247 | return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset; |
| 248 | } |
| 249 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 250 | /** |
| 251 | * i2c_dw_init() - initialize the designware i2c master hardware |
| 252 | * @dev: device private data |
| 253 | * |
| 254 | * This functions configures and enables the I2C master. |
| 255 | * This function is called during I2C init function, and in case of timeout at |
| 256 | * run time. |
| 257 | */ |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 258 | int i2c_dw_init(struct dw_i2c_dev *dev) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 259 | { |
Dirk Brandewie | 1d31b58 | 2011-10-06 11:26:30 -0700 | [diff] [blame] | 260 | u32 input_clock_khz; |
Dirk Brandewie | e18563f | 2011-10-06 11:26:32 -0700 | [diff] [blame] | 261 | u32 hcnt, lcnt; |
Dirk Brandewie | 4a423a8 | 2011-10-06 11:26:28 -0700 | [diff] [blame] | 262 | u32 reg; |
| 263 | |
Dirk Brandewie | 1d31b58 | 2011-10-06 11:26:30 -0700 | [diff] [blame] | 264 | input_clock_khz = dev->get_clk_rate_khz(dev); |
| 265 | |
Dirk Brandewie | 4a423a8 | 2011-10-06 11:26:28 -0700 | [diff] [blame] | 266 | reg = dw_readl(dev, DW_IC_COMP_TYPE); |
| 267 | if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) { |
Stefan Roese | a8a9f3f | 2012-04-18 15:01:41 +0200 | [diff] [blame] | 268 | /* Configure register endianess access */ |
| 269 | dev->accessor_flags |= ACCESS_SWAP; |
| 270 | } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { |
| 271 | /* Configure register access mode 16bit */ |
| 272 | dev->accessor_flags |= ACCESS_16BIT; |
| 273 | } else if (reg != DW_IC_COMP_TYPE_VALUE) { |
Dirk Brandewie | 4a423a8 | 2011-10-06 11:26:28 -0700 | [diff] [blame] | 274 | dev_err(dev->dev, "Unknown Synopsys component type: " |
| 275 | "0x%08x\n", reg); |
| 276 | return -ENODEV; |
| 277 | } |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 278 | |
| 279 | /* Disable the adapter */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 280 | dw_writel(dev, 0, DW_IC_ENABLE); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 281 | |
| 282 | /* set standard and fast speed deviders for high/low periods */ |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 283 | |
| 284 | /* Standard-mode */ |
| 285 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, |
| 286 | 40, /* tHD;STA = tHIGH = 4.0 us */ |
| 287 | 3, /* tf = 0.3 us */ |
| 288 | 0, /* 0: DW default, 1: Ideal */ |
| 289 | 0); /* No offset */ |
| 290 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, |
| 291 | 47, /* tLOW = 4.7 us */ |
| 292 | 3, /* tf = 0.3 us */ |
| 293 | 0); /* No offset */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 294 | dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); |
| 295 | dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 296 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
| 297 | |
| 298 | /* Fast-mode */ |
| 299 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, |
| 300 | 6, /* tHD;STA = tHIGH = 0.6 us */ |
| 301 | 3, /* tf = 0.3 us */ |
| 302 | 0, /* 0: DW default, 1: Ideal */ |
| 303 | 0); /* No offset */ |
| 304 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, |
| 305 | 13, /* tLOW = 1.3 us */ |
| 306 | 3, /* tf = 0.3 us */ |
| 307 | 0); /* No offset */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 308 | dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); |
| 309 | dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 310 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 311 | |
Shinya Kuribayashi | 4cb6d1d | 2009-11-06 21:48:12 +0900 | [diff] [blame] | 312 | /* Configure Tx/Rx FIFO threshold levels */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 313 | dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL); |
| 314 | dw_writel(dev, 0, DW_IC_RX_TL); |
Shinya Kuribayashi | 4cb6d1d | 2009-11-06 21:48:12 +0900 | [diff] [blame] | 315 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 316 | /* configure the i2c master */ |
Dirk Brandewie | e18563f | 2011-10-06 11:26:32 -0700 | [diff] [blame] | 317 | dw_writel(dev, dev->master_cfg , DW_IC_CON); |
Dirk Brandewie | 4a423a8 | 2011-10-06 11:26:28 -0700 | [diff] [blame] | 318 | return 0; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 319 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 320 | EXPORT_SYMBOL_GPL(i2c_dw_init); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 321 | |
| 322 | /* |
| 323 | * Waiting for bus not busy |
| 324 | */ |
| 325 | static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) |
| 326 | { |
| 327 | int timeout = TIMEOUT; |
| 328 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 329 | while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 330 | if (timeout <= 0) { |
| 331 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); |
| 332 | return -ETIMEDOUT; |
| 333 | } |
| 334 | timeout--; |
| 335 | mdelay(1); |
| 336 | } |
| 337 | |
| 338 | return 0; |
| 339 | } |
| 340 | |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 341 | static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) |
| 342 | { |
| 343 | struct i2c_msg *msgs = dev->msgs; |
| 344 | u32 ic_con; |
| 345 | |
| 346 | /* Disable the adapter */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 347 | dw_writel(dev, 0, DW_IC_ENABLE); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 348 | |
| 349 | /* set the slave (target) address */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 350 | dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 351 | |
| 352 | /* if the slave address is ten bit address, enable 10BITADDR */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 353 | ic_con = dw_readl(dev, DW_IC_CON); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 354 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) |
| 355 | ic_con |= DW_IC_CON_10BITADDR_MASTER; |
| 356 | else |
| 357 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 358 | dw_writel(dev, ic_con, DW_IC_CON); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 359 | |
| 360 | /* Enable the adapter */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 361 | dw_writel(dev, 1, DW_IC_ENABLE); |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 362 | |
| 363 | /* Enable interrupts */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 364 | dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 365 | } |
| 366 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 367 | /* |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 368 | * Initiate (and continue) low level master read/write transaction. |
| 369 | * This function is only called from i2c_dw_isr, and pumping i2c_msg |
| 370 | * messages into the tx buffer. Even if the size of i2c_msg data is |
| 371 | * longer than the size of the tx buffer, it handles everything. |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 372 | */ |
Jean Delvare | bccd780 | 2012-10-05 22:23:53 +0200 | [diff] [blame] | 373 | static void |
Shinya Kuribayashi | e77cf23 | 2009-11-06 21:46:04 +0900 | [diff] [blame] | 374 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 375 | { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 376 | struct i2c_msg *msgs = dev->msgs; |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 377 | u32 intr_mask; |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 378 | int tx_limit, rx_limit; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 379 | u32 addr = msgs[dev->msg_write_idx].addr; |
| 380 | u32 buf_len = dev->tx_buf_len; |
Justin P. Mattock | 6993248 | 2011-07-26 23:06:29 -0700 | [diff] [blame] | 381 | u8 *buf = dev->tx_buf; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 382 | |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 383 | intr_mask = DW_IC_INTR_DEFAULT_MASK; |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 384 | |
Shinya Kuribayashi | 6d2ea48 | 2009-11-06 21:46:29 +0900 | [diff] [blame] | 385 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 386 | /* |
| 387 | * if target address has changed, we need to |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 388 | * reprogram the target address in the i2c |
| 389 | * adapter when we are done with this transfer |
| 390 | */ |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 391 | if (msgs[dev->msg_write_idx].addr != addr) { |
| 392 | dev_err(dev->dev, |
| 393 | "%s: invalid target address\n", __func__); |
| 394 | dev->msg_err = -EINVAL; |
| 395 | break; |
| 396 | } |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 397 | |
| 398 | if (msgs[dev->msg_write_idx].len == 0) { |
| 399 | dev_err(dev->dev, |
| 400 | "%s: invalid message length\n", __func__); |
| 401 | dev->msg_err = -EINVAL; |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 402 | break; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 403 | } |
| 404 | |
| 405 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { |
| 406 | /* new i2c_msg */ |
Shinya Kuribayashi | 26ea15b | 2009-11-06 21:49:14 +0900 | [diff] [blame] | 407 | buf = msgs[dev->msg_write_idx].buf; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 408 | buf_len = msgs[dev->msg_write_idx].len; |
| 409 | } |
| 410 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 411 | tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR); |
| 412 | rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR); |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 413 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 414 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { |
| 415 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 416 | dw_writel(dev, 0x100, DW_IC_DATA_CMD); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 417 | rx_limit--; |
| 418 | } else |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 419 | dw_writel(dev, *buf++, DW_IC_DATA_CMD); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 420 | tx_limit--; buf_len--; |
| 421 | } |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 422 | |
Shinya Kuribayashi | 26ea15b | 2009-11-06 21:49:14 +0900 | [diff] [blame] | 423 | dev->tx_buf = buf; |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 424 | dev->tx_buf_len = buf_len; |
| 425 | |
| 426 | if (buf_len > 0) { |
| 427 | /* more bytes to be written */ |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 428 | dev->status |= STATUS_WRITE_IN_PROGRESS; |
| 429 | break; |
Shinya Kuribayashi | 69151e5 | 2009-11-06 21:51:00 +0900 | [diff] [blame] | 430 | } else |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 431 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 432 | } |
| 433 | |
Shinya Kuribayashi | 69151e5 | 2009-11-06 21:51:00 +0900 | [diff] [blame] | 434 | /* |
| 435 | * If i2c_msg index search is completed, we don't need TX_EMPTY |
| 436 | * interrupt any more. |
| 437 | */ |
| 438 | if (dev->msg_write_idx == dev->msgs_num) |
| 439 | intr_mask &= ~DW_IC_INTR_TX_EMPTY; |
| 440 | |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 441 | if (dev->msg_err) |
| 442 | intr_mask = 0; |
| 443 | |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 444 | dw_writel(dev, intr_mask, DW_IC_INTR_MASK); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 445 | } |
| 446 | |
| 447 | static void |
Shinya Kuribayashi | 78839bd | 2009-11-06 21:45:39 +0900 | [diff] [blame] | 448 | i2c_dw_read(struct dw_i2c_dev *dev) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 449 | { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 450 | struct i2c_msg *msgs = dev->msgs; |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 451 | int rx_valid; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 452 | |
Shinya Kuribayashi | 6d2ea48 | 2009-11-06 21:46:29 +0900 | [diff] [blame] | 453 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 454 | u32 len; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 455 | u8 *buf; |
| 456 | |
| 457 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) |
| 458 | continue; |
| 459 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 460 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { |
| 461 | len = msgs[dev->msg_read_idx].len; |
| 462 | buf = msgs[dev->msg_read_idx].buf; |
| 463 | } else { |
| 464 | len = dev->rx_buf_len; |
| 465 | buf = dev->rx_buf; |
| 466 | } |
| 467 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 468 | rx_valid = dw_readl(dev, DW_IC_RXFLR); |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 469 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 470 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 471 | *buf++ = dw_readl(dev, DW_IC_DATA_CMD); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 472 | |
| 473 | if (len > 0) { |
| 474 | dev->status |= STATUS_READ_IN_PROGRESS; |
| 475 | dev->rx_buf_len = len; |
| 476 | dev->rx_buf = buf; |
| 477 | return; |
| 478 | } else |
| 479 | dev->status &= ~STATUS_READ_IN_PROGRESS; |
| 480 | } |
| 481 | } |
| 482 | |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 483 | static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) |
| 484 | { |
| 485 | unsigned long abort_source = dev->abort_source; |
| 486 | int i; |
| 487 | |
Shinya Kuribayashi | 6d1ea0f | 2009-11-16 20:40:14 +0900 | [diff] [blame] | 488 | if (abort_source & DW_IC_TX_ABRT_NOACK) { |
Akinobu Mita | 984b3f5 | 2010-03-05 13:41:37 -0800 | [diff] [blame] | 489 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
Shinya Kuribayashi | 6d1ea0f | 2009-11-16 20:40:14 +0900 | [diff] [blame] | 490 | dev_dbg(dev->dev, |
| 491 | "%s: %s\n", __func__, abort_sources[i]); |
| 492 | return -EREMOTEIO; |
| 493 | } |
| 494 | |
Akinobu Mita | 984b3f5 | 2010-03-05 13:41:37 -0800 | [diff] [blame] | 495 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 496 | dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); |
| 497 | |
| 498 | if (abort_source & DW_IC_TX_ARB_LOST) |
| 499 | return -EAGAIN; |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 500 | else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) |
| 501 | return -EINVAL; /* wrong msgs[] data */ |
| 502 | else |
| 503 | return -EIO; |
| 504 | } |
| 505 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 506 | /* |
| 507 | * Prepare controller for a transaction and call i2c_dw_xfer_msg |
| 508 | */ |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 509 | int |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 510 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) |
| 511 | { |
| 512 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); |
| 513 | int ret; |
| 514 | |
| 515 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); |
| 516 | |
| 517 | mutex_lock(&dev->lock); |
Dirk Brandewie | 18dbdda | 2011-10-06 11:26:36 -0700 | [diff] [blame] | 518 | pm_runtime_get_sync(dev->dev); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 519 | |
| 520 | INIT_COMPLETION(dev->cmd_complete); |
| 521 | dev->msgs = msgs; |
| 522 | dev->msgs_num = num; |
| 523 | dev->cmd_err = 0; |
| 524 | dev->msg_write_idx = 0; |
| 525 | dev->msg_read_idx = 0; |
| 526 | dev->msg_err = 0; |
| 527 | dev->status = STATUS_IDLE; |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 528 | dev->abort_source = 0; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 529 | |
| 530 | ret = i2c_dw_wait_bus_not_busy(dev); |
| 531 | if (ret < 0) |
| 532 | goto done; |
| 533 | |
| 534 | /* start the transfers */ |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 535 | i2c_dw_xfer_init(dev); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 536 | |
| 537 | /* wait for tx to complete */ |
| 538 | ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ); |
| 539 | if (ret == 0) { |
| 540 | dev_err(dev->dev, "controller timed out\n"); |
| 541 | i2c_dw_init(dev); |
| 542 | ret = -ETIMEDOUT; |
| 543 | goto done; |
| 544 | } else if (ret < 0) |
| 545 | goto done; |
| 546 | |
| 547 | if (dev->msg_err) { |
| 548 | ret = dev->msg_err; |
| 549 | goto done; |
| 550 | } |
| 551 | |
| 552 | /* no error */ |
| 553 | if (likely(!dev->cmd_err)) { |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 554 | /* Disable the adapter */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 555 | dw_writel(dev, 0, DW_IC_ENABLE); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 556 | ret = num; |
| 557 | goto done; |
| 558 | } |
| 559 | |
| 560 | /* We have an error */ |
| 561 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 562 | ret = i2c_dw_handle_tx_abort(dev); |
| 563 | goto done; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 564 | } |
| 565 | ret = -EIO; |
| 566 | |
| 567 | done: |
Dirk Brandewie | 18dbdda | 2011-10-06 11:26:36 -0700 | [diff] [blame] | 568 | pm_runtime_put(dev->dev); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 569 | mutex_unlock(&dev->lock); |
| 570 | |
| 571 | return ret; |
| 572 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 573 | EXPORT_SYMBOL_GPL(i2c_dw_xfer); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 574 | |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 575 | u32 i2c_dw_func(struct i2c_adapter *adap) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 576 | { |
Dirk Brandewie | 2fa8326 | 2011-10-06 11:26:31 -0700 | [diff] [blame] | 577 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); |
| 578 | return dev->functionality; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 579 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 580 | EXPORT_SYMBOL_GPL(i2c_dw_func); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 581 | |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 582 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
| 583 | { |
| 584 | u32 stat; |
| 585 | |
| 586 | /* |
| 587 | * The IC_INTR_STAT register just indicates "enabled" interrupts. |
| 588 | * Ths unmasked raw version of interrupt status bits are available |
| 589 | * in the IC_RAW_INTR_STAT register. |
| 590 | * |
| 591 | * That is, |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 592 | * stat = dw_readl(IC_INTR_STAT); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 593 | * equals to, |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 594 | * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 595 | * |
| 596 | * The raw version might be useful for debugging purposes. |
| 597 | */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 598 | stat = dw_readl(dev, DW_IC_INTR_STAT); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 599 | |
| 600 | /* |
| 601 | * Do not use the IC_CLR_INTR register to clear interrupts, or |
| 602 | * you'll miss some interrupts, triggered during the period from |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 603 | * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR). |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 604 | * |
| 605 | * Instead, use the separately-prepared IC_CLR_* registers. |
| 606 | */ |
| 607 | if (stat & DW_IC_INTR_RX_UNDER) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 608 | dw_readl(dev, DW_IC_CLR_RX_UNDER); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 609 | if (stat & DW_IC_INTR_RX_OVER) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 610 | dw_readl(dev, DW_IC_CLR_RX_OVER); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 611 | if (stat & DW_IC_INTR_TX_OVER) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 612 | dw_readl(dev, DW_IC_CLR_TX_OVER); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 613 | if (stat & DW_IC_INTR_RD_REQ) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 614 | dw_readl(dev, DW_IC_CLR_RD_REQ); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 615 | if (stat & DW_IC_INTR_TX_ABRT) { |
| 616 | /* |
| 617 | * The IC_TX_ABRT_SOURCE register is cleared whenever |
| 618 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. |
| 619 | */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 620 | dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE); |
| 621 | dw_readl(dev, DW_IC_CLR_TX_ABRT); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 622 | } |
| 623 | if (stat & DW_IC_INTR_RX_DONE) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 624 | dw_readl(dev, DW_IC_CLR_RX_DONE); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 625 | if (stat & DW_IC_INTR_ACTIVITY) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 626 | dw_readl(dev, DW_IC_CLR_ACTIVITY); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 627 | if (stat & DW_IC_INTR_STOP_DET) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 628 | dw_readl(dev, DW_IC_CLR_STOP_DET); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 629 | if (stat & DW_IC_INTR_START_DET) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 630 | dw_readl(dev, DW_IC_CLR_START_DET); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 631 | if (stat & DW_IC_INTR_GEN_CALL) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 632 | dw_readl(dev, DW_IC_CLR_GEN_CALL); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 633 | |
| 634 | return stat; |
| 635 | } |
| 636 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 637 | /* |
| 638 | * Interrupt service routine. This gets called whenever an I2C interrupt |
| 639 | * occurs. |
| 640 | */ |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 641 | irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 642 | { |
| 643 | struct dw_i2c_dev *dev = dev_id; |
Dirk Brandewie | af06cf6 | 2011-10-06 11:26:33 -0700 | [diff] [blame] | 644 | u32 stat, enabled; |
| 645 | |
| 646 | enabled = dw_readl(dev, DW_IC_ENABLE); |
| 647 | stat = dw_readl(dev, DW_IC_RAW_INTR_STAT); |
| 648 | dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__, |
| 649 | dev->adapter.name, enabled, stat); |
| 650 | if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY)) |
| 651 | return IRQ_NONE; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 652 | |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 653 | stat = i2c_dw_read_clear_intrbits(dev); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 654 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 655 | if (stat & DW_IC_INTR_TX_ABRT) { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 656 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
| 657 | dev->status = STATUS_IDLE; |
Shinya Kuribayashi | 597fe31 | 2009-11-06 21:51:36 +0900 | [diff] [blame] | 658 | |
| 659 | /* |
| 660 | * Anytime TX_ABRT is set, the contents of the tx/rx |
| 661 | * buffers are flushed. Make sure to skip them. |
| 662 | */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 663 | dw_writel(dev, 0, DW_IC_INTR_MASK); |
Shinya Kuribayashi | 597fe31 | 2009-11-06 21:51:36 +0900 | [diff] [blame] | 664 | goto tx_aborted; |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 665 | } |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 666 | |
Shinya Kuribayashi | 21a89d4 | 2009-11-06 21:48:33 +0900 | [diff] [blame] | 667 | if (stat & DW_IC_INTR_RX_FULL) |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 668 | i2c_dw_read(dev); |
Shinya Kuribayashi | 21a89d4 | 2009-11-06 21:48:33 +0900 | [diff] [blame] | 669 | |
| 670 | if (stat & DW_IC_INTR_TX_EMPTY) |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 671 | i2c_dw_xfer_msg(dev); |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 672 | |
| 673 | /* |
| 674 | * No need to modify or disable the interrupt mask here. |
| 675 | * i2c_dw_xfer_msg() will take care of it according to |
| 676 | * the current transmit status. |
| 677 | */ |
| 678 | |
Shinya Kuribayashi | 597fe31 | 2009-11-06 21:51:36 +0900 | [diff] [blame] | 679 | tx_aborted: |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 680 | if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 681 | complete(&dev->cmd_complete); |
| 682 | |
| 683 | return IRQ_HANDLED; |
| 684 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 685 | EXPORT_SYMBOL_GPL(i2c_dw_isr); |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 686 | |
| 687 | void i2c_dw_enable(struct dw_i2c_dev *dev) |
| 688 | { |
| 689 | /* Enable the adapter */ |
| 690 | dw_writel(dev, 1, DW_IC_ENABLE); |
| 691 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 692 | EXPORT_SYMBOL_GPL(i2c_dw_enable); |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 693 | |
Dirk Brandewie | 18dbdda | 2011-10-06 11:26:36 -0700 | [diff] [blame] | 694 | u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev) |
| 695 | { |
| 696 | return dw_readl(dev, DW_IC_ENABLE); |
| 697 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 698 | EXPORT_SYMBOL_GPL(i2c_dw_is_enabled); |
Dirk Brandewie | 18dbdda | 2011-10-06 11:26:36 -0700 | [diff] [blame] | 699 | |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 700 | void i2c_dw_disable(struct dw_i2c_dev *dev) |
| 701 | { |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 702 | /* Disable controller */ |
| 703 | dw_writel(dev, 0, DW_IC_ENABLE); |
| 704 | |
| 705 | /* Disable all interupts */ |
| 706 | dw_writel(dev, 0, DW_IC_INTR_MASK); |
| 707 | dw_readl(dev, DW_IC_CLR_INTR); |
| 708 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 709 | EXPORT_SYMBOL_GPL(i2c_dw_disable); |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 710 | |
| 711 | void i2c_dw_clear_int(struct dw_i2c_dev *dev) |
| 712 | { |
| 713 | dw_readl(dev, DW_IC_CLR_INTR); |
| 714 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 715 | EXPORT_SYMBOL_GPL(i2c_dw_clear_int); |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 716 | |
| 717 | void i2c_dw_disable_int(struct dw_i2c_dev *dev) |
| 718 | { |
| 719 | dw_writel(dev, 0, DW_IC_INTR_MASK); |
| 720 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 721 | EXPORT_SYMBOL_GPL(i2c_dw_disable_int); |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 722 | |
| 723 | u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev) |
| 724 | { |
| 725 | return dw_readl(dev, DW_IC_COMP_PARAM_1); |
| 726 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 727 | EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param); |