Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 13 | #ifndef _SDE_HW_CTL_H |
| 14 | #define _SDE_HW_CTL_H |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 15 | |
| 16 | #include "sde_hw_mdss.h" |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 17 | #include "sde_hw_util.h" |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 18 | #include "sde_hw_catalog.h" |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 19 | #include "sde_hw_sspp.h" |
Lloyd Atkinson | 652e59b | 2017-05-03 11:20:30 -0400 | [diff] [blame] | 20 | #include "sde_hw_blk.h" |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 21 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 22 | /** |
| 23 | * sde_ctl_mode_sel: Interface mode selection |
| 24 | * SDE_CTL_MODE_SEL_VID: Video mode interface |
| 25 | * SDE_CTL_MODE_SEL_CMD: Command mode interface |
| 26 | */ |
| 27 | enum sde_ctl_mode_sel { |
| 28 | SDE_CTL_MODE_SEL_VID = 0, |
| 29 | SDE_CTL_MODE_SEL_CMD |
| 30 | }; |
| 31 | |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 32 | /** |
| 33 | * sde_ctl_rot_op_mode - inline rotation mode |
| 34 | * SDE_CTL_ROT_OP_MODE_OFFLINE: offline rotation |
| 35 | * SDE_CTL_ROT_OP_MODE_RESERVED: reserved |
| 36 | * SDE_CTL_ROT_OP_MODE_INLINE_SYNC: inline rotation synchronous mode |
| 37 | * SDE_CTL_ROT_OP_MODE_INLINE_ASYNC: inline rotation asynchronous mode |
| 38 | */ |
| 39 | enum sde_ctl_rot_op_mode { |
| 40 | SDE_CTL_ROT_OP_MODE_OFFLINE, |
| 41 | SDE_CTL_ROT_OP_MODE_RESERVED, |
| 42 | SDE_CTL_ROT_OP_MODE_INLINE_SYNC, |
| 43 | SDE_CTL_ROT_OP_MODE_INLINE_ASYNC, |
| 44 | }; |
| 45 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 46 | struct sde_hw_ctl; |
| 47 | /** |
| 48 | * struct sde_hw_stage_cfg - blending stage cfg |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 49 | * @stage : SSPP_ID at each stage |
| 50 | * @multirect_index: index of the rectangle of SSPP. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 51 | */ |
| 52 | struct sde_hw_stage_cfg { |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 53 | enum sde_sspp stage[SDE_STAGE_MAX][PIPES_PER_STAGE]; |
| 54 | enum sde_sspp_multirect_index multirect_index |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 55 | [SDE_STAGE_MAX][PIPES_PER_STAGE]; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 56 | }; |
| 57 | |
| 58 | /** |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 59 | * struct sde_hw_intf_cfg :Describes how the SDE writes data to output interface |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 60 | * @intf : Interface id |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 61 | * @wb: Writeback id |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 62 | * @mode_3d: 3d mux configuration |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 63 | * @intf_mode_sel: Interface mode, cmd / vid |
| 64 | * @stream_sel: Stream selection for multi-stream interfaces |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 65 | */ |
| 66 | struct sde_hw_intf_cfg { |
| 67 | enum sde_intf intf; |
| 68 | enum sde_wb wb; |
| 69 | enum sde_3d_blend_mode mode_3d; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 70 | enum sde_ctl_mode_sel intf_mode_sel; |
| 71 | int stream_sel; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 72 | }; |
| 73 | |
| 74 | /** |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 75 | * struct sde_ctl_sbuf_cfg - control for stream buffer configuration |
| 76 | * @rot_op_mode: rotator operation mode |
| 77 | */ |
| 78 | struct sde_ctl_sbuf_cfg { |
| 79 | enum sde_ctl_rot_op_mode rot_op_mode; |
| 80 | }; |
| 81 | |
| 82 | /** |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 83 | * struct sde_hw_ctl_ops - Interface to the wb Hw driver functions |
| 84 | * Assumption is these functions will be called after clocks are enabled |
| 85 | */ |
| 86 | struct sde_hw_ctl_ops { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 87 | /** |
| 88 | * kickoff hw operation for Sw controlled interfaces |
| 89 | * DSI cmd mode and WB interface are SW controlled |
| 90 | * @ctx : ctl path ctx pointer |
| 91 | */ |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 92 | void (*trigger_start)(struct sde_hw_ctl *ctx); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 93 | |
| 94 | /** |
Dhaval Patel | 0e558f4 | 2017-04-30 00:51:40 -0700 | [diff] [blame] | 95 | * kickoff prepare is in progress hw operation for sw |
| 96 | * controlled interfaces: DSI cmd mode and WB interface |
| 97 | * are SW controlled |
| 98 | * @ctx : ctl path ctx pointer |
| 99 | */ |
| 100 | void (*trigger_pending)(struct sde_hw_ctl *ctx); |
| 101 | |
| 102 | /** |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 103 | * kickoff rotator operation for Sw controlled interfaces |
| 104 | * DSI cmd mode and WB interface are SW controlled |
| 105 | * @ctx : ctl path ctx pointer |
| 106 | */ |
| 107 | void (*trigger_rot_start)(struct sde_hw_ctl *ctx); |
| 108 | |
| 109 | /** |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 110 | * Clear the value of the cached pending_flush_mask |
| 111 | * No effect on hardware |
| 112 | * @ctx : ctl path ctx pointer |
| 113 | */ |
| 114 | void (*clear_pending_flush)(struct sde_hw_ctl *ctx); |
| 115 | |
| 116 | /** |
Clarence Ip | 110d15c | 2016-08-16 14:44:41 -0400 | [diff] [blame] | 117 | * Query the value of the cached pending_flush_mask |
| 118 | * No effect on hardware |
| 119 | * @ctx : ctl path ctx pointer |
| 120 | */ |
| 121 | u32 (*get_pending_flush)(struct sde_hw_ctl *ctx); |
| 122 | |
| 123 | /** |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 124 | * OR in the given flushbits to the cached pending_flush_mask |
| 125 | * No effect on hardware |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 126 | * @ctx : ctl path ctx pointer |
| 127 | * @flushbits : module flushmask |
| 128 | */ |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 129 | void (*update_pending_flush)(struct sde_hw_ctl *ctx, |
| 130 | u32 flushbits); |
| 131 | |
| 132 | /** |
| 133 | * Write the value of the pending_flush_mask to hardware |
| 134 | * @ctx : ctl path ctx pointer |
| 135 | */ |
| 136 | void (*trigger_flush)(struct sde_hw_ctl *ctx); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 137 | |
| 138 | /** |
Lloyd Atkinson | 6340a37 | 2017-04-05 13:04:22 -0700 | [diff] [blame] | 139 | * Read the value of the flush register |
| 140 | * @ctx : ctl path ctx pointer |
| 141 | * @Return: value of the ctl flush register. |
| 142 | */ |
| 143 | u32 (*get_flush_register)(struct sde_hw_ctl *ctx); |
| 144 | |
| 145 | /** |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 146 | * Setup ctl_path interface config |
| 147 | * @ctx |
| 148 | * @cfg : interface config structure pointer |
| 149 | */ |
| 150 | void (*setup_intf_cfg)(struct sde_hw_ctl *ctx, |
| 151 | struct sde_hw_intf_cfg *cfg); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 152 | |
| 153 | int (*reset)(struct sde_hw_ctl *c); |
| 154 | |
Lloyd Atkinson | 6cc9de3 | 2016-11-17 17:56:13 -0500 | [diff] [blame] | 155 | /* |
| 156 | * wait_reset_status - checks ctl reset status |
| 157 | * @ctx : ctl path ctx pointer |
| 158 | * |
| 159 | * This function checks the ctl reset status bit. |
| 160 | * If the reset bit is set, it keeps polling the status till the hw |
| 161 | * reset is complete. |
| 162 | * Returns: 0 on success or -error if reset incomplete within interval |
| 163 | */ |
| 164 | int (*wait_reset_status)(struct sde_hw_ctl *ctx); |
| 165 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 166 | uint32_t (*get_bitmask_sspp)(struct sde_hw_ctl *ctx, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 167 | enum sde_sspp blk); |
| 168 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 169 | uint32_t (*get_bitmask_mixer)(struct sde_hw_ctl *ctx, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 170 | enum sde_lm blk); |
| 171 | |
| 172 | int (*get_bitmask_dspp)(struct sde_hw_ctl *ctx, |
| 173 | u32 *flushbits, |
| 174 | enum sde_dspp blk); |
| 175 | |
| 176 | int (*get_bitmask_intf)(struct sde_hw_ctl *ctx, |
| 177 | u32 *flushbits, |
| 178 | enum sde_intf blk); |
| 179 | |
| 180 | int (*get_bitmask_cdm)(struct sde_hw_ctl *ctx, |
| 181 | u32 *flushbits, |
| 182 | enum sde_cdm blk); |
| 183 | |
Alan Kwong | 3232ca5 | 2016-07-29 02:27:47 -0400 | [diff] [blame] | 184 | int (*get_bitmask_wb)(struct sde_hw_ctl *ctx, |
| 185 | u32 *flushbits, |
| 186 | enum sde_wb blk); |
| 187 | |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 188 | int (*get_bitmask_rot)(struct sde_hw_ctl *ctx, |
| 189 | u32 *flushbits, |
| 190 | enum sde_rot blk); |
| 191 | |
Lloyd Atkinson | e5ec30d | 2016-08-23 14:32:32 -0400 | [diff] [blame] | 192 | /** |
| 193 | * Set all blend stages to disabled |
| 194 | * @ctx : ctl path ctx pointer |
| 195 | */ |
| 196 | void (*clear_all_blendstages)(struct sde_hw_ctl *ctx); |
| 197 | |
| 198 | /** |
| 199 | * Configure layer mixer to pipe configuration |
| 200 | * @ctx : ctl path ctx pointer |
| 201 | * @lm : layer mixer enumeration |
| 202 | * @cfg : blend stage configuration |
| 203 | */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 204 | void (*setup_blendstage)(struct sde_hw_ctl *ctx, |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 205 | enum sde_lm lm, struct sde_hw_stage_cfg *cfg); |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 206 | |
| 207 | void (*setup_sbuf_cfg)(struct sde_hw_ctl *ctx, |
| 208 | struct sde_ctl_sbuf_cfg *cfg); |
Gopikrishnaiah Anandan | 3872684 | 2017-08-23 17:56:35 -0700 | [diff] [blame] | 209 | |
| 210 | /** |
| 211 | * Flush the reg dma by sending last command. |
| 212 | * @ctx : ctl path ctx pointer |
| 213 | */ |
| 214 | void (*reg_dma_flush)(struct sde_hw_ctl *ctx); |
| 215 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 216 | }; |
| 217 | |
| 218 | /** |
| 219 | * struct sde_hw_ctl : CTL PATH driver object |
Lloyd Atkinson | 652e59b | 2017-05-03 11:20:30 -0400 | [diff] [blame] | 220 | * @base: hardware block base structure |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 221 | * @hw: block register map object |
| 222 | * @idx: control path index |
Lloyd Atkinson | 652e59b | 2017-05-03 11:20:30 -0400 | [diff] [blame] | 223 | * @caps: control path capabilities |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 224 | * @mixer_count: number of mixers |
| 225 | * @mixer_hw_caps: mixer hardware capabilities |
| 226 | * @pending_flush_mask: storage for pending ctl_flush managed via ops |
| 227 | * @ops: operation list |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 228 | */ |
| 229 | struct sde_hw_ctl { |
Lloyd Atkinson | 652e59b | 2017-05-03 11:20:30 -0400 | [diff] [blame] | 230 | struct sde_hw_blk base; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 231 | struct sde_hw_blk_reg_map hw; |
| 232 | |
| 233 | /* ctl path */ |
| 234 | int idx; |
| 235 | const struct sde_ctl_cfg *caps; |
| 236 | int mixer_count; |
| 237 | const struct sde_lm_cfg *mixer_hw_caps; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 238 | u32 pending_flush_mask; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 239 | |
| 240 | /* ops */ |
| 241 | struct sde_hw_ctl_ops ops; |
| 242 | }; |
| 243 | |
| 244 | /** |
Lloyd Atkinson | ccb5621 | 2017-05-19 16:18:05 -0400 | [diff] [blame] | 245 | * sde_hw_ctl - convert base object sde_hw_base to container |
| 246 | * @hw: Pointer to base hardware block |
| 247 | * return: Pointer to hardware block container |
| 248 | */ |
| 249 | static inline struct sde_hw_ctl *to_sde_hw_ctl(struct sde_hw_blk *hw) |
| 250 | { |
| 251 | return container_of(hw, struct sde_hw_ctl, base); |
| 252 | } |
| 253 | |
| 254 | /** |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 255 | * sde_hw_ctl_init(): Initializes the ctl_path hw driver object. |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 256 | * should be called before accessing every ctl path registers. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 257 | * @idx: ctl_path index for which driver object is required |
| 258 | * @addr: mapped register io address of MDP |
| 259 | * @m : pointer to mdss catalog data |
| 260 | */ |
| 261 | struct sde_hw_ctl *sde_hw_ctl_init(enum sde_ctl idx, |
| 262 | void __iomem *addr, |
| 263 | struct sde_mdss_cfg *m); |
| 264 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 265 | /** |
| 266 | * sde_hw_ctl_destroy(): Destroys ctl driver context |
| 267 | * should be called to free the context |
| 268 | */ |
| 269 | void sde_hw_ctl_destroy(struct sde_hw_ctl *ctx); |
| 270 | |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 271 | #endif /*_SDE_HW_CTL_H */ |