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Bryan Wu1394f032007-05-06 14:50:22 -07001/*
Robin Getz96f10502009-09-24 14:11:24 +00002 * Set up the interrupt priorities
Bryan Wu1394f032007-05-06 14:50:22 -07003 *
Robin Getz96f10502009-09-24 14:11:24 +00004 * Copyright 2004-2009 Analog Devices Inc.
5 * 2003 Bas Vermeulen <bas@buyways.nl>
6 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
7 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
9 * 1996 Roman Zippel
Bryan Wu1394f032007-05-06 14:50:22 -070010 *
Robin Getz96f10502009-09-24 14:11:24 +000011 * Licensed under the GPL-2
Bryan Wu1394f032007-05-06 14:50:22 -070012 */
13
14#include <linux/module.h>
15#include <linux/kernel_stat.h>
16#include <linux/seq_file.h>
17#include <linux/irq.h>
Philippe Gerum5b5da4c2011-03-17 02:12:48 -040018#include <linux/sched.h>
Steven Miao4f6b6002012-05-16 17:56:51 +080019#include <linux/syscore_ops.h>
20#include <asm/delay.h>
Yi Li6a01f232009-01-07 23:14:39 +080021#ifdef CONFIG_IPIPE
22#include <linux/ipipe.h>
23#endif
Bryan Wu1394f032007-05-06 14:50:22 -070024#include <asm/traps.h>
25#include <asm/blackfin.h>
26#include <asm/gpio.h>
27#include <asm/irq_handler.h>
Mike Frysinger761ec442009-10-15 17:12:05 +000028#include <asm/dpmc.h>
Sonic Zhang06051fd2012-07-04 19:22:55 +080029#include <asm/traps.h>
Bryan Wu1394f032007-05-06 14:50:22 -070030
Bryan Wu1394f032007-05-06 14:50:22 -070031/*
32 * NOTES:
33 * - we have separated the physical Hardware interrupt from the
34 * levels that the LINUX kernel sees (see the description in irq.h)
35 * -
36 */
37
Graf Yang6b3087c2009-01-07 23:14:39 +080038#ifndef CONFIG_SMP
Mike Frysingera99bbcc2007-10-22 00:19:31 +080039/* Initialize this to an actual value to force it into the .data
40 * section so that we know it is properly initialized at entry into
41 * the kernel but before bss is initialized to zero (which is where
42 * it would live otherwise). The 0x1f magic represents the IRQs we
43 * cannot actually mask out in hardware.
44 */
Mike Frysinger40059782008-11-18 17:48:22 +080045unsigned long bfin_irq_flags = 0x1f;
46EXPORT_SYMBOL(bfin_irq_flags);
Graf Yang6b3087c2009-01-07 23:14:39 +080047#endif
Bryan Wu1394f032007-05-06 14:50:22 -070048
Michael Hennerichcfefe3c2008-02-09 04:12:37 +080049#ifdef CONFIG_PM
50unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
Michael Hennerich4a88d0c2008-08-05 17:38:41 +080051unsigned vr_wakeup;
Michael Hennerichcfefe3c2008-02-09 04:12:37 +080052#endif
53
Sonic Zhang11b27cb2012-06-28 19:16:48 +080054#ifndef SEC_GCTL
Mike Frysingere9e334c2011-03-30 00:43:52 -040055static struct ivgx {
Michael Hennerich464abc52008-02-25 13:50:20 +080056 /* irq number for request_irq, available in mach-bf5xx/irq.h */
Roy Huang24a07a12007-07-12 22:41:45 +080057 unsigned int irqno;
Bryan Wu1394f032007-05-06 14:50:22 -070058 /* corresponding bit in the SIC_ISR register */
Roy Huang24a07a12007-07-12 22:41:45 +080059 unsigned int isrflag;
Bryan Wu1394f032007-05-06 14:50:22 -070060} ivg_table[NR_PERI_INTS];
61
Mike Frysingere9e334c2011-03-30 00:43:52 -040062static struct ivg_slice {
Bryan Wu1394f032007-05-06 14:50:22 -070063 /* position of first irq in ivg_table for given ivg */
64 struct ivgx *ifirst;
65 struct ivgx *istop;
66} ivg7_13[IVG13 - IVG7 + 1];
67
Bryan Wu1394f032007-05-06 14:50:22 -070068
69/*
70 * Search SIC_IAR and fill tables with the irqvalues
71 * and their positions in the SIC_ISR register.
72 */
73static void __init search_IAR(void)
74{
75 unsigned ivg, irq_pos = 0;
76 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
Mike Frysinger80fcdb92010-04-22 21:15:00 +000077 int irqN;
Bryan Wu1394f032007-05-06 14:50:22 -070078
Michael Hennerich34e0fc82007-07-12 16:17:18 +080079 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
Bryan Wu1394f032007-05-06 14:50:22 -070080
Mike Frysinger80fcdb92010-04-22 21:15:00 +000081 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
82 int irqn;
Steven Miao4f6b6002012-05-16 17:56:51 +080083 u32 iar =
84 bfin_read32((unsigned long *)SIC_IAR0 +
Mike Frysinger80fcdb92010-04-22 21:15:00 +000085#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
86 defined(CONFIG_BF538) || defined(CONFIG_BF539)
87 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
Michael Hennerich59003142007-10-21 16:54:27 +080088#else
Mike Frysinger80fcdb92010-04-22 21:15:00 +000089 (irqN >> 3)
Michael Hennerich59003142007-10-21 16:54:27 +080090#endif
Mike Frysinger80fcdb92010-04-22 21:15:00 +000091 );
Mike Frysinger80fcdb92010-04-22 21:15:00 +000092 for (irqn = irqN; irqn < irqN + 4; ++irqn) {
93 int iar_shift = (irqn & 7) * 4;
94 if (ivg == (0xf & (iar >> iar_shift))) {
95 ivg_table[irq_pos].irqno = IVG7 + irqn;
96 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
97 ivg7_13[ivg].istop++;
98 irq_pos++;
99 }
Bryan Wu1394f032007-05-06 14:50:22 -0700100 }
101 }
102 }
103}
Steven Miao4f6b6002012-05-16 17:56:51 +0800104#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700105
106/*
Michael Hennerich464abc52008-02-25 13:50:20 +0800107 * This is for core internal IRQs
Bryan Wu1394f032007-05-06 14:50:22 -0700108 */
Mike Frysingerf58c3272011-04-15 03:08:20 -0400109void bfin_ack_noop(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700110{
111 /* Dummy function. */
112}
113
Thomas Gleixner4f19ea42011-02-06 18:23:27 +0000114static void bfin_core_mask_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700115{
Thomas Gleixner4f19ea42011-02-06 18:23:27 +0000116 bfin_irq_flags &= ~(1 << d->irq);
David Howells3b139cd2010-10-07 14:08:52 +0100117 if (!hard_irqs_disabled())
118 hard_local_irq_enable();
Bryan Wu1394f032007-05-06 14:50:22 -0700119}
120
Thomas Gleixner4f19ea42011-02-06 18:23:27 +0000121static void bfin_core_unmask_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700122{
Thomas Gleixner4f19ea42011-02-06 18:23:27 +0000123 bfin_irq_flags |= 1 << d->irq;
Bryan Wu1394f032007-05-06 14:50:22 -0700124 /*
125 * If interrupts are enabled, IMASK must contain the same value
Mike Frysinger40059782008-11-18 17:48:22 +0800126 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
Bryan Wu1394f032007-05-06 14:50:22 -0700127 * are currently disabled we need not do anything; one of the
128 * callers will take care of setting IMASK to the proper value
129 * when reenabling interrupts.
Mike Frysinger40059782008-11-18 17:48:22 +0800130 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
Bryan Wu1394f032007-05-06 14:50:22 -0700131 * what we need.
132 */
David Howells3b139cd2010-10-07 14:08:52 +0100133 if (!hard_irqs_disabled())
134 hard_local_irq_enable();
Bryan Wu1394f032007-05-06 14:50:22 -0700135 return;
136}
137
Sonic Zhang86794b42012-12-14 11:19:24 +0800138#ifndef SEC_GCTL
Mike Frysingerf58c3272011-04-15 03:08:20 -0400139void bfin_internal_mask_irq(unsigned int irq)
Bryan Wu1394f032007-05-06 14:50:22 -0700140{
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400141 unsigned long flags = hard_local_irq_save();
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400142#ifdef SIC_IMASK0
Sonic Zhang86794b42012-12-14 11:19:24 +0800143 unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
144 unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
Bryan Wuc04d66b2007-07-12 17:26:31 +0800145 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
Steven Miao4f6b6002012-05-16 17:56:51 +0800146 ~(1 << mask_bit));
147# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
Graf Yang6b3087c2009-01-07 23:14:39 +0800148 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
Steven Miao4f6b6002012-05-16 17:56:51 +0800149 ~(1 << mask_bit));
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400150# endif
151#else
152 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
Sonic Zhang86794b42012-12-14 11:19:24 +0800153 ~(1 << BFIN_SYSIRQ(irq)));
Steven Miao4f6b6002012-05-16 17:56:51 +0800154#endif /* end of SIC_IMASK0 */
David Howells3b139cd2010-10-07 14:08:52 +0100155 hard_local_irq_restore(flags);
Bryan Wu1394f032007-05-06 14:50:22 -0700156}
157
Thomas Gleixnerff43a672011-02-06 18:23:29 +0000158static void bfin_internal_mask_irq_chip(struct irq_data *d)
159{
160 bfin_internal_mask_irq(d->irq);
161}
162
Sonic Zhang0325f252009-12-28 07:29:57 +0000163#ifdef CONFIG_SMP
Steven Miao4f6b6002012-05-16 17:56:51 +0800164void bfin_internal_unmask_irq_affinity(unsigned int irq,
Sonic Zhang0325f252009-12-28 07:29:57 +0000165 const struct cpumask *affinity)
166#else
Mike Frysingerf58c3272011-04-15 03:08:20 -0400167void bfin_internal_unmask_irq(unsigned int irq)
Sonic Zhang0325f252009-12-28 07:29:57 +0000168#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700169{
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400170 unsigned long flags = hard_local_irq_save();
Philippe Gerum9bd50df2009-03-04 16:52:38 +0800171
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400172#ifdef SIC_IMASK0
Sonic Zhang86794b42012-12-14 11:19:24 +0800173 unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
174 unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400175# ifdef CONFIG_SMP
Sonic Zhang0325f252009-12-28 07:29:57 +0000176 if (cpumask_test_cpu(0, affinity))
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400177# endif
Sonic Zhang0325f252009-12-28 07:29:57 +0000178 bfin_write_SIC_IMASK(mask_bank,
Steven Miao4f6b6002012-05-16 17:56:51 +0800179 bfin_read_SIC_IMASK(mask_bank) |
180 (1 << mask_bit));
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400181# ifdef CONFIG_SMP
Sonic Zhang0325f252009-12-28 07:29:57 +0000182 if (cpumask_test_cpu(1, affinity))
183 bfin_write_SICB_IMASK(mask_bank,
Steven Miao4f6b6002012-05-16 17:56:51 +0800184 bfin_read_SICB_IMASK(mask_bank) |
185 (1 << mask_bit));
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400186# endif
187#else
188 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
Sonic Zhang86794b42012-12-14 11:19:24 +0800189 (1 << BFIN_SYSIRQ(irq)));
Steven Miao4f6b6002012-05-16 17:56:51 +0800190#endif
191 hard_local_irq_restore(flags);
192}
193
Sonic Zhang86794b42012-12-14 11:19:24 +0800194#ifdef CONFIG_SMP
195static void bfin_internal_unmask_irq_chip(struct irq_data *d)
196{
197 bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
198}
199
200static int bfin_internal_set_affinity(struct irq_data *d,
201 const struct cpumask *mask, bool force)
202{
203 bfin_internal_mask_irq(d->irq);
204 bfin_internal_unmask_irq_affinity(d->irq, mask);
205
206 return 0;
207}
208#else
209static void bfin_internal_unmask_irq_chip(struct irq_data *d)
210{
211 bfin_internal_unmask_irq(d->irq);
212}
213#endif
214
215#if defined(CONFIG_PM)
216int bfin_internal_set_wake(unsigned int irq, unsigned int state)
217{
218 u32 bank, bit, wakeup = 0;
219 unsigned long flags;
220 bank = BFIN_SYSIRQ(irq) / 32;
221 bit = BFIN_SYSIRQ(irq) % 32;
222
223 switch (irq) {
224#ifdef IRQ_RTC
225 case IRQ_RTC:
226 wakeup |= WAKE;
227 break;
228#endif
229#ifdef IRQ_CAN0_RX
230 case IRQ_CAN0_RX:
231 wakeup |= CANWE;
232 break;
233#endif
234#ifdef IRQ_CAN1_RX
235 case IRQ_CAN1_RX:
236 wakeup |= CANWE;
237 break;
238#endif
239#ifdef IRQ_USB_INT0
240 case IRQ_USB_INT0:
241 wakeup |= USBWE;
242 break;
243#endif
244#ifdef CONFIG_BF54x
245 case IRQ_CNT:
246 wakeup |= ROTWE;
247 break;
248#endif
249 default:
250 break;
251 }
252
253 flags = hard_local_irq_save();
254
255 if (state) {
256 bfin_sic_iwr[bank] |= (1 << bit);
257 vr_wakeup |= wakeup;
258
259 } else {
260 bfin_sic_iwr[bank] &= ~(1 << bit);
261 vr_wakeup &= ~wakeup;
262 }
263
264 hard_local_irq_restore(flags);
265
266 return 0;
267}
268
269static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
270{
271 return bfin_internal_set_wake(d->irq, state);
272}
273#else
274inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
275{
276 return 0;
277}
278# define bfin_internal_set_wake_chip NULL
279#endif
280
281#else /* SEC_GCTL */
Steven Miao4f6b6002012-05-16 17:56:51 +0800282static void bfin_sec_preflow_handler(struct irq_data *d)
283{
284 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800285 unsigned int sid = BFIN_SYSIRQ(d->irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800286
287 bfin_write_SEC_SCI(0, SEC_CSID, sid);
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400288
David Howells3b139cd2010-10-07 14:08:52 +0100289 hard_local_irq_restore(flags);
Bryan Wu1394f032007-05-06 14:50:22 -0700290}
291
Steven Miao4f6b6002012-05-16 17:56:51 +0800292static void bfin_sec_mask_ack_irq(struct irq_data *d)
293{
294 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800295 unsigned int sid = BFIN_SYSIRQ(d->irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800296
297 bfin_write_SEC_SCI(0, SEC_CSID, sid);
298
299 hard_local_irq_restore(flags);
300}
301
302static void bfin_sec_unmask_irq(struct irq_data *d)
303{
304 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800305 unsigned int sid = BFIN_SYSIRQ(d->irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800306
307 bfin_write32(SEC_END, sid);
308
309 hard_local_irq_restore(flags);
310}
311
312static void bfin_sec_enable_ssi(unsigned int sid)
313{
314 unsigned long flags = hard_local_irq_save();
315 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
316
317 reg_sctl |= SEC_SCTL_SRC_EN;
318 bfin_write_SEC_SCTL(sid, reg_sctl);
319
320 hard_local_irq_restore(flags);
321}
322
323static void bfin_sec_disable_ssi(unsigned int sid)
324{
325 unsigned long flags = hard_local_irq_save();
326 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
327
328 reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
329 bfin_write_SEC_SCTL(sid, reg_sctl);
330
331 hard_local_irq_restore(flags);
332}
333
334static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
335{
336 unsigned long flags = hard_local_irq_save();
337 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
338
339 reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
340 bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
341
342 hard_local_irq_restore(flags);
343}
344
345static void bfin_sec_enable_sci(unsigned int sid)
346{
347 unsigned long flags = hard_local_irq_save();
348 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
349
Sonic Zhang86794b42012-12-14 11:19:24 +0800350 if (sid == BFIN_SYSIRQ(IRQ_WATCH0))
Steven Miao4f6b6002012-05-16 17:56:51 +0800351 reg_sctl |= SEC_SCTL_FAULT_EN;
352 else
353 reg_sctl |= SEC_SCTL_INT_EN;
354 bfin_write_SEC_SCTL(sid, reg_sctl);
355
356 hard_local_irq_restore(flags);
357}
358
359static void bfin_sec_disable_sci(unsigned int sid)
360{
361 unsigned long flags = hard_local_irq_save();
362 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
363
364 reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
365 bfin_write_SEC_SCTL(sid, reg_sctl);
366
367 hard_local_irq_restore(flags);
368}
369
370static void bfin_sec_enable(struct irq_data *d)
371{
372 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800373 unsigned int sid = BFIN_SYSIRQ(d->irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800374
375 bfin_sec_enable_sci(sid);
376 bfin_sec_enable_ssi(sid);
377
378 hard_local_irq_restore(flags);
379}
380
381static void bfin_sec_disable(struct irq_data *d)
382{
383 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800384 unsigned int sid = BFIN_SYSIRQ(d->irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800385
386 bfin_sec_disable_sci(sid);
387 bfin_sec_disable_ssi(sid);
388
389 hard_local_irq_restore(flags);
390}
391
Sonic Zhange0a59312012-06-29 18:19:29 +0800392static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority)
393{
394 unsigned long flags = hard_local_irq_save();
395 uint32_t reg_sctl;
396 int i;
397
398 bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels);
399
400 for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) {
401 reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO;
402 reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET;
403 bfin_write_SEC_SCTL(i, reg_sctl);
404 }
405
406 hard_local_irq_restore(flags);
407}
408
Sonic Zhang86794b42012-12-14 11:19:24 +0800409void bfin_sec_raise_irq(unsigned int irq)
Steven Miao4f6b6002012-05-16 17:56:51 +0800410{
411 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800412 unsigned int sid = BFIN_SYSIRQ(irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800413
414 bfin_write32(SEC_RAISE, sid);
415
416 hard_local_irq_restore(flags);
417}
418
419static void init_software_driven_irq(void)
420{
421 bfin_sec_set_ssi_coreid(34, 0);
422 bfin_sec_set_ssi_coreid(35, 1);
Sonic Zhang86794b42012-12-14 11:19:24 +0800423
424 bfin_sec_enable_sci(35);
425 bfin_sec_enable_ssi(35);
Steven Miao4f6b6002012-05-16 17:56:51 +0800426 bfin_sec_set_ssi_coreid(36, 0);
427 bfin_sec_set_ssi_coreid(37, 1);
Sonic Zhang86794b42012-12-14 11:19:24 +0800428 bfin_sec_enable_sci(37);
429 bfin_sec_enable_ssi(37);
Steven Miao4f6b6002012-05-16 17:56:51 +0800430}
431
432void bfin_sec_resume(void)
433{
434 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
435 udelay(100);
436 bfin_write_SEC_GCTL(SEC_GCTL_EN);
437 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
438}
439
440void handle_sec_sfi_fault(uint32_t gstat)
441{
442
443}
444
445void handle_sec_sci_fault(uint32_t gstat)
446{
447 uint32_t core_id;
448 uint32_t cstat;
449
450 core_id = gstat & SEC_GSTAT_SCI;
451 cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
452 if (cstat & SEC_CSTAT_ERR) {
453 switch (cstat & SEC_CSTAT_ERRC) {
454 case SEC_CSTAT_ACKERR:
455 printk(KERN_DEBUG "sec ack err\n");
456 break;
457 default:
458 printk(KERN_DEBUG "sec sci unknow err\n");
459 }
460 }
461
462}
463
464void handle_sec_ssi_fault(uint32_t gstat)
465{
466 uint32_t sid;
467 uint32_t sstat;
468
469 sid = gstat & SEC_GSTAT_SID;
470 sstat = bfin_read_SEC_SSTAT(sid);
471
472}
473
Sonic Zhang1b601232013-12-04 15:27:47 +0800474void handle_sec_fault(uint32_t sec_gstat)
Steven Miao4f6b6002012-05-16 17:56:51 +0800475{
Steven Miao4f6b6002012-05-16 17:56:51 +0800476 if (sec_gstat & SEC_GSTAT_ERR) {
477
478 switch (sec_gstat & SEC_GSTAT_ERRC) {
479 case 0:
480 handle_sec_sfi_fault(sec_gstat);
481 break;
482 case SEC_GSTAT_SCIERR:
483 handle_sec_sci_fault(sec_gstat);
484 break;
485 case SEC_GSTAT_SSIERR:
486 handle_sec_ssi_fault(sec_gstat);
487 break;
488 }
489
490
491 }
Steven Miao4f6b6002012-05-16 17:56:51 +0800492}
493
Sonic Zhang1b601232013-12-04 15:27:47 +0800494static struct irqaction bfin_fault_irq = {
495 .name = "Blackfin fault",
496};
497
498static irqreturn_t bfin_fault_routine(int irq, void *data)
Sonic Zhang06051fd2012-07-04 19:22:55 +0800499{
500 struct pt_regs *fp = get_irq_regs();
501
Sonic Zhang06051fd2012-07-04 19:22:55 +0800502 switch (irq) {
503 case IRQ_C0_DBL_FAULT:
504 double_fault_c(fp);
505 break;
506 case IRQ_C0_HW_ERR:
507 dump_bfin_process(fp);
508 dump_bfin_mem(fp);
509 show_regs(fp);
510 printk(KERN_NOTICE "Kernel Stack\n");
511 show_stack(current, NULL);
512 print_modules();
Sonic Zhang86794b42012-12-14 11:19:24 +0800513 panic("Core 0 hardware error");
Sonic Zhang06051fd2012-07-04 19:22:55 +0800514 break;
515 case IRQ_C0_NMI_L1_PARITY_ERR:
Sonic Zhang86794b42012-12-14 11:19:24 +0800516 panic("Core 0 NMI L1 parity error");
Sonic Zhang06051fd2012-07-04 19:22:55 +0800517 break;
Sonic Zhang1b601232013-12-04 15:27:47 +0800518 case IRQ_SEC_ERR:
519 pr_err("SEC error\n");
520 handle_sec_fault(bfin_read32(SEC_GSTAT));
521 break;
Sonic Zhang06051fd2012-07-04 19:22:55 +0800522 default:
Sonic Zhang1b601232013-12-04 15:27:47 +0800523 panic("Unknown fault %d", irq);
Sonic Zhang06051fd2012-07-04 19:22:55 +0800524 }
525
Sonic Zhang1b601232013-12-04 15:27:47 +0800526 return IRQ_HANDLED;
Sonic Zhang06051fd2012-07-04 19:22:55 +0800527}
Sonic Zhang86794b42012-12-14 11:19:24 +0800528#endif /* SEC_GCTL */
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800529
Bryan Wu1394f032007-05-06 14:50:22 -0700530static struct irq_chip bfin_core_irqchip = {
Graf Yang763e63c2008-10-08 17:08:15 +0800531 .name = "CORE",
Thomas Gleixner4f19ea42011-02-06 18:23:27 +0000532 .irq_mask = bfin_core_mask_irq,
533 .irq_unmask = bfin_core_unmask_irq,
Bryan Wu1394f032007-05-06 14:50:22 -0700534};
535
Sonic Zhang86794b42012-12-14 11:19:24 +0800536#ifndef SEC_GCTL
Bryan Wu1394f032007-05-06 14:50:22 -0700537static struct irq_chip bfin_internal_irqchip = {
Graf Yang763e63c2008-10-08 17:08:15 +0800538 .name = "INTN",
Thomas Gleixnerff43a672011-02-06 18:23:29 +0000539 .irq_mask = bfin_internal_mask_irq_chip,
540 .irq_unmask = bfin_internal_unmask_irq_chip,
Thomas Gleixnerff43a672011-02-06 18:23:29 +0000541 .irq_disable = bfin_internal_mask_irq_chip,
542 .irq_enable = bfin_internal_unmask_irq_chip,
Sonic Zhang0325f252009-12-28 07:29:57 +0000543#ifdef CONFIG_SMP
Thomas Gleixnerff43a672011-02-06 18:23:29 +0000544 .irq_set_affinity = bfin_internal_set_affinity,
Sonic Zhang0325f252009-12-28 07:29:57 +0000545#endif
Thomas Gleixnerff43a672011-02-06 18:23:29 +0000546 .irq_set_wake = bfin_internal_set_wake_chip,
Bryan Wu1394f032007-05-06 14:50:22 -0700547};
Sonic Zhang86794b42012-12-14 11:19:24 +0800548#else
Steven Miao4f6b6002012-05-16 17:56:51 +0800549static struct irq_chip bfin_sec_irqchip = {
550 .name = "SEC",
551 .irq_mask_ack = bfin_sec_mask_ack_irq,
552 .irq_mask = bfin_sec_mask_ack_irq,
553 .irq_unmask = bfin_sec_unmask_irq,
554 .irq_eoi = bfin_sec_unmask_irq,
555 .irq_disable = bfin_sec_disable,
556 .irq_enable = bfin_sec_enable,
557};
558#endif
559
Mike Frysingerf58c3272011-04-15 03:08:20 -0400560void bfin_handle_irq(unsigned irq)
Yi Li6a01f232009-01-07 23:14:39 +0800561{
562#ifdef CONFIG_IPIPE
563 struct pt_regs regs; /* Contents not used. */
564 ipipe_trace_irq_entry(irq);
565 __ipipe_handle_irq(irq, &regs);
566 ipipe_trace_irq_exit(irq);
567#else /* !CONFIG_IPIPE */
Thomas Gleixnerb10bbbb2011-02-06 18:23:25 +0000568 generic_handle_irq(irq);
Yi Li6a01f232009-01-07 23:14:39 +0800569#endif /* !CONFIG_IPIPE */
570}
571
Michael Hennerichaec59c92010-02-19 15:09:10 +0000572#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
573static int mac_stat_int_mask;
574
575static void bfin_mac_status_ack_irq(unsigned int irq)
576{
577 switch (irq) {
578 case IRQ_MAC_MMCINT:
579 bfin_write_EMAC_MMC_TIRQS(
580 bfin_read_EMAC_MMC_TIRQE() &
581 bfin_read_EMAC_MMC_TIRQS());
582 bfin_write_EMAC_MMC_RIRQS(
583 bfin_read_EMAC_MMC_RIRQE() &
584 bfin_read_EMAC_MMC_RIRQS());
585 break;
586 case IRQ_MAC_RXFSINT:
587 bfin_write_EMAC_RX_STKY(
588 bfin_read_EMAC_RX_IRQE() &
589 bfin_read_EMAC_RX_STKY());
590 break;
591 case IRQ_MAC_TXFSINT:
592 bfin_write_EMAC_TX_STKY(
593 bfin_read_EMAC_TX_IRQE() &
594 bfin_read_EMAC_TX_STKY());
595 break;
596 case IRQ_MAC_WAKEDET:
597 bfin_write_EMAC_WKUP_CTL(
598 bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
599 break;
600 default:
601 /* These bits are W1C */
602 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
603 break;
604 }
605}
606
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000607static void bfin_mac_status_mask_irq(struct irq_data *d)
Michael Hennerichaec59c92010-02-19 15:09:10 +0000608{
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000609 unsigned int irq = d->irq;
610
Michael Hennerichaec59c92010-02-19 15:09:10 +0000611 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
Mike Frysingerf58c3272011-04-15 03:08:20 -0400612#ifdef BF537_FAMILY
Michael Hennerichaec59c92010-02-19 15:09:10 +0000613 switch (irq) {
614 case IRQ_MAC_PHYINT:
615 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
616 break;
617 default:
618 break;
619 }
620#else
621 if (!mac_stat_int_mask)
622 bfin_internal_mask_irq(IRQ_MAC_ERROR);
623#endif
624 bfin_mac_status_ack_irq(irq);
625}
626
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000627static void bfin_mac_status_unmask_irq(struct irq_data *d)
Michael Hennerichaec59c92010-02-19 15:09:10 +0000628{
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000629 unsigned int irq = d->irq;
630
Mike Frysingerf58c3272011-04-15 03:08:20 -0400631#ifdef BF537_FAMILY
Michael Hennerichaec59c92010-02-19 15:09:10 +0000632 switch (irq) {
633 case IRQ_MAC_PHYINT:
634 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
635 break;
636 default:
637 break;
638 }
639#else
640 if (!mac_stat_int_mask)
641 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
642#endif
643 mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
644}
645
646#ifdef CONFIG_PM
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000647int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
Michael Hennerichaec59c92010-02-19 15:09:10 +0000648{
Mike Frysingerf58c3272011-04-15 03:08:20 -0400649#ifdef BF537_FAMILY
Michael Hennerichaec59c92010-02-19 15:09:10 +0000650 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
651#else
652 return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
653#endif
654}
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400655#else
656# define bfin_mac_status_set_wake NULL
Michael Hennerichaec59c92010-02-19 15:09:10 +0000657#endif
658
659static struct irq_chip bfin_mac_status_irqchip = {
660 .name = "MACST",
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000661 .irq_mask = bfin_mac_status_mask_irq,
662 .irq_unmask = bfin_mac_status_unmask_irq,
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000663 .irq_set_wake = bfin_mac_status_set_wake,
Michael Hennerichaec59c92010-02-19 15:09:10 +0000664};
665
Mike Frysingerf58c3272011-04-15 03:08:20 -0400666void bfin_demux_mac_status_irq(unsigned int int_err_irq,
667 struct irq_desc *inta_desc)
Michael Hennerichaec59c92010-02-19 15:09:10 +0000668{
669 int i, irq = 0;
670 u32 status = bfin_read_EMAC_SYSTAT();
671
Michael Hennerichbedeea62010-08-20 11:59:27 +0000672 for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
Michael Hennerichaec59c92010-02-19 15:09:10 +0000673 if (status & (1L << i)) {
674 irq = IRQ_MAC_PHYINT + i;
675 break;
676 }
677
678 if (irq) {
679 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
680 bfin_handle_irq(irq);
681 } else {
682 bfin_mac_status_ack_irq(irq);
683 pr_debug("IRQ %d:"
Steven Miao4f6b6002012-05-16 17:56:51 +0800684 " MASKED MAC ERROR INTERRUPT ASSERTED\n",
685 irq);
Michael Hennerichaec59c92010-02-19 15:09:10 +0000686 }
687 } else
688 printk(KERN_ERR
Steven Miao4f6b6002012-05-16 17:56:51 +0800689 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
690 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
691 "(EMAC_SYSTAT=0x%X)\n",
692 __func__, __FILE__, __LINE__, status);
Michael Hennerichaec59c92010-02-19 15:09:10 +0000693}
694#endif
695
Graf Yangbfd15112008-10-08 18:02:44 +0800696static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
697{
Yi Li6a01f232009-01-07 23:14:39 +0800698#ifdef CONFIG_IPIPE
Philippe Gerum5b5da4c2011-03-17 02:12:48 -0400699 handle = handle_level_irq;
Yi Li6a01f232009-01-07 23:14:39 +0800700#endif
Thomas Gleixner43f2f112011-03-24 17:22:30 +0100701 __irq_set_handler_locked(irq, handle);
Graf Yangbfd15112008-10-08 18:02:44 +0800702}
703
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800704#ifdef CONFIG_GPIO_ADI
Michael Hennerich6fce6a82007-12-24 16:56:12 +0800705
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800706static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
Michael Hennerich8d022372008-11-18 17:48:22 +0800707
Thomas Gleixnere9502852011-02-06 18:23:36 +0000708static void bfin_gpio_ack_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700709{
Michael Hennerich8d022372008-11-18 17:48:22 +0800710 /* AFAIK ack_irq in case mask_ack is provided
711 * get's only called for edge sense irqs
712 */
Thomas Gleixnere9502852011-02-06 18:23:36 +0000713 set_gpio_data(irq_to_gpio(d->irq), 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700714}
715
Thomas Gleixnere9502852011-02-06 18:23:36 +0000716static void bfin_gpio_mask_ack_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700717{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000718 unsigned int irq = d->irq;
Michael Hennerich8d022372008-11-18 17:48:22 +0800719 u32 gpionr = irq_to_gpio(irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700720
Thomas Gleixner1907d8b2011-03-24 17:21:01 +0100721 if (!irqd_is_level_type(d))
Bryan Wu1394f032007-05-06 14:50:22 -0700722 set_gpio_data(gpionr, 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700723
724 set_gpio_maska(gpionr, 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700725}
726
Thomas Gleixnere9502852011-02-06 18:23:36 +0000727static void bfin_gpio_mask_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700728{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000729 set_gpio_maska(irq_to_gpio(d->irq), 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700730}
731
Thomas Gleixnere9502852011-02-06 18:23:36 +0000732static void bfin_gpio_unmask_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700733{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000734 set_gpio_maska(irq_to_gpio(d->irq), 1);
Bryan Wu1394f032007-05-06 14:50:22 -0700735}
736
Thomas Gleixnere9502852011-02-06 18:23:36 +0000737static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700738{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000739 u32 gpionr = irq_to_gpio(d->irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700740
Michael Hennerich8d022372008-11-18 17:48:22 +0800741 if (__test_and_set_bit(gpionr, gpio_enabled))
Michael Hennerichaffee2b2008-04-24 08:10:10 +0800742 bfin_gpio_irq_prepare(gpionr);
Bryan Wu1394f032007-05-06 14:50:22 -0700743
Thomas Gleixnere9502852011-02-06 18:23:36 +0000744 bfin_gpio_unmask_irq(d);
Bryan Wu1394f032007-05-06 14:50:22 -0700745
Michael Hennerichaffee2b2008-04-24 08:10:10 +0800746 return 0;
Bryan Wu1394f032007-05-06 14:50:22 -0700747}
748
Thomas Gleixnere9502852011-02-06 18:23:36 +0000749static void bfin_gpio_irq_shutdown(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700750{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000751 u32 gpionr = irq_to_gpio(d->irq);
Graf Yang30af6d42008-11-18 17:48:21 +0800752
Thomas Gleixnere9502852011-02-06 18:23:36 +0000753 bfin_gpio_mask_irq(d);
Graf Yang30af6d42008-11-18 17:48:21 +0800754 __clear_bit(gpionr, gpio_enabled);
Graf Yang9570ff42009-01-07 23:14:38 +0800755 bfin_gpio_irq_free(gpionr);
Bryan Wu1394f032007-05-06 14:50:22 -0700756}
757
Thomas Gleixnere9502852011-02-06 18:23:36 +0000758static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
Bryan Wu1394f032007-05-06 14:50:22 -0700759{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000760 unsigned int irq = d->irq;
Graf Yang8eb3e3b2008-11-18 17:48:22 +0800761 int ret;
762 char buf[16];
Michael Hennerich8d022372008-11-18 17:48:22 +0800763 u32 gpionr = irq_to_gpio(irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700764
765 if (type == IRQ_TYPE_PROBE) {
766 /* only probe unenabled GPIO interrupt lines */
Mike Frysingerc3695342009-06-13 10:32:29 -0400767 if (test_bit(gpionr, gpio_enabled))
Bryan Wu1394f032007-05-06 14:50:22 -0700768 return 0;
769 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
770 }
771
772 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800773 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
Michael Hennerich8d022372008-11-18 17:48:22 +0800774
Graf Yang9570ff42009-01-07 23:14:38 +0800775 snprintf(buf, 16, "gpio-irq%d", irq);
776 ret = bfin_gpio_irq_request(gpionr, buf);
777 if (ret)
778 return ret;
779
Michael Hennerich8d022372008-11-18 17:48:22 +0800780 if (__test_and_set_bit(gpionr, gpio_enabled))
Michael Hennerichaffee2b2008-04-24 08:10:10 +0800781 bfin_gpio_irq_prepare(gpionr);
Bryan Wu1394f032007-05-06 14:50:22 -0700782
Bryan Wu1394f032007-05-06 14:50:22 -0700783 } else {
Michael Hennerich8d022372008-11-18 17:48:22 +0800784 __clear_bit(gpionr, gpio_enabled);
Bryan Wu1394f032007-05-06 14:50:22 -0700785 return 0;
786 }
787
Michael Hennerichf1bceb42008-02-02 16:17:52 +0800788 set_gpio_inen(gpionr, 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700789 set_gpio_dir(gpionr, 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700790
791 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
792 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
793 set_gpio_both(gpionr, 1);
794 else
795 set_gpio_both(gpionr, 0);
796
797 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
798 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
799 else
800 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
801
Michael Hennerichf1bceb42008-02-02 16:17:52 +0800802 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
803 set_gpio_edge(gpionr, 1);
804 set_gpio_inen(gpionr, 1);
Michael Hennerichf1bceb42008-02-02 16:17:52 +0800805 set_gpio_data(gpionr, 0);
806
807 } else {
808 set_gpio_edge(gpionr, 0);
Michael Hennerichf1bceb42008-02-02 16:17:52 +0800809 set_gpio_inen(gpionr, 1);
810 }
811
Bryan Wu1394f032007-05-06 14:50:22 -0700812 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
Graf Yangbfd15112008-10-08 18:02:44 +0800813 bfin_set_irq_handler(irq, handle_edge_irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700814 else
Graf Yangbfd15112008-10-08 18:02:44 +0800815 bfin_set_irq_handler(irq, handle_level_irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700816
817 return 0;
818}
819
Mike Frysingere2a80922011-04-15 12:51:33 -0400820static void bfin_demux_gpio_block(unsigned int irq)
821{
822 unsigned int gpio, mask;
823
824 gpio = irq_to_gpio(irq);
825 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
826
827 while (mask) {
828 if (mask & 1)
829 bfin_handle_irq(irq);
830 irq++;
831 mask >>= 1;
832 }
833}
834
Mike Frysinger8c054102011-04-15 13:04:59 -0400835void bfin_demux_gpio_irq(unsigned int inta_irq,
Steven Miao4f6b6002012-05-16 17:56:51 +0800836 struct irq_desc *desc)
Bryan Wu1394f032007-05-06 14:50:22 -0700837{
Mike Frysingere2a80922011-04-15 12:51:33 -0400838 unsigned int irq;
Bryan Wu1394f032007-05-06 14:50:22 -0700839
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800840 switch (inta_irq) {
Mike Frysingere2a80922011-04-15 12:51:33 -0400841#if defined(BF537_FAMILY)
Mike Frysinger8c054102011-04-15 13:04:59 -0400842 case IRQ_PF_INTA_PG_INTA:
Mike Frysingere2a80922011-04-15 12:51:33 -0400843 bfin_demux_gpio_block(IRQ_PF0);
844 irq = IRQ_PG0;
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800845 break;
Mike Frysinger8c054102011-04-15 13:04:59 -0400846 case IRQ_PH_INTA_MAC_RX:
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800847 irq = IRQ_PH0;
848 break;
Mike Frysingere2a80922011-04-15 12:51:33 -0400849#elif defined(BF533_FAMILY)
850 case IRQ_PROG_INTA:
851 irq = IRQ_PF0;
852 break;
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400853#elif defined(BF538_FAMILY)
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800854 case IRQ_PORTF_INTA:
855 irq = IRQ_PF0;
856 break;
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800857#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800858 case IRQ_PORTF_INTA:
859 irq = IRQ_PF0;
860 break;
861 case IRQ_PORTG_INTA:
862 irq = IRQ_PG0;
863 break;
864 case IRQ_PORTH_INTA:
865 irq = IRQ_PH0;
866 break;
867#elif defined(CONFIG_BF561)
868 case IRQ_PROG0_INTA:
869 irq = IRQ_PF0;
870 break;
871 case IRQ_PROG1_INTA:
872 irq = IRQ_PF16;
873 break;
874 case IRQ_PROG2_INTA:
875 irq = IRQ_PF32;
876 break;
877#endif
878 default:
879 BUG();
880 return;
Bryan Wu1394f032007-05-06 14:50:22 -0700881 }
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800882
Mike Frysingere2a80922011-04-15 12:51:33 -0400883 bfin_demux_gpio_block(irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700884}
885
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800886#ifdef CONFIG_PM
Steven Miaod49cdf8402012-06-14 18:04:01 +0800887
Mike Frysingerdd8cb372011-04-15 03:19:22 -0400888static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800889{
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800890 return bfin_gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
891}
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800892
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800893#else
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800894
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800895# define bfin_gpio_set_wake NULL
896
Sonic Zhang86794b42012-12-14 11:19:24 +0800897#endif
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800898
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800899static struct irq_chip bfin_gpio_irqchip = {
900 .name = "GPIO",
901 .irq_ack = bfin_gpio_ack_irq,
902 .irq_mask = bfin_gpio_mask_irq,
903 .irq_mask_ack = bfin_gpio_mask_ack_irq,
904 .irq_unmask = bfin_gpio_unmask_irq,
905 .irq_disable = bfin_gpio_mask_irq,
906 .irq_enable = bfin_gpio_unmask_irq,
907 .irq_set_type = bfin_gpio_irq_type,
908 .irq_startup = bfin_gpio_irq_startup,
909 .irq_shutdown = bfin_gpio_irq_shutdown,
910 .irq_set_wake = bfin_gpio_set_wake,
911};
Steven Miaod49cdf8402012-06-14 18:04:01 +0800912
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800913#endif
Steven Miaod49cdf8402012-06-14 18:04:01 +0800914
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800915#ifdef CONFIG_PM
Steven Miaod49cdf8402012-06-14 18:04:01 +0800916
Sonic Zhang11b27cb2012-06-28 19:16:48 +0800917#ifdef SEC_GCTL
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800918static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
919
Steven Miaod49cdf8402012-06-14 18:04:01 +0800920static int sec_suspend(void)
921{
922 u32 bank;
923
924 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
Sonic Zhang86794b42012-12-14 11:19:24 +0800925 save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0));
Steven Miaod49cdf8402012-06-14 18:04:01 +0800926 return 0;
927}
928
929static void sec_resume(void)
930{
931 u32 bank;
932
933 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
934 udelay(100);
935 bfin_write_SEC_GCTL(SEC_GCTL_EN);
936 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
937
938 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
Sonic Zhang86794b42012-12-14 11:19:24 +0800939 bfin_write_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
Steven Miaod49cdf8402012-06-14 18:04:01 +0800940}
941
942static struct syscore_ops sec_pm_syscore_ops = {
943 .suspend = sec_suspend,
944 .resume = sec_resume,
945};
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800946#endif
947
Steven Miao4f6b6002012-05-16 17:56:51 +0800948#endif
Michael Hennerich8d022372008-11-18 17:48:22 +0800949
Paul Gortmaker13dff622013-06-18 16:56:21 -0400950void init_exception_vectors(void)
Bernd Schmidt8be80ed2007-07-25 14:44:49 +0800951{
Mike Frysingerf0b5d122007-08-05 17:03:59 +0800952 /* cannot program in software:
953 * evt0 - emulation (jtag)
954 * evt1 - reset
955 */
956 bfin_write_EVT2(evt_nmi);
Bernd Schmidt8be80ed2007-07-25 14:44:49 +0800957 bfin_write_EVT3(trap);
958 bfin_write_EVT5(evt_ivhw);
959 bfin_write_EVT6(evt_timer);
960 bfin_write_EVT7(evt_evt7);
961 bfin_write_EVT8(evt_evt8);
962 bfin_write_EVT9(evt_evt9);
963 bfin_write_EVT10(evt_evt10);
964 bfin_write_EVT11(evt_evt11);
965 bfin_write_EVT12(evt_evt12);
966 bfin_write_EVT13(evt_evt13);
Philippe Gerum9703a732009-06-22 18:23:48 +0200967 bfin_write_EVT14(evt_evt14);
Bernd Schmidt8be80ed2007-07-25 14:44:49 +0800968 bfin_write_EVT15(evt_system_call);
969 CSYNC();
970}
971
Sonic Zhang11b27cb2012-06-28 19:16:48 +0800972#ifndef SEC_GCTL
Bryan Wu1394f032007-05-06 14:50:22 -0700973/*
974 * This function should be called during kernel startup to initialize
975 * the BFin IRQ handling routines.
976 */
Michael Hennerich8d022372008-11-18 17:48:22 +0800977
Bryan Wu1394f032007-05-06 14:50:22 -0700978int __init init_arch_irq(void)
979{
980 int irq;
981 unsigned long ilat = 0;
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400982
Bryan Wu1394f032007-05-06 14:50:22 -0700983 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400984#ifdef SIC_IMASK0
Roy Huang24a07a12007-07-12 22:41:45 +0800985 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
986 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400987# ifdef SIC_IMASK2
Michael Hennerich59003142007-10-21 16:54:27 +0800988 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
Mike Frysingera055b2b2007-11-15 21:12:32 +0800989# endif
Steven Miao4f6b6002012-05-16 17:56:51 +0800990# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
Graf Yang6b3087c2009-01-07 23:14:39 +0800991 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
992 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
993# endif
Roy Huang24a07a12007-07-12 22:41:45 +0800994#else
Bryan Wu1394f032007-05-06 14:50:22 -0700995 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
Roy Huang24a07a12007-07-12 22:41:45 +0800996#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700997
998 local_irq_disable();
999
Michael Hennerich34e0fc82007-07-12 16:17:18 +08001000 for (irq = 0; irq <= SYS_IRQS; irq++) {
Bryan Wu1394f032007-05-06 14:50:22 -07001001 if (irq <= IRQ_CORETMR)
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001002 irq_set_chip(irq, &bfin_core_irqchip);
Bryan Wu1394f032007-05-06 14:50:22 -07001003 else
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001004 irq_set_chip(irq, &bfin_internal_irqchip);
Bryan Wu1394f032007-05-06 14:50:22 -07001005
Michael Hennerich464abc52008-02-25 13:50:20 +08001006 switch (irq) {
Sonic Zhang54e4ff42013-05-30 18:37:28 +08001007#if !BFIN_GPIO_PINT
1008#if defined(BF537_FAMILY)
Mike Frysinger01f8e342011-06-26 13:56:23 -04001009 case IRQ_PH_INTA_MAC_RX:
1010 case IRQ_PF_INTA_PG_INTA:
1011#elif defined(BF533_FAMILY)
1012 case IRQ_PROG_INTA:
Bryan Wu2f6f4bc2008-11-18 17:48:21 +08001013#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
Michael Hennerich464abc52008-02-25 13:50:20 +08001014 case IRQ_PORTF_INTA:
1015 case IRQ_PORTG_INTA:
1016 case IRQ_PORTH_INTA:
Michael Hennerich2c4f8292008-02-09 04:11:14 +08001017#elif defined(CONFIG_BF561)
Michael Hennerich464abc52008-02-25 13:50:20 +08001018 case IRQ_PROG0_INTA:
1019 case IRQ_PROG1_INTA:
1020 case IRQ_PROG2_INTA:
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -04001021#elif defined(BF538_FAMILY)
Michael Hennerichdc26aec2008-11-18 17:48:22 +08001022 case IRQ_PORTF_INTA:
Michael Hennerich59003142007-10-21 16:54:27 +08001023#endif
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001024 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
Michael Hennerich464abc52008-02-25 13:50:20 +08001025 break;
Sonic Zhang54e4ff42013-05-30 18:37:28 +08001026#endif
Michael Hennerichaec59c92010-02-19 15:09:10 +00001027#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1028 case IRQ_MAC_ERROR:
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001029 irq_set_chained_handler(irq,
1030 bfin_demux_mac_status_irq);
Michael Hennerichaec59c92010-02-19 15:09:10 +00001031 break;
1032#endif
Steven Miao4f6b6002012-05-16 17:56:51 +08001033#if defined(CONFIG_SMP) || defined(CONFIG_ICC)
Graf Yang6b3087c2009-01-07 23:14:39 +08001034 case IRQ_SUPPLE_0:
1035 case IRQ_SUPPLE_1:
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001036 irq_set_handler(irq, handle_percpu_irq);
Graf Yang6b3087c2009-01-07 23:14:39 +08001037 break;
1038#endif
Graf Yang179413142009-08-18 04:29:33 +00001039
Yi Licb191712009-12-30 07:12:50 +00001040#ifdef CONFIG_TICKSOURCE_CORETMR
1041 case IRQ_CORETMR:
1042# ifdef CONFIG_SMP
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001043 irq_set_handler(irq, handle_percpu_irq);
Yi Licb191712009-12-30 07:12:50 +00001044# else
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001045 irq_set_handler(irq, handle_simple_irq);
Yi Licb191712009-12-30 07:12:50 +00001046# endif
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -04001047 break;
Yi Licb191712009-12-30 07:12:50 +00001048#endif
1049
1050#ifdef CONFIG_TICKSOURCE_GPTMR0
Philippe Geruma40494a2009-06-16 05:25:42 +02001051 case IRQ_TIMER0:
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001052 irq_set_handler(irq, handle_simple_irq);
Michael Hennerich464abc52008-02-25 13:50:20 +08001053 break;
Graf Yang179413142009-08-18 04:29:33 +00001054#endif
Yi Licb191712009-12-30 07:12:50 +00001055
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -04001056 default:
Yi Licb191712009-12-30 07:12:50 +00001057#ifdef CONFIG_IPIPE
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001058 irq_set_handler(irq, handle_level_irq);
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -04001059#else
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001060 irq_set_handler(irq, handle_simple_irq);
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -04001061#endif
Philippe Geruma40494a2009-06-16 05:25:42 +02001062 break;
Bryan Wu1394f032007-05-06 14:50:22 -07001063 }
Bryan Wu1394f032007-05-06 14:50:22 -07001064 }
Michael Hennerich464abc52008-02-25 13:50:20 +08001065
Mike Frysingerf58c3272011-04-15 03:08:20 -04001066 init_mach_irq();
Bryan Wu1394f032007-05-06 14:50:22 -07001067
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001068#if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
Michael Hennerichaec59c92010-02-19 15:09:10 +00001069 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001070 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
Michael Hennerichaec59c92010-02-19 15:09:10 +00001071 handle_level_irq);
1072#endif
Michael Hennerich464abc52008-02-25 13:50:20 +08001073 /* if configured as edge, then will be changed to do_edge_IRQ */
Sonic Zhang54e4ff42013-05-30 18:37:28 +08001074#ifdef CONFIG_GPIO_ADI
Michael Hennerichaec59c92010-02-19 15:09:10 +00001075 for (irq = GPIO_IRQ_BASE;
1076 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001077 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
Michael Hennerich464abc52008-02-25 13:50:20 +08001078 handle_level_irq);
Sonic Zhang54e4ff42013-05-30 18:37:28 +08001079#endif
Bryan Wu1394f032007-05-06 14:50:22 -07001080 bfin_write_IMASK(0);
1081 CSYNC();
1082 ilat = bfin_read_ILAT();
1083 CSYNC();
1084 bfin_write_ILAT(ilat);
1085 CSYNC();
1086
Michael Hennerich34e0fc82007-07-12 16:17:18 +08001087 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
Mike Frysinger40059782008-11-18 17:48:22 +08001088 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
Bryan Wu1394f032007-05-06 14:50:22 -07001089 * local_irq_enable()
1090 */
1091 program_IAR();
1092 /* Therefore it's better to setup IARs before interrupts enabled */
1093 search_IAR();
1094
1095 /* Enable interrupts IVG7-15 */
Mike Frysinger40059782008-11-18 17:48:22 +08001096 bfin_irq_flags |= IMASK_IVG15 |
Steven Miao4f6b6002012-05-16 17:56:51 +08001097 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1098 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1099
Bryan Wu1394f032007-05-06 14:50:22 -07001100
Michael Hennerich349ebbc2009-04-15 08:48:08 +00001101 /* This implicitly covers ANOMALY_05000171
1102 * Boot-ROM code modifies SICA_IWRx wakeup registers
1103 */
Mike Frysingerbe1d8542009-02-04 16:49:45 +08001104#ifdef SIC_IWR0
Michael Hennerich56f5f592008-08-06 17:55:32 +08001105 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
Mike Frysingerbe1d8542009-02-04 16:49:45 +08001106# ifdef SIC_IWR1
Bryan Wu2f6f4bc2008-11-18 17:48:21 +08001107 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
Michael Hennerich55546ac2008-08-13 17:41:13 +08001108 * will screw up the bootrom as it relies on MDMA0/1 waking it
1109 * up from IDLE instructions. See this report for more info:
1110 * http://blackfin.uclinux.org/gf/tracker/4323
1111 */
Mike Frysingerb7e11292008-11-18 17:48:22 +08001112 if (ANOMALY_05000435)
1113 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1114 else
1115 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
Mike Frysingerbe1d8542009-02-04 16:49:45 +08001116# endif
1117# ifdef SIC_IWR2
Michael Hennerich56f5f592008-08-06 17:55:32 +08001118 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
Michael Hennerichfe9ec9b2008-02-25 12:04:57 +08001119# endif
1120#else
Michael Hennerich56f5f592008-08-06 17:55:32 +08001121 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
Michael Hennerichfe9ec9b2008-02-25 12:04:57 +08001122#endif
Bryan Wu1394f032007-05-06 14:50:22 -07001123 return 0;
1124}
1125
1126#ifdef CONFIG_DO_IRQ_L1
Mike Frysingera055b2b2007-11-15 21:12:32 +08001127__attribute__((l1_text))
Bryan Wu1394f032007-05-06 14:50:22 -07001128#endif
Mike Frysinger6b108042011-03-30 01:35:41 -04001129static int vec_to_irq(int vec)
1130{
1131 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1132 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1133 unsigned long sic_status[3];
Mike Frysinger6b108042011-03-30 01:35:41 -04001134 if (likely(vec == EVT_IVTMR_P))
1135 return IRQ_CORETMR;
Mike Frysinger6b108042011-03-30 01:35:41 -04001136#ifdef SIC_ISR
1137 sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1138#else
1139 if (smp_processor_id()) {
1140# ifdef SICB_ISR0
1141 /* This will be optimized out in UP mode. */
1142 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1143 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1144# endif
1145 } else {
1146 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1147 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1148 }
1149#endif
1150#ifdef SIC_ISR2
1151 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1152#endif
1153
1154 for (;; ivg++) {
1155 if (ivg >= ivg_stop)
1156 return -1;
1157#ifdef SIC_ISR
1158 if (sic_status[0] & ivg->isrflag)
1159#else
1160 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1161#endif
1162 return ivg->irqno;
1163 }
1164}
1165
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001166#else /* SEC_GCTL */
1167
1168/*
1169 * This function should be called during kernel startup to initialize
1170 * the BFin IRQ handling routines.
1171 */
1172
1173int __init init_arch_irq(void)
1174{
1175 int irq;
1176 unsigned long ilat = 0;
1177
1178 bfin_write_SEC_GCTL(SEC_GCTL_RESET);
1179
1180 local_irq_disable();
1181
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001182 for (irq = 0; irq <= SYS_IRQS; irq++) {
1183 if (irq <= IRQ_CORETMR) {
Sonic Zhang86794b42012-12-14 11:19:24 +08001184 irq_set_chip_and_handler(irq, &bfin_core_irqchip,
1185 handle_simple_irq);
1186#if defined(CONFIG_TICKSOURCE_CORETMR) && defined(CONFIG_SMP)
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001187 if (irq == IRQ_CORETMR)
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001188 irq_set_handler(irq, handle_percpu_irq);
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001189#endif
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001190 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001191 irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
Sonic Zhang86794b42012-12-14 11:19:24 +08001192 handle_percpu_irq);
1193 } else {
1194 irq_set_chip(irq, &bfin_sec_irqchip);
Sonic Zhang1b601232013-12-04 15:27:47 +08001195 irq_set_handler(irq, handle_fasteoi_irq);
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001196 __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
1197 }
1198 }
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001199
1200 bfin_write_IMASK(0);
1201 CSYNC();
1202 ilat = bfin_read_ILAT();
1203 CSYNC();
1204 bfin_write_ILAT(ilat);
1205 CSYNC();
1206
1207 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1208
Sonic Zhange0a59312012-06-29 18:19:29 +08001209 bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
1210
1211 bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
1212
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001213 /* Enable interrupts IVG7-15 */
1214 bfin_irq_flags |= IMASK_IVG15 |
1215 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1216 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1217
1218
1219 bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
Sonic Zhang86794b42012-12-14 11:19:24 +08001220 bfin_sec_enable_sci(BFIN_SYSIRQ(IRQ_WATCH0));
1221 bfin_sec_enable_ssi(BFIN_SYSIRQ(IRQ_WATCH0));
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001222 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1223 udelay(100);
1224 bfin_write_SEC_GCTL(SEC_GCTL_EN);
1225 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1226 bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1227
1228 init_software_driven_irq();
Steven Miao36c47232012-12-21 14:34:16 +08001229
1230#ifdef CONFIG_PM
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001231 register_syscore_ops(&sec_pm_syscore_ops);
Steven Miao36c47232012-12-21 14:34:16 +08001232#endif
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001233
Sonic Zhang1b601232013-12-04 15:27:47 +08001234 bfin_fault_irq.handler = bfin_fault_routine;
1235#ifdef CONFIG_L1_PARITY_CHECK
1236 setup_irq(IRQ_C0_NMI_L1_PARITY_ERR, &bfin_fault_irq);
1237#endif
1238 setup_irq(IRQ_C0_DBL_FAULT, &bfin_fault_irq);
1239 setup_irq(IRQ_SEC_ERR, &bfin_fault_irq);
1240
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001241 return 0;
1242}
1243
1244#ifdef CONFIG_DO_IRQ_L1
1245__attribute__((l1_text))
1246#endif
1247static int vec_to_irq(int vec)
1248{
1249 if (likely(vec == EVT_IVTMR_P))
1250 return IRQ_CORETMR;
1251
1252 return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
1253}
1254#endif /* SEC_GCTL */
1255
Mike Frysinger6b108042011-03-30 01:35:41 -04001256#ifdef CONFIG_DO_IRQ_L1
1257__attribute__((l1_text))
1258#endif
Bryan Wu1394f032007-05-06 14:50:22 -07001259void do_irq(int vec, struct pt_regs *fp)
1260{
Mike Frysinger6b108042011-03-30 01:35:41 -04001261 int irq = vec_to_irq(vec);
1262 if (irq == -1)
1263 return;
1264 asm_do_IRQ(irq, fp);
Bryan Wu1394f032007-05-06 14:50:22 -07001265}
Yi Li6a01f232009-01-07 23:14:39 +08001266
1267#ifdef CONFIG_IPIPE
1268
1269int __ipipe_get_irq_priority(unsigned irq)
1270{
1271 int ient, prio;
1272
1273 if (irq <= IRQ_CORETMR)
1274 return irq;
1275
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001276#ifdef SEC_GCTL
1277 if (irq >= BFIN_IRQ(0))
1278 return IVG11;
1279#else
Yi Li6a01f232009-01-07 23:14:39 +08001280 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1281 struct ivgx *ivg = ivg_table + ient;
1282 if (ivg->irqno == irq) {
1283 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1284 if (ivg7_13[prio].ifirst <= ivg &&
1285 ivg7_13[prio].istop > ivg)
1286 return IVG7 + prio;
1287 }
1288 }
1289 }
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001290#endif
Yi Li6a01f232009-01-07 23:14:39 +08001291
1292 return IVG15;
1293}
1294
Yi Li6a01f232009-01-07 23:14:39 +08001295/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1296#ifdef CONFIG_DO_IRQ_L1
1297__attribute__((l1_text))
1298#endif
1299asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1300{
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001301 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
Philippe Geruma40494a2009-06-16 05:25:42 +02001302 struct ipipe_domain *this_domain = __ipipe_current_domain;
Philippe Gerum5b5da4c2011-03-17 02:12:48 -04001303 int irq, s = 0;
Yi Li6a01f232009-01-07 23:14:39 +08001304
Mike Frysinger6b108042011-03-30 01:35:41 -04001305 irq = vec_to_irq(vec);
1306 if (irq == -1)
1307 return 0;
Yi Li6a01f232009-01-07 23:14:39 +08001308
1309 if (irq == IRQ_SYSTMR) {
Philippe Geruma40494a2009-06-16 05:25:42 +02001310#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
Yi Li6a01f232009-01-07 23:14:39 +08001311 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001312#endif
Yi Li6a01f232009-01-07 23:14:39 +08001313 /* This is basically what we need from the register frame. */
1314 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1315 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001316 if (this_domain != ipipe_root_domain)
Yi Li6a01f232009-01-07 23:14:39 +08001317 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001318 else
1319 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
Yi Li6a01f232009-01-07 23:14:39 +08001320 }
1321
Philippe Gerum5b5da4c2011-03-17 02:12:48 -04001322 /*
1323 * We don't want Linux interrupt handlers to run at the
1324 * current core priority level (i.e. < EVT15), since this
1325 * might delay other interrupts handled by a high priority
1326 * domain. Here is what we do instead:
1327 *
1328 * - we raise the SYNCDEFER bit to prevent
1329 * __ipipe_handle_irq() to sync the pipeline for the root
1330 * stage for the incoming interrupt. Upon return, that IRQ is
1331 * pending in the interrupt log.
1332 *
1333 * - we raise the TIF_IRQ_SYNC bit for the current thread, so
1334 * that _schedule_and_signal_from_int will eventually sync the
1335 * pipeline from EVT15.
1336 */
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001337 if (this_domain == ipipe_root_domain) {
1338 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1339 barrier();
1340 }
Yi Li6a01f232009-01-07 23:14:39 +08001341
1342 ipipe_trace_irq_entry(irq);
1343 __ipipe_handle_irq(irq, regs);
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001344 ipipe_trace_irq_exit(irq);
Yi Li6a01f232009-01-07 23:14:39 +08001345
Philippe Gerum5b5da4c2011-03-17 02:12:48 -04001346 if (user_mode(regs) &&
1347 !ipipe_test_foreign_stack() &&
1348 (current->ipipe_flags & PF_EVTRET) != 0) {
1349 /*
1350 * Testing for user_regs() does NOT fully eliminate
1351 * foreign stack contexts, because of the forged
1352 * interrupt returns we do through
1353 * __ipipe_call_irqtail. In that case, we might have
1354 * preempted a foreign stack context in a high
1355 * priority domain, with a single interrupt level now
1356 * pending after the irqtail unwinding is done. In
1357 * which case user_mode() is now true, and the event
1358 * gets dispatched spuriously.
1359 */
1360 current->ipipe_flags &= ~PF_EVTRET;
1361 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
1362 }
1363
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001364 if (this_domain == ipipe_root_domain) {
1365 set_thread_flag(TIF_IRQ_SYNC);
1366 if (!s) {
1367 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1368 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1369 }
1370 }
Yi Li6a01f232009-01-07 23:14:39 +08001371
Graf Yang1fa9be72009-05-15 11:01:59 +00001372 return 0;
Yi Li6a01f232009-01-07 23:14:39 +08001373}
1374
1375#endif /* CONFIG_IPIPE */