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gerrit-public.fairphone.software / kernel / msm-4.9 / 86a46a0569660570e2ad0a5e670aff5bebbbbb23 / . / arch / arm64 / boot / dts / qcom / sdm845-v2.dtsi
blob: dcc64a909624d7a3fab2812b38f337c270d52057 [file] [log] [blame]
Channagoud Kadabi459f0112017-03-20 12:42:15 -0700[diff] [blame]1/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "sdm845.dtsi"
Soundrapandian Jeyaprakash3cc03bb2017-08-09 15:16:41 -0700[diff] [blame]14#include "sdm845-v2-camera.dtsi"
Channagoud Kadabi459f0112017-03-20 12:42:15 -0700[diff] [blame]15
16/ {
17 model = "Qualcomm Technologies, Inc. SDM845 V2";
18 qcom,msm-id = <321 0x20000>;
19};
David Collins36050182017-04-26 11:41:22 -0700[diff] [blame]20
Subhash Jadavani0842b272017-07-19 17:05:13 -0700[diff] [blame]21&sdhc_2 {
Subhash Jadavani3497a962017-07-31 13:57:47 -0700[diff] [blame]22 /delete-property/ qcom,sdr104-wa;
Subhash Jadavani0842b272017-07-19 17:05:13 -0700[diff] [blame]23};
24
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]25/delete-node/ &apc0_cpr;
26/delete-node/ &apc1_cpr;
27
28&soc {
29 /* CPR controller regulators */
30 apc0_cpr: cprh-ctrl@17dc0000 {
31 compatible = "qcom,cprh-sdm845-v2-kbss-regulator";
32 reg = <0x17dc0000 0x4000>,
33 <0x00784000 0x1000>,
34 <0x17840000 0x1000>;
35 reg-names = "cpr_ctrl", "fuse_base", "saw";
36 clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
37 clock-names = "core_clk";
38 qcom,cpr-ctrl-name = "apc0";
39 qcom,cpr-controller-id = <0>;
40
41 qcom,cpr-sensor-time = <1000>;
42 qcom,cpr-loop-time = <5000000>;
43 qcom,cpr-idle-cycles = <15>;
44 qcom,cpr-up-down-delay-time = <3000>;
45 qcom,cpr-step-quot-init-min = <11>;
46 qcom,cpr-step-quot-init-max = <12>;
47 qcom,cpr-count-mode = <0>; /* All at once */
48 qcom,cpr-count-repeat = <20>;
49 qcom,cpr-down-error-step-limit = <1>;
50 qcom,cpr-up-error-step-limit = <1>;
51 qcom,cpr-corner-switch-delay-time = <1042>;
52 qcom,cpr-voltage-settling-time = <1760>;
53 qcom,cpr-reset-step-quot-loop-en;
54
55 qcom,voltage-step = <4000>;
56 qcom,voltage-base = <352000>;
57 qcom,cpr-saw-use-unit-mV;
58
59 qcom,saw-avs-ctrl = <0x101C031>;
60 qcom,saw-avs-limit = <0x3B803B8>;
61
62 qcom,cpr-enable;
63 qcom,cpr-hw-closed-loop;
64
65 qcom,cpr-panic-reg-addr-list =
66 <0x17dc3a84 0x17dc3a88 0x17840c18>;
67 qcom,cpr-panic-reg-name-list =
68 "APSS_SILVER_CPRH_STATUS_0",
69 "APSS_SILVER_CPRH_STATUS_1",
70 "SILVER_SAW4_PMIC_STS";
71
72 qcom,cpr-aging-ref-voltage = <952000>;
73 vdd-supply = <&pm8998_s13>;
74
75 thread@0 {
76 qcom,cpr-thread-id = <0>;
77 qcom,cpr-consecutive-up = <0>;
78 qcom,cpr-consecutive-down = <0>;
79 qcom,cpr-up-threshold = <2>;
80 qcom,cpr-down-threshold = <2>;
81
82 apc0_pwrcl_vreg: regulator {
83 regulator-name = "apc0_pwrcl_corner";
84 regulator-min-microvolt = <1>;
85 regulator-max-microvolt = <18>;
86
87 qcom,cpr-fuse-corners = <4>;
88 qcom,cpr-fuse-combos = <16>;
89 qcom,cpr-speed-bins = <2>;
90 qcom,cpr-speed-bin-corners = <18 18>;
91 qcom,cpr-corners = <18>;
92
93 qcom,cpr-corner-fmax-map = <6 12 15 18>;
94
95 qcom,cpr-voltage-ceiling =
96 <828000 828000 828000 828000 828000
97 828000 828000 828000 828000 828000
98 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]99 932000 1000000 1000000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]100
101 qcom,cpr-voltage-floor =
102 <568000 568000 568000 568000 568000
103 568000 568000 568000 568000 568000
104 568000 568000 568000 568000 568000
105 568000 568000 568000>;
106
107 qcom,cpr-floor-to-ceiling-max-range =
108 <32000 32000 32000 32000 32000
109 32000 32000 32000 32000 32000
110 32000 32000 32000 32000 32000
111 32000 40000 40000>;
112
113 qcom,corner-frequencies =
114 <300000000 403200000 480000000
115 576000000 652800000 748800000
116 825600000 902400000 979200000
117 1056000000 1132800000 1228800000
118 1324800000 1420800000 1516800000
119 1612800000 1689600000 1766400000>;
120
121 qcom,cpr-ro-scaling-factor =
122 <2594 2795 2576 2761 2469 2673 2198
123 2553 3188 3255 3191 2962 3055 2984
124 2043 2947>,
125 <2594 2795 2576 2761 2469 2673 2198
126 2553 3188 3255 3191 2962 3055 2984
127 2043 2947>,
128 <2259 2389 2387 2531 2294 2464 2218
129 2476 2525 2855 2817 2836 2740 2490
130 1950 2632>,
131 <2259 2389 2387 2531 2294 2464 2218
132 2476 2525 2855 2817 2836 2740 2490
133 1950 2632>;
134
135 qcom,cpr-open-loop-voltage-fuse-adjustment =
David Collins33b588a2017-08-22 15:28:03 -0700[diff] [blame]136 < 0 0 12000 12000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]137
138 qcom,cpr-closed-loop-voltage-fuse-adjustment =
David Collins33b588a2017-08-22 15:28:03 -0700[diff] [blame]139 < 0 0 12000 10000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]140
141 qcom,allow-voltage-interpolation;
142 qcom,allow-quotient-interpolation;
143 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
144
145 qcom,cpr-aging-max-voltage-adjustment = <15000>;
146 qcom,cpr-aging-ref-corner = <18>;
147 qcom,cpr-aging-ro-scaling-factor = <1620>;
148 qcom,allow-aging-voltage-adjustment =
149 /* Speed bin 0 */
150 <0 1 1 1 1 1 1 1>,
151 /* Speed bin 1 */
152 <0 1 1 1 1 1 1 1>;
153 qcom,allow-aging-open-loop-voltage-adjustment =
154 <1>;
155 };
156 };
157
158 thread@1 {
159 qcom,cpr-thread-id = <1>;
160 qcom,cpr-consecutive-up = <0>;
161 qcom,cpr-consecutive-down = <0>;
162 qcom,cpr-up-threshold = <2>;
163 qcom,cpr-down-threshold = <2>;
164
165 apc0_l3_vreg: regulator {
166 regulator-name = "apc0_l3_corner";
167 regulator-min-microvolt = <1>;
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]168 regulator-max-microvolt = <15>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]169
170 qcom,cpr-fuse-corners = <4>;
171 qcom,cpr-fuse-combos = <16>;
172 qcom,cpr-speed-bins = <2>;
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]173 qcom,cpr-speed-bin-corners = <14 15>;
174 qcom,cpr-corners =
175 /* Speed bin 0 */
176 <14 14 14 14 14 14 14 14>,
177 /* Speed bin 1 */
178 <15 15 15 15 15 15 15 15>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]179
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]180 qcom,cpr-corner-fmax-map =
181 /* Speed bin 0 */
182 <4 8 11 14>,
183 /* Speed bin 1 */
184 <4 8 11 15>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]185
186 qcom,cpr-voltage-ceiling =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]187 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]188 <828000 828000 828000 828000 828000
189 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]190 828000 932000 932000 1000000>,
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]191 /* Speed bin 1 */
192 <828000 828000 828000 828000 828000
193 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]194 828000 932000 932000 1000000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]195 1000000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]196
197 qcom,cpr-voltage-floor =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]198 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]199 <568000 568000 568000 568000 568000
200 568000 568000 568000 568000 568000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]201 568000 568000 568000 568000>,
202 /* Speed bin 1 */
203 <568000 568000 568000 568000 568000
204 568000 568000 568000 568000 568000
205 568000 568000 568000 568000
206 568000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]207
208 qcom,cpr-floor-to-ceiling-max-range =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]209 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]210 <32000 32000 32000 32000 32000
211 32000 32000 32000 32000 32000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]212 32000 32000 32000 40000>,
213 /* Speed bin 1 */
214 <32000 32000 32000 32000 32000
215 32000 32000 32000 32000 32000
216 32000 32000 32000 40000 40000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]217
218 qcom,corner-frequencies =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]219 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]220 <300000000 403200000 480000000
221 576000000 652800000 748800000
222 844800000 940800000 1036800000
223 1132800000 1209600000 1305600000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]224 1401600000 1478400000>,
225 /* Speed bin 1 */
226 <300000000 403200000 480000000
227 576000000 652800000 748800000
228 844800000 940800000 1036800000
229 1132800000 1209600000 1305600000
230 1401600000 1497600000 1593600000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]231
232 qcom,cpr-ro-scaling-factor =
233 <2857 3056 2828 2952 2699 2796 2447
234 2631 2630 2579 2244 3343 3287 3137
235 3164 2656>,
236 <2857 3056 2828 2952 2699 2796 2447
237 2631 2630 2579 2244 3343 3287 3137
238 3164 2656>,
239 <2439 2577 2552 2667 2461 2577 2394
240 2536 2132 2307 2191 2903 2838 2912
241 2501 2095>,
242 <2439 2577 2552 2667 2461 2577 2394
243 2536 2132 2307 2191 2903 2838 2912
244 2501 2095>;
245
246 qcom,cpr-open-loop-voltage-fuse-adjustment =
David Collins33b588a2017-08-22 15:28:03 -0700[diff] [blame]247 < 8000 16000 16000 12000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]248
249 qcom,cpr-closed-loop-voltage-fuse-adjustment =
David Collins33b588a2017-08-22 15:28:03 -0700[diff] [blame]250 < 6000 14000 16000 12000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]251
252 qcom,allow-voltage-interpolation;
253 qcom,allow-quotient-interpolation;
254 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
255
256 qcom,cpr-aging-max-voltage-adjustment = <15000>;
257 qcom,cpr-aging-ref-corner = <14>;
258 qcom,cpr-aging-ro-scaling-factor = <1620>;
259 qcom,allow-aging-voltage-adjustment =
260 /* Speed bin 0 */
261 <0 1 1 1 1 1 1 1>,
262 /* Speed bin 1 */
263 <0 1 1 1 1 1 1 1>;
264 qcom,allow-aging-open-loop-voltage-adjustment =
265 <1>;
266 };
267 };
268 };
269
270 apc1_cpr: cprh-ctrl@17db0000 {
271 compatible = "qcom,cprh-sdm845-v2-kbss-regulator";
272 reg = <0x17db0000 0x4000>,
273 <0x00784000 0x1000>,
274 <0x17830000 0x1000>;
275 reg-names = "cpr_ctrl", "fuse_base", "saw";
276 clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
277 clock-names = "core_clk";
278 qcom,cpr-ctrl-name = "apc1";
279 qcom,cpr-controller-id = <1>;
280
281 qcom,cpr-sensor-time = <1000>;
282 qcom,cpr-loop-time = <5000000>;
283 qcom,cpr-idle-cycles = <15>;
284 qcom,cpr-up-down-delay-time = <3000>;
285 qcom,cpr-step-quot-init-min = <9>;
286 qcom,cpr-step-quot-init-max = <14>;
287 qcom,cpr-count-mode = <0>; /* All at once */
288 qcom,cpr-count-repeat = <20>;
289 qcom,cpr-down-error-step-limit = <1>;
290 qcom,cpr-up-error-step-limit = <1>;
291 qcom,cpr-corner-switch-delay-time = <1042>;
292 qcom,cpr-voltage-settling-time = <1760>;
293 qcom,cpr-reset-step-quot-loop-en;
294
295 qcom,apm-threshold-voltage = <800000>;
296 qcom,apm-crossover-voltage = <880000>;
297 qcom,mem-acc-threshold-voltage = <852000>;
298 qcom,mem-acc-crossover-voltage = <852000>;
299
300 qcom,voltage-step = <4000>;
301 qcom,voltage-base = <352000>;
302 qcom,cpr-saw-use-unit-mV;
303
304 qcom,saw-avs-ctrl = <0x101C031>;
305 qcom,saw-avs-limit = <0x4700470>;
306
307 qcom,cpr-enable;
308 qcom,cpr-hw-closed-loop;
309
310 qcom,cpr-panic-reg-addr-list =
311 <0x17db3a84 0x17830c18>;
312 qcom,cpr-panic-reg-name-list =
313 "APSS_GOLD_CPRH_STATUS_0", "GOLD_SAW4_PMIC_STS";
314
315 qcom,cpr-aging-ref-voltage = <1136000>;
316 vdd-supply = <&pm8998_s12>;
317
318 thread@0 {
319 qcom,cpr-thread-id = <0>;
320 qcom,cpr-consecutive-up = <0>;
321 qcom,cpr-consecutive-down = <0>;
322 qcom,cpr-up-threshold = <2>;
323 qcom,cpr-down-threshold = <2>;
324
325 apc1_perfcl_vreg: regulator {
326 regulator-name = "apc1_perfcl_corner";
327 regulator-min-microvolt = <1>;
328 regulator-max-microvolt = <33>;
329
330 qcom,cpr-fuse-corners = <5>;
331 qcom,cpr-fuse-combos = <16>;
332 qcom,cpr-speed-bins = <2>;
333 qcom,cpr-speed-bin-corners = <28 31>;
334 qcom,cpr-corners =
335 /* Speed bin 0 */
336 <28 28 28 28 28 28 28 28>,
337 /* Speed bin 1 */
338 <31 31 31 31 31 31 31 31>;
339
340 qcom,cpr-corner-fmax-map =
341 /* Speed bin 0 */
342 <7 14 22 27 28>,
343 /* Speed bin 1 */
344 <7 14 22 27 31>;
345
346 qcom,cpr-voltage-ceiling =
347 /* Speed bin 0 */
348 <828000 828000 828000 828000 828000
349 828000 828000 828000 828000 828000
350 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]351 828000 828000 828000 932000 932000
352 932000 932000 1104000 1104000 1104000
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]353 1104000 1136000 1136000>,
354 /* Speed bin 1 */
355 <828000 828000 828000 828000 828000
356 828000 828000 828000 828000 828000
357 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]358 828000 828000 828000 932000 932000
359 932000 932000 1104000 1104000 1104000
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]360 1104000 1136000 1136000 1136000 1136000
361 1136000>;
362
363 qcom,cpr-voltage-floor =
364 /* Speed bin 0 */
365 <568000 568000 568000 568000 568000
366 568000 568000 568000 568000 568000
367 568000 568000 568000 568000 568000
368 568000 568000 568000 568000 568000
369 568000 568000 568000 568000 568000
370 568000 568000 568000>,
371 /* Speed bin 1 */
372 <568000 568000 568000 568000 568000
373 568000 568000 568000 568000 568000
374 568000 568000 568000 568000 568000
375 568000 568000 568000 568000 568000
376 568000 568000 568000 568000 568000
377 568000 568000 568000 568000 568000
378 568000>;
379
380 qcom,cpr-floor-to-ceiling-max-range =
381 /* Speed bin 0 */
382 <32000 32000 32000 32000 32000
383 32000 32000 32000 32000 32000
384 32000 32000 32000 32000 32000
385 32000 32000 32000 32000 32000
386 32000 32000 32000 32000 32000
387 32000 32000 32000>,
388 /* Speed bin 1 */
389 <32000 32000 32000 32000 32000
390 32000 32000 32000 32000 32000
391 32000 32000 32000 32000 32000
392 32000 32000 32000 32000 32000
393 32000 32000 32000 32000 32000
394 32000 32000 40000 40000 40000
395 40000>;
396
397 qcom,corner-frequencies =
398 /* Speed bin 0 */
399 <300000000 403200000 480000000
400 576000000 652800000 748800000
401 825600000 902400000 979200000
402 1056000000 1132800000 1209600000
403 1286400000 1363200000 1459200000
404 1536000000 1612800000 1689600000
405 1766400000 1843200000 1920000000
406 1996800000 2092800000 2169600000
407 2246400000 2323200000 2400000000
408 2400000000>,
409 /* Speed bin 1 */
410 <300000000 403200000 480000000
411 576000000 652800000 748800000
412 825600000 902400000 979200000
413 1056000000 1132800000 1209600000
414 1286400000 1363200000 1459200000
415 1536000000 1612800000 1689600000
416 1766400000 1843200000 1920000000
417 1996800000 2092800000 2169600000
418 2246400000 2323200000 2400000000
David Collinsae2591d2017-08-22 14:15:14 -0700[diff] [blame]419 2476800000 2553600000 2649600000
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]420 2707200000>;
421
422 qcom,cpr-ro-scaling-factor =
423 <2857 3056 2828 2952 2699 2796 2447
424 2631 2630 2579 2244 3343 3287 3137
425 3164 2656>,
426 <2857 3056 2828 2952 2699 2796 2447
427 2631 2630 2579 2244 3343 3287 3137
428 3164 2656>,
429 <2086 2208 2273 2408 2203 2327 2213
430 2340 1755 2039 2049 2474 2437 2618
431 2003 1675>,
432 <2086 2208 2273 2408 2203 2327 2213
433 2340 1755 2039 2049 2474 2437 2618
434 2003 1675>,
435 <2086 2208 2273 2408 2203 2327 2213
436 2340 1755 2039 2049 2474 2437 2618
437 2003 1675>;
438
439 qcom,cpr-open-loop-voltage-fuse-adjustment =
David Collins33b588a2017-08-22 15:28:03 -0700[diff] [blame]440 /* Speed bin 0 */
441 < 8000 8000 8000 0 0>,
442 /* Speed bin 1 */
443 < 8000 8000 8000 0 16000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]444
445 qcom,cpr-closed-loop-voltage-fuse-adjustment =
David Collins33b588a2017-08-22 15:28:03 -0700[diff] [blame]446 /* Speed bin 0 */
447 < 6000 6000 8000 0 0>,
448 /* Speed bin 1 */
449 < 6000 6000 8000 0 16000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]450
451 qcom,allow-voltage-interpolation;
452 qcom,allow-quotient-interpolation;
453 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
454
455 qcom,cpr-aging-max-voltage-adjustment = <15000>;
456 qcom,cpr-aging-ref-corner = <27 31>;
457 qcom,cpr-aging-ro-scaling-factor = <1700>;
458 qcom,allow-aging-voltage-adjustment =
459 /* Speed bin 0 */
460 <0 1 1 1 1 1 1 1>,
461 /* Speed bin 1 */
462 <0 1 1 1 1 1 1 1>;
463 qcom,allow-aging-open-loop-voltage-adjustment =
464 <1>;
465 };
466 };
467 };
Vicky Wallaceddf4fad2017-08-03 20:15:55 -0700[diff] [blame]468
469 gpu_gx_domain_addr: syscon@0x5091508 {
470 compatible = "syscon";
471 reg = <0x5091508 0x4>;
472 };
473
474 gpu_gx_sw_reset: syscon@0x5091008 {
475 compatible = "syscon";
476 reg = <0x5091008 0x4>;
477 };
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]478};
479
480&clock_cpucc {
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]481 compatible = "qcom,clk-cpu-osm-v2";
482
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]483 vdd-l3-supply = <&apc0_l3_vreg>;
484 vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]485 vdd-perfcl-supply = <&apc1_perfcl_vreg>;
486
487 qcom,l3-speedbin0-v0 =
488 < 300000000 0x000c000f 0x00002020 0x1 1 >,
489 < 403200000 0x500c0115 0x00002020 0x1 2 >,
490 < 480000000 0x50140219 0x00002020 0x1 3 >,
491 < 576000000 0x5014031e 0x00002020 0x1 4 >,
492 < 652800000 0x401c0422 0x00002020 0x1 5 >,
493 < 748800000 0x401c0527 0x00002020 0x1 6 >,
494 < 844800000 0x4024062c 0x00002323 0x2 7 >,
495 < 940800000 0x40240731 0x00002727 0x2 8 >,
496 < 1036800000 0x40240836 0x00002b2b 0x2 9 >,
497 < 1132800000 0x402c093b 0x00002f2f 0x2 10 >,
498 < 1209600000 0x402c0a3f 0x00003232 0x2 11 >,
499 < 1305600000 0x40340b44 0x00003636 0x2 12 >,
500 < 1401600000 0x40340c49 0x00003a3a 0x2 13 >,
501 < 1478400000 0x403c0d4d 0x00003e3e 0x2 14 >;
502
Deepak Katragadda288d2b52017-08-11 10:13:59 -0700[diff] [blame]503 qcom,l3-speedbin1-v0 =
504 < 300000000 0x000c000f 0x00002020 0x1 1 >,
505 < 403200000 0x500c0115 0x00002020 0x1 2 >,
506 < 480000000 0x50140219 0x00002020 0x1 3 >,
507 < 576000000 0x5014031e 0x00002020 0x1 4 >,
508 < 652800000 0x401c0422 0x00002020 0x1 5 >,
509 < 748800000 0x401c0527 0x00002020 0x1 6 >,
510 < 844800000 0x4024062c 0x00002323 0x2 7 >,
511 < 940800000 0x40240731 0x00002727 0x2 8 >,
512 < 1036800000 0x40240836 0x00002b2b 0x2 9 >,
513 < 1132800000 0x402c093b 0x00002f2f 0x2 10 >,
514 < 1209600000 0x402c0a3f 0x00003232 0x2 11 >,
515 < 1305600000 0x40340b44 0x00003636 0x2 12 >,
516 < 1401600000 0x40340c49 0x00003a3a 0x2 13 >,
517 < 1497600000 0x403c0d4e 0x00003e3e 0x2 14 >,
518 < 1593600000 0x403c0e53 0x00004242 0x2 15 >;
519
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]520 qcom,pwrcl-speedbin0-v0 =
521 < 300000000 0x000c000f 0x00002020 0x1 1 >,
522 < 403200000 0x500c0115 0x00002020 0x1 2 >,
523 < 480000000 0x50140219 0x00002020 0x1 3 >,
524 < 576000000 0x5014031e 0x00002020 0x1 4 >,
525 < 652800000 0x401c0422 0x00002020 0x1 5 >,
526 < 748800000 0x401c0527 0x00002020 0x1 6 >,
527 < 825600000 0x401c062b 0x00002222 0x1 7 >,
528 < 902400000 0x4024072f 0x00002626 0x1 8 >,
529 < 979200000 0x40240833 0x00002929 0x1 9 >,
530 < 1056000000 0x402c0937 0x00002c2c 0x2 10 >,
531 < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >,
532 < 1228800000 0x402c0b40 0x00003333 0x2 12 >,
533 < 1324800000 0x40340c45 0x00003737 0x2 13 >,
534 < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >,
535 < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >,
536 < 1612800000 0x403c0f54 0x00004343 0x2 16 >,
537 < 1689600000 0x40441058 0x00004646 0x2 17 >,
538 < 1766400000 0x4044115c 0x00004a4a 0x2 18 >;
539
Deepak Katragadda401fcb92017-08-21 16:30:15 -0700[diff] [blame]540 qcom,pwrcl-speedbin1-v0 =
541 < 300000000 0x000c000f 0x00002020 0x1 1 >,
542 < 403200000 0x500c0115 0x00002020 0x1 2 >,
543 < 480000000 0x50140219 0x00002020 0x1 3 >,
544 < 576000000 0x5014031e 0x00002020 0x1 4 >,
545 < 652800000 0x401c0422 0x00002020 0x1 5 >,
546 < 748800000 0x401c0527 0x00002020 0x1 6 >,
547 < 825600000 0x401c062b 0x00002222 0x1 7 >,
548 < 902400000 0x4024072f 0x00002626 0x1 8 >,
549 < 979200000 0x40240833 0x00002929 0x1 9 >,
550 < 1056000000 0x402c0937 0x00002c2c 0x2 10 >,
551 < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >,
552 < 1228800000 0x402c0b40 0x00003333 0x2 12 >,
553 < 1324800000 0x40340c45 0x00003737 0x2 13 >,
554 < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >,
555 < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >,
556 < 1612800000 0x403c0f54 0x00004343 0x2 16 >,
557 < 1689600000 0x40441058 0x00004646 0x2 17 >,
558 < 1766400000 0x4044115c 0x00004a4a 0x2 18 >;
559
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]560 qcom,perfcl-speedbin0-v0 =
561 < 300000000 0x000c000f 0x00002020 0x1 1 >,
562 < 403200000 0x500c0115 0x00002020 0x1 2 >,
563 < 480000000 0x50140219 0x00002020 0x1 3 >,
564 < 576000000 0x5014031e 0x00002020 0x1 4 >,
565 < 652800000 0x401c0422 0x00002020 0x1 5 >,
566 < 748800000 0x401c0527 0x00002020 0x1 6 >,
567 < 825600000 0x401c062b 0x00002222 0x1 7 >,
568 < 902400000 0x4024072f 0x00002626 0x1 8 >,
569 < 979200000 0x40240833 0x00002929 0x1 9 >,
570 < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
571 < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
572 < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
573 < 1286400000 0x40340c43 0x00003636 0x2 13 >,
574 < 1363200000 0x40340d47 0x00003939 0x2 14 >,
575 < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
576 < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
577 < 1612800000 0x403c1054 0x00004343 0x2 17 >,
578 < 1689600000 0x40441158 0x00004646 0x2 18 >,
579 < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
580 < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
581 < 1920000000 0x404c1464 0x00005050 0x2 21 >,
582 < 1996800000 0x404c1568 0x00005353 0x2 22 >,
583 < 2092800000 0x4054166d 0x00005757 0x2 23 >,
584 < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
585 < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
586 < 2323200000 0x40541979 0x00006161 0x2 26 >,
587 < 2400000000 0x40541a7d 0x00006464 0x2 27 >;
588
589 qcom,perfcl-speedbin1-v0 =
590 < 300000000 0x000c000f 0x00002020 0x1 1 >,
591 < 403200000 0x500c0115 0x00002020 0x1 2 >,
592 < 480000000 0x50140219 0x00002020 0x1 3 >,
593 < 576000000 0x5014031e 0x00002020 0x1 4 >,
594 < 652800000 0x401c0422 0x00002020 0x1 5 >,
595 < 748800000 0x401c0527 0x00002020 0x1 6 >,
596 < 825600000 0x401c062b 0x00002222 0x1 7 >,
597 < 902400000 0x4024072f 0x00002626 0x1 8 >,
598 < 979200000 0x40240833 0x00002929 0x1 9 >,
599 < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
600 < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
601 < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
602 < 1286400000 0x40340c43 0x00003636 0x2 13 >,
603 < 1363200000 0x40340d47 0x00003939 0x2 14 >,
604 < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
605 < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
606 < 1612800000 0x403c1054 0x00004343 0x2 17 >,
607 < 1689600000 0x40441158 0x00004646 0x2 18 >,
608 < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
609 < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
610 < 1920000000 0x404c1464 0x00005050 0x2 21 >,
611 < 1996800000 0x404c1568 0x00005353 0x2 22 >,
612 < 2092800000 0x4054166d 0x00005757 0x2 23 >,
613 < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
614 < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
615 < 2323200000 0x40541979 0x00006161 0x2 26 >,
616 < 2400000000 0x40541a7d 0x00006464 0x2 27 >,
617 < 2476800000 0x40541b81 0x00006767 0x2 28 >,
618 < 2553600000 0x40541c85 0x00006a6a 0x2 29 >,
Deepak Katragadda1a183252017-08-21 12:44:34 -0700[diff] [blame]619 < 2649600000 0x40541d8a 0x00006e6e 0x2 30 >,
620 < 2745600000 0x40511e8f 0x00007272 0x2 31 >;
Deepak Katragadda30d72dd2017-08-01 13:56:00 -0700[diff] [blame]621
622 qcom,l3-memacc-level-vc-bin0 = <8 13>;
Deepak Katragadda288d2b52017-08-11 10:13:59 -0700[diff] [blame]623 qcom,l3-memacc-level-vc-bin1 = <8 13>;
Deepak Katragadda30d72dd2017-08-01 13:56:00 -0700[diff] [blame]624
625 qcom,pwrcl-memacc-level-vc-bin0 = <12 16>;
Deepak Katragadda401fcb92017-08-21 16:30:15 -0700[diff] [blame]626 qcom,pwrcl-memacc-level-vc-bin1 = <12 16>;
Deepak Katragadda30d72dd2017-08-01 13:56:00 -0700[diff] [blame]627
628 qcom,perfcl-memacc-level-vc-bin0 = <14 22>;
629 qcom,perfcl-memacc-level-vc-bin1 = <14 22>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]630};
631
Stephen Boydcbe46a02017-08-02 13:59:31 -0700[diff] [blame]632&bwmon {
633 qcom,count-unit = <0x10000>;
634};
635
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]636&clock_gcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]637 compatible = "qcom,gcc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]638};
639
640&clock_camcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]641 compatible = "qcom,cam_cc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]642};
643
644&clock_dispcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]645 compatible = "qcom,dispcc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]646};
647
Vicky Wallace1762ab32017-07-12 19:00:04 -0700[diff] [blame]648&clock_gpucc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]649 compatible = "qcom,gpucc-sdm845-v2", "syscon";
Vicky Wallace1762ab32017-07-12 19:00:04 -0700[diff] [blame]650};
651
652&clock_gfx {
653 compatible = "qcom,gfxcc-sdm845-v2";
654};
655
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]656&clock_videocc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]657 compatible = "qcom,video_cc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]658};
Praneeth Paladugu55381212017-07-05 15:02:44 -0700[diff] [blame]659
660&msm_vidc {
661 qcom,allowed-clock-rates = <100000000 200000000 330000000
662 404000000 444000000 533000000>;
663};
Reut Zysman861fd6c2017-07-30 15:39:13 +0300[diff] [blame]664
David Collins113cc2772017-06-27 17:26:54 -0700[diff] [blame]665&refgen {
666 status = "ok";
David Collinsd388dd82017-08-15 16:23:21 -0700[diff] [blame]667 regulator-always-on;
David Collins113cc2772017-06-27 17:26:54 -0700[diff] [blame]668};
669
Reut Zysman861fd6c2017-07-30 15:39:13 +0300[diff] [blame]670&spss_utils {
671 qcom,spss-dev-firmware-name = "spss2d"; /* 8 chars max */
672 qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */
673 qcom,spss-prod-firmware-name = "spss2p"; /* 8 chars max */
674};
Narendra Muppalla4efd3442017-07-24 17:36:15 -0700[diff] [blame]675
676&mdss_mdp {
677 clock-max-rate = <0 0 0 0 430000000 19200000 0>;
Narendra Muppalla86a46a02017-08-17 11:14:37 -0700[diff] [blame^]678 qcom,sde-min-core-ib-kbps = <4800000>;
Narendra Muppalla4efd3442017-07-24 17:36:15 -0700[diff] [blame]679};
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]680
681&energy_costs {
682 CPU_COST_0: core-cost0 {
683 busy-cost-data = <
684 300000 11
685 403200 17
686 480000 21
687 576000 26
688 652800 31
689 748800 37
690 825600 42
691 902400 47
692 979200 52
693 1056000 57
694 1132800 62
695 1228800 69
696 1324800 78
697 1420800 89
698 1516800 103
699 1612800 122
700 1689600 140
701 1766400 159
702 >;
703 idle-cost-data = <
704 22 18 14 12
705 >;
706 };
707 CPU_COST_1: core-cost1 {
708 busy-cost-data = <
709 300000 130
710 403200 480
711 480000 730
712 576000 1030
713 652800 1260
714 748800 1530
715 825600 1740
716 902400 1930
717 979200 2110
718 1056000 2290
719 1132800 2460
720 1209600 2630
721 1286400 2800
722 1363200 2980
723 1459200 3240
724 1536000 3490
725 1612800 3780
726 1689600 4120
727 1766400 4530
728 1843200 5020
729 1920000 5590
730 1996800 6230
731 2092800 7120
732 2169600 7870
733 2246400 8620
734 2323200 9330
735 2400000 10030
736 2476800 10830
737 2553600 12080
738 2630400 14580
739 2707200 19960
740 >;
741 idle-cost-data = <
742 100 80 60 40
743 >;
744 };
745 CLUSTER_COST_0: cluster-cost0 {
746 busy-cost-data = <
747 300000 3
748 403200 4
749 480000 4
750 576000 4
751 652800 5
752 748800 5
753 825600 6
754 902400 7
755 979200 7
756 1056000 8
757 1132800 9
758 1228800 9
759 1324800 10
760 1420800 11
761 1516800 12
762 1612800 13
763 1689600 15
764 1766400 17
765 >;
766 idle-cost-data = <
767 4 3 2 1
768 >;
769 };
770 CLUSTER_COST_1: cluster-cost1 {
771 busy-cost-data = <
772 300000 24
773 403200 24
774 480000 25
775 576000 25
776 652800 26
777 748800 27
778 825600 28
779 902400 29
780 979200 30
781 1056000 32
782 1132800 34
783 1209600 37
784 1286400 40
785 1363200 45
786 1459200 50
787 1536000 57
788 1612800 64
789 1689600 74
790 1766400 84
791 1843200 96
792 1920000 106
793 1996800 113
794 2092800 120
795 2169600 125
796 2246400 127
797 2323200 130
798 2400000 135
799 2476800 140
800 2553600 145
801 2630400 150
802 2707200 155
803 >;
804 idle-cost-data = <
805 4 3 2 1
806 >;
807 };
808};
Vicky Wallaceddf4fad2017-08-03 20:15:55 -0700[diff] [blame]809
810&gpu_gx_gdsc {
811 domain-addr = <&gpu_gx_domain_addr>;
812 sw-reset = <&gpu_gx_sw_reset>;
813 qcom,reset-aon-logic;
814};
Lokesh Batra835f0162017-08-01 11:55:53 -0700[diff] [blame]815
816/* GPU overrides */
817&msm_gpu {
818 /* Updated chip ID */
819 qcom,chipid = <0x06030001>;
820 qcom,initial-pwrlevel = <5>;
821
822 qcom,gpu-pwrlevels {
823 #address-cells = <1>;
824 #size-cells = <0>;
825
826 compatible = "qcom,gpu-pwrlevels";
827
828 qcom,gpu-pwrlevel@0 {
829 reg = <0>;
830 qcom,gpu-freq = <675000000>;
831 qcom,bus-freq = <12>;
832 qcom,bus-min = <10>;
833 qcom,bus-max = <12>;
834 };
835
836 qcom,gpu-pwrlevel@1 {
837 reg = <1>;
838 qcom,gpu-freq = <596000000>;
839 qcom,bus-freq = <10>;
840 qcom,bus-min = <9>;
841 qcom,bus-max = <11>;
842 };
843
844 qcom,gpu-pwrlevel@2 {
845 reg = <2>;
846 qcom,gpu-freq = <520000000>;
847 qcom,bus-freq = <9>;
848 qcom,bus-min = <8>;
849 qcom,bus-max = <10>;
850 };
851
852 qcom,gpu-pwrlevel@3 {
853 reg = <3>;
854 qcom,gpu-freq = <414000000>;
855 qcom,bus-freq = <8>;
856 qcom,bus-min = <7>;
857 qcom,bus-max = <9>;
858 };
859
860 qcom,gpu-pwrlevel@4 {
861 reg = <4>;
862 qcom,gpu-freq = <342000000>;
863 qcom,bus-freq = <6>;
864 qcom,bus-min = <5>;
865 qcom,bus-max = <7>;
866 };
867
868 qcom,gpu-pwrlevel@5 {
869 reg = <5>;
870 qcom,gpu-freq = <257000000>;
871 qcom,bus-freq = <4>;
872 qcom,bus-min = <3>;
873 qcom,bus-max = <5>;
874 };
875
876 qcom,gpu-pwrlevel@6 {
877 reg = <6>;
878 qcom,gpu-freq = <0>;
879 qcom,bus-freq = <0>;
880 qcom,bus-min = <0>;
881 qcom,bus-max = <0>;
882 };
883 };
884};
885
886&gmu {
887 qcom,gmu-pwrlevels {
888 #address-cells = <1>;
889 #size-cells = <0>;
890
891 compatible = "qcom,gmu-pwrlevels";
892
893 qcom,gmu-pwrlevel@0 {
894 reg = <0>;
895 qcom,gmu-freq = <500000000>;
896 };
897
898 qcom,gmu-pwrlevel@1 {
899 reg = <1>;
900 qcom,gmu-freq = <200000000>;
901 };
902
903 qcom,gmu-pwrlevel@2 {
904 reg = <2>;
905 qcom,gmu-freq = <0>;
906 };
907 };
908};