blob: 9fadf7e31c5f86459efc0b70fb1674f45da5a289 [file] [log] [blame]
Xiubo Li43550822013-12-17 11:24:38 +08001/*
2 * Freescale ALSA SoC Digital Audio Interface (SAI) driver.
3 *
Zidan Wangc3ecef22015-05-11 18:24:41 +08004 * Copyright 2012-2015 Freescale Semiconductor, Inc.
Xiubo Li43550822013-12-17 11:24:38 +08005 *
6 * This program is free software, you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation, either version 2 of the License, or(at your
9 * option) any later version.
10 *
11 */
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/dmaengine.h>
16#include <linux/module.h>
17#include <linux/of_address.h>
Xiubo Li78957fc2014-02-08 14:38:28 +080018#include <linux/regmap.h>
Xiubo Li43550822013-12-17 11:24:38 +080019#include <linux/slab.h>
Xiubo Li512feb42016-01-15 19:35:24 +080020#include <linux/time.h>
Xiubo Li43550822013-12-17 11:24:38 +080021#include <sound/core.h>
22#include <sound/dmaengine_pcm.h>
23#include <sound/pcm_params.h>
Fabio Estevam4d245852016-05-04 19:33:59 -030024#include <linux/mfd/syscon.h>
25#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
Xiubo Li43550822013-12-17 11:24:38 +080026
27#include "fsl_sai.h"
Nicolin Chenc7540642014-04-01 19:34:09 +080028#include "imx-pcm.h"
Xiubo Li43550822013-12-17 11:24:38 +080029
Nicolin Chene2681a12014-03-27 19:06:59 +080030#define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
31 FSL_SAI_CSR_FEIE)
32
Lars-Peter Clausen444c37ae2015-10-22 10:43:23 +020033static const unsigned int fsl_sai_rates[] = {
Zidan Wangc5f48232015-05-11 18:24:43 +080034 8000, 11025, 12000, 16000, 22050,
35 24000, 32000, 44100, 48000, 64000,
36 88200, 96000, 176400, 192000
37};
38
Lars-Peter Clausen444c37ae2015-10-22 10:43:23 +020039static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
Zidan Wangc5f48232015-05-11 18:24:43 +080040 .count = ARRAY_SIZE(fsl_sai_rates),
41 .list = fsl_sai_rates,
42};
43
Nicolin Chene2681a12014-03-27 19:06:59 +080044static irqreturn_t fsl_sai_isr(int irq, void *devid)
45{
46 struct fsl_sai *sai = (struct fsl_sai *)devid;
47 struct device *dev = &sai->pdev->dev;
Nicolin Chen413312a2014-03-28 19:39:25 +080048 u32 flags, xcsr, mask;
49 bool irq_none = true;
Nicolin Chene2681a12014-03-27 19:06:59 +080050
Nicolin Chen413312a2014-03-28 19:39:25 +080051 /*
52 * Both IRQ status bits and IRQ mask bits are in the xCSR but
53 * different shifts. And we here create a mask only for those
54 * IRQs that we activated.
55 */
Nicolin Chene2681a12014-03-27 19:06:59 +080056 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
57
58 /* Tx IRQ */
59 regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
Nicolin Chen413312a2014-03-28 19:39:25 +080060 flags = xcsr & mask;
Nicolin Chene2681a12014-03-27 19:06:59 +080061
Nicolin Chen413312a2014-03-28 19:39:25 +080062 if (flags)
63 irq_none = false;
64 else
65 goto irq_rx;
66
67 if (flags & FSL_SAI_CSR_WSF)
Nicolin Chene2681a12014-03-27 19:06:59 +080068 dev_dbg(dev, "isr: Start of Tx word detected\n");
69
Nicolin Chen413312a2014-03-28 19:39:25 +080070 if (flags & FSL_SAI_CSR_SEF)
Nicolin Chene2681a12014-03-27 19:06:59 +080071 dev_warn(dev, "isr: Tx Frame sync error detected\n");
72
Nicolin Chen413312a2014-03-28 19:39:25 +080073 if (flags & FSL_SAI_CSR_FEF) {
Nicolin Chene2681a12014-03-27 19:06:59 +080074 dev_warn(dev, "isr: Transmit underrun detected\n");
75 /* FIFO reset for safety */
76 xcsr |= FSL_SAI_CSR_FR;
77 }
78
Nicolin Chen413312a2014-03-28 19:39:25 +080079 if (flags & FSL_SAI_CSR_FWF)
Nicolin Chene2681a12014-03-27 19:06:59 +080080 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
81
Nicolin Chen413312a2014-03-28 19:39:25 +080082 if (flags & FSL_SAI_CSR_FRF)
Nicolin Chene2681a12014-03-27 19:06:59 +080083 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
84
Nicolin Chen413312a2014-03-28 19:39:25 +080085 flags &= FSL_SAI_CSR_xF_W_MASK;
86 xcsr &= ~FSL_SAI_CSR_xF_MASK;
Nicolin Chene2681a12014-03-27 19:06:59 +080087
Nicolin Chen413312a2014-03-28 19:39:25 +080088 if (flags)
89 regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
90
91irq_rx:
Nicolin Chene2681a12014-03-27 19:06:59 +080092 /* Rx IRQ */
93 regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
Nicolin Chen413312a2014-03-28 19:39:25 +080094 flags = xcsr & mask;
Nicolin Chene2681a12014-03-27 19:06:59 +080095
Nicolin Chen413312a2014-03-28 19:39:25 +080096 if (flags)
97 irq_none = false;
98 else
99 goto out;
100
101 if (flags & FSL_SAI_CSR_WSF)
Nicolin Chene2681a12014-03-27 19:06:59 +0800102 dev_dbg(dev, "isr: Start of Rx word detected\n");
103
Nicolin Chen413312a2014-03-28 19:39:25 +0800104 if (flags & FSL_SAI_CSR_SEF)
Nicolin Chene2681a12014-03-27 19:06:59 +0800105 dev_warn(dev, "isr: Rx Frame sync error detected\n");
106
Nicolin Chen413312a2014-03-28 19:39:25 +0800107 if (flags & FSL_SAI_CSR_FEF) {
Nicolin Chene2681a12014-03-27 19:06:59 +0800108 dev_warn(dev, "isr: Receive overflow detected\n");
109 /* FIFO reset for safety */
110 xcsr |= FSL_SAI_CSR_FR;
111 }
112
Nicolin Chen413312a2014-03-28 19:39:25 +0800113 if (flags & FSL_SAI_CSR_FWF)
Nicolin Chene2681a12014-03-27 19:06:59 +0800114 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
115
Nicolin Chen413312a2014-03-28 19:39:25 +0800116 if (flags & FSL_SAI_CSR_FRF)
Nicolin Chene2681a12014-03-27 19:06:59 +0800117 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
118
Nicolin Chen413312a2014-03-28 19:39:25 +0800119 flags &= FSL_SAI_CSR_xF_W_MASK;
120 xcsr &= ~FSL_SAI_CSR_xF_MASK;
Nicolin Chene2681a12014-03-27 19:06:59 +0800121
Nicolin Chen413312a2014-03-28 19:39:25 +0800122 if (flags)
Nicolin Chen4800f882014-07-17 21:21:38 +0800123 regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr);
Nicolin Chen413312a2014-03-28 19:39:25 +0800124
125out:
126 if (irq_none)
127 return IRQ_NONE;
128 else
129 return IRQ_HANDLED;
Nicolin Chene2681a12014-03-27 19:06:59 +0800130}
131
Zidan Wangc1df2962015-11-24 15:31:54 +0800132static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
133 u32 rx_mask, int slots, int slot_width)
134{
135 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
136
137 sai->slots = slots;
138 sai->slot_width = slot_width;
139
140 return 0;
141}
142
Xiubo Li43550822013-12-17 11:24:38 +0800143static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
144 int clk_id, unsigned int freq, int fsl_dir)
145{
Xiubo Li43550822013-12-17 11:24:38 +0800146 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
Nicolin Chen2a266f82014-04-11 18:30:09 +0800147 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
148 u32 val_cr2 = 0;
Xiubo Li633ff8f2014-01-08 16:13:05 +0800149
Xiubo Li43550822013-12-17 11:24:38 +0800150 switch (clk_id) {
151 case FSL_SAI_CLK_BUS:
Xiubo Li43550822013-12-17 11:24:38 +0800152 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
153 break;
154 case FSL_SAI_CLK_MAST1:
Xiubo Li43550822013-12-17 11:24:38 +0800155 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
156 break;
157 case FSL_SAI_CLK_MAST2:
Xiubo Li43550822013-12-17 11:24:38 +0800158 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
159 break;
160 case FSL_SAI_CLK_MAST3:
Xiubo Li43550822013-12-17 11:24:38 +0800161 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
162 break;
163 default:
164 return -EINVAL;
165 }
Xiubo Li633ff8f2014-01-08 16:13:05 +0800166
Nicolin Chen2a266f82014-04-11 18:30:09 +0800167 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
168 FSL_SAI_CR2_MSEL_MASK, val_cr2);
Xiubo Li43550822013-12-17 11:24:38 +0800169
170 return 0;
171}
172
173static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
174 int clk_id, unsigned int freq, int dir)
175{
Nicolin Chen4e3a99f2013-12-20 16:41:05 +0800176 int ret;
Xiubo Li43550822013-12-17 11:24:38 +0800177
178 if (dir == SND_SOC_CLOCK_IN)
179 return 0;
180
Xiubo Li43550822013-12-17 11:24:38 +0800181 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
182 FSL_FMT_TRANSMITTER);
183 if (ret) {
Nicolin Chen190af122013-12-20 16:41:04 +0800184 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
Xiubo Li78957fc2014-02-08 14:38:28 +0800185 return ret;
Xiubo Li43550822013-12-17 11:24:38 +0800186 }
187
188 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
189 FSL_FMT_RECEIVER);
Xiubo Li78957fc2014-02-08 14:38:28 +0800190 if (ret)
Nicolin Chen190af122013-12-20 16:41:04 +0800191 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
Xiubo Li43550822013-12-17 11:24:38 +0800192
Nicolin Chen1fb2d9d2013-12-20 16:41:00 +0800193 return ret;
Xiubo Li43550822013-12-17 11:24:38 +0800194}
195
196static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
197 unsigned int fmt, int fsl_dir)
198{
Xiubo Li43550822013-12-17 11:24:38 +0800199 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
Nicolin Chen2a266f82014-04-11 18:30:09 +0800200 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
201 u32 val_cr2 = 0, val_cr4 = 0;
Xiubo Li43550822013-12-17 11:24:38 +0800202
Xiubo Lieadb0012014-08-29 15:12:12 +0800203 if (!sai->is_lsb_first)
Xiubo Li72aa62b2013-12-31 15:33:22 +0800204 val_cr4 |= FSL_SAI_CR4_MF;
Xiubo Li43550822013-12-17 11:24:38 +0800205
Xiubo Li13cde092014-02-25 17:54:51 +0800206 /* DAI mode */
Xiubo Li43550822013-12-17 11:24:38 +0800207 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
208 case SND_SOC_DAIFMT_I2S:
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800209 /*
210 * Frame low, 1clk before data, one word length for frame sync,
211 * frame sync starts one serial clock cycle earlier,
212 * that is, together with the last bit of the previous
213 * data word.
214 */
Nicolin Chenef33bc32014-04-04 15:09:47 +0800215 val_cr2 |= FSL_SAI_CR2_BCP;
Xiubo Li13cde092014-02-25 17:54:51 +0800216 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
Xiubo Li43550822013-12-17 11:24:38 +0800217 break;
Xiubo Li13cde092014-02-25 17:54:51 +0800218 case SND_SOC_DAIFMT_LEFT_J:
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800219 /*
220 * Frame high, one word length for frame sync,
221 * frame sync asserts with the first bit of the frame.
222 */
Nicolin Chenef33bc32014-04-04 15:09:47 +0800223 val_cr2 |= FSL_SAI_CR2_BCP;
Xiubo Li13cde092014-02-25 17:54:51 +0800224 break;
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800225 case SND_SOC_DAIFMT_DSP_A:
226 /*
227 * Frame high, 1clk before data, one bit for frame sync,
228 * frame sync starts one serial clock cycle earlier,
229 * that is, together with the last bit of the previous
230 * data word.
231 */
Nicolin Chenef33bc32014-04-04 15:09:47 +0800232 val_cr2 |= FSL_SAI_CR2_BCP;
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800233 val_cr4 |= FSL_SAI_CR4_FSE;
234 sai->is_dsp_mode = true;
235 break;
236 case SND_SOC_DAIFMT_DSP_B:
237 /*
238 * Frame high, one bit for frame sync,
239 * frame sync asserts with the first bit of the frame.
240 */
Nicolin Chenef33bc32014-04-04 15:09:47 +0800241 val_cr2 |= FSL_SAI_CR2_BCP;
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800242 sai->is_dsp_mode = true;
243 break;
Xiubo Li13cde092014-02-25 17:54:51 +0800244 case SND_SOC_DAIFMT_RIGHT_J:
245 /* To be done */
Xiubo Li43550822013-12-17 11:24:38 +0800246 default:
247 return -EINVAL;
248 }
249
Xiubo Li13cde092014-02-25 17:54:51 +0800250 /* DAI clock inversion */
Xiubo Li43550822013-12-17 11:24:38 +0800251 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
252 case SND_SOC_DAIFMT_IB_IF:
Xiubo Li13cde092014-02-25 17:54:51 +0800253 /* Invert both clocks */
254 val_cr2 ^= FSL_SAI_CR2_BCP;
255 val_cr4 ^= FSL_SAI_CR4_FSP;
Xiubo Li43550822013-12-17 11:24:38 +0800256 break;
257 case SND_SOC_DAIFMT_IB_NF:
Xiubo Li13cde092014-02-25 17:54:51 +0800258 /* Invert bit clock */
259 val_cr2 ^= FSL_SAI_CR2_BCP;
Xiubo Li43550822013-12-17 11:24:38 +0800260 break;
261 case SND_SOC_DAIFMT_NB_IF:
Xiubo Li13cde092014-02-25 17:54:51 +0800262 /* Invert frame clock */
263 val_cr4 ^= FSL_SAI_CR4_FSP;
Xiubo Li43550822013-12-17 11:24:38 +0800264 break;
265 case SND_SOC_DAIFMT_NB_NF:
Xiubo Li13cde092014-02-25 17:54:51 +0800266 /* Nothing to do for both normal cases */
Xiubo Li43550822013-12-17 11:24:38 +0800267 break;
268 default:
269 return -EINVAL;
270 }
271
Xiubo Li13cde092014-02-25 17:54:51 +0800272 /* DAI clock master masks */
Xiubo Li43550822013-12-17 11:24:38 +0800273 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
274 case SND_SOC_DAIFMT_CBS_CFS:
275 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
276 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
277 break;
278 case SND_SOC_DAIFMT_CBM_CFM:
Zidan Wangc3ecef22015-05-11 18:24:41 +0800279 sai->is_slave_mode = true;
Xiubo Li43550822013-12-17 11:24:38 +0800280 break;
Xiubo Li13cde092014-02-25 17:54:51 +0800281 case SND_SOC_DAIFMT_CBS_CFM:
282 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
Xiubo Li13cde092014-02-25 17:54:51 +0800283 break;
284 case SND_SOC_DAIFMT_CBM_CFS:
Xiubo Li13cde092014-02-25 17:54:51 +0800285 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
Zidan Wangc3ecef22015-05-11 18:24:41 +0800286 sai->is_slave_mode = true;
Xiubo Li13cde092014-02-25 17:54:51 +0800287 break;
Xiubo Li43550822013-12-17 11:24:38 +0800288 default:
289 return -EINVAL;
290 }
291
Nicolin Chen2a266f82014-04-11 18:30:09 +0800292 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
293 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
294 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
295 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
296 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
Xiubo Li43550822013-12-17 11:24:38 +0800297
298 return 0;
299}
300
301static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
302{
Nicolin Chen4e3a99f2013-12-20 16:41:05 +0800303 int ret;
Xiubo Li43550822013-12-17 11:24:38 +0800304
Xiubo Li43550822013-12-17 11:24:38 +0800305 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
306 if (ret) {
Nicolin Chen190af122013-12-20 16:41:04 +0800307 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
Xiubo Li78957fc2014-02-08 14:38:28 +0800308 return ret;
Xiubo Li43550822013-12-17 11:24:38 +0800309 }
310
311 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
Xiubo Li78957fc2014-02-08 14:38:28 +0800312 if (ret)
Nicolin Chen190af122013-12-20 16:41:04 +0800313 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
Xiubo Li43550822013-12-17 11:24:38 +0800314
Nicolin Chen1fb2d9d2013-12-20 16:41:00 +0800315 return ret;
Xiubo Li43550822013-12-17 11:24:38 +0800316}
317
Zidan Wangc3ecef22015-05-11 18:24:41 +0800318static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
319{
320 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
321 unsigned long clk_rate;
322 u32 savediv = 0, ratio, savesub = freq;
323 u32 id;
324 int ret = 0;
325
326 /* Don't apply to slave mode */
327 if (sai->is_slave_mode)
328 return 0;
329
330 for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
331 clk_rate = clk_get_rate(sai->mclk_clk[id]);
332 if (!clk_rate)
333 continue;
334
335 ratio = clk_rate / freq;
336
337 ret = clk_rate - ratio * freq;
338
339 /*
340 * Drop the source that can not be
341 * divided into the required rate.
342 */
343 if (ret != 0 && clk_rate / ret < 1000)
344 continue;
345
346 dev_dbg(dai->dev,
347 "ratio %d for freq %dHz based on clock %ldHz\n",
348 ratio, freq, clk_rate);
349
350 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
351 ratio /= 2;
352 else
353 continue;
354
355 if (ret < savesub) {
356 savediv = ratio;
357 sai->mclk_id[tx] = id;
358 savesub = ret;
359 }
360
361 if (ret == 0)
362 break;
363 }
364
365 if (savediv == 0) {
366 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
367 tx ? 'T' : 'R', freq);
368 return -EINVAL;
369 }
370
Zidan Wang9cc58712015-11-09 19:02:29 +0800371 /*
372 * 1) For Asynchronous mode, we must set RCR2 register for capture, and
373 * set TCR2 register for playback.
374 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
375 * and capture.
376 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
377 * and capture.
378 * 4) For Tx and Rx are both Synchronous with another SAI, we just
379 * ignore it.
380 */
381 if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||
382 (!tx && !sai->synchronous[RX])) {
Zidan Wangc3ecef22015-05-11 18:24:41 +0800383 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
384 FSL_SAI_CR2_MSEL_MASK,
385 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
386 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
387 FSL_SAI_CR2_DIV_MASK, savediv - 1);
Zidan Wang9cc58712015-11-09 19:02:29 +0800388 } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||
389 (tx && !sai->synchronous[TX])) {
Zidan Wangc3ecef22015-05-11 18:24:41 +0800390 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
391 FSL_SAI_CR2_MSEL_MASK,
392 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
393 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
394 FSL_SAI_CR2_DIV_MASK, savediv - 1);
395 }
396
397 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
398 sai->mclk_id[tx], savediv, savesub);
399
400 return 0;
401}
402
Xiubo Li43550822013-12-17 11:24:38 +0800403static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
404 struct snd_pcm_hw_params *params,
405 struct snd_soc_dai *cpu_dai)
406{
Nicolin Chen4e3a99f2013-12-20 16:41:05 +0800407 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
Nicolin Chen2a266f82014-04-11 18:30:09 +0800408 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
Xiubo Li43550822013-12-17 11:24:38 +0800409 unsigned int channels = params_channels(params);
Zidan Wang4ca73042015-11-24 15:32:09 +0800410 u32 word_width = params_width(params);
Nicolin Chen2a266f82014-04-11 18:30:09 +0800411 u32 val_cr4 = 0, val_cr5 = 0;
Zidan Wangc1df2962015-11-24 15:31:54 +0800412 u32 slots = (channels == 1) ? 2 : channels;
413 u32 slot_width = word_width;
Zidan Wangc3ecef22015-05-11 18:24:41 +0800414 int ret;
415
Zidan Wangc1df2962015-11-24 15:31:54 +0800416 if (sai->slots)
417 slots = sai->slots;
418
419 if (sai->slot_width)
420 slot_width = sai->slot_width;
421
Zidan Wangc3ecef22015-05-11 18:24:41 +0800422 if (!sai->is_slave_mode) {
423 ret = fsl_sai_set_bclk(cpu_dai, tx,
Zidan Wangc1df2962015-11-24 15:31:54 +0800424 slots * slot_width * params_rate(params));
Zidan Wangc3ecef22015-05-11 18:24:41 +0800425 if (ret)
426 return ret;
427
428 /* Do not enable the clock if it is already enabled */
429 if (!(sai->mclk_streams & BIT(substream->stream))) {
430 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
431 if (ret)
432 return ret;
433
434 sai->mclk_streams |= BIT(substream->stream);
435 }
Zidan Wangc3ecef22015-05-11 18:24:41 +0800436 }
Xiubo Li43550822013-12-17 11:24:38 +0800437
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800438 if (!sai->is_dsp_mode)
Zidan Wangc1df2962015-11-24 15:31:54 +0800439 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800440
Zidan Wangc1df2962015-11-24 15:31:54 +0800441 val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
442 val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
Xiubo Li43550822013-12-17 11:24:38 +0800443
Xiubo Lieadb0012014-08-29 15:12:12 +0800444 if (sai->is_lsb_first)
Xiubo Li43550822013-12-17 11:24:38 +0800445 val_cr5 |= FSL_SAI_CR5_FBT(0);
Xiubo Li72aa62b2013-12-31 15:33:22 +0800446 else
447 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
Xiubo Li43550822013-12-17 11:24:38 +0800448
Zidan Wangc1df2962015-11-24 15:31:54 +0800449 val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
Xiubo Li43550822013-12-17 11:24:38 +0800450
Zidan Wang51659ca2015-11-09 19:03:13 +0800451 /*
452 * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
453 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
454 * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
455 * error.
456 */
457
458 if (!sai->is_slave_mode) {
459 if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
460 regmap_update_bits(sai->regmap, FSL_SAI_TCR4,
461 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
462 val_cr4);
463 regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
464 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
465 FSL_SAI_CR5_FBT_MASK, val_cr5);
466 regmap_write(sai->regmap, FSL_SAI_TMR,
467 ~0UL - ((1 << channels) - 1));
468 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
469 regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
470 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
471 val_cr4);
472 regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
473 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
474 FSL_SAI_CR5_FBT_MASK, val_cr5);
475 regmap_write(sai->regmap, FSL_SAI_RMR,
476 ~0UL - ((1 << channels) - 1));
477 }
478 }
Xiubo Li43550822013-12-17 11:24:38 +0800479
Nicolin Chen2a266f82014-04-11 18:30:09 +0800480 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
481 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
482 val_cr4);
483 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
484 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
485 FSL_SAI_CR5_FBT_MASK, val_cr5);
486 regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
Xiubo Li43550822013-12-17 11:24:38 +0800487
488 return 0;
489}
490
Zidan Wangc3ecef22015-05-11 18:24:41 +0800491static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
492 struct snd_soc_dai *cpu_dai)
493{
494 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
495 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
496
497 if (!sai->is_slave_mode &&
498 sai->mclk_streams & BIT(substream->stream)) {
499 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
500 sai->mclk_streams &= ~BIT(substream->stream);
501 }
502
503 return 0;
504}
505
506
Xiubo Li43550822013-12-17 11:24:38 +0800507static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
508 struct snd_soc_dai *cpu_dai)
509{
510 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
Nicolin Chene6b39842014-04-01 11:17:06 +0800511 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
Nicolin Chenc44b56a2014-07-23 19:23:39 +0800512 u32 xcsr, count = 100;
Xiubo Li496a39d2013-12-31 15:33:21 +0800513
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800514 /*
Nicolin Chen08fdf652014-08-05 15:32:05 +0800515 * Asynchronous mode: Clear SYNC for both Tx and Rx.
516 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
517 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800518 */
Stefan Agner3cc77802015-10-19 17:42:23 -0700519 regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
520 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
Xiubo Li78957fc2014-02-08 14:38:28 +0800521 regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
Nicolin Chen08fdf652014-08-05 15:32:05 +0800522 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
Xiubo Li496a39d2013-12-31 15:33:21 +0800523
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800524 /*
525 * It is recommended that the transmitter is the last enabled
526 * and the first disabled.
527 */
Xiubo Li43550822013-12-17 11:24:38 +0800528 switch (cmd) {
529 case SNDRV_PCM_TRIGGER_START:
530 case SNDRV_PCM_TRIGGER_RESUME:
531 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Nicolin Chena3fdc672014-07-23 19:23:40 +0800532 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
533 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
534
Nicolin Chenf4075a82014-07-23 19:23:38 +0800535 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
536 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
537 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
538 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
Xiubo Lie5d0fa92013-12-25 12:40:04 +0800539
Nicolin Chene6b39842014-04-01 11:17:06 +0800540 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
Nicolin Chen8abba5d2014-04-01 11:17:07 +0800541 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
Xiubo Li43550822013-12-17 11:24:38 +0800542 break;
Xiubo Li43550822013-12-17 11:24:38 +0800543 case SNDRV_PCM_TRIGGER_STOP:
544 case SNDRV_PCM_TRIGGER_SUSPEND:
545 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
Nicolin Chene6b39842014-04-01 11:17:06 +0800546 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
547 FSL_SAI_CSR_FRDE, 0);
Nicolin Chen8abba5d2014-04-01 11:17:07 +0800548 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
549 FSL_SAI_CSR_xIE_MASK, 0);
Xiubo Lie5d0fa92013-12-25 12:40:04 +0800550
Nicolin Chenf84526c2014-04-11 22:10:00 +0800551 /* Check if the opposite FRDE is also disabled */
Nicolin Chenf4075a82014-07-23 19:23:38 +0800552 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
553 if (!(xcsr & FSL_SAI_CSR_FRDE)) {
Nicolin Cheneff952b2014-07-17 21:21:37 +0800554 /* Disable both directions and reset their FIFOs */
Nicolin Chene6b39842014-04-01 11:17:06 +0800555 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
Nicolin Chenc44b56a2014-07-23 19:23:39 +0800556 FSL_SAI_CSR_TERE, 0);
Nicolin Chene6b39842014-04-01 11:17:06 +0800557 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
Nicolin Chenc44b56a2014-07-23 19:23:39 +0800558 FSL_SAI_CSR_TERE, 0);
559
560 /* TERE will remain set till the end of current frame */
561 do {
562 udelay(10);
563 regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
564 } while (--count && xcsr & FSL_SAI_CSR_TERE);
565
566 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
567 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
568 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
569 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
Zidan Wang3e3f8bd2015-12-18 16:53:41 +0800570
571 /*
572 * For sai master mode, after several open/close sai,
573 * there will be no frame clock, and can't recover
574 * anymore. Add software reset to fix this issue.
575 * This is a hardware bug, and will be fix in the
576 * next sai version.
577 */
578 if (!sai->is_slave_mode) {
579 /* Software Reset for both Tx and Rx */
580 regmap_write(sai->regmap,
581 FSL_SAI_TCSR, FSL_SAI_CSR_SR);
582 regmap_write(sai->regmap,
583 FSL_SAI_RCSR, FSL_SAI_CSR_SR);
584 /* Clear SR bit to finish the reset */
585 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
586 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
587 }
Nicolin Chene6b39842014-04-01 11:17:06 +0800588 }
Xiubo Li43550822013-12-17 11:24:38 +0800589 break;
590 default:
591 return -EINVAL;
592 }
593
594 return 0;
595}
596
597static int fsl_sai_startup(struct snd_pcm_substream *substream,
598 struct snd_soc_dai *cpu_dai)
599{
Xiubo Li43550822013-12-17 11:24:38 +0800600 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
Nicolin Chen2a266f82014-04-11 18:30:09 +0800601 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
Nicolin Chenca3e35c2014-04-10 23:26:15 +0800602 struct device *dev = &sai->pdev->dev;
Nicolin Chenca3e35c2014-04-10 23:26:15 +0800603 int ret;
604
605 ret = clk_prepare_enable(sai->bus_clk);
606 if (ret) {
607 dev_err(dev, "failed to enable bus clock: %d\n", ret);
608 return ret;
609 }
Xiubo Li43550822013-12-17 11:24:38 +0800610
Nicolin Chen2a266f82014-04-11 18:30:09 +0800611 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
Xiubo Li78957fc2014-02-08 14:38:28 +0800612 FSL_SAI_CR3_TRCE);
613
Zidan Wangc5f48232015-05-11 18:24:43 +0800614 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
615 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
616
617 return ret;
Xiubo Li43550822013-12-17 11:24:38 +0800618}
619
620static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
621 struct snd_soc_dai *cpu_dai)
622{
623 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
Nicolin Chen2a266f82014-04-11 18:30:09 +0800624 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
Xiubo Li43550822013-12-17 11:24:38 +0800625
Nicolin Chen2a266f82014-04-11 18:30:09 +0800626 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
Nicolin Chenca3e35c2014-04-10 23:26:15 +0800627
628 clk_disable_unprepare(sai->bus_clk);
Xiubo Li43550822013-12-17 11:24:38 +0800629}
630
631static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
632 .set_sysclk = fsl_sai_set_dai_sysclk,
633 .set_fmt = fsl_sai_set_dai_fmt,
Zidan Wangc1df2962015-11-24 15:31:54 +0800634 .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
Xiubo Li43550822013-12-17 11:24:38 +0800635 .hw_params = fsl_sai_hw_params,
Zidan Wangc3ecef22015-05-11 18:24:41 +0800636 .hw_free = fsl_sai_hw_free,
Xiubo Li43550822013-12-17 11:24:38 +0800637 .trigger = fsl_sai_trigger,
638 .startup = fsl_sai_startup,
639 .shutdown = fsl_sai_shutdown,
640};
641
642static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
643{
644 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
Xiubo Lie6dc12d2013-12-25 11:20:14 +0800645
Nicolin Chen376d1a92014-08-05 17:20:21 +0800646 /* Software Reset for both Tx and Rx */
647 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
648 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
649 /* Clear SR bit to finish the reset */
650 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
651 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
652
Xiubo Li78957fc2014-02-08 14:38:28 +0800653 regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
654 FSL_SAI_MAXBURST_TX * 2);
655 regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
656 FSL_SAI_MAXBURST_RX - 1);
Xiubo Li43550822013-12-17 11:24:38 +0800657
Xiubo Lidd9f4062013-12-20 12:35:33 +0800658 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
659 &sai->dma_params_rx);
Xiubo Li43550822013-12-17 11:24:38 +0800660
661 snd_soc_dai_set_drvdata(cpu_dai, sai);
662
663 return 0;
664}
665
Xiubo Li43550822013-12-17 11:24:38 +0800666static struct snd_soc_dai_driver fsl_sai_dai = {
667 .probe = fsl_sai_dai_probe,
Xiubo Li43550822013-12-17 11:24:38 +0800668 .playback = {
Nicolin Chen20d5b762014-07-30 11:10:27 +0800669 .stream_name = "CPU-Playback",
Xiubo Li43550822013-12-17 11:24:38 +0800670 .channels_min = 1,
671 .channels_max = 2,
Zidan Wangc5f48232015-05-11 18:24:43 +0800672 .rate_min = 8000,
673 .rate_max = 192000,
674 .rates = SNDRV_PCM_RATE_KNOT,
Xiubo Li43550822013-12-17 11:24:38 +0800675 .formats = FSL_SAI_FORMATS,
676 },
677 .capture = {
Nicolin Chen20d5b762014-07-30 11:10:27 +0800678 .stream_name = "CPU-Capture",
Xiubo Li43550822013-12-17 11:24:38 +0800679 .channels_min = 1,
680 .channels_max = 2,
Zidan Wangc5f48232015-05-11 18:24:43 +0800681 .rate_min = 8000,
682 .rate_max = 192000,
683 .rates = SNDRV_PCM_RATE_KNOT,
Xiubo Li43550822013-12-17 11:24:38 +0800684 .formats = FSL_SAI_FORMATS,
685 },
686 .ops = &fsl_sai_pcm_dai_ops,
687};
688
689static const struct snd_soc_component_driver fsl_component = {
690 .name = "fsl-sai",
691};
692
Zidan Wang3f6f5b02015-10-26 15:19:03 +0800693static struct reg_default fsl_sai_reg_defaults[] = {
694 {FSL_SAI_TCR1, 0},
695 {FSL_SAI_TCR2, 0},
696 {FSL_SAI_TCR3, 0},
697 {FSL_SAI_TCR4, 0},
698 {FSL_SAI_TCR5, 0},
699 {FSL_SAI_TDR, 0},
700 {FSL_SAI_TMR, 0},
701 {FSL_SAI_RCR1, 0},
702 {FSL_SAI_RCR2, 0},
703 {FSL_SAI_RCR3, 0},
704 {FSL_SAI_RCR4, 0},
705 {FSL_SAI_RCR5, 0},
706 {FSL_SAI_RMR, 0},
707};
708
Xiubo Li78957fc2014-02-08 14:38:28 +0800709static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
710{
711 switch (reg) {
712 case FSL_SAI_TCSR:
713 case FSL_SAI_TCR1:
714 case FSL_SAI_TCR2:
715 case FSL_SAI_TCR3:
716 case FSL_SAI_TCR4:
717 case FSL_SAI_TCR5:
718 case FSL_SAI_TFR:
719 case FSL_SAI_TMR:
720 case FSL_SAI_RCSR:
721 case FSL_SAI_RCR1:
722 case FSL_SAI_RCR2:
723 case FSL_SAI_RCR3:
724 case FSL_SAI_RCR4:
725 case FSL_SAI_RCR5:
726 case FSL_SAI_RDR:
727 case FSL_SAI_RFR:
728 case FSL_SAI_RMR:
729 return true;
730 default:
731 return false;
732 }
733}
734
735static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
736{
737 switch (reg) {
Zidan Wang1fde5e82015-09-18 11:09:10 +0800738 case FSL_SAI_TCSR:
739 case FSL_SAI_RCSR:
Xiubo Li78957fc2014-02-08 14:38:28 +0800740 case FSL_SAI_TFR:
741 case FSL_SAI_RFR:
Xiubo Li78957fc2014-02-08 14:38:28 +0800742 case FSL_SAI_RDR:
743 return true;
744 default:
745 return false;
746 }
Xiubo Li78957fc2014-02-08 14:38:28 +0800747}
748
749static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
750{
751 switch (reg) {
752 case FSL_SAI_TCSR:
753 case FSL_SAI_TCR1:
754 case FSL_SAI_TCR2:
755 case FSL_SAI_TCR3:
756 case FSL_SAI_TCR4:
757 case FSL_SAI_TCR5:
758 case FSL_SAI_TDR:
759 case FSL_SAI_TMR:
760 case FSL_SAI_RCSR:
761 case FSL_SAI_RCR1:
762 case FSL_SAI_RCR2:
763 case FSL_SAI_RCR3:
764 case FSL_SAI_RCR4:
765 case FSL_SAI_RCR5:
766 case FSL_SAI_RMR:
767 return true;
768 default:
769 return false;
770 }
771}
772
Xiubo Li014fd222014-08-25 11:31:02 +0800773static const struct regmap_config fsl_sai_regmap_config = {
Xiubo Li78957fc2014-02-08 14:38:28 +0800774 .reg_bits = 32,
775 .reg_stride = 4,
776 .val_bits = 32,
777
778 .max_register = FSL_SAI_RMR,
Zidan Wang3f6f5b02015-10-26 15:19:03 +0800779 .reg_defaults = fsl_sai_reg_defaults,
780 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults),
Xiubo Li78957fc2014-02-08 14:38:28 +0800781 .readable_reg = fsl_sai_readable_reg,
782 .volatile_reg = fsl_sai_volatile_reg,
783 .writeable_reg = fsl_sai_writeable_reg,
Zidan Wang1fde5e82015-09-18 11:09:10 +0800784 .cache_type = REGCACHE_FLAT,
Xiubo Li78957fc2014-02-08 14:38:28 +0800785};
786
Xiubo Li43550822013-12-17 11:24:38 +0800787static int fsl_sai_probe(struct platform_device *pdev)
788{
Nicolin Chen4e3a99f2013-12-20 16:41:05 +0800789 struct device_node *np = pdev->dev.of_node;
Xiubo Li43550822013-12-17 11:24:38 +0800790 struct fsl_sai *sai;
Fabio Estevam4d245852016-05-04 19:33:59 -0300791 struct regmap *gpr;
Xiubo Li43550822013-12-17 11:24:38 +0800792 struct resource *res;
Xiubo Li78957fc2014-02-08 14:38:28 +0800793 void __iomem *base;
Nicolin Chenca3e35c2014-04-10 23:26:15 +0800794 char tmp[8];
795 int irq, ret, i;
Fabio Estevam4d245852016-05-04 19:33:59 -0300796 int index;
Xiubo Li43550822013-12-17 11:24:38 +0800797
798 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
799 if (!sai)
800 return -ENOMEM;
801
Nicolin Chene2681a12014-03-27 19:06:59 +0800802 sai->pdev = pdev;
803
Fabio Estevam6ea9c7d2016-08-16 21:00:54 -0300804 if (of_device_is_compatible(np, "fsl,imx6sx-sai") ||
805 of_device_is_compatible(np, "fsl,imx6ul-sai"))
Nicolin Chenc7540642014-04-01 19:34:09 +0800806 sai->sai_on_imx = true;
807
Xiubo Lieadb0012014-08-29 15:12:12 +0800808 sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
Xiubo Li78957fc2014-02-08 14:38:28 +0800809
810 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
811 base = devm_ioremap_resource(&pdev->dev, res);
812 if (IS_ERR(base))
813 return PTR_ERR(base);
814
815 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
Nicolin Chenca3e35c2014-04-10 23:26:15 +0800816 "bus", base, &fsl_sai_regmap_config);
817
818 /* Compatible with old DTB cases */
819 if (IS_ERR(sai->regmap))
820 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
821 "sai", base, &fsl_sai_regmap_config);
Xiubo Li78957fc2014-02-08 14:38:28 +0800822 if (IS_ERR(sai->regmap)) {
823 dev_err(&pdev->dev, "regmap init failed\n");
824 return PTR_ERR(sai->regmap);
Xiubo Li43550822013-12-17 11:24:38 +0800825 }
826
Nicolin Chenca3e35c2014-04-10 23:26:15 +0800827 /* No error out for old DTB cases but only mark the clock NULL */
828 sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
829 if (IS_ERR(sai->bus_clk)) {
830 dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
831 PTR_ERR(sai->bus_clk));
832 sai->bus_clk = NULL;
833 }
834
Zidan Wangc3ecef22015-05-11 18:24:41 +0800835 sai->mclk_clk[0] = sai->bus_clk;
836 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
837 sprintf(tmp, "mclk%d", i);
Nicolin Chenca3e35c2014-04-10 23:26:15 +0800838 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
839 if (IS_ERR(sai->mclk_clk[i])) {
840 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
841 i + 1, PTR_ERR(sai->mclk_clk[i]));
842 sai->mclk_clk[i] = NULL;
843 }
844 }
845
Nicolin Chene2681a12014-03-27 19:06:59 +0800846 irq = platform_get_irq(pdev, 0);
847 if (irq < 0) {
Fabio Estevam09542372015-01-07 13:44:34 -0200848 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
Nicolin Chene2681a12014-03-27 19:06:59 +0800849 return irq;
850 }
851
852 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
853 if (ret) {
854 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
855 return ret;
856 }
857
Nicolin Chen08fdf652014-08-05 15:32:05 +0800858 /* Sync Tx with Rx as default by following old DT binding */
859 sai->synchronous[RX] = true;
860 sai->synchronous[TX] = false;
861 fsl_sai_dai.symmetric_rates = 1;
862 fsl_sai_dai.symmetric_channels = 1;
863 fsl_sai_dai.symmetric_samplebits = 1;
864
Nicolin Chence7344a2014-08-08 18:41:19 +0800865 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
866 of_find_property(np, "fsl,sai-asynchronous", NULL)) {
867 /* error out if both synchronous and asynchronous are present */
868 dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
869 return -EINVAL;
870 }
871
Nicolin Chen08fdf652014-08-05 15:32:05 +0800872 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
873 /* Sync Rx with Tx */
874 sai->synchronous[RX] = false;
875 sai->synchronous[TX] = true;
876 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
877 /* Discard all settings for asynchronous mode */
878 sai->synchronous[RX] = false;
879 sai->synchronous[TX] = false;
880 fsl_sai_dai.symmetric_rates = 0;
881 fsl_sai_dai.symmetric_channels = 0;
882 fsl_sai_dai.symmetric_samplebits = 0;
883 }
884
Fabio Estevam4d245852016-05-04 19:33:59 -0300885 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
Fabio Estevam6ea9c7d2016-08-16 21:00:54 -0300886 of_device_is_compatible(np, "fsl,imx6ul-sai")) {
Fabio Estevam4d245852016-05-04 19:33:59 -0300887 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
888 if (IS_ERR(gpr)) {
889 dev_err(&pdev->dev, "cannot find iomuxc registers\n");
890 return PTR_ERR(gpr);
891 }
892
893 index = of_alias_get_id(np, "sai");
894 if (index < 0)
895 return index;
896
897 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
898 MCLK_DIR(index));
899 }
900
Xiubo Li43550822013-12-17 11:24:38 +0800901 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
902 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
903 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
904 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
905
Xiubo Li43550822013-12-17 11:24:38 +0800906 platform_set_drvdata(pdev, sai);
907
908 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
909 &fsl_sai_dai, 1);
910 if (ret)
911 return ret;
912
Nicolin Chenc7540642014-04-01 19:34:09 +0800913 if (sai->sai_on_imx)
Shengjiu Wang0d69e0d2015-06-23 18:23:53 +0800914 return imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
Nicolin Chenc7540642014-04-01 19:34:09 +0800915 else
Lars-Peter Clausenacde50a2015-04-27 12:44:25 +0200916 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
Xiubo Li43550822013-12-17 11:24:38 +0800917}
918
919static const struct of_device_id fsl_sai_ids[] = {
920 { .compatible = "fsl,vf610-sai", },
Nicolin Chenc7540642014-04-01 19:34:09 +0800921 { .compatible = "fsl,imx6sx-sai", },
Fabio Estevam1593af62016-05-04 19:33:58 -0300922 { .compatible = "fsl,imx6ul-sai", },
Xiubo Li43550822013-12-17 11:24:38 +0800923 { /* sentinel */ }
924};
Luis de Bethencourtc7592412015-09-03 12:58:23 +0200925MODULE_DEVICE_TABLE(of, fsl_sai_ids);
Xiubo Li43550822013-12-17 11:24:38 +0800926
Nicolin Chen739146b2015-10-22 15:56:40 -0700927#ifdef CONFIG_PM_SLEEP
Zidan Wang1fde5e82015-09-18 11:09:10 +0800928static int fsl_sai_suspend(struct device *dev)
929{
930 struct fsl_sai *sai = dev_get_drvdata(dev);
931
932 regcache_cache_only(sai->regmap, true);
933 regcache_mark_dirty(sai->regmap);
934
935 return 0;
936}
937
938static int fsl_sai_resume(struct device *dev)
939{
940 struct fsl_sai *sai = dev_get_drvdata(dev);
941
942 regcache_cache_only(sai->regmap, false);
943 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
944 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
Xiubo Li512feb42016-01-15 19:35:24 +0800945 usleep_range(1000, 2000);
Zidan Wang1fde5e82015-09-18 11:09:10 +0800946 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
947 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
948 return regcache_sync(sai->regmap);
949}
950#endif /* CONFIG_PM_SLEEP */
951
952static const struct dev_pm_ops fsl_sai_pm_ops = {
953 SET_SYSTEM_SLEEP_PM_OPS(fsl_sai_suspend, fsl_sai_resume)
954};
955
Xiubo Li43550822013-12-17 11:24:38 +0800956static struct platform_driver fsl_sai_driver = {
957 .probe = fsl_sai_probe,
Xiubo Li43550822013-12-17 11:24:38 +0800958 .driver = {
959 .name = "fsl-sai",
Zidan Wang1fde5e82015-09-18 11:09:10 +0800960 .pm = &fsl_sai_pm_ops,
Xiubo Li43550822013-12-17 11:24:38 +0800961 .of_match_table = fsl_sai_ids,
962 },
963};
964module_platform_driver(fsl_sai_driver);
965
966MODULE_DESCRIPTION("Freescale Soc SAI Interface");
967MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
968MODULE_ALIAS("platform:fsl-sai");
969MODULE_LICENSE("GPL");