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Bryan Wu1394f032007-05-06 14:50:22 -07001/*
Robin Getz96f10502009-09-24 14:11:24 +00002 * Set up the interrupt priorities
Bryan Wu1394f032007-05-06 14:50:22 -07003 *
Robin Getz96f10502009-09-24 14:11:24 +00004 * Copyright 2004-2009 Analog Devices Inc.
5 * 2003 Bas Vermeulen <bas@buyways.nl>
6 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
7 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
9 * 1996 Roman Zippel
Bryan Wu1394f032007-05-06 14:50:22 -070010 *
Robin Getz96f10502009-09-24 14:11:24 +000011 * Licensed under the GPL-2
Bryan Wu1394f032007-05-06 14:50:22 -070012 */
13
14#include <linux/module.h>
15#include <linux/kernel_stat.h>
16#include <linux/seq_file.h>
17#include <linux/irq.h>
Philippe Gerum5b5da4c2011-03-17 02:12:48 -040018#include <linux/sched.h>
Steven Miao4f6b6002012-05-16 17:56:51 +080019#include <linux/syscore_ops.h>
Bjorn Helgaas288e6ea2016-02-02 13:53:23 -060020#include <linux/gpio.h>
Steven Miao4f6b6002012-05-16 17:56:51 +080021#include <asm/delay.h>
Yi Li6a01f232009-01-07 23:14:39 +080022#ifdef CONFIG_IPIPE
23#include <linux/ipipe.h>
24#endif
Bryan Wu1394f032007-05-06 14:50:22 -070025#include <asm/traps.h>
26#include <asm/blackfin.h>
Bryan Wu1394f032007-05-06 14:50:22 -070027#include <asm/irq_handler.h>
Mike Frysinger761ec442009-10-15 17:12:05 +000028#include <asm/dpmc.h>
Sonic Zhang06051fd2012-07-04 19:22:55 +080029#include <asm/traps.h>
Bryan Wu1394f032007-05-06 14:50:22 -070030
Bryan Wu1394f032007-05-06 14:50:22 -070031/*
32 * NOTES:
33 * - we have separated the physical Hardware interrupt from the
34 * levels that the LINUX kernel sees (see the description in irq.h)
35 * -
36 */
37
Graf Yang6b3087c2009-01-07 23:14:39 +080038#ifndef CONFIG_SMP
Mike Frysingera99bbcc2007-10-22 00:19:31 +080039/* Initialize this to an actual value to force it into the .data
40 * section so that we know it is properly initialized at entry into
41 * the kernel but before bss is initialized to zero (which is where
42 * it would live otherwise). The 0x1f magic represents the IRQs we
43 * cannot actually mask out in hardware.
44 */
Mike Frysinger40059782008-11-18 17:48:22 +080045unsigned long bfin_irq_flags = 0x1f;
46EXPORT_SYMBOL(bfin_irq_flags);
Graf Yang6b3087c2009-01-07 23:14:39 +080047#endif
Bryan Wu1394f032007-05-06 14:50:22 -070048
Michael Hennerichcfefe3c2008-02-09 04:12:37 +080049#ifdef CONFIG_PM
50unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
Michael Hennerich4a88d0c2008-08-05 17:38:41 +080051unsigned vr_wakeup;
Michael Hennerichcfefe3c2008-02-09 04:12:37 +080052#endif
53
Sonic Zhang11b27cb2012-06-28 19:16:48 +080054#ifndef SEC_GCTL
Mike Frysingere9e334c2011-03-30 00:43:52 -040055static struct ivgx {
Michael Hennerich464abc52008-02-25 13:50:20 +080056 /* irq number for request_irq, available in mach-bf5xx/irq.h */
Roy Huang24a07a12007-07-12 22:41:45 +080057 unsigned int irqno;
Bryan Wu1394f032007-05-06 14:50:22 -070058 /* corresponding bit in the SIC_ISR register */
Roy Huang24a07a12007-07-12 22:41:45 +080059 unsigned int isrflag;
Bryan Wu1394f032007-05-06 14:50:22 -070060} ivg_table[NR_PERI_INTS];
61
Mike Frysingere9e334c2011-03-30 00:43:52 -040062static struct ivg_slice {
Bryan Wu1394f032007-05-06 14:50:22 -070063 /* position of first irq in ivg_table for given ivg */
64 struct ivgx *ifirst;
65 struct ivgx *istop;
66} ivg7_13[IVG13 - IVG7 + 1];
67
Bryan Wu1394f032007-05-06 14:50:22 -070068
69/*
70 * Search SIC_IAR and fill tables with the irqvalues
71 * and their positions in the SIC_ISR register.
72 */
73static void __init search_IAR(void)
74{
75 unsigned ivg, irq_pos = 0;
76 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
Mike Frysinger80fcdb92010-04-22 21:15:00 +000077 int irqN;
Bryan Wu1394f032007-05-06 14:50:22 -070078
Michael Hennerich34e0fc82007-07-12 16:17:18 +080079 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
Bryan Wu1394f032007-05-06 14:50:22 -070080
Mike Frysinger80fcdb92010-04-22 21:15:00 +000081 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
82 int irqn;
Steven Miao4f6b6002012-05-16 17:56:51 +080083 u32 iar =
84 bfin_read32((unsigned long *)SIC_IAR0 +
Mike Frysinger80fcdb92010-04-22 21:15:00 +000085#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
86 defined(CONFIG_BF538) || defined(CONFIG_BF539)
87 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
Michael Hennerich59003142007-10-21 16:54:27 +080088#else
Mike Frysinger80fcdb92010-04-22 21:15:00 +000089 (irqN >> 3)
Michael Hennerich59003142007-10-21 16:54:27 +080090#endif
Mike Frysinger80fcdb92010-04-22 21:15:00 +000091 );
Mike Frysinger80fcdb92010-04-22 21:15:00 +000092 for (irqn = irqN; irqn < irqN + 4; ++irqn) {
93 int iar_shift = (irqn & 7) * 4;
94 if (ivg == (0xf & (iar >> iar_shift))) {
95 ivg_table[irq_pos].irqno = IVG7 + irqn;
96 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
97 ivg7_13[ivg].istop++;
98 irq_pos++;
99 }
Bryan Wu1394f032007-05-06 14:50:22 -0700100 }
101 }
102 }
103}
Steven Miao4f6b6002012-05-16 17:56:51 +0800104#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700105
106/*
Michael Hennerich464abc52008-02-25 13:50:20 +0800107 * This is for core internal IRQs
Bryan Wu1394f032007-05-06 14:50:22 -0700108 */
Mike Frysingerf58c3272011-04-15 03:08:20 -0400109void bfin_ack_noop(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700110{
111 /* Dummy function. */
112}
113
Thomas Gleixner4f19ea42011-02-06 18:23:27 +0000114static void bfin_core_mask_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700115{
Thomas Gleixner4f19ea42011-02-06 18:23:27 +0000116 bfin_irq_flags &= ~(1 << d->irq);
David Howells3b139cd2010-10-07 14:08:52 +0100117 if (!hard_irqs_disabled())
118 hard_local_irq_enable();
Bryan Wu1394f032007-05-06 14:50:22 -0700119}
120
Thomas Gleixner4f19ea42011-02-06 18:23:27 +0000121static void bfin_core_unmask_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700122{
Thomas Gleixner4f19ea42011-02-06 18:23:27 +0000123 bfin_irq_flags |= 1 << d->irq;
Bryan Wu1394f032007-05-06 14:50:22 -0700124 /*
125 * If interrupts are enabled, IMASK must contain the same value
Mike Frysinger40059782008-11-18 17:48:22 +0800126 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
Bryan Wu1394f032007-05-06 14:50:22 -0700127 * are currently disabled we need not do anything; one of the
128 * callers will take care of setting IMASK to the proper value
129 * when reenabling interrupts.
Mike Frysinger40059782008-11-18 17:48:22 +0800130 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
Bryan Wu1394f032007-05-06 14:50:22 -0700131 * what we need.
132 */
David Howells3b139cd2010-10-07 14:08:52 +0100133 if (!hard_irqs_disabled())
134 hard_local_irq_enable();
Bryan Wu1394f032007-05-06 14:50:22 -0700135 return;
136}
137
Sonic Zhang86794b42012-12-14 11:19:24 +0800138#ifndef SEC_GCTL
Mike Frysingerf58c3272011-04-15 03:08:20 -0400139void bfin_internal_mask_irq(unsigned int irq)
Bryan Wu1394f032007-05-06 14:50:22 -0700140{
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400141 unsigned long flags = hard_local_irq_save();
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400142#ifdef SIC_IMASK0
Sonic Zhang86794b42012-12-14 11:19:24 +0800143 unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
144 unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
Bryan Wuc04d66b2007-07-12 17:26:31 +0800145 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
Steven Miao4f6b6002012-05-16 17:56:51 +0800146 ~(1 << mask_bit));
147# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
Graf Yang6b3087c2009-01-07 23:14:39 +0800148 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
Steven Miao4f6b6002012-05-16 17:56:51 +0800149 ~(1 << mask_bit));
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400150# endif
151#else
152 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
Sonic Zhang86794b42012-12-14 11:19:24 +0800153 ~(1 << BFIN_SYSIRQ(irq)));
Steven Miao4f6b6002012-05-16 17:56:51 +0800154#endif /* end of SIC_IMASK0 */
David Howells3b139cd2010-10-07 14:08:52 +0100155 hard_local_irq_restore(flags);
Bryan Wu1394f032007-05-06 14:50:22 -0700156}
157
Thomas Gleixnerff43a672011-02-06 18:23:29 +0000158static void bfin_internal_mask_irq_chip(struct irq_data *d)
159{
160 bfin_internal_mask_irq(d->irq);
161}
162
Sonic Zhang0325f252009-12-28 07:29:57 +0000163#ifdef CONFIG_SMP
Steven Miao4f6b6002012-05-16 17:56:51 +0800164void bfin_internal_unmask_irq_affinity(unsigned int irq,
Sonic Zhang0325f252009-12-28 07:29:57 +0000165 const struct cpumask *affinity)
166#else
Mike Frysingerf58c3272011-04-15 03:08:20 -0400167void bfin_internal_unmask_irq(unsigned int irq)
Sonic Zhang0325f252009-12-28 07:29:57 +0000168#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700169{
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400170 unsigned long flags = hard_local_irq_save();
Philippe Gerum9bd50df2009-03-04 16:52:38 +0800171
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400172#ifdef SIC_IMASK0
Sonic Zhang86794b42012-12-14 11:19:24 +0800173 unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
174 unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400175# ifdef CONFIG_SMP
Sonic Zhang0325f252009-12-28 07:29:57 +0000176 if (cpumask_test_cpu(0, affinity))
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400177# endif
Sonic Zhang0325f252009-12-28 07:29:57 +0000178 bfin_write_SIC_IMASK(mask_bank,
Steven Miao4f6b6002012-05-16 17:56:51 +0800179 bfin_read_SIC_IMASK(mask_bank) |
180 (1 << mask_bit));
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400181# ifdef CONFIG_SMP
Sonic Zhang0325f252009-12-28 07:29:57 +0000182 if (cpumask_test_cpu(1, affinity))
183 bfin_write_SICB_IMASK(mask_bank,
Steven Miao4f6b6002012-05-16 17:56:51 +0800184 bfin_read_SICB_IMASK(mask_bank) |
185 (1 << mask_bit));
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400186# endif
187#else
188 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
Sonic Zhang86794b42012-12-14 11:19:24 +0800189 (1 << BFIN_SYSIRQ(irq)));
Steven Miao4f6b6002012-05-16 17:56:51 +0800190#endif
191 hard_local_irq_restore(flags);
192}
193
Sonic Zhang86794b42012-12-14 11:19:24 +0800194#ifdef CONFIG_SMP
195static void bfin_internal_unmask_irq_chip(struct irq_data *d)
196{
Jiang Liu247bd4f2015-07-13 20:34:56 +0000197 bfin_internal_unmask_irq_affinity(d->irq,
198 irq_data_get_affinity_mask(d));
Sonic Zhang86794b42012-12-14 11:19:24 +0800199}
200
201static int bfin_internal_set_affinity(struct irq_data *d,
202 const struct cpumask *mask, bool force)
203{
204 bfin_internal_mask_irq(d->irq);
205 bfin_internal_unmask_irq_affinity(d->irq, mask);
206
207 return 0;
208}
209#else
210static void bfin_internal_unmask_irq_chip(struct irq_data *d)
211{
212 bfin_internal_unmask_irq(d->irq);
213}
214#endif
215
216#if defined(CONFIG_PM)
217int bfin_internal_set_wake(unsigned int irq, unsigned int state)
218{
219 u32 bank, bit, wakeup = 0;
220 unsigned long flags;
221 bank = BFIN_SYSIRQ(irq) / 32;
222 bit = BFIN_SYSIRQ(irq) % 32;
223
224 switch (irq) {
225#ifdef IRQ_RTC
226 case IRQ_RTC:
227 wakeup |= WAKE;
228 break;
229#endif
230#ifdef IRQ_CAN0_RX
231 case IRQ_CAN0_RX:
232 wakeup |= CANWE;
233 break;
234#endif
235#ifdef IRQ_CAN1_RX
236 case IRQ_CAN1_RX:
237 wakeup |= CANWE;
238 break;
239#endif
240#ifdef IRQ_USB_INT0
241 case IRQ_USB_INT0:
242 wakeup |= USBWE;
243 break;
244#endif
245#ifdef CONFIG_BF54x
246 case IRQ_CNT:
247 wakeup |= ROTWE;
248 break;
249#endif
250 default:
251 break;
252 }
253
254 flags = hard_local_irq_save();
255
256 if (state) {
257 bfin_sic_iwr[bank] |= (1 << bit);
258 vr_wakeup |= wakeup;
259
260 } else {
261 bfin_sic_iwr[bank] &= ~(1 << bit);
262 vr_wakeup &= ~wakeup;
263 }
264
265 hard_local_irq_restore(flags);
266
267 return 0;
268}
269
270static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
271{
272 return bfin_internal_set_wake(d->irq, state);
273}
274#else
275inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
276{
277 return 0;
278}
279# define bfin_internal_set_wake_chip NULL
280#endif
281
282#else /* SEC_GCTL */
Steven Miao4f6b6002012-05-16 17:56:51 +0800283static void bfin_sec_preflow_handler(struct irq_data *d)
284{
285 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800286 unsigned int sid = BFIN_SYSIRQ(d->irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800287
288 bfin_write_SEC_SCI(0, SEC_CSID, sid);
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400289
David Howells3b139cd2010-10-07 14:08:52 +0100290 hard_local_irq_restore(flags);
Bryan Wu1394f032007-05-06 14:50:22 -0700291}
292
Steven Miao4f6b6002012-05-16 17:56:51 +0800293static void bfin_sec_mask_ack_irq(struct irq_data *d)
294{
295 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800296 unsigned int sid = BFIN_SYSIRQ(d->irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800297
298 bfin_write_SEC_SCI(0, SEC_CSID, sid);
299
300 hard_local_irq_restore(flags);
301}
302
303static void bfin_sec_unmask_irq(struct irq_data *d)
304{
305 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800306 unsigned int sid = BFIN_SYSIRQ(d->irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800307
308 bfin_write32(SEC_END, sid);
309
310 hard_local_irq_restore(flags);
311}
312
313static void bfin_sec_enable_ssi(unsigned int sid)
314{
315 unsigned long flags = hard_local_irq_save();
316 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
317
318 reg_sctl |= SEC_SCTL_SRC_EN;
319 bfin_write_SEC_SCTL(sid, reg_sctl);
320
321 hard_local_irq_restore(flags);
322}
323
324static void bfin_sec_disable_ssi(unsigned int sid)
325{
326 unsigned long flags = hard_local_irq_save();
327 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
328
329 reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
330 bfin_write_SEC_SCTL(sid, reg_sctl);
331
332 hard_local_irq_restore(flags);
333}
334
335static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
336{
337 unsigned long flags = hard_local_irq_save();
338 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
339
340 reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
341 bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
342
343 hard_local_irq_restore(flags);
344}
345
346static void bfin_sec_enable_sci(unsigned int sid)
347{
348 unsigned long flags = hard_local_irq_save();
349 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
350
Sonic Zhang86794b42012-12-14 11:19:24 +0800351 if (sid == BFIN_SYSIRQ(IRQ_WATCH0))
Steven Miao4f6b6002012-05-16 17:56:51 +0800352 reg_sctl |= SEC_SCTL_FAULT_EN;
353 else
354 reg_sctl |= SEC_SCTL_INT_EN;
355 bfin_write_SEC_SCTL(sid, reg_sctl);
356
357 hard_local_irq_restore(flags);
358}
359
360static void bfin_sec_disable_sci(unsigned int sid)
361{
362 unsigned long flags = hard_local_irq_save();
363 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
364
365 reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
366 bfin_write_SEC_SCTL(sid, reg_sctl);
367
368 hard_local_irq_restore(flags);
369}
370
371static void bfin_sec_enable(struct irq_data *d)
372{
373 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800374 unsigned int sid = BFIN_SYSIRQ(d->irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800375
376 bfin_sec_enable_sci(sid);
377 bfin_sec_enable_ssi(sid);
378
379 hard_local_irq_restore(flags);
380}
381
382static void bfin_sec_disable(struct irq_data *d)
383{
384 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800385 unsigned int sid = BFIN_SYSIRQ(d->irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800386
387 bfin_sec_disable_sci(sid);
388 bfin_sec_disable_ssi(sid);
389
390 hard_local_irq_restore(flags);
391}
392
Sonic Zhange0a59312012-06-29 18:19:29 +0800393static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority)
394{
395 unsigned long flags = hard_local_irq_save();
396 uint32_t reg_sctl;
397 int i;
398
399 bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels);
400
401 for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) {
402 reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO;
403 reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET;
404 bfin_write_SEC_SCTL(i, reg_sctl);
405 }
406
407 hard_local_irq_restore(flags);
408}
409
Sonic Zhang86794b42012-12-14 11:19:24 +0800410void bfin_sec_raise_irq(unsigned int irq)
Steven Miao4f6b6002012-05-16 17:56:51 +0800411{
412 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800413 unsigned int sid = BFIN_SYSIRQ(irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800414
415 bfin_write32(SEC_RAISE, sid);
416
417 hard_local_irq_restore(flags);
418}
419
420static void init_software_driven_irq(void)
421{
422 bfin_sec_set_ssi_coreid(34, 0);
423 bfin_sec_set_ssi_coreid(35, 1);
Sonic Zhang86794b42012-12-14 11:19:24 +0800424
425 bfin_sec_enable_sci(35);
426 bfin_sec_enable_ssi(35);
Steven Miao4f6b6002012-05-16 17:56:51 +0800427 bfin_sec_set_ssi_coreid(36, 0);
428 bfin_sec_set_ssi_coreid(37, 1);
Sonic Zhang86794b42012-12-14 11:19:24 +0800429 bfin_sec_enable_sci(37);
430 bfin_sec_enable_ssi(37);
Steven Miao4f6b6002012-05-16 17:56:51 +0800431}
432
Steven Miao4f6b6002012-05-16 17:56:51 +0800433void handle_sec_sfi_fault(uint32_t gstat)
434{
435
436}
437
438void handle_sec_sci_fault(uint32_t gstat)
439{
440 uint32_t core_id;
441 uint32_t cstat;
442
443 core_id = gstat & SEC_GSTAT_SCI;
444 cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
445 if (cstat & SEC_CSTAT_ERR) {
446 switch (cstat & SEC_CSTAT_ERRC) {
447 case SEC_CSTAT_ACKERR:
448 printk(KERN_DEBUG "sec ack err\n");
449 break;
450 default:
Masanari Iida9b134942014-08-06 22:31:28 +0900451 printk(KERN_DEBUG "sec sci unknown err\n");
Steven Miao4f6b6002012-05-16 17:56:51 +0800452 }
453 }
454
455}
456
457void handle_sec_ssi_fault(uint32_t gstat)
458{
459 uint32_t sid;
460 uint32_t sstat;
461
462 sid = gstat & SEC_GSTAT_SID;
463 sstat = bfin_read_SEC_SSTAT(sid);
464
465}
466
Sonic Zhang1b601232013-12-04 15:27:47 +0800467void handle_sec_fault(uint32_t sec_gstat)
Steven Miao4f6b6002012-05-16 17:56:51 +0800468{
Steven Miao4f6b6002012-05-16 17:56:51 +0800469 if (sec_gstat & SEC_GSTAT_ERR) {
470
471 switch (sec_gstat & SEC_GSTAT_ERRC) {
472 case 0:
473 handle_sec_sfi_fault(sec_gstat);
474 break;
475 case SEC_GSTAT_SCIERR:
476 handle_sec_sci_fault(sec_gstat);
477 break;
478 case SEC_GSTAT_SSIERR:
479 handle_sec_ssi_fault(sec_gstat);
480 break;
481 }
482
483
484 }
Steven Miao4f6b6002012-05-16 17:56:51 +0800485}
486
Sonic Zhang1b601232013-12-04 15:27:47 +0800487static struct irqaction bfin_fault_irq = {
488 .name = "Blackfin fault",
489};
490
491static irqreturn_t bfin_fault_routine(int irq, void *data)
Sonic Zhang06051fd2012-07-04 19:22:55 +0800492{
493 struct pt_regs *fp = get_irq_regs();
494
Sonic Zhang06051fd2012-07-04 19:22:55 +0800495 switch (irq) {
496 case IRQ_C0_DBL_FAULT:
497 double_fault_c(fp);
498 break;
499 case IRQ_C0_HW_ERR:
500 dump_bfin_process(fp);
501 dump_bfin_mem(fp);
502 show_regs(fp);
503 printk(KERN_NOTICE "Kernel Stack\n");
504 show_stack(current, NULL);
505 print_modules();
Sonic Zhang86794b42012-12-14 11:19:24 +0800506 panic("Core 0 hardware error");
Sonic Zhang06051fd2012-07-04 19:22:55 +0800507 break;
508 case IRQ_C0_NMI_L1_PARITY_ERR:
Sonic Zhang86794b42012-12-14 11:19:24 +0800509 panic("Core 0 NMI L1 parity error");
Sonic Zhang06051fd2012-07-04 19:22:55 +0800510 break;
Sonic Zhang1b601232013-12-04 15:27:47 +0800511 case IRQ_SEC_ERR:
512 pr_err("SEC error\n");
513 handle_sec_fault(bfin_read32(SEC_GSTAT));
514 break;
Sonic Zhang06051fd2012-07-04 19:22:55 +0800515 default:
Sonic Zhang1b601232013-12-04 15:27:47 +0800516 panic("Unknown fault %d", irq);
Sonic Zhang06051fd2012-07-04 19:22:55 +0800517 }
518
Sonic Zhang1b601232013-12-04 15:27:47 +0800519 return IRQ_HANDLED;
Sonic Zhang06051fd2012-07-04 19:22:55 +0800520}
Sonic Zhang86794b42012-12-14 11:19:24 +0800521#endif /* SEC_GCTL */
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800522
Bryan Wu1394f032007-05-06 14:50:22 -0700523static struct irq_chip bfin_core_irqchip = {
Graf Yang763e63c2008-10-08 17:08:15 +0800524 .name = "CORE",
Thomas Gleixner4f19ea42011-02-06 18:23:27 +0000525 .irq_mask = bfin_core_mask_irq,
526 .irq_unmask = bfin_core_unmask_irq,
Bryan Wu1394f032007-05-06 14:50:22 -0700527};
528
Sonic Zhang86794b42012-12-14 11:19:24 +0800529#ifndef SEC_GCTL
Bryan Wu1394f032007-05-06 14:50:22 -0700530static struct irq_chip bfin_internal_irqchip = {
Graf Yang763e63c2008-10-08 17:08:15 +0800531 .name = "INTN",
Thomas Gleixnerff43a672011-02-06 18:23:29 +0000532 .irq_mask = bfin_internal_mask_irq_chip,
533 .irq_unmask = bfin_internal_unmask_irq_chip,
Thomas Gleixnerff43a672011-02-06 18:23:29 +0000534 .irq_disable = bfin_internal_mask_irq_chip,
535 .irq_enable = bfin_internal_unmask_irq_chip,
Sonic Zhang0325f252009-12-28 07:29:57 +0000536#ifdef CONFIG_SMP
Thomas Gleixnerff43a672011-02-06 18:23:29 +0000537 .irq_set_affinity = bfin_internal_set_affinity,
Sonic Zhang0325f252009-12-28 07:29:57 +0000538#endif
Thomas Gleixnerff43a672011-02-06 18:23:29 +0000539 .irq_set_wake = bfin_internal_set_wake_chip,
Bryan Wu1394f032007-05-06 14:50:22 -0700540};
Sonic Zhang86794b42012-12-14 11:19:24 +0800541#else
Steven Miao4f6b6002012-05-16 17:56:51 +0800542static struct irq_chip bfin_sec_irqchip = {
543 .name = "SEC",
544 .irq_mask_ack = bfin_sec_mask_ack_irq,
545 .irq_mask = bfin_sec_mask_ack_irq,
546 .irq_unmask = bfin_sec_unmask_irq,
547 .irq_eoi = bfin_sec_unmask_irq,
548 .irq_disable = bfin_sec_disable,
549 .irq_enable = bfin_sec_enable,
550};
551#endif
552
Mike Frysingerf58c3272011-04-15 03:08:20 -0400553void bfin_handle_irq(unsigned irq)
Yi Li6a01f232009-01-07 23:14:39 +0800554{
555#ifdef CONFIG_IPIPE
556 struct pt_regs regs; /* Contents not used. */
557 ipipe_trace_irq_entry(irq);
558 __ipipe_handle_irq(irq, &regs);
559 ipipe_trace_irq_exit(irq);
560#else /* !CONFIG_IPIPE */
Thomas Gleixnerb10bbbb2011-02-06 18:23:25 +0000561 generic_handle_irq(irq);
Yi Li6a01f232009-01-07 23:14:39 +0800562#endif /* !CONFIG_IPIPE */
563}
564
Michael Hennerichaec59c92010-02-19 15:09:10 +0000565#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
566static int mac_stat_int_mask;
567
568static void bfin_mac_status_ack_irq(unsigned int irq)
569{
570 switch (irq) {
571 case IRQ_MAC_MMCINT:
572 bfin_write_EMAC_MMC_TIRQS(
573 bfin_read_EMAC_MMC_TIRQE() &
574 bfin_read_EMAC_MMC_TIRQS());
575 bfin_write_EMAC_MMC_RIRQS(
576 bfin_read_EMAC_MMC_RIRQE() &
577 bfin_read_EMAC_MMC_RIRQS());
578 break;
579 case IRQ_MAC_RXFSINT:
580 bfin_write_EMAC_RX_STKY(
581 bfin_read_EMAC_RX_IRQE() &
582 bfin_read_EMAC_RX_STKY());
583 break;
584 case IRQ_MAC_TXFSINT:
585 bfin_write_EMAC_TX_STKY(
586 bfin_read_EMAC_TX_IRQE() &
587 bfin_read_EMAC_TX_STKY());
588 break;
589 case IRQ_MAC_WAKEDET:
590 bfin_write_EMAC_WKUP_CTL(
591 bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
592 break;
593 default:
594 /* These bits are W1C */
595 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
596 break;
597 }
598}
599
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000600static void bfin_mac_status_mask_irq(struct irq_data *d)
Michael Hennerichaec59c92010-02-19 15:09:10 +0000601{
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000602 unsigned int irq = d->irq;
603
Michael Hennerichaec59c92010-02-19 15:09:10 +0000604 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
Mike Frysingerf58c3272011-04-15 03:08:20 -0400605#ifdef BF537_FAMILY
Michael Hennerichaec59c92010-02-19 15:09:10 +0000606 switch (irq) {
607 case IRQ_MAC_PHYINT:
608 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
609 break;
610 default:
611 break;
612 }
613#else
614 if (!mac_stat_int_mask)
615 bfin_internal_mask_irq(IRQ_MAC_ERROR);
616#endif
617 bfin_mac_status_ack_irq(irq);
618}
619
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000620static void bfin_mac_status_unmask_irq(struct irq_data *d)
Michael Hennerichaec59c92010-02-19 15:09:10 +0000621{
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000622 unsigned int irq = d->irq;
623
Mike Frysingerf58c3272011-04-15 03:08:20 -0400624#ifdef BF537_FAMILY
Michael Hennerichaec59c92010-02-19 15:09:10 +0000625 switch (irq) {
626 case IRQ_MAC_PHYINT:
627 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
628 break;
629 default:
630 break;
631 }
632#else
633 if (!mac_stat_int_mask)
634 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
635#endif
636 mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
637}
638
639#ifdef CONFIG_PM
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000640int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
Michael Hennerichaec59c92010-02-19 15:09:10 +0000641{
Mike Frysingerf58c3272011-04-15 03:08:20 -0400642#ifdef BF537_FAMILY
Michael Hennerichaec59c92010-02-19 15:09:10 +0000643 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
644#else
645 return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
646#endif
647}
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400648#else
649# define bfin_mac_status_set_wake NULL
Michael Hennerichaec59c92010-02-19 15:09:10 +0000650#endif
651
652static struct irq_chip bfin_mac_status_irqchip = {
653 .name = "MACST",
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000654 .irq_mask = bfin_mac_status_mask_irq,
655 .irq_unmask = bfin_mac_status_unmask_irq,
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000656 .irq_set_wake = bfin_mac_status_set_wake,
Michael Hennerichaec59c92010-02-19 15:09:10 +0000657};
658
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200659void bfin_demux_mac_status_irq(struct irq_desc *inta_desc)
Michael Hennerichaec59c92010-02-19 15:09:10 +0000660{
661 int i, irq = 0;
662 u32 status = bfin_read_EMAC_SYSTAT();
663
Michael Hennerichbedeea62010-08-20 11:59:27 +0000664 for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
Michael Hennerichaec59c92010-02-19 15:09:10 +0000665 if (status & (1L << i)) {
666 irq = IRQ_MAC_PHYINT + i;
667 break;
668 }
669
670 if (irq) {
671 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
672 bfin_handle_irq(irq);
673 } else {
674 bfin_mac_status_ack_irq(irq);
675 pr_debug("IRQ %d:"
Steven Miao4f6b6002012-05-16 17:56:51 +0800676 " MASKED MAC ERROR INTERRUPT ASSERTED\n",
677 irq);
Michael Hennerichaec59c92010-02-19 15:09:10 +0000678 }
679 } else
680 printk(KERN_ERR
Steven Miao4f6b6002012-05-16 17:56:51 +0800681 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
682 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
683 "(EMAC_SYSTAT=0x%X)\n",
684 __func__, __FILE__, __LINE__, status);
Michael Hennerichaec59c92010-02-19 15:09:10 +0000685}
686#endif
687
Thomas Gleixner28438442015-07-13 20:34:57 +0000688static inline void bfin_set_irq_handler(struct irq_data *d, irq_flow_handler_t handle)
Graf Yangbfd15112008-10-08 18:02:44 +0800689{
Yi Li6a01f232009-01-07 23:14:39 +0800690#ifdef CONFIG_IPIPE
Philippe Gerum5b5da4c2011-03-17 02:12:48 -0400691 handle = handle_level_irq;
Yi Li6a01f232009-01-07 23:14:39 +0800692#endif
Thomas Gleixner28438442015-07-13 20:34:57 +0000693 irq_set_handler_locked(d, handle);
Graf Yangbfd15112008-10-08 18:02:44 +0800694}
695
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800696#ifdef CONFIG_GPIO_ADI
Michael Hennerich6fce6a82007-12-24 16:56:12 +0800697
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800698static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
Michael Hennerich8d022372008-11-18 17:48:22 +0800699
Thomas Gleixnere9502852011-02-06 18:23:36 +0000700static void bfin_gpio_ack_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700701{
Michael Hennerich8d022372008-11-18 17:48:22 +0800702 /* AFAIK ack_irq in case mask_ack is provided
703 * get's only called for edge sense irqs
704 */
Thomas Gleixnere9502852011-02-06 18:23:36 +0000705 set_gpio_data(irq_to_gpio(d->irq), 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700706}
707
Thomas Gleixnere9502852011-02-06 18:23:36 +0000708static void bfin_gpio_mask_ack_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700709{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000710 unsigned int irq = d->irq;
Michael Hennerich8d022372008-11-18 17:48:22 +0800711 u32 gpionr = irq_to_gpio(irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700712
Thomas Gleixner1907d8b2011-03-24 17:21:01 +0100713 if (!irqd_is_level_type(d))
Bryan Wu1394f032007-05-06 14:50:22 -0700714 set_gpio_data(gpionr, 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700715
716 set_gpio_maska(gpionr, 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700717}
718
Thomas Gleixnere9502852011-02-06 18:23:36 +0000719static void bfin_gpio_mask_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700720{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000721 set_gpio_maska(irq_to_gpio(d->irq), 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700722}
723
Thomas Gleixnere9502852011-02-06 18:23:36 +0000724static void bfin_gpio_unmask_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700725{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000726 set_gpio_maska(irq_to_gpio(d->irq), 1);
Bryan Wu1394f032007-05-06 14:50:22 -0700727}
728
Thomas Gleixnere9502852011-02-06 18:23:36 +0000729static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700730{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000731 u32 gpionr = irq_to_gpio(d->irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700732
Michael Hennerich8d022372008-11-18 17:48:22 +0800733 if (__test_and_set_bit(gpionr, gpio_enabled))
Michael Hennerichaffee2b2008-04-24 08:10:10 +0800734 bfin_gpio_irq_prepare(gpionr);
Bryan Wu1394f032007-05-06 14:50:22 -0700735
Thomas Gleixnere9502852011-02-06 18:23:36 +0000736 bfin_gpio_unmask_irq(d);
Bryan Wu1394f032007-05-06 14:50:22 -0700737
Michael Hennerichaffee2b2008-04-24 08:10:10 +0800738 return 0;
Bryan Wu1394f032007-05-06 14:50:22 -0700739}
740
Thomas Gleixnere9502852011-02-06 18:23:36 +0000741static void bfin_gpio_irq_shutdown(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700742{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000743 u32 gpionr = irq_to_gpio(d->irq);
Graf Yang30af6d42008-11-18 17:48:21 +0800744
Thomas Gleixnere9502852011-02-06 18:23:36 +0000745 bfin_gpio_mask_irq(d);
Graf Yang30af6d42008-11-18 17:48:21 +0800746 __clear_bit(gpionr, gpio_enabled);
Graf Yang9570ff42009-01-07 23:14:38 +0800747 bfin_gpio_irq_free(gpionr);
Bryan Wu1394f032007-05-06 14:50:22 -0700748}
749
Thomas Gleixnere9502852011-02-06 18:23:36 +0000750static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
Bryan Wu1394f032007-05-06 14:50:22 -0700751{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000752 unsigned int irq = d->irq;
Graf Yang8eb3e3b2008-11-18 17:48:22 +0800753 int ret;
754 char buf[16];
Michael Hennerich8d022372008-11-18 17:48:22 +0800755 u32 gpionr = irq_to_gpio(irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700756
757 if (type == IRQ_TYPE_PROBE) {
758 /* only probe unenabled GPIO interrupt lines */
Mike Frysingerc3695342009-06-13 10:32:29 -0400759 if (test_bit(gpionr, gpio_enabled))
Bryan Wu1394f032007-05-06 14:50:22 -0700760 return 0;
761 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
762 }
763
764 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800765 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
Michael Hennerich8d022372008-11-18 17:48:22 +0800766
Graf Yang9570ff42009-01-07 23:14:38 +0800767 snprintf(buf, 16, "gpio-irq%d", irq);
768 ret = bfin_gpio_irq_request(gpionr, buf);
769 if (ret)
770 return ret;
771
Michael Hennerich8d022372008-11-18 17:48:22 +0800772 if (__test_and_set_bit(gpionr, gpio_enabled))
Michael Hennerichaffee2b2008-04-24 08:10:10 +0800773 bfin_gpio_irq_prepare(gpionr);
Bryan Wu1394f032007-05-06 14:50:22 -0700774
Bryan Wu1394f032007-05-06 14:50:22 -0700775 } else {
Michael Hennerich8d022372008-11-18 17:48:22 +0800776 __clear_bit(gpionr, gpio_enabled);
Bryan Wu1394f032007-05-06 14:50:22 -0700777 return 0;
778 }
779
Michael Hennerichf1bceb42008-02-02 16:17:52 +0800780 set_gpio_inen(gpionr, 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700781 set_gpio_dir(gpionr, 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700782
783 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
784 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
785 set_gpio_both(gpionr, 1);
786 else
787 set_gpio_both(gpionr, 0);
788
789 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
790 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
791 else
792 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
793
Michael Hennerichf1bceb42008-02-02 16:17:52 +0800794 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
795 set_gpio_edge(gpionr, 1);
796 set_gpio_inen(gpionr, 1);
Michael Hennerichf1bceb42008-02-02 16:17:52 +0800797 set_gpio_data(gpionr, 0);
798
799 } else {
800 set_gpio_edge(gpionr, 0);
Michael Hennerichf1bceb42008-02-02 16:17:52 +0800801 set_gpio_inen(gpionr, 1);
802 }
803
Bryan Wu1394f032007-05-06 14:50:22 -0700804 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
Thomas Gleixner28438442015-07-13 20:34:57 +0000805 bfin_set_irq_handler(d, handle_edge_irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700806 else
Thomas Gleixner28438442015-07-13 20:34:57 +0000807 bfin_set_irq_handler(d, handle_level_irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700808
809 return 0;
810}
811
Mike Frysingere2a80922011-04-15 12:51:33 -0400812static void bfin_demux_gpio_block(unsigned int irq)
813{
814 unsigned int gpio, mask;
815
816 gpio = irq_to_gpio(irq);
817 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
818
819 while (mask) {
820 if (mask & 1)
821 bfin_handle_irq(irq);
822 irq++;
823 mask >>= 1;
824 }
825}
826
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200827void bfin_demux_gpio_irq(struct irq_desc *desc)
Bryan Wu1394f032007-05-06 14:50:22 -0700828{
Thomas Gleixner2b5017692015-07-31 21:50:30 +0200829 unsigned int inta_irq = irq_desc_get_irq(desc);
Mike Frysingere2a80922011-04-15 12:51:33 -0400830 unsigned int irq;
Bryan Wu1394f032007-05-06 14:50:22 -0700831
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800832 switch (inta_irq) {
Mike Frysingere2a80922011-04-15 12:51:33 -0400833#if defined(BF537_FAMILY)
Mike Frysinger8c054102011-04-15 13:04:59 -0400834 case IRQ_PF_INTA_PG_INTA:
Mike Frysingere2a80922011-04-15 12:51:33 -0400835 bfin_demux_gpio_block(IRQ_PF0);
836 irq = IRQ_PG0;
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800837 break;
Mike Frysinger8c054102011-04-15 13:04:59 -0400838 case IRQ_PH_INTA_MAC_RX:
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800839 irq = IRQ_PH0;
840 break;
Mike Frysingere2a80922011-04-15 12:51:33 -0400841#elif defined(BF533_FAMILY)
842 case IRQ_PROG_INTA:
843 irq = IRQ_PF0;
844 break;
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400845#elif defined(BF538_FAMILY)
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800846 case IRQ_PORTF_INTA:
847 irq = IRQ_PF0;
848 break;
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800849#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800850 case IRQ_PORTF_INTA:
851 irq = IRQ_PF0;
852 break;
853 case IRQ_PORTG_INTA:
854 irq = IRQ_PG0;
855 break;
856 case IRQ_PORTH_INTA:
857 irq = IRQ_PH0;
858 break;
859#elif defined(CONFIG_BF561)
860 case IRQ_PROG0_INTA:
861 irq = IRQ_PF0;
862 break;
863 case IRQ_PROG1_INTA:
864 irq = IRQ_PF16;
865 break;
866 case IRQ_PROG2_INTA:
867 irq = IRQ_PF32;
868 break;
869#endif
870 default:
871 BUG();
872 return;
Bryan Wu1394f032007-05-06 14:50:22 -0700873 }
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800874
Mike Frysingere2a80922011-04-15 12:51:33 -0400875 bfin_demux_gpio_block(irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700876}
877
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800878#ifdef CONFIG_PM
Steven Miaod49cdf8402012-06-14 18:04:01 +0800879
Mike Frysingerdd8cb372011-04-15 03:19:22 -0400880static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800881{
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800882 return bfin_gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
883}
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800884
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800885#else
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800886
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800887# define bfin_gpio_set_wake NULL
888
Sonic Zhang86794b42012-12-14 11:19:24 +0800889#endif
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800890
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800891static struct irq_chip bfin_gpio_irqchip = {
892 .name = "GPIO",
893 .irq_ack = bfin_gpio_ack_irq,
894 .irq_mask = bfin_gpio_mask_irq,
895 .irq_mask_ack = bfin_gpio_mask_ack_irq,
896 .irq_unmask = bfin_gpio_unmask_irq,
897 .irq_disable = bfin_gpio_mask_irq,
898 .irq_enable = bfin_gpio_unmask_irq,
899 .irq_set_type = bfin_gpio_irq_type,
900 .irq_startup = bfin_gpio_irq_startup,
901 .irq_shutdown = bfin_gpio_irq_shutdown,
902 .irq_set_wake = bfin_gpio_set_wake,
903};
Steven Miaod49cdf8402012-06-14 18:04:01 +0800904
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800905#endif
Steven Miaod49cdf8402012-06-14 18:04:01 +0800906
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800907#ifdef CONFIG_PM
Steven Miaod49cdf8402012-06-14 18:04:01 +0800908
Sonic Zhang11b27cb2012-06-28 19:16:48 +0800909#ifdef SEC_GCTL
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800910static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
911
Steven Miaod49cdf8402012-06-14 18:04:01 +0800912static int sec_suspend(void)
913{
914 u32 bank;
915
916 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
Sonic Zhang86794b42012-12-14 11:19:24 +0800917 save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0));
Steven Miaod49cdf8402012-06-14 18:04:01 +0800918 return 0;
919}
920
921static void sec_resume(void)
922{
923 u32 bank;
924
925 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
926 udelay(100);
927 bfin_write_SEC_GCTL(SEC_GCTL_EN);
928 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
929
930 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
Sonic Zhang86794b42012-12-14 11:19:24 +0800931 bfin_write_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
Steven Miaod49cdf8402012-06-14 18:04:01 +0800932}
933
934static struct syscore_ops sec_pm_syscore_ops = {
935 .suspend = sec_suspend,
936 .resume = sec_resume,
937};
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800938#endif
939
Steven Miao4f6b6002012-05-16 17:56:51 +0800940#endif
Michael Hennerich8d022372008-11-18 17:48:22 +0800941
Paul Gortmaker13dff622013-06-18 16:56:21 -0400942void init_exception_vectors(void)
Bernd Schmidt8be80ed2007-07-25 14:44:49 +0800943{
Mike Frysingerf0b5d122007-08-05 17:03:59 +0800944 /* cannot program in software:
945 * evt0 - emulation (jtag)
946 * evt1 - reset
947 */
948 bfin_write_EVT2(evt_nmi);
Bernd Schmidt8be80ed2007-07-25 14:44:49 +0800949 bfin_write_EVT3(trap);
950 bfin_write_EVT5(evt_ivhw);
951 bfin_write_EVT6(evt_timer);
952 bfin_write_EVT7(evt_evt7);
953 bfin_write_EVT8(evt_evt8);
954 bfin_write_EVT9(evt_evt9);
955 bfin_write_EVT10(evt_evt10);
956 bfin_write_EVT11(evt_evt11);
957 bfin_write_EVT12(evt_evt12);
958 bfin_write_EVT13(evt_evt13);
Philippe Gerum9703a732009-06-22 18:23:48 +0200959 bfin_write_EVT14(evt_evt14);
Bernd Schmidt8be80ed2007-07-25 14:44:49 +0800960 bfin_write_EVT15(evt_system_call);
961 CSYNC();
962}
963
Sonic Zhang11b27cb2012-06-28 19:16:48 +0800964#ifndef SEC_GCTL
Bryan Wu1394f032007-05-06 14:50:22 -0700965/*
966 * This function should be called during kernel startup to initialize
967 * the BFin IRQ handling routines.
968 */
Michael Hennerich8d022372008-11-18 17:48:22 +0800969
Bryan Wu1394f032007-05-06 14:50:22 -0700970int __init init_arch_irq(void)
971{
972 int irq;
973 unsigned long ilat = 0;
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400974
Bryan Wu1394f032007-05-06 14:50:22 -0700975 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400976#ifdef SIC_IMASK0
Roy Huang24a07a12007-07-12 22:41:45 +0800977 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
978 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400979# ifdef SIC_IMASK2
Michael Hennerich59003142007-10-21 16:54:27 +0800980 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
Mike Frysingera055b2b2007-11-15 21:12:32 +0800981# endif
Steven Miao4f6b6002012-05-16 17:56:51 +0800982# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
Graf Yang6b3087c2009-01-07 23:14:39 +0800983 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
984 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
985# endif
Roy Huang24a07a12007-07-12 22:41:45 +0800986#else
Bryan Wu1394f032007-05-06 14:50:22 -0700987 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
Roy Huang24a07a12007-07-12 22:41:45 +0800988#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700989
990 local_irq_disable();
991
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800992 for (irq = 0; irq <= SYS_IRQS; irq++) {
Bryan Wu1394f032007-05-06 14:50:22 -0700993 if (irq <= IRQ_CORETMR)
Thomas Gleixner43f2f112011-03-24 17:22:30 +0100994 irq_set_chip(irq, &bfin_core_irqchip);
Bryan Wu1394f032007-05-06 14:50:22 -0700995 else
Thomas Gleixner43f2f112011-03-24 17:22:30 +0100996 irq_set_chip(irq, &bfin_internal_irqchip);
Bryan Wu1394f032007-05-06 14:50:22 -0700997
Michael Hennerich464abc52008-02-25 13:50:20 +0800998 switch (irq) {
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800999#if !BFIN_GPIO_PINT
1000#if defined(BF537_FAMILY)
Mike Frysinger01f8e342011-06-26 13:56:23 -04001001 case IRQ_PH_INTA_MAC_RX:
1002 case IRQ_PF_INTA_PG_INTA:
1003#elif defined(BF533_FAMILY)
1004 case IRQ_PROG_INTA:
Bryan Wu2f6f4bc2008-11-18 17:48:21 +08001005#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
Michael Hennerich464abc52008-02-25 13:50:20 +08001006 case IRQ_PORTF_INTA:
1007 case IRQ_PORTG_INTA:
1008 case IRQ_PORTH_INTA:
Michael Hennerich2c4f8292008-02-09 04:11:14 +08001009#elif defined(CONFIG_BF561)
Michael Hennerich464abc52008-02-25 13:50:20 +08001010 case IRQ_PROG0_INTA:
1011 case IRQ_PROG1_INTA:
1012 case IRQ_PROG2_INTA:
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -04001013#elif defined(BF538_FAMILY)
Michael Hennerichdc26aec2008-11-18 17:48:22 +08001014 case IRQ_PORTF_INTA:
Michael Hennerich59003142007-10-21 16:54:27 +08001015#endif
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001016 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
Michael Hennerich464abc52008-02-25 13:50:20 +08001017 break;
Sonic Zhang54e4ff42013-05-30 18:37:28 +08001018#endif
Michael Hennerichaec59c92010-02-19 15:09:10 +00001019#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1020 case IRQ_MAC_ERROR:
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001021 irq_set_chained_handler(irq,
1022 bfin_demux_mac_status_irq);
Michael Hennerichaec59c92010-02-19 15:09:10 +00001023 break;
1024#endif
Steven Miao4f6b6002012-05-16 17:56:51 +08001025#if defined(CONFIG_SMP) || defined(CONFIG_ICC)
Graf Yang6b3087c2009-01-07 23:14:39 +08001026 case IRQ_SUPPLE_0:
1027 case IRQ_SUPPLE_1:
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001028 irq_set_handler(irq, handle_percpu_irq);
Graf Yang6b3087c2009-01-07 23:14:39 +08001029 break;
1030#endif
Graf Yang179413142009-08-18 04:29:33 +00001031
Yi Licb191712009-12-30 07:12:50 +00001032#ifdef CONFIG_TICKSOURCE_CORETMR
1033 case IRQ_CORETMR:
1034# ifdef CONFIG_SMP
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001035 irq_set_handler(irq, handle_percpu_irq);
Yi Licb191712009-12-30 07:12:50 +00001036# else
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001037 irq_set_handler(irq, handle_simple_irq);
Yi Licb191712009-12-30 07:12:50 +00001038# endif
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -04001039 break;
Yi Licb191712009-12-30 07:12:50 +00001040#endif
1041
1042#ifdef CONFIG_TICKSOURCE_GPTMR0
Philippe Geruma40494a2009-06-16 05:25:42 +02001043 case IRQ_TIMER0:
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001044 irq_set_handler(irq, handle_simple_irq);
Michael Hennerich464abc52008-02-25 13:50:20 +08001045 break;
Graf Yang179413142009-08-18 04:29:33 +00001046#endif
Yi Licb191712009-12-30 07:12:50 +00001047
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -04001048 default:
Yi Licb191712009-12-30 07:12:50 +00001049#ifdef CONFIG_IPIPE
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001050 irq_set_handler(irq, handle_level_irq);
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -04001051#else
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001052 irq_set_handler(irq, handle_simple_irq);
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -04001053#endif
Philippe Geruma40494a2009-06-16 05:25:42 +02001054 break;
Bryan Wu1394f032007-05-06 14:50:22 -07001055 }
Bryan Wu1394f032007-05-06 14:50:22 -07001056 }
Michael Hennerich464abc52008-02-25 13:50:20 +08001057
Mike Frysingerf58c3272011-04-15 03:08:20 -04001058 init_mach_irq();
Bryan Wu1394f032007-05-06 14:50:22 -07001059
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001060#if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
Michael Hennerichaec59c92010-02-19 15:09:10 +00001061 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001062 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
Michael Hennerichaec59c92010-02-19 15:09:10 +00001063 handle_level_irq);
1064#endif
Michael Hennerich464abc52008-02-25 13:50:20 +08001065 /* if configured as edge, then will be changed to do_edge_IRQ */
Sonic Zhang54e4ff42013-05-30 18:37:28 +08001066#ifdef CONFIG_GPIO_ADI
Michael Hennerichaec59c92010-02-19 15:09:10 +00001067 for (irq = GPIO_IRQ_BASE;
1068 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001069 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
Michael Hennerich464abc52008-02-25 13:50:20 +08001070 handle_level_irq);
Sonic Zhang54e4ff42013-05-30 18:37:28 +08001071#endif
Bryan Wu1394f032007-05-06 14:50:22 -07001072 bfin_write_IMASK(0);
1073 CSYNC();
1074 ilat = bfin_read_ILAT();
1075 CSYNC();
1076 bfin_write_ILAT(ilat);
1077 CSYNC();
1078
Michael Hennerich34e0fc82007-07-12 16:17:18 +08001079 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
Mike Frysinger40059782008-11-18 17:48:22 +08001080 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
Bryan Wu1394f032007-05-06 14:50:22 -07001081 * local_irq_enable()
1082 */
1083 program_IAR();
1084 /* Therefore it's better to setup IARs before interrupts enabled */
1085 search_IAR();
1086
1087 /* Enable interrupts IVG7-15 */
Mike Frysinger40059782008-11-18 17:48:22 +08001088 bfin_irq_flags |= IMASK_IVG15 |
Steven Miao4f6b6002012-05-16 17:56:51 +08001089 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1090 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1091
Bryan Wu1394f032007-05-06 14:50:22 -07001092
Michael Hennerich349ebbc2009-04-15 08:48:08 +00001093 /* This implicitly covers ANOMALY_05000171
1094 * Boot-ROM code modifies SICA_IWRx wakeup registers
1095 */
Mike Frysingerbe1d8542009-02-04 16:49:45 +08001096#ifdef SIC_IWR0
Michael Hennerich56f5f592008-08-06 17:55:32 +08001097 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
Mike Frysingerbe1d8542009-02-04 16:49:45 +08001098# ifdef SIC_IWR1
Bryan Wu2f6f4bc2008-11-18 17:48:21 +08001099 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
Michael Hennerich55546ac2008-08-13 17:41:13 +08001100 * will screw up the bootrom as it relies on MDMA0/1 waking it
1101 * up from IDLE instructions. See this report for more info:
1102 * http://blackfin.uclinux.org/gf/tracker/4323
1103 */
Mike Frysingerb7e11292008-11-18 17:48:22 +08001104 if (ANOMALY_05000435)
1105 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1106 else
1107 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
Mike Frysingerbe1d8542009-02-04 16:49:45 +08001108# endif
1109# ifdef SIC_IWR2
Michael Hennerich56f5f592008-08-06 17:55:32 +08001110 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
Michael Hennerichfe9ec9b2008-02-25 12:04:57 +08001111# endif
1112#else
Michael Hennerich56f5f592008-08-06 17:55:32 +08001113 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
Michael Hennerichfe9ec9b2008-02-25 12:04:57 +08001114#endif
Bryan Wu1394f032007-05-06 14:50:22 -07001115 return 0;
1116}
1117
1118#ifdef CONFIG_DO_IRQ_L1
Mike Frysingera055b2b2007-11-15 21:12:32 +08001119__attribute__((l1_text))
Bryan Wu1394f032007-05-06 14:50:22 -07001120#endif
Mike Frysinger6b108042011-03-30 01:35:41 -04001121static int vec_to_irq(int vec)
1122{
1123 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1124 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1125 unsigned long sic_status[3];
Mike Frysinger6b108042011-03-30 01:35:41 -04001126 if (likely(vec == EVT_IVTMR_P))
1127 return IRQ_CORETMR;
Mike Frysinger6b108042011-03-30 01:35:41 -04001128#ifdef SIC_ISR
1129 sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1130#else
1131 if (smp_processor_id()) {
1132# ifdef SICB_ISR0
1133 /* This will be optimized out in UP mode. */
1134 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1135 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1136# endif
1137 } else {
1138 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1139 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1140 }
1141#endif
1142#ifdef SIC_ISR2
1143 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1144#endif
1145
1146 for (;; ivg++) {
1147 if (ivg >= ivg_stop)
1148 return -1;
1149#ifdef SIC_ISR
1150 if (sic_status[0] & ivg->isrflag)
1151#else
1152 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1153#endif
1154 return ivg->irqno;
1155 }
1156}
1157
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001158#else /* SEC_GCTL */
1159
1160/*
1161 * This function should be called during kernel startup to initialize
1162 * the BFin IRQ handling routines.
1163 */
1164
1165int __init init_arch_irq(void)
1166{
1167 int irq;
1168 unsigned long ilat = 0;
1169
1170 bfin_write_SEC_GCTL(SEC_GCTL_RESET);
1171
1172 local_irq_disable();
1173
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001174 for (irq = 0; irq <= SYS_IRQS; irq++) {
1175 if (irq <= IRQ_CORETMR) {
Sonic Zhang86794b42012-12-14 11:19:24 +08001176 irq_set_chip_and_handler(irq, &bfin_core_irqchip,
1177 handle_simple_irq);
1178#if defined(CONFIG_TICKSOURCE_CORETMR) && defined(CONFIG_SMP)
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001179 if (irq == IRQ_CORETMR)
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001180 irq_set_handler(irq, handle_percpu_irq);
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001181#endif
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001182 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001183 irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
Sonic Zhang86794b42012-12-14 11:19:24 +08001184 handle_percpu_irq);
1185 } else {
1186 irq_set_chip(irq, &bfin_sec_irqchip);
Sonic Zhang1b601232013-12-04 15:27:47 +08001187 irq_set_handler(irq, handle_fasteoi_irq);
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001188 __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
1189 }
1190 }
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001191
1192 bfin_write_IMASK(0);
1193 CSYNC();
1194 ilat = bfin_read_ILAT();
1195 CSYNC();
1196 bfin_write_ILAT(ilat);
1197 CSYNC();
1198
1199 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1200
Sonic Zhange0a59312012-06-29 18:19:29 +08001201 bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
1202
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001203 /* Enable interrupts IVG7-15 */
1204 bfin_irq_flags |= IMASK_IVG15 |
1205 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1206 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1207
1208
1209 bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
Sonic Zhang86794b42012-12-14 11:19:24 +08001210 bfin_sec_enable_sci(BFIN_SYSIRQ(IRQ_WATCH0));
1211 bfin_sec_enable_ssi(BFIN_SYSIRQ(IRQ_WATCH0));
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001212 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1213 udelay(100);
1214 bfin_write_SEC_GCTL(SEC_GCTL_EN);
1215 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1216 bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1217
1218 init_software_driven_irq();
Steven Miao36c47232012-12-21 14:34:16 +08001219
1220#ifdef CONFIG_PM
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001221 register_syscore_ops(&sec_pm_syscore_ops);
Steven Miao36c47232012-12-21 14:34:16 +08001222#endif
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001223
Sonic Zhang1b601232013-12-04 15:27:47 +08001224 bfin_fault_irq.handler = bfin_fault_routine;
1225#ifdef CONFIG_L1_PARITY_CHECK
1226 setup_irq(IRQ_C0_NMI_L1_PARITY_ERR, &bfin_fault_irq);
1227#endif
1228 setup_irq(IRQ_C0_DBL_FAULT, &bfin_fault_irq);
1229 setup_irq(IRQ_SEC_ERR, &bfin_fault_irq);
1230
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001231 return 0;
1232}
1233
1234#ifdef CONFIG_DO_IRQ_L1
1235__attribute__((l1_text))
1236#endif
1237static int vec_to_irq(int vec)
1238{
1239 if (likely(vec == EVT_IVTMR_P))
1240 return IRQ_CORETMR;
1241
1242 return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
1243}
1244#endif /* SEC_GCTL */
1245
Mike Frysinger6b108042011-03-30 01:35:41 -04001246#ifdef CONFIG_DO_IRQ_L1
1247__attribute__((l1_text))
1248#endif
Bryan Wu1394f032007-05-06 14:50:22 -07001249void do_irq(int vec, struct pt_regs *fp)
1250{
Mike Frysinger6b108042011-03-30 01:35:41 -04001251 int irq = vec_to_irq(vec);
1252 if (irq == -1)
1253 return;
1254 asm_do_IRQ(irq, fp);
Bryan Wu1394f032007-05-06 14:50:22 -07001255}
Yi Li6a01f232009-01-07 23:14:39 +08001256
1257#ifdef CONFIG_IPIPE
1258
1259int __ipipe_get_irq_priority(unsigned irq)
1260{
1261 int ient, prio;
1262
1263 if (irq <= IRQ_CORETMR)
1264 return irq;
1265
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001266#ifdef SEC_GCTL
1267 if (irq >= BFIN_IRQ(0))
1268 return IVG11;
1269#else
Yi Li6a01f232009-01-07 23:14:39 +08001270 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1271 struct ivgx *ivg = ivg_table + ient;
1272 if (ivg->irqno == irq) {
1273 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1274 if (ivg7_13[prio].ifirst <= ivg &&
1275 ivg7_13[prio].istop > ivg)
1276 return IVG7 + prio;
1277 }
1278 }
1279 }
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001280#endif
Yi Li6a01f232009-01-07 23:14:39 +08001281
1282 return IVG15;
1283}
1284
Yi Li6a01f232009-01-07 23:14:39 +08001285/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1286#ifdef CONFIG_DO_IRQ_L1
1287__attribute__((l1_text))
1288#endif
1289asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1290{
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001291 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
Philippe Geruma40494a2009-06-16 05:25:42 +02001292 struct ipipe_domain *this_domain = __ipipe_current_domain;
Philippe Gerum5b5da4c2011-03-17 02:12:48 -04001293 int irq, s = 0;
Yi Li6a01f232009-01-07 23:14:39 +08001294
Mike Frysinger6b108042011-03-30 01:35:41 -04001295 irq = vec_to_irq(vec);
1296 if (irq == -1)
1297 return 0;
Yi Li6a01f232009-01-07 23:14:39 +08001298
1299 if (irq == IRQ_SYSTMR) {
Philippe Geruma40494a2009-06-16 05:25:42 +02001300#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
Yi Li6a01f232009-01-07 23:14:39 +08001301 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001302#endif
Yi Li6a01f232009-01-07 23:14:39 +08001303 /* This is basically what we need from the register frame. */
Christoph Lameter7e788ab2014-08-17 12:30:52 -05001304 __this_cpu_write(__ipipe_tick_regs.ipend, regs->ipend);
1305 __this_cpu_write(__ipipe_tick_regs.pc, regs->pc);
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001306 if (this_domain != ipipe_root_domain)
Christoph Lameter7e788ab2014-08-17 12:30:52 -05001307 __this_cpu_and(__ipipe_tick_regs.ipend, ~0x10);
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001308 else
Christoph Lameter7e788ab2014-08-17 12:30:52 -05001309 __this_cpu_or(__ipipe_tick_regs.ipend, 0x10);
Yi Li6a01f232009-01-07 23:14:39 +08001310 }
1311
Philippe Gerum5b5da4c2011-03-17 02:12:48 -04001312 /*
1313 * We don't want Linux interrupt handlers to run at the
1314 * current core priority level (i.e. < EVT15), since this
1315 * might delay other interrupts handled by a high priority
1316 * domain. Here is what we do instead:
1317 *
1318 * - we raise the SYNCDEFER bit to prevent
1319 * __ipipe_handle_irq() to sync the pipeline for the root
1320 * stage for the incoming interrupt. Upon return, that IRQ is
1321 * pending in the interrupt log.
1322 *
1323 * - we raise the TIF_IRQ_SYNC bit for the current thread, so
1324 * that _schedule_and_signal_from_int will eventually sync the
1325 * pipeline from EVT15.
1326 */
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001327 if (this_domain == ipipe_root_domain) {
1328 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1329 barrier();
1330 }
Yi Li6a01f232009-01-07 23:14:39 +08001331
1332 ipipe_trace_irq_entry(irq);
1333 __ipipe_handle_irq(irq, regs);
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001334 ipipe_trace_irq_exit(irq);
Yi Li6a01f232009-01-07 23:14:39 +08001335
Philippe Gerum5b5da4c2011-03-17 02:12:48 -04001336 if (user_mode(regs) &&
1337 !ipipe_test_foreign_stack() &&
1338 (current->ipipe_flags & PF_EVTRET) != 0) {
1339 /*
1340 * Testing for user_regs() does NOT fully eliminate
1341 * foreign stack contexts, because of the forged
1342 * interrupt returns we do through
1343 * __ipipe_call_irqtail. In that case, we might have
1344 * preempted a foreign stack context in a high
1345 * priority domain, with a single interrupt level now
1346 * pending after the irqtail unwinding is done. In
1347 * which case user_mode() is now true, and the event
1348 * gets dispatched spuriously.
1349 */
1350 current->ipipe_flags &= ~PF_EVTRET;
1351 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
1352 }
1353
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001354 if (this_domain == ipipe_root_domain) {
1355 set_thread_flag(TIF_IRQ_SYNC);
1356 if (!s) {
1357 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1358 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1359 }
1360 }
Yi Li6a01f232009-01-07 23:14:39 +08001361
Graf Yang1fa9be72009-05-15 11:01:59 +00001362 return 0;
Yi Li6a01f232009-01-07 23:14:39 +08001363}
1364
1365#endif /* CONFIG_IPIPE */