Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008-2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Zou Nan hai <nanhai.zou@intel.com> |
| 26 | * Xiang Hai hao<haihao.xiang@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include "drmP.h" |
| 31 | #include "drm.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 32 | #include "i915_drv.h" |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 33 | #include "i915_drm.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 34 | #include "i915_trace.h" |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 35 | #include "intel_drv.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 36 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 37 | /* |
| 38 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
| 39 | * over cache flushing. |
| 40 | */ |
| 41 | struct pipe_control { |
| 42 | struct drm_i915_gem_object *obj; |
| 43 | volatile u32 *cpu_page; |
| 44 | u32 gtt_offset; |
| 45 | }; |
| 46 | |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 47 | static inline int ring_space(struct intel_ring_buffer *ring) |
| 48 | { |
| 49 | int space = (ring->head & HEAD_ADDR) - (ring->tail + 8); |
| 50 | if (space < 0) |
| 51 | space += ring->size; |
| 52 | return space; |
| 53 | } |
| 54 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 55 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 56 | render_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 57 | u32 invalidate_domains, |
| 58 | u32 flush_domains) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 59 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 60 | struct drm_device *dev = ring->dev; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 61 | u32 cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 62 | int ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 63 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 64 | /* |
| 65 | * read/write caches: |
| 66 | * |
| 67 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 68 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 69 | * also flushed at 2d versus 3d pipeline switches. |
| 70 | * |
| 71 | * read-only caches: |
| 72 | * |
| 73 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 74 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 75 | * |
| 76 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 77 | * |
| 78 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 79 | * invalidated when MI_EXE_FLUSH is set. |
| 80 | * |
| 81 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 82 | * invalidated with every MI_FLUSH. |
| 83 | * |
| 84 | * TLBs: |
| 85 | * |
| 86 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 87 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 88 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 89 | * are flushed at any MI_FLUSH. |
| 90 | */ |
| 91 | |
| 92 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
| 93 | if ((invalidate_domains|flush_domains) & |
| 94 | I915_GEM_DOMAIN_RENDER) |
| 95 | cmd &= ~MI_NO_WRITE_FLUSH; |
| 96 | if (INTEL_INFO(dev)->gen < 4) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 97 | /* |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 98 | * On the 965, the sampler cache always gets flushed |
| 99 | * and this bit is reserved. |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 100 | */ |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 101 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 102 | cmd |= MI_READ_FLUSH; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 103 | } |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 104 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 105 | cmd |= MI_EXE_FLUSH; |
| 106 | |
| 107 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
| 108 | (IS_G4X(dev) || IS_GEN5(dev))) |
| 109 | cmd |= MI_INVALIDATE_ISP; |
| 110 | |
| 111 | ret = intel_ring_begin(ring, 2); |
| 112 | if (ret) |
| 113 | return ret; |
| 114 | |
| 115 | intel_ring_emit(ring, cmd); |
| 116 | intel_ring_emit(ring, MI_NOOP); |
| 117 | intel_ring_advance(ring); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 118 | |
| 119 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 120 | } |
| 121 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 122 | /** |
| 123 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
| 124 | * implementing two workarounds on gen6. From section 1.4.7.1 |
| 125 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: |
| 126 | * |
| 127 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those |
| 128 | * produced by non-pipelined state commands), software needs to first |
| 129 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
| 130 | * 0. |
| 131 | * |
| 132 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable |
| 133 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. |
| 134 | * |
| 135 | * And the workaround for these two requires this workaround first: |
| 136 | * |
| 137 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
| 138 | * BEFORE the pipe-control with a post-sync op and no write-cache |
| 139 | * flushes. |
| 140 | * |
| 141 | * And this last workaround is tricky because of the requirements on |
| 142 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM |
| 143 | * volume 2 part 1: |
| 144 | * |
| 145 | * "1 of the following must also be set: |
| 146 | * - Render Target Cache Flush Enable ([12] of DW1) |
| 147 | * - Depth Cache Flush Enable ([0] of DW1) |
| 148 | * - Stall at Pixel Scoreboard ([1] of DW1) |
| 149 | * - Depth Stall ([13] of DW1) |
| 150 | * - Post-Sync Operation ([13] of DW1) |
| 151 | * - Notify Enable ([8] of DW1)" |
| 152 | * |
| 153 | * The cache flushes require the workaround flush that triggered this |
| 154 | * one, so we can't use it. Depth stall would trigger the same. |
| 155 | * Post-sync nonzero is what triggered this second workaround, so we |
| 156 | * can't use that one either. Notify enable is IRQs, which aren't |
| 157 | * really our business. That leaves only stall at scoreboard. |
| 158 | */ |
| 159 | static int |
| 160 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) |
| 161 | { |
| 162 | struct pipe_control *pc = ring->private; |
| 163 | u32 scratch_addr = pc->gtt_offset + 128; |
| 164 | int ret; |
| 165 | |
| 166 | |
| 167 | ret = intel_ring_begin(ring, 6); |
| 168 | if (ret) |
| 169 | return ret; |
| 170 | |
| 171 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 172 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 173 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 174 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 175 | intel_ring_emit(ring, 0); /* low dword */ |
| 176 | intel_ring_emit(ring, 0); /* high dword */ |
| 177 | intel_ring_emit(ring, MI_NOOP); |
| 178 | intel_ring_advance(ring); |
| 179 | |
| 180 | ret = intel_ring_begin(ring, 6); |
| 181 | if (ret) |
| 182 | return ret; |
| 183 | |
| 184 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 185 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); |
| 186 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 187 | intel_ring_emit(ring, 0); |
| 188 | intel_ring_emit(ring, 0); |
| 189 | intel_ring_emit(ring, MI_NOOP); |
| 190 | intel_ring_advance(ring); |
| 191 | |
| 192 | return 0; |
| 193 | } |
| 194 | |
| 195 | static int |
| 196 | gen6_render_ring_flush(struct intel_ring_buffer *ring, |
| 197 | u32 invalidate_domains, u32 flush_domains) |
| 198 | { |
| 199 | u32 flags = 0; |
| 200 | struct pipe_control *pc = ring->private; |
| 201 | u32 scratch_addr = pc->gtt_offset + 128; |
| 202 | int ret; |
| 203 | |
| 204 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
| 205 | intel_emit_post_sync_nonzero_flush(ring); |
| 206 | |
| 207 | /* Just flush everything. Experiments have shown that reducing the |
| 208 | * number of bits based on the write domains has little performance |
| 209 | * impact. |
| 210 | */ |
| 211 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 212 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 213 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 214 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 215 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 216 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 217 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 218 | |
| 219 | ret = intel_ring_begin(ring, 6); |
| 220 | if (ret) |
| 221 | return ret; |
| 222 | |
| 223 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 224 | intel_ring_emit(ring, flags); |
| 225 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
| 226 | intel_ring_emit(ring, 0); /* lower dword */ |
| 227 | intel_ring_emit(ring, 0); /* uppwer dword */ |
| 228 | intel_ring_emit(ring, MI_NOOP); |
| 229 | intel_ring_advance(ring); |
| 230 | |
| 231 | return 0; |
| 232 | } |
| 233 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 234 | static void ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 235 | u32 value) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 236 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 237 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 238 | I915_WRITE_TAIL(ring, value); |
Xiang, Haihao | d46eefa | 2010-09-16 10:43:12 +0800 | [diff] [blame] | 239 | } |
| 240 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 241 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 242 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 243 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 244 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? |
Daniel Vetter | 3d281d8 | 2010-09-24 21:14:22 +0200 | [diff] [blame] | 245 | RING_ACTHD(ring->mmio_base) : ACTHD; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 246 | |
| 247 | return I915_READ(acthd_reg); |
| 248 | } |
| 249 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 250 | static int init_ring_common(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 251 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 252 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 253 | struct drm_i915_gem_object *obj = ring->obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 254 | u32 head; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 255 | |
| 256 | /* Stop the ring if it's running. */ |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 257 | I915_WRITE_CTL(ring, 0); |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 258 | I915_WRITE_HEAD(ring, 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 259 | ring->write_tail(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 260 | |
| 261 | /* Initialize the ring. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 262 | I915_WRITE_START(ring, obj->gtt_offset); |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 263 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 264 | |
| 265 | /* G45 ring initialization fails to reset head to zero */ |
| 266 | if (head != 0) { |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 267 | DRM_DEBUG_KMS("%s head not reset to zero " |
| 268 | "ctl %08x head %08x tail %08x start %08x\n", |
| 269 | ring->name, |
| 270 | I915_READ_CTL(ring), |
| 271 | I915_READ_HEAD(ring), |
| 272 | I915_READ_TAIL(ring), |
| 273 | I915_READ_START(ring)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 274 | |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 275 | I915_WRITE_HEAD(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 276 | |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 277 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
| 278 | DRM_ERROR("failed to set %s head to zero " |
| 279 | "ctl %08x head %08x tail %08x start %08x\n", |
| 280 | ring->name, |
| 281 | I915_READ_CTL(ring), |
| 282 | I915_READ_HEAD(ring), |
| 283 | I915_READ_TAIL(ring), |
| 284 | I915_READ_START(ring)); |
| 285 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 286 | } |
| 287 | |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 288 | I915_WRITE_CTL(ring, |
Chris Wilson | ae69b42 | 2010-11-07 11:45:52 +0000 | [diff] [blame] | 289 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
Chris Wilson | 6aa5606 | 2010-10-29 21:44:37 +0100 | [diff] [blame] | 290 | | RING_REPORT_64K | RING_VALID); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 291 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 292 | /* If the head is still not zero, the ring is dead */ |
Chris Wilson | 176f28e | 2010-10-28 11:18:07 +0100 | [diff] [blame] | 293 | if ((I915_READ_CTL(ring) & RING_VALID) == 0 || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 294 | I915_READ_START(ring) != obj->gtt_offset || |
Chris Wilson | 176f28e | 2010-10-28 11:18:07 +0100 | [diff] [blame] | 295 | (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) { |
Chris Wilson | e74cfed | 2010-11-09 10:16:56 +0000 | [diff] [blame] | 296 | DRM_ERROR("%s initialization failed " |
| 297 | "ctl %08x head %08x tail %08x start %08x\n", |
| 298 | ring->name, |
| 299 | I915_READ_CTL(ring), |
| 300 | I915_READ_HEAD(ring), |
| 301 | I915_READ_TAIL(ring), |
| 302 | I915_READ_START(ring)); |
| 303 | return -EIO; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 304 | } |
| 305 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 306 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
| 307 | i915_kernel_lost_context(ring->dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 308 | else { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 309 | ring->head = I915_READ_HEAD(ring); |
Daniel Vetter | 870e86d | 2010-08-02 16:29:44 +0200 | [diff] [blame] | 310 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 311 | ring->space = ring_space(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 312 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 313 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 314 | return 0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 315 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 316 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 317 | static int |
| 318 | init_pipe_control(struct intel_ring_buffer *ring) |
| 319 | { |
| 320 | struct pipe_control *pc; |
| 321 | struct drm_i915_gem_object *obj; |
| 322 | int ret; |
| 323 | |
| 324 | if (ring->private) |
| 325 | return 0; |
| 326 | |
| 327 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); |
| 328 | if (!pc) |
| 329 | return -ENOMEM; |
| 330 | |
| 331 | obj = i915_gem_alloc_object(ring->dev, 4096); |
| 332 | if (obj == NULL) { |
| 333 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 334 | ret = -ENOMEM; |
| 335 | goto err; |
| 336 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 337 | |
| 338 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 339 | |
| 340 | ret = i915_gem_object_pin(obj, 4096, true); |
| 341 | if (ret) |
| 342 | goto err_unref; |
| 343 | |
| 344 | pc->gtt_offset = obj->gtt_offset; |
| 345 | pc->cpu_page = kmap(obj->pages[0]); |
| 346 | if (pc->cpu_page == NULL) |
| 347 | goto err_unpin; |
| 348 | |
| 349 | pc->obj = obj; |
| 350 | ring->private = pc; |
| 351 | return 0; |
| 352 | |
| 353 | err_unpin: |
| 354 | i915_gem_object_unpin(obj); |
| 355 | err_unref: |
| 356 | drm_gem_object_unreference(&obj->base); |
| 357 | err: |
| 358 | kfree(pc); |
| 359 | return ret; |
| 360 | } |
| 361 | |
| 362 | static void |
| 363 | cleanup_pipe_control(struct intel_ring_buffer *ring) |
| 364 | { |
| 365 | struct pipe_control *pc = ring->private; |
| 366 | struct drm_i915_gem_object *obj; |
| 367 | |
| 368 | if (!ring->private) |
| 369 | return; |
| 370 | |
| 371 | obj = pc->obj; |
| 372 | kunmap(obj->pages[0]); |
| 373 | i915_gem_object_unpin(obj); |
| 374 | drm_gem_object_unreference(&obj->base); |
| 375 | |
| 376 | kfree(pc); |
| 377 | ring->private = NULL; |
| 378 | } |
| 379 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 380 | static int init_render_ring(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 381 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 382 | struct drm_device *dev = ring->dev; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 383 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 384 | int ret = init_ring_common(ring); |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 385 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 386 | if (INTEL_INFO(dev)->gen > 3) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 387 | int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 388 | I915_WRITE(MI_MODE, mode); |
Jesse Barnes | b095cd0 | 2011-08-12 15:28:32 -0700 | [diff] [blame] | 389 | if (IS_GEN7(dev)) |
| 390 | I915_WRITE(GFX_MODE_GEN7, |
| 391 | GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | |
| 392 | GFX_MODE_ENABLE(GFX_REPLAY_MODE)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 393 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 394 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 395 | if (INTEL_INFO(dev)->gen >= 5) { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 396 | ret = init_pipe_control(ring); |
| 397 | if (ret) |
| 398 | return ret; |
| 399 | } |
| 400 | |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 401 | if (INTEL_INFO(dev)->gen >= 6) { |
| 402 | I915_WRITE(INSTPM, |
| 403 | INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING); |
| 404 | } |
| 405 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 406 | return ret; |
| 407 | } |
| 408 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 409 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
| 410 | { |
| 411 | if (!ring->private) |
| 412 | return; |
| 413 | |
| 414 | cleanup_pipe_control(ring); |
| 415 | } |
| 416 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 417 | static void |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 418 | update_mboxes(struct intel_ring_buffer *ring, |
| 419 | u32 seqno, |
| 420 | u32 mmio_offset) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 421 | { |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 422 | intel_ring_emit(ring, MI_SEMAPHORE_MBOX | |
| 423 | MI_SEMAPHORE_GLOBAL_GTT | |
| 424 | MI_SEMAPHORE_REGISTER | |
| 425 | MI_SEMAPHORE_UPDATE); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 426 | intel_ring_emit(ring, seqno); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 427 | intel_ring_emit(ring, mmio_offset); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 428 | } |
| 429 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 430 | /** |
| 431 | * gen6_add_request - Update the semaphore mailbox registers |
| 432 | * |
| 433 | * @ring - ring that is adding a request |
| 434 | * @seqno - return seqno stuck into the ring |
| 435 | * |
| 436 | * Update the mailbox registers in the *other* rings with the current seqno. |
| 437 | * This acts like a signal in the canonical semaphore. |
| 438 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 439 | static int |
| 440 | gen6_add_request(struct intel_ring_buffer *ring, |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 441 | u32 *seqno) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 442 | { |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 443 | u32 mbox1_reg; |
| 444 | u32 mbox2_reg; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 445 | int ret; |
| 446 | |
| 447 | ret = intel_ring_begin(ring, 10); |
| 448 | if (ret) |
| 449 | return ret; |
| 450 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 451 | mbox1_reg = ring->signal_mbox[0]; |
| 452 | mbox2_reg = ring->signal_mbox[1]; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 453 | |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 454 | *seqno = i915_gem_next_request_seqno(ring); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 455 | |
| 456 | update_mboxes(ring, *seqno, mbox1_reg); |
| 457 | update_mboxes(ring, *seqno, mbox2_reg); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 458 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 459 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 460 | intel_ring_emit(ring, *seqno); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 461 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 462 | intel_ring_advance(ring); |
| 463 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 464 | return 0; |
| 465 | } |
| 466 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 467 | /** |
| 468 | * intel_ring_sync - sync the waiter to the signaller on seqno |
| 469 | * |
| 470 | * @waiter - ring that is waiting |
| 471 | * @signaller - ring which has, or will signal |
| 472 | * @seqno - seqno which the waiter will block on |
| 473 | */ |
| 474 | static int |
| 475 | intel_ring_sync(struct intel_ring_buffer *waiter, |
| 476 | struct intel_ring_buffer *signaller, |
| 477 | int ring, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 478 | u32 seqno) |
| 479 | { |
| 480 | int ret; |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 481 | u32 dw1 = MI_SEMAPHORE_MBOX | |
| 482 | MI_SEMAPHORE_COMPARE | |
| 483 | MI_SEMAPHORE_REGISTER; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 484 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 485 | ret = intel_ring_begin(waiter, 4); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 486 | if (ret) |
| 487 | return ret; |
| 488 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 489 | intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]); |
| 490 | intel_ring_emit(waiter, seqno); |
| 491 | intel_ring_emit(waiter, 0); |
| 492 | intel_ring_emit(waiter, MI_NOOP); |
| 493 | intel_ring_advance(waiter); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 494 | |
| 495 | return 0; |
| 496 | } |
| 497 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 498 | /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */ |
| 499 | int |
| 500 | render_ring_sync_to(struct intel_ring_buffer *waiter, |
| 501 | struct intel_ring_buffer *signaller, |
| 502 | u32 seqno) |
| 503 | { |
| 504 | WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID); |
| 505 | return intel_ring_sync(waiter, |
| 506 | signaller, |
| 507 | RCS, |
| 508 | seqno); |
| 509 | } |
| 510 | |
| 511 | /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */ |
| 512 | int |
| 513 | gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter, |
| 514 | struct intel_ring_buffer *signaller, |
| 515 | u32 seqno) |
| 516 | { |
| 517 | WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID); |
| 518 | return intel_ring_sync(waiter, |
| 519 | signaller, |
| 520 | VCS, |
| 521 | seqno); |
| 522 | } |
| 523 | |
| 524 | /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */ |
| 525 | int |
| 526 | gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter, |
| 527 | struct intel_ring_buffer *signaller, |
| 528 | u32 seqno) |
| 529 | { |
| 530 | WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID); |
| 531 | return intel_ring_sync(waiter, |
| 532 | signaller, |
| 533 | BCS, |
| 534 | seqno); |
| 535 | } |
| 536 | |
| 537 | |
| 538 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 539 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 540 | do { \ |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 541 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
| 542 | PIPE_CONTROL_DEPTH_STALL); \ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 543 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 544 | intel_ring_emit(ring__, 0); \ |
| 545 | intel_ring_emit(ring__, 0); \ |
| 546 | } while (0) |
| 547 | |
| 548 | static int |
| 549 | pc_render_add_request(struct intel_ring_buffer *ring, |
| 550 | u32 *result) |
| 551 | { |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 552 | u32 seqno = i915_gem_next_request_seqno(ring); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 553 | struct pipe_control *pc = ring->private; |
| 554 | u32 scratch_addr = pc->gtt_offset + 128; |
| 555 | int ret; |
| 556 | |
| 557 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
| 558 | * incoherent with writes to memory, i.e. completely fubar, |
| 559 | * so we need to use PIPE_NOTIFY instead. |
| 560 | * |
| 561 | * However, we also need to workaround the qword write |
| 562 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
| 563 | * memory before requesting an interrupt. |
| 564 | */ |
| 565 | ret = intel_ring_begin(ring, 32); |
| 566 | if (ret) |
| 567 | return ret; |
| 568 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 569 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 570 | PIPE_CONTROL_WRITE_FLUSH | |
| 571 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 572 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 573 | intel_ring_emit(ring, seqno); |
| 574 | intel_ring_emit(ring, 0); |
| 575 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 576 | scratch_addr += 128; /* write to separate cachelines */ |
| 577 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 578 | scratch_addr += 128; |
| 579 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 580 | scratch_addr += 128; |
| 581 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 582 | scratch_addr += 128; |
| 583 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 584 | scratch_addr += 128; |
| 585 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame^] | 586 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 587 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 588 | PIPE_CONTROL_WRITE_FLUSH | |
| 589 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 590 | PIPE_CONTROL_NOTIFY); |
| 591 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 592 | intel_ring_emit(ring, seqno); |
| 593 | intel_ring_emit(ring, 0); |
| 594 | intel_ring_advance(ring); |
| 595 | |
| 596 | *result = seqno; |
| 597 | return 0; |
| 598 | } |
| 599 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 600 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 601 | render_ring_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 602 | u32 *result) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 603 | { |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 604 | u32 seqno = i915_gem_next_request_seqno(ring); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 605 | int ret; |
Zhenyu Wang | ca76482 | 2010-05-27 10:26:42 +0800 | [diff] [blame] | 606 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 607 | ret = intel_ring_begin(ring, 4); |
| 608 | if (ret) |
| 609 | return ret; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 610 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 611 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 612 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 613 | intel_ring_emit(ring, seqno); |
| 614 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 615 | intel_ring_advance(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 616 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 617 | *result = seqno; |
| 618 | return 0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 619 | } |
| 620 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 621 | static u32 |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 622 | gen6_ring_get_seqno(struct intel_ring_buffer *ring) |
| 623 | { |
| 624 | struct drm_device *dev = ring->dev; |
| 625 | |
| 626 | /* Workaround to force correct ordering between irq and seqno writes on |
| 627 | * ivb (and maybe also on snb) by reading from a CS register (like |
| 628 | * ACTHD) before reading the status page. */ |
| 629 | if (IS_GEN7(dev)) |
| 630 | intel_ring_get_active_head(ring); |
| 631 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 632 | } |
| 633 | |
| 634 | static u32 |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 635 | ring_get_seqno(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 636 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 637 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 638 | } |
| 639 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 640 | static u32 |
| 641 | pc_render_get_seqno(struct intel_ring_buffer *ring) |
| 642 | { |
| 643 | struct pipe_control *pc = ring->private; |
| 644 | return pc->cpu_page[0]; |
| 645 | } |
| 646 | |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 647 | static void |
| 648 | ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 649 | { |
| 650 | dev_priv->gt_irq_mask &= ~mask; |
| 651 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 652 | POSTING_READ(GTIMR); |
| 653 | } |
| 654 | |
| 655 | static void |
| 656 | ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 657 | { |
| 658 | dev_priv->gt_irq_mask |= mask; |
| 659 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 660 | POSTING_READ(GTIMR); |
| 661 | } |
| 662 | |
| 663 | static void |
| 664 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 665 | { |
| 666 | dev_priv->irq_mask &= ~mask; |
| 667 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 668 | POSTING_READ(IMR); |
| 669 | } |
| 670 | |
| 671 | static void |
| 672 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 673 | { |
| 674 | dev_priv->irq_mask |= mask; |
| 675 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 676 | POSTING_READ(IMR); |
| 677 | } |
| 678 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 679 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 680 | render_ring_get_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 681 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 682 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 683 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 684 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 685 | if (!dev->irq_enabled) |
| 686 | return false; |
| 687 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 688 | spin_lock(&ring->irq_lock); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 689 | if (ring->irq_refcount++ == 0) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 690 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 691 | ironlake_enable_irq(dev_priv, |
| 692 | GT_PIPE_NOTIFY | GT_USER_INTERRUPT); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 693 | else |
| 694 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); |
| 695 | } |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 696 | spin_unlock(&ring->irq_lock); |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 697 | |
| 698 | return true; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 699 | } |
| 700 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 701 | static void |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 702 | render_ring_put_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 703 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 704 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 705 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 706 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 707 | spin_lock(&ring->irq_lock); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 708 | if (--ring->irq_refcount == 0) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 709 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 710 | ironlake_disable_irq(dev_priv, |
| 711 | GT_USER_INTERRUPT | |
| 712 | GT_PIPE_NOTIFY); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 713 | else |
| 714 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); |
| 715 | } |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 716 | spin_unlock(&ring->irq_lock); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 717 | } |
| 718 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 719 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 720 | { |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 721 | struct drm_device *dev = ring->dev; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 722 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 723 | u32 mmio = 0; |
| 724 | |
| 725 | /* The ring status page addresses are no longer next to the rest of |
| 726 | * the ring registers as of gen7. |
| 727 | */ |
| 728 | if (IS_GEN7(dev)) { |
| 729 | switch (ring->id) { |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 730 | case RCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 731 | mmio = RENDER_HWS_PGA_GEN7; |
| 732 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 733 | case BCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 734 | mmio = BLT_HWS_PGA_GEN7; |
| 735 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 736 | case VCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 737 | mmio = BSD_HWS_PGA_GEN7; |
| 738 | break; |
| 739 | } |
| 740 | } else if (IS_GEN6(ring->dev)) { |
| 741 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
| 742 | } else { |
| 743 | mmio = RING_HWS_PGA(ring->mmio_base); |
| 744 | } |
| 745 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 746 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
| 747 | POSTING_READ(mmio); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 748 | } |
| 749 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 750 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 751 | bsd_ring_flush(struct intel_ring_buffer *ring, |
| 752 | u32 invalidate_domains, |
| 753 | u32 flush_domains) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 754 | { |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 755 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 756 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 757 | ret = intel_ring_begin(ring, 2); |
| 758 | if (ret) |
| 759 | return ret; |
| 760 | |
| 761 | intel_ring_emit(ring, MI_FLUSH); |
| 762 | intel_ring_emit(ring, MI_NOOP); |
| 763 | intel_ring_advance(ring); |
| 764 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 765 | } |
| 766 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 767 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 768 | ring_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 769 | u32 *result) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 770 | { |
| 771 | u32 seqno; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 772 | int ret; |
| 773 | |
| 774 | ret = intel_ring_begin(ring, 4); |
| 775 | if (ret) |
| 776 | return ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 777 | |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 778 | seqno = i915_gem_next_request_seqno(ring); |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 779 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 780 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 781 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 782 | intel_ring_emit(ring, seqno); |
| 783 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 784 | intel_ring_advance(ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 785 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 786 | *result = seqno; |
| 787 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 788 | } |
| 789 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 790 | static bool |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 791 | gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) |
| 792 | { |
| 793 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 794 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 795 | |
| 796 | if (!dev->irq_enabled) |
| 797 | return false; |
| 798 | |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 799 | /* It looks like we need to prevent the gt from suspending while waiting |
| 800 | * for an notifiy irq, otherwise irqs seem to get lost on at least the |
| 801 | * blt/bsd rings on ivb. */ |
Daniel Vetter | 99ffa16 | 2012-01-25 14:04:00 +0100 | [diff] [blame] | 802 | gen6_gt_force_wake_get(dev_priv); |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 803 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 804 | spin_lock(&ring->irq_lock); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 805 | if (ring->irq_refcount++ == 0) { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 806 | ring->irq_mask &= ~rflag; |
| 807 | I915_WRITE_IMR(ring, ring->irq_mask); |
| 808 | ironlake_enable_irq(dev_priv, gflag); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 809 | } |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 810 | spin_unlock(&ring->irq_lock); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 811 | |
| 812 | return true; |
| 813 | } |
| 814 | |
| 815 | static void |
| 816 | gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) |
| 817 | { |
| 818 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 819 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 820 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 821 | spin_lock(&ring->irq_lock); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 822 | if (--ring->irq_refcount == 0) { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 823 | ring->irq_mask |= rflag; |
| 824 | I915_WRITE_IMR(ring, ring->irq_mask); |
| 825 | ironlake_disable_irq(dev_priv, gflag); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 826 | } |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 827 | spin_unlock(&ring->irq_lock); |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 828 | |
Daniel Vetter | 99ffa16 | 2012-01-25 14:04:00 +0100 | [diff] [blame] | 829 | gen6_gt_force_wake_put(dev_priv); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 830 | } |
| 831 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 832 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 833 | bsd_ring_get_irq(struct intel_ring_buffer *ring) |
| 834 | { |
Feng, Boqun | 5bfa106 | 2011-05-16 16:02:39 +0800 | [diff] [blame] | 835 | struct drm_device *dev = ring->dev; |
| 836 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 837 | |
| 838 | if (!dev->irq_enabled) |
| 839 | return false; |
| 840 | |
| 841 | spin_lock(&ring->irq_lock); |
| 842 | if (ring->irq_refcount++ == 0) { |
| 843 | if (IS_G4X(dev)) |
| 844 | i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT); |
| 845 | else |
| 846 | ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT); |
| 847 | } |
| 848 | spin_unlock(&ring->irq_lock); |
| 849 | |
| 850 | return true; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 851 | } |
| 852 | static void |
| 853 | bsd_ring_put_irq(struct intel_ring_buffer *ring) |
| 854 | { |
Feng, Boqun | 5bfa106 | 2011-05-16 16:02:39 +0800 | [diff] [blame] | 855 | struct drm_device *dev = ring->dev; |
| 856 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 857 | |
| 858 | spin_lock(&ring->irq_lock); |
| 859 | if (--ring->irq_refcount == 0) { |
| 860 | if (IS_G4X(dev)) |
| 861 | i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT); |
| 862 | else |
| 863 | ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT); |
| 864 | } |
| 865 | spin_unlock(&ring->irq_lock); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 866 | } |
| 867 | |
| 868 | static int |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 869 | ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 870 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 871 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 872 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 873 | ret = intel_ring_begin(ring, 2); |
| 874 | if (ret) |
| 875 | return ret; |
| 876 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 877 | intel_ring_emit(ring, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 878 | MI_BATCH_BUFFER_START | (2 << 6) | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 879 | MI_BATCH_NON_SECURE_I965); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 880 | intel_ring_emit(ring, offset); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 881 | intel_ring_advance(ring); |
| 882 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 883 | return 0; |
| 884 | } |
| 885 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 886 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 887 | render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 888 | u32 offset, u32 len) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 889 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 890 | struct drm_device *dev = ring->dev; |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 891 | int ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 892 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 893 | if (IS_I830(dev) || IS_845G(dev)) { |
| 894 | ret = intel_ring_begin(ring, 4); |
| 895 | if (ret) |
| 896 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 897 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 898 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 899 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
| 900 | intel_ring_emit(ring, offset + len - 8); |
| 901 | intel_ring_emit(ring, 0); |
| 902 | } else { |
| 903 | ret = intel_ring_begin(ring, 2); |
| 904 | if (ret) |
| 905 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 906 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 907 | if (INTEL_INFO(dev)->gen >= 4) { |
| 908 | intel_ring_emit(ring, |
| 909 | MI_BATCH_BUFFER_START | (2 << 6) | |
| 910 | MI_BATCH_NON_SECURE_I965); |
| 911 | intel_ring_emit(ring, offset); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 912 | } else { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 913 | intel_ring_emit(ring, |
| 914 | MI_BATCH_BUFFER_START | (2 << 6)); |
| 915 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 916 | } |
| 917 | } |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 918 | intel_ring_advance(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 919 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 920 | return 0; |
| 921 | } |
| 922 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 923 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 924 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 925 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 926 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 927 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 928 | obj = ring->status_page.obj; |
| 929 | if (obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 930 | return; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 931 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 932 | kunmap(obj->pages[0]); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 933 | i915_gem_object_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 934 | drm_gem_object_unreference(&obj->base); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 935 | ring->status_page.obj = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 936 | |
| 937 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 938 | } |
| 939 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 940 | static int init_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 941 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 942 | struct drm_device *dev = ring->dev; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 943 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 944 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 945 | int ret; |
| 946 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 947 | obj = i915_gem_alloc_object(dev, 4096); |
| 948 | if (obj == NULL) { |
| 949 | DRM_ERROR("Failed to allocate status page\n"); |
| 950 | ret = -ENOMEM; |
| 951 | goto err; |
| 952 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 953 | |
| 954 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 955 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 956 | ret = i915_gem_object_pin(obj, 4096, true); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 957 | if (ret != 0) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 958 | goto err_unref; |
| 959 | } |
| 960 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 961 | ring->status_page.gfx_addr = obj->gtt_offset; |
| 962 | ring->status_page.page_addr = kmap(obj->pages[0]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 963 | if (ring->status_page.page_addr == NULL) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 964 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 965 | goto err_unpin; |
| 966 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 967 | ring->status_page.obj = obj; |
| 968 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 969 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 970 | intel_ring_setup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 971 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
| 972 | ring->name, ring->status_page.gfx_addr); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 973 | |
| 974 | return 0; |
| 975 | |
| 976 | err_unpin: |
| 977 | i915_gem_object_unpin(obj); |
| 978 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 979 | drm_gem_object_unreference(&obj->base); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 980 | err: |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 981 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 982 | } |
| 983 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 984 | int intel_init_ring_buffer(struct drm_device *dev, |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 985 | struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 986 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 987 | struct drm_i915_gem_object *obj; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 988 | int ret; |
| 989 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 990 | ring->dev = dev; |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 991 | INIT_LIST_HEAD(&ring->active_list); |
| 992 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 993 | INIT_LIST_HEAD(&ring->gpu_write_list); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 994 | |
Chris Wilson | b259f67 | 2011-03-29 13:19:09 +0100 | [diff] [blame] | 995 | init_waitqueue_head(&ring->irq_queue); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 996 | spin_lock_init(&ring->irq_lock); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 997 | ring->irq_mask = ~0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 998 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 999 | if (I915_NEED_GFX_HWS(dev)) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1000 | ret = init_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1001 | if (ret) |
| 1002 | return ret; |
| 1003 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1004 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1005 | obj = i915_gem_alloc_object(dev, ring->size); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1006 | if (obj == NULL) { |
| 1007 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1008 | ret = -ENOMEM; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1009 | goto err_hws; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1010 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1011 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1012 | ring->obj = obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1013 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1014 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1015 | if (ret) |
| 1016 | goto err_unref; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1017 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1018 | ring->map.size = ring->size; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1019 | ring->map.offset = dev->agp->base + obj->gtt_offset; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1020 | ring->map.type = 0; |
| 1021 | ring->map.flags = 0; |
| 1022 | ring->map.mtrr = 0; |
| 1023 | |
| 1024 | drm_core_ioremap_wc(&ring->map, dev); |
| 1025 | if (ring->map.handle == NULL) { |
| 1026 | DRM_ERROR("Failed to map ringbuffer.\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1027 | ret = -EINVAL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1028 | goto err_unpin; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1029 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1030 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1031 | ring->virtual_start = ring->map.handle; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1032 | ret = ring->init(ring); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1033 | if (ret) |
| 1034 | goto err_unmap; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1035 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1036 | /* Workaround an erratum on the i830 which causes a hang if |
| 1037 | * the TAIL pointer points to within the last 2 cachelines |
| 1038 | * of the buffer. |
| 1039 | */ |
| 1040 | ring->effective_size = ring->size; |
| 1041 | if (IS_I830(ring->dev)) |
| 1042 | ring->effective_size -= 128; |
| 1043 | |
Chris Wilson | c584fe4 | 2010-10-29 18:15:52 +0100 | [diff] [blame] | 1044 | return 0; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1045 | |
| 1046 | err_unmap: |
| 1047 | drm_core_ioremapfree(&ring->map, dev); |
| 1048 | err_unpin: |
| 1049 | i915_gem_object_unpin(obj); |
| 1050 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1051 | drm_gem_object_unreference(&obj->base); |
| 1052 | ring->obj = NULL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1053 | err_hws: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1054 | cleanup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1055 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1056 | } |
| 1057 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1058 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1059 | { |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1060 | struct drm_i915_private *dev_priv; |
| 1061 | int ret; |
| 1062 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1063 | if (ring->obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1064 | return; |
| 1065 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1066 | /* Disable the ring buffer. The ring must be idle at this point */ |
| 1067 | dev_priv = ring->dev->dev_private; |
Ben Widawsky | 96f298a | 2011-03-19 18:14:27 -0700 | [diff] [blame] | 1068 | ret = intel_wait_ring_idle(ring); |
Chris Wilson | 29ee399 | 2011-01-24 16:35:42 +0000 | [diff] [blame] | 1069 | if (ret) |
| 1070 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
| 1071 | ring->name, ret); |
| 1072 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1073 | I915_WRITE_CTL(ring, 0); |
| 1074 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1075 | drm_core_ioremapfree(&ring->map, ring->dev); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1076 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1077 | i915_gem_object_unpin(ring->obj); |
| 1078 | drm_gem_object_unreference(&ring->obj->base); |
| 1079 | ring->obj = NULL; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1080 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1081 | if (ring->cleanup) |
| 1082 | ring->cleanup(ring); |
| 1083 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1084 | cleanup_status_page(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1085 | } |
| 1086 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1087 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1088 | { |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1089 | unsigned int *virt; |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1090 | int rem = ring->size - ring->tail; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1091 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1092 | if (ring->space < rem) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1093 | int ret = intel_wait_ring_buffer(ring, rem); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1094 | if (ret) |
| 1095 | return ret; |
| 1096 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1097 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1098 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
Chris Wilson | 1741dd4 | 2010-08-04 15:18:12 +0100 | [diff] [blame] | 1099 | rem /= 8; |
| 1100 | while (rem--) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1101 | *virt++ = MI_NOOP; |
Chris Wilson | 1741dd4 | 2010-08-04 15:18:12 +0100 | [diff] [blame] | 1102 | *virt++ = MI_NOOP; |
| 1103 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1104 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1105 | ring->tail = 0; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1106 | ring->space = ring_space(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1107 | |
| 1108 | return 0; |
| 1109 | } |
| 1110 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame^] | 1111 | static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 1112 | { |
| 1113 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 1114 | bool was_interruptible; |
| 1115 | int ret; |
| 1116 | |
| 1117 | /* XXX As we have not yet audited all the paths to check that |
| 1118 | * they are ready for ERESTARTSYS from intel_ring_begin, do not |
| 1119 | * allow us to be interruptible by a signal. |
| 1120 | */ |
| 1121 | was_interruptible = dev_priv->mm.interruptible; |
| 1122 | dev_priv->mm.interruptible = false; |
| 1123 | |
| 1124 | ret = i915_wait_request(ring, seqno, true); |
| 1125 | |
| 1126 | dev_priv->mm.interruptible = was_interruptible; |
| 1127 | |
| 1128 | return ret; |
| 1129 | } |
| 1130 | |
| 1131 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) |
| 1132 | { |
| 1133 | struct drm_i915_gem_request *request; |
| 1134 | u32 seqno = 0; |
| 1135 | int ret; |
| 1136 | |
| 1137 | i915_gem_retire_requests_ring(ring); |
| 1138 | |
| 1139 | if (ring->last_retired_head != -1) { |
| 1140 | ring->head = ring->last_retired_head; |
| 1141 | ring->last_retired_head = -1; |
| 1142 | ring->space = ring_space(ring); |
| 1143 | if (ring->space >= n) |
| 1144 | return 0; |
| 1145 | } |
| 1146 | |
| 1147 | list_for_each_entry(request, &ring->request_list, list) { |
| 1148 | int space; |
| 1149 | |
| 1150 | if (request->tail == -1) |
| 1151 | continue; |
| 1152 | |
| 1153 | space = request->tail - (ring->tail + 8); |
| 1154 | if (space < 0) |
| 1155 | space += ring->size; |
| 1156 | if (space >= n) { |
| 1157 | seqno = request->seqno; |
| 1158 | break; |
| 1159 | } |
| 1160 | |
| 1161 | /* Consume this request in case we need more space than |
| 1162 | * is available and so need to prevent a race between |
| 1163 | * updating last_retired_head and direct reads of |
| 1164 | * I915_RING_HEAD. It also provides a nice sanity check. |
| 1165 | */ |
| 1166 | request->tail = -1; |
| 1167 | } |
| 1168 | |
| 1169 | if (seqno == 0) |
| 1170 | return -ENOSPC; |
| 1171 | |
| 1172 | ret = intel_ring_wait_seqno(ring, seqno); |
| 1173 | if (ret) |
| 1174 | return ret; |
| 1175 | |
| 1176 | if (WARN_ON(ring->last_retired_head == -1)) |
| 1177 | return -ENOSPC; |
| 1178 | |
| 1179 | ring->head = ring->last_retired_head; |
| 1180 | ring->last_retired_head = -1; |
| 1181 | ring->space = ring_space(ring); |
| 1182 | if (WARN_ON(ring->space < n)) |
| 1183 | return -ENOSPC; |
| 1184 | |
| 1185 | return 0; |
| 1186 | } |
| 1187 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1188 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1189 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1190 | struct drm_device *dev = ring->dev; |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1191 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1192 | unsigned long end; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame^] | 1193 | int ret; |
Chris Wilson | 6aa5606 | 2010-10-29 21:44:37 +0100 | [diff] [blame] | 1194 | u32 head; |
| 1195 | |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1196 | /* If the reported head position has wrapped or hasn't advanced, |
| 1197 | * fallback to the slow and accurate path. |
| 1198 | */ |
| 1199 | head = intel_read_status_page(ring, 4); |
| 1200 | if (head > ring->head) { |
| 1201 | ring->head = head; |
| 1202 | ring->space = ring_space(ring); |
| 1203 | if (ring->space >= n) |
| 1204 | return 0; |
| 1205 | } |
| 1206 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame^] | 1207 | ret = intel_ring_wait_request(ring, n); |
| 1208 | if (ret != -ENOSPC) |
| 1209 | return ret; |
| 1210 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1211 | trace_i915_ring_wait_begin(ring); |
Daniel Vetter | e6bfaf8 | 2011-12-14 13:56:59 +0100 | [diff] [blame] | 1212 | if (drm_core_check_feature(dev, DRIVER_GEM)) |
| 1213 | /* With GEM the hangcheck timer should kick us out of the loop, |
| 1214 | * leaving it early runs the risk of corrupting GEM state (due |
| 1215 | * to running on almost untested codepaths). But on resume |
| 1216 | * timers don't work yet, so prevent a complete hang in that |
| 1217 | * case by choosing an insanely large timeout. */ |
| 1218 | end = jiffies + 60 * HZ; |
| 1219 | else |
| 1220 | end = jiffies + 3 * HZ; |
| 1221 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1222 | do { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1223 | ring->head = I915_READ_HEAD(ring); |
| 1224 | ring->space = ring_space(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1225 | if (ring->space >= n) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1226 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1227 | return 0; |
| 1228 | } |
| 1229 | |
| 1230 | if (dev->primary->master) { |
| 1231 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
| 1232 | if (master_priv->sarea_priv) |
| 1233 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
| 1234 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1235 | |
Chris Wilson | e60a0b1 | 2010-10-13 10:09:14 +0100 | [diff] [blame] | 1236 | msleep(1); |
Chris Wilson | f4e0b29 | 2010-10-29 21:06:16 +0100 | [diff] [blame] | 1237 | if (atomic_read(&dev_priv->mm.wedged)) |
| 1238 | return -EAGAIN; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1239 | } while (!time_after(jiffies, end)); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1240 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1241 | return -EBUSY; |
| 1242 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1243 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1244 | int intel_ring_begin(struct intel_ring_buffer *ring, |
| 1245 | int num_dwords) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1246 | { |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 1247 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Zou Nan hai | be26a10 | 2010-06-12 17:40:24 +0800 | [diff] [blame] | 1248 | int n = 4*num_dwords; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1249 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1250 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 1251 | if (unlikely(atomic_read(&dev_priv->mm.wedged))) |
| 1252 | return -EIO; |
| 1253 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1254 | if (unlikely(ring->tail + n > ring->effective_size)) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1255 | ret = intel_wrap_ring_buffer(ring); |
| 1256 | if (unlikely(ret)) |
| 1257 | return ret; |
| 1258 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1259 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1260 | if (unlikely(ring->space < n)) { |
| 1261 | ret = intel_wait_ring_buffer(ring, n); |
| 1262 | if (unlikely(ret)) |
| 1263 | return ret; |
| 1264 | } |
Chris Wilson | d97ed33 | 2010-08-04 15:18:13 +0100 | [diff] [blame] | 1265 | |
| 1266 | ring->space -= n; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1267 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1268 | } |
| 1269 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1270 | void intel_ring_advance(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1271 | { |
Chris Wilson | d97ed33 | 2010-08-04 15:18:13 +0100 | [diff] [blame] | 1272 | ring->tail &= ring->size - 1; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1273 | ring->write_tail(ring, ring->tail); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1274 | } |
| 1275 | |
Chris Wilson | e070868 | 2010-09-19 14:46:27 +0100 | [diff] [blame] | 1276 | static const struct intel_ring_buffer render_ring = { |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1277 | .name = "render ring", |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 1278 | .id = RCS, |
Daniel Vetter | 333e9fe | 2010-08-02 16:24:01 +0200 | [diff] [blame] | 1279 | .mmio_base = RENDER_RING_BASE, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1280 | .size = 32 * PAGE_SIZE, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1281 | .init = init_render_ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1282 | .write_tail = ring_write_tail, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1283 | .flush = render_ring_flush, |
| 1284 | .add_request = render_ring_add_request, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1285 | .get_seqno = ring_get_seqno, |
| 1286 | .irq_get = render_ring_get_irq, |
| 1287 | .irq_put = render_ring_put_irq, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1288 | .dispatch_execbuffer = render_ring_dispatch_execbuffer, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1289 | .cleanup = render_ring_cleanup, |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1290 | .sync_to = render_ring_sync_to, |
| 1291 | .semaphore_register = {MI_SEMAPHORE_SYNC_INVALID, |
| 1292 | MI_SEMAPHORE_SYNC_RV, |
| 1293 | MI_SEMAPHORE_SYNC_RB}, |
| 1294 | .signal_mbox = {GEN6_VRSYNC, GEN6_BRSYNC}, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1295 | }; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1296 | |
| 1297 | /* ring buffer for bit-stream decoder */ |
| 1298 | |
Chris Wilson | e070868 | 2010-09-19 14:46:27 +0100 | [diff] [blame] | 1299 | static const struct intel_ring_buffer bsd_ring = { |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1300 | .name = "bsd ring", |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 1301 | .id = VCS, |
Daniel Vetter | 333e9fe | 2010-08-02 16:24:01 +0200 | [diff] [blame] | 1302 | .mmio_base = BSD_RING_BASE, |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1303 | .size = 32 * PAGE_SIZE, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1304 | .init = init_ring_common, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1305 | .write_tail = ring_write_tail, |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1306 | .flush = bsd_ring_flush, |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1307 | .add_request = ring_add_request, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1308 | .get_seqno = ring_get_seqno, |
| 1309 | .irq_get = bsd_ring_get_irq, |
| 1310 | .irq_put = bsd_ring_put_irq, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1311 | .dispatch_execbuffer = ring_dispatch_execbuffer, |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1312 | }; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1313 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1314 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1315 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1316 | u32 value) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1317 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1318 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1319 | |
| 1320 | /* Every tail move must follow the sequence below */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1321 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 1322 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
| 1323 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); |
| 1324 | I915_WRITE(GEN6_BSD_RNCID, 0x0); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1325 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1326 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
| 1327 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, |
| 1328 | 50)) |
| 1329 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1330 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1331 | I915_WRITE_TAIL(ring, value); |
| 1332 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 1333 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
| 1334 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1335 | } |
| 1336 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1337 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1338 | u32 invalidate, u32 flush) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1339 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1340 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1341 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1342 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1343 | ret = intel_ring_begin(ring, 4); |
| 1344 | if (ret) |
| 1345 | return ret; |
| 1346 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1347 | cmd = MI_FLUSH_DW; |
| 1348 | if (invalidate & I915_GEM_GPU_DOMAINS) |
| 1349 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
| 1350 | intel_ring_emit(ring, cmd); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1351 | intel_ring_emit(ring, 0); |
| 1352 | intel_ring_emit(ring, 0); |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1353 | intel_ring_emit(ring, MI_NOOP); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1354 | intel_ring_advance(ring); |
| 1355 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1356 | } |
| 1357 | |
| 1358 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1359 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1360 | u32 offset, u32 len) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1361 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1362 | int ret; |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1363 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1364 | ret = intel_ring_begin(ring, 2); |
| 1365 | if (ret) |
| 1366 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1367 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1368 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
| 1369 | /* bit0-7 is the length on GEN6+ */ |
| 1370 | intel_ring_emit(ring, offset); |
| 1371 | intel_ring_advance(ring); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1372 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1373 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1374 | } |
| 1375 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1376 | static bool |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1377 | gen6_render_ring_get_irq(struct intel_ring_buffer *ring) |
| 1378 | { |
| 1379 | return gen6_ring_get_irq(ring, |
| 1380 | GT_USER_INTERRUPT, |
| 1381 | GEN6_RENDER_USER_INTERRUPT); |
| 1382 | } |
| 1383 | |
| 1384 | static void |
| 1385 | gen6_render_ring_put_irq(struct intel_ring_buffer *ring) |
| 1386 | { |
| 1387 | return gen6_ring_put_irq(ring, |
| 1388 | GT_USER_INTERRUPT, |
| 1389 | GEN6_RENDER_USER_INTERRUPT); |
| 1390 | } |
| 1391 | |
| 1392 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1393 | gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring) |
| 1394 | { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1395 | return gen6_ring_get_irq(ring, |
| 1396 | GT_GEN6_BSD_USER_INTERRUPT, |
| 1397 | GEN6_BSD_USER_INTERRUPT); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1398 | } |
| 1399 | |
| 1400 | static void |
| 1401 | gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring) |
| 1402 | { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1403 | return gen6_ring_put_irq(ring, |
| 1404 | GT_GEN6_BSD_USER_INTERRUPT, |
| 1405 | GEN6_BSD_USER_INTERRUPT); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1406 | } |
| 1407 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1408 | /* ring buffer for Video Codec for Gen6+ */ |
Chris Wilson | e070868 | 2010-09-19 14:46:27 +0100 | [diff] [blame] | 1409 | static const struct intel_ring_buffer gen6_bsd_ring = { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1410 | .name = "gen6 bsd ring", |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 1411 | .id = VCS, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1412 | .mmio_base = GEN6_BSD_RING_BASE, |
| 1413 | .size = 32 * PAGE_SIZE, |
| 1414 | .init = init_ring_common, |
| 1415 | .write_tail = gen6_bsd_ring_write_tail, |
| 1416 | .flush = gen6_ring_flush, |
| 1417 | .add_request = gen6_add_request, |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1418 | .get_seqno = gen6_ring_get_seqno, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1419 | .irq_get = gen6_bsd_ring_get_irq, |
| 1420 | .irq_put = gen6_bsd_ring_put_irq, |
| 1421 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1422 | .sync_to = gen6_bsd_ring_sync_to, |
| 1423 | .semaphore_register = {MI_SEMAPHORE_SYNC_VR, |
| 1424 | MI_SEMAPHORE_SYNC_INVALID, |
| 1425 | MI_SEMAPHORE_SYNC_VB}, |
| 1426 | .signal_mbox = {GEN6_RVSYNC, GEN6_BVSYNC}, |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1427 | }; |
| 1428 | |
| 1429 | /* Blitter support (SandyBridge+) */ |
| 1430 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1431 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1432 | blt_ring_get_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1433 | { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1434 | return gen6_ring_get_irq(ring, |
| 1435 | GT_BLT_USER_INTERRUPT, |
| 1436 | GEN6_BLITTER_USER_INTERRUPT); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1437 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1438 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1439 | static void |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1440 | blt_ring_put_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1441 | { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1442 | gen6_ring_put_irq(ring, |
| 1443 | GT_BLT_USER_INTERRUPT, |
| 1444 | GEN6_BLITTER_USER_INTERRUPT); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1445 | } |
| 1446 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1447 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1448 | u32 invalidate, u32 flush) |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1449 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1450 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1451 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1452 | |
Daniel Vetter | 6a233c7 | 2011-12-14 13:57:07 +0100 | [diff] [blame] | 1453 | ret = intel_ring_begin(ring, 4); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1454 | if (ret) |
| 1455 | return ret; |
| 1456 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1457 | cmd = MI_FLUSH_DW; |
| 1458 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
| 1459 | cmd |= MI_INVALIDATE_TLB; |
| 1460 | intel_ring_emit(ring, cmd); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1461 | intel_ring_emit(ring, 0); |
| 1462 | intel_ring_emit(ring, 0); |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1463 | intel_ring_emit(ring, MI_NOOP); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1464 | intel_ring_advance(ring); |
| 1465 | return 0; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1466 | } |
| 1467 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1468 | static const struct intel_ring_buffer gen6_blt_ring = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1469 | .name = "blt ring", |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 1470 | .id = BCS, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1471 | .mmio_base = BLT_RING_BASE, |
| 1472 | .size = 32 * PAGE_SIZE, |
Daniel Vetter | 6a233c7 | 2011-12-14 13:57:07 +0100 | [diff] [blame] | 1473 | .init = init_ring_common, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1474 | .write_tail = ring_write_tail, |
| 1475 | .flush = blt_ring_flush, |
| 1476 | .add_request = gen6_add_request, |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1477 | .get_seqno = gen6_ring_get_seqno, |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1478 | .irq_get = blt_ring_get_irq, |
| 1479 | .irq_put = blt_ring_put_irq, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1480 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1481 | .sync_to = gen6_blt_ring_sync_to, |
| 1482 | .semaphore_register = {MI_SEMAPHORE_SYNC_BR, |
| 1483 | MI_SEMAPHORE_SYNC_BV, |
| 1484 | MI_SEMAPHORE_SYNC_INVALID}, |
| 1485 | .signal_mbox = {GEN6_RBSYNC, GEN6_VBSYNC}, |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1486 | }; |
| 1487 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1488 | int intel_init_render_ring_buffer(struct drm_device *dev) |
| 1489 | { |
| 1490 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1491 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1492 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1493 | *ring = render_ring; |
| 1494 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1495 | ring->add_request = gen6_add_request; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 1496 | ring->flush = gen6_render_ring_flush; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1497 | ring->irq_get = gen6_render_ring_get_irq; |
| 1498 | ring->irq_put = gen6_render_ring_put_irq; |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1499 | ring->get_seqno = gen6_ring_get_seqno; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1500 | } else if (IS_GEN5(dev)) { |
| 1501 | ring->add_request = pc_render_add_request; |
| 1502 | ring->get_seqno = pc_render_get_seqno; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1503 | } |
| 1504 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1505 | if (!I915_NEED_GFX_HWS(dev)) { |
| 1506 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1507 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
| 1508 | } |
| 1509 | |
| 1510 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1511 | } |
| 1512 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1513 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
| 1514 | { |
| 1515 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1516 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
| 1517 | |
| 1518 | *ring = render_ring; |
| 1519 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1520 | ring->add_request = gen6_add_request; |
| 1521 | ring->irq_get = gen6_render_ring_get_irq; |
| 1522 | ring->irq_put = gen6_render_ring_put_irq; |
| 1523 | } else if (IS_GEN5(dev)) { |
| 1524 | ring->add_request = pc_render_add_request; |
| 1525 | ring->get_seqno = pc_render_get_seqno; |
| 1526 | } |
| 1527 | |
Keith Packard | f323470 | 2011-07-22 10:44:39 -0700 | [diff] [blame] | 1528 | if (!I915_NEED_GFX_HWS(dev)) |
| 1529 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1530 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1531 | ring->dev = dev; |
| 1532 | INIT_LIST_HEAD(&ring->active_list); |
| 1533 | INIT_LIST_HEAD(&ring->request_list); |
| 1534 | INIT_LIST_HEAD(&ring->gpu_write_list); |
| 1535 | |
| 1536 | ring->size = size; |
| 1537 | ring->effective_size = ring->size; |
| 1538 | if (IS_I830(ring->dev)) |
| 1539 | ring->effective_size -= 128; |
| 1540 | |
| 1541 | ring->map.offset = start; |
| 1542 | ring->map.size = size; |
| 1543 | ring->map.type = 0; |
| 1544 | ring->map.flags = 0; |
| 1545 | ring->map.mtrr = 0; |
| 1546 | |
| 1547 | drm_core_ioremap_wc(&ring->map, dev); |
| 1548 | if (ring->map.handle == NULL) { |
| 1549 | DRM_ERROR("can not ioremap virtual address for" |
| 1550 | " ring buffer\n"); |
| 1551 | return -ENOMEM; |
| 1552 | } |
| 1553 | |
| 1554 | ring->virtual_start = (void __force __iomem *)ring->map.handle; |
| 1555 | return 0; |
| 1556 | } |
| 1557 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1558 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
| 1559 | { |
| 1560 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1561 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1562 | |
Jesse Barnes | 65d3eb1 | 2011-04-06 14:54:44 -0700 | [diff] [blame] | 1563 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1564 | *ring = gen6_bsd_ring; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1565 | else |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1566 | *ring = bsd_ring; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1567 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1568 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1569 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1570 | |
| 1571 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
| 1572 | { |
| 1573 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1574 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1575 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1576 | *ring = gen6_blt_ring; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1577 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1578 | return intel_init_ring_buffer(dev, ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1579 | } |