Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Source for the r8a7790 SoC |
| 3 | * |
Kazuya Mizuguchi | b621f6d | 2015-02-19 10:42:55 -0500 | [diff] [blame] | 4 | * Copyright (C) 2015 Renesas Electronics Corporation |
Sergei Shtylyov | d8913c6 | 2014-02-20 02:20:43 +0300 | [diff] [blame] | 5 | * Copyright (C) 2013-2014 Renesas Solutions Corp. |
| 6 | * Copyright (C) 2014 Cogent Embedded Inc. |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public License |
| 9 | * version 2. This program is licensed "as is" without any warranty of any |
| 10 | * kind, whether express or implied. |
| 11 | */ |
| 12 | |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 13 | #include <dt-bindings/clock/r8a7790-clock.h> |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 16 | |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 17 | / { |
| 18 | compatible = "renesas,r8a7790"; |
| 19 | interrupt-parent = <&gic>; |
Takashi Yoshii | 8585deb | 2013-03-29 16:49:17 +0900 | [diff] [blame] | 20 | #address-cells = <2>; |
| 21 | #size-cells = <2>; |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 22 | |
Wolfram Sang | 6b1d7c6 | 2014-02-16 10:40:58 +0100 | [diff] [blame] | 23 | aliases { |
| 24 | i2c0 = &i2c0; |
| 25 | i2c1 = &i2c1; |
| 26 | i2c2 = &i2c2; |
| 27 | i2c3 = &i2c3; |
Wolfram Sang | 05f3991 | 2014-03-25 19:56:29 +0100 | [diff] [blame] | 28 | i2c4 = &iic0; |
| 29 | i2c5 = &iic1; |
| 30 | i2c6 = &iic2; |
| 31 | i2c7 = &iic3; |
Geert Uytterhoeven | fad6d45 | 2014-02-25 11:30:13 +0100 | [diff] [blame] | 32 | spi0 = &qspi; |
Geert Uytterhoeven | ae8a614 | 2014-02-25 11:30:15 +0100 | [diff] [blame] | 33 | spi1 = &msiof0; |
| 34 | spi2 = &msiof1; |
| 35 | spi3 = &msiof2; |
| 36 | spi4 = &msiof3; |
Ben Dooks | 9f685bf | 2014-08-13 00:16:18 +0400 | [diff] [blame] | 37 | vin0 = &vin0; |
| 38 | vin1 = &vin1; |
| 39 | vin2 = &vin2; |
| 40 | vin3 = &vin3; |
Wolfram Sang | 6b1d7c6 | 2014-02-16 10:40:58 +0100 | [diff] [blame] | 41 | }; |
| 42 | |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 43 | cpus { |
| 44 | #address-cells = <1>; |
| 45 | #size-cells = <0>; |
| 46 | |
| 47 | cpu0: cpu@0 { |
| 48 | device_type = "cpu"; |
| 49 | compatible = "arm,cortex-a15"; |
| 50 | reg = <0>; |
| 51 | clock-frequency = <1300000000>; |
Benoit Cousson | b989e13 | 2014-06-03 21:02:24 +0900 | [diff] [blame] | 52 | voltage-tolerance = <1>; /* 1% */ |
| 53 | clocks = <&cpg_clocks R8A7790_CLK_Z>; |
| 54 | clock-latency = <300000>; /* 300 us */ |
| 55 | |
| 56 | /* kHz - uV - OPPs unknown yet */ |
| 57 | operating-points = <1400000 1000000>, |
| 58 | <1225000 1000000>, |
| 59 | <1050000 1000000>, |
| 60 | < 875000 1000000>, |
| 61 | < 700000 1000000>, |
| 62 | < 350000 1000000>; |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 63 | }; |
Magnus Damm | c1f9597 | 2013-08-29 08:22:17 +0900 | [diff] [blame] | 64 | |
| 65 | cpu1: cpu@1 { |
| 66 | device_type = "cpu"; |
| 67 | compatible = "arm,cortex-a15"; |
| 68 | reg = <1>; |
| 69 | clock-frequency = <1300000000>; |
| 70 | }; |
| 71 | |
| 72 | cpu2: cpu@2 { |
| 73 | device_type = "cpu"; |
| 74 | compatible = "arm,cortex-a15"; |
| 75 | reg = <2>; |
| 76 | clock-frequency = <1300000000>; |
| 77 | }; |
| 78 | |
| 79 | cpu3: cpu@3 { |
| 80 | device_type = "cpu"; |
| 81 | compatible = "arm,cortex-a15"; |
| 82 | reg = <3>; |
| 83 | clock-frequency = <1300000000>; |
| 84 | }; |
Magnus Damm | 2007e74 | 2013-09-15 00:28:58 +0900 | [diff] [blame] | 85 | |
| 86 | cpu4: cpu@4 { |
| 87 | device_type = "cpu"; |
| 88 | compatible = "arm,cortex-a7"; |
| 89 | reg = <0x100>; |
| 90 | clock-frequency = <780000000>; |
| 91 | }; |
| 92 | |
| 93 | cpu5: cpu@5 { |
| 94 | device_type = "cpu"; |
| 95 | compatible = "arm,cortex-a7"; |
| 96 | reg = <0x101>; |
| 97 | clock-frequency = <780000000>; |
| 98 | }; |
| 99 | |
| 100 | cpu6: cpu@6 { |
| 101 | device_type = "cpu"; |
| 102 | compatible = "arm,cortex-a7"; |
| 103 | reg = <0x102>; |
| 104 | clock-frequency = <780000000>; |
| 105 | }; |
| 106 | |
| 107 | cpu7: cpu@7 { |
| 108 | device_type = "cpu"; |
| 109 | compatible = "arm,cortex-a7"; |
| 110 | reg = <0x103>; |
| 111 | clock-frequency = <780000000>; |
| 112 | }; |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 113 | }; |
| 114 | |
Kuninori Morimoto | a8b805f | 2016-01-28 02:45:34 +0000 | [diff] [blame^] | 115 | thermal-zones { |
| 116 | cpu_thermal: cpu-thermal { |
| 117 | polling-delay-passive = <0>; |
| 118 | polling-delay = <0>; |
| 119 | |
| 120 | thermal-sensors = <&thermal>; |
| 121 | |
| 122 | trips { |
| 123 | cpu-crit { |
| 124 | temperature = <115000>; |
| 125 | hysteresis = <0>; |
| 126 | type = "critical"; |
| 127 | }; |
| 128 | }; |
| 129 | cooling-maps { |
| 130 | }; |
| 131 | }; |
| 132 | }; |
| 133 | |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 134 | gic: interrupt-controller@f1001000 { |
Geert Uytterhoeven | e715e9c | 2015-06-17 15:03:33 +0200 | [diff] [blame] | 135 | compatible = "arm,gic-400"; |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 136 | #interrupt-cells = <3>; |
| 137 | #address-cells = <0>; |
| 138 | interrupt-controller; |
Takashi Yoshii | 8585deb | 2013-03-29 16:49:17 +0900 | [diff] [blame] | 139 | reg = <0 0xf1001000 0 0x1000>, |
| 140 | <0 0xf1002000 0 0x1000>, |
| 141 | <0 0xf1004000 0 0x2000>, |
| 142 | <0 0xf1006000 0 0x2000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 143 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 144 | }; |
| 145 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 146 | gpio0: gpio@e6050000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 147 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 148 | reg = <0 0xe6050000 0 0x50>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 149 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 150 | #gpio-cells = <2>; |
| 151 | gpio-controller; |
| 152 | gpio-ranges = <&pfc 0 0 32>; |
| 153 | #interrupt-cells = <2>; |
| 154 | interrupt-controller; |
Geert Uytterhoeven | 81f6883 | 2014-04-23 10:25:27 +0200 | [diff] [blame] | 155 | clocks = <&mstp9_clks R8A7790_CLK_GPIO0>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 156 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 157 | }; |
| 158 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 159 | gpio1: gpio@e6051000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 160 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 161 | reg = <0 0xe6051000 0 0x50>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 162 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 163 | #gpio-cells = <2>; |
| 164 | gpio-controller; |
Sergei Shtylyov | 56a2182f | 2015-10-22 02:04:41 +0300 | [diff] [blame] | 165 | gpio-ranges = <&pfc 0 32 30>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 166 | #interrupt-cells = <2>; |
| 167 | interrupt-controller; |
Geert Uytterhoeven | 81f6883 | 2014-04-23 10:25:27 +0200 | [diff] [blame] | 168 | clocks = <&mstp9_clks R8A7790_CLK_GPIO1>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 169 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 170 | }; |
| 171 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 172 | gpio2: gpio@e6052000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 173 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 174 | reg = <0 0xe6052000 0 0x50>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 175 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 176 | #gpio-cells = <2>; |
| 177 | gpio-controller; |
Sergei Shtylyov | 56a2182f | 2015-10-22 02:04:41 +0300 | [diff] [blame] | 178 | gpio-ranges = <&pfc 0 64 30>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 179 | #interrupt-cells = <2>; |
| 180 | interrupt-controller; |
Geert Uytterhoeven | 81f6883 | 2014-04-23 10:25:27 +0200 | [diff] [blame] | 181 | clocks = <&mstp9_clks R8A7790_CLK_GPIO2>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 182 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 183 | }; |
| 184 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 185 | gpio3: gpio@e6053000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 186 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 187 | reg = <0 0xe6053000 0 0x50>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 188 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 189 | #gpio-cells = <2>; |
| 190 | gpio-controller; |
| 191 | gpio-ranges = <&pfc 0 96 32>; |
| 192 | #interrupt-cells = <2>; |
| 193 | interrupt-controller; |
Geert Uytterhoeven | 81f6883 | 2014-04-23 10:25:27 +0200 | [diff] [blame] | 194 | clocks = <&mstp9_clks R8A7790_CLK_GPIO3>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 195 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 196 | }; |
| 197 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 198 | gpio4: gpio@e6054000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 199 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 200 | reg = <0 0xe6054000 0 0x50>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 201 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 202 | #gpio-cells = <2>; |
| 203 | gpio-controller; |
| 204 | gpio-ranges = <&pfc 0 128 32>; |
| 205 | #interrupt-cells = <2>; |
| 206 | interrupt-controller; |
Geert Uytterhoeven | 81f6883 | 2014-04-23 10:25:27 +0200 | [diff] [blame] | 207 | clocks = <&mstp9_clks R8A7790_CLK_GPIO4>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 208 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 209 | }; |
| 210 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 211 | gpio5: gpio@e6055000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 212 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 213 | reg = <0 0xe6055000 0 0x50>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 214 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 215 | #gpio-cells = <2>; |
| 216 | gpio-controller; |
| 217 | gpio-ranges = <&pfc 0 160 32>; |
| 218 | #interrupt-cells = <2>; |
| 219 | interrupt-controller; |
Geert Uytterhoeven | 81f6883 | 2014-04-23 10:25:27 +0200 | [diff] [blame] | 220 | clocks = <&mstp9_clks R8A7790_CLK_GPIO5>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 221 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 222 | }; |
| 223 | |
Kuninori Morimoto | a8b805f | 2016-01-28 02:45:34 +0000 | [diff] [blame^] | 224 | thermal: thermal@e61f0000 { |
| 225 | compatible = "renesas,thermal-r8a7790", |
| 226 | "renesas,rcar-gen2-thermal", |
| 227 | "renesas,rcar-thermal"; |
Magnus Damm | 03e2f56 | 2013-11-20 16:59:30 +0900 | [diff] [blame] | 228 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 229 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | d3a439d | 2014-01-07 19:57:14 +0100 | [diff] [blame] | 230 | clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 231 | power-domains = <&cpg_clocks>; |
Kuninori Morimoto | a8b805f | 2016-01-28 02:45:34 +0000 | [diff] [blame^] | 232 | #thermal-sensor-cells = <0>; |
Magnus Damm | 03e2f56 | 2013-11-20 16:59:30 +0900 | [diff] [blame] | 233 | }; |
| 234 | |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 235 | timer { |
| 236 | compatible = "arm,armv7-timer"; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 237 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 238 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 239 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 240 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 241 | }; |
Magnus Damm | 8f5ec0a | 2013-03-28 00:49:54 +0900 | [diff] [blame] | 242 | |
Laurent Pinchart | 39cf6d7 | 2014-07-09 15:12:37 +0200 | [diff] [blame] | 243 | cmt0: timer@ffca0000 { |
Simon Horman | 3775703 | 2014-09-08 09:27:45 +0900 | [diff] [blame] | 244 | compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; |
Laurent Pinchart | 39cf6d7 | 2014-07-09 15:12:37 +0200 | [diff] [blame] | 245 | reg = <0 0xffca0000 0 0x1004>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 246 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 247 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 39cf6d7 | 2014-07-09 15:12:37 +0200 | [diff] [blame] | 248 | clocks = <&mstp1_clks R8A7790_CLK_CMT0>; |
| 249 | clock-names = "fck"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 250 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 39cf6d7 | 2014-07-09 15:12:37 +0200 | [diff] [blame] | 251 | |
| 252 | renesas,channels-mask = <0x60>; |
| 253 | |
| 254 | status = "disabled"; |
| 255 | }; |
| 256 | |
| 257 | cmt1: timer@e6130000 { |
Simon Horman | 3775703 | 2014-09-08 09:27:45 +0900 | [diff] [blame] | 258 | compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; |
Laurent Pinchart | 39cf6d7 | 2014-07-09 15:12:37 +0200 | [diff] [blame] | 259 | reg = <0 0xe6130000 0 0x1004>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 260 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
| 261 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 262 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, |
| 263 | <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
| 264 | <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, |
| 265 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, |
| 266 | <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, |
| 267 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 39cf6d7 | 2014-07-09 15:12:37 +0200 | [diff] [blame] | 268 | clocks = <&mstp3_clks R8A7790_CLK_CMT1>; |
| 269 | clock-names = "fck"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 270 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 39cf6d7 | 2014-07-09 15:12:37 +0200 | [diff] [blame] | 271 | |
| 272 | renesas,channels-mask = <0xff>; |
| 273 | |
| 274 | status = "disabled"; |
| 275 | }; |
| 276 | |
Magnus Damm | 8f5ec0a | 2013-03-28 00:49:54 +0900 | [diff] [blame] | 277 | irqc0: interrupt-controller@e61c0000 { |
Magnus Damm | 220fc35 | 2013-11-20 09:07:40 +0900 | [diff] [blame] | 278 | compatible = "renesas,irqc-r8a7790", "renesas,irqc"; |
Magnus Damm | 8f5ec0a | 2013-03-28 00:49:54 +0900 | [diff] [blame] | 279 | #interrupt-cells = <2>; |
| 280 | interrupt-controller; |
Takashi Yoshii | 8585deb | 2013-03-29 16:49:17 +0900 | [diff] [blame] | 281 | reg = <0 0xe61c0000 0 0x200>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 282 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 283 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 284 | <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, |
| 285 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 61624ca | 2015-03-18 19:55:59 +0100 | [diff] [blame] | 286 | clocks = <&mstp4_clks R8A7790_CLK_IRQC>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 287 | power-domains = <&cpg_clocks>; |
Magnus Damm | 8f5ec0a | 2013-03-28 00:49:54 +0900 | [diff] [blame] | 288 | }; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 289 | |
Laurent Pinchart | b9fea49 | 2014-07-19 01:50:24 +0200 | [diff] [blame] | 290 | dmac0: dma-controller@e6700000 { |
Simon Horman | 4af0a66 | 2015-11-13 11:23:48 +0900 | [diff] [blame] | 291 | compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; |
Laurent Pinchart | b9fea49 | 2014-07-19 01:50:24 +0200 | [diff] [blame] | 292 | reg = <0 0xe6700000 0 0x20000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 293 | interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH |
| 294 | GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH |
| 295 | GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH |
| 296 | GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH |
| 297 | GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH |
| 298 | GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH |
| 299 | GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH |
| 300 | GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH |
| 301 | GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH |
| 302 | GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH |
| 303 | GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH |
| 304 | GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH |
| 305 | GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH |
| 306 | GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH |
| 307 | GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH |
| 308 | GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | b9fea49 | 2014-07-19 01:50:24 +0200 | [diff] [blame] | 309 | interrupt-names = "error", |
| 310 | "ch0", "ch1", "ch2", "ch3", |
| 311 | "ch4", "ch5", "ch6", "ch7", |
| 312 | "ch8", "ch9", "ch10", "ch11", |
| 313 | "ch12", "ch13", "ch14"; |
| 314 | clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; |
| 315 | clock-names = "fck"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 316 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | b9fea49 | 2014-07-19 01:50:24 +0200 | [diff] [blame] | 317 | #dma-cells = <1>; |
| 318 | dma-channels = <15>; |
| 319 | }; |
| 320 | |
| 321 | dmac1: dma-controller@e6720000 { |
Simon Horman | 4af0a66 | 2015-11-13 11:23:48 +0900 | [diff] [blame] | 322 | compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; |
Laurent Pinchart | b9fea49 | 2014-07-19 01:50:24 +0200 | [diff] [blame] | 323 | reg = <0 0xe6720000 0 0x20000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 324 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH |
| 325 | GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH |
| 326 | GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH |
| 327 | GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH |
| 328 | GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH |
| 329 | GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH |
| 330 | GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH |
| 331 | GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH |
| 332 | GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH |
| 333 | GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH |
| 334 | GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH |
| 335 | GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH |
| 336 | GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH |
| 337 | GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH |
| 338 | GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH |
| 339 | GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | b9fea49 | 2014-07-19 01:50:24 +0200 | [diff] [blame] | 340 | interrupt-names = "error", |
| 341 | "ch0", "ch1", "ch2", "ch3", |
| 342 | "ch4", "ch5", "ch6", "ch7", |
| 343 | "ch8", "ch9", "ch10", "ch11", |
| 344 | "ch12", "ch13", "ch14"; |
| 345 | clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; |
| 346 | clock-names = "fck"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 347 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | b9fea49 | 2014-07-19 01:50:24 +0200 | [diff] [blame] | 348 | #dma-cells = <1>; |
| 349 | dma-channels = <15>; |
| 350 | }; |
Kuninori Morimoto | ba3240b | 2014-11-03 17:44:51 -0800 | [diff] [blame] | 351 | |
| 352 | audma0: dma-controller@ec700000 { |
Simon Horman | 4af0a66 | 2015-11-13 11:23:48 +0900 | [diff] [blame] | 353 | compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; |
Kuninori Morimoto | ba3240b | 2014-11-03 17:44:51 -0800 | [diff] [blame] | 354 | reg = <0 0xec700000 0 0x10000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 355 | interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH |
| 356 | GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH |
| 357 | GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH |
| 358 | GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH |
| 359 | GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH |
| 360 | GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH |
| 361 | GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH |
| 362 | GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH |
| 363 | GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH |
| 364 | GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH |
| 365 | GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH |
| 366 | GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH |
| 367 | GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH |
| 368 | GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | ba3240b | 2014-11-03 17:44:51 -0800 | [diff] [blame] | 369 | interrupt-names = "error", |
| 370 | "ch0", "ch1", "ch2", "ch3", |
| 371 | "ch4", "ch5", "ch6", "ch7", |
| 372 | "ch8", "ch9", "ch10", "ch11", |
| 373 | "ch12"; |
| 374 | clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>; |
| 375 | clock-names = "fck"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 376 | power-domains = <&cpg_clocks>; |
Kuninori Morimoto | ba3240b | 2014-11-03 17:44:51 -0800 | [diff] [blame] | 377 | #dma-cells = <1>; |
| 378 | dma-channels = <13>; |
| 379 | }; |
| 380 | |
| 381 | audma1: dma-controller@ec720000 { |
Simon Horman | 4af0a66 | 2015-11-13 11:23:48 +0900 | [diff] [blame] | 382 | compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; |
Kuninori Morimoto | ba3240b | 2014-11-03 17:44:51 -0800 | [diff] [blame] | 383 | reg = <0 0xec720000 0 0x10000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 384 | interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH |
| 385 | GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH |
| 386 | GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH |
| 387 | GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH |
| 388 | GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH |
| 389 | GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH |
| 390 | GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH |
| 391 | GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH |
| 392 | GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH |
| 393 | GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH |
| 394 | GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH |
| 395 | GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH |
| 396 | GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH |
| 397 | GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | ba3240b | 2014-11-03 17:44:51 -0800 | [diff] [blame] | 398 | interrupt-names = "error", |
| 399 | "ch0", "ch1", "ch2", "ch3", |
| 400 | "ch4", "ch5", "ch6", "ch7", |
| 401 | "ch8", "ch9", "ch10", "ch11", |
| 402 | "ch12"; |
| 403 | clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>; |
| 404 | clock-names = "fck"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 405 | power-domains = <&cpg_clocks>; |
Kuninori Morimoto | ba3240b | 2014-11-03 17:44:51 -0800 | [diff] [blame] | 406 | #dma-cells = <1>; |
| 407 | dma-channels = <13>; |
| 408 | }; |
| 409 | |
Yoshihiro Shimoda | a3ff209 | 2015-05-08 16:13:06 +0900 | [diff] [blame] | 410 | usb_dmac0: dma-controller@e65a0000 { |
Simon Horman | d01c8be | 2015-12-11 11:59:38 +0900 | [diff] [blame] | 411 | compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac"; |
Yoshihiro Shimoda | a3ff209 | 2015-05-08 16:13:06 +0900 | [diff] [blame] | 412 | reg = <0 0xe65a0000 0 0x100>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 413 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH |
| 414 | GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
Yoshihiro Shimoda | a3ff209 | 2015-05-08 16:13:06 +0900 | [diff] [blame] | 415 | interrupt-names = "ch0", "ch1"; |
| 416 | clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 417 | power-domains = <&cpg_clocks>; |
Yoshihiro Shimoda | a3ff209 | 2015-05-08 16:13:06 +0900 | [diff] [blame] | 418 | #dma-cells = <1>; |
| 419 | dma-channels = <2>; |
| 420 | }; |
| 421 | |
| 422 | usb_dmac1: dma-controller@e65b0000 { |
Simon Horman | d01c8be | 2015-12-11 11:59:38 +0900 | [diff] [blame] | 423 | compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac"; |
Yoshihiro Shimoda | a3ff209 | 2015-05-08 16:13:06 +0900 | [diff] [blame] | 424 | reg = <0 0xe65b0000 0 0x100>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 425 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH |
| 426 | GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
Yoshihiro Shimoda | a3ff209 | 2015-05-08 16:13:06 +0900 | [diff] [blame] | 427 | interrupt-names = "ch0", "ch1"; |
| 428 | clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 429 | power-domains = <&cpg_clocks>; |
Yoshihiro Shimoda | a3ff209 | 2015-05-08 16:13:06 +0900 | [diff] [blame] | 430 | #dma-cells = <1>; |
| 431 | dma-channels = <2>; |
| 432 | }; |
| 433 | |
Guennadi Liakhovetski | edd2b9f | 2013-09-26 19:20:58 +0200 | [diff] [blame] | 434 | i2c0: i2c@e6508000 { |
| 435 | #address-cells = <1>; |
| 436 | #size-cells = <0>; |
| 437 | compatible = "renesas,i2c-r8a7790"; |
| 438 | reg = <0 0xe6508000 0 0x40>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 439 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; |
Ben Dooks | 2450bad | 2014-01-20 11:44:21 +0000 | [diff] [blame] | 440 | clocks = <&mstp9_clks R8A7790_CLK_I2C0>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 441 | power-domains = <&cpg_clocks>; |
Wolfram Sang | ac8e7f3 | 2015-12-08 10:37:50 +0100 | [diff] [blame] | 442 | i2c-scl-internal-delay-ns = <110>; |
Guennadi Liakhovetski | edd2b9f | 2013-09-26 19:20:58 +0200 | [diff] [blame] | 443 | status = "disabled"; |
| 444 | }; |
| 445 | |
| 446 | i2c1: i2c@e6518000 { |
| 447 | #address-cells = <1>; |
| 448 | #size-cells = <0>; |
| 449 | compatible = "renesas,i2c-r8a7790"; |
| 450 | reg = <0 0xe6518000 0 0x40>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 451 | interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; |
Ben Dooks | 2450bad | 2014-01-20 11:44:21 +0000 | [diff] [blame] | 452 | clocks = <&mstp9_clks R8A7790_CLK_I2C1>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 453 | power-domains = <&cpg_clocks>; |
Wolfram Sang | ac8e7f3 | 2015-12-08 10:37:50 +0100 | [diff] [blame] | 454 | i2c-scl-internal-delay-ns = <6>; |
Guennadi Liakhovetski | edd2b9f | 2013-09-26 19:20:58 +0200 | [diff] [blame] | 455 | status = "disabled"; |
| 456 | }; |
| 457 | |
| 458 | i2c2: i2c@e6530000 { |
| 459 | #address-cells = <1>; |
| 460 | #size-cells = <0>; |
| 461 | compatible = "renesas,i2c-r8a7790"; |
| 462 | reg = <0 0xe6530000 0 0x40>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 463 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; |
Ben Dooks | 2450bad | 2014-01-20 11:44:21 +0000 | [diff] [blame] | 464 | clocks = <&mstp9_clks R8A7790_CLK_I2C2>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 465 | power-domains = <&cpg_clocks>; |
Wolfram Sang | ac8e7f3 | 2015-12-08 10:37:50 +0100 | [diff] [blame] | 466 | i2c-scl-internal-delay-ns = <6>; |
Guennadi Liakhovetski | edd2b9f | 2013-09-26 19:20:58 +0200 | [diff] [blame] | 467 | status = "disabled"; |
| 468 | }; |
| 469 | |
| 470 | i2c3: i2c@e6540000 { |
| 471 | #address-cells = <1>; |
| 472 | #size-cells = <0>; |
| 473 | compatible = "renesas,i2c-r8a7790"; |
| 474 | reg = <0 0xe6540000 0 0x40>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 475 | interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; |
Ben Dooks | 2450bad | 2014-01-20 11:44:21 +0000 | [diff] [blame] | 476 | clocks = <&mstp9_clks R8A7790_CLK_I2C3>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 477 | power-domains = <&cpg_clocks>; |
Wolfram Sang | ac8e7f3 | 2015-12-08 10:37:50 +0100 | [diff] [blame] | 478 | i2c-scl-internal-delay-ns = <110>; |
Guennadi Liakhovetski | edd2b9f | 2013-09-26 19:20:58 +0200 | [diff] [blame] | 479 | status = "disabled"; |
| 480 | }; |
| 481 | |
Wolfram Sang | 05f3991 | 2014-03-25 19:56:29 +0100 | [diff] [blame] | 482 | iic0: i2c@e6500000 { |
| 483 | #address-cells = <1>; |
| 484 | #size-cells = <0>; |
| 485 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; |
| 486 | reg = <0 0xe6500000 0 0x425>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 487 | interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
Wolfram Sang | 05f3991 | 2014-03-25 19:56:29 +0100 | [diff] [blame] | 488 | clocks = <&mstp3_clks R8A7790_CLK_IIC0>; |
Wolfram Sang | 0d73ca4 | 2014-11-07 11:11:43 +0100 | [diff] [blame] | 489 | dmas = <&dmac0 0x61>, <&dmac0 0x62>; |
| 490 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 491 | power-domains = <&cpg_clocks>; |
Wolfram Sang | 05f3991 | 2014-03-25 19:56:29 +0100 | [diff] [blame] | 492 | status = "disabled"; |
| 493 | }; |
| 494 | |
| 495 | iic1: i2c@e6510000 { |
| 496 | #address-cells = <1>; |
| 497 | #size-cells = <0>; |
| 498 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; |
| 499 | reg = <0 0xe6510000 0 0x425>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 500 | interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; |
Wolfram Sang | 05f3991 | 2014-03-25 19:56:29 +0100 | [diff] [blame] | 501 | clocks = <&mstp3_clks R8A7790_CLK_IIC1>; |
Wolfram Sang | 0d73ca4 | 2014-11-07 11:11:43 +0100 | [diff] [blame] | 502 | dmas = <&dmac0 0x65>, <&dmac0 0x66>; |
| 503 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 504 | power-domains = <&cpg_clocks>; |
Wolfram Sang | 05f3991 | 2014-03-25 19:56:29 +0100 | [diff] [blame] | 505 | status = "disabled"; |
| 506 | }; |
| 507 | |
| 508 | iic2: i2c@e6520000 { |
| 509 | #address-cells = <1>; |
| 510 | #size-cells = <0>; |
| 511 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; |
| 512 | reg = <0 0xe6520000 0 0x425>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 513 | interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; |
Wolfram Sang | 05f3991 | 2014-03-25 19:56:29 +0100 | [diff] [blame] | 514 | clocks = <&mstp3_clks R8A7790_CLK_IIC2>; |
Wolfram Sang | 0d73ca4 | 2014-11-07 11:11:43 +0100 | [diff] [blame] | 515 | dmas = <&dmac0 0x69>, <&dmac0 0x6a>; |
| 516 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 517 | power-domains = <&cpg_clocks>; |
Wolfram Sang | 05f3991 | 2014-03-25 19:56:29 +0100 | [diff] [blame] | 518 | status = "disabled"; |
| 519 | }; |
| 520 | |
| 521 | iic3: i2c@e60b0000 { |
| 522 | #address-cells = <1>; |
| 523 | #size-cells = <0>; |
| 524 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; |
| 525 | reg = <0 0xe60b0000 0 0x425>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 526 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
Wolfram Sang | 05f3991 | 2014-03-25 19:56:29 +0100 | [diff] [blame] | 527 | clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; |
Wolfram Sang | 0d73ca4 | 2014-11-07 11:11:43 +0100 | [diff] [blame] | 528 | dmas = <&dmac0 0x77>, <&dmac0 0x78>; |
| 529 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 530 | power-domains = <&cpg_clocks>; |
Wolfram Sang | 05f3991 | 2014-03-25 19:56:29 +0100 | [diff] [blame] | 531 | status = "disabled"; |
| 532 | }; |
| 533 | |
Laurent Pinchart | 22c2b78 | 2014-10-26 19:40:11 +0200 | [diff] [blame] | 534 | mmcif0: mmc@ee200000 { |
Magnus Damm | 063e8560 | 2013-11-20 09:05:53 +0900 | [diff] [blame] | 535 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 536 | reg = <0 0xee200000 0 0x80>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 537 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 538 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; |
Laurent Pinchart | 108216c | 2014-10-26 19:40:13 +0200 | [diff] [blame] | 539 | dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; |
| 540 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 541 | power-domains = <&cpg_clocks>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 542 | reg-io-width = <4>; |
| 543 | status = "disabled"; |
Kuninori Morimoto | 9637005 | 2015-05-14 07:23:04 +0000 | [diff] [blame] | 544 | max-frequency = <97500000>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 545 | }; |
| 546 | |
Kuninori Morimoto | b718aa4 | 2013-10-21 19:36:13 -0700 | [diff] [blame] | 547 | mmcif1: mmc@ee220000 { |
Magnus Damm | 063e8560 | 2013-11-20 09:05:53 +0900 | [diff] [blame] | 548 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 549 | reg = <0 0xee220000 0 0x80>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 550 | interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 551 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; |
Laurent Pinchart | 108216c | 2014-10-26 19:40:13 +0200 | [diff] [blame] | 552 | dmas = <&dmac0 0xe1>, <&dmac0 0xe2>; |
| 553 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 554 | power-domains = <&cpg_clocks>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 555 | reg-io-width = <4>; |
| 556 | status = "disabled"; |
Kuninori Morimoto | 9637005 | 2015-05-14 07:23:04 +0000 | [diff] [blame] | 557 | max-frequency = <97500000>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 558 | }; |
| 559 | |
Laurent Pinchart | 9694c77 | 2013-05-09 15:05:57 +0200 | [diff] [blame] | 560 | pfc: pfc@e6060000 { |
| 561 | compatible = "renesas,pfc-r8a7790"; |
| 562 | reg = <0 0xe6060000 0 0x250>; |
| 563 | }; |
Olof Johansson | 55689bf | 2013-08-14 00:24:05 -0700 | [diff] [blame] | 564 | |
Kuninori Morimoto | b718aa4 | 2013-10-21 19:36:13 -0700 | [diff] [blame] | 565 | sdhi0: sd@ee100000 { |
Guennadi Liakhovetski | df1d058 | 2013-08-29 17:14:49 +0200 | [diff] [blame] | 566 | compatible = "renesas,sdhi-r8a7790"; |
Kuninori Morimoto | 66f47ed | 2015-02-24 02:20:37 +0000 | [diff] [blame] | 567 | reg = <0 0xee100000 0 0x328>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 568 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 569 | clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; |
Laurent Pinchart | 941fe36 | 2015-02-24 02:20:03 +0000 | [diff] [blame] | 570 | dmas = <&dmac1 0xcd>, <&dmac1 0xce>; |
| 571 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 572 | power-domains = <&cpg_clocks>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 573 | status = "disabled"; |
| 574 | }; |
| 575 | |
Kuninori Morimoto | b718aa4 | 2013-10-21 19:36:13 -0700 | [diff] [blame] | 576 | sdhi1: sd@ee120000 { |
Guennadi Liakhovetski | df1d058 | 2013-08-29 17:14:49 +0200 | [diff] [blame] | 577 | compatible = "renesas,sdhi-r8a7790"; |
Kuninori Morimoto | 66f47ed | 2015-02-24 02:20:37 +0000 | [diff] [blame] | 578 | reg = <0 0xee120000 0 0x328>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 579 | interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 580 | clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; |
Laurent Pinchart | 941fe36 | 2015-02-24 02:20:03 +0000 | [diff] [blame] | 581 | dmas = <&dmac1 0xc9>, <&dmac1 0xca>; |
| 582 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 583 | power-domains = <&cpg_clocks>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 584 | status = "disabled"; |
| 585 | }; |
| 586 | |
Kuninori Morimoto | b718aa4 | 2013-10-21 19:36:13 -0700 | [diff] [blame] | 587 | sdhi2: sd@ee140000 { |
Guennadi Liakhovetski | df1d058 | 2013-08-29 17:14:49 +0200 | [diff] [blame] | 588 | compatible = "renesas,sdhi-r8a7790"; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 589 | reg = <0 0xee140000 0 0x100>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 590 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 591 | clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; |
Laurent Pinchart | 941fe36 | 2015-02-24 02:20:03 +0000 | [diff] [blame] | 592 | dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; |
| 593 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 594 | power-domains = <&cpg_clocks>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 595 | status = "disabled"; |
| 596 | }; |
| 597 | |
Kuninori Morimoto | b718aa4 | 2013-10-21 19:36:13 -0700 | [diff] [blame] | 598 | sdhi3: sd@ee160000 { |
Guennadi Liakhovetski | df1d058 | 2013-08-29 17:14:49 +0200 | [diff] [blame] | 599 | compatible = "renesas,sdhi-r8a7790"; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 600 | reg = <0 0xee160000 0 0x100>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 601 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 602 | clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; |
Laurent Pinchart | 941fe36 | 2015-02-24 02:20:03 +0000 | [diff] [blame] | 603 | dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; |
| 604 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 605 | power-domains = <&cpg_clocks>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 606 | status = "disabled"; |
| 607 | }; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 608 | |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 609 | scifa0: serial@e6c40000 { |
Geert Uytterhoeven | a20dc9f | 2016-01-29 10:32:04 +0100 | [diff] [blame] | 610 | compatible = "renesas,scifa-r8a7790", |
| 611 | "renesas,rcar-gen2-scifa", "renesas,scifa"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 612 | reg = <0 0xe6c40000 0 64>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 613 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 614 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; |
Laurent Pinchart | 6c6e12a | 2016-01-29 10:47:37 +0100 | [diff] [blame] | 615 | clock-names = "fck"; |
Geert Uytterhoeven | acea43f | 2015-05-20 19:46:25 +0200 | [diff] [blame] | 616 | dmas = <&dmac0 0x21>, <&dmac0 0x22>; |
| 617 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 618 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 619 | status = "disabled"; |
| 620 | }; |
| 621 | |
| 622 | scifa1: serial@e6c50000 { |
Geert Uytterhoeven | a20dc9f | 2016-01-29 10:32:04 +0100 | [diff] [blame] | 623 | compatible = "renesas,scifa-r8a7790", |
| 624 | "renesas,rcar-gen2-scifa", "renesas,scifa"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 625 | reg = <0 0xe6c50000 0 64>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 626 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 627 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; |
Laurent Pinchart | 6c6e12a | 2016-01-29 10:47:37 +0100 | [diff] [blame] | 628 | clock-names = "fck"; |
Geert Uytterhoeven | acea43f | 2015-05-20 19:46:25 +0200 | [diff] [blame] | 629 | dmas = <&dmac0 0x25>, <&dmac0 0x26>; |
| 630 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 631 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 632 | status = "disabled"; |
| 633 | }; |
| 634 | |
| 635 | scifa2: serial@e6c60000 { |
Geert Uytterhoeven | a20dc9f | 2016-01-29 10:32:04 +0100 | [diff] [blame] | 636 | compatible = "renesas,scifa-r8a7790", |
| 637 | "renesas,rcar-gen2-scifa", "renesas,scifa"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 638 | reg = <0 0xe6c60000 0 64>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 639 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 640 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; |
Laurent Pinchart | 6c6e12a | 2016-01-29 10:47:37 +0100 | [diff] [blame] | 641 | clock-names = "fck"; |
Geert Uytterhoeven | acea43f | 2015-05-20 19:46:25 +0200 | [diff] [blame] | 642 | dmas = <&dmac0 0x27>, <&dmac0 0x28>; |
| 643 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 644 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 645 | status = "disabled"; |
| 646 | }; |
| 647 | |
| 648 | scifb0: serial@e6c20000 { |
Geert Uytterhoeven | a20dc9f | 2016-01-29 10:32:04 +0100 | [diff] [blame] | 649 | compatible = "renesas,scifb-r8a7790", |
| 650 | "renesas,rcar-gen2-scifb", "renesas,scifb"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 651 | reg = <0 0xe6c20000 0 64>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 652 | interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 653 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; |
Laurent Pinchart | 6c6e12a | 2016-01-29 10:47:37 +0100 | [diff] [blame] | 654 | clock-names = "fck"; |
Geert Uytterhoeven | acea43f | 2015-05-20 19:46:25 +0200 | [diff] [blame] | 655 | dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; |
| 656 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 657 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 658 | status = "disabled"; |
| 659 | }; |
| 660 | |
| 661 | scifb1: serial@e6c30000 { |
Geert Uytterhoeven | a20dc9f | 2016-01-29 10:32:04 +0100 | [diff] [blame] | 662 | compatible = "renesas,scifb-r8a7790", |
| 663 | "renesas,rcar-gen2-scifb", "renesas,scifb"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 664 | reg = <0 0xe6c30000 0 64>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 665 | interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 666 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; |
Laurent Pinchart | 6c6e12a | 2016-01-29 10:47:37 +0100 | [diff] [blame] | 667 | clock-names = "fck"; |
Geert Uytterhoeven | acea43f | 2015-05-20 19:46:25 +0200 | [diff] [blame] | 668 | dmas = <&dmac0 0x19>, <&dmac0 0x1a>; |
| 669 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 670 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 671 | status = "disabled"; |
| 672 | }; |
| 673 | |
| 674 | scifb2: serial@e6ce0000 { |
Geert Uytterhoeven | a20dc9f | 2016-01-29 10:32:04 +0100 | [diff] [blame] | 675 | compatible = "renesas,scifb-r8a7790", |
| 676 | "renesas,rcar-gen2-scifb", "renesas,scifb"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 677 | reg = <0 0xe6ce0000 0 64>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 678 | interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 679 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; |
Laurent Pinchart | 6c6e12a | 2016-01-29 10:47:37 +0100 | [diff] [blame] | 680 | clock-names = "fck"; |
Geert Uytterhoeven | acea43f | 2015-05-20 19:46:25 +0200 | [diff] [blame] | 681 | dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; |
| 682 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 683 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 684 | status = "disabled"; |
| 685 | }; |
| 686 | |
| 687 | scif0: serial@e6e60000 { |
Geert Uytterhoeven | a20dc9f | 2016-01-29 10:32:04 +0100 | [diff] [blame] | 688 | compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif", |
| 689 | "renesas,scif"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 690 | reg = <0 0xe6e60000 0 64>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 691 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 42af65e | 2016-01-29 11:04:39 +0100 | [diff] [blame] | 692 | clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>, |
| 693 | <&scif_clk>; |
| 694 | clock-names = "fck", "brg_int", "scif_clk"; |
Geert Uytterhoeven | acea43f | 2015-05-20 19:46:25 +0200 | [diff] [blame] | 695 | dmas = <&dmac0 0x29>, <&dmac0 0x2a>; |
| 696 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 697 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 698 | status = "disabled"; |
| 699 | }; |
| 700 | |
| 701 | scif1: serial@e6e68000 { |
Geert Uytterhoeven | a20dc9f | 2016-01-29 10:32:04 +0100 | [diff] [blame] | 702 | compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif", |
| 703 | "renesas,scif"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 704 | reg = <0 0xe6e68000 0 64>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 705 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 42af65e | 2016-01-29 11:04:39 +0100 | [diff] [blame] | 706 | clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>, |
| 707 | <&scif_clk>; |
| 708 | clock-names = "fck", "brg_int", "scif_clk"; |
Geert Uytterhoeven | acea43f | 2015-05-20 19:46:25 +0200 | [diff] [blame] | 709 | dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; |
| 710 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 711 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 712 | status = "disabled"; |
| 713 | }; |
| 714 | |
| 715 | hscif0: serial@e62c0000 { |
Geert Uytterhoeven | a20dc9f | 2016-01-29 10:32:04 +0100 | [diff] [blame] | 716 | compatible = "renesas,hscif-r8a7790", |
| 717 | "renesas,rcar-gen2-hscif", "renesas,hscif"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 718 | reg = <0 0xe62c0000 0 96>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 719 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 42af65e | 2016-01-29 11:04:39 +0100 | [diff] [blame] | 720 | clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>, |
| 721 | <&scif_clk>; |
| 722 | clock-names = "fck", "brg_int", "scif_clk"; |
Geert Uytterhoeven | acea43f | 2015-05-20 19:46:25 +0200 | [diff] [blame] | 723 | dmas = <&dmac0 0x39>, <&dmac0 0x3a>; |
| 724 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 725 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 726 | status = "disabled"; |
| 727 | }; |
| 728 | |
| 729 | hscif1: serial@e62c8000 { |
Geert Uytterhoeven | a20dc9f | 2016-01-29 10:32:04 +0100 | [diff] [blame] | 730 | compatible = "renesas,hscif-r8a7790", |
| 731 | "renesas,rcar-gen2-hscif", "renesas,hscif"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 732 | reg = <0 0xe62c8000 0 96>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 733 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 42af65e | 2016-01-29 11:04:39 +0100 | [diff] [blame] | 734 | clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>, |
| 735 | <&scif_clk>; |
| 736 | clock-names = "fck", "brg_int", "scif_clk"; |
Geert Uytterhoeven | acea43f | 2015-05-20 19:46:25 +0200 | [diff] [blame] | 737 | dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; |
| 738 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 739 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 740 | status = "disabled"; |
| 741 | }; |
| 742 | |
Sergei Shtylyov | d8913c6 | 2014-02-20 02:20:43 +0300 | [diff] [blame] | 743 | ether: ethernet@ee700000 { |
| 744 | compatible = "renesas,ether-r8a7790"; |
| 745 | reg = <0 0xee700000 0 0x400>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 746 | interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | d8913c6 | 2014-02-20 02:20:43 +0300 | [diff] [blame] | 747 | clocks = <&mstp8_clks R8A7790_CLK_ETHER>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 748 | power-domains = <&cpg_clocks>; |
Sergei Shtylyov | d8913c6 | 2014-02-20 02:20:43 +0300 | [diff] [blame] | 749 | phy-mode = "rmii"; |
| 750 | #address-cells = <1>; |
| 751 | #size-cells = <0>; |
| 752 | status = "disabled"; |
| 753 | }; |
| 754 | |
Sergei Shtylyov | f25d6b9 | 2015-06-16 02:43:51 +0300 | [diff] [blame] | 755 | avb: ethernet@e6800000 { |
| 756 | compatible = "renesas,etheravb-r8a7790"; |
| 757 | reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 758 | interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | f25d6b9 | 2015-06-16 02:43:51 +0300 | [diff] [blame] | 759 | clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 760 | power-domains = <&cpg_clocks>; |
Sergei Shtylyov | f25d6b9 | 2015-06-16 02:43:51 +0300 | [diff] [blame] | 761 | #address-cells = <1>; |
| 762 | #size-cells = <0>; |
| 763 | status = "disabled"; |
| 764 | }; |
| 765 | |
Valentine Barshak | cde630f | 2014-01-14 21:05:30 +0400 | [diff] [blame] | 766 | sata0: sata@ee300000 { |
| 767 | compatible = "renesas,sata-r8a7790"; |
| 768 | reg = <0 0xee300000 0 0x2000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 769 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
Valentine Barshak | cde630f | 2014-01-14 21:05:30 +0400 | [diff] [blame] | 770 | clocks = <&mstp8_clks R8A7790_CLK_SATA0>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 771 | power-domains = <&cpg_clocks>; |
Valentine Barshak | cde630f | 2014-01-14 21:05:30 +0400 | [diff] [blame] | 772 | status = "disabled"; |
| 773 | }; |
| 774 | |
| 775 | sata1: sata@ee500000 { |
| 776 | compatible = "renesas,sata-r8a7790"; |
| 777 | reg = <0 0xee500000 0 0x2000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 778 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
Valentine Barshak | cde630f | 2014-01-14 21:05:30 +0400 | [diff] [blame] | 779 | clocks = <&mstp8_clks R8A7790_CLK_SATA1>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 780 | power-domains = <&cpg_clocks>; |
Valentine Barshak | cde630f | 2014-01-14 21:05:30 +0400 | [diff] [blame] | 781 | status = "disabled"; |
| 782 | }; |
| 783 | |
Yoshihiro Shimoda | ae0a555 | 2014-10-24 19:44:33 +0900 | [diff] [blame] | 784 | hsusb: usb@e6590000 { |
Simon Horman | d87ec94 | 2016-01-04 08:20:17 +1100 | [diff] [blame] | 785 | compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs"; |
Yoshihiro Shimoda | ae0a555 | 2014-10-24 19:44:33 +0900 | [diff] [blame] | 786 | reg = <0 0xe6590000 0 0x100>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 787 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
Yoshihiro Shimoda | ae0a555 | 2014-10-24 19:44:33 +0900 | [diff] [blame] | 788 | clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; |
Yoshihiro Shimoda | e8295dc | 2015-05-08 16:13:07 +0900 | [diff] [blame] | 789 | dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, |
| 790 | <&usb_dmac1 0>, <&usb_dmac1 1>; |
| 791 | dma-names = "ch0", "ch1", "ch2", "ch3"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 792 | power-domains = <&cpg_clocks>; |
| 793 | renesas,buswait = <4>; |
| 794 | phys = <&usb0 1>; |
| 795 | phy-names = "usb"; |
Yoshihiro Shimoda | ae0a555 | 2014-10-24 19:44:33 +0900 | [diff] [blame] | 796 | status = "disabled"; |
| 797 | }; |
| 798 | |
Sergei Shtylyov | e089f65 | 2014-09-27 01:00:20 +0400 | [diff] [blame] | 799 | usbphy: usb-phy@e6590100 { |
| 800 | compatible = "renesas,usb-phy-r8a7790"; |
| 801 | reg = <0 0xe6590100 0 0x100>; |
| 802 | #address-cells = <1>; |
| 803 | #size-cells = <0>; |
| 804 | clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; |
| 805 | clock-names = "usbhs"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 806 | power-domains = <&cpg_clocks>; |
Sergei Shtylyov | e089f65 | 2014-09-27 01:00:20 +0400 | [diff] [blame] | 807 | status = "disabled"; |
| 808 | |
| 809 | usb0: usb-channel@0 { |
| 810 | reg = <0>; |
| 811 | #phy-cells = <1>; |
| 812 | }; |
| 813 | usb2: usb-channel@2 { |
| 814 | reg = <2>; |
| 815 | #phy-cells = <1>; |
| 816 | }; |
| 817 | }; |
| 818 | |
Ben Dooks | 9f685bf | 2014-08-13 00:16:18 +0400 | [diff] [blame] | 819 | vin0: video@e6ef0000 { |
| 820 | compatible = "renesas,vin-r8a7790"; |
Ben Dooks | 9f685bf | 2014-08-13 00:16:18 +0400 | [diff] [blame] | 821 | reg = <0 0xe6ef0000 0 0x1000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 822 | interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 823 | clocks = <&mstp8_clks R8A7790_CLK_VIN0>; |
| 824 | power-domains = <&cpg_clocks>; |
Ben Dooks | 9f685bf | 2014-08-13 00:16:18 +0400 | [diff] [blame] | 825 | status = "disabled"; |
| 826 | }; |
| 827 | |
| 828 | vin1: video@e6ef1000 { |
| 829 | compatible = "renesas,vin-r8a7790"; |
Ben Dooks | 9f685bf | 2014-08-13 00:16:18 +0400 | [diff] [blame] | 830 | reg = <0 0xe6ef1000 0 0x1000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 831 | interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 832 | clocks = <&mstp8_clks R8A7790_CLK_VIN1>; |
| 833 | power-domains = <&cpg_clocks>; |
Ben Dooks | 9f685bf | 2014-08-13 00:16:18 +0400 | [diff] [blame] | 834 | status = "disabled"; |
| 835 | }; |
| 836 | |
| 837 | vin2: video@e6ef2000 { |
| 838 | compatible = "renesas,vin-r8a7790"; |
Ben Dooks | 9f685bf | 2014-08-13 00:16:18 +0400 | [diff] [blame] | 839 | reg = <0 0xe6ef2000 0 0x1000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 840 | interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 841 | clocks = <&mstp8_clks R8A7790_CLK_VIN2>; |
| 842 | power-domains = <&cpg_clocks>; |
Ben Dooks | 9f685bf | 2014-08-13 00:16:18 +0400 | [diff] [blame] | 843 | status = "disabled"; |
| 844 | }; |
| 845 | |
| 846 | vin3: video@e6ef3000 { |
| 847 | compatible = "renesas,vin-r8a7790"; |
Ben Dooks | 9f685bf | 2014-08-13 00:16:18 +0400 | [diff] [blame] | 848 | reg = <0 0xe6ef3000 0 0x1000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 849 | interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 850 | clocks = <&mstp8_clks R8A7790_CLK_VIN3>; |
| 851 | power-domains = <&cpg_clocks>; |
Ben Dooks | 9f685bf | 2014-08-13 00:16:18 +0400 | [diff] [blame] | 852 | status = "disabled"; |
| 853 | }; |
| 854 | |
Laurent Pinchart | 3ac6a83 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 855 | vsp1@fe920000 { |
| 856 | compatible = "renesas,vsp1"; |
| 857 | reg = <0 0xfe920000 0 0x8000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 858 | interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 3ac6a83 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 859 | clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 860 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 3ac6a83 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 861 | |
| 862 | renesas,has-sru; |
| 863 | renesas,#rpf = <5>; |
| 864 | renesas,#uds = <1>; |
| 865 | renesas,#wpf = <4>; |
| 866 | }; |
| 867 | |
| 868 | vsp1@fe928000 { |
| 869 | compatible = "renesas,vsp1"; |
| 870 | reg = <0 0xfe928000 0 0x8000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 871 | interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 3ac6a83 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 872 | clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 873 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 3ac6a83 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 874 | |
| 875 | renesas,has-lut; |
| 876 | renesas,has-sru; |
| 877 | renesas,#rpf = <5>; |
| 878 | renesas,#uds = <3>; |
| 879 | renesas,#wpf = <4>; |
| 880 | }; |
| 881 | |
| 882 | vsp1@fe930000 { |
| 883 | compatible = "renesas,vsp1"; |
| 884 | reg = <0 0xfe930000 0 0x8000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 885 | interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 3ac6a83 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 886 | clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 887 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 3ac6a83 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 888 | |
| 889 | renesas,has-lif; |
| 890 | renesas,has-lut; |
| 891 | renesas,#rpf = <4>; |
| 892 | renesas,#uds = <1>; |
| 893 | renesas,#wpf = <4>; |
| 894 | }; |
| 895 | |
| 896 | vsp1@fe938000 { |
| 897 | compatible = "renesas,vsp1"; |
| 898 | reg = <0 0xfe938000 0 0x8000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 899 | interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 3ac6a83 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 900 | clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 901 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 3ac6a83 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 902 | |
| 903 | renesas,has-lif; |
| 904 | renesas,has-lut; |
| 905 | renesas,#rpf = <4>; |
| 906 | renesas,#uds = <1>; |
| 907 | renesas,#wpf = <4>; |
| 908 | }; |
| 909 | |
| 910 | du: display@feb00000 { |
| 911 | compatible = "renesas,du-r8a7790"; |
| 912 | reg = <0 0xfeb00000 0 0x70000>, |
| 913 | <0 0xfeb90000 0 0x1c>, |
| 914 | <0 0xfeb94000 0 0x1c>; |
| 915 | reg-names = "du", "lvds.0", "lvds.1"; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 916 | interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
| 917 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, |
| 918 | <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 3ac6a83 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 919 | clocks = <&mstp7_clks R8A7790_CLK_DU0>, |
| 920 | <&mstp7_clks R8A7790_CLK_DU1>, |
| 921 | <&mstp7_clks R8A7790_CLK_DU2>, |
| 922 | <&mstp7_clks R8A7790_CLK_LVDS0>, |
| 923 | <&mstp7_clks R8A7790_CLK_LVDS1>; |
| 924 | clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1"; |
| 925 | status = "disabled"; |
| 926 | |
| 927 | ports { |
| 928 | #address-cells = <1>; |
| 929 | #size-cells = <0>; |
| 930 | |
| 931 | port@0 { |
| 932 | reg = <0>; |
| 933 | du_out_rgb: endpoint { |
| 934 | }; |
| 935 | }; |
| 936 | port@1 { |
| 937 | reg = <1>; |
| 938 | du_out_lvds0: endpoint { |
| 939 | }; |
| 940 | }; |
| 941 | port@2 { |
| 942 | reg = <2>; |
| 943 | du_out_lvds1: endpoint { |
| 944 | }; |
| 945 | }; |
| 946 | }; |
| 947 | }; |
| 948 | |
Sergei Shtylyov | 6a7742b | 2015-01-06 00:34:42 +0300 | [diff] [blame] | 949 | can0: can@e6e80000 { |
| 950 | compatible = "renesas,can-r8a7790"; |
| 951 | reg = <0 0xe6e80000 0 0x1000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 952 | interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 6a7742b | 2015-01-06 00:34:42 +0300 | [diff] [blame] | 953 | clocks = <&mstp9_clks R8A7790_CLK_RCAN0>, |
| 954 | <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; |
| 955 | clock-names = "clkp1", "clkp2", "can_clk"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 956 | power-domains = <&cpg_clocks>; |
Sergei Shtylyov | 6a7742b | 2015-01-06 00:34:42 +0300 | [diff] [blame] | 957 | status = "disabled"; |
| 958 | }; |
| 959 | |
| 960 | can1: can@e6e88000 { |
| 961 | compatible = "renesas,can-r8a7790"; |
| 962 | reg = <0 0xe6e88000 0 0x1000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 963 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 6a7742b | 2015-01-06 00:34:42 +0300 | [diff] [blame] | 964 | clocks = <&mstp9_clks R8A7790_CLK_RCAN1>, |
| 965 | <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; |
| 966 | clock-names = "clkp1", "clkp2", "can_clk"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 967 | power-domains = <&cpg_clocks>; |
Sergei Shtylyov | 6a7742b | 2015-01-06 00:34:42 +0300 | [diff] [blame] | 968 | status = "disabled"; |
| 969 | }; |
| 970 | |
Mikhail Ulyanov | fb84757 | 2015-07-24 16:25:45 +0300 | [diff] [blame] | 971 | jpu: jpeg-codec@fe980000 { |
| 972 | compatible = "renesas,jpu-r8a7790"; |
| 973 | reg = <0 0xfe980000 0 0x10300>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 974 | interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; |
Mikhail Ulyanov | fb84757 | 2015-07-24 16:25:45 +0300 | [diff] [blame] | 975 | clocks = <&mstp1_clks R8A7790_CLK_JPU>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 976 | power-domains = <&cpg_clocks>; |
Mikhail Ulyanov | fb84757 | 2015-07-24 16:25:45 +0300 | [diff] [blame] | 977 | }; |
| 978 | |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 979 | clocks { |
| 980 | #address-cells = <2>; |
| 981 | #size-cells = <2>; |
| 982 | ranges; |
| 983 | |
| 984 | /* External root clock */ |
| 985 | extal_clk: extal_clk { |
| 986 | compatible = "fixed-clock"; |
| 987 | #clock-cells = <0>; |
| 988 | /* This value must be overriden by the board. */ |
| 989 | clock-frequency = <0>; |
| 990 | clock-output-names = "extal"; |
| 991 | }; |
| 992 | |
Phil Edworthy | 51d1791 | 2014-06-13 10:37:16 +0100 | [diff] [blame] | 993 | /* External PCIe clock - can be overridden by the board */ |
| 994 | pcie_bus_clk: pcie_bus_clk { |
| 995 | compatible = "fixed-clock"; |
| 996 | #clock-cells = <0>; |
| 997 | clock-frequency = <100000000>; |
| 998 | clock-output-names = "pcie_bus"; |
| 999 | status = "disabled"; |
| 1000 | }; |
| 1001 | |
Kuninori Morimoto | c7c2ec3 | 2014-01-13 18:25:39 -0800 | [diff] [blame] | 1002 | /* |
| 1003 | * The external audio clocks are configured as 0 Hz fixed frequency clocks by |
| 1004 | * default. Boards that provide audio clocks should override them. |
| 1005 | */ |
| 1006 | audio_clk_a: audio_clk_a { |
| 1007 | compatible = "fixed-clock"; |
| 1008 | #clock-cells = <0>; |
| 1009 | clock-frequency = <0>; |
| 1010 | clock-output-names = "audio_clk_a"; |
| 1011 | }; |
| 1012 | audio_clk_b: audio_clk_b { |
| 1013 | compatible = "fixed-clock"; |
| 1014 | #clock-cells = <0>; |
| 1015 | clock-frequency = <0>; |
| 1016 | clock-output-names = "audio_clk_b"; |
| 1017 | }; |
| 1018 | audio_clk_c: audio_clk_c { |
| 1019 | compatible = "fixed-clock"; |
| 1020 | #clock-cells = <0>; |
| 1021 | clock-frequency = <0>; |
| 1022 | clock-output-names = "audio_clk_c"; |
| 1023 | }; |
| 1024 | |
Geert Uytterhoeven | 42af65e | 2016-01-29 11:04:39 +0100 | [diff] [blame] | 1025 | /* External SCIF clock */ |
| 1026 | scif_clk: scif { |
| 1027 | compatible = "fixed-clock"; |
| 1028 | #clock-cells = <0>; |
| 1029 | /* This value must be overridden by the board. */ |
| 1030 | clock-frequency = <0>; |
| 1031 | status = "disabled"; |
| 1032 | }; |
| 1033 | |
Sergei Shtylyov | 41650f4 | 2015-01-06 00:33:25 +0300 | [diff] [blame] | 1034 | /* External USB clock - can be overridden by the board */ |
| 1035 | usb_extal_clk: usb_extal_clk { |
| 1036 | compatible = "fixed-clock"; |
| 1037 | #clock-cells = <0>; |
| 1038 | clock-frequency = <48000000>; |
| 1039 | clock-output-names = "usb_extal"; |
| 1040 | }; |
| 1041 | |
| 1042 | /* External CAN clock */ |
| 1043 | can_clk: can_clk { |
| 1044 | compatible = "fixed-clock"; |
| 1045 | #clock-cells = <0>; |
| 1046 | /* This value must be overridden by the board. */ |
| 1047 | clock-frequency = <0>; |
| 1048 | clock-output-names = "can_clk"; |
| 1049 | status = "disabled"; |
| 1050 | }; |
| 1051 | |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1052 | /* Special CPG clocks */ |
| 1053 | cpg_clocks: cpg_clocks@e6150000 { |
| 1054 | compatible = "renesas,r8a7790-cpg-clocks", |
| 1055 | "renesas,rcar-gen2-cpg-clocks"; |
| 1056 | reg = <0 0xe6150000 0 0x1000>; |
Sergei Shtylyov | 41650f4 | 2015-01-06 00:33:25 +0300 | [diff] [blame] | 1057 | clocks = <&extal_clk &usb_extal_clk>; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1058 | #clock-cells = <1>; |
| 1059 | clock-output-names = "main", "pll0", "pll1", "pll3", |
| 1060 | "lb", "qspi", "sdh", "sd0", "sd1", |
Sergei Shtylyov | 3453ca9 | 2014-12-30 23:21:45 +0300 | [diff] [blame] | 1061 | "z", "rcan", "adsp"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 1062 | #power-domain-cells = <0>; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1063 | }; |
| 1064 | |
| 1065 | /* Variable factor clocks */ |
| 1066 | sd2_clk: sd2_clk@e6150078 { |
| 1067 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| 1068 | reg = <0 0xe6150078 0 4>; |
| 1069 | clocks = <&pll1_div2_clk>; |
| 1070 | #clock-cells = <0>; |
| 1071 | clock-output-names = "sd2"; |
| 1072 | }; |
Shinobu Uehara | edd7b93 | 2014-10-30 14:57:57 +0900 | [diff] [blame] | 1073 | sd3_clk: sd3_clk@e615026c { |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1074 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
Shinobu Uehara | edd7b93 | 2014-10-30 14:57:57 +0900 | [diff] [blame] | 1075 | reg = <0 0xe615026c 0 4>; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1076 | clocks = <&pll1_div2_clk>; |
| 1077 | #clock-cells = <0>; |
| 1078 | clock-output-names = "sd3"; |
| 1079 | }; |
| 1080 | mmc0_clk: mmc0_clk@e6150240 { |
| 1081 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| 1082 | reg = <0 0xe6150240 0 4>; |
| 1083 | clocks = <&pll1_div2_clk>; |
| 1084 | #clock-cells = <0>; |
| 1085 | clock-output-names = "mmc0"; |
| 1086 | }; |
| 1087 | mmc1_clk: mmc1_clk@e6150244 { |
| 1088 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| 1089 | reg = <0 0xe6150244 0 4>; |
| 1090 | clocks = <&pll1_div2_clk>; |
| 1091 | #clock-cells = <0>; |
| 1092 | clock-output-names = "mmc1"; |
| 1093 | }; |
| 1094 | ssp_clk: ssp_clk@e6150248 { |
| 1095 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| 1096 | reg = <0 0xe6150248 0 4>; |
| 1097 | clocks = <&pll1_div2_clk>; |
| 1098 | #clock-cells = <0>; |
| 1099 | clock-output-names = "ssp"; |
| 1100 | }; |
| 1101 | ssprs_clk: ssprs_clk@e615024c { |
| 1102 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| 1103 | reg = <0 0xe615024c 0 4>; |
| 1104 | clocks = <&pll1_div2_clk>; |
| 1105 | #clock-cells = <0>; |
| 1106 | clock-output-names = "ssprs"; |
| 1107 | }; |
| 1108 | |
| 1109 | /* Fixed factor clocks */ |
| 1110 | pll1_div2_clk: pll1_div2_clk { |
| 1111 | compatible = "fixed-factor-clock"; |
| 1112 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 1113 | #clock-cells = <0>; |
| 1114 | clock-div = <2>; |
| 1115 | clock-mult = <1>; |
| 1116 | clock-output-names = "pll1_div2"; |
| 1117 | }; |
| 1118 | z2_clk: z2_clk { |
| 1119 | compatible = "fixed-factor-clock"; |
| 1120 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 1121 | #clock-cells = <0>; |
| 1122 | clock-div = <2>; |
| 1123 | clock-mult = <1>; |
| 1124 | clock-output-names = "z2"; |
| 1125 | }; |
| 1126 | zg_clk: zg_clk { |
| 1127 | compatible = "fixed-factor-clock"; |
| 1128 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 1129 | #clock-cells = <0>; |
| 1130 | clock-div = <3>; |
| 1131 | clock-mult = <1>; |
| 1132 | clock-output-names = "zg"; |
| 1133 | }; |
| 1134 | zx_clk: zx_clk { |
| 1135 | compatible = "fixed-factor-clock"; |
| 1136 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 1137 | #clock-cells = <0>; |
| 1138 | clock-div = <3>; |
| 1139 | clock-mult = <1>; |
| 1140 | clock-output-names = "zx"; |
| 1141 | }; |
| 1142 | zs_clk: zs_clk { |
| 1143 | compatible = "fixed-factor-clock"; |
| 1144 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 1145 | #clock-cells = <0>; |
| 1146 | clock-div = <6>; |
| 1147 | clock-mult = <1>; |
| 1148 | clock-output-names = "zs"; |
| 1149 | }; |
| 1150 | hp_clk: hp_clk { |
| 1151 | compatible = "fixed-factor-clock"; |
| 1152 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 1153 | #clock-cells = <0>; |
| 1154 | clock-div = <12>; |
| 1155 | clock-mult = <1>; |
| 1156 | clock-output-names = "hp"; |
| 1157 | }; |
| 1158 | i_clk: i_clk { |
| 1159 | compatible = "fixed-factor-clock"; |
| 1160 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 1161 | #clock-cells = <0>; |
| 1162 | clock-div = <2>; |
| 1163 | clock-mult = <1>; |
| 1164 | clock-output-names = "i"; |
| 1165 | }; |
| 1166 | b_clk: b_clk { |
| 1167 | compatible = "fixed-factor-clock"; |
| 1168 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 1169 | #clock-cells = <0>; |
| 1170 | clock-div = <12>; |
| 1171 | clock-mult = <1>; |
| 1172 | clock-output-names = "b"; |
| 1173 | }; |
| 1174 | p_clk: p_clk { |
| 1175 | compatible = "fixed-factor-clock"; |
| 1176 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 1177 | #clock-cells = <0>; |
| 1178 | clock-div = <24>; |
| 1179 | clock-mult = <1>; |
| 1180 | clock-output-names = "p"; |
| 1181 | }; |
| 1182 | cl_clk: cl_clk { |
| 1183 | compatible = "fixed-factor-clock"; |
| 1184 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 1185 | #clock-cells = <0>; |
| 1186 | clock-div = <48>; |
| 1187 | clock-mult = <1>; |
| 1188 | clock-output-names = "cl"; |
| 1189 | }; |
| 1190 | m2_clk: m2_clk { |
| 1191 | compatible = "fixed-factor-clock"; |
| 1192 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 1193 | #clock-cells = <0>; |
| 1194 | clock-div = <8>; |
| 1195 | clock-mult = <1>; |
| 1196 | clock-output-names = "m2"; |
| 1197 | }; |
| 1198 | imp_clk: imp_clk { |
| 1199 | compatible = "fixed-factor-clock"; |
| 1200 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 1201 | #clock-cells = <0>; |
| 1202 | clock-div = <4>; |
| 1203 | clock-mult = <1>; |
| 1204 | clock-output-names = "imp"; |
| 1205 | }; |
| 1206 | rclk_clk: rclk_clk { |
| 1207 | compatible = "fixed-factor-clock"; |
| 1208 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 1209 | #clock-cells = <0>; |
| 1210 | clock-div = <(48 * 1024)>; |
| 1211 | clock-mult = <1>; |
| 1212 | clock-output-names = "rclk"; |
| 1213 | }; |
| 1214 | oscclk_clk: oscclk_clk { |
| 1215 | compatible = "fixed-factor-clock"; |
| 1216 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 1217 | #clock-cells = <0>; |
| 1218 | clock-div = <(12 * 1024)>; |
| 1219 | clock-mult = <1>; |
| 1220 | clock-output-names = "oscclk"; |
| 1221 | }; |
| 1222 | zb3_clk: zb3_clk { |
| 1223 | compatible = "fixed-factor-clock"; |
| 1224 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; |
| 1225 | #clock-cells = <0>; |
| 1226 | clock-div = <4>; |
| 1227 | clock-mult = <1>; |
| 1228 | clock-output-names = "zb3"; |
| 1229 | }; |
| 1230 | zb3d2_clk: zb3d2_clk { |
| 1231 | compatible = "fixed-factor-clock"; |
| 1232 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; |
| 1233 | #clock-cells = <0>; |
| 1234 | clock-div = <8>; |
| 1235 | clock-mult = <1>; |
| 1236 | clock-output-names = "zb3d2"; |
| 1237 | }; |
| 1238 | ddr_clk: ddr_clk { |
| 1239 | compatible = "fixed-factor-clock"; |
| 1240 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; |
| 1241 | #clock-cells = <0>; |
| 1242 | clock-div = <8>; |
| 1243 | clock-mult = <1>; |
| 1244 | clock-output-names = "ddr"; |
| 1245 | }; |
| 1246 | mp_clk: mp_clk { |
| 1247 | compatible = "fixed-factor-clock"; |
| 1248 | clocks = <&pll1_div2_clk>; |
| 1249 | #clock-cells = <0>; |
| 1250 | clock-div = <15>; |
| 1251 | clock-mult = <1>; |
| 1252 | clock-output-names = "mp"; |
| 1253 | }; |
| 1254 | cp_clk: cp_clk { |
| 1255 | compatible = "fixed-factor-clock"; |
| 1256 | clocks = <&extal_clk>; |
| 1257 | #clock-cells = <0>; |
| 1258 | clock-div = <2>; |
| 1259 | clock-mult = <1>; |
| 1260 | clock-output-names = "cp"; |
| 1261 | }; |
| 1262 | |
| 1263 | /* Gate clocks */ |
Laurent Pinchart | 9d90951 | 2013-12-19 16:51:01 +0100 | [diff] [blame] | 1264 | mstp0_clks: mstp0_clks@e6150130 { |
| 1265 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1266 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; |
| 1267 | clocks = <&mp_clk>; |
| 1268 | #clock-cells = <1>; |
Ben Dooks | b54010a | 2014-11-10 19:49:37 +0100 | [diff] [blame] | 1269 | clock-indices = <R8A7790_CLK_MSIOF0>; |
Laurent Pinchart | 9d90951 | 2013-12-19 16:51:01 +0100 | [diff] [blame] | 1270 | clock-output-names = "msiof0"; |
| 1271 | }; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1272 | mstp1_clks: mstp1_clks@e6150134 { |
| 1273 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1274 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; |
Yoshifumi Hosoya | 4ba8f24 | 2014-10-14 16:01:42 +0900 | [diff] [blame] | 1275 | clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>, |
| 1276 | <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>, |
| 1277 | <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, |
| 1278 | <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1279 | #clock-cells = <1>; |
Ben Dooks | b54010a | 2014-11-10 19:49:37 +0100 | [diff] [blame] | 1280 | clock-indices = < |
Yoshifumi Hosoya | 4ba8f24 | 2014-10-14 16:01:42 +0900 | [diff] [blame] | 1281 | R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1 |
| 1282 | R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1 |
| 1283 | R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC |
| 1284 | R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0 |
| 1285 | R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0 |
| 1286 | R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0 |
| 1287 | R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1288 | >; |
| 1289 | clock-output-names = |
Yoshifumi Hosoya | 4ba8f24 | 2014-10-14 16:01:42 +0900 | [diff] [blame] | 1290 | "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1", |
| 1291 | "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1", |
| 1292 | "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0", |
Kouei Abe | 2284ff5 | 2014-10-14 16:01:40 +0900 | [diff] [blame] | 1293 | "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy"; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1294 | }; |
| 1295 | mstp2_clks: mstp2_clks@e6150138 { |
| 1296 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1297 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; |
| 1298 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, |
Laurent Pinchart | c819acd | 2014-07-19 01:50:23 +0200 | [diff] [blame] | 1299 | <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>, |
| 1300 | <&zs_clk>; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1301 | #clock-cells = <1>; |
Ben Dooks | b54010a | 2014-11-10 19:49:37 +0100 | [diff] [blame] | 1302 | clock-indices = < |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1303 | R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 |
Laurent Pinchart | 9d90951 | 2013-12-19 16:51:01 +0100 | [diff] [blame] | 1304 | R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 |
| 1305 | R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 |
Laurent Pinchart | c819acd | 2014-07-19 01:50:23 +0200 | [diff] [blame] | 1306 | R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0 |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1307 | >; |
| 1308 | clock-output-names = |
Laurent Pinchart | 9d90951 | 2013-12-19 16:51:01 +0100 | [diff] [blame] | 1309 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", |
Laurent Pinchart | c819acd | 2014-07-19 01:50:23 +0200 | [diff] [blame] | 1310 | "scifb1", "msiof1", "msiof3", "scifb2", |
| 1311 | "sys-dmac1", "sys-dmac0"; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1312 | }; |
| 1313 | mstp3_clks: mstp3_clks@e615013c { |
| 1314 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1315 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; |
Wolfram Sang | 1746514 | 2014-03-11 22:24:37 +0100 | [diff] [blame] | 1316 | clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, |
| 1317 | <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, |
Yoshihiro Shimoda | b02ce79 | 2014-11-17 18:25:13 +0900 | [diff] [blame] | 1318 | <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, |
| 1319 | <&hp_clk>, <&hp_clk>; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1320 | #clock-cells = <1>; |
Ben Dooks | b54010a | 2014-11-10 19:49:37 +0100 | [diff] [blame] | 1321 | clock-indices = < |
Wolfram Sang | 1746514 | 2014-03-11 22:24:37 +0100 | [diff] [blame] | 1322 | R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 |
| 1323 | R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 |
Phil Edworthy | ecafea8 | 2014-06-13 10:37:15 +0100 | [diff] [blame] | 1324 | R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 |
Yoshihiro Shimoda | b02ce79 | 2014-11-17 18:25:13 +0900 | [diff] [blame] | 1325 | R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1 |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1326 | >; |
| 1327 | clock-output-names = |
Wolfram Sang | 1746514 | 2014-03-11 22:24:37 +0100 | [diff] [blame] | 1328 | "iic2", "tpu0", "mmcif1", "sdhi3", |
| 1329 | "sdhi2", "sdhi1", "sdhi0", "mmcif0", |
Yoshihiro Shimoda | b02ce79 | 2014-11-17 18:25:13 +0900 | [diff] [blame] | 1330 | "iic0", "pciec", "iic1", "ssusb", "cmt1", |
| 1331 | "usbdmac0", "usbdmac1"; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1332 | }; |
Geert Uytterhoeven | 61624ca | 2015-03-18 19:55:59 +0100 | [diff] [blame] | 1333 | mstp4_clks: mstp4_clks@e6150140 { |
| 1334 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1335 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; |
| 1336 | clocks = <&cp_clk>; |
| 1337 | #clock-cells = <1>; |
| 1338 | clock-indices = <R8A7790_CLK_IRQC>; |
| 1339 | clock-output-names = "irqc"; |
| 1340 | }; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1341 | mstp5_clks: mstp5_clks@e6150144 { |
| 1342 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1343 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; |
Sergei Shtylyov | 3453ca9 | 2014-12-30 23:21:45 +0300 | [diff] [blame] | 1344 | clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>, |
| 1345 | <&extal_clk>, <&p_clk>; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1346 | #clock-cells = <1>; |
Ben Dooks | b54010a | 2014-11-10 19:49:37 +0100 | [diff] [blame] | 1347 | clock-indices = < |
| 1348 | R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1 |
Sergei Shtylyov | 3453ca9 | 2014-12-30 23:21:45 +0300 | [diff] [blame] | 1349 | R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL |
| 1350 | R8A7790_CLK_PWM |
Ben Dooks | b54010a | 2014-11-10 19:49:37 +0100 | [diff] [blame] | 1351 | >; |
Sergei Shtylyov | 3453ca9 | 2014-12-30 23:21:45 +0300 | [diff] [blame] | 1352 | clock-output-names = "audmac0", "audmac1", "adsp_mod", |
| 1353 | "thermal", "pwm"; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1354 | }; |
| 1355 | mstp7_clks: mstp7_clks@e615014c { |
| 1356 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1357 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; |
Kazuya Mizuguchi | b621f6d | 2015-02-19 10:42:55 -0500 | [diff] [blame] | 1358 | clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1359 | <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, |
| 1360 | <&zx_clk>; |
| 1361 | #clock-cells = <1>; |
Ben Dooks | b54010a | 2014-11-10 19:49:37 +0100 | [diff] [blame] | 1362 | clock-indices = < |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1363 | R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 |
| 1364 | R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 |
| 1365 | R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 |
| 1366 | R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0 |
| 1367 | >; |
| 1368 | clock-output-names = |
| 1369 | "ehci", "hsusb", "hscif1", "hscif0", "scif1", |
| 1370 | "scif0", "du2", "du1", "du0", "lvds1", "lvds0"; |
| 1371 | }; |
| 1372 | mstp8_clks: mstp8_clks@e6150990 { |
| 1373 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1374 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; |
Andrey Gusakov | f6b5dd4 | 2014-12-18 23:41:52 +0300 | [diff] [blame] | 1375 | clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, |
Sergei Shtylyov | 63d2d75 | 2015-06-16 02:42:42 +0300 | [diff] [blame] | 1376 | <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>, |
| 1377 | <&zs_clk>; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1378 | #clock-cells = <1>; |
Ben Dooks | b54010a | 2014-11-10 19:49:37 +0100 | [diff] [blame] | 1379 | clock-indices = < |
Andrey Gusakov | f6b5dd4 | 2014-12-18 23:41:52 +0300 | [diff] [blame] | 1380 | R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 |
Sergei Shtylyov | 63d2d75 | 2015-06-16 02:42:42 +0300 | [diff] [blame] | 1381 | R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 |
| 1382 | R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER |
Andrey Gusakov | f6b5dd4 | 2014-12-18 23:41:52 +0300 | [diff] [blame] | 1383 | R8A7790_CLK_SATA1 R8A7790_CLK_SATA0 |
Laurent Pinchart | 3f2beaa | 2014-01-07 09:22:53 +0100 | [diff] [blame] | 1384 | >; |
Laurent Pinchart | bccccc3 | 2014-01-07 09:22:55 +0100 | [diff] [blame] | 1385 | clock-output-names = |
Sergei Shtylyov | 63d2d75 | 2015-06-16 02:42:42 +0300 | [diff] [blame] | 1386 | "mlb", "vin3", "vin2", "vin1", "vin0", |
| 1387 | "etheravb", "ether", "sata1", "sata0"; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1388 | }; |
| 1389 | mstp9_clks: mstp9_clks@e6150994 { |
| 1390 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1391 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; |
Geert Uytterhoeven | 81f6883 | 2014-04-23 10:25:27 +0200 | [diff] [blame] | 1392 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, |
| 1393 | <&cp_clk>, <&cp_clk>, <&cp_clk>, |
| 1394 | <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, |
Laurent Pinchart | 3672b05 | 2014-04-01 13:02:17 +0200 | [diff] [blame] | 1395 | <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1396 | #clock-cells = <1>; |
Ben Dooks | b54010a | 2014-11-10 19:49:37 +0100 | [diff] [blame] | 1397 | clock-indices = < |
Geert Uytterhoeven | 81f6883 | 2014-04-23 10:25:27 +0200 | [diff] [blame] | 1398 | R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3 |
| 1399 | R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0 |
Wolfram Sang | 1746514 | 2014-03-11 22:24:37 +0100 | [diff] [blame] | 1400 | R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS |
| 1401 | R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1402 | >; |
Laurent Pinchart | 91b56ca | 2013-12-19 16:51:03 +0100 | [diff] [blame] | 1403 | clock-output-names = |
Geert Uytterhoeven | 81f6883 | 2014-04-23 10:25:27 +0200 | [diff] [blame] | 1404 | "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", |
Wolfram Sang | 1746514 | 2014-03-11 22:24:37 +0100 | [diff] [blame] | 1405 | "rcan1", "rcan0", "qspi_mod", "iic3", |
| 1406 | "i2c3", "i2c2", "i2c1", "i2c0"; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1407 | }; |
Kuninori Morimoto | bcde372 | 2014-06-10 23:53:27 -0700 | [diff] [blame] | 1408 | mstp10_clks: mstp10_clks@e6150998 { |
| 1409 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1410 | reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; |
| 1411 | clocks = <&p_clk>, |
| 1412 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, |
| 1413 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, |
| 1414 | <&p_clk>, |
| 1415 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, |
| 1416 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, |
| 1417 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, |
| 1418 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, |
| 1419 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, |
Kuninori Morimoto | a716378 | 2015-07-21 00:26:20 +0000 | [diff] [blame] | 1420 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, |
Kuninori Morimoto | bcde372 | 2014-06-10 23:53:27 -0700 | [diff] [blame] | 1421 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>; |
| 1422 | |
| 1423 | #clock-cells = <1>; |
| 1424 | clock-indices = < |
| 1425 | R8A7790_CLK_SSI_ALL |
| 1426 | R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5 |
| 1427 | R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0 |
| 1428 | R8A7790_CLK_SCU_ALL |
| 1429 | R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0 |
Kuninori Morimoto | a716378 | 2015-07-21 00:26:20 +0000 | [diff] [blame] | 1430 | R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0 |
Kuninori Morimoto | bcde372 | 2014-06-10 23:53:27 -0700 | [diff] [blame] | 1431 | R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5 |
| 1432 | R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0 |
| 1433 | >; |
| 1434 | clock-output-names = |
| 1435 | "ssi-all", |
| 1436 | "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", |
| 1437 | "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", |
| 1438 | "scu-all", |
| 1439 | "scu-dvc1", "scu-dvc0", |
Kuninori Morimoto | a716378 | 2015-07-21 00:26:20 +0000 | [diff] [blame] | 1440 | "scu-ctu1-mix1", "scu-ctu0-mix0", |
Kuninori Morimoto | bcde372 | 2014-06-10 23:53:27 -0700 | [diff] [blame] | 1441 | "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", |
| 1442 | "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; |
| 1443 | }; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 1444 | }; |
Geert Uytterhoeven | 7053e13 | 2014-02-10 11:47:29 +0100 | [diff] [blame] | 1445 | |
Geert Uytterhoeven | fad6d45 | 2014-02-25 11:30:13 +0100 | [diff] [blame] | 1446 | qspi: spi@e6b10000 { |
Geert Uytterhoeven | 7053e13 | 2014-02-10 11:47:29 +0100 | [diff] [blame] | 1447 | compatible = "renesas,qspi-r8a7790", "renesas,qspi"; |
| 1448 | reg = <0 0xe6b10000 0 0x2c>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1449 | interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 7053e13 | 2014-02-10 11:47:29 +0100 | [diff] [blame] | 1450 | clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; |
Geert Uytterhoeven | 37cf3d6 | 2014-08-06 14:59:08 +0200 | [diff] [blame] | 1451 | dmas = <&dmac0 0x17>, <&dmac0 0x18>; |
| 1452 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 1453 | power-domains = <&cpg_clocks>; |
Geert Uytterhoeven | 7053e13 | 2014-02-10 11:47:29 +0100 | [diff] [blame] | 1454 | num-cs = <1>; |
| 1455 | #address-cells = <1>; |
| 1456 | #size-cells = <0>; |
| 1457 | status = "disabled"; |
| 1458 | }; |
Geert Uytterhoeven | ae8a614 | 2014-02-25 11:30:15 +0100 | [diff] [blame] | 1459 | |
| 1460 | msiof0: spi@e6e20000 { |
| 1461 | compatible = "renesas,msiof-r8a7790"; |
Ryo Kataoka | c7d1f08 | 2015-04-05 01:54:31 +0900 | [diff] [blame] | 1462 | reg = <0 0xe6e20000 0 0x0064>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1463 | interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | ae8a614 | 2014-02-25 11:30:15 +0100 | [diff] [blame] | 1464 | clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; |
Geert Uytterhoeven | fbff668 | 2014-08-06 14:59:09 +0200 | [diff] [blame] | 1465 | dmas = <&dmac0 0x51>, <&dmac0 0x52>; |
| 1466 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 1467 | power-domains = <&cpg_clocks>; |
Geert Uytterhoeven | ae8a614 | 2014-02-25 11:30:15 +0100 | [diff] [blame] | 1468 | #address-cells = <1>; |
| 1469 | #size-cells = <0>; |
| 1470 | status = "disabled"; |
| 1471 | }; |
| 1472 | |
| 1473 | msiof1: spi@e6e10000 { |
| 1474 | compatible = "renesas,msiof-r8a7790"; |
Ryo Kataoka | c7d1f08 | 2015-04-05 01:54:31 +0900 | [diff] [blame] | 1475 | reg = <0 0xe6e10000 0 0x0064>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1476 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | ae8a614 | 2014-02-25 11:30:15 +0100 | [diff] [blame] | 1477 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; |
Geert Uytterhoeven | fbff668 | 2014-08-06 14:59:09 +0200 | [diff] [blame] | 1478 | dmas = <&dmac0 0x55>, <&dmac0 0x56>; |
| 1479 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 1480 | power-domains = <&cpg_clocks>; |
Geert Uytterhoeven | ae8a614 | 2014-02-25 11:30:15 +0100 | [diff] [blame] | 1481 | #address-cells = <1>; |
| 1482 | #size-cells = <0>; |
| 1483 | status = "disabled"; |
| 1484 | }; |
| 1485 | |
| 1486 | msiof2: spi@e6e00000 { |
| 1487 | compatible = "renesas,msiof-r8a7790"; |
Ryo Kataoka | c7d1f08 | 2015-04-05 01:54:31 +0900 | [diff] [blame] | 1488 | reg = <0 0xe6e00000 0 0x0064>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1489 | interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | ae8a614 | 2014-02-25 11:30:15 +0100 | [diff] [blame] | 1490 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; |
Geert Uytterhoeven | fbff668 | 2014-08-06 14:59:09 +0200 | [diff] [blame] | 1491 | dmas = <&dmac0 0x41>, <&dmac0 0x42>; |
| 1492 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 1493 | power-domains = <&cpg_clocks>; |
Geert Uytterhoeven | ae8a614 | 2014-02-25 11:30:15 +0100 | [diff] [blame] | 1494 | #address-cells = <1>; |
| 1495 | #size-cells = <0>; |
| 1496 | status = "disabled"; |
| 1497 | }; |
| 1498 | |
| 1499 | msiof3: spi@e6c90000 { |
| 1500 | compatible = "renesas,msiof-r8a7790"; |
Ryo Kataoka | c7d1f08 | 2015-04-05 01:54:31 +0900 | [diff] [blame] | 1501 | reg = <0 0xe6c90000 0 0x0064>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1502 | interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | ae8a614 | 2014-02-25 11:30:15 +0100 | [diff] [blame] | 1503 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; |
Geert Uytterhoeven | fbff668 | 2014-08-06 14:59:09 +0200 | [diff] [blame] | 1504 | dmas = <&dmac0 0x45>, <&dmac0 0x46>; |
| 1505 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 1506 | power-domains = <&cpg_clocks>; |
Geert Uytterhoeven | ae8a614 | 2014-02-25 11:30:15 +0100 | [diff] [blame] | 1507 | #address-cells = <1>; |
| 1508 | #size-cells = <0>; |
| 1509 | status = "disabled"; |
| 1510 | }; |
Kuninori Morimoto | 7df2fd5 | 2014-06-10 23:53:54 -0700 | [diff] [blame] | 1511 | |
Yoshihiro Shimoda | 157fcd8 | 2014-10-24 19:41:46 +0900 | [diff] [blame] | 1512 | xhci: usb@ee000000 { |
| 1513 | compatible = "renesas,xhci-r8a7790"; |
| 1514 | reg = <0 0xee000000 0 0xc00>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1515 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
Yoshihiro Shimoda | 157fcd8 | 2014-10-24 19:41:46 +0900 | [diff] [blame] | 1516 | clocks = <&mstp3_clks R8A7790_CLK_SSUSB>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 1517 | power-domains = <&cpg_clocks>; |
Yoshihiro Shimoda | 157fcd8 | 2014-10-24 19:41:46 +0900 | [diff] [blame] | 1518 | phys = <&usb2 1>; |
| 1519 | phy-names = "usb"; |
| 1520 | status = "disabled"; |
| 1521 | }; |
| 1522 | |
Ben Dooks | ff4f3eb | 2014-06-24 21:59:54 +0400 | [diff] [blame] | 1523 | pci0: pci@ee090000 { |
Simon Horman | 2d82c14 | 2015-12-18 11:42:37 +0900 | [diff] [blame] | 1524 | compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; |
Ben Dooks | ff4f3eb | 2014-06-24 21:59:54 +0400 | [diff] [blame] | 1525 | device_type = "pci"; |
Ben Dooks | ff4f3eb | 2014-06-24 21:59:54 +0400 | [diff] [blame] | 1526 | reg = <0 0xee090000 0 0xc00>, |
| 1527 | <0 0xee080000 0 0x1100>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1528 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 1529 | clocks = <&mstp7_clks R8A7790_CLK_EHCI>; |
| 1530 | power-domains = <&cpg_clocks>; |
Ben Dooks | ff4f3eb | 2014-06-24 21:59:54 +0400 | [diff] [blame] | 1531 | status = "disabled"; |
| 1532 | |
| 1533 | bus-range = <0 0>; |
| 1534 | #address-cells = <3>; |
| 1535 | #size-cells = <2>; |
| 1536 | #interrupt-cells = <1>; |
| 1537 | ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; |
| 1538 | interrupt-map-mask = <0xff00 0 0 0x7>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1539 | interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH |
| 1540 | 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH |
| 1541 | 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 538c40e | 2014-09-29 22:21:59 +0400 | [diff] [blame] | 1542 | |
| 1543 | usb@0,1 { |
| 1544 | reg = <0x800 0 0 0 0>; |
| 1545 | device_type = "pci"; |
| 1546 | phys = <&usb0 0>; |
| 1547 | phy-names = "usb"; |
| 1548 | }; |
| 1549 | |
| 1550 | usb@0,2 { |
| 1551 | reg = <0x1000 0 0 0 0>; |
| 1552 | device_type = "pci"; |
| 1553 | phys = <&usb0 0>; |
| 1554 | phy-names = "usb"; |
| 1555 | }; |
Ben Dooks | ff4f3eb | 2014-06-24 21:59:54 +0400 | [diff] [blame] | 1556 | }; |
| 1557 | |
| 1558 | pci1: pci@ee0b0000 { |
Simon Horman | 2d82c14 | 2015-12-18 11:42:37 +0900 | [diff] [blame] | 1559 | compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; |
Ben Dooks | ff4f3eb | 2014-06-24 21:59:54 +0400 | [diff] [blame] | 1560 | device_type = "pci"; |
Ben Dooks | ff4f3eb | 2014-06-24 21:59:54 +0400 | [diff] [blame] | 1561 | reg = <0 0xee0b0000 0 0xc00>, |
| 1562 | <0 0xee0a0000 0 0x1100>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1563 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 1564 | clocks = <&mstp7_clks R8A7790_CLK_EHCI>; |
| 1565 | power-domains = <&cpg_clocks>; |
Ben Dooks | ff4f3eb | 2014-06-24 21:59:54 +0400 | [diff] [blame] | 1566 | status = "disabled"; |
| 1567 | |
| 1568 | bus-range = <1 1>; |
| 1569 | #address-cells = <3>; |
| 1570 | #size-cells = <2>; |
| 1571 | #interrupt-cells = <1>; |
| 1572 | ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; |
| 1573 | interrupt-map-mask = <0xff00 0 0 0x7>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1574 | interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH |
| 1575 | 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH |
| 1576 | 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
Ben Dooks | ff4f3eb | 2014-06-24 21:59:54 +0400 | [diff] [blame] | 1577 | }; |
| 1578 | |
| 1579 | pci2: pci@ee0d0000 { |
Simon Horman | 2d82c14 | 2015-12-18 11:42:37 +0900 | [diff] [blame] | 1580 | compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; |
Ben Dooks | ff4f3eb | 2014-06-24 21:59:54 +0400 | [diff] [blame] | 1581 | device_type = "pci"; |
| 1582 | clocks = <&mstp7_clks R8A7790_CLK_EHCI>; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 1583 | power-domains = <&cpg_clocks>; |
Ben Dooks | ff4f3eb | 2014-06-24 21:59:54 +0400 | [diff] [blame] | 1584 | reg = <0 0xee0d0000 0 0xc00>, |
| 1585 | <0 0xee0c0000 0 0x1100>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1586 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
Ben Dooks | ff4f3eb | 2014-06-24 21:59:54 +0400 | [diff] [blame] | 1587 | status = "disabled"; |
| 1588 | |
| 1589 | bus-range = <2 2>; |
| 1590 | #address-cells = <3>; |
| 1591 | #size-cells = <2>; |
| 1592 | #interrupt-cells = <1>; |
| 1593 | ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; |
| 1594 | interrupt-map-mask = <0xff00 0 0 0x7>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1595 | interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH |
| 1596 | 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH |
| 1597 | 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 538c40e | 2014-09-29 22:21:59 +0400 | [diff] [blame] | 1598 | |
| 1599 | usb@0,1 { |
| 1600 | reg = <0x800 0 0 0 0>; |
| 1601 | device_type = "pci"; |
| 1602 | phys = <&usb2 0>; |
| 1603 | phy-names = "usb"; |
| 1604 | }; |
| 1605 | |
| 1606 | usb@0,2 { |
| 1607 | reg = <0x1000 0 0 0 0>; |
| 1608 | device_type = "pci"; |
| 1609 | phys = <&usb2 0>; |
| 1610 | phy-names = "usb"; |
| 1611 | }; |
Ben Dooks | ff4f3eb | 2014-06-24 21:59:54 +0400 | [diff] [blame] | 1612 | }; |
| 1613 | |
Phil Edworthy | 745329d | 2014-06-13 10:37:17 +0100 | [diff] [blame] | 1614 | pciec: pcie@fe000000 { |
Simon Horman | e670be8 | 2015-12-18 11:36:02 +0900 | [diff] [blame] | 1615 | compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2"; |
Phil Edworthy | 745329d | 2014-06-13 10:37:17 +0100 | [diff] [blame] | 1616 | reg = <0 0xfe000000 0 0x80000>; |
| 1617 | #address-cells = <3>; |
| 1618 | #size-cells = <2>; |
| 1619 | bus-range = <0x00 0xff>; |
| 1620 | device_type = "pci"; |
| 1621 | ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 |
| 1622 | 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 |
| 1623 | 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 |
| 1624 | 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; |
| 1625 | /* Map all possible DDR as inbound ranges */ |
| 1626 | dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 |
| 1627 | 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1628 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 1629 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 1630 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; |
Phil Edworthy | 745329d | 2014-06-13 10:37:17 +0100 | [diff] [blame] | 1631 | #interrupt-cells = <1>; |
| 1632 | interrupt-map-mask = <0 0 0 0>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1633 | interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
Phil Edworthy | 745329d | 2014-06-13 10:37:17 +0100 | [diff] [blame] | 1634 | clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>; |
| 1635 | clock-names = "pcie", "pcie_bus"; |
Geert Uytterhoeven | 484adb0 | 2015-08-04 14:28:10 +0200 | [diff] [blame] | 1636 | power-domains = <&cpg_clocks>; |
Phil Edworthy | 745329d | 2014-06-13 10:37:17 +0100 | [diff] [blame] | 1637 | status = "disabled"; |
| 1638 | }; |
| 1639 | |
Geert Uytterhoeven | b694e38 | 2015-04-27 14:55:28 +0200 | [diff] [blame] | 1640 | rcar_sound: sound@ec500000 { |
Kuninori Morimoto | ad63241 | 2014-12-17 06:11:52 +0000 | [diff] [blame] | 1641 | /* |
| 1642 | * #sound-dai-cells is required |
| 1643 | * |
| 1644 | * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; |
| 1645 | * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; |
| 1646 | */ |
Geert Uytterhoeven | 31078ec | 2015-01-06 21:01:52 +0100 | [diff] [blame] | 1647 | compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2"; |
Kuninori Morimoto | 7df2fd5 | 2014-06-10 23:53:54 -0700 | [diff] [blame] | 1648 | reg = <0 0xec500000 0 0x1000>, /* SCU */ |
| 1649 | <0 0xec5a0000 0 0x100>, /* ADG */ |
| 1650 | <0 0xec540000 0 0x1000>, /* SSIU */ |
Kuninori Morimoto | 4bc4a20 | 2015-08-24 08:27:56 +0000 | [diff] [blame] | 1651 | <0 0xec541000 0 0x280>, /* SSI */ |
Kuninori Morimoto | 0c60267 | 2015-03-10 01:39:39 +0000 | [diff] [blame] | 1652 | <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ |
| 1653 | reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; |
Kuninori Morimoto | 46a158f | 2015-03-10 01:39:01 +0000 | [diff] [blame] | 1654 | |
Kuninori Morimoto | 7df2fd5 | 2014-06-10 23:53:54 -0700 | [diff] [blame] | 1655 | clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>, |
| 1656 | <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>, |
| 1657 | <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>, |
| 1658 | <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>, |
| 1659 | <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>, |
| 1660 | <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>, |
| 1661 | <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>, |
| 1662 | <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>, |
| 1663 | <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>, |
| 1664 | <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>, |
| 1665 | <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>, |
Kuninori Morimoto | a716378 | 2015-07-21 00:26:20 +0000 | [diff] [blame] | 1666 | <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, |
Kuninori Morimoto | fc67bf4 | 2015-07-21 00:26:42 +0000 | [diff] [blame] | 1667 | <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, |
Kuninori Morimoto | 334d69a | 2014-06-25 17:52:17 -0700 | [diff] [blame] | 1668 | <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>, |
Kuninori Morimoto | 7df2fd5 | 2014-06-10 23:53:54 -0700 | [diff] [blame] | 1669 | <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; |
| 1670 | clock-names = "ssi-all", |
| 1671 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", |
| 1672 | "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", |
| 1673 | "src.9", "src.8", "src.7", "src.6", "src.5", |
| 1674 | "src.4", "src.3", "src.2", "src.1", "src.0", |
Kuninori Morimoto | a716378 | 2015-07-21 00:26:20 +0000 | [diff] [blame] | 1675 | "ctu.0", "ctu.1", |
Kuninori Morimoto | fc67bf4 | 2015-07-21 00:26:42 +0000 | [diff] [blame] | 1676 | "mix.0", "mix.1", |
Kuninori Morimoto | 334d69a | 2014-06-25 17:52:17 -0700 | [diff] [blame] | 1677 | "dvc.0", "dvc.1", |
Kuninori Morimoto | 7df2fd5 | 2014-06-10 23:53:54 -0700 | [diff] [blame] | 1678 | "clk_a", "clk_b", "clk_c", "clk_i"; |
Geert Uytterhoeven | 6507c4e | 2015-08-20 01:24:44 +0000 | [diff] [blame] | 1679 | power-domains = <&cpg_clocks>; |
Kuninori Morimoto | 7df2fd5 | 2014-06-10 23:53:54 -0700 | [diff] [blame] | 1680 | |
| 1681 | status = "disabled"; |
| 1682 | |
Kuninori Morimoto | 334d69a | 2014-06-25 17:52:17 -0700 | [diff] [blame] | 1683 | rcar_sound,dvc { |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1684 | dvc0: dvc@0 { |
| 1685 | dmas = <&audma0 0xbc>; |
| 1686 | dma-names = "tx"; |
| 1687 | }; |
| 1688 | dvc1: dvc@1 { |
| 1689 | dmas = <&audma0 0xbe>; |
| 1690 | dma-names = "tx"; |
| 1691 | }; |
Kuninori Morimoto | 334d69a | 2014-06-25 17:52:17 -0700 | [diff] [blame] | 1692 | }; |
| 1693 | |
Kuninori Morimoto | fc67bf4 | 2015-07-21 00:26:42 +0000 | [diff] [blame] | 1694 | rcar_sound,mix { |
| 1695 | mix0: mix@0 { }; |
| 1696 | mix1: mix@1 { }; |
| 1697 | }; |
| 1698 | |
Kuninori Morimoto | a716378 | 2015-07-21 00:26:20 +0000 | [diff] [blame] | 1699 | rcar_sound,ctu { |
| 1700 | ctu00: ctu@0 { }; |
| 1701 | ctu01: ctu@1 { }; |
| 1702 | ctu02: ctu@2 { }; |
| 1703 | ctu03: ctu@3 { }; |
| 1704 | ctu10: ctu@4 { }; |
| 1705 | ctu11: ctu@5 { }; |
| 1706 | ctu12: ctu@6 { }; |
| 1707 | ctu13: ctu@7 { }; |
| 1708 | }; |
| 1709 | |
Kuninori Morimoto | 7df2fd5 | 2014-06-10 23:53:54 -0700 | [diff] [blame] | 1710 | rcar_sound,src { |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1711 | src0: src@0 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1712 | interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1713 | dmas = <&audma0 0x85>, <&audma1 0x9a>; |
| 1714 | dma-names = "rx", "tx"; |
| 1715 | }; |
| 1716 | src1: src@1 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1717 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1718 | dmas = <&audma0 0x87>, <&audma1 0x9c>; |
| 1719 | dma-names = "rx", "tx"; |
| 1720 | }; |
| 1721 | src2: src@2 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1722 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1723 | dmas = <&audma0 0x89>, <&audma1 0x9e>; |
| 1724 | dma-names = "rx", "tx"; |
| 1725 | }; |
| 1726 | src3: src@3 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1727 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1728 | dmas = <&audma0 0x8b>, <&audma1 0xa0>; |
| 1729 | dma-names = "rx", "tx"; |
| 1730 | }; |
| 1731 | src4: src@4 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1732 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1733 | dmas = <&audma0 0x8d>, <&audma1 0xb0>; |
| 1734 | dma-names = "rx", "tx"; |
| 1735 | }; |
| 1736 | src5: src@5 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1737 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1738 | dmas = <&audma0 0x8f>, <&audma1 0xb2>; |
| 1739 | dma-names = "rx", "tx"; |
| 1740 | }; |
| 1741 | src6: src@6 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1742 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1743 | dmas = <&audma0 0x91>, <&audma1 0xb4>; |
| 1744 | dma-names = "rx", "tx"; |
| 1745 | }; |
| 1746 | src7: src@7 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1747 | interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1748 | dmas = <&audma0 0x93>, <&audma1 0xb6>; |
| 1749 | dma-names = "rx", "tx"; |
| 1750 | }; |
| 1751 | src8: src@8 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1752 | interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1753 | dmas = <&audma0 0x95>, <&audma1 0xb8>; |
| 1754 | dma-names = "rx", "tx"; |
| 1755 | }; |
| 1756 | src9: src@9 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1757 | interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1758 | dmas = <&audma0 0x97>, <&audma1 0xba>; |
| 1759 | dma-names = "rx", "tx"; |
| 1760 | }; |
Kuninori Morimoto | 7df2fd5 | 2014-06-10 23:53:54 -0700 | [diff] [blame] | 1761 | }; |
| 1762 | |
| 1763 | rcar_sound,ssi { |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1764 | ssi0: ssi@0 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1765 | interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1766 | dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; |
| 1767 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1768 | }; |
| 1769 | ssi1: ssi@1 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1770 | interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1771 | dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; |
| 1772 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1773 | }; |
| 1774 | ssi2: ssi@2 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1775 | interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1776 | dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; |
| 1777 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1778 | }; |
| 1779 | ssi3: ssi@3 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1780 | interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1781 | dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; |
| 1782 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1783 | }; |
| 1784 | ssi4: ssi@4 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1785 | interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1786 | dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; |
| 1787 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1788 | }; |
| 1789 | ssi5: ssi@5 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1790 | interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1791 | dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; |
| 1792 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1793 | }; |
| 1794 | ssi6: ssi@6 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1795 | interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1796 | dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; |
| 1797 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1798 | }; |
| 1799 | ssi7: ssi@7 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1800 | interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1801 | dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; |
| 1802 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1803 | }; |
| 1804 | ssi8: ssi@8 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1805 | interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1806 | dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; |
| 1807 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1808 | }; |
| 1809 | ssi9: ssi@9 { |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1810 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 118a509 | 2015-03-10 01:40:13 +0000 | [diff] [blame] | 1811 | dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; |
| 1812 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1813 | }; |
Kuninori Morimoto | 7df2fd5 | 2014-06-10 23:53:54 -0700 | [diff] [blame] | 1814 | }; |
| 1815 | }; |
Laurent Pinchart | 7049672 | 2015-01-27 11:13:23 +0200 | [diff] [blame] | 1816 | |
| 1817 | ipmmu_sy0: mmu@e6280000 { |
Magnus Damm | c8d6686 | 2015-11-17 13:30:56 +0900 | [diff] [blame] | 1818 | compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | 7049672 | 2015-01-27 11:13:23 +0200 | [diff] [blame] | 1819 | reg = <0 0xe6280000 0 0x1000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1820 | interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, |
| 1821 | <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 7049672 | 2015-01-27 11:13:23 +0200 | [diff] [blame] | 1822 | #iommu-cells = <1>; |
| 1823 | status = "disabled"; |
| 1824 | }; |
| 1825 | |
| 1826 | ipmmu_sy1: mmu@e6290000 { |
Magnus Damm | c8d6686 | 2015-11-17 13:30:56 +0900 | [diff] [blame] | 1827 | compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | 7049672 | 2015-01-27 11:13:23 +0200 | [diff] [blame] | 1828 | reg = <0 0xe6290000 0 0x1000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1829 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 7049672 | 2015-01-27 11:13:23 +0200 | [diff] [blame] | 1830 | #iommu-cells = <1>; |
| 1831 | status = "disabled"; |
| 1832 | }; |
| 1833 | |
| 1834 | ipmmu_ds: mmu@e6740000 { |
Magnus Damm | c8d6686 | 2015-11-17 13:30:56 +0900 | [diff] [blame] | 1835 | compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | 7049672 | 2015-01-27 11:13:23 +0200 | [diff] [blame] | 1836 | reg = <0 0xe6740000 0 0x1000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1837 | interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
| 1838 | <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 7049672 | 2015-01-27 11:13:23 +0200 | [diff] [blame] | 1839 | #iommu-cells = <1>; |
| 1840 | status = "disabled"; |
| 1841 | }; |
| 1842 | |
| 1843 | ipmmu_mp: mmu@ec680000 { |
Magnus Damm | c8d6686 | 2015-11-17 13:30:56 +0900 | [diff] [blame] | 1844 | compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | 7049672 | 2015-01-27 11:13:23 +0200 | [diff] [blame] | 1845 | reg = <0 0xec680000 0 0x1000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1846 | interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 7049672 | 2015-01-27 11:13:23 +0200 | [diff] [blame] | 1847 | #iommu-cells = <1>; |
| 1848 | status = "disabled"; |
| 1849 | }; |
| 1850 | |
| 1851 | ipmmu_mx: mmu@fe951000 { |
Magnus Damm | c8d6686 | 2015-11-17 13:30:56 +0900 | [diff] [blame] | 1852 | compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | 7049672 | 2015-01-27 11:13:23 +0200 | [diff] [blame] | 1853 | reg = <0 0xfe951000 0 0x1000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1854 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, |
| 1855 | <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 7049672 | 2015-01-27 11:13:23 +0200 | [diff] [blame] | 1856 | #iommu-cells = <1>; |
| 1857 | status = "disabled"; |
| 1858 | }; |
| 1859 | |
| 1860 | ipmmu_rt: mmu@ffc80000 { |
Magnus Damm | c8d6686 | 2015-11-17 13:30:56 +0900 | [diff] [blame] | 1861 | compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | 7049672 | 2015-01-27 11:13:23 +0200 | [diff] [blame] | 1862 | reg = <0 0xffc80000 0 0x1000>; |
Simon Horman | 3abb4d5 | 2016-01-15 11:44:15 +0900 | [diff] [blame] | 1863 | interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 7049672 | 2015-01-27 11:13:23 +0200 | [diff] [blame] | 1864 | #iommu-cells = <1>; |
| 1865 | status = "disabled"; |
| 1866 | }; |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 1867 | }; |