blob: 85fa6a2a6dd20c8866b9e58f12193b6f6a20a390 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
David Brownell75862692005-09-23 17:14:37 -070010 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 */
13
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/types.h>
15#include <linux/kernel.h>
Paul Gortmaker363c75d2011-05-27 09:37:25 -040016#include <linux/export.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/pci.h>
18#include <linux/init.h>
19#include <linux/delay.h>
Len Brown25be5e62005-05-27 04:21:50 -040020#include <linux/acpi.h>
bjorn.helgaas@hp.com9f23ed32007-12-17 14:09:38 -070021#include <linux/kallsyms.h>
Andreas Petlund75e07fc2008-11-20 20:42:25 -080022#include <linux/dmi.h>
Alexander Duyck649426e2009-03-05 13:57:28 -050023#include <linux/pci-aspm.h>
Yuji Shimada32a9a6822009-03-16 17:13:39 +090024#include <linux/ioport.h>
Arjan van de Ven32098742012-01-30 20:52:07 -080025#include <linux/sched.h>
26#include <linux/ktime.h>
Douglas Lehr9fe373f2014-08-21 09:26:52 +100027#include <linux/mm.h>
Rafael J. Wysocki93177a72010-01-02 22:57:24 +010028#include <asm/dma.h> /* isa_dma_bridge_buggy */
Greg KHbc56b9e2005-04-08 14:53:31 +090029#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
Yuji Shimada32a9a6822009-03-16 17:13:39 +090031/*
Jacob Pan253d2e52010-07-16 10:19:22 -070032 * Decoding should be disabled for a PCI device during BAR sizing to avoid
33 * conflict. But doing so may cause problems on host bridge and perhaps other
34 * key system devices. For devices that need to have mmio decoding always-on,
35 * we need to set the dev->mmio_always_on bit.
36 */
Bill Pemberton15856ad2012-11-21 15:35:00 -050037static void quirk_mmio_always_on(struct pci_dev *dev)
Jacob Pan253d2e52010-07-16 10:19:22 -070038{
Yinghai Lu52d21b52012-02-23 23:46:53 -080039 dev->mmio_always_on = 1;
Jacob Pan253d2e52010-07-16 10:19:22 -070040}
Yinghai Lu52d21b52012-02-23 23:46:53 -080041DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
42 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
Jacob Pan253d2e52010-07-16 10:19:22 -070043
Doug Thompsonbd8481e2006-05-08 17:06:09 -070044/* The Mellanox Tavor device gives false positive parity errors
45 * Mark this device with a broken_parity_status, to allow
46 * PCI scanning code to "skip" this now blacklisted device.
47 */
Bill Pemberton15856ad2012-11-21 15:35:00 -050048static void quirk_mellanox_tavor(struct pci_dev *dev)
Doug Thompsonbd8481e2006-05-08 17:06:09 -070049{
50 dev->broken_parity_status = 1; /* This device gives false positives */
51}
Ryan Desfosses3c78bc62014-04-18 20:13:49 -040052DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
53DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
Doug Thompsonbd8481e2006-05-08 17:06:09 -070054
Bjorn Helgaasf7625982013-11-14 11:28:18 -070055/* Deal with broken BIOSes that neglect to enable passive release,
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 which can cause problems in combination with the 82441FX/PPro MTRRs */
Alan Cox1597cac2006-12-04 15:14:45 -080057static void quirk_passive_release(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070058{
59 struct pci_dev *d = NULL;
60 unsigned char dlc;
61
62 /* We have to make sure a particular bit is set in the PIIX3
63 ISA bridge, so we have to go out and find it. */
64 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
65 pci_read_config_byte(d, 0x82, &dlc);
66 if (!(dlc & 1<<1)) {
Adam Jackson999da9f2008-12-01 14:30:29 -080067 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070068 dlc |= 1<<1;
69 pci_write_config_byte(d, 0x82, dlc);
70 }
71 }
72}
Andrew Morton652c5382007-11-21 15:07:13 -080073DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
74DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
Linus Torvalds1da177e2005-04-16 15:20:36 -070075
76/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
77 but VIA don't answer queries. If you happen to have good contacts at VIA
Bjorn Helgaasf7625982013-11-14 11:28:18 -070078 ask them for me please -- Alan
79
80 This appears to be BIOS not version dependent. So presumably there is a
Linus Torvalds1da177e2005-04-16 15:20:36 -070081 chipset level fix */
Bjorn Helgaasf7625982013-11-14 11:28:18 -070082
Bill Pemberton15856ad2012-11-21 15:35:00 -050083static void quirk_isa_dma_hangs(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070084{
85 if (!isa_dma_bridge_buggy) {
Ryan Desfosses3c78bc62014-04-18 20:13:49 -040086 isa_dma_bridge_buggy = 1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -070087 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070088 }
89}
90 /*
91 * Its not totally clear which chipsets are the problematic ones
92 * We know 82C586 and 82C596 variants are affected.
93 */
Andrew Morton652c5382007-11-21 15:07:13 -080094DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
95DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
96DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
Bjorn Helgaasf7625982013-11-14 11:28:18 -070097DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
Andrew Morton652c5382007-11-21 15:07:13 -080098DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102/*
Len Brown4731fdc2010-09-24 21:02:27 -0400103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
104 * for some HT machines to use C4 w/o hanging.
105 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500106static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
Len Brown4731fdc2010-09-24 21:02:27 -0400107{
108 u32 pmbase;
109 u16 pm1a;
110
111 pci_read_config_dword(dev, 0x40, &pmbase);
112 pmbase = pmbase & 0xff80;
113 pm1a = inw(pmbase);
114
115 if (pm1a & 0x10) {
116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
117 outw(0x10, pmbase);
118 }
119}
120DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
121
122/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123 * Chipsets where PCI->PCI transfers vanish or hang
124 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500125static void quirk_nopcipci(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400127 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700128 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129 pci_pci_problems |= PCIPCI_FAIL;
130 }
131}
Andrew Morton652c5382007-11-21 15:07:13 -0800132DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
133DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
Alan Cox236561e2006-09-30 23:27:03 -0700134
Bill Pemberton15856ad2012-11-21 15:35:00 -0500135static void quirk_nopciamd(struct pci_dev *dev)
Alan Cox236561e2006-09-30 23:27:03 -0700136{
137 u8 rev;
138 pci_read_config_byte(dev, 0x08, &rev);
139 if (rev == 0x13) {
140 /* Erratum 24 */
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700141 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
Alan Cox236561e2006-09-30 23:27:03 -0700142 pci_pci_problems |= PCIAGP_FAIL;
143 }
144}
Andrew Morton652c5382007-11-21 15:07:13 -0800145DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146
147/*
148 * Triton requires workarounds to be used by the drivers
149 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500150static void quirk_triton(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400152 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700153 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154 pci_pci_problems |= PCIPCI_TRITON;
155 }
156}
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161
162/*
163 * VIA Apollo KT133 needs PCI latency patch
164 * Made according to a windows driver based patch by George E. Breese
165 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400166 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
167 * the info on which Mr Breese based his work.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168 *
169 * Updated based on further information from the site and also on
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700170 * information provided by VIA
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171 */
Alan Cox1597cac2006-12-04 15:14:45 -0800172static void quirk_vialatency(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173{
174 struct pci_dev *p;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175 u8 busarb;
176 /* Ok we have a potential problem chipset here. Now see if we have
177 a buggy southbridge */
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700178
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400180 if (p != NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
182 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700183 if (p->revision < 0x40 || p->revision > 0x42)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184 goto exit;
185 } else {
186 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400187 if (p == NULL) /* No problem parts */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188 goto exit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700190 if (p->revision < 0x10 || p->revision > 0x12)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191 goto exit;
192 }
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700193
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194 /*
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700195 * Ok we have the problem. Now set the PCI master grant to
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196 * occur every master grant. The apparent bug is that under high
197 * PCI load (quite common in Linux of course) you can get data
198 * loss when the CPU is held off the bus for 3 bus master requests
199 * This happens to include the IDE controllers....
200 *
201 * VIA only apply this fix when an SB Live! is present but under
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300202 * both Linux and Windows this isn't enough, and we have seen
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203 * corruption without SB Live! but with things like 3 UDMA IDE
204 * controllers. So we ignore that bit of the VIA recommendation..
205 */
206
207 pci_read_config_byte(dev, 0x76, &busarb);
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700208 /* Set bit 4 and bi 5 of byte 76 to 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209 "Master priority rotation on every PCI master grant */
210 busarb &= ~(1<<5);
211 busarb |= (1<<4);
212 pci_write_config_byte(dev, 0x76, busarb);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700213 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214exit:
215 pci_dev_put(p);
216}
Andrew Morton652c5382007-11-21 15:07:13 -0800217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Alan Cox1597cac2006-12-04 15:14:45 -0800220/* Must restore this on a resume from RAM */
Andrew Morton652c5382007-11-21 15:07:13 -0800221DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
222DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
223DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224
225/*
226 * VIA Apollo VP3 needs ETBF on BT848/878
227 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500228static void quirk_viaetbf(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400230 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700231 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232 pci_pci_problems |= PCIPCI_VIAETBF;
233 }
234}
Andrew Morton652c5382007-11-21 15:07:13 -0800235DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236
Bill Pemberton15856ad2012-11-21 15:35:00 -0500237static void quirk_vsfx(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400239 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700240 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241 pci_pci_problems |= PCIPCI_VSFX;
242 }
243}
Andrew Morton652c5382007-11-21 15:07:13 -0800244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245
246/*
247 * Ali Magik requires workarounds to be used by the drivers
248 * that DMA to AGP space. Latency must be set to 0xA and triton
249 * workaround applied too
250 * [Info kindly provided by ALi]
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700251 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500252static void quirk_alimagik(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400254 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700255 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
257 }
258}
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700259DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261
262/*
263 * Natoma has some interesting boundary conditions with Zoran stuff
264 * at least
265 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500266static void quirk_natoma(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400268 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700269 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270 pci_pci_problems |= PCIPCI_NATOMA;
271 }
272}
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700273DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
274DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
275DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
276DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279
280/*
281 * This chip can cause PCI parity errors if config register 0xA0 is read
282 * while DMAs are occurring.
283 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500284static void quirk_citrine(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285{
286 dev->cfg_size = 0xA0;
287}
Andrew Morton652c5382007-11-21 15:07:13 -0800288DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289
Jason S. McMullan9f33a2a2015-09-30 15:35:07 +0900290/*
291 * This chip can cause bus lockups if config addresses above 0x600
292 * are read or written.
293 */
294static void quirk_nfp6000(struct pci_dev *dev)
295{
296 dev->cfg_size = 0x600;
297}
Simon Hormanc2e771b2015-12-11 11:30:12 +0900298DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
Jason S. McMullan9f33a2a2015-09-30 15:35:07 +0900299DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
300DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
301
Douglas Lehr9fe373f2014-08-21 09:26:52 +1000302/* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
303static void quirk_extend_bar_to_page(struct pci_dev *dev)
304{
305 int i;
306
307 for (i = 0; i < PCI_STD_RESOURCE_END; i++) {
308 struct resource *r = &dev->resource[i];
309
310 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
311 r->end = PAGE_SIZE - 1;
312 r->start = 0;
313 r->flags |= IORESOURCE_UNSET;
314 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
315 i, r);
316 }
317 }
318}
319DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
320
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321/*
322 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
323 * If it's needed, re-allocate the region.
324 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500325static void quirk_s3_64M(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326{
327 struct resource *r = &dev->resource[0];
328
329 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
Bjorn Helgaasbd064f02014-02-26 11:25:58 -0700330 r->flags |= IORESOURCE_UNSET;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331 r->start = 0;
332 r->end = 0x3ffffff;
333 }
334}
Andrew Morton652c5382007-11-21 15:07:13 -0800335DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
336DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337
Myron Stowe06cf35f2015-02-03 16:01:24 -0700338static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
339 const char *name)
340{
341 u32 region;
342 struct pci_bus_region bus_region;
343 struct resource *res = dev->resource + pos;
344
345 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
346
347 if (!region)
348 return;
349
350 res->name = pci_name(dev);
351 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
352 res->flags |=
353 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
354 region &= ~(size - 1);
355
356 /* Convert from PCI bus to resource space */
357 bus_region.start = region;
358 bus_region.end = region + size - 1;
359 pcibios_bus_to_resource(dev->bus, res, &bus_region);
360
361 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
362 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
363}
364
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500365/*
366 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
367 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
368 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
369 * (which conflicts w/ BAR1's memory range).
Myron Stowe06cf35f2015-02-03 16:01:24 -0700370 *
371 * CS553x's ISA PCI BARs may also be read-only (ref:
372 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500373 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500374static void quirk_cs5536_vsa(struct pci_dev *dev)
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500375{
Myron Stowe06cf35f2015-02-03 16:01:24 -0700376 static char *name = "CS5536 ISA bridge";
377
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500378 if (pci_resource_len(dev, 0) != 8) {
Myron Stowe06cf35f2015-02-03 16:01:24 -0700379 quirk_io(dev, 0, 8, name); /* SMB */
380 quirk_io(dev, 1, 256, name); /* GPIO */
381 quirk_io(dev, 2, 64, name); /* MFGPT */
382 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
383 name);
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500384 }
385}
386DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
387
Yinghai Lu65195c72013-04-12 12:44:15 +0000388static void quirk_io_region(struct pci_dev *dev, int port,
389 unsigned size, int nr, const char *name)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390{
Yinghai Lu65195c72013-04-12 12:44:15 +0000391 u16 region;
392 struct pci_bus_region bus_region;
393 struct resource *res = dev->resource + nr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394
Yinghai Lu65195c72013-04-12 12:44:15 +0000395 pci_read_config_word(dev, port, &region);
396 region &= ~(size - 1);
David S. Miller085ae412005-08-08 13:19:08 -0700397
Yinghai Lu65195c72013-04-12 12:44:15 +0000398 if (!region)
399 return;
David S. Miller085ae412005-08-08 13:19:08 -0700400
Yinghai Lu65195c72013-04-12 12:44:15 +0000401 res->name = pci_name(dev);
402 res->flags = IORESOURCE_IO;
403
404 /* Convert from PCI bus to resource space */
405 bus_region.start = region;
406 bus_region.end = region + size - 1;
Yinghai Lufc279852013-12-09 22:54:40 -0800407 pcibios_bus_to_resource(dev->bus, res, &bus_region);
Yinghai Lu65195c72013-04-12 12:44:15 +0000408
409 if (!pci_claim_resource(dev, nr))
410 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
411}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412
413/*
414 * ATI Northbridge setups MCE the processor if you even
415 * read somewhere between 0x3b0->0x3bb or read 0x3d3
416 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500417static void quirk_ati_exploding_mce(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418{
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700419 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
421 request_region(0x3b0, 0x0C, "RadeonIGP");
422 request_region(0x3d3, 0x01, "RadeonIGP");
423}
Andrew Morton652c5382007-11-21 15:07:13 -0800424DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425
426/*
Huang Ruibe6646b2014-10-31 11:11:16 +0800427 * In the AMD NL platform, this device ([1022:7912]) has a class code of
428 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
429 * claim it.
430 * But the dwc3 driver is a more specific driver for this device, and we'd
431 * prefer to use it instead of xhci. To prevent xhci from claiming the
432 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
433 * defines as "USB device (not host controller)". The dwc3 driver can then
434 * claim it based on its Vendor and Device ID.
435 */
436static void quirk_amd_nl_class(struct pci_dev *pdev)
437{
Bjorn Helgaascd76d102015-06-19 15:28:31 -0500438 u32 class = pdev->class;
439
440 /* Use "USB Device (not host controller)" class */
441 pdev->class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe;
442 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
443 class, pdev->class);
Huang Ruibe6646b2014-10-31 11:11:16 +0800444}
445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
446 quirk_amd_nl_class);
447
448/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449 * Let's make the southbridge information explicit instead
450 * of having to worry about people probing the ACPI areas,
451 * for example.. (Yes, it happens, and if you read the wrong
452 * ACPI register it will put the machine to sleep with no
453 * way of waking it up again. Bummer).
454 *
455 * ALI M7101: Two IO regions pointed to by words at
456 * 0xE0 (64 bytes of ACPI registers)
457 * 0xE2 (32 bytes of SMB registers)
458 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500459static void quirk_ali7101_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460{
Yinghai Lu65195c72013-04-12 12:44:15 +0000461 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
462 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700463}
Andrew Morton652c5382007-11-21 15:07:13 -0800464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465
Linus Torvalds6693e742005-10-25 20:40:09 -0700466static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
467{
468 u32 devres;
469 u32 mask, size, base;
470
471 pci_read_config_dword(dev, port, &devres);
472 if ((devres & enable) != enable)
473 return;
474 mask = (devres >> 16) & 15;
475 base = devres & 0xffff;
476 size = 16;
477 for (;;) {
478 unsigned bit = size >> 1;
479 if ((bit & mask) == bit)
480 break;
481 size = bit;
482 }
483 /*
484 * For now we only print it out. Eventually we'll want to
485 * reserve it (at least if it's in the 0x1000+ range), but
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700486 * let's get enough confirmation reports first.
Linus Torvalds6693e742005-10-25 20:40:09 -0700487 */
488 base &= -size;
Ryan Desfosses227f0642014-04-18 20:13:50 -0400489 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
490 base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700491}
492
493static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
494{
495 u32 devres;
496 u32 mask, size, base;
497
498 pci_read_config_dword(dev, port, &devres);
499 if ((devres & enable) != enable)
500 return;
501 base = devres & 0xffff0000;
502 mask = (devres & 0x3f) << 16;
503 size = 128 << 16;
504 for (;;) {
505 unsigned bit = size >> 1;
506 if ((bit & mask) == bit)
507 break;
508 size = bit;
509 }
510 /*
511 * For now we only print it out. Eventually we'll want to
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700512 * reserve it, but let's get enough confirmation reports first.
Linus Torvalds6693e742005-10-25 20:40:09 -0700513 */
514 base &= -size;
Ryan Desfosses227f0642014-04-18 20:13:50 -0400515 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
516 base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700517}
518
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519/*
520 * PIIX4 ACPI: Two IO regions pointed to by longwords at
521 * 0x40 (64 bytes of ACPI registers)
Linus Torvalds08db2a72005-10-30 14:40:07 -0800522 * 0x90 (16 bytes of SMB registers)
Linus Torvalds6693e742005-10-25 20:40:09 -0700523 * and a few strange programmable PIIX4 device resources.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700524 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500525static void quirk_piix4_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526{
Yinghai Lu65195c72013-04-12 12:44:15 +0000527 u32 res_a;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528
Yinghai Lu65195c72013-04-12 12:44:15 +0000529 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
530 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
Linus Torvalds6693e742005-10-25 20:40:09 -0700531
532 /* Device resource A has enables for some of the other ones */
533 pci_read_config_dword(dev, 0x5c, &res_a);
534
535 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
536 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
537
538 /* Device resource D is just bitfields for static resources */
539
540 /* Device 12 enabled? */
541 if (res_a & (1 << 29)) {
542 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
543 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
544 }
545 /* Device 13 enabled? */
546 if (res_a & (1 << 30)) {
547 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
548 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
549 }
550 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
551 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700552}
Andrew Morton652c5382007-11-21 15:07:13 -0800553DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
554DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700555
Jiri Slabycdb97552011-02-28 10:45:09 +0100556#define ICH_PMBASE 0x40
557#define ICH_ACPI_CNTL 0x44
558#define ICH4_ACPI_EN 0x10
559#define ICH6_ACPI_EN 0x80
560#define ICH4_GPIOBASE 0x58
561#define ICH4_GPIO_CNTL 0x5c
562#define ICH4_GPIO_EN 0x10
563#define ICH6_GPIOBASE 0x48
564#define ICH6_GPIO_CNTL 0x4c
565#define ICH6_GPIO_EN 0x10
566
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567/*
568 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
569 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
570 * 0x58 (64 bytes of GPIO I/O space)
571 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500572static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573{
Jiri Slabycdb97552011-02-28 10:45:09 +0100574 u8 enable;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700575
Jiri Slaby87e3dc32011-02-28 10:45:10 +0100576 /*
577 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
578 * with low legacy (and fixed) ports. We don't know the decoding
579 * priority and can't tell whether the legacy device or the one created
580 * here is really at that address. This happens on boards with broken
581 * BIOSes.
582 */
583
Jiri Slabycdb97552011-02-28 10:45:09 +0100584 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
Yinghai Lu65195c72013-04-12 12:44:15 +0000585 if (enable & ICH4_ACPI_EN)
586 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
587 "ICH4 ACPI/GPIO/TCO");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700588
Jiri Slabycdb97552011-02-28 10:45:09 +0100589 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
Yinghai Lu65195c72013-04-12 12:44:15 +0000590 if (enable & ICH4_GPIO_EN)
591 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
592 "ICH4 GPIO");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700593}
Andrew Morton652c5382007-11-21 15:07:13 -0800594DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
595DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
596DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
597DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
598DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
599DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
600DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
601DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
602DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
603DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604
Bill Pemberton15856ad2012-11-21 15:35:00 -0500605static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000606{
Jiri Slabycdb97552011-02-28 10:45:09 +0100607 u8 enable;
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000608
Jiri Slabycdb97552011-02-28 10:45:09 +0100609 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
Yinghai Lu65195c72013-04-12 12:44:15 +0000610 if (enable & ICH6_ACPI_EN)
611 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
612 "ICH6 ACPI/GPIO/TCO");
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000613
Jiri Slabycdb97552011-02-28 10:45:09 +0100614 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
Yinghai Lu65195c72013-04-12 12:44:15 +0000615 if (enable & ICH6_GPIO_EN)
616 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
617 "ICH6 GPIO");
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000618}
Linus Torvalds894886e2008-12-06 10:10:10 -0800619
Bill Pemberton15856ad2012-11-21 15:35:00 -0500620static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
Linus Torvalds894886e2008-12-06 10:10:10 -0800621{
622 u32 val;
623 u32 size, base;
624
625 pci_read_config_dword(dev, reg, &val);
626
627 /* Enabled? */
628 if (!(val & 1))
629 return;
630 base = val & 0xfffc;
631 if (dynsize) {
632 /*
633 * This is not correct. It is 16, 32 or 64 bytes depending on
634 * register D31:F0:ADh bits 5:4.
635 *
636 * But this gets us at least _part_ of it.
637 */
638 size = 16;
639 } else {
640 size = 128;
641 }
642 base &= ~(size-1);
643
644 /* Just print it out for now. We should reserve it after more debugging */
645 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
646}
647
Bill Pemberton15856ad2012-11-21 15:35:00 -0500648static void quirk_ich6_lpc(struct pci_dev *dev)
Linus Torvalds894886e2008-12-06 10:10:10 -0800649{
650 /* Shared ACPI/GPIO decode with all ICH6+ */
651 ich6_lpc_acpi_gpio(dev);
652
653 /* ICH6-specific generic IO decode */
654 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
655 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
656}
657DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
658DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
659
Bill Pemberton15856ad2012-11-21 15:35:00 -0500660static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
Linus Torvalds894886e2008-12-06 10:10:10 -0800661{
662 u32 val;
663 u32 mask, base;
664
665 pci_read_config_dword(dev, reg, &val);
666
667 /* Enabled? */
668 if (!(val & 1))
669 return;
670
671 /*
672 * IO base in bits 15:2, mask in bits 23:18, both
673 * are dword-based
674 */
675 base = val & 0xfffc;
676 mask = (val >> 16) & 0xfc;
677 mask |= 3;
678
679 /* Just print it out for now. We should reserve it after more debugging */
680 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
681}
682
683/* ICH7-10 has the same common LPC generic IO decode registers */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500684static void quirk_ich7_lpc(struct pci_dev *dev)
Linus Torvalds894886e2008-12-06 10:10:10 -0800685{
Jean Delvare5d9c0a72011-04-15 10:03:53 +0200686 /* We share the common ACPI/GPIO decode with ICH6 */
Linus Torvalds894886e2008-12-06 10:10:10 -0800687 ich6_lpc_acpi_gpio(dev);
688
689 /* And have 4 ICH7+ generic decodes */
690 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
691 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
692 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
693 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
694}
695DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
696DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
697DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
698DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
699DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
700DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
701DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
702DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
704DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
705DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
706DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
707DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000708
Linus Torvalds1da177e2005-04-16 15:20:36 -0700709/*
710 * VIA ACPI: One IO region pointed to by longword at
711 * 0x48 or 0x20 (256 bytes of ACPI registers)
712 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500713static void quirk_vt82c586_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700714{
Yinghai Lu65195c72013-04-12 12:44:15 +0000715 if (dev->revision & 0x10)
716 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
717 "vt82c586 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718}
Andrew Morton652c5382007-11-21 15:07:13 -0800719DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720
721/*
722 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
723 * 0x48 (256 bytes of ACPI registers)
724 * 0x70 (128 bytes of hardware monitoring register)
725 * 0x90 (16 bytes of SMB registers)
726 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500727static void quirk_vt82c686_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700728{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729 quirk_vt82c586_acpi(dev);
730
Yinghai Lu65195c72013-04-12 12:44:15 +0000731 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
732 "vt82c686 HW-mon");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700733
Yinghai Lu65195c72013-04-12 12:44:15 +0000734 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700735}
Andrew Morton652c5382007-11-21 15:07:13 -0800736DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700737
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400738/*
739 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
740 * 0x88 (128 bytes of power management registers)
741 * 0xd0 (16 bytes of SMB registers)
742 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500743static void quirk_vt8235_acpi(struct pci_dev *dev)
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400744{
Yinghai Lu65195c72013-04-12 12:44:15 +0000745 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
746 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400747}
748DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
749
Gabe Black1f56f4a2009-10-06 09:19:45 -0500750/*
751 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
752 * Disable fast back-to-back on the secondary bus segment
753 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500754static void quirk_xio2000a(struct pci_dev *dev)
Gabe Black1f56f4a2009-10-06 09:19:45 -0500755{
756 struct pci_dev *pdev;
757 u16 command;
758
Ryan Desfosses227f0642014-04-18 20:13:50 -0400759 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
Gabe Black1f56f4a2009-10-06 09:19:45 -0500760 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
761 pci_read_config_word(pdev, PCI_COMMAND, &command);
762 if (command & PCI_COMMAND_FAST_BACK)
763 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
764 }
765}
766DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
767 quirk_xio2000a);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700768
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700769#ifdef CONFIG_X86_IO_APIC
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770
771#include <asm/io_apic.h>
772
773/*
774 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
775 * devices to the external APIC.
776 *
777 * TODO: When we have device-specific interrupt routers,
778 * this code will go away from quirks.
779 */
Alan Cox1597cac2006-12-04 15:14:45 -0800780static void quirk_via_ioapic(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781{
782 u8 tmp;
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700783
Linus Torvalds1da177e2005-04-16 15:20:36 -0700784 if (nr_ioapics < 1)
785 tmp = 0; /* nothing routed to external APIC */
786 else
787 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700788
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700789 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790 tmp == 0 ? "Disa" : "Ena");
791
792 /* Offset 0x58: External APIC IRQ output control */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400793 pci_write_config_byte(dev, 0x58, tmp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794}
Andrew Morton652c5382007-11-21 15:07:13 -0800795DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200796DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797
798/*
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700799 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
Karsten Wiesea1740912005-09-03 15:56:33 -0700800 * This leads to doubled level interrupt rates.
801 * Set this bit to get rid of cycle wastage.
802 * Otherwise uncritical.
803 */
Alan Cox1597cac2006-12-04 15:14:45 -0800804static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
Karsten Wiesea1740912005-09-03 15:56:33 -0700805{
806 u8 misc_control2;
807#define BYPASS_APIC_DEASSERT 8
808
809 pci_read_config_byte(dev, 0x5B, &misc_control2);
810 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700811 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
Karsten Wiesea1740912005-09-03 15:56:33 -0700812 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
813 }
814}
815DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200816DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Karsten Wiesea1740912005-09-03 15:56:33 -0700817
818/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819 * The AMD io apic can hang the box when an apic irq is masked.
820 * We check all revs >= B0 (yet not in the pre production!) as the bug
821 * is currently marked NoFix
822 *
823 * We have multiple reports of hangs with this chipset that went away with
Alan Cox236561e2006-09-30 23:27:03 -0700824 * noapic specified. For the moment we assume it's the erratum. We may be wrong
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825 * of course. However the advice is demonstrably good even if so..
826 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500827static void quirk_amd_ioapic(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700828{
Auke Kok44c10132007-06-08 15:46:36 -0700829 if (dev->revision >= 0x02) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700830 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
831 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700832 }
833}
Andrew Morton652c5382007-11-21 15:07:13 -0800834DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835#endif /* CONFIG_X86_IO_APIC */
836
Peter Orubad556ad42007-05-15 13:59:13 +0200837/*
838 * Some settings of MMRBC can lead to data corruption so block changes.
839 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
840 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500841static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
Peter Orubad556ad42007-05-15 13:59:13 +0200842{
Auke Kokaa288d42007-08-27 16:17:47 -0700843 if (dev->subordinate && dev->revision <= 0x12) {
Ryan Desfosses227f0642014-04-18 20:13:50 -0400844 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
845 dev->revision);
Peter Orubad556ad42007-05-15 13:59:13 +0200846 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
847 }
848}
849DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850
851/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852 * FIXME: it is questionable that quirk_via_acpi
853 * is needed. It shows up as an ISA bridge, and does not
854 * support the PCI_INTERRUPT_LINE register at all. Therefore
855 * it seems like setting the pci_dev's 'irq' to the
856 * value of the ACPI SCI interrupt is only done for convenience.
857 * -jgarzik
858 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500859static void quirk_via_acpi(struct pci_dev *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860{
861 /*
862 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
863 */
864 u8 irq;
865 pci_read_config_byte(d, 0x42, &irq);
866 irq &= 0xf;
867 if (irq && (irq != 2))
868 d->irq = irq;
869}
Andrew Morton652c5382007-11-21 15:07:13 -0800870DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
871DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700872
Daniel Drake09d60292006-09-25 16:52:19 -0700873
874/*
Alan Cox1597cac2006-12-04 15:14:45 -0800875 * VIA bridges which have VLink
Daniel Drake09d60292006-09-25 16:52:19 -0700876 */
Alan Cox1597cac2006-12-04 15:14:45 -0800877
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800878static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
879
880static void quirk_via_bridge(struct pci_dev *dev)
881{
882 /* See what bridge we have and find the device ranges */
883 switch (dev->device) {
884 case PCI_DEVICE_ID_VIA_82C686:
Jean Delvarecb7468e2007-01-31 23:48:12 -0800885 /* The VT82C686 is special, it attaches to PCI and can have
886 any device number. All its subdevices are functions of
887 that single device. */
888 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
889 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800890 break;
891 case PCI_DEVICE_ID_VIA_8237:
892 case PCI_DEVICE_ID_VIA_8237A:
893 via_vlink_dev_lo = 15;
894 break;
895 case PCI_DEVICE_ID_VIA_8235:
896 via_vlink_dev_lo = 16;
897 break;
898 case PCI_DEVICE_ID_VIA_8231:
899 case PCI_DEVICE_ID_VIA_8233_0:
900 case PCI_DEVICE_ID_VIA_8233A:
901 case PCI_DEVICE_ID_VIA_8233C_0:
902 via_vlink_dev_lo = 17;
903 break;
904 }
905}
906DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
907DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
908DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
909DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
910DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
911DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
912DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
913DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
Daniel Drake09d60292006-09-25 16:52:19 -0700914
Alan Cox1597cac2006-12-04 15:14:45 -0800915/**
916 * quirk_via_vlink - VIA VLink IRQ number update
917 * @dev: PCI device
918 *
919 * If the device we are dealing with is on a PIC IRQ we need to
920 * ensure that the IRQ line register which usually is not relevant
921 * for PCI cards, is actually written so that interrupts get sent
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800922 * to the right place.
923 * We only do this on systems where a VIA south bridge was detected,
924 * and only for VIA devices on the motherboard (see quirk_via_bridge
925 * above).
Alan Cox1597cac2006-12-04 15:14:45 -0800926 */
927
928static void quirk_via_vlink(struct pci_dev *dev)
Len Brown25be5e62005-05-27 04:21:50 -0400929{
930 u8 irq, new_irq;
931
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800932 /* Check if we have VLink at all */
933 if (via_vlink_dev_lo == -1)
Daniel Drake09d60292006-09-25 16:52:19 -0700934 return;
935
936 new_irq = dev->irq;
937
938 /* Don't quirk interrupts outside the legacy IRQ range */
939 if (!new_irq || new_irq > 15)
940 return;
941
Alan Cox1597cac2006-12-04 15:14:45 -0800942 /* Internal device ? */
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800943 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
944 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
Alan Cox1597cac2006-12-04 15:14:45 -0800945 return;
946
947 /* This is an internal VLink device on a PIC interrupt. The BIOS
948 ought to have set this but may not have, so we redo it */
949
Len Brown25be5e62005-05-27 04:21:50 -0400950 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
951 if (new_irq != irq) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700952 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
953 irq, new_irq);
Len Brown25be5e62005-05-27 04:21:50 -0400954 udelay(15); /* unknown if delay really needed */
955 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
956 }
957}
Alan Cox1597cac2006-12-04 15:14:45 -0800958DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
Len Brown25be5e62005-05-27 04:21:50 -0400959
Linus Torvalds1da177e2005-04-16 15:20:36 -0700960/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700961 * VIA VT82C598 has its device ID settable and many BIOSes
962 * set it to the ID of VT82C597 for backward compatibility.
963 * We need to switch it off to be able to recognize the real
964 * type of the chip.
965 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500966static void quirk_vt82c598_id(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700967{
968 pci_write_config_byte(dev, 0xfc, 0);
969 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
970}
Andrew Morton652c5382007-11-21 15:07:13 -0800971DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700972
973/*
974 * CardBus controllers have a legacy base address that enables them
975 * to respond as i82365 pcmcia controllers. We don't want them to
976 * do this even if the Linux CardBus driver is not loaded, because
977 * the Linux i82365 driver does not (and should not) handle CardBus.
978 */
Alan Cox1597cac2006-12-04 15:14:45 -0800979static void quirk_cardbus_legacy(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700980{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700981 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
982}
Yinghai Luae9de562012-02-23 23:46:54 -0800983DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
984 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
985DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
986 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700987
988/*
989 * Following the PCI ordering rules is optional on the AMD762. I'm not
990 * sure what the designers were smoking but let's not inhale...
991 *
992 * To be fair to AMD, it follows the spec by default, its BIOS people
993 * who turn it off!
994 */
Alan Cox1597cac2006-12-04 15:14:45 -0800995static void quirk_amd_ordering(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700996{
997 u32 pcic;
998 pci_read_config_dword(dev, 0x4C, &pcic);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400999 if ((pcic & 6) != 6) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001000 pcic |= 6;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001001 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001002 pci_write_config_dword(dev, 0x4C, pcic);
1003 pci_read_config_dword(dev, 0x84, &pcic);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001004 pcic |= (1 << 23); /* Required in this mode */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001005 pci_write_config_dword(dev, 0x84, pcic);
1006 }
1007}
Andrew Morton652c5382007-11-21 15:07:13 -08001008DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001009DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001010
1011/*
1012 * DreamWorks provided workaround for Dunord I-3000 problem
1013 *
1014 * This card decodes and responds to addresses not apparently
1015 * assigned to it. We force a larger allocation to ensure that
1016 * nothing gets put too close to it.
1017 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001018static void quirk_dunord(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001019{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001020 struct resource *r = &dev->resource[1];
Bjorn Helgaasbd064f02014-02-26 11:25:58 -07001021
1022 r->flags |= IORESOURCE_UNSET;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001023 r->start = 0;
1024 r->end = 0xffffff;
1025}
Andrew Morton652c5382007-11-21 15:07:13 -08001026DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001027
1028/*
1029 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1030 * is subtractive decoding (transparent), and does indicate this
1031 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1032 * instead of 0x01.
1033 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001034static void quirk_transparent_bridge(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001035{
1036 dev->transparent = 1;
1037}
Andrew Morton652c5382007-11-21 15:07:13 -08001038DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1039DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001040
1041/*
1042 * Common misconfiguration of the MediaGX/Geode PCI master that will
1043 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
Justin P. Mattock631dd1a2010-10-18 11:03:14 +02001044 * datasheets found at http://www.national.com/analog for info on what
Linus Torvalds1da177e2005-04-16 15:20:36 -07001045 * these bits do. <christer@weinigel.se>
1046 */
Alan Cox1597cac2006-12-04 15:14:45 -08001047static void quirk_mediagx_master(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001048{
1049 u8 reg;
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001050
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051 pci_read_config_byte(dev, 0x41, &reg);
1052 if (reg & 2) {
1053 reg &= ~2;
Ryan Desfosses227f0642014-04-18 20:13:50 -04001054 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1055 reg);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001056 pci_write_config_byte(dev, 0x41, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001057 }
1058}
Andrew Morton652c5382007-11-21 15:07:13 -08001059DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1060DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001061
1062/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001063 * Ensure C0 rev restreaming is off. This is normally done by
1064 * the BIOS but in the odd case it is not the results are corruption
1065 * hence the presence of a Linux check
1066 */
Alan Cox1597cac2006-12-04 15:14:45 -08001067static void quirk_disable_pxb(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001068{
1069 u16 config;
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001070
Auke Kok44c10132007-06-08 15:46:36 -07001071 if (pdev->revision != 0x04) /* Only C0 requires this */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001072 return;
1073 pci_read_config_word(pdev, 0x40, &config);
1074 if (config & (1<<6)) {
1075 config &= ~(1<<6);
1076 pci_write_config_word(pdev, 0x40, config);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001077 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001078 }
1079}
Andrew Morton652c5382007-11-21 15:07:13 -08001080DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001081DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001082
Myron Stowe25e742b2012-07-09 15:36:14 -06001083static void quirk_amd_ide_mode(struct pci_dev *pdev)
Conke Huab174432006-12-19 13:11:37 -08001084{
Shane Huang5deab532009-10-13 11:14:00 +08001085 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
Crane Cai05a7d222008-02-02 13:56:56 +08001086 u8 tmp;
Conke Huab174432006-12-19 13:11:37 -08001087
Crane Cai05a7d222008-02-02 13:56:56 +08001088 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1089 if (tmp == 0x01) {
Conke Huab174432006-12-19 13:11:37 -08001090 pci_read_config_byte(pdev, 0x40, &tmp);
1091 pci_write_config_byte(pdev, 0x40, tmp|1);
1092 pci_write_config_byte(pdev, 0x9, 1);
1093 pci_write_config_byte(pdev, 0xa, 6);
1094 pci_write_config_byte(pdev, 0x40, tmp);
1095
Conke Huc9f89472007-01-09 05:32:51 -05001096 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
Crane Cai05a7d222008-02-02 13:56:56 +08001097 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
Conke Huab174432006-12-19 13:11:37 -08001098 }
1099}
Crane Cai05a7d222008-02-02 13:56:56 +08001100DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001101DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Crane Cai05a7d222008-02-02 13:56:56 +08001102DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001103DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Shane Huang5deab532009-10-13 11:14:00 +08001104DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1105DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
Shane Huangfafe5c3d82013-06-03 18:24:10 +08001106DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1107DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
Conke Huab174432006-12-19 13:11:37 -08001108
Linus Torvalds1da177e2005-04-16 15:20:36 -07001109/*
1110 * Serverworks CSB5 IDE does not fully support native mode
1111 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001112static void quirk_svwks_csb5ide(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113{
1114 u8 prog;
1115 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1116 if (prog & 5) {
1117 prog &= ~5;
1118 pdev->class &= ~5;
1119 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Alan Cox368c73d2006-10-04 00:41:26 +01001120 /* PCI layer will sort out resources */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001121 }
1122}
Andrew Morton652c5382007-11-21 15:07:13 -08001123DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001124
1125/*
1126 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1127 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001128static void quirk_ide_samemode(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001129{
1130 u8 prog;
1131
1132 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1133
1134 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001135 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001136 prog &= ~5;
1137 pdev->class &= ~5;
1138 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001139 }
1140}
Alan Cox368c73d2006-10-04 00:41:26 +01001141DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142
Alan Cox979b1792008-07-24 17:18:38 +01001143/*
1144 * Some ATA devices break if put into D3
1145 */
1146
Bill Pemberton15856ad2012-11-21 15:35:00 -05001147static void quirk_no_ata_d3(struct pci_dev *pdev)
Alan Cox979b1792008-07-24 17:18:38 +01001148{
Yinghai Lufaa738b2012-02-23 23:46:55 -08001149 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
Alan Cox979b1792008-07-24 17:18:38 +01001150}
Yinghai Lufaa738b2012-02-23 23:46:55 -08001151/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1152DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1153 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1154DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1155 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
Alan Cox7a661c62009-06-24 16:02:27 +01001156/* ALi loses some register settings that we cannot then restore */
Yinghai Lufaa738b2012-02-23 23:46:55 -08001157DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1158 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
Alan Cox7a661c62009-06-24 16:02:27 +01001159/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1160 occur when mode detecting */
Yinghai Lufaa738b2012-02-23 23:46:55 -08001161DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1162 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
Alan Cox979b1792008-07-24 17:18:38 +01001163
Linus Torvalds1da177e2005-04-16 15:20:36 -07001164/* This was originally an Alpha specific thing, but it really fits here.
1165 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1166 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001167static void quirk_eisa_bridge(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001168{
1169 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1170}
Andrew Morton652c5382007-11-21 15:07:13 -08001171DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001172
Johannes Goecke7daa0c42006-04-20 02:43:17 -07001173
1174/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001175 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1176 * is not activated. The myth is that Asus said that they do not want the
1177 * users to be irritated by just another PCI Device in the Win98 device
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001178 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
Linus Torvalds1da177e2005-04-16 15:20:36 -07001179 * package 2.7.0 for details)
1180 *
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001181 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1182 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001183 * becomes necessary to do this tweak in two steps -- the chosen trigger
1184 * is either the Host bridge (preferred) or on-board VGA controller.
Jean Delvare9208ee82007-03-24 16:56:44 +01001185 *
1186 * Note that we used to unhide the SMBus that way on Toshiba laptops
1187 * (Satellite A40 and Tecra M2) but then found that the thermal management
1188 * was done by SMM code, which could cause unsynchronized concurrent
1189 * accesses to the SMBus registers, with potentially bad effects. Thus you
1190 * should be very careful when adding new entries: if SMM is accessing the
1191 * Intel SMBus, this is a very good reason to leave it hidden.
Jean Delvarea99acc82008-03-28 14:16:04 -07001192 *
1193 * Likewise, many recent laptops use ACPI for thermal management. If the
1194 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1195 * natively, and keeping the SMBus hidden is the right thing to do. If you
1196 * are about to add an entry in the table below, please first disassemble
1197 * the DSDT and double-check that there is no code accessing the SMBus.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001198 */
Vivek Goyal9d24a812007-01-11 01:52:44 +01001199static int asus_hides_smbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001200
Bill Pemberton15856ad2012-11-21 15:35:00 -05001201static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001202{
1203 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1204 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001205 switch (dev->subsystem_device) {
Jean Delvarea00db372005-06-29 17:04:06 +02001206 case 0x8025: /* P4B-LX */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001207 case 0x8070: /* P4B */
1208 case 0x8088: /* P4B533 */
1209 case 0x1626: /* L3C notebook */
1210 asus_hides_smbus = 1;
1211 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001212 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001213 switch (dev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001214 case 0x80b1: /* P4GE-V */
1215 case 0x80b2: /* P4PE */
1216 case 0x8093: /* P4B533-V */
1217 asus_hides_smbus = 1;
1218 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001219 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001220 switch (dev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001221 case 0x8030: /* P4T533 */
1222 asus_hides_smbus = 1;
1223 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001224 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001225 switch (dev->subsystem_device) {
1226 case 0x8070: /* P4G8X Deluxe */
1227 asus_hides_smbus = 1;
1228 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001229 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
Jean Delvare321311a2006-07-31 08:53:15 +02001230 switch (dev->subsystem_device) {
1231 case 0x80c9: /* PU-DLS */
1232 asus_hides_smbus = 1;
1233 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001234 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001235 switch (dev->subsystem_device) {
1236 case 0x1751: /* M2N notebook */
1237 case 0x1821: /* M5N notebook */
Mats Erik Andersson4096ed02009-05-12 12:05:23 +02001238 case 0x1897: /* A6L notebook */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001239 asus_hides_smbus = 1;
1240 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001241 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001242 switch (dev->subsystem_device) {
1243 case 0x184b: /* W1N notebook */
1244 case 0x186a: /* M6Ne notebook */
1245 asus_hides_smbus = 1;
1246 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001247 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Jean Delvare2e457852007-01-05 09:17:56 +01001248 switch (dev->subsystem_device) {
1249 case 0x80f2: /* P4P800-X */
1250 asus_hides_smbus = 1;
1251 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001252 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001253 switch (dev->subsystem_device) {
1254 case 0x1882: /* M6V notebook */
Jean Delvare2d1e1c72006-04-01 16:46:35 +02001255 case 0x1977: /* A6VA notebook */
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001256 asus_hides_smbus = 1;
1257 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001258 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1259 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001260 switch (dev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001261 case 0x088C: /* HP Compaq nc8000 */
1262 case 0x0890: /* HP Compaq nc6000 */
1263 asus_hides_smbus = 1;
1264 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001265 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001266 switch (dev->subsystem_device) {
1267 case 0x12bc: /* HP D330L */
Jean Delvaree3b1bd52005-09-21 22:26:31 +02001268 case 0x12bd: /* HP D530 */
Michal Miroslaw74c57422009-05-12 13:49:25 -07001269 case 0x006a: /* HP Compaq nx9500 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001270 asus_hides_smbus = 1;
1271 }
Jean Delvare677cc642007-11-21 18:29:06 +01001272 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1273 switch (dev->subsystem_device) {
1274 case 0x12bf: /* HP xw4100 */
1275 asus_hides_smbus = 1;
1276 }
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001277 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1278 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1279 switch (dev->subsystem_device) {
1280 case 0xC00C: /* Samsung P35 notebook */
1281 asus_hides_smbus = 1;
1282 }
Rumen Ivanov Zarevc87f8832005-09-06 13:39:32 -07001283 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1284 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001285 switch (dev->subsystem_device) {
Rumen Ivanov Zarevc87f8832005-09-06 13:39:32 -07001286 case 0x0058: /* Compaq Evo N620c */
1287 asus_hides_smbus = 1;
1288 }
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001289 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001290 switch (dev->subsystem_device) {
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001291 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1292 /* Motherboard doesn't have Host bridge
1293 * subvendor/subdevice IDs, therefore checking
1294 * its on-board VGA controller */
1295 asus_hides_smbus = 1;
1296 }
David O'Shea8293b0f2009-03-02 09:51:13 +01001297 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001298 switch (dev->subsystem_device) {
Jean Delvare10260d92008-06-04 13:53:31 +02001299 case 0x00b8: /* Compaq Evo D510 CMT */
1300 case 0x00b9: /* Compaq Evo D510 SFF */
Jean Delvare6b5096e2009-07-28 11:49:19 +02001301 case 0x00ba: /* Compaq Evo D510 USDT */
David O'Shea8293b0f2009-03-02 09:51:13 +01001302 /* Motherboard doesn't have Host bridge
1303 * subvendor/subdevice IDs and on-board VGA
1304 * controller is disabled if an AGP card is
1305 * inserted, therefore checking USB UHCI
1306 * Controller #1 */
Jean Delvare10260d92008-06-04 13:53:31 +02001307 asus_hides_smbus = 1;
1308 }
Krzysztof Helt27e46852008-06-08 13:47:02 +02001309 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1310 switch (dev->subsystem_device) {
1311 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1312 /* Motherboard doesn't have host bridge
1313 * subvendor/subdevice IDs, therefore checking
1314 * its on-board VGA controller */
1315 asus_hides_smbus = 1;
1316 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001317 }
1318}
Andrew Morton652c5382007-11-21 15:07:13 -08001319DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1322DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
Jean Delvare677cc642007-11-21 18:29:06 +01001323DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
Andrew Morton652c5382007-11-21 15:07:13 -08001324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1326DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1327DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1328DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001329
Andrew Morton652c5382007-11-21 15:07:13 -08001330DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
David O'Shea8293b0f2009-03-02 09:51:13 +01001331DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
Krzysztof Helt27e46852008-06-08 13:47:02 +02001332DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001333
Alan Cox1597cac2006-12-04 15:14:45 -08001334static void asus_hides_smbus_lpc(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001335{
1336 u16 val;
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001337
Linus Torvalds1da177e2005-04-16 15:20:36 -07001338 if (likely(!asus_hides_smbus))
1339 return;
1340
1341 pci_read_config_word(dev, 0xF2, &val);
1342 if (val & 0x8) {
1343 pci_write_config_word(dev, 0xF2, val & (~0x8));
1344 pci_read_config_word(dev, 0xF2, &val);
1345 if (val & 0x8)
Ryan Desfosses227f0642014-04-18 20:13:50 -04001346 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1347 val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001348 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001349 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001350 }
1351}
Andrew Morton652c5382007-11-21 15:07:13 -08001352DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1353DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1354DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1355DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1356DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1357DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1358DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001359DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1360DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1361DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1362DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1363DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1364DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1365DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001366
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001367/* It appears we just have one such device. If not, we have a warning */
1368static void __iomem *asus_rcba_base;
1369static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001370{
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001371 u32 rcba;
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001372
1373 if (likely(!asus_hides_smbus))
1374 return;
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001375 WARN_ON(asus_rcba_base);
1376
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001377 pci_read_config_dword(dev, 0xF0, &rcba);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001378 /* use bits 31:14, 16 kB aligned */
1379 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1380 if (asus_rcba_base == NULL)
1381 return;
1382}
1383
1384static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1385{
1386 u32 val;
1387
1388 if (likely(!asus_hides_smbus || !asus_rcba_base))
1389 return;
1390 /* read the Function Disable register, dword mode only */
1391 val = readl(asus_rcba_base + 0x3418);
1392 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1393}
1394
1395static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1396{
1397 if (likely(!asus_hides_smbus || !asus_rcba_base))
1398 return;
1399 iounmap(asus_rcba_base);
1400 asus_rcba_base = NULL;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001401 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001402}
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001403
1404static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1405{
1406 asus_hides_smbus_lpc_ich6_suspend(dev);
1407 asus_hides_smbus_lpc_ich6_resume_early(dev);
1408 asus_hides_smbus_lpc_ich6_resume(dev);
1409}
Andrew Morton652c5382007-11-21 15:07:13 -08001410DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001411DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1412DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1413DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
Carl-Daniel Hailfingerce007ea2006-05-15 09:44:33 -07001414
Linus Torvalds1da177e2005-04-16 15:20:36 -07001415/*
1416 * SiS 96x south bridge: BIOS typically hides SMBus device...
1417 */
Alan Cox1597cac2006-12-04 15:14:45 -08001418static void quirk_sis_96x_smbus(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001419{
1420 u8 val = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001421 pci_read_config_byte(dev, 0x77, &val);
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001422 if (val & 0x10) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001423 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001424 pci_write_config_byte(dev, 0x77, val & ~0x10);
1425 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001426}
Andrew Morton652c5382007-11-21 15:07:13 -08001427DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1428DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1429DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1430DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001431DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1432DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1433DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1434DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001435
Linus Torvalds1da177e2005-04-16 15:20:36 -07001436/*
1437 * ... This is further complicated by the fact that some SiS96x south
1438 * bridges pretend to be 85C503/5513 instead. In that case see if we
1439 * spotted a compatible north bridge to make sure.
1440 * (pci_find_device doesn't work yet)
1441 *
1442 * We can also enable the sis96x bit in the discovery register..
1443 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001444#define SIS_DETECT_REGISTER 0x40
1445
Alan Cox1597cac2006-12-04 15:14:45 -08001446static void quirk_sis_503(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001447{
1448 u8 reg;
1449 u16 devid;
1450
1451 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1452 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1453 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1454 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1455 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1456 return;
1457 }
1458
Linus Torvalds1da177e2005-04-16 15:20:36 -07001459 /*
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001460 * Ok, it now shows up as a 96x.. run the 96x quirk by
1461 * hand in case it has already been processed.
1462 * (depends on link order, which is apparently not guaranteed)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001463 */
1464 dev->device = devid;
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001465 quirk_sis_96x_smbus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001466}
Andrew Morton652c5382007-11-21 15:07:13 -08001467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001468DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001469
Linus Torvalds1da177e2005-04-16 15:20:36 -07001470
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001471/*
1472 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1473 * and MC97 modem controller are disabled when a second PCI soundcard is
1474 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1475 * -- bjd
1476 */
Alan Cox1597cac2006-12-04 15:14:45 -08001477static void asus_hides_ac97_lpc(struct pci_dev *dev)
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001478{
1479 u8 val;
1480 int asus_hides_ac97 = 0;
1481
1482 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1483 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1484 asus_hides_ac97 = 1;
1485 }
1486
1487 if (!asus_hides_ac97)
1488 return;
1489
1490 pci_read_config_byte(dev, 0x50, &val);
1491 if (val & 0xc0) {
1492 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1493 pci_read_config_byte(dev, 0x50, &val);
1494 if (val & 0xc0)
Ryan Desfosses227f0642014-04-18 20:13:50 -04001495 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1496 val);
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001497 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001498 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001499 }
1500}
Andrew Morton652c5382007-11-21 15:07:13 -08001501DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001502DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Alan Cox1597cac2006-12-04 15:14:45 -08001503
Tejun Heo77967052006-08-19 03:54:39 +09001504#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
Alan Cox15e0c692006-07-12 15:05:41 +01001505
1506/*
1507 * If we are using libata we can drive this chip properly but must
1508 * do this early on to make the additional device appear during
1509 * the PCI scanning.
1510 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001511static void quirk_jmicron_ata(struct pci_dev *pdev)
Alan Cox15e0c692006-07-12 15:05:41 +01001512{
Tejun Heoe34bb372007-02-26 20:24:03 +09001513 u32 conf1, conf5, class;
Alan Cox15e0c692006-07-12 15:05:41 +01001514 u8 hdr;
1515
1516 /* Only poke fn 0 */
1517 if (PCI_FUNC(pdev->devfn))
1518 return;
1519
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001520 pci_read_config_dword(pdev, 0x40, &conf1);
1521 pci_read_config_dword(pdev, 0x80, &conf5);
Alan Cox15e0c692006-07-12 15:05:41 +01001522
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001523 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1524 conf5 &= ~(1 << 24); /* Clear bit 24 */
Alan Cox15e0c692006-07-12 15:05:41 +01001525
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001526 switch (pdev->device) {
Tejun Heo4daedcf2010-06-03 11:57:04 +02001527 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1528 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001529 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001530 /* The controller should be in single function ahci mode */
1531 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1532 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001533
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001534 case PCI_DEVICE_ID_JMICRON_JMB365:
1535 case PCI_DEVICE_ID_JMICRON_JMB366:
1536 /* Redirect IDE second PATA port to the right spot */
1537 conf5 |= (1 << 24);
1538 /* Fall through */
1539 case PCI_DEVICE_ID_JMICRON_JMB361:
1540 case PCI_DEVICE_ID_JMICRON_JMB363:
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001541 case PCI_DEVICE_ID_JMICRON_JMB369:
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001542 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1543 /* Set the class codes correctly and then direct IDE 0 */
Tejun Heo3a9e3a52007-10-23 15:27:31 +09001544 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001545 break;
1546
1547 case PCI_DEVICE_ID_JMICRON_JMB368:
1548 /* The controller should be in single function IDE mode */
1549 conf1 |= 0x00C00000; /* Set 22, 23 */
1550 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001551 }
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001552
1553 pci_write_config_dword(pdev, 0x40, conf1);
1554 pci_write_config_dword(pdev, 0x80, conf5);
1555
1556 /* Update pdev accordingly */
1557 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1558 pdev->hdr_type = hdr & 0x7f;
1559 pdev->multifunction = !!(hdr & 0x80);
Tejun Heoe34bb372007-02-26 20:24:03 +09001560
1561 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1562 pdev->class = class >> 8;
Alan Cox15e0c692006-07-12 15:05:41 +01001563}
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001564DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1565DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
Tejun Heo4daedcf2010-06-03 11:57:04 +02001566DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001567DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001568DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001569DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1570DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1571DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001572DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001573DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1574DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
Tejun Heo4daedcf2010-06-03 11:57:04 +02001575DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001576DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001577DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001578DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1579DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1580DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001581DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
Alan Cox15e0c692006-07-12 15:05:41 +01001582
1583#endif
1584
Zhang Rui91f15fb2015-08-24 15:27:11 -05001585static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1586{
1587 if (dev->multifunction) {
1588 device_disable_async_suspend(&dev->dev);
1589 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1590 }
1591}
1592DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1593DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1594DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1595DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1596
Linus Torvalds1da177e2005-04-16 15:20:36 -07001597#ifdef CONFIG_X86_IO_APIC
Bill Pemberton15856ad2012-11-21 15:35:00 -05001598static void quirk_alder_ioapic(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001599{
1600 int i;
1601
1602 if ((pdev->class >> 8) != 0xff00)
1603 return;
1604
1605 /* the first BAR is the location of the IO APIC...we must
1606 * not touch this (and it's already covered by the fixmap), so
1607 * forcibly insert it into the resource tree */
1608 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1609 insert_resource(&iomem_resource, &pdev->resource[0]);
1610
1611 /* The next five BARs all seem to be rubbish, so just clean
1612 * them out */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001613 for (i = 1; i < 6; i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001614 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001615}
Andrew Morton652c5382007-11-21 15:07:13 -08001616DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001617#endif
1618
Bill Pemberton15856ad2012-11-21 15:35:00 -05001619static void quirk_pcie_mch(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001620{
Eric W. Biederman0ba379e2009-09-06 21:48:35 -07001621 pdev->no_msi = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001622}
Andrew Morton652c5382007-11-21 15:07:13 -08001623DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1624DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1625DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001626
Kristen Accardi4602b882005-08-16 15:15:58 -07001627
1628/*
1629 * It's possible for the MSI to get corrupted if shpc and acpi
1630 * are used together on certain PXH-based systems.
1631 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001632static void quirk_pcie_pxh(struct pci_dev *dev)
Kristen Accardi4602b882005-08-16 15:15:58 -07001633{
Kristen Accardi4602b882005-08-16 15:15:58 -07001634 dev->no_msi = 1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001635 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
Kristen Accardi4602b882005-08-16 15:15:58 -07001636}
1637DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1638DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1639DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1640DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1641DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1642
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -07001643/*
1644 * Some Intel PCI Express chipsets have trouble with downstream
1645 * device power management.
1646 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001647static void quirk_intel_pcie_pm(struct pci_dev *dev)
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -07001648{
1649 pci_pm_d3_delay = 120;
1650 dev->no_d1d2 = 1;
1651}
1652
1653DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1654DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1655DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1656DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1657DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1658DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1659DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1660DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1661DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1662DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1663DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1664DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1665DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1667DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1668DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1669DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1670DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1671DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1672DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1673DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
Kristen Accardi4602b882005-08-16 15:15:58 -07001674
Stefan Assmann426b3b82008-06-11 16:35:16 +02001675#ifdef CONFIG_X86_IO_APIC
1676/*
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001677 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1678 * remap the original interrupt in the linux kernel to the boot interrupt, so
1679 * that a PCI device's interrupt handler is installed on the boot interrupt
1680 * line instead.
1681 */
1682static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1683{
Stefan Assmann41b9eb22008-07-15 13:48:55 +02001684 if (noioapicquirk || noioapicreroute)
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001685 return;
1686
1687 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001688 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1689 dev->vendor, dev->device);
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001690}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001691DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1692DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1693DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1694DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1695DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1696DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1697DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1698DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1699DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1700DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1701DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1702DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1703DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1704DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1705DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1706DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001707
1708/*
Stefan Assmann426b3b82008-06-11 16:35:16 +02001709 * On some chipsets we can disable the generation of legacy INTx boot
1710 * interrupts.
1711 */
1712
1713/*
1714 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1715 * 300641-004US, section 5.7.3.
1716 */
1717#define INTEL_6300_IOAPIC_ABAR 0x40
1718#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1719
1720static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1721{
1722 u16 pci_config_word;
1723
1724 if (noioapicquirk)
1725 return;
1726
1727 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1728 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1729 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1730
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001731 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1732 dev->vendor, dev->device);
Stefan Assmann426b3b82008-06-11 16:35:16 +02001733}
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001734DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1735DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
Olaf Dabrunz77251182008-07-08 15:59:47 +02001736
1737/*
1738 * disable boot interrupts on HT-1000
1739 */
1740#define BC_HT1000_FEATURE_REG 0x64
1741#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1742#define BC_HT1000_MAP_IDX 0xC00
1743#define BC_HT1000_MAP_DATA 0xC01
1744
1745static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1746{
1747 u32 pci_config_dword;
1748 u8 irq;
1749
1750 if (noioapicquirk)
1751 return;
1752
1753 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1754 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1755 BC_HT1000_PIC_REGS_ENABLE);
1756
1757 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1758 outb(irq, BC_HT1000_MAP_IDX);
1759 outb(0x00, BC_HT1000_MAP_DATA);
1760 }
1761
1762 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1763
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001764 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1765 dev->vendor, dev->device);
Olaf Dabrunz77251182008-07-08 15:59:47 +02001766}
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001767DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1768DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001769
1770/*
1771 * disable boot interrupts on AMD and ATI chipsets
1772 */
1773/*
1774 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1775 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1776 * (due to an erratum).
1777 */
1778#define AMD_813X_MISC 0x40
1779#define AMD_813X_NOIOAMODE (1<<0)
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001780#define AMD_813X_REV_B1 0x12
Stefan Assmannbbe19442009-02-26 10:46:48 -08001781#define AMD_813X_REV_B2 0x13
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001782
1783static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1784{
1785 u32 pci_config_dword;
1786
1787 if (noioapicquirk)
1788 return;
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001789 if ((dev->revision == AMD_813X_REV_B1) ||
1790 (dev->revision == AMD_813X_REV_B2))
Stefan Assmannbbe19442009-02-26 10:46:48 -08001791 return;
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001792
1793 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1794 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1795 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1796
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001797 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1798 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001799}
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001800DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1801DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1802DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1803DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001804
1805#define AMD_8111_PCI_IRQ_ROUTING 0x56
1806
1807static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1808{
1809 u16 pci_config_word;
1810
1811 if (noioapicquirk)
1812 return;
1813
1814 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1815 if (!pci_config_word) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04001816 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1817 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001818 return;
1819 }
1820 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001821 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1822 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001823}
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001824DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1825DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
Stefan Assmann426b3b82008-06-11 16:35:16 +02001826#endif /* CONFIG_X86_IO_APIC */
1827
Sergei Shtylyov33dced22007-02-07 18:18:45 +01001828/*
1829 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1830 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1831 * Re-allocate the region if needed...
1832 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001833static void quirk_tc86c001_ide(struct pci_dev *dev)
Sergei Shtylyov33dced22007-02-07 18:18:45 +01001834{
1835 struct resource *r = &dev->resource[0];
1836
1837 if (r->start & 0x8) {
Bjorn Helgaasbd064f02014-02-26 11:25:58 -07001838 r->flags |= IORESOURCE_UNSET;
Sergei Shtylyov33dced22007-02-07 18:18:45 +01001839 r->start = 0;
1840 r->end = 0xf;
1841 }
1842}
1843DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1844 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1845 quirk_tc86c001_ide);
1846
Ian Abbott21c5fd92012-10-30 17:25:53 +00001847/*
1848 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1849 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1850 * being read correctly if bit 7 of the base address is set.
1851 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1852 * Re-allocate the regions to a 256-byte boundary if necessary.
1853 */
Linus Torvalds193c0d62012-12-13 12:14:47 -08001854static void quirk_plx_pci9050(struct pci_dev *dev)
Ian Abbott21c5fd92012-10-30 17:25:53 +00001855{
1856 unsigned int bar;
1857
1858 /* Fixed in revision 2 (PCI 9052). */
1859 if (dev->revision >= 2)
1860 return;
1861 for (bar = 0; bar <= 1; bar++)
1862 if (pci_resource_len(dev, bar) == 0x80 &&
1863 (pci_resource_start(dev, bar) & 0x80)) {
1864 struct resource *r = &dev->resource[bar];
Ryan Desfosses227f0642014-04-18 20:13:50 -04001865 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
Ian Abbott21c5fd92012-10-30 17:25:53 +00001866 bar);
Bjorn Helgaasbd064f02014-02-26 11:25:58 -07001867 r->flags |= IORESOURCE_UNSET;
Ian Abbott21c5fd92012-10-30 17:25:53 +00001868 r->start = 0;
1869 r->end = 0xff;
1870 }
1871}
1872DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1873 quirk_plx_pci9050);
Ian Abbott2794bb22012-10-29 14:40:18 +00001874/*
1875 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1876 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1877 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1878 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1879 *
1880 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1881 * driver.
1882 */
1883DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1884DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
Ian Abbott21c5fd92012-10-30 17:25:53 +00001885
Bill Pemberton15856ad2012-11-21 15:35:00 -05001886static void quirk_netmos(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001887{
1888 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1889 unsigned int num_serial = dev->subsystem_device & 0xf;
1890
1891 /*
1892 * These Netmos parts are multiport serial devices with optional
1893 * parallel ports. Even when parallel ports are present, they
1894 * are identified as class SERIAL, which means the serial driver
1895 * will claim them. To prevent this, mark them as class OTHER.
1896 * These combo devices should be claimed by parport_serial.
1897 *
1898 * The subdevice ID is of the form 0x00PS, where <P> is the number
1899 * of parallel ports and <S> is the number of serial ports.
1900 */
1901 switch (dev->device) {
Jiri Slaby4c9c1682008-12-08 16:19:14 +01001902 case PCI_DEVICE_ID_NETMOS_9835:
1903 /* Well, this rule doesn't hold for the following 9835 device */
1904 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1905 dev->subsystem_device == 0x0299)
1906 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001907 case PCI_DEVICE_ID_NETMOS_9735:
1908 case PCI_DEVICE_ID_NETMOS_9745:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001909 case PCI_DEVICE_ID_NETMOS_9845:
1910 case PCI_DEVICE_ID_NETMOS_9855:
Yinghai Lu08803ef2012-02-23 23:46:56 -08001911 if (num_parallel) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04001912 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001913 dev->device, num_parallel, num_serial);
1914 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1915 (dev->class & 0xff);
1916 }
1917 }
1918}
Yinghai Lu08803ef2012-02-23 23:46:56 -08001919DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1920 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001921
Alex Williamsonda2d03e2015-09-15 22:24:46 -06001922/*
1923 * Quirk non-zero PCI functions to route VPD access through function 0 for
1924 * devices that share VPD resources between functions. The functions are
1925 * expected to be identical devices.
1926 */
Mark Rustad7aa6ca42015-07-13 11:40:07 -07001927static void quirk_f0_vpd_link(struct pci_dev *dev)
1928{
Alex Williamsonda2d03e2015-09-15 22:24:46 -06001929 struct pci_dev *f0;
1930
1931 if (!PCI_FUNC(dev->devfn))
Mark Rustad7aa6ca42015-07-13 11:40:07 -07001932 return;
Alex Williamsonda2d03e2015-09-15 22:24:46 -06001933
1934 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
1935 if (!f0)
1936 return;
1937
1938 if (f0->vpd && dev->class == f0->class &&
1939 dev->vendor == f0->vendor && dev->device == f0->device)
1940 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
1941
1942 pci_dev_put(f0);
Mark Rustad7aa6ca42015-07-13 11:40:07 -07001943}
1944DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1945 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
1946
Bill Pemberton15856ad2012-11-21 15:35:00 -05001947static void quirk_e100_interrupt(struct pci_dev *dev)
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001948{
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001949 u16 command, pmcsr;
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001950 u8 __iomem *csr;
1951 u8 cmd_hi;
1952
1953 switch (dev->device) {
1954 /* PCI IDs taken from drivers/net/e100.c */
1955 case 0x1029:
1956 case 0x1030 ... 0x1034:
1957 case 0x1038 ... 0x103E:
1958 case 0x1050 ... 0x1057:
1959 case 0x1059:
1960 case 0x1064 ... 0x106B:
1961 case 0x1091 ... 0x1095:
1962 case 0x1209:
1963 case 0x1229:
1964 case 0x2449:
1965 case 0x2459:
1966 case 0x245D:
1967 case 0x27DC:
1968 break;
1969 default:
1970 return;
1971 }
1972
1973 /*
1974 * Some firmware hands off the e100 with interrupts enabled,
1975 * which can cause a flood of interrupts if packets are
1976 * received before the driver attaches to the device. So
1977 * disable all e100 interrupts here. The driver will
1978 * re-enable them when it's ready.
1979 */
1980 pci_read_config_word(dev, PCI_COMMAND, &command);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001981
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10001982 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001983 return;
1984
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001985 /*
1986 * Check that the device is in the D0 power state. If it's not,
1987 * there is no point to look any further.
1988 */
Yijing Wang728cdb72013-06-18 16:22:14 +08001989 if (dev->pm_cap) {
1990 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001991 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1992 return;
1993 }
1994
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10001995 /* Convert from PCI bus to resource space. */
1996 csr = ioremap(pci_resource_start(dev, 0), 8);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001997 if (!csr) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001998 dev_warn(&dev->dev, "Can't map e100 registers\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001999 return;
2000 }
2001
2002 cmd_hi = readb(csr + 3);
2003 if (cmd_hi == 0) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002004 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04002005 writeb(1, csr + 3);
2006 }
2007
2008 iounmap(csr);
2009}
Yinghai Lu4c5b28e2012-02-23 23:46:57 -08002010DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2011 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03002012
Alexander Duyck649426e2009-03-05 13:57:28 -05002013/*
2014 * The 82575 and 82598 may experience data corruption issues when transitioning
2015 * out of L0S. To prevent this we need to disable L0S on the pci-e link
2016 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002017static void quirk_disable_aspm_l0s(struct pci_dev *dev)
Alexander Duyck649426e2009-03-05 13:57:28 -05002018{
2019 dev_info(&dev->dev, "Disabling L0s\n");
2020 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2021}
2022DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2023DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2024DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2025DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2026DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2027DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2028DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2029DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2030DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2031DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2032DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2033DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2034DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2035DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2036
Bill Pemberton15856ad2012-11-21 15:35:00 -05002037static void fixup_rev1_53c810(struct pci_dev *dev)
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03002038{
Bjorn Helgaase6323e32015-06-19 15:36:45 -05002039 u32 class = dev->class;
2040
2041 /*
2042 * rev 1 ncr53c810 chips don't set the class at all which means
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03002043 * they don't get their resources remapped. Fix that here.
2044 */
Bjorn Helgaase6323e32015-06-19 15:36:45 -05002045 if (class)
2046 return;
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03002047
Bjorn Helgaase6323e32015-06-19 15:36:45 -05002048 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2049 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2050 class, dev->class);
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03002051}
2052DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2053
Daniel Yeisley9d265122005-12-05 07:06:43 -05002054/* Enable 1k I/O space granularity on the Intel P64H2 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002055static void quirk_p64h2_1k_io(struct pci_dev *dev)
Daniel Yeisley9d265122005-12-05 07:06:43 -05002056{
2057 u16 en1k;
Daniel Yeisley9d265122005-12-05 07:06:43 -05002058
2059 pci_read_config_word(dev, 0x40, &en1k);
2060
2061 if (en1k & 0x200) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002062 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -06002063 dev->io_window_1k = 1;
Daniel Yeisley9d265122005-12-05 07:06:43 -05002064 }
2065}
2066DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2067
Brice Goglincf34a8e2006-06-13 14:35:42 -04002068/* Under some circumstances, AER is not linked with extended capabilities.
2069 * Force it to be linked by setting the corresponding control bit in the
2070 * config space.
2071 */
Alan Cox1597cac2006-12-04 15:14:45 -08002072static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
Brice Goglincf34a8e2006-06-13 14:35:42 -04002073{
2074 uint8_t b;
2075 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2076 if (!(b & 0x20)) {
2077 pci_write_config_byte(dev, 0xf41, b | 0x20);
Ryan Desfosses227f0642014-04-18 20:13:50 -04002078 dev_info(&dev->dev, "Linking AER extended capability\n");
Brice Goglincf34a8e2006-06-13 14:35:42 -04002079 }
2080 }
2081}
2082DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2083 quirk_nvidia_ck804_pcie_aer_ext_cap);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02002084DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
Alan Cox1597cac2006-12-04 15:14:45 -08002085 quirk_nvidia_ck804_pcie_aer_ext_cap);
Brice Goglincf34a8e2006-06-13 14:35:42 -04002086
Bill Pemberton15856ad2012-11-21 15:35:00 -05002087static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
Tim Yamin53a9bf42007-11-01 23:14:54 +00002088{
2089 /*
2090 * Disable PCI Bus Parking and PCI Master read caching on CX700
2091 * which causes unspecified timing errors with a VT6212L on the PCI
Tim Yaminca846392010-03-19 14:22:58 -07002092 * bus leading to USB2.0 packet loss.
2093 *
2094 * This quirk is only enabled if a second (on the external PCI bus)
2095 * VT6212L is found -- the CX700 core itself also contains a USB
2096 * host controller with the same PCI ID as the VT6212L.
Tim Yamin53a9bf42007-11-01 23:14:54 +00002097 */
2098
Tim Yaminca846392010-03-19 14:22:58 -07002099 /* Count VT6212L instances */
2100 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2101 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
Tim Yamin53a9bf42007-11-01 23:14:54 +00002102 uint8_t b;
Tim Yaminca846392010-03-19 14:22:58 -07002103
2104 /* p should contain the first (internal) VT6212L -- see if we have
2105 an external one by searching again */
2106 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2107 if (!p)
2108 return;
2109 pci_dev_put(p);
2110
Tim Yamin53a9bf42007-11-01 23:14:54 +00002111 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2112 if (b & 0x40) {
2113 /* Turn off PCI Bus Parking */
2114 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2115
Ryan Desfosses227f0642014-04-18 20:13:50 -04002116 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
Tim Yaminbc043272008-03-30 20:58:59 +01002117 }
2118 }
2119
2120 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2121 if (b != 0) {
Tim Yamin53a9bf42007-11-01 23:14:54 +00002122 /* Turn off PCI Master read caching */
2123 pci_write_config_byte(dev, 0x72, 0x0);
Tim Yaminbc043272008-03-30 20:58:59 +01002124
2125 /* Set PCI Master Bus time-out to "1x16 PCLK" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00002126 pci_write_config_byte(dev, 0x75, 0x1);
Tim Yaminbc043272008-03-30 20:58:59 +01002127
2128 /* Disable "Read FIFO Timer" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00002129 pci_write_config_byte(dev, 0x77, 0x0);
2130
Ryan Desfosses227f0642014-04-18 20:13:50 -04002131 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
Tim Yamin53a9bf42007-11-01 23:14:54 +00002132 }
2133 }
2134}
Tim Yaminca846392010-03-19 14:22:58 -07002135DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
Tim Yamin53a9bf42007-11-01 23:14:54 +00002136
Benjamin Li99cb233d2008-07-02 10:59:04 -07002137/*
2138 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2139 * VPD end tag will hang the device. This problem was initially
2140 * observed when a vpd entry was created in sysfs
2141 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2142 * will dump 32k of data. Reading a full 32k will cause an access
2143 * beyond the VPD end tag causing the device to hang. Once the device
2144 * is hung, the bnx2 driver will not be able to reset the device.
2145 * We believe that it is legal to read beyond the end tag and
2146 * therefore the solution is to limit the read/write length.
2147 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002148static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
Benjamin Li99cb233d2008-07-02 10:59:04 -07002149{
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002150 /*
Dean Hildebrand35405f22008-08-07 17:31:45 -07002151 * Only disable the VPD capability for 5706, 5706S, 5708,
2152 * 5708S and 5709 rev. A
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002153 */
Benjamin Li99cb233d2008-07-02 10:59:04 -07002154 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
Dean Hildebrand35405f22008-08-07 17:31:45 -07002155 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
Benjamin Li99cb233d2008-07-02 10:59:04 -07002156 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002157 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
Benjamin Li99cb233d2008-07-02 10:59:04 -07002158 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2159 (dev->revision & 0xf0) == 0x0)) {
2160 if (dev->vpd)
2161 dev->vpd->len = 0x80;
2162 }
2163}
2164
Yu Zhaobffadff2008-10-28 14:44:11 +08002165DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2166 PCI_DEVICE_ID_NX2_5706,
2167 quirk_brcm_570x_limit_vpd);
2168DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2169 PCI_DEVICE_ID_NX2_5706S,
2170 quirk_brcm_570x_limit_vpd);
2171DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2172 PCI_DEVICE_ID_NX2_5708,
2173 quirk_brcm_570x_limit_vpd);
2174DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2175 PCI_DEVICE_ID_NX2_5708S,
2176 quirk_brcm_570x_limit_vpd);
2177DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2178 PCI_DEVICE_ID_NX2_5709,
2179 quirk_brcm_570x_limit_vpd);
2180DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2181 PCI_DEVICE_ID_NX2_5709S,
2182 quirk_brcm_570x_limit_vpd);
Benjamin Li99cb233d2008-07-02 10:59:04 -07002183
Myron Stowe25e742b2012-07-09 15:36:14 -06002184static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
Matt Carlson0b471502012-02-27 09:44:48 +00002185{
2186 u32 rev;
2187
2188 pci_read_config_dword(dev, 0xf4, &rev);
2189
2190 /* Only CAP the MRRS if the device is a 5719 A0 */
2191 if (rev == 0x05719000) {
2192 int readrq = pcie_get_readrq(dev);
2193 if (readrq > 2048)
2194 pcie_set_readrq(dev, 2048);
2195 }
2196}
2197
2198DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2199 PCI_DEVICE_ID_TIGON3_5719,
2200 quirk_brcm_5719_limit_mrrs);
2201
Michal Miroslaw26c56dc2009-05-12 13:49:26 -07002202/* Originally in EDAC sources for i82875P:
2203 * Intel tells BIOS developers to hide device 6 which
2204 * configures the overflow device access containing
2205 * the DRBs - this is where we expose device 6.
2206 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2207 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002208static void quirk_unhide_mch_dev6(struct pci_dev *dev)
Michal Miroslaw26c56dc2009-05-12 13:49:26 -07002209{
2210 u8 reg;
2211
2212 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2213 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2214 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2215 }
2216}
2217
2218DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2219 quirk_unhide_mch_dev6);
2220DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2221 quirk_unhide_mch_dev6);
2222
Chris Metcalf12962262012-04-07 17:10:17 -04002223#ifdef CONFIG_TILEPRO
Chris Metcalff02cbbe2010-11-02 12:05:10 -04002224/*
Chris Metcalf12962262012-04-07 17:10:17 -04002225 * The Tilera TILEmpower tilepro platform needs to set the link speed
Chris Metcalff02cbbe2010-11-02 12:05:10 -04002226 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2227 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2228 * capability register of the PEX8624 PCIe switch. The switch
2229 * supports link speed auto negotiation, but falsely sets
2230 * the link speed to 5GT/s.
2231 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002232static void quirk_tile_plx_gen1(struct pci_dev *dev)
Chris Metcalff02cbbe2010-11-02 12:05:10 -04002233{
2234 if (tile_plx_gen1) {
2235 pci_write_config_dword(dev, 0x98, 0x1);
2236 mdelay(50);
2237 }
2238}
2239DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
Chris Metcalf12962262012-04-07 17:10:17 -04002240#endif /* CONFIG_TILEPRO */
Michal Miroslaw26c56dc2009-05-12 13:49:26 -07002241
Brice Goglin3f79e102006-08-31 01:54:56 -04002242#ifdef CONFIG_PCI_MSI
Tejun Heoebdf7d32007-05-31 00:40:48 -07002243/* Some chipsets do not support MSI. We cannot easily rely on setting
2244 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002245 * some other buses controlled by the chipset even if Linux is not
2246 * aware of it. Instead of setting the flag on all buses in the
Tejun Heoebdf7d32007-05-31 00:40:48 -07002247 * machine, simply disable MSI globally.
Brice Goglin3f79e102006-08-31 01:54:56 -04002248 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002249static void quirk_disable_all_msi(struct pci_dev *dev)
Brice Goglin3f79e102006-08-31 01:54:56 -04002250{
Michael Ellerman88187df2007-01-25 19:34:07 +11002251 pci_no_msi();
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002252 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04002253}
Tejun Heoebdf7d32007-05-31 00:40:48 -07002254DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2255DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2256DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
Tejun Heo66d715c2008-07-04 09:59:32 -07002257DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
Jay Cliburn184b8122007-05-26 17:01:04 -05002258DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
Thomas Renninger162dedd2009-04-03 06:34:00 -07002259DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
Tejun Heo549e1562010-05-23 10:22:55 +02002260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
Ondrej Zary10b4ad12015-09-24 17:02:07 -05002261DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
Brice Goglin3f79e102006-08-31 01:54:56 -04002262
2263/* Disable MSI on chipsets that are known to not support it */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002264static void quirk_disable_msi(struct pci_dev *dev)
Brice Goglin3f79e102006-08-31 01:54:56 -04002265{
2266 if (dev->subordinate) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002267 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04002268 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2269 }
2270}
2271DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
Matthew Wilcox134b3452010-03-24 07:11:01 -06002272DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
Alex Deucher9313ff42010-05-18 10:42:53 -04002273DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
Brice Goglin6397c752006-08-31 01:55:32 -04002274
Clemens Ladischaff61362010-05-26 12:21:10 +02002275/*
2276 * The APC bridge device in AMD 780 family northbridges has some random
2277 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2278 * we use the possible vendor/device IDs of the host bridge for the
2279 * declared quirk, and search for the APC bridge by slot number.
2280 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002281static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
Clemens Ladischaff61362010-05-26 12:21:10 +02002282{
2283 struct pci_dev *apc_bridge;
2284
2285 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2286 if (apc_bridge) {
2287 if (apc_bridge->device == 0x9602)
2288 quirk_disable_msi(apc_bridge);
2289 pci_dev_put(apc_bridge);
2290 }
2291}
2292DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2293DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2294
Brice Goglin6397c752006-08-31 01:55:32 -04002295/* Go through the list of Hypertransport capabilities and
2296 * return 1 if a HT MSI capability is found and enabled */
Myron Stowe25e742b2012-07-09 15:36:14 -06002297static int msi_ht_cap_enabled(struct pci_dev *dev)
Brice Goglin6397c752006-08-31 01:55:32 -04002298{
Wei Yangfff905f2015-06-30 09:16:41 +08002299 int pos, ttl = PCI_FIND_CAP_TTL;
Michael Ellerman7a380502006-11-22 18:26:21 +11002300
2301 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2302 while (pos && ttl--) {
2303 u8 flags;
2304
2305 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04002306 &flags) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002307 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
Michael Ellerman7a380502006-11-22 18:26:21 +11002308 flags & HT_MSI_FLAGS_ENABLE ?
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002309 "enabled" : "disabled");
Michael Ellerman7a380502006-11-22 18:26:21 +11002310 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
Brice Goglin6397c752006-08-31 01:55:32 -04002311 }
Michael Ellerman7a380502006-11-22 18:26:21 +11002312
2313 pos = pci_find_next_ht_capability(dev, pos,
2314 HT_CAPTYPE_MSI_MAPPING);
Brice Goglin6397c752006-08-31 01:55:32 -04002315 }
2316 return 0;
2317}
2318
2319/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
Myron Stowe25e742b2012-07-09 15:36:14 -06002320static void quirk_msi_ht_cap(struct pci_dev *dev)
Brice Goglin6397c752006-08-31 01:55:32 -04002321{
2322 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002323 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04002324 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2325 }
2326}
2327DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2328 quirk_msi_ht_cap);
Sebastien Dugue6bae1d92007-12-13 16:09:25 -08002329
Brice Goglin6397c752006-08-31 01:55:32 -04002330/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2331 * MSI are supported if the MSI capability set in any of these mappings.
2332 */
Myron Stowe25e742b2012-07-09 15:36:14 -06002333static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
Brice Goglin6397c752006-08-31 01:55:32 -04002334{
2335 struct pci_dev *pdev;
2336
2337 if (!dev->subordinate)
2338 return;
2339
2340 /* check HT MSI cap on this chipset and the root one.
2341 * a single one having MSI is enough to be sure that MSI are supported.
2342 */
Alan Cox11f242f2006-10-10 14:39:00 -07002343 pdev = pci_get_slot(dev->bus, 0);
Jesper Juhl9ac0ce82006-12-04 15:14:48 -08002344 if (!pdev)
2345 return;
David Rientjes0c875c22006-12-03 11:55:34 -08002346 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002347 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04002348 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2349 }
Alan Cox11f242f2006-10-10 14:39:00 -07002350 pci_dev_put(pdev);
Brice Goglin6397c752006-08-31 01:55:32 -04002351}
2352DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2353 quirk_nvidia_ck804_msi_ht_cap);
David Millerba698ad2007-10-25 01:16:30 -07002354
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07002355/* Force enable MSI mapping capability on HT bridges */
Myron Stowe25e742b2012-07-09 15:36:14 -06002356static void ht_enable_msi_mapping(struct pci_dev *dev)
Peer Chen9dc625e2008-02-04 23:50:13 -08002357{
Wei Yangfff905f2015-06-30 09:16:41 +08002358 int pos, ttl = PCI_FIND_CAP_TTL;
Peer Chen9dc625e2008-02-04 23:50:13 -08002359
2360 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2361 while (pos && ttl--) {
2362 u8 flags;
2363
2364 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2365 &flags) == 0) {
2366 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2367
2368 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2369 flags | HT_MSI_FLAGS_ENABLE);
2370 }
2371 pos = pci_find_next_ht_capability(dev, pos,
2372 HT_CAPTYPE_MSI_MAPPING);
2373 }
2374}
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07002375DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2376 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2377 ht_enable_msi_mapping);
Peer Chen9dc625e2008-02-04 23:50:13 -08002378
Yinghai Lue0ae4f52009-02-17 20:40:09 -08002379DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2380 ht_enable_msi_mapping);
2381
Ben Hutchingse4146bb2010-05-16 02:28:49 +01002382/* The P5N32-SLI motherboards from Asus have a problem with msi
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002383 * for the MCP55 NIC. It is not yet determined whether the msi problem
2384 * also affects other devices. As for now, turn off msi for this device.
2385 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002386static void nvenet_msi_disable(struct pci_dev *dev)
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002387{
Jean Delvare9251bac2011-05-15 18:13:46 +02002388 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2389
2390 if (board_name &&
2391 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2392 strstr(board_name, "P5N32-E SLI"))) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002393 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002394 dev->no_msi = 1;
2395 }
2396}
2397DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2398 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2399 nvenet_msi_disable);
2400
Neil Horman66db60e2010-09-21 13:54:39 -04002401/*
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002402 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2403 * config register. This register controls the routing of legacy
2404 * interrupts from devices that route through the MCP55. If this register
2405 * is misprogrammed, interrupts are only sent to the BSP, unlike
2406 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2407 * having this register set properly prevents kdump from booting up
2408 * properly, so let's make sure that we have it set correctly.
2409 * Note that this is an undocumented register.
Neil Horman66db60e2010-09-21 13:54:39 -04002410 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002411static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
Neil Horman66db60e2010-09-21 13:54:39 -04002412{
2413 u32 cfg;
2414
Neil Horman49c2fa082010-12-08 09:47:48 -05002415 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2416 return;
2417
Neil Horman66db60e2010-09-21 13:54:39 -04002418 pci_read_config_dword(dev, 0x74, &cfg);
2419
2420 if (cfg & ((1 << 2) | (1 << 15))) {
2421 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2422 cfg &= ~((1 << 2) | (1 << 15));
2423 pci_write_config_dword(dev, 0x74, cfg);
2424 }
2425}
2426
2427DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2428 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2429 nvbridge_check_legacy_irq_routing);
2430
2431DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2432 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2433 nvbridge_check_legacy_irq_routing);
2434
Myron Stowe25e742b2012-07-09 15:36:14 -06002435static int ht_check_msi_mapping(struct pci_dev *dev)
Yinghai Lude745302009-03-20 19:29:41 -07002436{
Wei Yangfff905f2015-06-30 09:16:41 +08002437 int pos, ttl = PCI_FIND_CAP_TTL;
Yinghai Lude745302009-03-20 19:29:41 -07002438 int found = 0;
2439
2440 /* check if there is HT MSI cap or enabled on this device */
2441 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2442 while (pos && ttl--) {
2443 u8 flags;
2444
2445 if (found < 1)
2446 found = 1;
2447 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2448 &flags) == 0) {
2449 if (flags & HT_MSI_FLAGS_ENABLE) {
2450 if (found < 2) {
2451 found = 2;
2452 break;
2453 }
2454 }
2455 }
2456 pos = pci_find_next_ht_capability(dev, pos,
2457 HT_CAPTYPE_MSI_MAPPING);
2458 }
2459
2460 return found;
2461}
2462
Myron Stowe25e742b2012-07-09 15:36:14 -06002463static int host_bridge_with_leaf(struct pci_dev *host_bridge)
Yinghai Lude745302009-03-20 19:29:41 -07002464{
2465 struct pci_dev *dev;
2466 int pos;
2467 int i, dev_no;
2468 int found = 0;
2469
2470 dev_no = host_bridge->devfn >> 3;
2471 for (i = dev_no + 1; i < 0x20; i++) {
2472 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2473 if (!dev)
2474 continue;
2475
2476 /* found next host bridge ?*/
2477 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2478 if (pos != 0) {
2479 pci_dev_put(dev);
2480 break;
2481 }
2482
2483 if (ht_check_msi_mapping(dev)) {
2484 found = 1;
2485 pci_dev_put(dev);
2486 break;
2487 }
2488 pci_dev_put(dev);
2489 }
2490
2491 return found;
2492}
2493
Yinghai Lueeafda72009-03-29 12:30:05 -07002494#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2495#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2496
Myron Stowe25e742b2012-07-09 15:36:14 -06002497static int is_end_of_ht_chain(struct pci_dev *dev)
Yinghai Lueeafda72009-03-29 12:30:05 -07002498{
2499 int pos, ctrl_off;
2500 int end = 0;
2501 u16 flags, ctrl;
2502
2503 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2504
2505 if (!pos)
2506 goto out;
2507
2508 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2509
2510 ctrl_off = ((flags >> 10) & 1) ?
2511 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2512 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2513
2514 if (ctrl & (1 << 6))
2515 end = 1;
2516
2517out:
2518 return end;
2519}
2520
Myron Stowe25e742b2012-07-09 15:36:14 -06002521static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002522{
2523 struct pci_dev *host_bridge;
2524 int pos;
2525 int i, dev_no;
2526 int found = 0;
2527
2528 dev_no = dev->devfn >> 3;
2529 for (i = dev_no; i >= 0; i--) {
2530 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2531 if (!host_bridge)
2532 continue;
2533
2534 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2535 if (pos != 0) {
2536 found = 1;
2537 break;
2538 }
2539 pci_dev_put(host_bridge);
2540 }
2541
2542 if (!found)
2543 return;
2544
Yinghai Lueeafda72009-03-29 12:30:05 -07002545 /* don't enable end_device/host_bridge with leaf directly here */
2546 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2547 host_bridge_with_leaf(host_bridge))
Yinghai Lude745302009-03-20 19:29:41 -07002548 goto out;
2549
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002550 /* root did that ! */
2551 if (msi_ht_cap_enabled(host_bridge))
2552 goto out;
2553
2554 ht_enable_msi_mapping(dev);
2555
2556out:
2557 pci_dev_put(host_bridge);
2558}
2559
Myron Stowe25e742b2012-07-09 15:36:14 -06002560static void ht_disable_msi_mapping(struct pci_dev *dev)
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002561{
Wei Yangfff905f2015-06-30 09:16:41 +08002562 int pos, ttl = PCI_FIND_CAP_TTL;
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002563
2564 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2565 while (pos && ttl--) {
2566 u8 flags;
2567
2568 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2569 &flags) == 0) {
Prakash Punnoor6a958d52009-03-06 10:10:35 +01002570 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002571
2572 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2573 flags & ~HT_MSI_FLAGS_ENABLE);
2574 }
2575 pos = pci_find_next_ht_capability(dev, pos,
2576 HT_CAPTYPE_MSI_MAPPING);
2577 }
2578}
2579
Myron Stowe25e742b2012-07-09 15:36:14 -06002580static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
Peer Chen9dc625e2008-02-04 23:50:13 -08002581{
2582 struct pci_dev *host_bridge;
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002583 int pos;
2584 int found;
2585
Rafael J. Wysocki3d2a5312010-07-23 22:19:55 +02002586 if (!pci_msi_enabled())
2587 return;
2588
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002589 /* check if there is HT MSI cap or enabled on this device */
2590 found = ht_check_msi_mapping(dev);
2591
2592 /* no HT MSI CAP */
2593 if (found == 0)
2594 return;
Peer Chen9dc625e2008-02-04 23:50:13 -08002595
2596 /*
2597 * HT MSI mapping should be disabled on devices that are below
2598 * a non-Hypertransport host bridge. Locate the host bridge...
2599 */
2600 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2601 if (host_bridge == NULL) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002602 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
Peer Chen9dc625e2008-02-04 23:50:13 -08002603 return;
2604 }
2605
2606 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2607 if (pos != 0) {
2608 /* Host bridge is to HT */
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002609 if (found == 1) {
2610 /* it is not enabled, try to enable it */
Yinghai Lude745302009-03-20 19:29:41 -07002611 if (all)
2612 ht_enable_msi_mapping(dev);
2613 else
2614 nv_ht_enable_msi_mapping(dev);
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002615 }
Myron Stowedff3aef2012-07-09 15:36:08 -06002616 goto out;
Peer Chen9dc625e2008-02-04 23:50:13 -08002617 }
2618
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002619 /* HT MSI is not enabled */
2620 if (found == 1)
Myron Stowedff3aef2012-07-09 15:36:08 -06002621 goto out;
Peer Chen9dc625e2008-02-04 23:50:13 -08002622
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002623 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2624 ht_disable_msi_mapping(dev);
Myron Stowedff3aef2012-07-09 15:36:08 -06002625
2626out:
2627 pci_dev_put(host_bridge);
Peer Chen9dc625e2008-02-04 23:50:13 -08002628}
Yinghai Lude745302009-03-20 19:29:41 -07002629
Myron Stowe25e742b2012-07-09 15:36:14 -06002630static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
Yinghai Lude745302009-03-20 19:29:41 -07002631{
2632 return __nv_msi_ht_cap_quirk(dev, 1);
2633}
2634
Myron Stowe25e742b2012-07-09 15:36:14 -06002635static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
Yinghai Lude745302009-03-20 19:29:41 -07002636{
2637 return __nv_msi_ht_cap_quirk(dev, 0);
2638}
2639
2640DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
Tejun Heo6dab62e2009-07-21 16:08:43 -07002641DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
Yinghai Lude745302009-03-20 19:29:41 -07002642
2643DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
Tejun Heo6dab62e2009-07-21 16:08:43 -07002644DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
Peer Chen9dc625e2008-02-04 23:50:13 -08002645
Bill Pemberton15856ad2012-11-21 15:35:00 -05002646static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
David Millerba698ad2007-10-25 01:16:30 -07002647{
2648 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2649}
Bill Pemberton15856ad2012-11-21 15:35:00 -05002650static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
Shane Huang4600c9d2008-01-25 15:46:24 +09002651{
2652 struct pci_dev *p;
2653
2654 /* SB700 MSI issue will be fixed at HW level from revision A21,
2655 * we need check PCI REVISION ID of SMBus controller to get SB700
2656 * revision.
2657 */
2658 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2659 NULL);
2660 if (!p)
2661 return;
2662
2663 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2664 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2665 pci_dev_put(p);
2666}
Xiong Huang70588812013-03-07 08:55:16 +00002667static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2668{
2669 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2670 if (dev->revision < 0x18) {
2671 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2672 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2673 }
2674}
David Millerba698ad2007-10-25 01:16:30 -07002675DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2676 PCI_DEVICE_ID_TIGON3_5780,
2677 quirk_msi_intx_disable_bug);
2678DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2679 PCI_DEVICE_ID_TIGON3_5780S,
2680 quirk_msi_intx_disable_bug);
2681DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2682 PCI_DEVICE_ID_TIGON3_5714,
2683 quirk_msi_intx_disable_bug);
2684DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2685 PCI_DEVICE_ID_TIGON3_5714S,
2686 quirk_msi_intx_disable_bug);
2687DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2688 PCI_DEVICE_ID_TIGON3_5715,
2689 quirk_msi_intx_disable_bug);
2690DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2691 PCI_DEVICE_ID_TIGON3_5715S,
2692 quirk_msi_intx_disable_bug);
2693
David Millerbc38b412007-10-25 01:16:52 -07002694DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
Shane Huang4600c9d2008-01-25 15:46:24 +09002695 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002696DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
Shane Huang4600c9d2008-01-25 15:46:24 +09002697 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002698DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
Shane Huang4600c9d2008-01-25 15:46:24 +09002699 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002700DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
Shane Huang4600c9d2008-01-25 15:46:24 +09002701 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002702DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
Shane Huang4600c9d2008-01-25 15:46:24 +09002703 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002704
2705DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2706 quirk_msi_intx_disable_bug);
2707DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2708 quirk_msi_intx_disable_bug);
2709DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2710 quirk_msi_intx_disable_bug);
2711
Huang, Xiong7cb6a292012-04-30 15:38:49 +00002712DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2713 quirk_msi_intx_disable_bug);
2714DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2715 quirk_msi_intx_disable_bug);
2716DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2717 quirk_msi_intx_disable_bug);
2718DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2719 quirk_msi_intx_disable_bug);
2720DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2721 quirk_msi_intx_disable_bug);
2722DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2723 quirk_msi_intx_disable_bug);
Xiong Huang70588812013-03-07 08:55:16 +00002724DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2725 quirk_msi_intx_disable_qca_bug);
2726DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2727 quirk_msi_intx_disable_qca_bug);
2728DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2729 quirk_msi_intx_disable_qca_bug);
2730DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2731 quirk_msi_intx_disable_qca_bug);
2732DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2733 quirk_msi_intx_disable_qca_bug);
Brice Goglin3f79e102006-08-31 01:54:56 -04002734#endif /* CONFIG_PCI_MSI */
Thomas Petazzoni3d137312008-08-19 10:28:24 +02002735
Felix Radensky33223402010-03-28 16:02:02 +03002736/* Allow manual resource allocation for PCI hotplug bridges
2737 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2738 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002739 * kernel fails to allocate resources when hotplug device is
Felix Radensky33223402010-03-28 16:02:02 +03002740 * inserted and PCI bus is rescanned.
2741 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002742static void quirk_hotplug_bridge(struct pci_dev *dev)
Felix Radensky33223402010-03-28 16:02:02 +03002743{
2744 dev->is_hotplug_bridge = 1;
2745}
2746
2747DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2748
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002749/*
2750 * This is a quirk for the Ricoh MMC controller found as a part of
2751 * some mulifunction chips.
2752
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002753 * This is very similar and based on the ricoh_mmc driver written by
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002754 * Philip Langdale. Thank you for these magic sequences.
2755 *
2756 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2757 * and one or both of cardbus or firewire.
2758 *
2759 * It happens that they implement SD and MMC
2760 * support as separate controllers (and PCI functions). The linux SDHCI
2761 * driver supports MMC cards but the chip detects MMC cards in hardware
2762 * and directs them to the MMC controller - so the SDHCI driver never sees
2763 * them.
2764 *
2765 * To get around this, we must disable the useless MMC controller.
2766 * At that point, the SDHCI controller will start seeing them
2767 * It seems to be the case that the relevant PCI registers to deactivate the
2768 * MMC controller live on PCI function 0, which might be the cardbus controller
2769 * or the firewire controller, depending on the particular chip in question
2770 *
2771 * This has to be done early, because as soon as we disable the MMC controller
2772 * other pci functions shift up one level, e.g. function #2 becomes function
2773 * #1, and this will confuse the pci core.
2774 */
2775
2776#ifdef CONFIG_MMC_RICOH_MMC
2777static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2778{
2779 /* disable via cardbus interface */
2780 u8 write_enable;
2781 u8 write_target;
2782 u8 disable;
2783
2784 /* disable must be done via function #0 */
2785 if (PCI_FUNC(dev->devfn))
2786 return;
2787
2788 pci_read_config_byte(dev, 0xB7, &disable);
2789 if (disable & 0x02)
2790 return;
2791
2792 pci_read_config_byte(dev, 0x8E, &write_enable);
2793 pci_write_config_byte(dev, 0x8E, 0xAA);
2794 pci_read_config_byte(dev, 0x8D, &write_target);
2795 pci_write_config_byte(dev, 0x8D, 0xB7);
2796 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2797 pci_write_config_byte(dev, 0x8E, write_enable);
2798 pci_write_config_byte(dev, 0x8D, write_target);
2799
2800 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2801 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2802}
2803DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2804DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2805
2806static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2807{
2808 /* disable via firewire interface */
2809 u8 write_enable;
2810 u8 disable;
2811
2812 /* disable must be done via function #0 */
2813 if (PCI_FUNC(dev->devfn))
2814 return;
Manoj Iyer15bed0f2011-07-11 16:28:35 -05002815 /*
Andy Lutomirski812089e2012-12-01 12:37:20 -08002816 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
Manoj Iyer15bed0f2011-07-11 16:28:35 -05002817 * certain types of SD/MMC cards. Lowering the SD base
2818 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2819 *
2820 * 0x150 - SD2.0 mode enable for changing base clock
2821 * frequency to 50Mhz
2822 * 0xe1 - Base clock frequency
2823 * 0x32 - 50Mhz new clock frequency
2824 * 0xf9 - Key register for 0x150
2825 * 0xfc - key register for 0xe1
2826 */
Andy Lutomirski812089e2012-12-01 12:37:20 -08002827 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2828 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
Manoj Iyer15bed0f2011-07-11 16:28:35 -05002829 pci_write_config_byte(dev, 0xf9, 0xfc);
2830 pci_write_config_byte(dev, 0x150, 0x10);
2831 pci_write_config_byte(dev, 0xf9, 0x00);
2832 pci_write_config_byte(dev, 0xfc, 0x01);
2833 pci_write_config_byte(dev, 0xe1, 0x32);
2834 pci_write_config_byte(dev, 0xfc, 0x00);
2835
2836 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2837 }
Josh Boyer3e309cd2011-10-05 11:44:50 -04002838
2839 pci_read_config_byte(dev, 0xCB, &disable);
2840
2841 if (disable & 0x02)
2842 return;
2843
2844 pci_read_config_byte(dev, 0xCA, &write_enable);
2845 pci_write_config_byte(dev, 0xCA, 0x57);
2846 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2847 pci_write_config_byte(dev, 0xCA, write_enable);
2848
2849 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2850 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2851
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002852}
2853DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2854DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
Andy Lutomirski812089e2012-12-01 12:37:20 -08002855DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2856DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
Manoj Iyerbe98ca62011-05-26 11:19:05 -05002857DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2858DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002859#endif /*CONFIG_MMC_RICOH_MMC*/
2860
Suresh Siddhad3f13812011-08-23 17:05:25 -07002861#ifdef CONFIG_DMAR_TABLE
Suresh Siddha254e42002010-12-06 12:26:30 -08002862#define VTUNCERRMSK_REG 0x1ac
2863#define VTD_MSK_SPEC_ERRORS (1 << 31)
2864/*
2865 * This is a quirk for masking vt-d spec defined errors to platform error
2866 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2867 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2868 * on the RAS config settings of the platform) when a vt-d fault happens.
2869 * The resulting SMI caused the system to hang.
2870 *
2871 * VT-d spec related errors are already handled by the VT-d OS code, so no
2872 * need to report the same error through other channels.
2873 */
2874static void vtd_mask_spec_errors(struct pci_dev *dev)
2875{
2876 u32 word;
2877
2878 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2879 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2880}
2881DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2882DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2883#endif
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002884
Bill Pemberton15856ad2012-11-21 15:35:00 -05002885static void fixup_ti816x_class(struct pci_dev *dev)
Hemant Pedanekar63c44082011-04-05 12:32:50 +05302886{
Bjorn Helgaasd1541dc2015-06-19 15:58:24 -05002887 u32 class = dev->class;
2888
Hemant Pedanekar63c44082011-04-05 12:32:50 +05302889 /* TI 816x devices do not have class code set when in PCIe boot mode */
Bjorn Helgaasd1541dc2015-06-19 15:58:24 -05002890 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
2891 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
2892 class, dev->class);
Hemant Pedanekar63c44082011-04-05 12:32:50 +05302893}
Yinghai Lu40c96232012-02-23 23:46:58 -08002894DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05002895 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
Hemant Pedanekar63c44082011-04-05 12:32:50 +05302896
Ben Hutchingsa94d0722011-10-05 22:35:03 +01002897/* Some PCIe devices do not work reliably with the claimed maximum
2898 * payload size supported.
2899 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002900static void fixup_mpss_256(struct pci_dev *dev)
Ben Hutchingsa94d0722011-10-05 22:35:03 +01002901{
2902 dev->pcie_mpss = 1; /* 256 bytes */
2903}
2904DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2905 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2906DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2907 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2908DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2909 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2910
Jon Masond387a8d2011-10-14 14:56:13 -05002911/* Intel 5000 and 5100 Memory controllers have an errata with read completion
2912 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2913 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2914 * until all of the devices are discovered and buses walked, read completion
2915 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2916 * it is possible to hotplug a device with MPS of 256B.
2917 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002918static void quirk_intel_mc_errata(struct pci_dev *dev)
Jon Masond387a8d2011-10-14 14:56:13 -05002919{
2920 int err;
2921 u16 rcc;
2922
Keith Busch27d868b2015-08-24 08:48:16 -05002923 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2924 pcie_bus_config == PCIE_BUS_DEFAULT)
Jon Masond387a8d2011-10-14 14:56:13 -05002925 return;
2926
2927 /* Intel errata specifies bits to change but does not say what they are.
2928 * Keeping them magical until such time as the registers and values can
2929 * be explained.
2930 */
2931 err = pci_read_config_word(dev, 0x48, &rcc);
2932 if (err) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002933 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
Jon Masond387a8d2011-10-14 14:56:13 -05002934 return;
2935 }
2936
2937 if (!(rcc & (1 << 10)))
2938 return;
2939
2940 rcc &= ~(1 << 10);
2941
2942 err = pci_write_config_word(dev, 0x48, rcc);
2943 if (err) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002944 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
Jon Masond387a8d2011-10-14 14:56:13 -05002945 return;
2946 }
2947
Ryan Desfosses227f0642014-04-18 20:13:50 -04002948 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
Jon Masond387a8d2011-10-14 14:56:13 -05002949}
2950/* Intel 5000 series memory controllers and ports 2-7 */
2951DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2952DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2953DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2954DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2955DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2956DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2957DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2958DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2959DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2960DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2961DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2962DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2963DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2964DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2965/* Intel 5100 series memory controllers and ports 2-7 */
2966DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2967DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2968DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2969DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2970DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2971DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2972DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2973DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2974DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2975DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2976DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2977
Arjan van de Ven32098742012-01-30 20:52:07 -08002978
Jon Mason12b03182013-05-06 08:03:33 +00002979/*
2980 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
2981 * work around this, query the size it should be configured to by the device and
2982 * modify the resource end to correspond to this new size.
2983 */
2984static void quirk_intel_ntb(struct pci_dev *dev)
2985{
2986 int rc;
2987 u8 val;
2988
2989 rc = pci_read_config_byte(dev, 0x00D0, &val);
2990 if (rc)
2991 return;
2992
2993 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
2994
2995 rc = pci_read_config_byte(dev, 0x00D1, &val);
2996 if (rc)
2997 return;
2998
2999 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3000}
3001DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3002DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3003
Myron Stowe2729d5b2012-07-09 15:36:02 -06003004static ktime_t fixup_debug_start(struct pci_dev *dev,
3005 void (*fn)(struct pci_dev *dev))
Arjan van de Ven32098742012-01-30 20:52:07 -08003006{
Myron Stowe2729d5b2012-07-09 15:36:02 -06003007 ktime_t calltime = ktime_set(0, 0);
3008
3009 dev_dbg(&dev->dev, "calling %pF\n", fn);
3010 if (initcall_debug) {
3011 pr_debug("calling %pF @ %i for %s\n",
3012 fn, task_pid_nr(current), dev_name(&dev->dev));
3013 calltime = ktime_get();
3014 }
3015
3016 return calltime;
3017}
3018
3019static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
3020 void (*fn)(struct pci_dev *dev))
3021{
3022 ktime_t delta, rettime;
Arjan van de Ven32098742012-01-30 20:52:07 -08003023 unsigned long long duration;
3024
Myron Stowe2729d5b2012-07-09 15:36:02 -06003025 if (initcall_debug) {
3026 rettime = ktime_get();
3027 delta = ktime_sub(rettime, calltime);
3028 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3029 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
3030 fn, duration, dev_name(&dev->dev));
3031 }
Arjan van de Ven32098742012-01-30 20:52:07 -08003032}
3033
Thomas Jaroschf67fd552011-12-07 22:08:11 +01003034/*
3035 * Some BIOS implementations leave the Intel GPU interrupts enabled,
3036 * even though no one is handling them (f.e. i915 driver is never loaded).
3037 * Additionally the interrupt destination is not set up properly
3038 * and the interrupt ends up -somewhere-.
3039 *
3040 * These spurious interrupts are "sticky" and the kernel disables
3041 * the (shared) interrupt line after 100.000+ generated interrupts.
3042 *
3043 * Fix it by disabling the still enabled interrupts.
3044 * This resolves crashes often seen on monitor unplug.
3045 */
3046#define I915_DEIER_REG 0x4400c
Bill Pemberton15856ad2012-11-21 15:35:00 -05003047static void disable_igfx_irq(struct pci_dev *dev)
Thomas Jaroschf67fd552011-12-07 22:08:11 +01003048{
3049 void __iomem *regs = pci_iomap(dev, 0, 0);
3050 if (regs == NULL) {
3051 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
3052 return;
3053 }
3054
3055 /* Check if any interrupt line is still enabled */
3056 if (readl(regs + I915_DEIER_REG) != 0) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04003057 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
Thomas Jaroschf67fd552011-12-07 22:08:11 +01003058
3059 writel(0, regs + I915_DEIER_REG);
3060 }
3061
3062 pci_iounmap(dev, regs);
3063}
3064DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3065DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
Thomas Jarosch7c821262014-04-07 15:10:32 +02003066DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
Thomas Jaroschf67fd552011-12-07 22:08:11 +01003067
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003068/*
Todd E Brandtb8cac702013-09-10 16:10:43 -07003069 * PCI devices which are on Intel chips can skip the 10ms delay
3070 * before entering D3 mode.
3071 */
3072static void quirk_remove_d3_delay(struct pci_dev *dev)
3073{
3074 dev->d3_delay = 0;
3075}
3076DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3077DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3078DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3079DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3080DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3081DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3082DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3083DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3084DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3085DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3086DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3087DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3088DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3089DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
Srinidhi Kasagar4a118752015-06-19 11:52:46 +05303090/* Intel Cherrytrail devices do not need 10ms d3_delay */
3091DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3092DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3093DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3094DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3095DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3096DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3097DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3098DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3099DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
Todd E Brandtb8cac702013-09-10 16:10:43 -07003100/*
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003101 * Some devices may pass our check in pci_intx_mask_supported if
3102 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3103 * support this feature.
3104 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05003105static void quirk_broken_intx_masking(struct pci_dev *dev)
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003106{
3107 dev->broken_intx_masking = 1;
3108}
Jan Kiszkade509f92012-06-07 10:30:59 +02003109DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
3110 quirk_broken_intx_masking);
Alex Williamson0bdb3b22012-06-07 11:01:59 -06003111DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3112 quirk_broken_intx_masking);
Alex Williamson3cb30b72014-05-01 14:36:31 -06003113/*
3114 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3115 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3116 *
3117 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3118 */
3119DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK, 0x8169,
3120 quirk_broken_intx_masking);
Gavin Shan11e42532014-09-05 15:35:30 -06003121DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3122 quirk_broken_intx_masking);
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003123
Alex Williamsonc3e59ee2015-01-15 18:17:12 -06003124static void quirk_no_bus_reset(struct pci_dev *dev)
3125{
3126 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3127}
3128
3129/*
3130 * Atheros AR93xx chips do not behave after a bus reset. The device will
3131 * throw a Link Down error on AER-capable systems and regardless of AER,
3132 * config space of the device is never accessible again and typically
3133 * causes the system to hang or reset when access is attempted.
3134 * http://www.spinics.net/lists/linux-pci/msg34797.html
3135 */
3136DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3137
Alex Williamsond84f3172014-11-21 11:24:14 -07003138static void quirk_no_pm_reset(struct pci_dev *dev)
3139{
3140 /*
3141 * We can't do a bus reset on root bus devices, but an ineffective
3142 * PM reset may be better than nothing.
3143 */
3144 if (!pci_is_root_bus(dev->bus))
3145 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3146}
3147
3148/*
3149 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3150 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3151 * to have no effect on the device: it retains the framebuffer contents and
3152 * monitor sync. Advertising this support makes other layers, like VFIO,
3153 * assume pci_reset_function() is viable for this device. Mark it as
3154 * unavailable to skip it when testing reset methods.
3155 */
3156DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3157 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3158
Andreas Noever1df51722014-06-03 22:04:10 +02003159#ifdef CONFIG_ACPI
3160/*
3161 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3162 *
3163 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3164 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3165 * be present after resume if a device was plugged in before suspend.
3166 *
3167 * The thunderbolt controller consists of a pcie switch with downstream
3168 * bridges leading to the NHI and to the tunnel pci bridges.
3169 *
3170 * This quirk cuts power to the whole chip. Therefore we have to apply it
3171 * during suspend_noirq of the upstream bridge.
3172 *
3173 * Power is automagically restored before resume. No action is needed.
3174 */
3175static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3176{
3177 acpi_handle bridge, SXIO, SXFP, SXLV;
3178
3179 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3180 return;
3181 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3182 return;
3183 bridge = ACPI_HANDLE(&dev->dev);
3184 if (!bridge)
3185 return;
3186 /*
3187 * SXIO and SXLV are present only on machines requiring this quirk.
3188 * TB bridges in external devices might have the same device id as those
3189 * on the host, but they will not have the associated ACPI methods. This
3190 * implicitly checks that we are at the right bridge.
3191 */
3192 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3193 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3194 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3195 return;
3196 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
3197
3198 /* magic sequence */
3199 acpi_execute_simple_method(SXIO, NULL, 1);
3200 acpi_execute_simple_method(SXFP, NULL, 0);
3201 msleep(300);
3202 acpi_execute_simple_method(SXLV, NULL, 0);
3203 acpi_execute_simple_method(SXIO, NULL, 0);
3204 acpi_execute_simple_method(SXLV, NULL, 0);
3205}
3206DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 0x1547,
3207 quirk_apple_poweroff_thunderbolt);
3208
3209/*
3210 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3211 *
3212 * During suspend the thunderbolt controller is reset and all pci
3213 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3214 * during resume. We have to manually wait for the NHI since there is
3215 * no parent child relationship between the NHI and the tunneled
3216 * bridges.
3217 */
3218static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3219{
3220 struct pci_dev *sibling = NULL;
3221 struct pci_dev *nhi = NULL;
3222
3223 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3224 return;
3225 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3226 return;
3227 /*
3228 * Find the NHI and confirm that we are a bridge on the tb host
3229 * controller and not on a tb endpoint.
3230 */
3231 sibling = pci_get_slot(dev->bus, 0x0);
3232 if (sibling == dev)
3233 goto out; /* we are the downstream bridge to the NHI */
3234 if (!sibling || !sibling->subordinate)
3235 goto out;
3236 nhi = pci_get_slot(sibling->subordinate, 0x0);
3237 if (!nhi)
3238 goto out;
3239 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3240 || (nhi->device != 0x1547 && nhi->device != 0x156c)
3241 || nhi->subsystem_vendor != 0x2222
3242 || nhi->subsystem_device != 0x1111)
3243 goto out;
Darrick J. Wongc89ac442015-03-31 19:38:38 -07003244 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
Andreas Noever1df51722014-06-03 22:04:10 +02003245 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3246out:
3247 pci_dev_put(nhi);
3248 pci_dev_put(sibling);
3249}
3250DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x1547,
3251 quirk_apple_wait_for_thunderbolt);
3252DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x156d,
3253 quirk_apple_wait_for_thunderbolt);
3254#endif
3255
Jesse Barnesbfb0f332008-10-27 17:50:21 -07003256static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3257 struct pci_fixup *end)
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003258{
Myron Stowe2729d5b2012-07-09 15:36:02 -06003259 ktime_t calltime;
3260
Yinghai Luf4ca5c62012-02-23 23:46:49 -08003261 for (; f < end; f++)
3262 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3263 f->class == (u32) PCI_ANY_ID) &&
3264 (f->vendor == dev->vendor ||
3265 f->vendor == (u16) PCI_ANY_ID) &&
3266 (f->device == dev->device ||
3267 f->device == (u16) PCI_ANY_ID)) {
Myron Stowe2729d5b2012-07-09 15:36:02 -06003268 calltime = fixup_debug_start(dev, f->hook);
3269 f->hook(dev);
3270 fixup_debug_report(dev, calltime, f->hook);
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003271 }
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003272}
3273
3274extern struct pci_fixup __start_pci_fixups_early[];
3275extern struct pci_fixup __end_pci_fixups_early[];
3276extern struct pci_fixup __start_pci_fixups_header[];
3277extern struct pci_fixup __end_pci_fixups_header[];
3278extern struct pci_fixup __start_pci_fixups_final[];
3279extern struct pci_fixup __end_pci_fixups_final[];
3280extern struct pci_fixup __start_pci_fixups_enable[];
3281extern struct pci_fixup __end_pci_fixups_enable[];
3282extern struct pci_fixup __start_pci_fixups_resume[];
3283extern struct pci_fixup __end_pci_fixups_resume[];
3284extern struct pci_fixup __start_pci_fixups_resume_early[];
3285extern struct pci_fixup __end_pci_fixups_resume_early[];
3286extern struct pci_fixup __start_pci_fixups_suspend[];
3287extern struct pci_fixup __end_pci_fixups_suspend[];
Andreas Noever7d2a01b2014-06-03 22:04:09 +02003288extern struct pci_fixup __start_pci_fixups_suspend_late[];
3289extern struct pci_fixup __end_pci_fixups_suspend_late[];
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003290
Myron Stowe95df8b82012-07-13 14:29:00 -06003291static bool pci_apply_fixup_final_quirks;
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003292
3293void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3294{
3295 struct pci_fixup *start, *end;
3296
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04003297 switch (pass) {
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003298 case pci_fixup_early:
3299 start = __start_pci_fixups_early;
3300 end = __end_pci_fixups_early;
3301 break;
3302
3303 case pci_fixup_header:
3304 start = __start_pci_fixups_header;
3305 end = __end_pci_fixups_header;
3306 break;
3307
3308 case pci_fixup_final:
Myron Stowe95df8b82012-07-13 14:29:00 -06003309 if (!pci_apply_fixup_final_quirks)
3310 return;
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003311 start = __start_pci_fixups_final;
3312 end = __end_pci_fixups_final;
3313 break;
3314
3315 case pci_fixup_enable:
3316 start = __start_pci_fixups_enable;
3317 end = __end_pci_fixups_enable;
3318 break;
3319
3320 case pci_fixup_resume:
3321 start = __start_pci_fixups_resume;
3322 end = __end_pci_fixups_resume;
3323 break;
3324
3325 case pci_fixup_resume_early:
3326 start = __start_pci_fixups_resume_early;
3327 end = __end_pci_fixups_resume_early;
3328 break;
3329
3330 case pci_fixup_suspend:
3331 start = __start_pci_fixups_suspend;
3332 end = __end_pci_fixups_suspend;
3333 break;
3334
Andreas Noever7d2a01b2014-06-03 22:04:09 +02003335 case pci_fixup_suspend_late:
3336 start = __start_pci_fixups_suspend_late;
3337 end = __end_pci_fixups_suspend_late;
3338 break;
3339
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003340 default:
3341 /* stupid compiler warning, you would think with an enum... */
3342 return;
3343 }
3344 pci_do_fixups(dev, start, end);
3345}
Rafael J. Wysocki93177a72010-01-02 22:57:24 +01003346EXPORT_SYMBOL(pci_fixup_device);
David Woodhouse8d86fb22009-10-12 12:48:43 +01003347
Myron Stowe735bff12012-07-09 15:36:46 -06003348
David Woodhouse00010262009-10-12 12:50:34 +01003349static int __init pci_apply_final_quirks(void)
David Woodhouse8d86fb22009-10-12 12:48:43 +01003350{
3351 struct pci_dev *dev = NULL;
Jesse Barnesac1aa472009-10-26 13:20:44 -07003352 u8 cls = 0;
3353 u8 tmp;
3354
3355 if (pci_cache_line_size)
3356 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3357 pci_cache_line_size << 2);
David Woodhouse8d86fb22009-10-12 12:48:43 +01003358
Myron Stowe95df8b82012-07-13 14:29:00 -06003359 pci_apply_fixup_final_quirks = true;
Kulikov Vasiliy4e344b12010-07-03 20:04:39 +04003360 for_each_pci_dev(dev) {
David Woodhouse8d86fb22009-10-12 12:48:43 +01003361 pci_fixup_device(pci_fixup_final, dev);
Jesse Barnesac1aa472009-10-26 13:20:44 -07003362 /*
3363 * If arch hasn't set it explicitly yet, use the CLS
3364 * value shared by all PCI devices. If there's a
3365 * mismatch, fall back to the default value.
3366 */
3367 if (!pci_cache_line_size) {
3368 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3369 if (!cls)
3370 cls = tmp;
3371 if (!tmp || cls == tmp)
3372 continue;
3373
Ryan Desfosses227f0642014-04-18 20:13:50 -04003374 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3375 cls << 2, tmp << 2,
Jesse Barnesac1aa472009-10-26 13:20:44 -07003376 pci_dfl_cache_line_size << 2);
3377 pci_cache_line_size = pci_dfl_cache_line_size;
3378 }
3379 }
Myron Stowe735bff12012-07-09 15:36:46 -06003380
Jesse Barnesac1aa472009-10-26 13:20:44 -07003381 if (!pci_cache_line_size) {
3382 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3383 cls << 2, pci_dfl_cache_line_size << 2);
Csaba Henk2820f332009-12-15 17:55:25 +05303384 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
David Woodhouse8d86fb22009-10-12 12:48:43 +01003385 }
3386
3387 return 0;
3388}
3389
David Woodhousecf6f3bf2009-10-12 12:51:22 +01003390fs_initcall_sync(pci_apply_final_quirks);
Dexuan Cuib9c3b262009-12-07 13:03:21 +08003391
3392/*
3393 * Followings are device-specific reset methods which can be used to
3394 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3395 * not available.
3396 */
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003397static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3398{
Bjorn Helgaas76b57c62012-08-22 09:41:27 -06003399 /*
3400 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3401 *
3402 * The 82599 supports FLR on VFs, but FLR support is reported only
3403 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3404 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3405 */
3406
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003407 if (probe)
3408 return 0;
3409
Casey Leedom4d708ab2013-08-06 15:48:39 +05303410 if (!pci_wait_for_pending_transaction(dev))
3411 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
Bjorn Helgaas76b57c62012-08-22 09:41:27 -06003412
Bjorn Helgaas76b57c62012-08-22 09:41:27 -06003413 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3414
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003415 msleep(100);
3416
3417 return 0;
3418}
3419
Ville Syrjäläaba72dd2015-11-04 23:19:49 +02003420#define SOUTH_CHICKEN2 0xc2004
3421#define PCH_PP_STATUS 0xc7200
3422#define PCH_PP_CONTROL 0xc7204
Xudong Haodf558de2012-04-27 09:16:46 -06003423#define MSG_CTL 0x45010
3424#define NSDE_PWR_STATE 0xd0100
3425#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3426
3427static int reset_ivb_igd(struct pci_dev *dev, int probe)
3428{
3429 void __iomem *mmio_base;
3430 unsigned long timeout;
3431 u32 val;
3432
3433 if (probe)
3434 return 0;
3435
3436 mmio_base = pci_iomap(dev, 0, 0);
3437 if (!mmio_base)
3438 return -ENOMEM;
3439
3440 iowrite32(0x00000002, mmio_base + MSG_CTL);
3441
3442 /*
3443 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3444 * driver loaded sets the right bits. However, this's a reset and
3445 * the bits have been set by i915 previously, so we clobber
3446 * SOUTH_CHICKEN2 register directly here.
3447 */
3448 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3449
3450 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3451 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3452
3453 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3454 do {
3455 val = ioread32(mmio_base + PCH_PP_STATUS);
3456 if ((val & 0xb0000000) == 0)
3457 goto reset_complete;
3458 msleep(10);
3459 } while (time_before(jiffies, timeout));
3460 dev_warn(&dev->dev, "timeout during reset\n");
3461
3462reset_complete:
3463 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3464
3465 pci_iounmap(dev, mmio_base);
3466 return 0;
3467}
3468
Casey Leedom2c6217e2013-08-06 15:48:37 +05303469/*
3470 * Device-specific reset method for Chelsio T4-based adapters.
3471 */
3472static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3473{
3474 u16 old_command;
3475 u16 msix_flags;
3476
3477 /*
3478 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3479 * that we have no device-specific reset method.
3480 */
3481 if ((dev->device & 0xf000) != 0x4000)
3482 return -ENOTTY;
3483
3484 /*
3485 * If this is the "probe" phase, return 0 indicating that we can
3486 * reset this device.
3487 */
3488 if (probe)
3489 return 0;
3490
3491 /*
3492 * T4 can wedge if there are DMAs in flight within the chip and Bus
3493 * Master has been disabled. We need to have it on till the Function
3494 * Level Reset completes. (BUS_MASTER is disabled in
3495 * pci_reset_function()).
3496 */
3497 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3498 pci_write_config_word(dev, PCI_COMMAND,
3499 old_command | PCI_COMMAND_MASTER);
3500
3501 /*
3502 * Perform the actual device function reset, saving and restoring
3503 * configuration information around the reset.
3504 */
3505 pci_save_state(dev);
3506
3507 /*
3508 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3509 * are disabled when an MSI-X interrupt message needs to be delivered.
3510 * So we briefly re-enable MSI-X interrupts for the duration of the
3511 * FLR. The pci_restore_state() below will restore the original
3512 * MSI-X state.
3513 */
3514 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3515 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3516 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3517 msix_flags |
3518 PCI_MSIX_FLAGS_ENABLE |
3519 PCI_MSIX_FLAGS_MASKALL);
3520
3521 /*
3522 * Start of pcie_flr() code sequence. This reset code is a copy of
3523 * the guts of pcie_flr() because that's not an exported function.
3524 */
3525
3526 if (!pci_wait_for_pending_transaction(dev))
3527 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3528
3529 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3530 msleep(100);
3531
3532 /*
3533 * End of pcie_flr() code sequence.
3534 */
3535
3536 /*
3537 * Restore the configuration information (BAR values, etc.) including
3538 * the original PCI Configuration Space Command word, and return
3539 * success.
3540 */
3541 pci_restore_state(dev);
3542 pci_write_config_word(dev, PCI_COMMAND, old_command);
3543 return 0;
3544}
3545
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003546#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
Xudong Haodf558de2012-04-27 09:16:46 -06003547#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3548#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003549
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003550static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003551 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3552 reset_intel_82599_sfp_virtfn },
Xudong Haodf558de2012-04-27 09:16:46 -06003553 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3554 reset_ivb_igd },
3555 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3556 reset_ivb_igd },
Casey Leedom2c6217e2013-08-06 15:48:37 +05303557 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3558 reset_chelsio_generic_dev },
Dexuan Cuib9c3b262009-12-07 13:03:21 +08003559 { 0 }
3560};
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003561
Xudong Haodf558de2012-04-27 09:16:46 -06003562/*
3563 * These device-specific reset methods are here rather than in a driver
3564 * because when a host assigns a device to a guest VM, the host may need
3565 * to reset the device but probably doesn't have a driver for it.
3566 */
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003567int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3568{
Linus Torvaldsdf9d1e82009-12-31 16:44:43 -08003569 const struct pci_dev_reset_methods *i;
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003570
3571 for (i = pci_dev_reset_methods; i->reset; i++) {
3572 if ((i->vendor == dev->vendor ||
3573 i->vendor == (u16)PCI_ANY_ID) &&
3574 (i->device == dev->device ||
3575 i->device == (u16)PCI_ANY_ID))
3576 return i->reset(dev, probe);
3577 }
3578
3579 return -ENOTTY;
3580}
Alex Williamson12ea6ca2012-06-11 05:26:55 +00003581
Alex Williamsonec637fb2014-05-22 17:07:49 -06003582static void quirk_dma_func0_alias(struct pci_dev *dev)
3583{
3584 if (PCI_FUNC(dev->devfn) != 0) {
3585 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
3586 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3587 }
3588}
3589
3590/*
3591 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3592 *
3593 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3594 */
3595DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3596DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3597
Alex Williamsoncc346a42014-05-28 14:54:00 -06003598static void quirk_dma_func1_alias(struct pci_dev *dev)
3599{
3600 if (PCI_FUNC(dev->devfn) != 1) {
3601 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 1);
3602 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3603 }
3604}
3605
3606/*
3607 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3608 * SKUs function 1 is present and is a legacy IDE controller, in other
3609 * SKUs this function is not present, making this a ghost requester.
3610 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3611 */
Sakari Ailus247de692015-05-22 00:03:38 +03003612DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3613 quirk_dma_func1_alias);
Alex Williamsoncc346a42014-05-28 14:54:00 -06003614DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3615 quirk_dma_func1_alias);
3616/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3617DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3618 quirk_dma_func1_alias);
3619/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3620DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3621 quirk_dma_func1_alias);
3622/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3623DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3624 quirk_dma_func1_alias);
3625/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3626DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3627 quirk_dma_func1_alias);
3628/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3629DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3630 quirk_dma_func1_alias);
Jérôme Carreteroc2e0fb92014-06-03 15:41:56 -04003631DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3632 quirk_dma_func1_alias);
Alex Williamsoncc346a42014-05-28 14:54:00 -06003633/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3634DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3635 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3636 quirk_dma_func1_alias);
Tim Sander8b9b9632016-01-19 14:32:29 -06003637/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3638DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
3639 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
3640 quirk_dma_func1_alias);
Alex Williamsoncc346a42014-05-28 14:54:00 -06003641
Alex Williamsonebdb51e2014-05-22 17:08:07 -06003642/*
Alex Williamsond3d2ab42015-01-13 11:26:50 -07003643 * Some devices DMA with the wrong devfn, not just the wrong function.
3644 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3645 * the alias is "fixed" and independent of the device devfn.
3646 *
3647 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3648 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3649 * single device on the secondary bus. In reality, the single exposed
3650 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3651 * that provides a bridge to the internal bus of the I/O processor. The
3652 * controller supports private devices, which can be hidden from PCI config
3653 * space. In the case of the Adaptec 3405, a private device at 01.0
3654 * appears to be the DMA engine, which therefore needs to become a DMA
3655 * alias for the device.
3656 */
3657static const struct pci_device_id fixed_dma_alias_tbl[] = {
3658 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3659 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3660 .driver_data = PCI_DEVFN(1, 0) },
3661 { 0 }
3662};
3663
3664static void quirk_fixed_dma_alias(struct pci_dev *dev)
3665{
3666 const struct pci_device_id *id;
3667
3668 id = pci_match_id(fixed_dma_alias_tbl, dev);
3669 if (id) {
3670 dev->dma_alias_devfn = id->driver_data;
3671 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3672 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
3673 PCI_SLOT(dev->dma_alias_devfn),
3674 PCI_FUNC(dev->dma_alias_devfn));
3675 }
3676}
3677
3678DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3679
3680/*
Alex Williamsonebdb51e2014-05-22 17:08:07 -06003681 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3682 * using the wrong DMA alias for the device. Some of these devices can be
3683 * used as either forward or reverse bridges, so we need to test whether the
3684 * device is operating in the correct mode. We could probably apply this
3685 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3686 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3687 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3688 */
3689static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3690{
3691 if (!pci_is_root_bus(pdev->bus) &&
3692 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3693 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3694 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3695 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3696}
3697/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3698DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3699 quirk_use_pcie_bridge_dma_alias);
3700/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3701DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
Alex Williamson98ca50d2014-06-09 12:43:25 -06003702/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3703DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
Alex Williamson8ab4abb2014-07-05 15:26:52 -06003704/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3705DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
Alex Williamsonebdb51e2014-05-22 17:08:07 -06003706
Alex Williamson15b100d2013-06-27 16:40:00 -06003707/*
Krzysztof =?utf-8?Q?Ha=C5=82asa?=3657ceb2015-06-19 10:00:15 +02003708 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
3709 * class code. Fix it.
3710 */
3711static void quirk_tw686x_class(struct pci_dev *pdev)
3712{
3713 u32 class = pdev->class;
3714
3715 /* Use "Multimedia controller" class */
3716 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
3717 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
3718 class, pdev->class);
3719}
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05003720DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
Krzysztof =?utf-8?Q?Ha=C5=82asa?=3657ceb2015-06-19 10:00:15 +02003721 quirk_tw686x_class);
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05003722DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
Krzysztof =?utf-8?Q?Ha=C5=82asa?=3657ceb2015-06-19 10:00:15 +02003723 quirk_tw686x_class);
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05003724DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
Krzysztof =?utf-8?Q?Ha=C5=82asa?=3657ceb2015-06-19 10:00:15 +02003725 quirk_tw686x_class);
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05003726DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
Krzysztof =?utf-8?Q?Ha=C5=82asa?=3657ceb2015-06-19 10:00:15 +02003727 quirk_tw686x_class);
3728
3729/*
Hariprasad Shenaic56d4452015-10-18 19:55:04 +05303730 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
3731 * values for the Attribute as were supplied in the header of the
3732 * corresponding Request, except as explicitly allowed when IDO is used."
3733 *
3734 * If a non-compliant device generates a completion with a different
3735 * attribute than the request, the receiver may accept it (which itself
3736 * seems non-compliant based on sec 2.3.2), or it may handle it as a
3737 * Malformed TLP or an Unexpected Completion, which will probably lead to a
3738 * device access timeout.
3739 *
3740 * If the non-compliant device generates completions with zero attributes
3741 * (instead of copying the attributes from the request), we can work around
3742 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
3743 * upstream devices so they always generate requests with zero attributes.
3744 *
3745 * This affects other devices under the same Root Port, but since these
3746 * attributes are performance hints, there should be no functional problem.
3747 *
3748 * Note that Configuration Space accesses are never supposed to have TLP
3749 * Attributes, so we're safe waiting till after any Configuration Space
3750 * accesses to do the Root Port fixup.
3751 */
3752static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
3753{
3754 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
3755
3756 if (!root_port) {
3757 dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n");
3758 return;
3759 }
3760
3761 dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
3762 dev_name(&pdev->dev));
3763 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
3764 PCI_EXP_DEVCTL_RELAX_EN |
3765 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
3766}
3767
3768/*
3769 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
3770 * Completion it generates.
3771 */
3772static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
3773{
3774 /*
3775 * This mask/compare operation selects for Physical Function 4 on a
3776 * T5. We only need to fix up the Root Port once for any of the
3777 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
3778 * 0x54xx so we use that one,
3779 */
3780 if ((pdev->device & 0xff00) == 0x5400)
3781 quirk_disable_root_port_attributes(pdev);
3782}
3783DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3784 quirk_chelsio_T5_disable_root_port_attributes);
3785
3786/*
Alex Williamson15b100d2013-06-27 16:40:00 -06003787 * AMD has indicated that the devices below do not support peer-to-peer
3788 * in any system where they are found in the southbridge with an AMD
3789 * IOMMU in the system. Multifunction devices that do not support
3790 * peer-to-peer between functions can claim to support a subset of ACS.
3791 * Such devices effectively enable request redirect (RR) and completion
3792 * redirect (CR) since all transactions are redirected to the upstream
3793 * root complex.
3794 *
3795 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
3796 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
3797 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
3798 *
3799 * 1002:4385 SBx00 SMBus Controller
3800 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
3801 * 1002:4383 SBx00 Azalia (Intel HDA)
3802 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
3803 * 1002:4384 SBx00 PCI to PCI Bridge
3804 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
Marti Raudsepp3587e622014-10-02 08:50:31 -06003805 *
3806 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
3807 *
3808 * 1022:780f [AMD] FCH PCI Bridge
3809 * 1022:7809 [AMD] FCH USB OHCI Controller
Alex Williamson15b100d2013-06-27 16:40:00 -06003810 */
3811static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
3812{
3813#ifdef CONFIG_ACPI
3814 struct acpi_table_header *header = NULL;
3815 acpi_status status;
3816
3817 /* Targeting multifunction devices on the SB (appears on root bus) */
3818 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
3819 return -ENODEV;
3820
3821 /* The IVRS table describes the AMD IOMMU */
3822 status = acpi_get_table("IVRS", 0, &header);
3823 if (ACPI_FAILURE(status))
3824 return -ENODEV;
3825
3826 /* Filter out flags not applicable to multifunction */
3827 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
3828
3829 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
3830#else
3831 return -ENODEV;
3832#endif
3833}
3834
Manish Jaggib404bcf2016-01-30 01:33:58 +05303835static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
3836{
3837 /*
3838 * Cavium devices matching this quirk do not perform peer-to-peer
3839 * with other functions, allowing masking out these bits as if they
3840 * were unimplemented in the ACS capability.
3841 */
3842 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
3843 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
3844
3845 return acs_flags ? 0 : 1;
3846}
3847
Alex Williamsond99321b2014-02-03 14:27:46 -07003848/*
3849 * Many Intel PCH root ports do provide ACS-like features to disable peer
3850 * transactions and validate bus numbers in requests, but do not provide an
3851 * actual PCIe ACS capability. This is the list of device IDs known to fall
3852 * into that category as provided by Intel in Red Hat bugzilla 1037684.
3853 */
3854static const u16 pci_quirk_intel_pch_acs_ids[] = {
3855 /* Ibexpeak PCH */
3856 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
3857 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
3858 /* Cougarpoint PCH */
3859 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
3860 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
3861 /* Pantherpoint PCH */
3862 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
3863 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
3864 /* Lynxpoint-H PCH */
3865 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
3866 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
3867 /* Lynxpoint-LP PCH */
3868 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
3869 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
3870 /* Wildcat PCH */
3871 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
3872 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
Alex Williamson1a30fd02014-03-31 12:21:38 -06003873 /* Patsburg (X79) PCH */
3874 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
Alex Williamson78e88352015-01-22 11:15:43 -07003875 /* Wellsburg (X99) PCH */
3876 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
3877 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
Alex Williamsondca230d2015-05-01 13:20:13 -06003878 /* Lynx Point (9 series) PCH */
3879 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
Alex Williamsond99321b2014-02-03 14:27:46 -07003880};
3881
3882static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
3883{
3884 int i;
3885
3886 /* Filter out a few obvious non-matches first */
3887 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
3888 return false;
3889
3890 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
3891 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
3892 return true;
3893
3894 return false;
3895}
3896
3897#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
3898
3899static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
3900{
3901 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
3902 INTEL_PCH_ACS_FLAGS : 0;
3903
3904 if (!pci_quirk_intel_pch_acs_match(dev))
3905 return -ENOTTY;
3906
3907 return acs_flags & ~flags ? 0 : 1;
3908}
3909
Alex Williamson100ebb22014-09-26 17:07:59 -06003910static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
Alex Williamson89b51cb2014-09-17 08:59:36 -06003911{
3912 /*
3913 * SV, TB, and UF are not relevant to multifunction endpoints.
3914 *
Alex Williamson100ebb22014-09-26 17:07:59 -06003915 * Multifunction devices are only required to implement RR, CR, and DT
3916 * in their ACS capability if they support peer-to-peer transactions.
3917 * Devices matching this quirk have been verified by the vendor to not
3918 * perform peer-to-peer with other functions, allowing us to mask out
3919 * these bits as if they were unimplemented in the ACS capability.
Alex Williamson89b51cb2014-09-17 08:59:36 -06003920 */
3921 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
3922 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
3923
3924 return acs_flags ? 0 : 1;
3925}
3926
Alex Williamsonad805752012-06-11 05:27:07 +00003927static const struct pci_dev_acs_enabled {
3928 u16 vendor;
3929 u16 device;
3930 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3931} pci_dev_acs_enabled[] = {
Alex Williamson15b100d2013-06-27 16:40:00 -06003932 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
3933 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
3934 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
3935 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
3936 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
3937 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
Marti Raudsepp3587e622014-10-02 08:50:31 -06003938 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
3939 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
Alex Williamson100ebb22014-09-26 17:07:59 -06003940 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
3941 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
3942 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
3943 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
3944 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
3945 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
3946 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
3947 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
3948 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
3949 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
3950 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
3951 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
3952 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
3953 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
3954 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
3955 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
3956 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
3957 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
3958 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
3959 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
3960 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
3961 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
Alex Williamsond7488042015-03-20 12:27:57 -06003962 /* 82580 */
3963 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
3964 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
3965 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
3966 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
3967 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
3968 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
3969 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
3970 /* 82576 */
3971 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
3972 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
3973 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
3974 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
3975 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
3976 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
3977 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
3978 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
3979 /* 82575 */
3980 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
3981 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
3982 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
3983 /* I350 */
3984 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
3985 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
3986 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
3987 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
3988 /* 82571 (Quads omitted due to non-ACS switch) */
3989 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
3990 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
3991 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
3992 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
Alex Williamson95e16582015-08-10 12:32:04 -06003993 /* I219 */
3994 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
3995 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
Alex Williamsond7488042015-03-20 12:27:57 -06003996 /* Intel PCH root ports */
Alex Williamsond99321b2014-02-03 14:27:46 -07003997 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
Vasundhara Volam6a3763d2015-01-13 01:22:23 -05003998 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
3999 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
Manish Jaggib404bcf2016-01-30 01:33:58 +05304000 /* Cavium ThunderX */
4001 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
Alex Williamsonad805752012-06-11 05:27:07 +00004002 { 0 }
4003};
4004
4005int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4006{
4007 const struct pci_dev_acs_enabled *i;
4008 int ret;
4009
4010 /*
4011 * Allow devices that do not expose standard PCIe ACS capabilities
4012 * or control to indicate their support here. Multi-function express
4013 * devices which do not allow internal peer-to-peer between functions,
4014 * but do not implement PCIe ACS may wish to return true here.
4015 */
4016 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4017 if ((i->vendor == dev->vendor ||
4018 i->vendor == (u16)PCI_ANY_ID) &&
4019 (i->device == dev->device ||
4020 i->device == (u16)PCI_ANY_ID)) {
4021 ret = i->acs_enabled(dev, acs_flags);
4022 if (ret >= 0)
4023 return ret;
4024 }
4025 }
4026
4027 return -ENOTTY;
4028}
Alex Williamson2c744242014-02-03 14:27:33 -07004029
Alex Williamsond99321b2014-02-03 14:27:46 -07004030/* Config space offset of Root Complex Base Address register */
4031#define INTEL_LPC_RCBA_REG 0xf0
4032/* 31:14 RCBA address */
4033#define INTEL_LPC_RCBA_MASK 0xffffc000
4034/* RCBA Enable */
4035#define INTEL_LPC_RCBA_ENABLE (1 << 0)
4036
4037/* Backbone Scratch Pad Register */
4038#define INTEL_BSPR_REG 0x1104
4039/* Backbone Peer Non-Posted Disable */
4040#define INTEL_BSPR_REG_BPNPD (1 << 8)
4041/* Backbone Peer Posted Disable */
4042#define INTEL_BSPR_REG_BPPD (1 << 9)
4043
4044/* Upstream Peer Decode Configuration Register */
4045#define INTEL_UPDCR_REG 0x1114
4046/* 5:0 Peer Decode Enable bits */
4047#define INTEL_UPDCR_REG_MASK 0x3f
4048
4049static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4050{
4051 u32 rcba, bspr, updcr;
4052 void __iomem *rcba_mem;
4053
4054 /*
4055 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4056 * are D28:F* and therefore get probed before LPC, thus we can't
4057 * use pci_get_slot/pci_read_config_dword here.
4058 */
4059 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4060 INTEL_LPC_RCBA_REG, &rcba);
4061 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4062 return -EINVAL;
4063
4064 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4065 PAGE_ALIGN(INTEL_UPDCR_REG));
4066 if (!rcba_mem)
4067 return -ENOMEM;
4068
4069 /*
4070 * The BSPR can disallow peer cycles, but it's set by soft strap and
4071 * therefore read-only. If both posted and non-posted peer cycles are
4072 * disallowed, we're ok. If either are allowed, then we need to use
4073 * the UPDCR to disable peer decodes for each port. This provides the
4074 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4075 */
4076 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4077 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4078 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4079 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4080 if (updcr & INTEL_UPDCR_REG_MASK) {
4081 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
4082 updcr &= ~INTEL_UPDCR_REG_MASK;
4083 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4084 }
4085 }
4086
4087 iounmap(rcba_mem);
4088 return 0;
4089}
4090
4091/* Miscellaneous Port Configuration register */
4092#define INTEL_MPC_REG 0xd8
4093/* MPC: Invalid Receive Bus Number Check Enable */
4094#define INTEL_MPC_REG_IRBNCE (1 << 26)
4095
4096static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4097{
4098 u32 mpc;
4099
4100 /*
4101 * When enabled, the IRBNCE bit of the MPC register enables the
4102 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4103 * ensures that requester IDs fall within the bus number range
4104 * of the bridge. Enable if not already.
4105 */
4106 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4107 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4108 dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
4109 mpc |= INTEL_MPC_REG_IRBNCE;
4110 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4111 }
4112}
4113
4114static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4115{
4116 if (!pci_quirk_intel_pch_acs_match(dev))
4117 return -ENOTTY;
4118
4119 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4120 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
4121 return 0;
4122 }
4123
4124 pci_quirk_enable_intel_rp_mpc_acs(dev);
4125
4126 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4127
4128 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
4129
4130 return 0;
4131}
4132
Alex Williamson2c744242014-02-03 14:27:33 -07004133static const struct pci_dev_enable_acs {
4134 u16 vendor;
4135 u16 device;
4136 int (*enable_acs)(struct pci_dev *dev);
4137} pci_dev_enable_acs[] = {
Alex Williamsond99321b2014-02-03 14:27:46 -07004138 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
Alex Williamson2c744242014-02-03 14:27:33 -07004139 { 0 }
4140};
4141
4142void pci_dev_specific_enable_acs(struct pci_dev *dev)
4143{
4144 const struct pci_dev_enable_acs *i;
4145 int ret;
4146
4147 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4148 if ((i->vendor == dev->vendor ||
4149 i->vendor == (u16)PCI_ANY_ID) &&
4150 (i->device == dev->device ||
4151 i->device == (u16)PCI_ANY_ID)) {
4152 ret = i->enable_acs(dev);
4153 if (ret >= 0)
4154 return;
4155 }
4156 }
4157}
Tadeusz Struk3388a612015-08-07 11:34:42 -07004158
4159/*
4160 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with
4161 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4162 * Next Capability pointer in the MSI Capability Structure should point to
4163 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4164 * the list.
4165 */
4166static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4167{
4168 int pos, i = 0;
4169 u8 next_cap;
4170 u16 reg16, *cap;
4171 struct pci_cap_saved_state *state;
4172
4173 /* Bail if the hardware bug is fixed */
4174 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4175 return;
4176
4177 /* Bail if MSI Capability Structure is not found for some reason */
4178 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4179 if (!pos)
4180 return;
4181
4182 /*
4183 * Bail if Next Capability pointer in the MSI Capability Structure
4184 * is not the expected incorrect 0x00.
4185 */
4186 pci_read_config_byte(pdev, pos + 1, &next_cap);
4187 if (next_cap)
4188 return;
4189
4190 /*
4191 * PCIe Capability Structure is expected to be at 0x50 and should
4192 * terminate the list (Next Capability pointer is 0x00). Verify
4193 * Capability Id and Next Capability pointer is as expected.
4194 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4195 * to correctly set kernel data structures which have already been
4196 * set incorrectly due to the hardware bug.
4197 */
4198 pos = 0x50;
4199 pci_read_config_word(pdev, pos, &reg16);
4200 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4201 u32 status;
4202#ifndef PCI_EXP_SAVE_REGS
4203#define PCI_EXP_SAVE_REGS 7
4204#endif
4205 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4206
4207 pdev->pcie_cap = pos;
4208 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
4209 pdev->pcie_flags_reg = reg16;
4210 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
4211 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4212
4213 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4214 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4215 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4216 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4217
4218 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4219 return;
4220
4221 /*
4222 * Save PCIE cap
4223 */
4224 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4225 if (!state)
4226 return;
4227
4228 state->cap.cap_nr = PCI_CAP_ID_EXP;
4229 state->cap.cap_extended = 0;
4230 state->cap.size = size;
4231 cap = (u16 *)&state->cap.data[0];
4232 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4233 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4234 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4235 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4236 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4237 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4238 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4239 hlist_add_head(&state->next, &pdev->saved_cap_space);
4240 }
4241}
4242DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);