Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1 | /* |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 2 | * Copyright © 2006-2014 Intel Corporation. |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 13 | * Authors: David Woodhouse <dwmw2@infradead.org>, |
| 14 | * Ashok Raj <ashok.raj@intel.com>, |
| 15 | * Shaohua Li <shaohua.li@intel.com>, |
| 16 | * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>, |
| 17 | * Fenghua Yu <fenghua.yu@intel.com> |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 18 | * Joerg Roedel <jroedel@suse.de> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 19 | */ |
| 20 | |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 21 | #define pr_fmt(fmt) "DMAR: " fmt |
| 22 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 23 | #include <linux/init.h> |
| 24 | #include <linux/bitmap.h> |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 25 | #include <linux/debugfs.h> |
Paul Gortmaker | 54485c3 | 2011-10-29 10:26:25 -0400 | [diff] [blame] | 26 | #include <linux/export.h> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 27 | #include <linux/slab.h> |
| 28 | #include <linux/irq.h> |
| 29 | #include <linux/interrupt.h> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 30 | #include <linux/spinlock.h> |
| 31 | #include <linux/pci.h> |
| 32 | #include <linux/dmar.h> |
| 33 | #include <linux/dma-mapping.h> |
| 34 | #include <linux/mempool.h> |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 35 | #include <linux/memory.h> |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 36 | #include <linux/cpu.h> |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 37 | #include <linux/timer.h> |
Dan Williams | dfddb96 | 2015-10-09 18:16:46 -0400 | [diff] [blame] | 38 | #include <linux/io.h> |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 39 | #include <linux/iova.h> |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 40 | #include <linux/iommu.h> |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 41 | #include <linux/intel-iommu.h> |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 42 | #include <linux/syscore_ops.h> |
Shane Wang | 69575d3 | 2009-09-01 18:25:07 -0700 | [diff] [blame] | 43 | #include <linux/tboot.h> |
Stephen Rothwell | adb2fe0 | 2009-08-31 15:24:23 +1000 | [diff] [blame] | 44 | #include <linux/dmi.h> |
Joerg Roedel | 5cdede2 | 2011-04-04 15:55:18 +0200 | [diff] [blame] | 45 | #include <linux/pci-ats.h> |
Tejun Heo | 0ee332c | 2011-12-08 10:22:09 -0800 | [diff] [blame] | 46 | #include <linux/memblock.h> |
Akinobu Mita | 3674643 | 2014-06-04 16:06:51 -0700 | [diff] [blame] | 47 | #include <linux/dma-contiguous.h> |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 48 | #include <linux/crash_dump.h> |
Suresh Siddha | 8a8f422 | 2012-03-30 11:47:08 -0700 | [diff] [blame] | 49 | #include <asm/irq_remapping.h> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 50 | #include <asm/cacheflush.h> |
FUJITA Tomonori | 46a7fa2 | 2008-07-11 10:23:42 +0900 | [diff] [blame] | 51 | #include <asm/iommu.h> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 52 | |
Joerg Roedel | 078e1ee | 2012-09-26 12:44:43 +0200 | [diff] [blame] | 53 | #include "irq_remapping.h" |
| 54 | |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 55 | #define ROOT_SIZE VTD_PAGE_SIZE |
| 56 | #define CONTEXT_SIZE VTD_PAGE_SIZE |
| 57 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 58 | #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY) |
David Woodhouse | 18436af | 2015-03-25 15:05:47 +0000 | [diff] [blame] | 59 | #define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 60 | #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 61 | #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 62 | |
| 63 | #define IOAPIC_RANGE_START (0xfee00000) |
| 64 | #define IOAPIC_RANGE_END (0xfeefffff) |
| 65 | #define IOVA_START_ADDR (0x1000) |
| 66 | |
| 67 | #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 |
| 68 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 69 | #define MAX_AGAW_WIDTH 64 |
Jiang Liu | 5c645b3 | 2014-01-06 14:18:12 +0800 | [diff] [blame] | 70 | #define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT) |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 71 | |
David Woodhouse | 2ebe315 | 2009-09-19 07:34:04 -0700 | [diff] [blame] | 72 | #define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1) |
| 73 | #define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1) |
| 74 | |
| 75 | /* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR |
| 76 | to match. That way, we can use 'unsigned long' for PFNs with impunity. */ |
| 77 | #define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \ |
| 78 | __DOMAIN_MAX_PFN(gaw), (unsigned long)-1)) |
| 79 | #define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 80 | |
Robin Murphy | 1b72250 | 2015-01-12 17:51:15 +0000 | [diff] [blame] | 81 | /* IO virtual address start page frame number */ |
| 82 | #define IOVA_START_PFN (1) |
| 83 | |
Mark McLoughlin | f27be03 | 2008-11-20 15:49:43 +0000 | [diff] [blame] | 84 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 85 | #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) |
Yang Hongyang | 6a35528 | 2009-04-06 19:01:13 -0700 | [diff] [blame] | 86 | #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64)) |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 87 | |
Andrew Morton | df08cdc | 2010-09-22 13:05:11 -0700 | [diff] [blame] | 88 | /* page table handling */ |
| 89 | #define LEVEL_STRIDE (9) |
| 90 | #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1) |
| 91 | |
Ohad Ben-Cohen | 6d1c56a | 2011-11-10 11:32:30 +0200 | [diff] [blame] | 92 | /* |
| 93 | * This bitmap is used to advertise the page sizes our hardware support |
| 94 | * to the IOMMU core, which will then use this information to split |
| 95 | * physically contiguous memory regions it is mapping into page sizes |
| 96 | * that we support. |
| 97 | * |
| 98 | * Traditionally the IOMMU core just handed us the mappings directly, |
| 99 | * after making sure the size is an order of a 4KiB page and that the |
| 100 | * mapping has natural alignment. |
| 101 | * |
| 102 | * To retain this behavior, we currently advertise that we support |
| 103 | * all page sizes that are an order of 4KiB. |
| 104 | * |
| 105 | * If at some point we'd like to utilize the IOMMU core's new behavior, |
| 106 | * we could change this to advertise the real page sizes we support. |
| 107 | */ |
| 108 | #define INTEL_IOMMU_PGSIZES (~0xFFFUL) |
| 109 | |
Andrew Morton | df08cdc | 2010-09-22 13:05:11 -0700 | [diff] [blame] | 110 | static inline int agaw_to_level(int agaw) |
| 111 | { |
| 112 | return agaw + 2; |
| 113 | } |
| 114 | |
| 115 | static inline int agaw_to_width(int agaw) |
| 116 | { |
Jiang Liu | 5c645b3 | 2014-01-06 14:18:12 +0800 | [diff] [blame] | 117 | return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH); |
Andrew Morton | df08cdc | 2010-09-22 13:05:11 -0700 | [diff] [blame] | 118 | } |
| 119 | |
| 120 | static inline int width_to_agaw(int width) |
| 121 | { |
Jiang Liu | 5c645b3 | 2014-01-06 14:18:12 +0800 | [diff] [blame] | 122 | return DIV_ROUND_UP(width - 30, LEVEL_STRIDE); |
Andrew Morton | df08cdc | 2010-09-22 13:05:11 -0700 | [diff] [blame] | 123 | } |
| 124 | |
| 125 | static inline unsigned int level_to_offset_bits(int level) |
| 126 | { |
| 127 | return (level - 1) * LEVEL_STRIDE; |
| 128 | } |
| 129 | |
| 130 | static inline int pfn_level_offset(unsigned long pfn, int level) |
| 131 | { |
| 132 | return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK; |
| 133 | } |
| 134 | |
| 135 | static inline unsigned long level_mask(int level) |
| 136 | { |
| 137 | return -1UL << level_to_offset_bits(level); |
| 138 | } |
| 139 | |
| 140 | static inline unsigned long level_size(int level) |
| 141 | { |
| 142 | return 1UL << level_to_offset_bits(level); |
| 143 | } |
| 144 | |
| 145 | static inline unsigned long align_to_level(unsigned long pfn, int level) |
| 146 | { |
| 147 | return (pfn + level_size(level) - 1) & level_mask(level); |
| 148 | } |
David Woodhouse | fd18de5 | 2009-05-10 23:57:41 +0100 | [diff] [blame] | 149 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 150 | static inline unsigned long lvl_to_nr_pages(unsigned int lvl) |
| 151 | { |
Jiang Liu | 5c645b3 | 2014-01-06 14:18:12 +0800 | [diff] [blame] | 152 | return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH); |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 153 | } |
| 154 | |
David Woodhouse | dd4e831 | 2009-06-27 16:21:20 +0100 | [diff] [blame] | 155 | /* VT-d pages must always be _smaller_ than MM pages. Otherwise things |
| 156 | are never going to work. */ |
| 157 | static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn) |
| 158 | { |
| 159 | return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT); |
| 160 | } |
| 161 | |
| 162 | static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn) |
| 163 | { |
| 164 | return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT); |
| 165 | } |
| 166 | static inline unsigned long page_to_dma_pfn(struct page *pg) |
| 167 | { |
| 168 | return mm_to_dma_pfn(page_to_pfn(pg)); |
| 169 | } |
| 170 | static inline unsigned long virt_to_dma_pfn(void *p) |
| 171 | { |
| 172 | return page_to_dma_pfn(virt_to_page(p)); |
| 173 | } |
| 174 | |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 175 | /* global iommu list, set NULL for ignored DMAR units */ |
| 176 | static struct intel_iommu **g_iommus; |
| 177 | |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 178 | static void __init check_tylersburg_isoch(void); |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 179 | static int rwbf_quirk; |
| 180 | |
Mark McLoughlin | 46b08e1 | 2008-11-20 15:49:44 +0000 | [diff] [blame] | 181 | /* |
Joseph Cihula | b779260 | 2011-05-03 00:08:37 -0700 | [diff] [blame] | 182 | * set to 1 to panic kernel if can't successfully enable VT-d |
| 183 | * (used when kernel is launched w/ TXT) |
| 184 | */ |
| 185 | static int force_on = 0; |
| 186 | |
| 187 | /* |
Mark McLoughlin | 46b08e1 | 2008-11-20 15:49:44 +0000 | [diff] [blame] | 188 | * 0: Present |
| 189 | * 1-11: Reserved |
| 190 | * 12-63: Context Ptr (12 - (haw-1)) |
| 191 | * 64-127: Reserved |
| 192 | */ |
| 193 | struct root_entry { |
David Woodhouse | 03ecc32 | 2015-02-13 14:35:21 +0000 | [diff] [blame] | 194 | u64 lo; |
| 195 | u64 hi; |
Mark McLoughlin | 46b08e1 | 2008-11-20 15:49:44 +0000 | [diff] [blame] | 196 | }; |
| 197 | #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry)) |
Mark McLoughlin | 46b08e1 | 2008-11-20 15:49:44 +0000 | [diff] [blame] | 198 | |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 199 | /* |
| 200 | * Take a root_entry and return the Lower Context Table Pointer (LCTP) |
| 201 | * if marked present. |
| 202 | */ |
| 203 | static phys_addr_t root_entry_lctp(struct root_entry *re) |
| 204 | { |
| 205 | if (!(re->lo & 1)) |
| 206 | return 0; |
Mark McLoughlin | 46b08e1 | 2008-11-20 15:49:44 +0000 | [diff] [blame] | 207 | |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 208 | return re->lo & VTD_PAGE_MASK; |
| 209 | } |
| 210 | |
| 211 | /* |
| 212 | * Take a root_entry and return the Upper Context Table Pointer (UCTP) |
| 213 | * if marked present. |
| 214 | */ |
| 215 | static phys_addr_t root_entry_uctp(struct root_entry *re) |
| 216 | { |
| 217 | if (!(re->hi & 1)) |
| 218 | return 0; |
| 219 | |
| 220 | return re->hi & VTD_PAGE_MASK; |
| 221 | } |
Mark McLoughlin | 7a8fc25 | 2008-11-20 15:49:45 +0000 | [diff] [blame] | 222 | /* |
| 223 | * low 64 bits: |
| 224 | * 0: present |
| 225 | * 1: fault processing disable |
| 226 | * 2-3: translation type |
| 227 | * 12-63: address space root |
| 228 | * high 64 bits: |
| 229 | * 0-2: address width |
| 230 | * 3-6: aval |
| 231 | * 8-23: domain id |
| 232 | */ |
| 233 | struct context_entry { |
| 234 | u64 lo; |
| 235 | u64 hi; |
| 236 | }; |
Mark McLoughlin | 7a8fc25 | 2008-11-20 15:49:45 +0000 | [diff] [blame] | 237 | |
Joerg Roedel | cf484d0 | 2015-06-12 12:21:46 +0200 | [diff] [blame] | 238 | static inline void context_clear_pasid_enable(struct context_entry *context) |
| 239 | { |
| 240 | context->lo &= ~(1ULL << 11); |
| 241 | } |
| 242 | |
| 243 | static inline bool context_pasid_enabled(struct context_entry *context) |
| 244 | { |
| 245 | return !!(context->lo & (1ULL << 11)); |
| 246 | } |
| 247 | |
| 248 | static inline void context_set_copied(struct context_entry *context) |
| 249 | { |
| 250 | context->hi |= (1ull << 3); |
| 251 | } |
| 252 | |
| 253 | static inline bool context_copied(struct context_entry *context) |
| 254 | { |
| 255 | return !!(context->hi & (1ULL << 3)); |
| 256 | } |
| 257 | |
| 258 | static inline bool __context_present(struct context_entry *context) |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 259 | { |
| 260 | return (context->lo & 1); |
| 261 | } |
Joerg Roedel | cf484d0 | 2015-06-12 12:21:46 +0200 | [diff] [blame] | 262 | |
| 263 | static inline bool context_present(struct context_entry *context) |
| 264 | { |
| 265 | return context_pasid_enabled(context) ? |
| 266 | __context_present(context) : |
| 267 | __context_present(context) && !context_copied(context); |
| 268 | } |
| 269 | |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 270 | static inline void context_set_present(struct context_entry *context) |
| 271 | { |
| 272 | context->lo |= 1; |
| 273 | } |
| 274 | |
| 275 | static inline void context_set_fault_enable(struct context_entry *context) |
| 276 | { |
| 277 | context->lo &= (((u64)-1) << 2) | 1; |
| 278 | } |
| 279 | |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 280 | static inline void context_set_translation_type(struct context_entry *context, |
| 281 | unsigned long value) |
| 282 | { |
| 283 | context->lo &= (((u64)-1) << 4) | 3; |
| 284 | context->lo |= (value & 3) << 2; |
| 285 | } |
| 286 | |
| 287 | static inline void context_set_address_root(struct context_entry *context, |
| 288 | unsigned long value) |
| 289 | { |
Li, Zhen-Hua | 1a2262f | 2014-11-05 15:30:19 +0800 | [diff] [blame] | 290 | context->lo &= ~VTD_PAGE_MASK; |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 291 | context->lo |= value & VTD_PAGE_MASK; |
| 292 | } |
| 293 | |
| 294 | static inline void context_set_address_width(struct context_entry *context, |
| 295 | unsigned long value) |
| 296 | { |
| 297 | context->hi |= value & 7; |
| 298 | } |
| 299 | |
| 300 | static inline void context_set_domain_id(struct context_entry *context, |
| 301 | unsigned long value) |
| 302 | { |
| 303 | context->hi |= (value & ((1 << 16) - 1)) << 8; |
| 304 | } |
| 305 | |
Joerg Roedel | dbcd861 | 2015-06-12 12:02:09 +0200 | [diff] [blame] | 306 | static inline int context_domain_id(struct context_entry *c) |
| 307 | { |
| 308 | return((c->hi >> 8) & 0xffff); |
| 309 | } |
| 310 | |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 311 | static inline void context_clear_entry(struct context_entry *context) |
| 312 | { |
| 313 | context->lo = 0; |
| 314 | context->hi = 0; |
| 315 | } |
Mark McLoughlin | 7a8fc25 | 2008-11-20 15:49:45 +0000 | [diff] [blame] | 316 | |
Mark McLoughlin | 622ba12 | 2008-11-20 15:49:46 +0000 | [diff] [blame] | 317 | /* |
| 318 | * 0: readable |
| 319 | * 1: writable |
| 320 | * 2-6: reserved |
| 321 | * 7: super page |
Sheng Yang | 9cf06697 | 2009-03-18 15:33:07 +0800 | [diff] [blame] | 322 | * 8-10: available |
| 323 | * 11: snoop behavior |
Mark McLoughlin | 622ba12 | 2008-11-20 15:49:46 +0000 | [diff] [blame] | 324 | * 12-63: Host physcial address |
| 325 | */ |
| 326 | struct dma_pte { |
| 327 | u64 val; |
| 328 | }; |
Mark McLoughlin | 622ba12 | 2008-11-20 15:49:46 +0000 | [diff] [blame] | 329 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 330 | static inline void dma_clear_pte(struct dma_pte *pte) |
| 331 | { |
| 332 | pte->val = 0; |
| 333 | } |
| 334 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 335 | static inline u64 dma_pte_addr(struct dma_pte *pte) |
| 336 | { |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 337 | #ifdef CONFIG_64BIT |
| 338 | return pte->val & VTD_PAGE_MASK; |
| 339 | #else |
| 340 | /* Must have a full atomic 64-bit read */ |
David Woodhouse | 1a8bd48 | 2010-08-10 01:38:53 +0100 | [diff] [blame] | 341 | return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK; |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 342 | #endif |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 343 | } |
| 344 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 345 | static inline bool dma_pte_present(struct dma_pte *pte) |
| 346 | { |
| 347 | return (pte->val & 3) != 0; |
| 348 | } |
Mark McLoughlin | 622ba12 | 2008-11-20 15:49:46 +0000 | [diff] [blame] | 349 | |
Allen Kay | 4399c8b | 2011-10-14 12:32:46 -0700 | [diff] [blame] | 350 | static inline bool dma_pte_superpage(struct dma_pte *pte) |
| 351 | { |
Joerg Roedel | c3c75eb | 2014-07-04 11:19:10 +0200 | [diff] [blame] | 352 | return (pte->val & DMA_PTE_LARGE_PAGE); |
Allen Kay | 4399c8b | 2011-10-14 12:32:46 -0700 | [diff] [blame] | 353 | } |
| 354 | |
David Woodhouse | 75e6bf9 | 2009-07-02 11:21:16 +0100 | [diff] [blame] | 355 | static inline int first_pte_in_page(struct dma_pte *pte) |
| 356 | { |
| 357 | return !((unsigned long)pte & ~VTD_PAGE_MASK); |
| 358 | } |
| 359 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 360 | /* |
| 361 | * This domain is a statically identity mapping domain. |
| 362 | * 1. This domain creats a static 1:1 mapping to all usable memory. |
| 363 | * 2. It maps to each iommu if successful. |
| 364 | * 3. Each iommu mapps to this domain if successful. |
| 365 | */ |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 366 | static struct dmar_domain *si_domain; |
| 367 | static int hw_pass_through = 1; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 368 | |
Joerg Roedel | 28ccce0 | 2015-07-21 14:45:31 +0200 | [diff] [blame] | 369 | /* |
| 370 | * Domain represents a virtual machine, more than one devices |
Weidong Han | 1ce28fe | 2008-12-08 16:35:39 +0800 | [diff] [blame] | 371 | * across iommus may be owned in one domain, e.g. kvm guest. |
| 372 | */ |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 373 | #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 0) |
Weidong Han | 1ce28fe | 2008-12-08 16:35:39 +0800 | [diff] [blame] | 374 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 375 | /* si_domain contains mulitple devices */ |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 376 | #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 1) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 377 | |
Joerg Roedel | 29a2771 | 2015-07-21 17:17:12 +0200 | [diff] [blame] | 378 | #define for_each_domain_iommu(idx, domain) \ |
| 379 | for (idx = 0; idx < g_num_of_iommus; idx++) \ |
| 380 | if (domain->iommu_refcnt[idx]) |
| 381 | |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 382 | struct dmar_domain { |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 383 | int nid; /* node id */ |
Joerg Roedel | 29a2771 | 2015-07-21 17:17:12 +0200 | [diff] [blame] | 384 | |
| 385 | unsigned iommu_refcnt[DMAR_UNITS_SUPPORTED]; |
| 386 | /* Refcount of devices per iommu */ |
| 387 | |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 388 | |
Joerg Roedel | c0e8a6c | 2015-07-21 09:39:46 +0200 | [diff] [blame] | 389 | u16 iommu_did[DMAR_UNITS_SUPPORTED]; |
| 390 | /* Domain ids per IOMMU. Use u16 since |
| 391 | * domain ids are 16 bit wide according |
| 392 | * to VT-d spec, section 9.3 */ |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 393 | |
Omer Peleg | 0824c59 | 2016-04-20 19:03:35 +0300 | [diff] [blame] | 394 | bool has_iotlb_device; |
Joerg Roedel | 00a77de | 2015-03-26 13:43:08 +0100 | [diff] [blame] | 395 | struct list_head devices; /* all devices' list */ |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 396 | struct iova_domain iovad; /* iova's that belong to this domain */ |
| 397 | |
| 398 | struct dma_pte *pgd; /* virtual address */ |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 399 | int gaw; /* max guest address width */ |
| 400 | |
| 401 | /* adjusted guest address width, 0 is level 2 30-bit */ |
| 402 | int agaw; |
| 403 | |
Weidong Han | 3b5410e | 2008-12-08 09:17:15 +0800 | [diff] [blame] | 404 | int flags; /* flags to find out type of domain */ |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 405 | |
| 406 | int iommu_coherency;/* indicate coherency of iommu access */ |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 407 | int iommu_snooping; /* indicate snooping control feature*/ |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 408 | int iommu_count; /* reference count of iommu */ |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 409 | int iommu_superpage;/* Level of superpages supported: |
| 410 | 0 == 4KiB (no superpages), 1 == 2MiB, |
| 411 | 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */ |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 412 | u64 max_addr; /* maximum mapped address */ |
Joerg Roedel | 00a77de | 2015-03-26 13:43:08 +0100 | [diff] [blame] | 413 | |
| 414 | struct iommu_domain domain; /* generic domain data structure for |
| 415 | iommu core */ |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 416 | }; |
| 417 | |
Mark McLoughlin | a647dac | 2008-11-20 15:49:48 +0000 | [diff] [blame] | 418 | /* PCI domain-device relationship */ |
| 419 | struct device_domain_info { |
| 420 | struct list_head link; /* link to domain siblings */ |
| 421 | struct list_head global; /* link to global list */ |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 422 | u8 bus; /* PCI bus number */ |
Mark McLoughlin | a647dac | 2008-11-20 15:49:48 +0000 | [diff] [blame] | 423 | u8 devfn; /* PCI devfn number */ |
David Woodhouse | b16d0cb | 2015-10-12 14:17:37 +0100 | [diff] [blame] | 424 | u8 pasid_supported:3; |
| 425 | u8 pasid_enabled:1; |
| 426 | u8 pri_supported:1; |
| 427 | u8 pri_enabled:1; |
| 428 | u8 ats_supported:1; |
| 429 | u8 ats_enabled:1; |
| 430 | u8 ats_qdep; |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 431 | struct device *dev; /* it's NULL for PCIe-to-PCI bridge */ |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 432 | struct intel_iommu *iommu; /* IOMMU used by this device */ |
Mark McLoughlin | a647dac | 2008-11-20 15:49:48 +0000 | [diff] [blame] | 433 | struct dmar_domain *domain; /* pointer to domain */ |
| 434 | }; |
| 435 | |
Jiang Liu | b94e411 | 2014-02-19 14:07:25 +0800 | [diff] [blame] | 436 | struct dmar_rmrr_unit { |
| 437 | struct list_head list; /* list of rmrr units */ |
| 438 | struct acpi_dmar_header *hdr; /* ACPI header */ |
| 439 | u64 base_address; /* reserved base address*/ |
| 440 | u64 end_address; /* reserved end address */ |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 441 | struct dmar_dev_scope *devices; /* target devices */ |
Jiang Liu | b94e411 | 2014-02-19 14:07:25 +0800 | [diff] [blame] | 442 | int devices_cnt; /* target device count */ |
| 443 | }; |
| 444 | |
| 445 | struct dmar_atsr_unit { |
| 446 | struct list_head list; /* list of ATSR units */ |
| 447 | struct acpi_dmar_header *hdr; /* ACPI header */ |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 448 | struct dmar_dev_scope *devices; /* target devices */ |
Jiang Liu | b94e411 | 2014-02-19 14:07:25 +0800 | [diff] [blame] | 449 | int devices_cnt; /* target device count */ |
| 450 | u8 include_all:1; /* include all ports */ |
| 451 | }; |
| 452 | |
| 453 | static LIST_HEAD(dmar_atsr_units); |
| 454 | static LIST_HEAD(dmar_rmrr_units); |
| 455 | |
| 456 | #define for_each_rmrr_units(rmrr) \ |
| 457 | list_for_each_entry(rmrr, &dmar_rmrr_units, list) |
| 458 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 459 | static void flush_unmaps_timeout(unsigned long data); |
| 460 | |
Omer Peleg | 314f1dc | 2016-04-20 11:32:45 +0300 | [diff] [blame] | 461 | struct deferred_flush_entry { |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 462 | unsigned long iova_pfn; |
Omer Peleg | 769530e | 2016-04-20 11:33:25 +0300 | [diff] [blame] | 463 | unsigned long nrpages; |
Omer Peleg | 314f1dc | 2016-04-20 11:32:45 +0300 | [diff] [blame] | 464 | struct dmar_domain *domain; |
| 465 | struct page *freelist; |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 466 | }; |
| 467 | |
Omer Peleg | 314f1dc | 2016-04-20 11:32:45 +0300 | [diff] [blame] | 468 | #define HIGH_WATER_MARK 250 |
| 469 | struct deferred_flush_table { |
| 470 | int next; |
| 471 | struct deferred_flush_entry entries[HIGH_WATER_MARK]; |
| 472 | }; |
| 473 | |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 474 | struct deferred_flush_data { |
| 475 | spinlock_t lock; |
| 476 | int timer_on; |
| 477 | struct timer_list timer; |
| 478 | long size; |
| 479 | struct deferred_flush_table *tables; |
| 480 | }; |
| 481 | |
| 482 | DEFINE_PER_CPU(struct deferred_flush_data, deferred_flush); |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 483 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 484 | /* bitmap for indexing intel_iommus */ |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 485 | static int g_num_of_iommus; |
| 486 | |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 487 | static void domain_exit(struct dmar_domain *domain); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 488 | static void domain_remove_dev_info(struct dmar_domain *domain); |
Joerg Roedel | e6de0f8 | 2015-07-22 16:30:36 +0200 | [diff] [blame] | 489 | static void dmar_remove_one_dev_info(struct dmar_domain *domain, |
| 490 | struct device *dev); |
Joerg Roedel | 127c761 | 2015-07-23 17:44:46 +0200 | [diff] [blame] | 491 | static void __dmar_remove_one_dev_info(struct device_domain_info *info); |
Joerg Roedel | 2452d9d | 2015-07-23 16:20:14 +0200 | [diff] [blame] | 492 | static void domain_context_clear(struct intel_iommu *iommu, |
| 493 | struct device *dev); |
Jiang Liu | 2a46ddf | 2014-07-11 14:19:30 +0800 | [diff] [blame] | 494 | static int domain_detach_iommu(struct dmar_domain *domain, |
| 495 | struct intel_iommu *iommu); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 496 | |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 497 | #ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON |
Kyle McMartin | 0cd5c3c | 2009-02-04 14:29:19 -0800 | [diff] [blame] | 498 | int dmar_disabled = 0; |
| 499 | #else |
| 500 | int dmar_disabled = 1; |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 501 | #endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/ |
Kyle McMartin | 0cd5c3c | 2009-02-04 14:29:19 -0800 | [diff] [blame] | 502 | |
Eugeni Dodonov | 8bc1f85 | 2011-11-23 16:42:14 -0200 | [diff] [blame] | 503 | int intel_iommu_enabled = 0; |
| 504 | EXPORT_SYMBOL_GPL(intel_iommu_enabled); |
| 505 | |
David Woodhouse | 2d9e667 | 2010-06-15 10:57:57 +0100 | [diff] [blame] | 506 | static int dmar_map_gfx = 1; |
Keshavamurthy, Anil S | 7d3b03c | 2007-10-21 16:41:53 -0700 | [diff] [blame] | 507 | static int dmar_forcedac; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 508 | static int intel_iommu_strict; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 509 | static int intel_iommu_superpage = 1; |
David Woodhouse | c83b2f2 | 2015-06-12 10:15:49 +0100 | [diff] [blame] | 510 | static int intel_iommu_ecs = 1; |
David Woodhouse | ae853dd | 2015-09-09 11:58:59 +0100 | [diff] [blame] | 511 | static int intel_iommu_pasid28; |
| 512 | static int iommu_identity_mapping; |
David Woodhouse | c83b2f2 | 2015-06-12 10:15:49 +0100 | [diff] [blame] | 513 | |
David Woodhouse | ae853dd | 2015-09-09 11:58:59 +0100 | [diff] [blame] | 514 | #define IDENTMAP_ALL 1 |
| 515 | #define IDENTMAP_GFX 2 |
| 516 | #define IDENTMAP_AZALIA 4 |
David Woodhouse | c83b2f2 | 2015-06-12 10:15:49 +0100 | [diff] [blame] | 517 | |
David Woodhouse | d42fde7 | 2015-10-24 21:33:01 +0200 | [diff] [blame] | 518 | /* Broadwell and Skylake have broken ECS support — normal so-called "second |
| 519 | * level" translation of DMA requests-without-PASID doesn't actually happen |
| 520 | * unless you also set the NESTE bit in an extended context-entry. Which of |
| 521 | * course means that SVM doesn't work because it's trying to do nested |
| 522 | * translation of the physical addresses it finds in the process page tables, |
| 523 | * through the IOVA->phys mapping found in the "second level" page tables. |
| 524 | * |
| 525 | * The VT-d specification was retroactively changed to change the definition |
| 526 | * of the capability bits and pretend that Broadwell/Skylake never happened... |
| 527 | * but unfortunately the wrong bit was changed. It's ECS which is broken, but |
| 528 | * for some reason it was the PASID capability bit which was redefined (from |
| 529 | * bit 28 on BDW/SKL to bit 40 in future). |
| 530 | * |
| 531 | * So our test for ECS needs to eschew those implementations which set the old |
| 532 | * PASID capabiity bit 28, since those are the ones on which ECS is broken. |
| 533 | * Unless we are working around the 'pasid28' limitations, that is, by putting |
| 534 | * the device into passthrough mode for normal DMA and thus masking the bug. |
| 535 | */ |
David Woodhouse | c83b2f2 | 2015-06-12 10:15:49 +0100 | [diff] [blame] | 536 | #define ecs_enabled(iommu) (intel_iommu_ecs && ecap_ecs(iommu->ecap) && \ |
David Woodhouse | d42fde7 | 2015-10-24 21:33:01 +0200 | [diff] [blame] | 537 | (intel_iommu_pasid28 || !ecap_broken_pasid(iommu->ecap))) |
| 538 | /* PASID support is thus enabled if ECS is enabled and *either* of the old |
| 539 | * or new capability bits are set. */ |
| 540 | #define pasid_enabled(iommu) (ecs_enabled(iommu) && \ |
| 541 | (ecap_pasid(iommu->ecap) || ecap_broken_pasid(iommu->ecap))) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 542 | |
David Woodhouse | c0771df | 2011-10-14 20:59:46 +0100 | [diff] [blame] | 543 | int intel_iommu_gfx_mapped; |
| 544 | EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped); |
| 545 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 546 | #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1)) |
| 547 | static DEFINE_SPINLOCK(device_domain_lock); |
| 548 | static LIST_HEAD(device_domain_list); |
| 549 | |
Thierry Reding | b22f643 | 2014-06-27 09:03:12 +0200 | [diff] [blame] | 550 | static const struct iommu_ops intel_iommu_ops; |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 551 | |
Joerg Roedel | 4158c2e | 2015-06-12 10:14:02 +0200 | [diff] [blame] | 552 | static bool translation_pre_enabled(struct intel_iommu *iommu) |
| 553 | { |
| 554 | return (iommu->flags & VTD_FLAG_TRANS_PRE_ENABLED); |
| 555 | } |
| 556 | |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 557 | static void clear_translation_pre_enabled(struct intel_iommu *iommu) |
| 558 | { |
| 559 | iommu->flags &= ~VTD_FLAG_TRANS_PRE_ENABLED; |
| 560 | } |
| 561 | |
Joerg Roedel | 4158c2e | 2015-06-12 10:14:02 +0200 | [diff] [blame] | 562 | static void init_translation_status(struct intel_iommu *iommu) |
| 563 | { |
| 564 | u32 gsts; |
| 565 | |
| 566 | gsts = readl(iommu->reg + DMAR_GSTS_REG); |
| 567 | if (gsts & DMA_GSTS_TES) |
| 568 | iommu->flags |= VTD_FLAG_TRANS_PRE_ENABLED; |
| 569 | } |
| 570 | |
Joerg Roedel | 00a77de | 2015-03-26 13:43:08 +0100 | [diff] [blame] | 571 | /* Convert generic 'struct iommu_domain to private struct dmar_domain */ |
| 572 | static struct dmar_domain *to_dmar_domain(struct iommu_domain *dom) |
| 573 | { |
| 574 | return container_of(dom, struct dmar_domain, domain); |
| 575 | } |
| 576 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 577 | static int __init intel_iommu_setup(char *str) |
| 578 | { |
| 579 | if (!str) |
| 580 | return -EINVAL; |
| 581 | while (*str) { |
Kyle McMartin | 0cd5c3c | 2009-02-04 14:29:19 -0800 | [diff] [blame] | 582 | if (!strncmp(str, "on", 2)) { |
| 583 | dmar_disabled = 0; |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 584 | pr_info("IOMMU enabled\n"); |
Kyle McMartin | 0cd5c3c | 2009-02-04 14:29:19 -0800 | [diff] [blame] | 585 | } else if (!strncmp(str, "off", 3)) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 586 | dmar_disabled = 1; |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 587 | pr_info("IOMMU disabled\n"); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 588 | } else if (!strncmp(str, "igfx_off", 8)) { |
| 589 | dmar_map_gfx = 0; |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 590 | pr_info("Disable GFX device mapping\n"); |
Keshavamurthy, Anil S | 7d3b03c | 2007-10-21 16:41:53 -0700 | [diff] [blame] | 591 | } else if (!strncmp(str, "forcedac", 8)) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 592 | pr_info("Forcing DAC for PCI devices\n"); |
Keshavamurthy, Anil S | 7d3b03c | 2007-10-21 16:41:53 -0700 | [diff] [blame] | 593 | dmar_forcedac = 1; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 594 | } else if (!strncmp(str, "strict", 6)) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 595 | pr_info("Disable batched IOTLB flush\n"); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 596 | intel_iommu_strict = 1; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 597 | } else if (!strncmp(str, "sp_off", 6)) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 598 | pr_info("Disable supported super page\n"); |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 599 | intel_iommu_superpage = 0; |
David Woodhouse | c83b2f2 | 2015-06-12 10:15:49 +0100 | [diff] [blame] | 600 | } else if (!strncmp(str, "ecs_off", 7)) { |
| 601 | printk(KERN_INFO |
| 602 | "Intel-IOMMU: disable extended context table support\n"); |
| 603 | intel_iommu_ecs = 0; |
David Woodhouse | ae853dd | 2015-09-09 11:58:59 +0100 | [diff] [blame] | 604 | } else if (!strncmp(str, "pasid28", 7)) { |
| 605 | printk(KERN_INFO |
| 606 | "Intel-IOMMU: enable pre-production PASID support\n"); |
| 607 | intel_iommu_pasid28 = 1; |
| 608 | iommu_identity_mapping |= IDENTMAP_GFX; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 609 | } |
| 610 | |
| 611 | str += strcspn(str, ","); |
| 612 | while (*str == ',') |
| 613 | str++; |
| 614 | } |
| 615 | return 0; |
| 616 | } |
| 617 | __setup("intel_iommu=", intel_iommu_setup); |
| 618 | |
| 619 | static struct kmem_cache *iommu_domain_cache; |
| 620 | static struct kmem_cache *iommu_devinfo_cache; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 621 | |
Joerg Roedel | 9452d5b | 2015-07-21 10:00:56 +0200 | [diff] [blame] | 622 | static struct dmar_domain* get_iommu_domain(struct intel_iommu *iommu, u16 did) |
| 623 | { |
Joerg Roedel | 8bf4781 | 2015-07-21 10:41:21 +0200 | [diff] [blame] | 624 | struct dmar_domain **domains; |
| 625 | int idx = did >> 8; |
| 626 | |
| 627 | domains = iommu->domains[idx]; |
| 628 | if (!domains) |
| 629 | return NULL; |
| 630 | |
| 631 | return domains[did & 0xff]; |
Joerg Roedel | 9452d5b | 2015-07-21 10:00:56 +0200 | [diff] [blame] | 632 | } |
| 633 | |
| 634 | static void set_iommu_domain(struct intel_iommu *iommu, u16 did, |
| 635 | struct dmar_domain *domain) |
| 636 | { |
Joerg Roedel | 8bf4781 | 2015-07-21 10:41:21 +0200 | [diff] [blame] | 637 | struct dmar_domain **domains; |
| 638 | int idx = did >> 8; |
| 639 | |
| 640 | if (!iommu->domains[idx]) { |
| 641 | size_t size = 256 * sizeof(struct dmar_domain *); |
| 642 | iommu->domains[idx] = kzalloc(size, GFP_ATOMIC); |
| 643 | } |
| 644 | |
| 645 | domains = iommu->domains[idx]; |
| 646 | if (WARN_ON(!domains)) |
| 647 | return; |
| 648 | else |
| 649 | domains[did & 0xff] = domain; |
Joerg Roedel | 9452d5b | 2015-07-21 10:00:56 +0200 | [diff] [blame] | 650 | } |
| 651 | |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 652 | static inline void *alloc_pgtable_page(int node) |
Keshavamurthy, Anil S | eb3fa7c | 2007-10-21 16:41:52 -0700 | [diff] [blame] | 653 | { |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 654 | struct page *page; |
| 655 | void *vaddr = NULL; |
Keshavamurthy, Anil S | eb3fa7c | 2007-10-21 16:41:52 -0700 | [diff] [blame] | 656 | |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 657 | page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0); |
| 658 | if (page) |
| 659 | vaddr = page_address(page); |
Keshavamurthy, Anil S | eb3fa7c | 2007-10-21 16:41:52 -0700 | [diff] [blame] | 660 | return vaddr; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 661 | } |
| 662 | |
| 663 | static inline void free_pgtable_page(void *vaddr) |
| 664 | { |
| 665 | free_page((unsigned long)vaddr); |
| 666 | } |
| 667 | |
| 668 | static inline void *alloc_domain_mem(void) |
| 669 | { |
KOSAKI Motohiro | 354bb65 | 2009-11-17 16:21:09 +0900 | [diff] [blame] | 670 | return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 671 | } |
| 672 | |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 673 | static void free_domain_mem(void *vaddr) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 674 | { |
| 675 | kmem_cache_free(iommu_domain_cache, vaddr); |
| 676 | } |
| 677 | |
| 678 | static inline void * alloc_devinfo_mem(void) |
| 679 | { |
KOSAKI Motohiro | 354bb65 | 2009-11-17 16:21:09 +0900 | [diff] [blame] | 680 | return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 681 | } |
| 682 | |
| 683 | static inline void free_devinfo_mem(void *vaddr) |
| 684 | { |
| 685 | kmem_cache_free(iommu_devinfo_cache, vaddr); |
| 686 | } |
| 687 | |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 688 | static inline int domain_type_is_vm(struct dmar_domain *domain) |
| 689 | { |
| 690 | return domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE; |
| 691 | } |
| 692 | |
Joerg Roedel | 28ccce0 | 2015-07-21 14:45:31 +0200 | [diff] [blame] | 693 | static inline int domain_type_is_si(struct dmar_domain *domain) |
| 694 | { |
| 695 | return domain->flags & DOMAIN_FLAG_STATIC_IDENTITY; |
| 696 | } |
| 697 | |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 698 | static inline int domain_type_is_vm_or_si(struct dmar_domain *domain) |
| 699 | { |
| 700 | return domain->flags & (DOMAIN_FLAG_VIRTUAL_MACHINE | |
| 701 | DOMAIN_FLAG_STATIC_IDENTITY); |
| 702 | } |
Weidong Han | 1b57368 | 2008-12-08 15:34:06 +0800 | [diff] [blame] | 703 | |
Jiang Liu | 162d1b1 | 2014-07-11 14:19:35 +0800 | [diff] [blame] | 704 | static inline int domain_pfn_supported(struct dmar_domain *domain, |
| 705 | unsigned long pfn) |
| 706 | { |
| 707 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
| 708 | |
| 709 | return !(addr_width < BITS_PER_LONG && pfn >> addr_width); |
| 710 | } |
| 711 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 712 | static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw) |
Weidong Han | 1b57368 | 2008-12-08 15:34:06 +0800 | [diff] [blame] | 713 | { |
| 714 | unsigned long sagaw; |
| 715 | int agaw = -1; |
| 716 | |
| 717 | sagaw = cap_sagaw(iommu->cap); |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 718 | for (agaw = width_to_agaw(max_gaw); |
Weidong Han | 1b57368 | 2008-12-08 15:34:06 +0800 | [diff] [blame] | 719 | agaw >= 0; agaw--) { |
| 720 | if (test_bit(agaw, &sagaw)) |
| 721 | break; |
| 722 | } |
| 723 | |
| 724 | return agaw; |
| 725 | } |
| 726 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 727 | /* |
| 728 | * Calculate max SAGAW for each iommu. |
| 729 | */ |
| 730 | int iommu_calculate_max_sagaw(struct intel_iommu *iommu) |
| 731 | { |
| 732 | return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH); |
| 733 | } |
| 734 | |
| 735 | /* |
| 736 | * calculate agaw for each iommu. |
| 737 | * "SAGAW" may be different across iommus, use a default agaw, and |
| 738 | * get a supported less agaw for iommus that don't support the default agaw. |
| 739 | */ |
| 740 | int iommu_calculate_agaw(struct intel_iommu *iommu) |
| 741 | { |
| 742 | return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
| 743 | } |
| 744 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 745 | /* This functionin only returns single iommu in a domain */ |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 746 | static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain) |
| 747 | { |
| 748 | int iommu_id; |
| 749 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 750 | /* si_domain and vm domain should not get here. */ |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 751 | BUG_ON(domain_type_is_vm_or_si(domain)); |
Joerg Roedel | 29a2771 | 2015-07-21 17:17:12 +0200 | [diff] [blame] | 752 | for_each_domain_iommu(iommu_id, domain) |
| 753 | break; |
| 754 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 755 | if (iommu_id < 0 || iommu_id >= g_num_of_iommus) |
| 756 | return NULL; |
| 757 | |
| 758 | return g_iommus[iommu_id]; |
| 759 | } |
| 760 | |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 761 | static void domain_update_iommu_coherency(struct dmar_domain *domain) |
| 762 | { |
David Woodhouse | d050196 | 2014-03-11 17:10:29 -0700 | [diff] [blame] | 763 | struct dmar_drhd_unit *drhd; |
| 764 | struct intel_iommu *iommu; |
Quentin Lambert | 2f119c7 | 2015-02-06 10:59:53 +0100 | [diff] [blame] | 765 | bool found = false; |
| 766 | int i; |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 767 | |
David Woodhouse | d050196 | 2014-03-11 17:10:29 -0700 | [diff] [blame] | 768 | domain->iommu_coherency = 1; |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 769 | |
Joerg Roedel | 29a2771 | 2015-07-21 17:17:12 +0200 | [diff] [blame] | 770 | for_each_domain_iommu(i, domain) { |
Quentin Lambert | 2f119c7 | 2015-02-06 10:59:53 +0100 | [diff] [blame] | 771 | found = true; |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 772 | if (!ecap_coherent(g_iommus[i]->ecap)) { |
| 773 | domain->iommu_coherency = 0; |
| 774 | break; |
| 775 | } |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 776 | } |
David Woodhouse | d050196 | 2014-03-11 17:10:29 -0700 | [diff] [blame] | 777 | if (found) |
| 778 | return; |
| 779 | |
| 780 | /* No hardware attached; use lowest common denominator */ |
| 781 | rcu_read_lock(); |
| 782 | for_each_active_iommu(iommu, drhd) { |
| 783 | if (!ecap_coherent(iommu->ecap)) { |
| 784 | domain->iommu_coherency = 0; |
| 785 | break; |
| 786 | } |
| 787 | } |
| 788 | rcu_read_unlock(); |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 789 | } |
| 790 | |
Jiang Liu | 161f693 | 2014-07-11 14:19:37 +0800 | [diff] [blame] | 791 | static int domain_update_iommu_snooping(struct intel_iommu *skip) |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 792 | { |
Allen Kay | 8140a95 | 2011-10-14 12:32:17 -0700 | [diff] [blame] | 793 | struct dmar_drhd_unit *drhd; |
Jiang Liu | 161f693 | 2014-07-11 14:19:37 +0800 | [diff] [blame] | 794 | struct intel_iommu *iommu; |
| 795 | int ret = 1; |
| 796 | |
| 797 | rcu_read_lock(); |
| 798 | for_each_active_iommu(iommu, drhd) { |
| 799 | if (iommu != skip) { |
| 800 | if (!ecap_sc_support(iommu->ecap)) { |
| 801 | ret = 0; |
| 802 | break; |
| 803 | } |
| 804 | } |
| 805 | } |
| 806 | rcu_read_unlock(); |
| 807 | |
| 808 | return ret; |
| 809 | } |
| 810 | |
| 811 | static int domain_update_iommu_superpage(struct intel_iommu *skip) |
| 812 | { |
| 813 | struct dmar_drhd_unit *drhd; |
| 814 | struct intel_iommu *iommu; |
Allen Kay | 8140a95 | 2011-10-14 12:32:17 -0700 | [diff] [blame] | 815 | int mask = 0xf; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 816 | |
| 817 | if (!intel_iommu_superpage) { |
Jiang Liu | 161f693 | 2014-07-11 14:19:37 +0800 | [diff] [blame] | 818 | return 0; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 819 | } |
| 820 | |
Allen Kay | 8140a95 | 2011-10-14 12:32:17 -0700 | [diff] [blame] | 821 | /* set iommu_superpage to the smallest common denominator */ |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 822 | rcu_read_lock(); |
Allen Kay | 8140a95 | 2011-10-14 12:32:17 -0700 | [diff] [blame] | 823 | for_each_active_iommu(iommu, drhd) { |
Jiang Liu | 161f693 | 2014-07-11 14:19:37 +0800 | [diff] [blame] | 824 | if (iommu != skip) { |
| 825 | mask &= cap_super_page_val(iommu->cap); |
| 826 | if (!mask) |
| 827 | break; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 828 | } |
| 829 | } |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 830 | rcu_read_unlock(); |
| 831 | |
Jiang Liu | 161f693 | 2014-07-11 14:19:37 +0800 | [diff] [blame] | 832 | return fls(mask); |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 833 | } |
| 834 | |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 835 | /* Some capabilities may be different across iommus */ |
| 836 | static void domain_update_iommu_cap(struct dmar_domain *domain) |
| 837 | { |
| 838 | domain_update_iommu_coherency(domain); |
Jiang Liu | 161f693 | 2014-07-11 14:19:37 +0800 | [diff] [blame] | 839 | domain->iommu_snooping = domain_update_iommu_snooping(NULL); |
| 840 | domain->iommu_superpage = domain_update_iommu_superpage(NULL); |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 841 | } |
| 842 | |
David Woodhouse | 03ecc32 | 2015-02-13 14:35:21 +0000 | [diff] [blame] | 843 | static inline struct context_entry *iommu_context_addr(struct intel_iommu *iommu, |
| 844 | u8 bus, u8 devfn, int alloc) |
| 845 | { |
| 846 | struct root_entry *root = &iommu->root_entry[bus]; |
| 847 | struct context_entry *context; |
| 848 | u64 *entry; |
| 849 | |
Joerg Roedel | 4df4eab | 2015-08-25 10:54:28 +0200 | [diff] [blame] | 850 | entry = &root->lo; |
David Woodhouse | c83b2f2 | 2015-06-12 10:15:49 +0100 | [diff] [blame] | 851 | if (ecs_enabled(iommu)) { |
David Woodhouse | 03ecc32 | 2015-02-13 14:35:21 +0000 | [diff] [blame] | 852 | if (devfn >= 0x80) { |
| 853 | devfn -= 0x80; |
| 854 | entry = &root->hi; |
| 855 | } |
| 856 | devfn *= 2; |
| 857 | } |
David Woodhouse | 03ecc32 | 2015-02-13 14:35:21 +0000 | [diff] [blame] | 858 | if (*entry & 1) |
| 859 | context = phys_to_virt(*entry & VTD_PAGE_MASK); |
| 860 | else { |
| 861 | unsigned long phy_addr; |
| 862 | if (!alloc) |
| 863 | return NULL; |
| 864 | |
| 865 | context = alloc_pgtable_page(iommu->node); |
| 866 | if (!context) |
| 867 | return NULL; |
| 868 | |
| 869 | __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE); |
| 870 | phy_addr = virt_to_phys((void *)context); |
| 871 | *entry = phy_addr | 1; |
| 872 | __iommu_flush_cache(iommu, entry, sizeof(*entry)); |
| 873 | } |
| 874 | return &context[devfn]; |
| 875 | } |
| 876 | |
David Woodhouse | 4ed6a54 | 2015-05-11 14:59:20 +0100 | [diff] [blame] | 877 | static int iommu_dummy(struct device *dev) |
| 878 | { |
| 879 | return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO; |
| 880 | } |
| 881 | |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 882 | static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn) |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 883 | { |
| 884 | struct dmar_drhd_unit *drhd = NULL; |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 885 | struct intel_iommu *iommu; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 886 | struct device *tmp; |
| 887 | struct pci_dev *ptmp, *pdev = NULL; |
Yijing Wang | aa4d066 | 2014-05-26 20:14:06 +0800 | [diff] [blame] | 888 | u16 segment = 0; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 889 | int i; |
| 890 | |
David Woodhouse | 4ed6a54 | 2015-05-11 14:59:20 +0100 | [diff] [blame] | 891 | if (iommu_dummy(dev)) |
| 892 | return NULL; |
| 893 | |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 894 | if (dev_is_pci(dev)) { |
| 895 | pdev = to_pci_dev(dev); |
| 896 | segment = pci_domain_nr(pdev->bus); |
Rafael J. Wysocki | ca5b74d | 2015-03-16 23:49:08 +0100 | [diff] [blame] | 897 | } else if (has_acpi_companion(dev)) |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 898 | dev = &ACPI_COMPANION(dev)->dev; |
| 899 | |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 900 | rcu_read_lock(); |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 901 | for_each_active_iommu(iommu, drhd) { |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 902 | if (pdev && segment != drhd->segment) |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 903 | continue; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 904 | |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 905 | for_each_active_dev_scope(drhd->devices, |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 906 | drhd->devices_cnt, i, tmp) { |
| 907 | if (tmp == dev) { |
| 908 | *bus = drhd->devices[i].bus; |
| 909 | *devfn = drhd->devices[i].devfn; |
| 910 | goto out; |
| 911 | } |
| 912 | |
| 913 | if (!pdev || !dev_is_pci(tmp)) |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 914 | continue; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 915 | |
| 916 | ptmp = to_pci_dev(tmp); |
| 917 | if (ptmp->subordinate && |
| 918 | ptmp->subordinate->number <= pdev->bus->number && |
| 919 | ptmp->subordinate->busn_res.end >= pdev->bus->number) |
| 920 | goto got_pdev; |
David Woodhouse | 924b623 | 2009-04-04 00:39:25 +0100 | [diff] [blame] | 921 | } |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 922 | |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 923 | if (pdev && drhd->include_all) { |
| 924 | got_pdev: |
| 925 | *bus = pdev->bus->number; |
| 926 | *devfn = pdev->devfn; |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 927 | goto out; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 928 | } |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 929 | } |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 930 | iommu = NULL; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 931 | out: |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 932 | rcu_read_unlock(); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 933 | |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 934 | return iommu; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 935 | } |
| 936 | |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 937 | static void domain_flush_cache(struct dmar_domain *domain, |
| 938 | void *addr, int size) |
| 939 | { |
| 940 | if (!domain->iommu_coherency) |
| 941 | clflush_cache_range(addr, size); |
| 942 | } |
| 943 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 944 | static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn) |
| 945 | { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 946 | struct context_entry *context; |
David Woodhouse | 03ecc32 | 2015-02-13 14:35:21 +0000 | [diff] [blame] | 947 | int ret = 0; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 948 | unsigned long flags; |
| 949 | |
| 950 | spin_lock_irqsave(&iommu->lock, flags); |
David Woodhouse | 03ecc32 | 2015-02-13 14:35:21 +0000 | [diff] [blame] | 951 | context = iommu_context_addr(iommu, bus, devfn, 0); |
| 952 | if (context) |
| 953 | ret = context_present(context); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 954 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 955 | return ret; |
| 956 | } |
| 957 | |
| 958 | static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn) |
| 959 | { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 960 | struct context_entry *context; |
| 961 | unsigned long flags; |
| 962 | |
| 963 | spin_lock_irqsave(&iommu->lock, flags); |
David Woodhouse | 03ecc32 | 2015-02-13 14:35:21 +0000 | [diff] [blame] | 964 | context = iommu_context_addr(iommu, bus, devfn, 0); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 965 | if (context) { |
David Woodhouse | 03ecc32 | 2015-02-13 14:35:21 +0000 | [diff] [blame] | 966 | context_clear_entry(context); |
| 967 | __iommu_flush_cache(iommu, context, sizeof(*context)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 968 | } |
| 969 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 970 | } |
| 971 | |
| 972 | static void free_context_table(struct intel_iommu *iommu) |
| 973 | { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 974 | int i; |
| 975 | unsigned long flags; |
| 976 | struct context_entry *context; |
| 977 | |
| 978 | spin_lock_irqsave(&iommu->lock, flags); |
| 979 | if (!iommu->root_entry) { |
| 980 | goto out; |
| 981 | } |
| 982 | for (i = 0; i < ROOT_ENTRY_NR; i++) { |
David Woodhouse | 03ecc32 | 2015-02-13 14:35:21 +0000 | [diff] [blame] | 983 | context = iommu_context_addr(iommu, i, 0, 0); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 984 | if (context) |
| 985 | free_pgtable_page(context); |
David Woodhouse | 03ecc32 | 2015-02-13 14:35:21 +0000 | [diff] [blame] | 986 | |
David Woodhouse | c83b2f2 | 2015-06-12 10:15:49 +0100 | [diff] [blame] | 987 | if (!ecs_enabled(iommu)) |
David Woodhouse | 03ecc32 | 2015-02-13 14:35:21 +0000 | [diff] [blame] | 988 | continue; |
| 989 | |
| 990 | context = iommu_context_addr(iommu, i, 0x80, 0); |
| 991 | if (context) |
| 992 | free_pgtable_page(context); |
| 993 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 994 | } |
| 995 | free_pgtable_page(iommu->root_entry); |
| 996 | iommu->root_entry = NULL; |
| 997 | out: |
| 998 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 999 | } |
| 1000 | |
David Woodhouse | b026fd2 | 2009-06-28 10:37:25 +0100 | [diff] [blame] | 1001 | static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain, |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 1002 | unsigned long pfn, int *target_level) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1003 | { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1004 | struct dma_pte *parent, *pte = NULL; |
| 1005 | int level = agaw_to_level(domain->agaw); |
Allen Kay | 4399c8b | 2011-10-14 12:32:46 -0700 | [diff] [blame] | 1006 | int offset; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1007 | |
| 1008 | BUG_ON(!domain->pgd); |
Julian Stecklina | f942360 | 2013-10-09 10:03:52 +0200 | [diff] [blame] | 1009 | |
Jiang Liu | 162d1b1 | 2014-07-11 14:19:35 +0800 | [diff] [blame] | 1010 | if (!domain_pfn_supported(domain, pfn)) |
Julian Stecklina | f942360 | 2013-10-09 10:03:52 +0200 | [diff] [blame] | 1011 | /* Address beyond IOMMU's addressing capabilities. */ |
| 1012 | return NULL; |
| 1013 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1014 | parent = domain->pgd; |
| 1015 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 1016 | while (1) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1017 | void *tmp_page; |
| 1018 | |
David Woodhouse | b026fd2 | 2009-06-28 10:37:25 +0100 | [diff] [blame] | 1019 | offset = pfn_level_offset(pfn, level); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1020 | pte = &parent[offset]; |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 1021 | if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte))) |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1022 | break; |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 1023 | if (level == *target_level) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1024 | break; |
| 1025 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 1026 | if (!dma_pte_present(pte)) { |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 1027 | uint64_t pteval; |
| 1028 | |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 1029 | tmp_page = alloc_pgtable_page(domain->nid); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1030 | |
David Woodhouse | 206a73c1 | 2009-07-01 19:30:28 +0100 | [diff] [blame] | 1031 | if (!tmp_page) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1032 | return NULL; |
David Woodhouse | 206a73c1 | 2009-07-01 19:30:28 +0100 | [diff] [blame] | 1033 | |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 1034 | domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE); |
Benjamin LaHaise | 64de5af | 2009-09-16 21:05:55 -0400 | [diff] [blame] | 1035 | pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE; |
Yijing Wang | effad4b | 2014-05-26 20:13:47 +0800 | [diff] [blame] | 1036 | if (cmpxchg64(&pte->val, 0ULL, pteval)) |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 1037 | /* Someone else set it while we were thinking; use theirs. */ |
| 1038 | free_pgtable_page(tmp_page); |
Yijing Wang | effad4b | 2014-05-26 20:13:47 +0800 | [diff] [blame] | 1039 | else |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 1040 | domain_flush_cache(domain, pte, sizeof(*pte)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1041 | } |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 1042 | if (level == 1) |
| 1043 | break; |
| 1044 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 1045 | parent = phys_to_virt(dma_pte_addr(pte)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1046 | level--; |
| 1047 | } |
| 1048 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 1049 | if (!*target_level) |
| 1050 | *target_level = level; |
| 1051 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1052 | return pte; |
| 1053 | } |
| 1054 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1055 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1056 | /* return address's pte at specific level */ |
David Woodhouse | 90dcfb5 | 2009-06-27 17:14:59 +0100 | [diff] [blame] | 1057 | static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain, |
| 1058 | unsigned long pfn, |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1059 | int level, int *large_page) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1060 | { |
| 1061 | struct dma_pte *parent, *pte = NULL; |
| 1062 | int total = agaw_to_level(domain->agaw); |
| 1063 | int offset; |
| 1064 | |
| 1065 | parent = domain->pgd; |
| 1066 | while (level <= total) { |
David Woodhouse | 90dcfb5 | 2009-06-27 17:14:59 +0100 | [diff] [blame] | 1067 | offset = pfn_level_offset(pfn, total); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1068 | pte = &parent[offset]; |
| 1069 | if (level == total) |
| 1070 | return pte; |
| 1071 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1072 | if (!dma_pte_present(pte)) { |
| 1073 | *large_page = total; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1074 | break; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1075 | } |
| 1076 | |
Yijing Wang | e16922a | 2014-05-20 20:37:51 +0800 | [diff] [blame] | 1077 | if (dma_pte_superpage(pte)) { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1078 | *large_page = total; |
| 1079 | return pte; |
| 1080 | } |
| 1081 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 1082 | parent = phys_to_virt(dma_pte_addr(pte)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1083 | total--; |
| 1084 | } |
| 1085 | return NULL; |
| 1086 | } |
| 1087 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1088 | /* clear last level pte, a tlb flush should be followed */ |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 1089 | static void dma_pte_clear_range(struct dmar_domain *domain, |
David Woodhouse | 595badf | 2009-06-27 22:09:11 +0100 | [diff] [blame] | 1090 | unsigned long start_pfn, |
| 1091 | unsigned long last_pfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1092 | { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1093 | unsigned int large_page = 1; |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 1094 | struct dma_pte *first_pte, *pte; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1095 | |
Jiang Liu | 162d1b1 | 2014-07-11 14:19:35 +0800 | [diff] [blame] | 1096 | BUG_ON(!domain_pfn_supported(domain, start_pfn)); |
| 1097 | BUG_ON(!domain_pfn_supported(domain, last_pfn)); |
David Woodhouse | 59c3628 | 2009-09-19 07:36:28 -0700 | [diff] [blame] | 1098 | BUG_ON(start_pfn > last_pfn); |
David Woodhouse | 66eae84 | 2009-06-27 19:00:32 +0100 | [diff] [blame] | 1099 | |
David Woodhouse | 04b18e6 | 2009-06-27 19:15:01 +0100 | [diff] [blame] | 1100 | /* we don't need lock here; nobody else touches the iova range */ |
David Woodhouse | 59c3628 | 2009-09-19 07:36:28 -0700 | [diff] [blame] | 1101 | do { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1102 | large_page = 1; |
| 1103 | first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page); |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 1104 | if (!pte) { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1105 | start_pfn = align_to_level(start_pfn + 1, large_page + 1); |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 1106 | continue; |
| 1107 | } |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1108 | do { |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 1109 | dma_clear_pte(pte); |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1110 | start_pfn += lvl_to_nr_pages(large_page); |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 1111 | pte++; |
David Woodhouse | 75e6bf9 | 2009-07-02 11:21:16 +0100 | [diff] [blame] | 1112 | } while (start_pfn <= last_pfn && !first_pte_in_page(pte)); |
| 1113 | |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 1114 | domain_flush_cache(domain, first_pte, |
| 1115 | (void *)pte - (void *)first_pte); |
David Woodhouse | 59c3628 | 2009-09-19 07:36:28 -0700 | [diff] [blame] | 1116 | |
| 1117 | } while (start_pfn && start_pfn <= last_pfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1118 | } |
| 1119 | |
Alex Williamson | 3269ee0 | 2013-06-15 10:27:19 -0600 | [diff] [blame] | 1120 | static void dma_pte_free_level(struct dmar_domain *domain, int level, |
| 1121 | struct dma_pte *pte, unsigned long pfn, |
| 1122 | unsigned long start_pfn, unsigned long last_pfn) |
| 1123 | { |
| 1124 | pfn = max(start_pfn, pfn); |
| 1125 | pte = &pte[pfn_level_offset(pfn, level)]; |
| 1126 | |
| 1127 | do { |
| 1128 | unsigned long level_pfn; |
| 1129 | struct dma_pte *level_pte; |
| 1130 | |
| 1131 | if (!dma_pte_present(pte) || dma_pte_superpage(pte)) |
| 1132 | goto next; |
| 1133 | |
| 1134 | level_pfn = pfn & level_mask(level - 1); |
| 1135 | level_pte = phys_to_virt(dma_pte_addr(pte)); |
| 1136 | |
| 1137 | if (level > 2) |
| 1138 | dma_pte_free_level(domain, level - 1, level_pte, |
| 1139 | level_pfn, start_pfn, last_pfn); |
| 1140 | |
| 1141 | /* If range covers entire pagetable, free it */ |
| 1142 | if (!(start_pfn > level_pfn || |
Alex Williamson | 08336fd | 2014-01-21 15:48:18 -0800 | [diff] [blame] | 1143 | last_pfn < level_pfn + level_size(level) - 1)) { |
Alex Williamson | 3269ee0 | 2013-06-15 10:27:19 -0600 | [diff] [blame] | 1144 | dma_clear_pte(pte); |
| 1145 | domain_flush_cache(domain, pte, sizeof(*pte)); |
| 1146 | free_pgtable_page(level_pte); |
| 1147 | } |
| 1148 | next: |
| 1149 | pfn += level_size(level); |
| 1150 | } while (!first_pte_in_page(++pte) && pfn <= last_pfn); |
| 1151 | } |
| 1152 | |
Michael S. Tsirkin | 3d1a244 | 2016-03-23 20:34:19 +0200 | [diff] [blame] | 1153 | /* clear last level (leaf) ptes and free page table pages. */ |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1154 | static void dma_pte_free_pagetable(struct dmar_domain *domain, |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 1155 | unsigned long start_pfn, |
| 1156 | unsigned long last_pfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1157 | { |
Jiang Liu | 162d1b1 | 2014-07-11 14:19:35 +0800 | [diff] [blame] | 1158 | BUG_ON(!domain_pfn_supported(domain, start_pfn)); |
| 1159 | BUG_ON(!domain_pfn_supported(domain, last_pfn)); |
David Woodhouse | 59c3628 | 2009-09-19 07:36:28 -0700 | [diff] [blame] | 1160 | BUG_ON(start_pfn > last_pfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1161 | |
Jiang Liu | d41a4ad | 2014-07-11 14:19:34 +0800 | [diff] [blame] | 1162 | dma_pte_clear_range(domain, start_pfn, last_pfn); |
| 1163 | |
David Woodhouse | f3a0a52 | 2009-06-30 03:40:07 +0100 | [diff] [blame] | 1164 | /* We don't need lock here; nobody else touches the iova range */ |
Alex Williamson | 3269ee0 | 2013-06-15 10:27:19 -0600 | [diff] [blame] | 1165 | dma_pte_free_level(domain, agaw_to_level(domain->agaw), |
| 1166 | domain->pgd, 0, start_pfn, last_pfn); |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 1167 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1168 | /* free pgd */ |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 1169 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1170 | free_pgtable_page(domain->pgd); |
| 1171 | domain->pgd = NULL; |
| 1172 | } |
| 1173 | } |
| 1174 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1175 | /* When a page at a given level is being unlinked from its parent, we don't |
| 1176 | need to *modify* it at all. All we need to do is make a list of all the |
| 1177 | pages which can be freed just as soon as we've flushed the IOTLB and we |
| 1178 | know the hardware page-walk will no longer touch them. |
| 1179 | The 'pte' argument is the *parent* PTE, pointing to the page that is to |
| 1180 | be freed. */ |
| 1181 | static struct page *dma_pte_list_pagetables(struct dmar_domain *domain, |
| 1182 | int level, struct dma_pte *pte, |
| 1183 | struct page *freelist) |
| 1184 | { |
| 1185 | struct page *pg; |
| 1186 | |
| 1187 | pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT); |
| 1188 | pg->freelist = freelist; |
| 1189 | freelist = pg; |
| 1190 | |
| 1191 | if (level == 1) |
| 1192 | return freelist; |
| 1193 | |
Jiang Liu | adeb259 | 2014-04-09 10:20:39 +0800 | [diff] [blame] | 1194 | pte = page_address(pg); |
| 1195 | do { |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1196 | if (dma_pte_present(pte) && !dma_pte_superpage(pte)) |
| 1197 | freelist = dma_pte_list_pagetables(domain, level - 1, |
| 1198 | pte, freelist); |
Jiang Liu | adeb259 | 2014-04-09 10:20:39 +0800 | [diff] [blame] | 1199 | pte++; |
| 1200 | } while (!first_pte_in_page(pte)); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1201 | |
| 1202 | return freelist; |
| 1203 | } |
| 1204 | |
| 1205 | static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level, |
| 1206 | struct dma_pte *pte, unsigned long pfn, |
| 1207 | unsigned long start_pfn, |
| 1208 | unsigned long last_pfn, |
| 1209 | struct page *freelist) |
| 1210 | { |
| 1211 | struct dma_pte *first_pte = NULL, *last_pte = NULL; |
| 1212 | |
| 1213 | pfn = max(start_pfn, pfn); |
| 1214 | pte = &pte[pfn_level_offset(pfn, level)]; |
| 1215 | |
| 1216 | do { |
| 1217 | unsigned long level_pfn; |
| 1218 | |
| 1219 | if (!dma_pte_present(pte)) |
| 1220 | goto next; |
| 1221 | |
| 1222 | level_pfn = pfn & level_mask(level); |
| 1223 | |
| 1224 | /* If range covers entire pagetable, free it */ |
| 1225 | if (start_pfn <= level_pfn && |
| 1226 | last_pfn >= level_pfn + level_size(level) - 1) { |
| 1227 | /* These suborbinate page tables are going away entirely. Don't |
| 1228 | bother to clear them; we're just going to *free* them. */ |
| 1229 | if (level > 1 && !dma_pte_superpage(pte)) |
| 1230 | freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist); |
| 1231 | |
| 1232 | dma_clear_pte(pte); |
| 1233 | if (!first_pte) |
| 1234 | first_pte = pte; |
| 1235 | last_pte = pte; |
| 1236 | } else if (level > 1) { |
| 1237 | /* Recurse down into a level that isn't *entirely* obsolete */ |
| 1238 | freelist = dma_pte_clear_level(domain, level - 1, |
| 1239 | phys_to_virt(dma_pte_addr(pte)), |
| 1240 | level_pfn, start_pfn, last_pfn, |
| 1241 | freelist); |
| 1242 | } |
| 1243 | next: |
| 1244 | pfn += level_size(level); |
| 1245 | } while (!first_pte_in_page(++pte) && pfn <= last_pfn); |
| 1246 | |
| 1247 | if (first_pte) |
| 1248 | domain_flush_cache(domain, first_pte, |
| 1249 | (void *)++last_pte - (void *)first_pte); |
| 1250 | |
| 1251 | return freelist; |
| 1252 | } |
| 1253 | |
| 1254 | /* We can't just free the pages because the IOMMU may still be walking |
| 1255 | the page tables, and may have cached the intermediate levels. The |
| 1256 | pages can only be freed after the IOTLB flush has been done. */ |
Joerg Roedel | b690420 | 2015-08-13 11:32:18 +0200 | [diff] [blame] | 1257 | static struct page *domain_unmap(struct dmar_domain *domain, |
| 1258 | unsigned long start_pfn, |
| 1259 | unsigned long last_pfn) |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1260 | { |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1261 | struct page *freelist = NULL; |
| 1262 | |
Jiang Liu | 162d1b1 | 2014-07-11 14:19:35 +0800 | [diff] [blame] | 1263 | BUG_ON(!domain_pfn_supported(domain, start_pfn)); |
| 1264 | BUG_ON(!domain_pfn_supported(domain, last_pfn)); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1265 | BUG_ON(start_pfn > last_pfn); |
| 1266 | |
| 1267 | /* we don't need lock here; nobody else touches the iova range */ |
| 1268 | freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw), |
| 1269 | domain->pgd, 0, start_pfn, last_pfn, NULL); |
| 1270 | |
| 1271 | /* free pgd */ |
| 1272 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { |
| 1273 | struct page *pgd_page = virt_to_page(domain->pgd); |
| 1274 | pgd_page->freelist = freelist; |
| 1275 | freelist = pgd_page; |
| 1276 | |
| 1277 | domain->pgd = NULL; |
| 1278 | } |
| 1279 | |
| 1280 | return freelist; |
| 1281 | } |
| 1282 | |
Joerg Roedel | b690420 | 2015-08-13 11:32:18 +0200 | [diff] [blame] | 1283 | static void dma_free_pagelist(struct page *freelist) |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1284 | { |
| 1285 | struct page *pg; |
| 1286 | |
| 1287 | while ((pg = freelist)) { |
| 1288 | freelist = pg->freelist; |
| 1289 | free_pgtable_page(page_address(pg)); |
| 1290 | } |
| 1291 | } |
| 1292 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1293 | /* iommu handling */ |
| 1294 | static int iommu_alloc_root_entry(struct intel_iommu *iommu) |
| 1295 | { |
| 1296 | struct root_entry *root; |
| 1297 | unsigned long flags; |
| 1298 | |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 1299 | root = (struct root_entry *)alloc_pgtable_page(iommu->node); |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 1300 | if (!root) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 1301 | pr_err("Allocating root entry for %s failed\n", |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 1302 | iommu->name); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1303 | return -ENOMEM; |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 1304 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1305 | |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 1306 | __iommu_flush_cache(iommu, root, ROOT_SIZE); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1307 | |
| 1308 | spin_lock_irqsave(&iommu->lock, flags); |
| 1309 | iommu->root_entry = root; |
| 1310 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 1311 | |
| 1312 | return 0; |
| 1313 | } |
| 1314 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1315 | static void iommu_set_root_entry(struct intel_iommu *iommu) |
| 1316 | { |
David Woodhouse | 03ecc32 | 2015-02-13 14:35:21 +0000 | [diff] [blame] | 1317 | u64 addr; |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1318 | u32 sts; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1319 | unsigned long flag; |
| 1320 | |
David Woodhouse | 03ecc32 | 2015-02-13 14:35:21 +0000 | [diff] [blame] | 1321 | addr = virt_to_phys(iommu->root_entry); |
David Woodhouse | c83b2f2 | 2015-06-12 10:15:49 +0100 | [diff] [blame] | 1322 | if (ecs_enabled(iommu)) |
David Woodhouse | 03ecc32 | 2015-02-13 14:35:21 +0000 | [diff] [blame] | 1323 | addr |= DMA_RTADDR_RTT; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1324 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1325 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
David Woodhouse | 03ecc32 | 2015-02-13 14:35:21 +0000 | [diff] [blame] | 1326 | dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1327 | |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1328 | writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1329 | |
| 1330 | /* Make sure hardware complete it */ |
| 1331 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1332 | readl, (sts & DMA_GSTS_RTPS), sts); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1333 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1334 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1335 | } |
| 1336 | |
| 1337 | static void iommu_flush_write_buffer(struct intel_iommu *iommu) |
| 1338 | { |
| 1339 | u32 val; |
| 1340 | unsigned long flag; |
| 1341 | |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 1342 | if (!rwbf_quirk && !cap_rwbf(iommu->cap)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1343 | return; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1344 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1345 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
David Woodhouse | 462b60f | 2009-05-10 20:18:18 +0100 | [diff] [blame] | 1346 | writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1347 | |
| 1348 | /* Make sure hardware complete it */ |
| 1349 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1350 | readl, (!(val & DMA_GSTS_WBFS)), val); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1351 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1352 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1353 | } |
| 1354 | |
| 1355 | /* return value determine if we need a write buffer flush */ |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 1356 | static void __iommu_flush_context(struct intel_iommu *iommu, |
| 1357 | u16 did, u16 source_id, u8 function_mask, |
| 1358 | u64 type) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1359 | { |
| 1360 | u64 val = 0; |
| 1361 | unsigned long flag; |
| 1362 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1363 | switch (type) { |
| 1364 | case DMA_CCMD_GLOBAL_INVL: |
| 1365 | val = DMA_CCMD_GLOBAL_INVL; |
| 1366 | break; |
| 1367 | case DMA_CCMD_DOMAIN_INVL: |
| 1368 | val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did); |
| 1369 | break; |
| 1370 | case DMA_CCMD_DEVICE_INVL: |
| 1371 | val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did) |
| 1372 | | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask); |
| 1373 | break; |
| 1374 | default: |
| 1375 | BUG(); |
| 1376 | } |
| 1377 | val |= DMA_CCMD_ICC; |
| 1378 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1379 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1380 | dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); |
| 1381 | |
| 1382 | /* Make sure hardware complete it */ |
| 1383 | IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, |
| 1384 | dmar_readq, (!(val & DMA_CCMD_ICC)), val); |
| 1385 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1386 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1387 | } |
| 1388 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1389 | /* return value determine if we need a write buffer flush */ |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 1390 | static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, |
| 1391 | u64 addr, unsigned int size_order, u64 type) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1392 | { |
| 1393 | int tlb_offset = ecap_iotlb_offset(iommu->ecap); |
| 1394 | u64 val = 0, val_iva = 0; |
| 1395 | unsigned long flag; |
| 1396 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1397 | switch (type) { |
| 1398 | case DMA_TLB_GLOBAL_FLUSH: |
| 1399 | /* global flush doesn't need set IVA_REG */ |
| 1400 | val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT; |
| 1401 | break; |
| 1402 | case DMA_TLB_DSI_FLUSH: |
| 1403 | val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); |
| 1404 | break; |
| 1405 | case DMA_TLB_PSI_FLUSH: |
| 1406 | val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1407 | /* IH bit is passed in as part of address */ |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1408 | val_iva = size_order | addr; |
| 1409 | break; |
| 1410 | default: |
| 1411 | BUG(); |
| 1412 | } |
| 1413 | /* Note: set drain read/write */ |
| 1414 | #if 0 |
| 1415 | /* |
| 1416 | * This is probably to be super secure.. Looks like we can |
| 1417 | * ignore it without any impact. |
| 1418 | */ |
| 1419 | if (cap_read_drain(iommu->cap)) |
| 1420 | val |= DMA_TLB_READ_DRAIN; |
| 1421 | #endif |
| 1422 | if (cap_write_drain(iommu->cap)) |
| 1423 | val |= DMA_TLB_WRITE_DRAIN; |
| 1424 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1425 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1426 | /* Note: Only uses first TLB reg currently */ |
| 1427 | if (val_iva) |
| 1428 | dmar_writeq(iommu->reg + tlb_offset, val_iva); |
| 1429 | dmar_writeq(iommu->reg + tlb_offset + 8, val); |
| 1430 | |
| 1431 | /* Make sure hardware complete it */ |
| 1432 | IOMMU_WAIT_OP(iommu, tlb_offset + 8, |
| 1433 | dmar_readq, (!(val & DMA_TLB_IVT)), val); |
| 1434 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1435 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1436 | |
| 1437 | /* check IOTLB invalidation granularity */ |
| 1438 | if (DMA_TLB_IAIG(val) == 0) |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 1439 | pr_err("Flush IOTLB failed\n"); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1440 | if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type)) |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 1441 | pr_debug("TLB flush request %Lx, actual %Lx\n", |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 1442 | (unsigned long long)DMA_TLB_IIRG(type), |
| 1443 | (unsigned long long)DMA_TLB_IAIG(val)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1444 | } |
| 1445 | |
David Woodhouse | 64ae892 | 2014-03-09 12:52:30 -0700 | [diff] [blame] | 1446 | static struct device_domain_info * |
| 1447 | iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu, |
| 1448 | u8 bus, u8 devfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1449 | { |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1450 | struct device_domain_info *info; |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1451 | |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 1452 | assert_spin_locked(&device_domain_lock); |
| 1453 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1454 | if (!iommu->qi) |
| 1455 | return NULL; |
| 1456 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1457 | list_for_each_entry(info, &domain->devices, link) |
Jiang Liu | c3b497c | 2014-07-11 14:19:25 +0800 | [diff] [blame] | 1458 | if (info->iommu == iommu && info->bus == bus && |
| 1459 | info->devfn == devfn) { |
David Woodhouse | b16d0cb | 2015-10-12 14:17:37 +0100 | [diff] [blame] | 1460 | if (info->ats_supported && info->dev) |
| 1461 | return info; |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1462 | break; |
| 1463 | } |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1464 | |
David Woodhouse | b16d0cb | 2015-10-12 14:17:37 +0100 | [diff] [blame] | 1465 | return NULL; |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1466 | } |
| 1467 | |
Omer Peleg | 0824c59 | 2016-04-20 19:03:35 +0300 | [diff] [blame] | 1468 | static void domain_update_iotlb(struct dmar_domain *domain) |
| 1469 | { |
| 1470 | struct device_domain_info *info; |
| 1471 | bool has_iotlb_device = false; |
| 1472 | |
| 1473 | assert_spin_locked(&device_domain_lock); |
| 1474 | |
| 1475 | list_for_each_entry(info, &domain->devices, link) { |
| 1476 | struct pci_dev *pdev; |
| 1477 | |
| 1478 | if (!info->dev || !dev_is_pci(info->dev)) |
| 1479 | continue; |
| 1480 | |
| 1481 | pdev = to_pci_dev(info->dev); |
| 1482 | if (pdev->ats_enabled) { |
| 1483 | has_iotlb_device = true; |
| 1484 | break; |
| 1485 | } |
| 1486 | } |
| 1487 | |
| 1488 | domain->has_iotlb_device = has_iotlb_device; |
| 1489 | } |
| 1490 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1491 | static void iommu_enable_dev_iotlb(struct device_domain_info *info) |
| 1492 | { |
Bjorn Helgaas | fb0cc3a | 2015-07-20 09:10:36 -0500 | [diff] [blame] | 1493 | struct pci_dev *pdev; |
| 1494 | |
Omer Peleg | 0824c59 | 2016-04-20 19:03:35 +0300 | [diff] [blame] | 1495 | assert_spin_locked(&device_domain_lock); |
| 1496 | |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 1497 | if (!info || !dev_is_pci(info->dev)) |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1498 | return; |
| 1499 | |
Bjorn Helgaas | fb0cc3a | 2015-07-20 09:10:36 -0500 | [diff] [blame] | 1500 | pdev = to_pci_dev(info->dev); |
Bjorn Helgaas | fb0cc3a | 2015-07-20 09:10:36 -0500 | [diff] [blame] | 1501 | |
David Woodhouse | b16d0cb | 2015-10-12 14:17:37 +0100 | [diff] [blame] | 1502 | #ifdef CONFIG_INTEL_IOMMU_SVM |
| 1503 | /* The PCIe spec, in its wisdom, declares that the behaviour of |
| 1504 | the device if you enable PASID support after ATS support is |
| 1505 | undefined. So always enable PASID support on devices which |
| 1506 | have it, even if we can't yet know if we're ever going to |
| 1507 | use it. */ |
| 1508 | if (info->pasid_supported && !pci_enable_pasid(pdev, info->pasid_supported & ~1)) |
| 1509 | info->pasid_enabled = 1; |
| 1510 | |
| 1511 | if (info->pri_supported && !pci_reset_pri(pdev) && !pci_enable_pri(pdev, 32)) |
| 1512 | info->pri_enabled = 1; |
| 1513 | #endif |
| 1514 | if (info->ats_supported && !pci_enable_ats(pdev, VTD_PAGE_SHIFT)) { |
| 1515 | info->ats_enabled = 1; |
Omer Peleg | 0824c59 | 2016-04-20 19:03:35 +0300 | [diff] [blame] | 1516 | domain_update_iotlb(info->domain); |
David Woodhouse | b16d0cb | 2015-10-12 14:17:37 +0100 | [diff] [blame] | 1517 | info->ats_qdep = pci_ats_queue_depth(pdev); |
| 1518 | } |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1519 | } |
| 1520 | |
| 1521 | static void iommu_disable_dev_iotlb(struct device_domain_info *info) |
| 1522 | { |
David Woodhouse | b16d0cb | 2015-10-12 14:17:37 +0100 | [diff] [blame] | 1523 | struct pci_dev *pdev; |
| 1524 | |
Omer Peleg | 0824c59 | 2016-04-20 19:03:35 +0300 | [diff] [blame] | 1525 | assert_spin_locked(&device_domain_lock); |
| 1526 | |
Jeremy McNicoll | da972fb | 2016-01-14 21:33:06 -0800 | [diff] [blame] | 1527 | if (!dev_is_pci(info->dev)) |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1528 | return; |
| 1529 | |
David Woodhouse | b16d0cb | 2015-10-12 14:17:37 +0100 | [diff] [blame] | 1530 | pdev = to_pci_dev(info->dev); |
| 1531 | |
| 1532 | if (info->ats_enabled) { |
| 1533 | pci_disable_ats(pdev); |
| 1534 | info->ats_enabled = 0; |
Omer Peleg | 0824c59 | 2016-04-20 19:03:35 +0300 | [diff] [blame] | 1535 | domain_update_iotlb(info->domain); |
David Woodhouse | b16d0cb | 2015-10-12 14:17:37 +0100 | [diff] [blame] | 1536 | } |
| 1537 | #ifdef CONFIG_INTEL_IOMMU_SVM |
| 1538 | if (info->pri_enabled) { |
| 1539 | pci_disable_pri(pdev); |
| 1540 | info->pri_enabled = 0; |
| 1541 | } |
| 1542 | if (info->pasid_enabled) { |
| 1543 | pci_disable_pasid(pdev); |
| 1544 | info->pasid_enabled = 0; |
| 1545 | } |
| 1546 | #endif |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1547 | } |
| 1548 | |
| 1549 | static void iommu_flush_dev_iotlb(struct dmar_domain *domain, |
| 1550 | u64 addr, unsigned mask) |
| 1551 | { |
| 1552 | u16 sid, qdep; |
| 1553 | unsigned long flags; |
| 1554 | struct device_domain_info *info; |
| 1555 | |
Omer Peleg | 0824c59 | 2016-04-20 19:03:35 +0300 | [diff] [blame] | 1556 | if (!domain->has_iotlb_device) |
| 1557 | return; |
| 1558 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1559 | spin_lock_irqsave(&device_domain_lock, flags); |
| 1560 | list_for_each_entry(info, &domain->devices, link) { |
David Woodhouse | b16d0cb | 2015-10-12 14:17:37 +0100 | [diff] [blame] | 1561 | if (!info->ats_enabled) |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1562 | continue; |
| 1563 | |
| 1564 | sid = info->bus << 8 | info->devfn; |
David Woodhouse | b16d0cb | 2015-10-12 14:17:37 +0100 | [diff] [blame] | 1565 | qdep = info->ats_qdep; |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1566 | qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask); |
| 1567 | } |
| 1568 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 1569 | } |
| 1570 | |
Joerg Roedel | a1ddcbe | 2015-07-21 15:20:32 +0200 | [diff] [blame] | 1571 | static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, |
| 1572 | struct dmar_domain *domain, |
| 1573 | unsigned long pfn, unsigned int pages, |
| 1574 | int ih, int map) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1575 | { |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1576 | unsigned int mask = ilog2(__roundup_pow_of_two(pages)); |
David Woodhouse | 03d6a24 | 2009-06-28 15:33:46 +0100 | [diff] [blame] | 1577 | uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT; |
Joerg Roedel | a1ddcbe | 2015-07-21 15:20:32 +0200 | [diff] [blame] | 1578 | u16 did = domain->iommu_did[iommu->seq_id]; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1579 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1580 | BUG_ON(pages == 0); |
| 1581 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1582 | if (ih) |
| 1583 | ih = 1 << 6; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1584 | /* |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1585 | * Fallback to domain selective flush if no PSI support or the size is |
| 1586 | * too big. |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1587 | * PSI requires page size to be 2 ^ x, and the base address is naturally |
| 1588 | * aligned to the size |
| 1589 | */ |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1590 | if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap)) |
| 1591 | iommu->flush.flush_iotlb(iommu, did, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 1592 | DMA_TLB_DSI_FLUSH); |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1593 | else |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1594 | iommu->flush.flush_iotlb(iommu, did, addr | ih, mask, |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1595 | DMA_TLB_PSI_FLUSH); |
Yu Zhao | bf92df3 | 2009-06-29 11:31:45 +0800 | [diff] [blame] | 1596 | |
| 1597 | /* |
Nadav Amit | 8265363 | 2010-04-01 13:24:40 +0300 | [diff] [blame] | 1598 | * In caching mode, changes of pages from non-present to present require |
| 1599 | * flush. However, device IOTLB doesn't need to be flushed in this case. |
Yu Zhao | bf92df3 | 2009-06-29 11:31:45 +0800 | [diff] [blame] | 1600 | */ |
Nadav Amit | 8265363 | 2010-04-01 13:24:40 +0300 | [diff] [blame] | 1601 | if (!cap_caching_mode(iommu->cap) || !map) |
Joerg Roedel | 9452d5b | 2015-07-21 10:00:56 +0200 | [diff] [blame] | 1602 | iommu_flush_dev_iotlb(get_iommu_domain(iommu, did), |
| 1603 | addr, mask); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1604 | } |
| 1605 | |
mark gross | f8bab73 | 2008-02-08 04:18:38 -0800 | [diff] [blame] | 1606 | static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu) |
| 1607 | { |
| 1608 | u32 pmen; |
| 1609 | unsigned long flags; |
| 1610 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1611 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
mark gross | f8bab73 | 2008-02-08 04:18:38 -0800 | [diff] [blame] | 1612 | pmen = readl(iommu->reg + DMAR_PMEN_REG); |
| 1613 | pmen &= ~DMA_PMEN_EPM; |
| 1614 | writel(pmen, iommu->reg + DMAR_PMEN_REG); |
| 1615 | |
| 1616 | /* wait for the protected region status bit to clear */ |
| 1617 | IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG, |
| 1618 | readl, !(pmen & DMA_PMEN_PRS), pmen); |
| 1619 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1620 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
mark gross | f8bab73 | 2008-02-08 04:18:38 -0800 | [diff] [blame] | 1621 | } |
| 1622 | |
Jiang Liu | 2a41cce | 2014-07-11 14:19:33 +0800 | [diff] [blame] | 1623 | static void iommu_enable_translation(struct intel_iommu *iommu) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1624 | { |
| 1625 | u32 sts; |
| 1626 | unsigned long flags; |
| 1627 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1628 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1629 | iommu->gcmd |= DMA_GCMD_TE; |
| 1630 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1631 | |
| 1632 | /* Make sure hardware complete it */ |
| 1633 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1634 | readl, (sts & DMA_GSTS_TES), sts); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1635 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1636 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1637 | } |
| 1638 | |
Jiang Liu | 2a41cce | 2014-07-11 14:19:33 +0800 | [diff] [blame] | 1639 | static void iommu_disable_translation(struct intel_iommu *iommu) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1640 | { |
| 1641 | u32 sts; |
| 1642 | unsigned long flag; |
| 1643 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1644 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1645 | iommu->gcmd &= ~DMA_GCMD_TE; |
| 1646 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
| 1647 | |
| 1648 | /* Make sure hardware complete it */ |
| 1649 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1650 | readl, (!(sts & DMA_GSTS_TES)), sts); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1651 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1652 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1653 | } |
| 1654 | |
Keshavamurthy, Anil S | 3460a6d | 2007-10-21 16:41:54 -0700 | [diff] [blame] | 1655 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1656 | static int iommu_init_domains(struct intel_iommu *iommu) |
| 1657 | { |
Joerg Roedel | 8bf4781 | 2015-07-21 10:41:21 +0200 | [diff] [blame] | 1658 | u32 ndomains, nlongs; |
| 1659 | size_t size; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1660 | |
| 1661 | ndomains = cap_ndoms(iommu->cap); |
Joerg Roedel | 8bf4781 | 2015-07-21 10:41:21 +0200 | [diff] [blame] | 1662 | pr_debug("%s: Number of Domains supported <%d>\n", |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 1663 | iommu->name, ndomains); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1664 | nlongs = BITS_TO_LONGS(ndomains); |
| 1665 | |
Donald Dutile | 94a91b5 | 2009-08-20 16:51:34 -0400 | [diff] [blame] | 1666 | spin_lock_init(&iommu->lock); |
| 1667 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1668 | iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL); |
| 1669 | if (!iommu->domain_ids) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 1670 | pr_err("%s: Allocating domain id array failed\n", |
| 1671 | iommu->name); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1672 | return -ENOMEM; |
| 1673 | } |
Joerg Roedel | 8bf4781 | 2015-07-21 10:41:21 +0200 | [diff] [blame] | 1674 | |
Wei Yang | 86f004c | 2016-05-21 02:41:51 +0000 | [diff] [blame] | 1675 | size = (ALIGN(ndomains, 256) >> 8) * sizeof(struct dmar_domain **); |
Joerg Roedel | 8bf4781 | 2015-07-21 10:41:21 +0200 | [diff] [blame] | 1676 | iommu->domains = kzalloc(size, GFP_KERNEL); |
| 1677 | |
| 1678 | if (iommu->domains) { |
| 1679 | size = 256 * sizeof(struct dmar_domain *); |
| 1680 | iommu->domains[0] = kzalloc(size, GFP_KERNEL); |
| 1681 | } |
| 1682 | |
| 1683 | if (!iommu->domains || !iommu->domains[0]) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 1684 | pr_err("%s: Allocating domain array failed\n", |
| 1685 | iommu->name); |
Jiang Liu | 852bdb0 | 2014-01-06 14:18:11 +0800 | [diff] [blame] | 1686 | kfree(iommu->domain_ids); |
Joerg Roedel | 8bf4781 | 2015-07-21 10:41:21 +0200 | [diff] [blame] | 1687 | kfree(iommu->domains); |
Jiang Liu | 852bdb0 | 2014-01-06 14:18:11 +0800 | [diff] [blame] | 1688 | iommu->domain_ids = NULL; |
Joerg Roedel | 8bf4781 | 2015-07-21 10:41:21 +0200 | [diff] [blame] | 1689 | iommu->domains = NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1690 | return -ENOMEM; |
| 1691 | } |
| 1692 | |
Joerg Roedel | 8bf4781 | 2015-07-21 10:41:21 +0200 | [diff] [blame] | 1693 | |
| 1694 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1695 | /* |
Joerg Roedel | c0e8a6c | 2015-07-21 09:39:46 +0200 | [diff] [blame] | 1696 | * If Caching mode is set, then invalid translations are tagged |
| 1697 | * with domain-id 0, hence we need to pre-allocate it. We also |
| 1698 | * use domain-id 0 as a marker for non-allocated domain-id, so |
| 1699 | * make sure it is not used for a real domain. |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1700 | */ |
Joerg Roedel | c0e8a6c | 2015-07-21 09:39:46 +0200 | [diff] [blame] | 1701 | set_bit(0, iommu->domain_ids); |
| 1702 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1703 | return 0; |
| 1704 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1705 | |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 1706 | static void disable_dmar_iommu(struct intel_iommu *iommu) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1707 | { |
Joerg Roedel | 29a2771 | 2015-07-21 17:17:12 +0200 | [diff] [blame] | 1708 | struct device_domain_info *info, *tmp; |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 1709 | unsigned long flags; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1710 | |
Joerg Roedel | 29a2771 | 2015-07-21 17:17:12 +0200 | [diff] [blame] | 1711 | if (!iommu->domains || !iommu->domain_ids) |
| 1712 | return; |
Jiang Liu | a4eaa86 | 2014-02-19 14:07:30 +0800 | [diff] [blame] | 1713 | |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 1714 | spin_lock_irqsave(&device_domain_lock, flags); |
Joerg Roedel | 29a2771 | 2015-07-21 17:17:12 +0200 | [diff] [blame] | 1715 | list_for_each_entry_safe(info, tmp, &device_domain_list, global) { |
| 1716 | struct dmar_domain *domain; |
| 1717 | |
| 1718 | if (info->iommu != iommu) |
| 1719 | continue; |
| 1720 | |
| 1721 | if (!info->dev || !info->domain) |
| 1722 | continue; |
| 1723 | |
| 1724 | domain = info->domain; |
| 1725 | |
Joerg Roedel | e6de0f8 | 2015-07-22 16:30:36 +0200 | [diff] [blame] | 1726 | dmar_remove_one_dev_info(domain, info->dev); |
Joerg Roedel | 29a2771 | 2015-07-21 17:17:12 +0200 | [diff] [blame] | 1727 | |
| 1728 | if (!domain_type_is_vm_or_si(domain)) |
| 1729 | domain_exit(domain); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1730 | } |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 1731 | spin_unlock_irqrestore(&device_domain_lock, flags); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1732 | |
| 1733 | if (iommu->gcmd & DMA_GCMD_TE) |
| 1734 | iommu_disable_translation(iommu); |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 1735 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1736 | |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 1737 | static void free_dmar_iommu(struct intel_iommu *iommu) |
| 1738 | { |
| 1739 | if ((iommu->domains) && (iommu->domain_ids)) { |
Wei Yang | 86f004c | 2016-05-21 02:41:51 +0000 | [diff] [blame] | 1740 | int elems = ALIGN(cap_ndoms(iommu->cap), 256) >> 8; |
Joerg Roedel | 8bf4781 | 2015-07-21 10:41:21 +0200 | [diff] [blame] | 1741 | int i; |
| 1742 | |
| 1743 | for (i = 0; i < elems; i++) |
| 1744 | kfree(iommu->domains[i]); |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 1745 | kfree(iommu->domains); |
| 1746 | kfree(iommu->domain_ids); |
| 1747 | iommu->domains = NULL; |
| 1748 | iommu->domain_ids = NULL; |
| 1749 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1750 | |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 1751 | g_iommus[iommu->seq_id] = NULL; |
| 1752 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1753 | /* free context mapping */ |
| 1754 | free_context_table(iommu); |
David Woodhouse | 8a94ade | 2015-03-24 14:54:56 +0000 | [diff] [blame] | 1755 | |
| 1756 | #ifdef CONFIG_INTEL_IOMMU_SVM |
David Woodhouse | a222a7f | 2015-10-07 23:35:18 +0100 | [diff] [blame] | 1757 | if (pasid_enabled(iommu)) { |
| 1758 | if (ecap_prs(iommu->ecap)) |
| 1759 | intel_svm_finish_prq(iommu); |
David Woodhouse | 8a94ade | 2015-03-24 14:54:56 +0000 | [diff] [blame] | 1760 | intel_svm_free_pasid_tables(iommu); |
David Woodhouse | a222a7f | 2015-10-07 23:35:18 +0100 | [diff] [blame] | 1761 | } |
David Woodhouse | 8a94ade | 2015-03-24 14:54:56 +0000 | [diff] [blame] | 1762 | #endif |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1763 | } |
| 1764 | |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 1765 | static struct dmar_domain *alloc_domain(int flags) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1766 | { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1767 | struct dmar_domain *domain; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1768 | |
| 1769 | domain = alloc_domain_mem(); |
| 1770 | if (!domain) |
| 1771 | return NULL; |
| 1772 | |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 1773 | memset(domain, 0, sizeof(*domain)); |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 1774 | domain->nid = -1; |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 1775 | domain->flags = flags; |
Omer Peleg | 0824c59 | 2016-04-20 19:03:35 +0300 | [diff] [blame] | 1776 | domain->has_iotlb_device = false; |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1777 | INIT_LIST_HEAD(&domain->devices); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1778 | |
| 1779 | return domain; |
| 1780 | } |
| 1781 | |
Joerg Roedel | d160aca | 2015-07-22 11:52:53 +0200 | [diff] [blame] | 1782 | /* Must be called with iommu->lock */ |
| 1783 | static int domain_attach_iommu(struct dmar_domain *domain, |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1784 | struct intel_iommu *iommu) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1785 | { |
Jiang Liu | 44bde61 | 2014-07-11 14:19:29 +0800 | [diff] [blame] | 1786 | unsigned long ndomains; |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 1787 | int num; |
Jiang Liu | 44bde61 | 2014-07-11 14:19:29 +0800 | [diff] [blame] | 1788 | |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 1789 | assert_spin_locked(&device_domain_lock); |
Joerg Roedel | d160aca | 2015-07-22 11:52:53 +0200 | [diff] [blame] | 1790 | assert_spin_locked(&iommu->lock); |
Jiang Liu | 44bde61 | 2014-07-11 14:19:29 +0800 | [diff] [blame] | 1791 | |
Joerg Roedel | 29a2771 | 2015-07-21 17:17:12 +0200 | [diff] [blame] | 1792 | domain->iommu_refcnt[iommu->seq_id] += 1; |
| 1793 | domain->iommu_count += 1; |
| 1794 | if (domain->iommu_refcnt[iommu->seq_id] == 1) { |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1795 | ndomains = cap_ndoms(iommu->cap); |
Joerg Roedel | d160aca | 2015-07-22 11:52:53 +0200 | [diff] [blame] | 1796 | num = find_first_zero_bit(iommu->domain_ids, ndomains); |
| 1797 | |
| 1798 | if (num >= ndomains) { |
| 1799 | pr_err("%s: No free domain ids\n", iommu->name); |
| 1800 | domain->iommu_refcnt[iommu->seq_id] -= 1; |
| 1801 | domain->iommu_count -= 1; |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 1802 | return -ENOSPC; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1803 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1804 | |
Joerg Roedel | d160aca | 2015-07-22 11:52:53 +0200 | [diff] [blame] | 1805 | set_bit(num, iommu->domain_ids); |
| 1806 | set_iommu_domain(iommu, num, domain); |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1807 | |
Joerg Roedel | d160aca | 2015-07-22 11:52:53 +0200 | [diff] [blame] | 1808 | domain->iommu_did[iommu->seq_id] = num; |
| 1809 | domain->nid = iommu->node; |
| 1810 | |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1811 | domain_update_iommu_cap(domain); |
| 1812 | } |
Joerg Roedel | d160aca | 2015-07-22 11:52:53 +0200 | [diff] [blame] | 1813 | |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 1814 | return 0; |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1815 | } |
| 1816 | |
| 1817 | static int domain_detach_iommu(struct dmar_domain *domain, |
| 1818 | struct intel_iommu *iommu) |
| 1819 | { |
Joerg Roedel | d160aca | 2015-07-22 11:52:53 +0200 | [diff] [blame] | 1820 | int num, count = INT_MAX; |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1821 | |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 1822 | assert_spin_locked(&device_domain_lock); |
Joerg Roedel | d160aca | 2015-07-22 11:52:53 +0200 | [diff] [blame] | 1823 | assert_spin_locked(&iommu->lock); |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1824 | |
Joerg Roedel | 29a2771 | 2015-07-21 17:17:12 +0200 | [diff] [blame] | 1825 | domain->iommu_refcnt[iommu->seq_id] -= 1; |
| 1826 | count = --domain->iommu_count; |
| 1827 | if (domain->iommu_refcnt[iommu->seq_id] == 0) { |
Joerg Roedel | d160aca | 2015-07-22 11:52:53 +0200 | [diff] [blame] | 1828 | num = domain->iommu_did[iommu->seq_id]; |
| 1829 | clear_bit(num, iommu->domain_ids); |
| 1830 | set_iommu_domain(iommu, num, NULL); |
| 1831 | |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1832 | domain_update_iommu_cap(domain); |
Joerg Roedel | c0e8a6c | 2015-07-21 09:39:46 +0200 | [diff] [blame] | 1833 | domain->iommu_did[iommu->seq_id] = 0; |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1834 | } |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1835 | |
| 1836 | return count; |
| 1837 | } |
| 1838 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1839 | static struct iova_domain reserved_iova_list; |
Mark Gross | 8a443df | 2008-03-04 14:59:31 -0800 | [diff] [blame] | 1840 | static struct lock_class_key reserved_rbtree_key; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1841 | |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1842 | static int dmar_init_reserved_ranges(void) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1843 | { |
| 1844 | struct pci_dev *pdev = NULL; |
| 1845 | struct iova *iova; |
| 1846 | int i; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1847 | |
Robin Murphy | 0fb5fe8 | 2015-01-12 17:51:16 +0000 | [diff] [blame] | 1848 | init_iova_domain(&reserved_iova_list, VTD_PAGE_SIZE, IOVA_START_PFN, |
| 1849 | DMA_32BIT_PFN); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1850 | |
Mark Gross | 8a443df | 2008-03-04 14:59:31 -0800 | [diff] [blame] | 1851 | lockdep_set_class(&reserved_iova_list.iova_rbtree_lock, |
| 1852 | &reserved_rbtree_key); |
| 1853 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1854 | /* IOAPIC ranges shouldn't be accessed by DMA */ |
| 1855 | iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START), |
| 1856 | IOVA_PFN(IOAPIC_RANGE_END)); |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1857 | if (!iova) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 1858 | pr_err("Reserve IOAPIC range failed\n"); |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1859 | return -ENODEV; |
| 1860 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1861 | |
| 1862 | /* Reserve all PCI MMIO to avoid peer-to-peer access */ |
| 1863 | for_each_pci_dev(pdev) { |
| 1864 | struct resource *r; |
| 1865 | |
| 1866 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
| 1867 | r = &pdev->resource[i]; |
| 1868 | if (!r->flags || !(r->flags & IORESOURCE_MEM)) |
| 1869 | continue; |
David Woodhouse | 1a4a455 | 2009-06-28 16:00:42 +0100 | [diff] [blame] | 1870 | iova = reserve_iova(&reserved_iova_list, |
| 1871 | IOVA_PFN(r->start), |
| 1872 | IOVA_PFN(r->end)); |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1873 | if (!iova) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 1874 | pr_err("Reserve iova failed\n"); |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1875 | return -ENODEV; |
| 1876 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1877 | } |
| 1878 | } |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1879 | return 0; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1880 | } |
| 1881 | |
| 1882 | static void domain_reserve_special_ranges(struct dmar_domain *domain) |
| 1883 | { |
| 1884 | copy_reserved_iova(&reserved_iova_list, &domain->iovad); |
| 1885 | } |
| 1886 | |
| 1887 | static inline int guestwidth_to_adjustwidth(int gaw) |
| 1888 | { |
| 1889 | int agaw; |
| 1890 | int r = (gaw - 12) % 9; |
| 1891 | |
| 1892 | if (r == 0) |
| 1893 | agaw = gaw; |
| 1894 | else |
| 1895 | agaw = gaw + 9 - r; |
| 1896 | if (agaw > 64) |
| 1897 | agaw = 64; |
| 1898 | return agaw; |
| 1899 | } |
| 1900 | |
Joerg Roedel | dc534b2 | 2015-07-22 12:44:02 +0200 | [diff] [blame] | 1901 | static int domain_init(struct dmar_domain *domain, struct intel_iommu *iommu, |
| 1902 | int guest_width) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1903 | { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1904 | int adjust_width, agaw; |
| 1905 | unsigned long sagaw; |
| 1906 | |
Robin Murphy | 0fb5fe8 | 2015-01-12 17:51:16 +0000 | [diff] [blame] | 1907 | init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN, |
| 1908 | DMA_32BIT_PFN); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1909 | domain_reserve_special_ranges(domain); |
| 1910 | |
| 1911 | /* calculate AGAW */ |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1912 | if (guest_width > cap_mgaw(iommu->cap)) |
| 1913 | guest_width = cap_mgaw(iommu->cap); |
| 1914 | domain->gaw = guest_width; |
| 1915 | adjust_width = guestwidth_to_adjustwidth(guest_width); |
| 1916 | agaw = width_to_agaw(adjust_width); |
| 1917 | sagaw = cap_sagaw(iommu->cap); |
| 1918 | if (!test_bit(agaw, &sagaw)) { |
| 1919 | /* hardware doesn't support it, choose a bigger one */ |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 1920 | pr_debug("Hardware doesn't support agaw %d\n", agaw); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1921 | agaw = find_next_bit(&sagaw, 5, agaw); |
| 1922 | if (agaw >= 5) |
| 1923 | return -ENODEV; |
| 1924 | } |
| 1925 | domain->agaw = agaw; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1926 | |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 1927 | if (ecap_coherent(iommu->ecap)) |
| 1928 | domain->iommu_coherency = 1; |
| 1929 | else |
| 1930 | domain->iommu_coherency = 0; |
| 1931 | |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 1932 | if (ecap_sc_support(iommu->ecap)) |
| 1933 | domain->iommu_snooping = 1; |
| 1934 | else |
| 1935 | domain->iommu_snooping = 0; |
| 1936 | |
David Woodhouse | 214e39a | 2014-03-19 10:38:49 +0000 | [diff] [blame] | 1937 | if (intel_iommu_superpage) |
| 1938 | domain->iommu_superpage = fls(cap_super_page_val(iommu->cap)); |
| 1939 | else |
| 1940 | domain->iommu_superpage = 0; |
| 1941 | |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 1942 | domain->nid = iommu->node; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1943 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1944 | /* always allocate the top pgd */ |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 1945 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1946 | if (!domain->pgd) |
| 1947 | return -ENOMEM; |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 1948 | __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1949 | return 0; |
| 1950 | } |
| 1951 | |
| 1952 | static void domain_exit(struct dmar_domain *domain) |
| 1953 | { |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1954 | struct page *freelist = NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1955 | |
| 1956 | /* Domain 0 is reserved, so dont process it */ |
| 1957 | if (!domain) |
| 1958 | return; |
| 1959 | |
Alex Williamson | 7b66835 | 2011-05-24 12:02:41 +0100 | [diff] [blame] | 1960 | /* Flush any lazy unmaps that may reference this domain */ |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 1961 | if (!intel_iommu_strict) { |
| 1962 | int cpu; |
| 1963 | |
| 1964 | for_each_possible_cpu(cpu) |
| 1965 | flush_unmaps_timeout(cpu); |
| 1966 | } |
Alex Williamson | 7b66835 | 2011-05-24 12:02:41 +0100 | [diff] [blame] | 1967 | |
Joerg Roedel | d160aca | 2015-07-22 11:52:53 +0200 | [diff] [blame] | 1968 | /* Remove associated devices and clear attached or cached domains */ |
| 1969 | rcu_read_lock(); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1970 | domain_remove_dev_info(domain); |
Joerg Roedel | d160aca | 2015-07-22 11:52:53 +0200 | [diff] [blame] | 1971 | rcu_read_unlock(); |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1972 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1973 | /* destroy iovas */ |
| 1974 | put_iova_domain(&domain->iovad); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1975 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1976 | freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1977 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1978 | dma_free_pagelist(freelist); |
| 1979 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1980 | free_domain_mem(domain); |
| 1981 | } |
| 1982 | |
David Woodhouse | 64ae892 | 2014-03-09 12:52:30 -0700 | [diff] [blame] | 1983 | static int domain_context_mapping_one(struct dmar_domain *domain, |
| 1984 | struct intel_iommu *iommu, |
Joerg Roedel | 28ccce0 | 2015-07-21 14:45:31 +0200 | [diff] [blame] | 1985 | u8 bus, u8 devfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1986 | { |
Joerg Roedel | c6c2ceb | 2015-07-22 13:11:53 +0200 | [diff] [blame] | 1987 | u16 did = domain->iommu_did[iommu->seq_id]; |
Joerg Roedel | 28ccce0 | 2015-07-21 14:45:31 +0200 | [diff] [blame] | 1988 | int translation = CONTEXT_TT_MULTI_LEVEL; |
| 1989 | struct device_domain_info *info = NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1990 | struct context_entry *context; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1991 | unsigned long flags; |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1992 | struct dma_pte *pgd; |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 1993 | int ret, agaw; |
Joerg Roedel | 28ccce0 | 2015-07-21 14:45:31 +0200 | [diff] [blame] | 1994 | |
Joerg Roedel | c6c2ceb | 2015-07-22 13:11:53 +0200 | [diff] [blame] | 1995 | WARN_ON(did == 0); |
| 1996 | |
Joerg Roedel | 28ccce0 | 2015-07-21 14:45:31 +0200 | [diff] [blame] | 1997 | if (hw_pass_through && domain_type_is_si(domain)) |
| 1998 | translation = CONTEXT_TT_PASS_THROUGH; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1999 | |
| 2000 | pr_debug("Set context mapping for %02x:%02x.%d\n", |
| 2001 | bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2002 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2003 | BUG_ON(!domain->pgd); |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 2004 | |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 2005 | spin_lock_irqsave(&device_domain_lock, flags); |
| 2006 | spin_lock(&iommu->lock); |
| 2007 | |
| 2008 | ret = -ENOMEM; |
David Woodhouse | 03ecc32 | 2015-02-13 14:35:21 +0000 | [diff] [blame] | 2009 | context = iommu_context_addr(iommu, bus, devfn, 1); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2010 | if (!context) |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 2011 | goto out_unlock; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2012 | |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 2013 | ret = 0; |
| 2014 | if (context_present(context)) |
| 2015 | goto out_unlock; |
Joerg Roedel | cf484d0 | 2015-06-12 12:21:46 +0200 | [diff] [blame] | 2016 | |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 2017 | pgd = domain->pgd; |
| 2018 | |
Joerg Roedel | de24e55 | 2015-07-21 14:53:04 +0200 | [diff] [blame] | 2019 | context_clear_entry(context); |
Joerg Roedel | c6c2ceb | 2015-07-22 13:11:53 +0200 | [diff] [blame] | 2020 | context_set_domain_id(context, did); |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 2021 | |
Joerg Roedel | de24e55 | 2015-07-21 14:53:04 +0200 | [diff] [blame] | 2022 | /* |
| 2023 | * Skip top levels of page tables for iommu which has less agaw |
| 2024 | * than default. Unnecessary for PT mode. |
| 2025 | */ |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 2026 | if (translation != CONTEXT_TT_PASS_THROUGH) { |
Joerg Roedel | de24e55 | 2015-07-21 14:53:04 +0200 | [diff] [blame] | 2027 | for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) { |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 2028 | ret = -ENOMEM; |
Joerg Roedel | de24e55 | 2015-07-21 14:53:04 +0200 | [diff] [blame] | 2029 | pgd = phys_to_virt(dma_pte_addr(pgd)); |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 2030 | if (!dma_pte_present(pgd)) |
| 2031 | goto out_unlock; |
Joerg Roedel | de24e55 | 2015-07-21 14:53:04 +0200 | [diff] [blame] | 2032 | } |
| 2033 | |
David Woodhouse | 64ae892 | 2014-03-09 12:52:30 -0700 | [diff] [blame] | 2034 | info = iommu_support_dev_iotlb(domain, iommu, bus, devfn); |
David Woodhouse | b16d0cb | 2015-10-12 14:17:37 +0100 | [diff] [blame] | 2035 | if (info && info->ats_supported) |
| 2036 | translation = CONTEXT_TT_DEV_IOTLB; |
| 2037 | else |
| 2038 | translation = CONTEXT_TT_MULTI_LEVEL; |
Joerg Roedel | de24e55 | 2015-07-21 14:53:04 +0200 | [diff] [blame] | 2039 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 2040 | context_set_address_root(context, virt_to_phys(pgd)); |
| 2041 | context_set_address_width(context, iommu->agaw); |
Joerg Roedel | de24e55 | 2015-07-21 14:53:04 +0200 | [diff] [blame] | 2042 | } else { |
| 2043 | /* |
| 2044 | * In pass through mode, AW must be programmed to |
| 2045 | * indicate the largest AGAW value supported by |
| 2046 | * hardware. And ASR is ignored by hardware. |
| 2047 | */ |
| 2048 | context_set_address_width(context, iommu->msagaw); |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 2049 | } |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2050 | |
| 2051 | context_set_translation_type(context, translation); |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 2052 | context_set_fault_enable(context); |
| 2053 | context_set_present(context); |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 2054 | domain_flush_cache(domain, context, sizeof(*context)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2055 | |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 2056 | /* |
| 2057 | * It's a non-present to present mapping. If hardware doesn't cache |
| 2058 | * non-present entry we only need to flush the write-buffer. If the |
| 2059 | * _does_ cache non-present entries, then it does so in the special |
| 2060 | * domain #0, which we have to flush: |
| 2061 | */ |
| 2062 | if (cap_caching_mode(iommu->cap)) { |
| 2063 | iommu->flush.flush_context(iommu, 0, |
| 2064 | (((u16)bus) << 8) | devfn, |
| 2065 | DMA_CCMD_MASK_NOBIT, |
| 2066 | DMA_CCMD_DEVICE_INVL); |
Joerg Roedel | c6c2ceb | 2015-07-22 13:11:53 +0200 | [diff] [blame] | 2067 | iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 2068 | } else { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2069 | iommu_flush_write_buffer(iommu); |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 2070 | } |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 2071 | iommu_enable_dev_iotlb(info); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 2072 | |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 2073 | ret = 0; |
| 2074 | |
| 2075 | out_unlock: |
| 2076 | spin_unlock(&iommu->lock); |
| 2077 | spin_unlock_irqrestore(&device_domain_lock, flags); |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 2078 | |
Wei Yang | 5c365d1 | 2016-07-13 13:53:21 +0000 | [diff] [blame] | 2079 | return ret; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2080 | } |
| 2081 | |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2082 | struct domain_context_mapping_data { |
| 2083 | struct dmar_domain *domain; |
| 2084 | struct intel_iommu *iommu; |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2085 | }; |
| 2086 | |
| 2087 | static int domain_context_mapping_cb(struct pci_dev *pdev, |
| 2088 | u16 alias, void *opaque) |
| 2089 | { |
| 2090 | struct domain_context_mapping_data *data = opaque; |
| 2091 | |
| 2092 | return domain_context_mapping_one(data->domain, data->iommu, |
Joerg Roedel | 28ccce0 | 2015-07-21 14:45:31 +0200 | [diff] [blame] | 2093 | PCI_BUS_NUM(alias), alias & 0xff); |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2094 | } |
| 2095 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2096 | static int |
Joerg Roedel | 28ccce0 | 2015-07-21 14:45:31 +0200 | [diff] [blame] | 2097 | domain_context_mapping(struct dmar_domain *domain, struct device *dev) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2098 | { |
David Woodhouse | 64ae892 | 2014-03-09 12:52:30 -0700 | [diff] [blame] | 2099 | struct intel_iommu *iommu; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 2100 | u8 bus, devfn; |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2101 | struct domain_context_mapping_data data; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2102 | |
David Woodhouse | e1f167f | 2014-03-09 15:24:46 -0700 | [diff] [blame] | 2103 | iommu = device_to_iommu(dev, &bus, &devfn); |
David Woodhouse | 64ae892 | 2014-03-09 12:52:30 -0700 | [diff] [blame] | 2104 | if (!iommu) |
| 2105 | return -ENODEV; |
| 2106 | |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2107 | if (!dev_is_pci(dev)) |
Joerg Roedel | 28ccce0 | 2015-07-21 14:45:31 +0200 | [diff] [blame] | 2108 | return domain_context_mapping_one(domain, iommu, bus, devfn); |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2109 | |
| 2110 | data.domain = domain; |
| 2111 | data.iommu = iommu; |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2112 | |
| 2113 | return pci_for_each_dma_alias(to_pci_dev(dev), |
| 2114 | &domain_context_mapping_cb, &data); |
| 2115 | } |
| 2116 | |
| 2117 | static int domain_context_mapped_cb(struct pci_dev *pdev, |
| 2118 | u16 alias, void *opaque) |
| 2119 | { |
| 2120 | struct intel_iommu *iommu = opaque; |
| 2121 | |
| 2122 | return !device_context_mapped(iommu, PCI_BUS_NUM(alias), alias & 0xff); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2123 | } |
| 2124 | |
David Woodhouse | e1f167f | 2014-03-09 15:24:46 -0700 | [diff] [blame] | 2125 | static int domain_context_mapped(struct device *dev) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2126 | { |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 2127 | struct intel_iommu *iommu; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 2128 | u8 bus, devfn; |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 2129 | |
David Woodhouse | e1f167f | 2014-03-09 15:24:46 -0700 | [diff] [blame] | 2130 | iommu = device_to_iommu(dev, &bus, &devfn); |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 2131 | if (!iommu) |
| 2132 | return -ENODEV; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2133 | |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2134 | if (!dev_is_pci(dev)) |
| 2135 | return device_context_mapped(iommu, bus, devfn); |
David Woodhouse | e1f167f | 2014-03-09 15:24:46 -0700 | [diff] [blame] | 2136 | |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2137 | return !pci_for_each_dma_alias(to_pci_dev(dev), |
| 2138 | domain_context_mapped_cb, iommu); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2139 | } |
| 2140 | |
Fenghua Yu | f532959 | 2009-08-04 15:09:37 -0700 | [diff] [blame] | 2141 | /* Returns a number of VTD pages, but aligned to MM page size */ |
| 2142 | static inline unsigned long aligned_nrpages(unsigned long host_addr, |
| 2143 | size_t size) |
| 2144 | { |
| 2145 | host_addr &= ~PAGE_MASK; |
| 2146 | return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT; |
| 2147 | } |
| 2148 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2149 | /* Return largest possible superpage level for a given mapping */ |
| 2150 | static inline int hardware_largepage_caps(struct dmar_domain *domain, |
| 2151 | unsigned long iov_pfn, |
| 2152 | unsigned long phy_pfn, |
| 2153 | unsigned long pages) |
| 2154 | { |
| 2155 | int support, level = 1; |
| 2156 | unsigned long pfnmerge; |
| 2157 | |
| 2158 | support = domain->iommu_superpage; |
| 2159 | |
| 2160 | /* To use a large page, the virtual *and* physical addresses |
| 2161 | must be aligned to 2MiB/1GiB/etc. Lower bits set in either |
| 2162 | of them will mean we have to use smaller pages. So just |
| 2163 | merge them and check both at once. */ |
| 2164 | pfnmerge = iov_pfn | phy_pfn; |
| 2165 | |
| 2166 | while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) { |
| 2167 | pages >>= VTD_STRIDE_SHIFT; |
| 2168 | if (!pages) |
| 2169 | break; |
| 2170 | pfnmerge >>= VTD_STRIDE_SHIFT; |
| 2171 | level++; |
| 2172 | support--; |
| 2173 | } |
| 2174 | return level; |
| 2175 | } |
| 2176 | |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 2177 | static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
| 2178 | struct scatterlist *sg, unsigned long phys_pfn, |
| 2179 | unsigned long nr_pages, int prot) |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2180 | { |
| 2181 | struct dma_pte *first_pte = NULL, *pte = NULL; |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 2182 | phys_addr_t uninitialized_var(pteval); |
Jiang Liu | cc4f14a | 2014-11-26 09:42:10 +0800 | [diff] [blame] | 2183 | unsigned long sg_res = 0; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2184 | unsigned int largepage_lvl = 0; |
| 2185 | unsigned long lvl_pages = 0; |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2186 | |
Jiang Liu | 162d1b1 | 2014-07-11 14:19:35 +0800 | [diff] [blame] | 2187 | BUG_ON(!domain_pfn_supported(domain, iov_pfn + nr_pages - 1)); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2188 | |
| 2189 | if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0) |
| 2190 | return -EINVAL; |
| 2191 | |
| 2192 | prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP; |
| 2193 | |
Jiang Liu | cc4f14a | 2014-11-26 09:42:10 +0800 | [diff] [blame] | 2194 | if (!sg) { |
| 2195 | sg_res = nr_pages; |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 2196 | pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot; |
| 2197 | } |
| 2198 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2199 | while (nr_pages > 0) { |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 2200 | uint64_t tmp; |
| 2201 | |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2202 | if (!sg_res) { |
Fenghua Yu | f532959 | 2009-08-04 15:09:37 -0700 | [diff] [blame] | 2203 | sg_res = aligned_nrpages(sg->offset, sg->length); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2204 | sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset; |
| 2205 | sg->dma_length = sg->length; |
Dan Williams | 3e6110f | 2015-12-15 12:54:06 -0800 | [diff] [blame] | 2206 | pteval = page_to_phys(sg_page(sg)) | prot; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2207 | phys_pfn = pteval >> VTD_PAGE_SHIFT; |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2208 | } |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2209 | |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2210 | if (!pte) { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2211 | largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res); |
| 2212 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 2213 | first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2214 | if (!pte) |
| 2215 | return -ENOMEM; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2216 | /* It is large page*/ |
Woodhouse, David | 6491d4d | 2012-12-19 13:25:35 +0000 | [diff] [blame] | 2217 | if (largepage_lvl > 1) { |
Christian Zander | ba2374f | 2015-06-10 09:41:45 -0700 | [diff] [blame] | 2218 | unsigned long nr_superpages, end_pfn; |
| 2219 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2220 | pteval |= DMA_PTE_LARGE_PAGE; |
Jiang Liu | d41a4ad | 2014-07-11 14:19:34 +0800 | [diff] [blame] | 2221 | lvl_pages = lvl_to_nr_pages(largepage_lvl); |
Christian Zander | ba2374f | 2015-06-10 09:41:45 -0700 | [diff] [blame] | 2222 | |
| 2223 | nr_superpages = sg_res / lvl_pages; |
| 2224 | end_pfn = iov_pfn + nr_superpages * lvl_pages - 1; |
| 2225 | |
Jiang Liu | d41a4ad | 2014-07-11 14:19:34 +0800 | [diff] [blame] | 2226 | /* |
| 2227 | * Ensure that old small page tables are |
Christian Zander | ba2374f | 2015-06-10 09:41:45 -0700 | [diff] [blame] | 2228 | * removed to make room for superpage(s). |
Jiang Liu | d41a4ad | 2014-07-11 14:19:34 +0800 | [diff] [blame] | 2229 | */ |
Christian Zander | ba2374f | 2015-06-10 09:41:45 -0700 | [diff] [blame] | 2230 | dma_pte_free_pagetable(domain, iov_pfn, end_pfn); |
Woodhouse, David | 6491d4d | 2012-12-19 13:25:35 +0000 | [diff] [blame] | 2231 | } else { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2232 | pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE; |
Woodhouse, David | 6491d4d | 2012-12-19 13:25:35 +0000 | [diff] [blame] | 2233 | } |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2234 | |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2235 | } |
| 2236 | /* We don't need lock here, nobody else |
| 2237 | * touches the iova range |
| 2238 | */ |
David Woodhouse | 7766a3f | 2009-07-01 20:27:03 +0100 | [diff] [blame] | 2239 | tmp = cmpxchg64_local(&pte->val, 0ULL, pteval); |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 2240 | if (tmp) { |
David Woodhouse | 1bf20f0 | 2009-06-29 22:06:43 +0100 | [diff] [blame] | 2241 | static int dumps = 5; |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 2242 | pr_crit("ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n", |
| 2243 | iov_pfn, tmp, (unsigned long long)pteval); |
David Woodhouse | 1bf20f0 | 2009-06-29 22:06:43 +0100 | [diff] [blame] | 2244 | if (dumps) { |
| 2245 | dumps--; |
| 2246 | debug_dma_dump_mappings(NULL); |
| 2247 | } |
| 2248 | WARN_ON(1); |
| 2249 | } |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2250 | |
| 2251 | lvl_pages = lvl_to_nr_pages(largepage_lvl); |
| 2252 | |
| 2253 | BUG_ON(nr_pages < lvl_pages); |
| 2254 | BUG_ON(sg_res < lvl_pages); |
| 2255 | |
| 2256 | nr_pages -= lvl_pages; |
| 2257 | iov_pfn += lvl_pages; |
| 2258 | phys_pfn += lvl_pages; |
| 2259 | pteval += lvl_pages * VTD_PAGE_SIZE; |
| 2260 | sg_res -= lvl_pages; |
| 2261 | |
| 2262 | /* If the next PTE would be the first in a new page, then we |
| 2263 | need to flush the cache on the entries we've just written. |
| 2264 | And then we'll need to recalculate 'pte', so clear it and |
| 2265 | let it get set again in the if (!pte) block above. |
| 2266 | |
| 2267 | If we're done (!nr_pages) we need to flush the cache too. |
| 2268 | |
| 2269 | Also if we've been setting superpages, we may need to |
| 2270 | recalculate 'pte' and switch back to smaller pages for the |
| 2271 | end of the mapping, if the trailing size is not enough to |
| 2272 | use another superpage (i.e. sg_res < lvl_pages). */ |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2273 | pte++; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2274 | if (!nr_pages || first_pte_in_page(pte) || |
| 2275 | (largepage_lvl > 1 && sg_res < lvl_pages)) { |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2276 | domain_flush_cache(domain, first_pte, |
| 2277 | (void *)pte - (void *)first_pte); |
| 2278 | pte = NULL; |
| 2279 | } |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2280 | |
| 2281 | if (!sg_res && nr_pages) |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2282 | sg = sg_next(sg); |
| 2283 | } |
| 2284 | return 0; |
| 2285 | } |
| 2286 | |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 2287 | static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
| 2288 | struct scatterlist *sg, unsigned long nr_pages, |
| 2289 | int prot) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2290 | { |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 2291 | return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot); |
| 2292 | } |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 2293 | |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 2294 | static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
| 2295 | unsigned long phys_pfn, unsigned long nr_pages, |
| 2296 | int prot) |
| 2297 | { |
| 2298 | return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2299 | } |
| 2300 | |
Joerg Roedel | 2452d9d | 2015-07-23 16:20:14 +0200 | [diff] [blame] | 2301 | static void domain_context_clear_one(struct intel_iommu *iommu, u8 bus, u8 devfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2302 | { |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 2303 | if (!iommu) |
| 2304 | return; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2305 | |
| 2306 | clear_context_table(iommu, bus, devfn); |
| 2307 | iommu->flush.flush_context(iommu, 0, 0, 0, |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 2308 | DMA_CCMD_GLOBAL_INVL); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 2309 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2310 | } |
| 2311 | |
David Woodhouse | 109b9b0 | 2012-05-25 17:43:02 +0100 | [diff] [blame] | 2312 | static inline void unlink_domain_info(struct device_domain_info *info) |
| 2313 | { |
| 2314 | assert_spin_locked(&device_domain_lock); |
| 2315 | list_del(&info->link); |
| 2316 | list_del(&info->global); |
| 2317 | if (info->dev) |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 2318 | info->dev->archdata.iommu = NULL; |
David Woodhouse | 109b9b0 | 2012-05-25 17:43:02 +0100 | [diff] [blame] | 2319 | } |
| 2320 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2321 | static void domain_remove_dev_info(struct dmar_domain *domain) |
| 2322 | { |
Yijing Wang | 3a74ca0 | 2014-05-20 20:37:47 +0800 | [diff] [blame] | 2323 | struct device_domain_info *info, *tmp; |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 2324 | unsigned long flags; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2325 | |
| 2326 | spin_lock_irqsave(&device_domain_lock, flags); |
Joerg Roedel | 76f45fe | 2015-07-21 18:25:11 +0200 | [diff] [blame] | 2327 | list_for_each_entry_safe(info, tmp, &domain->devices, link) |
Joerg Roedel | 127c761 | 2015-07-23 17:44:46 +0200 | [diff] [blame] | 2328 | __dmar_remove_one_dev_info(info); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2329 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 2330 | } |
| 2331 | |
| 2332 | /* |
| 2333 | * find_domain |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame] | 2334 | * Note: we use struct device->archdata.iommu stores the info |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2335 | */ |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame] | 2336 | static struct dmar_domain *find_domain(struct device *dev) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2337 | { |
| 2338 | struct device_domain_info *info; |
| 2339 | |
| 2340 | /* No lock here, assumes no domain exit in normal case */ |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame] | 2341 | info = dev->archdata.iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2342 | if (info) |
| 2343 | return info->domain; |
| 2344 | return NULL; |
| 2345 | } |
| 2346 | |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2347 | static inline struct device_domain_info * |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2348 | dmar_search_domain_by_dev_info(int segment, int bus, int devfn) |
| 2349 | { |
| 2350 | struct device_domain_info *info; |
| 2351 | |
| 2352 | list_for_each_entry(info, &device_domain_list, global) |
David Woodhouse | 41e80dca | 2014-03-09 13:55:54 -0700 | [diff] [blame] | 2353 | if (info->iommu->segment == segment && info->bus == bus && |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2354 | info->devfn == devfn) |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2355 | return info; |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2356 | |
| 2357 | return NULL; |
| 2358 | } |
| 2359 | |
Joerg Roedel | 5db3156 | 2015-07-22 12:40:43 +0200 | [diff] [blame] | 2360 | static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu, |
| 2361 | int bus, int devfn, |
| 2362 | struct device *dev, |
| 2363 | struct dmar_domain *domain) |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2364 | { |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2365 | struct dmar_domain *found = NULL; |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2366 | struct device_domain_info *info; |
| 2367 | unsigned long flags; |
Joerg Roedel | d160aca | 2015-07-22 11:52:53 +0200 | [diff] [blame] | 2368 | int ret; |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2369 | |
| 2370 | info = alloc_devinfo_mem(); |
| 2371 | if (!info) |
David Woodhouse | b718cd3 | 2014-03-09 13:11:33 -0700 | [diff] [blame] | 2372 | return NULL; |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2373 | |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2374 | info->bus = bus; |
| 2375 | info->devfn = devfn; |
David Woodhouse | b16d0cb | 2015-10-12 14:17:37 +0100 | [diff] [blame] | 2376 | info->ats_supported = info->pasid_supported = info->pri_supported = 0; |
| 2377 | info->ats_enabled = info->pasid_enabled = info->pri_enabled = 0; |
| 2378 | info->ats_qdep = 0; |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2379 | info->dev = dev; |
| 2380 | info->domain = domain; |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2381 | info->iommu = iommu; |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2382 | |
David Woodhouse | b16d0cb | 2015-10-12 14:17:37 +0100 | [diff] [blame] | 2383 | if (dev && dev_is_pci(dev)) { |
| 2384 | struct pci_dev *pdev = to_pci_dev(info->dev); |
| 2385 | |
| 2386 | if (ecap_dev_iotlb_support(iommu->ecap) && |
| 2387 | pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS) && |
| 2388 | dmar_find_matched_atsr_unit(pdev)) |
| 2389 | info->ats_supported = 1; |
| 2390 | |
| 2391 | if (ecs_enabled(iommu)) { |
| 2392 | if (pasid_enabled(iommu)) { |
| 2393 | int features = pci_pasid_features(pdev); |
| 2394 | if (features >= 0) |
| 2395 | info->pasid_supported = features | 1; |
| 2396 | } |
| 2397 | |
| 2398 | if (info->ats_supported && ecap_prs(iommu->ecap) && |
| 2399 | pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI)) |
| 2400 | info->pri_supported = 1; |
| 2401 | } |
| 2402 | } |
| 2403 | |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2404 | spin_lock_irqsave(&device_domain_lock, flags); |
| 2405 | if (dev) |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 2406 | found = find_domain(dev); |
Joerg Roedel | f303e50 | 2015-07-23 18:37:13 +0200 | [diff] [blame] | 2407 | |
| 2408 | if (!found) { |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2409 | struct device_domain_info *info2; |
David Woodhouse | 41e80dca | 2014-03-09 13:55:54 -0700 | [diff] [blame] | 2410 | info2 = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn); |
Joerg Roedel | f303e50 | 2015-07-23 18:37:13 +0200 | [diff] [blame] | 2411 | if (info2) { |
| 2412 | found = info2->domain; |
| 2413 | info2->dev = dev; |
| 2414 | } |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2415 | } |
Joerg Roedel | f303e50 | 2015-07-23 18:37:13 +0200 | [diff] [blame] | 2416 | |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2417 | if (found) { |
| 2418 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 2419 | free_devinfo_mem(info); |
David Woodhouse | b718cd3 | 2014-03-09 13:11:33 -0700 | [diff] [blame] | 2420 | /* Caller must free the original domain */ |
| 2421 | return found; |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2422 | } |
| 2423 | |
Joerg Roedel | d160aca | 2015-07-22 11:52:53 +0200 | [diff] [blame] | 2424 | spin_lock(&iommu->lock); |
| 2425 | ret = domain_attach_iommu(domain, iommu); |
| 2426 | spin_unlock(&iommu->lock); |
| 2427 | |
| 2428 | if (ret) { |
Joerg Roedel | c6c2ceb | 2015-07-22 13:11:53 +0200 | [diff] [blame] | 2429 | spin_unlock_irqrestore(&device_domain_lock, flags); |
Sudip Mukherjee | 499f3aa | 2015-09-18 16:27:07 +0530 | [diff] [blame] | 2430 | free_devinfo_mem(info); |
Joerg Roedel | c6c2ceb | 2015-07-22 13:11:53 +0200 | [diff] [blame] | 2431 | return NULL; |
| 2432 | } |
Joerg Roedel | c6c2ceb | 2015-07-22 13:11:53 +0200 | [diff] [blame] | 2433 | |
David Woodhouse | b718cd3 | 2014-03-09 13:11:33 -0700 | [diff] [blame] | 2434 | list_add(&info->link, &domain->devices); |
| 2435 | list_add(&info->global, &device_domain_list); |
| 2436 | if (dev) |
| 2437 | dev->archdata.iommu = info; |
| 2438 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 2439 | |
Joerg Roedel | cc4e257 | 2015-07-22 10:04:36 +0200 | [diff] [blame] | 2440 | if (dev && domain_context_mapping(domain, dev)) { |
| 2441 | pr_err("Domain context map for %s failed\n", dev_name(dev)); |
Joerg Roedel | e6de0f8 | 2015-07-22 16:30:36 +0200 | [diff] [blame] | 2442 | dmar_remove_one_dev_info(domain, dev); |
Joerg Roedel | cc4e257 | 2015-07-22 10:04:36 +0200 | [diff] [blame] | 2443 | return NULL; |
| 2444 | } |
| 2445 | |
David Woodhouse | b718cd3 | 2014-03-09 13:11:33 -0700 | [diff] [blame] | 2446 | return domain; |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2447 | } |
| 2448 | |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2449 | static int get_last_alias(struct pci_dev *pdev, u16 alias, void *opaque) |
| 2450 | { |
| 2451 | *(u16 *)opaque = alias; |
| 2452 | return 0; |
| 2453 | } |
| 2454 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2455 | /* domain is initialized */ |
David Woodhouse | 146922e | 2014-03-09 15:44:17 -0700 | [diff] [blame] | 2456 | static struct dmar_domain *get_domain_for_dev(struct device *dev, int gaw) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2457 | { |
Joerg Roedel | cc4e257 | 2015-07-22 10:04:36 +0200 | [diff] [blame] | 2458 | struct device_domain_info *info = NULL; |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2459 | struct dmar_domain *domain, *tmp; |
| 2460 | struct intel_iommu *iommu; |
Joerg Roedel | 08a7f45 | 2015-07-23 18:09:11 +0200 | [diff] [blame] | 2461 | u16 req_id, dma_alias; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2462 | unsigned long flags; |
Yijing Wang | aa4d066 | 2014-05-26 20:14:06 +0800 | [diff] [blame] | 2463 | u8 bus, devfn; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2464 | |
David Woodhouse | 146922e | 2014-03-09 15:44:17 -0700 | [diff] [blame] | 2465 | domain = find_domain(dev); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2466 | if (domain) |
| 2467 | return domain; |
| 2468 | |
David Woodhouse | 146922e | 2014-03-09 15:44:17 -0700 | [diff] [blame] | 2469 | iommu = device_to_iommu(dev, &bus, &devfn); |
| 2470 | if (!iommu) |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2471 | return NULL; |
| 2472 | |
Joerg Roedel | 08a7f45 | 2015-07-23 18:09:11 +0200 | [diff] [blame] | 2473 | req_id = ((u16)bus << 8) | devfn; |
| 2474 | |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2475 | if (dev_is_pci(dev)) { |
| 2476 | struct pci_dev *pdev = to_pci_dev(dev); |
| 2477 | |
| 2478 | pci_for_each_dma_alias(pdev, get_last_alias, &dma_alias); |
| 2479 | |
| 2480 | spin_lock_irqsave(&device_domain_lock, flags); |
| 2481 | info = dmar_search_domain_by_dev_info(pci_domain_nr(pdev->bus), |
| 2482 | PCI_BUS_NUM(dma_alias), |
| 2483 | dma_alias & 0xff); |
| 2484 | if (info) { |
| 2485 | iommu = info->iommu; |
| 2486 | domain = info->domain; |
| 2487 | } |
| 2488 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 2489 | |
| 2490 | /* DMA alias already has a domain, uses it */ |
| 2491 | if (info) |
| 2492 | goto found_domain; |
| 2493 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2494 | |
David Woodhouse | 146922e | 2014-03-09 15:44:17 -0700 | [diff] [blame] | 2495 | /* Allocate and initialize new domain for the device */ |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 2496 | domain = alloc_domain(0); |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2497 | if (!domain) |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2498 | return NULL; |
Joerg Roedel | dc534b2 | 2015-07-22 12:44:02 +0200 | [diff] [blame] | 2499 | if (domain_init(domain, iommu, gaw)) { |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2500 | domain_exit(domain); |
| 2501 | return NULL; |
| 2502 | } |
| 2503 | |
| 2504 | /* register PCI DMA alias device */ |
Dan Carpenter | 0b74ecd | 2016-04-06 21:38:56 +0300 | [diff] [blame] | 2505 | if (dev_is_pci(dev) && req_id != dma_alias) { |
Joerg Roedel | 5db3156 | 2015-07-22 12:40:43 +0200 | [diff] [blame] | 2506 | tmp = dmar_insert_one_dev_info(iommu, PCI_BUS_NUM(dma_alias), |
| 2507 | dma_alias & 0xff, NULL, domain); |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2508 | |
| 2509 | if (!tmp || tmp != domain) { |
| 2510 | domain_exit(domain); |
| 2511 | domain = tmp; |
| 2512 | } |
| 2513 | |
David Woodhouse | b718cd3 | 2014-03-09 13:11:33 -0700 | [diff] [blame] | 2514 | if (!domain) |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2515 | return NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2516 | } |
| 2517 | |
| 2518 | found_domain: |
Joerg Roedel | 5db3156 | 2015-07-22 12:40:43 +0200 | [diff] [blame] | 2519 | tmp = dmar_insert_one_dev_info(iommu, bus, devfn, dev, domain); |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2520 | |
| 2521 | if (!tmp || tmp != domain) { |
| 2522 | domain_exit(domain); |
| 2523 | domain = tmp; |
| 2524 | } |
David Woodhouse | b718cd3 | 2014-03-09 13:11:33 -0700 | [diff] [blame] | 2525 | |
| 2526 | return domain; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2527 | } |
| 2528 | |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 2529 | static int iommu_domain_identity_map(struct dmar_domain *domain, |
| 2530 | unsigned long long start, |
| 2531 | unsigned long long end) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2532 | { |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 2533 | unsigned long first_vpfn = start >> VTD_PAGE_SHIFT; |
| 2534 | unsigned long last_vpfn = end >> VTD_PAGE_SHIFT; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2535 | |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 2536 | if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn), |
| 2537 | dma_to_mm_pfn(last_vpfn))) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 2538 | pr_err("Reserving iova failed\n"); |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 2539 | return -ENOMEM; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2540 | } |
| 2541 | |
Joerg Roedel | af1089c | 2015-07-21 15:45:19 +0200 | [diff] [blame] | 2542 | pr_debug("Mapping reserved region %llx-%llx\n", start, end); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2543 | /* |
| 2544 | * RMRR range might have overlap with physical memory range, |
| 2545 | * clear it first |
| 2546 | */ |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 2547 | dma_pte_clear_range(domain, first_vpfn, last_vpfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2548 | |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 2549 | return domain_pfn_mapping(domain, first_vpfn, first_vpfn, |
| 2550 | last_vpfn - first_vpfn + 1, |
David Woodhouse | 61df744 | 2009-06-28 11:55:58 +0100 | [diff] [blame] | 2551 | DMA_PTE_READ|DMA_PTE_WRITE); |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 2552 | } |
| 2553 | |
Joerg Roedel | d66ce54 | 2015-09-23 19:00:10 +0200 | [diff] [blame] | 2554 | static int domain_prepare_identity_map(struct device *dev, |
| 2555 | struct dmar_domain *domain, |
| 2556 | unsigned long long start, |
| 2557 | unsigned long long end) |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 2558 | { |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2559 | /* For _hardware_ passthrough, don't bother. But for software |
| 2560 | passthrough, we do it anyway -- it may indicate a memory |
| 2561 | range which is reserved in E820, so which didn't get set |
| 2562 | up to start with in si_domain */ |
| 2563 | if (domain == si_domain && hw_pass_through) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 2564 | pr_warn("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n", |
| 2565 | dev_name(dev), start, end); |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2566 | return 0; |
| 2567 | } |
| 2568 | |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 2569 | pr_info("Setting identity map for device %s [0x%Lx - 0x%Lx]\n", |
| 2570 | dev_name(dev), start, end); |
| 2571 | |
David Woodhouse | 5595b52 | 2009-12-02 09:21:55 +0000 | [diff] [blame] | 2572 | if (end < start) { |
| 2573 | WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n" |
| 2574 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", |
| 2575 | dmi_get_system_info(DMI_BIOS_VENDOR), |
| 2576 | dmi_get_system_info(DMI_BIOS_VERSION), |
| 2577 | dmi_get_system_info(DMI_PRODUCT_VERSION)); |
Joerg Roedel | d66ce54 | 2015-09-23 19:00:10 +0200 | [diff] [blame] | 2578 | return -EIO; |
David Woodhouse | 5595b52 | 2009-12-02 09:21:55 +0000 | [diff] [blame] | 2579 | } |
| 2580 | |
David Woodhouse | 2ff729f | 2009-08-26 14:25:41 +0100 | [diff] [blame] | 2581 | if (end >> agaw_to_width(domain->agaw)) { |
| 2582 | WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n" |
| 2583 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", |
| 2584 | agaw_to_width(domain->agaw), |
| 2585 | dmi_get_system_info(DMI_BIOS_VENDOR), |
| 2586 | dmi_get_system_info(DMI_BIOS_VERSION), |
| 2587 | dmi_get_system_info(DMI_PRODUCT_VERSION)); |
Joerg Roedel | d66ce54 | 2015-09-23 19:00:10 +0200 | [diff] [blame] | 2588 | return -EIO; |
David Woodhouse | 2ff729f | 2009-08-26 14:25:41 +0100 | [diff] [blame] | 2589 | } |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2590 | |
Joerg Roedel | d66ce54 | 2015-09-23 19:00:10 +0200 | [diff] [blame] | 2591 | return iommu_domain_identity_map(domain, start, end); |
| 2592 | } |
| 2593 | |
| 2594 | static int iommu_prepare_identity_map(struct device *dev, |
| 2595 | unsigned long long start, |
| 2596 | unsigned long long end) |
| 2597 | { |
| 2598 | struct dmar_domain *domain; |
| 2599 | int ret; |
| 2600 | |
| 2601 | domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
| 2602 | if (!domain) |
| 2603 | return -ENOMEM; |
| 2604 | |
| 2605 | ret = domain_prepare_identity_map(dev, domain, start, end); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2606 | if (ret) |
Joerg Roedel | d66ce54 | 2015-09-23 19:00:10 +0200 | [diff] [blame] | 2607 | domain_exit(domain); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2608 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2609 | return ret; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2610 | } |
| 2611 | |
| 2612 | static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr, |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2613 | struct device *dev) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2614 | { |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2615 | if (dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2616 | return 0; |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2617 | return iommu_prepare_identity_map(dev, rmrr->base_address, |
| 2618 | rmrr->end_address); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2619 | } |
| 2620 | |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 2621 | #ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2622 | static inline void iommu_prepare_isa(void) |
| 2623 | { |
| 2624 | struct pci_dev *pdev; |
| 2625 | int ret; |
| 2626 | |
| 2627 | pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); |
| 2628 | if (!pdev) |
| 2629 | return; |
| 2630 | |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 2631 | pr_info("Prepare 0-16MiB unity mapping for LPC\n"); |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2632 | ret = iommu_prepare_identity_map(&pdev->dev, 0, 16*1024*1024 - 1); |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2633 | |
| 2634 | if (ret) |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 2635 | pr_err("Failed to create 0-16MiB identity map - floppy might not work\n"); |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2636 | |
Yijing Wang | 9b27e82 | 2014-05-20 20:37:52 +0800 | [diff] [blame] | 2637 | pci_dev_put(pdev); |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2638 | } |
| 2639 | #else |
| 2640 | static inline void iommu_prepare_isa(void) |
| 2641 | { |
| 2642 | return; |
| 2643 | } |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 2644 | #endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */ |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2645 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2646 | static int md_domain_init(struct dmar_domain *domain, int guest_width); |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2647 | |
Matt Kraai | 071e137 | 2009-08-23 22:30:22 -0700 | [diff] [blame] | 2648 | static int __init si_domain_init(int hw) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2649 | { |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2650 | int nid, ret = 0; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2651 | |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 2652 | si_domain = alloc_domain(DOMAIN_FLAG_STATIC_IDENTITY); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2653 | if (!si_domain) |
| 2654 | return -EFAULT; |
| 2655 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2656 | if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
| 2657 | domain_exit(si_domain); |
| 2658 | return -EFAULT; |
| 2659 | } |
| 2660 | |
Joerg Roedel | 0dc7971 | 2015-07-21 15:40:06 +0200 | [diff] [blame] | 2661 | pr_debug("Identity mapping domain allocated\n"); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2662 | |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2663 | if (hw) |
| 2664 | return 0; |
| 2665 | |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2666 | for_each_online_node(nid) { |
Tejun Heo | d4bbf7e | 2011-11-28 09:46:22 -0800 | [diff] [blame] | 2667 | unsigned long start_pfn, end_pfn; |
| 2668 | int i; |
| 2669 | |
| 2670 | for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) { |
| 2671 | ret = iommu_domain_identity_map(si_domain, |
| 2672 | PFN_PHYS(start_pfn), PFN_PHYS(end_pfn)); |
| 2673 | if (ret) |
| 2674 | return ret; |
| 2675 | } |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2676 | } |
| 2677 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2678 | return 0; |
| 2679 | } |
| 2680 | |
David Woodhouse | 9b22662 | 2014-03-09 14:03:28 -0700 | [diff] [blame] | 2681 | static int identity_mapping(struct device *dev) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2682 | { |
| 2683 | struct device_domain_info *info; |
| 2684 | |
| 2685 | if (likely(!iommu_identity_mapping)) |
| 2686 | return 0; |
| 2687 | |
David Woodhouse | 9b22662 | 2014-03-09 14:03:28 -0700 | [diff] [blame] | 2688 | info = dev->archdata.iommu; |
Mike Travis | cb452a4 | 2011-05-28 13:15:03 -0500 | [diff] [blame] | 2689 | if (info && info != DUMMY_DEVICE_DOMAIN_INFO) |
| 2690 | return (info->domain == si_domain); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2691 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2692 | return 0; |
| 2693 | } |
| 2694 | |
Joerg Roedel | 28ccce0 | 2015-07-21 14:45:31 +0200 | [diff] [blame] | 2695 | static int domain_add_dev_info(struct dmar_domain *domain, struct device *dev) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2696 | { |
David Woodhouse | 0ac7266 | 2014-03-09 13:19:22 -0700 | [diff] [blame] | 2697 | struct dmar_domain *ndomain; |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2698 | struct intel_iommu *iommu; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 2699 | u8 bus, devfn; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2700 | |
David Woodhouse | 5913c9b | 2014-03-09 16:27:31 -0700 | [diff] [blame] | 2701 | iommu = device_to_iommu(dev, &bus, &devfn); |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2702 | if (!iommu) |
| 2703 | return -ENODEV; |
| 2704 | |
Joerg Roedel | 5db3156 | 2015-07-22 12:40:43 +0200 | [diff] [blame] | 2705 | ndomain = dmar_insert_one_dev_info(iommu, bus, devfn, dev, domain); |
David Woodhouse | 0ac7266 | 2014-03-09 13:19:22 -0700 | [diff] [blame] | 2706 | if (ndomain != domain) |
| 2707 | return -EBUSY; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2708 | |
| 2709 | return 0; |
| 2710 | } |
| 2711 | |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2712 | static bool device_has_rmrr(struct device *dev) |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2713 | { |
| 2714 | struct dmar_rmrr_unit *rmrr; |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 2715 | struct device *tmp; |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2716 | int i; |
| 2717 | |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 2718 | rcu_read_lock(); |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2719 | for_each_rmrr_units(rmrr) { |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 2720 | /* |
| 2721 | * Return TRUE if this RMRR contains the device that |
| 2722 | * is passed in. |
| 2723 | */ |
| 2724 | for_each_active_dev_scope(rmrr->devices, |
| 2725 | rmrr->devices_cnt, i, tmp) |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2726 | if (tmp == dev) { |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 2727 | rcu_read_unlock(); |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2728 | return true; |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 2729 | } |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2730 | } |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 2731 | rcu_read_unlock(); |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2732 | return false; |
| 2733 | } |
| 2734 | |
Alex Williamson | c875d2c | 2014-07-03 09:57:02 -0600 | [diff] [blame] | 2735 | /* |
| 2736 | * There are a couple cases where we need to restrict the functionality of |
| 2737 | * devices associated with RMRRs. The first is when evaluating a device for |
| 2738 | * identity mapping because problems exist when devices are moved in and out |
| 2739 | * of domains and their respective RMRR information is lost. This means that |
| 2740 | * a device with associated RMRRs will never be in a "passthrough" domain. |
| 2741 | * The second is use of the device through the IOMMU API. This interface |
| 2742 | * expects to have full control of the IOVA space for the device. We cannot |
| 2743 | * satisfy both the requirement that RMRR access is maintained and have an |
| 2744 | * unencumbered IOVA space. We also have no ability to quiesce the device's |
| 2745 | * use of the RMRR space or even inform the IOMMU API user of the restriction. |
| 2746 | * We therefore prevent devices associated with an RMRR from participating in |
| 2747 | * the IOMMU API, which eliminates them from device assignment. |
| 2748 | * |
| 2749 | * In both cases we assume that PCI USB devices with RMRRs have them largely |
| 2750 | * for historical reasons and that the RMRR space is not actively used post |
| 2751 | * boot. This exclusion may change if vendors begin to abuse it. |
David Woodhouse | 18436af | 2015-03-25 15:05:47 +0000 | [diff] [blame] | 2752 | * |
| 2753 | * The same exception is made for graphics devices, with the requirement that |
| 2754 | * any use of the RMRR regions will be torn down before assigning the device |
| 2755 | * to a guest. |
Alex Williamson | c875d2c | 2014-07-03 09:57:02 -0600 | [diff] [blame] | 2756 | */ |
| 2757 | static bool device_is_rmrr_locked(struct device *dev) |
| 2758 | { |
| 2759 | if (!device_has_rmrr(dev)) |
| 2760 | return false; |
| 2761 | |
| 2762 | if (dev_is_pci(dev)) { |
| 2763 | struct pci_dev *pdev = to_pci_dev(dev); |
| 2764 | |
David Woodhouse | 18436af | 2015-03-25 15:05:47 +0000 | [diff] [blame] | 2765 | if (IS_USB_DEVICE(pdev) || IS_GFX_DEVICE(pdev)) |
Alex Williamson | c875d2c | 2014-07-03 09:57:02 -0600 | [diff] [blame] | 2766 | return false; |
| 2767 | } |
| 2768 | |
| 2769 | return true; |
| 2770 | } |
| 2771 | |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2772 | static int iommu_should_identity_map(struct device *dev, int startup) |
David Woodhouse | 6941af2 | 2009-07-04 18:24:27 +0100 | [diff] [blame] | 2773 | { |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2774 | |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2775 | if (dev_is_pci(dev)) { |
| 2776 | struct pci_dev *pdev = to_pci_dev(dev); |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2777 | |
Alex Williamson | c875d2c | 2014-07-03 09:57:02 -0600 | [diff] [blame] | 2778 | if (device_is_rmrr_locked(dev)) |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2779 | return 0; |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 2780 | |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2781 | if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev)) |
| 2782 | return 1; |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 2783 | |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2784 | if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev)) |
| 2785 | return 1; |
| 2786 | |
| 2787 | if (!(iommu_identity_mapping & IDENTMAP_ALL)) |
| 2788 | return 0; |
| 2789 | |
| 2790 | /* |
| 2791 | * We want to start off with all devices in the 1:1 domain, and |
| 2792 | * take them out later if we find they can't access all of memory. |
| 2793 | * |
| 2794 | * However, we can't do this for PCI devices behind bridges, |
| 2795 | * because all PCI devices behind the same bridge will end up |
| 2796 | * with the same source-id on their transactions. |
| 2797 | * |
| 2798 | * Practically speaking, we can't change things around for these |
| 2799 | * devices at run-time, because we can't be sure there'll be no |
| 2800 | * DMA transactions in flight for any of their siblings. |
| 2801 | * |
| 2802 | * So PCI devices (unless they're on the root bus) as well as |
| 2803 | * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of |
| 2804 | * the 1:1 domain, just in _case_ one of their siblings turns out |
| 2805 | * not to be able to map all of memory. |
| 2806 | */ |
| 2807 | if (!pci_is_pcie(pdev)) { |
| 2808 | if (!pci_is_root_bus(pdev->bus)) |
| 2809 | return 0; |
| 2810 | if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI) |
| 2811 | return 0; |
| 2812 | } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE) |
| 2813 | return 0; |
| 2814 | } else { |
| 2815 | if (device_has_rmrr(dev)) |
| 2816 | return 0; |
| 2817 | } |
David Woodhouse | 6941af2 | 2009-07-04 18:24:27 +0100 | [diff] [blame] | 2818 | |
David Woodhouse | 3dfc813 | 2009-07-04 19:11:08 +0100 | [diff] [blame] | 2819 | /* |
David Woodhouse | 3dfc813 | 2009-07-04 19:11:08 +0100 | [diff] [blame] | 2820 | * At boot time, we don't yet know if devices will be 64-bit capable. |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2821 | * Assume that they will — if they turn out not to be, then we can |
David Woodhouse | 3dfc813 | 2009-07-04 19:11:08 +0100 | [diff] [blame] | 2822 | * take them out of the 1:1 domain later. |
| 2823 | */ |
Chris Wright | 8fcc537 | 2011-05-28 13:15:02 -0500 | [diff] [blame] | 2824 | if (!startup) { |
| 2825 | /* |
| 2826 | * If the device's dma_mask is less than the system's memory |
| 2827 | * size then this is not a candidate for identity mapping. |
| 2828 | */ |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2829 | u64 dma_mask = *dev->dma_mask; |
Chris Wright | 8fcc537 | 2011-05-28 13:15:02 -0500 | [diff] [blame] | 2830 | |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2831 | if (dev->coherent_dma_mask && |
| 2832 | dev->coherent_dma_mask < dma_mask) |
| 2833 | dma_mask = dev->coherent_dma_mask; |
Chris Wright | 8fcc537 | 2011-05-28 13:15:02 -0500 | [diff] [blame] | 2834 | |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2835 | return dma_mask >= dma_get_required_mask(dev); |
Chris Wright | 8fcc537 | 2011-05-28 13:15:02 -0500 | [diff] [blame] | 2836 | } |
David Woodhouse | 6941af2 | 2009-07-04 18:24:27 +0100 | [diff] [blame] | 2837 | |
| 2838 | return 1; |
| 2839 | } |
| 2840 | |
David Woodhouse | cf04eee | 2014-03-21 16:49:04 +0000 | [diff] [blame] | 2841 | static int __init dev_prepare_static_identity_mapping(struct device *dev, int hw) |
| 2842 | { |
| 2843 | int ret; |
| 2844 | |
| 2845 | if (!iommu_should_identity_map(dev, 1)) |
| 2846 | return 0; |
| 2847 | |
Joerg Roedel | 28ccce0 | 2015-07-21 14:45:31 +0200 | [diff] [blame] | 2848 | ret = domain_add_dev_info(si_domain, dev); |
David Woodhouse | cf04eee | 2014-03-21 16:49:04 +0000 | [diff] [blame] | 2849 | if (!ret) |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 2850 | pr_info("%s identity mapping for device %s\n", |
| 2851 | hw ? "Hardware" : "Software", dev_name(dev)); |
David Woodhouse | cf04eee | 2014-03-21 16:49:04 +0000 | [diff] [blame] | 2852 | else if (ret == -ENODEV) |
| 2853 | /* device not associated with an iommu */ |
| 2854 | ret = 0; |
| 2855 | |
| 2856 | return ret; |
| 2857 | } |
| 2858 | |
| 2859 | |
Matt Kraai | 071e137 | 2009-08-23 22:30:22 -0700 | [diff] [blame] | 2860 | static int __init iommu_prepare_static_identity_mapping(int hw) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2861 | { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2862 | struct pci_dev *pdev = NULL; |
David Woodhouse | cf04eee | 2014-03-21 16:49:04 +0000 | [diff] [blame] | 2863 | struct dmar_drhd_unit *drhd; |
| 2864 | struct intel_iommu *iommu; |
| 2865 | struct device *dev; |
| 2866 | int i; |
| 2867 | int ret = 0; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2868 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2869 | for_each_pci_dev(pdev) { |
David Woodhouse | cf04eee | 2014-03-21 16:49:04 +0000 | [diff] [blame] | 2870 | ret = dev_prepare_static_identity_mapping(&pdev->dev, hw); |
| 2871 | if (ret) |
| 2872 | return ret; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2873 | } |
| 2874 | |
David Woodhouse | cf04eee | 2014-03-21 16:49:04 +0000 | [diff] [blame] | 2875 | for_each_active_iommu(iommu, drhd) |
| 2876 | for_each_active_dev_scope(drhd->devices, drhd->devices_cnt, i, dev) { |
| 2877 | struct acpi_device_physical_node *pn; |
| 2878 | struct acpi_device *adev; |
| 2879 | |
| 2880 | if (dev->bus != &acpi_bus_type) |
| 2881 | continue; |
Joerg Roedel | 86080cc | 2015-06-12 12:27:16 +0200 | [diff] [blame] | 2882 | |
David Woodhouse | cf04eee | 2014-03-21 16:49:04 +0000 | [diff] [blame] | 2883 | adev= to_acpi_device(dev); |
| 2884 | mutex_lock(&adev->physical_node_lock); |
| 2885 | list_for_each_entry(pn, &adev->physical_node_list, node) { |
| 2886 | ret = dev_prepare_static_identity_mapping(pn->dev, hw); |
| 2887 | if (ret) |
| 2888 | break; |
| 2889 | } |
| 2890 | mutex_unlock(&adev->physical_node_lock); |
| 2891 | if (ret) |
| 2892 | return ret; |
| 2893 | } |
| 2894 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2895 | return 0; |
| 2896 | } |
| 2897 | |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 2898 | static void intel_iommu_init_qi(struct intel_iommu *iommu) |
| 2899 | { |
| 2900 | /* |
| 2901 | * Start from the sane iommu hardware state. |
| 2902 | * If the queued invalidation is already initialized by us |
| 2903 | * (for example, while enabling interrupt-remapping) then |
| 2904 | * we got the things already rolling from a sane state. |
| 2905 | */ |
| 2906 | if (!iommu->qi) { |
| 2907 | /* |
| 2908 | * Clear any previous faults. |
| 2909 | */ |
| 2910 | dmar_fault(-1, iommu); |
| 2911 | /* |
| 2912 | * Disable queued invalidation if supported and already enabled |
| 2913 | * before OS handover. |
| 2914 | */ |
| 2915 | dmar_disable_qi(iommu); |
| 2916 | } |
| 2917 | |
| 2918 | if (dmar_enable_qi(iommu)) { |
| 2919 | /* |
| 2920 | * Queued Invalidate not enabled, use Register Based Invalidate |
| 2921 | */ |
| 2922 | iommu->flush.flush_context = __iommu_flush_context; |
| 2923 | iommu->flush.flush_iotlb = __iommu_flush_iotlb; |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 2924 | pr_info("%s: Using Register based invalidation\n", |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 2925 | iommu->name); |
| 2926 | } else { |
| 2927 | iommu->flush.flush_context = qi_flush_context; |
| 2928 | iommu->flush.flush_iotlb = qi_flush_iotlb; |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 2929 | pr_info("%s: Using Queued invalidation\n", iommu->name); |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 2930 | } |
| 2931 | } |
| 2932 | |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 2933 | static int copy_context_table(struct intel_iommu *iommu, |
Dan Williams | dfddb96 | 2015-10-09 18:16:46 -0400 | [diff] [blame] | 2934 | struct root_entry *old_re, |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 2935 | struct context_entry **tbl, |
| 2936 | int bus, bool ext) |
| 2937 | { |
Joerg Roedel | dbcd861 | 2015-06-12 12:02:09 +0200 | [diff] [blame] | 2938 | int tbl_idx, pos = 0, idx, devfn, ret = 0, did; |
Joerg Roedel | 543c8dc | 2015-08-13 11:56:59 +0200 | [diff] [blame] | 2939 | struct context_entry *new_ce = NULL, ce; |
Dan Williams | dfddb96 | 2015-10-09 18:16:46 -0400 | [diff] [blame] | 2940 | struct context_entry *old_ce = NULL; |
Joerg Roedel | 543c8dc | 2015-08-13 11:56:59 +0200 | [diff] [blame] | 2941 | struct root_entry re; |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 2942 | phys_addr_t old_ce_phys; |
| 2943 | |
| 2944 | tbl_idx = ext ? bus * 2 : bus; |
Dan Williams | dfddb96 | 2015-10-09 18:16:46 -0400 | [diff] [blame] | 2945 | memcpy(&re, old_re, sizeof(re)); |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 2946 | |
| 2947 | for (devfn = 0; devfn < 256; devfn++) { |
| 2948 | /* First calculate the correct index */ |
| 2949 | idx = (ext ? devfn * 2 : devfn) % 256; |
| 2950 | |
| 2951 | if (idx == 0) { |
| 2952 | /* First save what we may have and clean up */ |
| 2953 | if (new_ce) { |
| 2954 | tbl[tbl_idx] = new_ce; |
| 2955 | __iommu_flush_cache(iommu, new_ce, |
| 2956 | VTD_PAGE_SIZE); |
| 2957 | pos = 1; |
| 2958 | } |
| 2959 | |
| 2960 | if (old_ce) |
| 2961 | iounmap(old_ce); |
| 2962 | |
| 2963 | ret = 0; |
| 2964 | if (devfn < 0x80) |
Joerg Roedel | 543c8dc | 2015-08-13 11:56:59 +0200 | [diff] [blame] | 2965 | old_ce_phys = root_entry_lctp(&re); |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 2966 | else |
Joerg Roedel | 543c8dc | 2015-08-13 11:56:59 +0200 | [diff] [blame] | 2967 | old_ce_phys = root_entry_uctp(&re); |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 2968 | |
| 2969 | if (!old_ce_phys) { |
| 2970 | if (ext && devfn == 0) { |
| 2971 | /* No LCTP, try UCTP */ |
| 2972 | devfn = 0x7f; |
| 2973 | continue; |
| 2974 | } else { |
| 2975 | goto out; |
| 2976 | } |
| 2977 | } |
| 2978 | |
| 2979 | ret = -ENOMEM; |
Dan Williams | dfddb96 | 2015-10-09 18:16:46 -0400 | [diff] [blame] | 2980 | old_ce = memremap(old_ce_phys, PAGE_SIZE, |
| 2981 | MEMREMAP_WB); |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 2982 | if (!old_ce) |
| 2983 | goto out; |
| 2984 | |
| 2985 | new_ce = alloc_pgtable_page(iommu->node); |
| 2986 | if (!new_ce) |
| 2987 | goto out_unmap; |
| 2988 | |
| 2989 | ret = 0; |
| 2990 | } |
| 2991 | |
| 2992 | /* Now copy the context entry */ |
Dan Williams | dfddb96 | 2015-10-09 18:16:46 -0400 | [diff] [blame] | 2993 | memcpy(&ce, old_ce + idx, sizeof(ce)); |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 2994 | |
Joerg Roedel | cf484d0 | 2015-06-12 12:21:46 +0200 | [diff] [blame] | 2995 | if (!__context_present(&ce)) |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 2996 | continue; |
| 2997 | |
Joerg Roedel | dbcd861 | 2015-06-12 12:02:09 +0200 | [diff] [blame] | 2998 | did = context_domain_id(&ce); |
| 2999 | if (did >= 0 && did < cap_ndoms(iommu->cap)) |
| 3000 | set_bit(did, iommu->domain_ids); |
| 3001 | |
Joerg Roedel | cf484d0 | 2015-06-12 12:21:46 +0200 | [diff] [blame] | 3002 | /* |
| 3003 | * We need a marker for copied context entries. This |
| 3004 | * marker needs to work for the old format as well as |
| 3005 | * for extended context entries. |
| 3006 | * |
| 3007 | * Bit 67 of the context entry is used. In the old |
| 3008 | * format this bit is available to software, in the |
| 3009 | * extended format it is the PGE bit, but PGE is ignored |
| 3010 | * by HW if PASIDs are disabled (and thus still |
| 3011 | * available). |
| 3012 | * |
| 3013 | * So disable PASIDs first and then mark the entry |
| 3014 | * copied. This means that we don't copy PASID |
| 3015 | * translations from the old kernel, but this is fine as |
| 3016 | * faults there are not fatal. |
| 3017 | */ |
| 3018 | context_clear_pasid_enable(&ce); |
| 3019 | context_set_copied(&ce); |
| 3020 | |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 3021 | new_ce[idx] = ce; |
| 3022 | } |
| 3023 | |
| 3024 | tbl[tbl_idx + pos] = new_ce; |
| 3025 | |
| 3026 | __iommu_flush_cache(iommu, new_ce, VTD_PAGE_SIZE); |
| 3027 | |
| 3028 | out_unmap: |
Dan Williams | dfddb96 | 2015-10-09 18:16:46 -0400 | [diff] [blame] | 3029 | memunmap(old_ce); |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 3030 | |
| 3031 | out: |
| 3032 | return ret; |
| 3033 | } |
| 3034 | |
| 3035 | static int copy_translation_tables(struct intel_iommu *iommu) |
| 3036 | { |
| 3037 | struct context_entry **ctxt_tbls; |
Dan Williams | dfddb96 | 2015-10-09 18:16:46 -0400 | [diff] [blame] | 3038 | struct root_entry *old_rt; |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 3039 | phys_addr_t old_rt_phys; |
| 3040 | int ctxt_table_entries; |
| 3041 | unsigned long flags; |
| 3042 | u64 rtaddr_reg; |
| 3043 | int bus, ret; |
Joerg Roedel | c3361f2 | 2015-06-12 12:39:25 +0200 | [diff] [blame] | 3044 | bool new_ext, ext; |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 3045 | |
| 3046 | rtaddr_reg = dmar_readq(iommu->reg + DMAR_RTADDR_REG); |
| 3047 | ext = !!(rtaddr_reg & DMA_RTADDR_RTT); |
Joerg Roedel | c3361f2 | 2015-06-12 12:39:25 +0200 | [diff] [blame] | 3048 | new_ext = !!ecap_ecs(iommu->ecap); |
| 3049 | |
| 3050 | /* |
| 3051 | * The RTT bit can only be changed when translation is disabled, |
| 3052 | * but disabling translation means to open a window for data |
| 3053 | * corruption. So bail out and don't copy anything if we would |
| 3054 | * have to change the bit. |
| 3055 | */ |
| 3056 | if (new_ext != ext) |
| 3057 | return -EINVAL; |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 3058 | |
| 3059 | old_rt_phys = rtaddr_reg & VTD_PAGE_MASK; |
| 3060 | if (!old_rt_phys) |
| 3061 | return -EINVAL; |
| 3062 | |
Dan Williams | dfddb96 | 2015-10-09 18:16:46 -0400 | [diff] [blame] | 3063 | old_rt = memremap(old_rt_phys, PAGE_SIZE, MEMREMAP_WB); |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 3064 | if (!old_rt) |
| 3065 | return -ENOMEM; |
| 3066 | |
| 3067 | /* This is too big for the stack - allocate it from slab */ |
| 3068 | ctxt_table_entries = ext ? 512 : 256; |
| 3069 | ret = -ENOMEM; |
| 3070 | ctxt_tbls = kzalloc(ctxt_table_entries * sizeof(void *), GFP_KERNEL); |
| 3071 | if (!ctxt_tbls) |
| 3072 | goto out_unmap; |
| 3073 | |
| 3074 | for (bus = 0; bus < 256; bus++) { |
| 3075 | ret = copy_context_table(iommu, &old_rt[bus], |
| 3076 | ctxt_tbls, bus, ext); |
| 3077 | if (ret) { |
| 3078 | pr_err("%s: Failed to copy context table for bus %d\n", |
| 3079 | iommu->name, bus); |
| 3080 | continue; |
| 3081 | } |
| 3082 | } |
| 3083 | |
| 3084 | spin_lock_irqsave(&iommu->lock, flags); |
| 3085 | |
| 3086 | /* Context tables are copied, now write them to the root_entry table */ |
| 3087 | for (bus = 0; bus < 256; bus++) { |
| 3088 | int idx = ext ? bus * 2 : bus; |
| 3089 | u64 val; |
| 3090 | |
| 3091 | if (ctxt_tbls[idx]) { |
| 3092 | val = virt_to_phys(ctxt_tbls[idx]) | 1; |
| 3093 | iommu->root_entry[bus].lo = val; |
| 3094 | } |
| 3095 | |
| 3096 | if (!ext || !ctxt_tbls[idx + 1]) |
| 3097 | continue; |
| 3098 | |
| 3099 | val = virt_to_phys(ctxt_tbls[idx + 1]) | 1; |
| 3100 | iommu->root_entry[bus].hi = val; |
| 3101 | } |
| 3102 | |
| 3103 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 3104 | |
| 3105 | kfree(ctxt_tbls); |
| 3106 | |
| 3107 | __iommu_flush_cache(iommu, iommu->root_entry, PAGE_SIZE); |
| 3108 | |
| 3109 | ret = 0; |
| 3110 | |
| 3111 | out_unmap: |
Dan Williams | dfddb96 | 2015-10-09 18:16:46 -0400 | [diff] [blame] | 3112 | memunmap(old_rt); |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 3113 | |
| 3114 | return ret; |
| 3115 | } |
| 3116 | |
Joseph Cihula | b779260 | 2011-05-03 00:08:37 -0700 | [diff] [blame] | 3117 | static int __init init_dmars(void) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3118 | { |
| 3119 | struct dmar_drhd_unit *drhd; |
| 3120 | struct dmar_rmrr_unit *rmrr; |
Joerg Roedel | a87f491 | 2015-06-12 12:32:54 +0200 | [diff] [blame] | 3121 | bool copied_tables = false; |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 3122 | struct device *dev; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3123 | struct intel_iommu *iommu; |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3124 | int i, ret, cpu; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3125 | |
| 3126 | /* |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3127 | * for each drhd |
| 3128 | * allocate root |
| 3129 | * initialize and program root entry to not present |
| 3130 | * endfor |
| 3131 | */ |
| 3132 | for_each_drhd_unit(drhd) { |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3133 | /* |
| 3134 | * lock not needed as this is only incremented in the single |
| 3135 | * threaded kernel __init code path all other access are read |
| 3136 | * only |
| 3137 | */ |
Jiang Liu | 78d8e70 | 2014-11-09 22:47:57 +0800 | [diff] [blame] | 3138 | if (g_num_of_iommus < DMAR_UNITS_SUPPORTED) { |
Mike Travis | 1b198bb | 2012-03-05 15:05:16 -0800 | [diff] [blame] | 3139 | g_num_of_iommus++; |
| 3140 | continue; |
| 3141 | } |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 3142 | pr_err_once("Exceeded %d IOMMUs\n", DMAR_UNITS_SUPPORTED); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3143 | } |
| 3144 | |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 3145 | /* Preallocate enough resources for IOMMU hot-addition */ |
| 3146 | if (g_num_of_iommus < DMAR_UNITS_SUPPORTED) |
| 3147 | g_num_of_iommus = DMAR_UNITS_SUPPORTED; |
| 3148 | |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 3149 | g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *), |
| 3150 | GFP_KERNEL); |
| 3151 | if (!g_iommus) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 3152 | pr_err("Allocating global iommu array failed\n"); |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 3153 | ret = -ENOMEM; |
| 3154 | goto error; |
| 3155 | } |
| 3156 | |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3157 | for_each_possible_cpu(cpu) { |
| 3158 | struct deferred_flush_data *dfd = per_cpu_ptr(&deferred_flush, |
| 3159 | cpu); |
| 3160 | |
| 3161 | dfd->tables = kzalloc(g_num_of_iommus * |
| 3162 | sizeof(struct deferred_flush_table), |
| 3163 | GFP_KERNEL); |
| 3164 | if (!dfd->tables) { |
| 3165 | ret = -ENOMEM; |
| 3166 | goto free_g_iommus; |
| 3167 | } |
| 3168 | |
| 3169 | spin_lock_init(&dfd->lock); |
| 3170 | setup_timer(&dfd->timer, flush_unmaps_timeout, cpu); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3171 | } |
| 3172 | |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 3173 | for_each_active_iommu(iommu, drhd) { |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 3174 | g_iommus[iommu->seq_id] = iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3175 | |
Joerg Roedel | b63d80d | 2015-06-12 09:14:34 +0200 | [diff] [blame] | 3176 | intel_iommu_init_qi(iommu); |
| 3177 | |
Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 3178 | ret = iommu_init_domains(iommu); |
| 3179 | if (ret) |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 3180 | goto free_iommu; |
Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 3181 | |
Joerg Roedel | 4158c2e | 2015-06-12 10:14:02 +0200 | [diff] [blame] | 3182 | init_translation_status(iommu); |
| 3183 | |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 3184 | if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { |
| 3185 | iommu_disable_translation(iommu); |
| 3186 | clear_translation_pre_enabled(iommu); |
| 3187 | pr_warn("Translation was enabled for %s but we are not in kdump mode\n", |
| 3188 | iommu->name); |
| 3189 | } |
Joerg Roedel | 4158c2e | 2015-06-12 10:14:02 +0200 | [diff] [blame] | 3190 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3191 | /* |
| 3192 | * TBD: |
| 3193 | * we could share the same root & context tables |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 3194 | * among all IOMMU's. Need to Split it later. |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3195 | */ |
| 3196 | ret = iommu_alloc_root_entry(iommu); |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 3197 | if (ret) |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 3198 | goto free_iommu; |
Joerg Roedel | 5f0a7f7 | 2015-06-12 09:18:53 +0200 | [diff] [blame] | 3199 | |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 3200 | if (translation_pre_enabled(iommu)) { |
| 3201 | pr_info("Translation already enabled - trying to copy translation structures\n"); |
| 3202 | |
| 3203 | ret = copy_translation_tables(iommu); |
| 3204 | if (ret) { |
| 3205 | /* |
| 3206 | * We found the IOMMU with translation |
| 3207 | * enabled - but failed to copy over the |
| 3208 | * old root-entry table. Try to proceed |
| 3209 | * by disabling translation now and |
| 3210 | * allocating a clean root-entry table. |
| 3211 | * This might cause DMAR faults, but |
| 3212 | * probably the dump will still succeed. |
| 3213 | */ |
| 3214 | pr_err("Failed to copy translation tables from previous kernel for %s\n", |
| 3215 | iommu->name); |
| 3216 | iommu_disable_translation(iommu); |
| 3217 | clear_translation_pre_enabled(iommu); |
| 3218 | } else { |
| 3219 | pr_info("Copied translation tables from previous kernel for %s\n", |
| 3220 | iommu->name); |
Joerg Roedel | a87f491 | 2015-06-12 12:32:54 +0200 | [diff] [blame] | 3221 | copied_tables = true; |
Joerg Roedel | 091d42e | 2015-06-12 11:56:10 +0200 | [diff] [blame] | 3222 | } |
| 3223 | } |
| 3224 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 3225 | if (!ecap_pass_through(iommu->ecap)) |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 3226 | hw_pass_through = 0; |
David Woodhouse | 8a94ade | 2015-03-24 14:54:56 +0000 | [diff] [blame] | 3227 | #ifdef CONFIG_INTEL_IOMMU_SVM |
| 3228 | if (pasid_enabled(iommu)) |
| 3229 | intel_svm_alloc_pasid_tables(iommu); |
| 3230 | #endif |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3231 | } |
| 3232 | |
Joerg Roedel | a4c34ff | 2016-06-17 11:29:48 +0200 | [diff] [blame] | 3233 | /* |
| 3234 | * Now that qi is enabled on all iommus, set the root entry and flush |
| 3235 | * caches. This is required on some Intel X58 chipsets, otherwise the |
| 3236 | * flush_context function will loop forever and the boot hangs. |
| 3237 | */ |
| 3238 | for_each_active_iommu(iommu, drhd) { |
| 3239 | iommu_flush_write_buffer(iommu); |
| 3240 | iommu_set_root_entry(iommu); |
| 3241 | iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); |
| 3242 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
| 3243 | } |
| 3244 | |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 3245 | if (iommu_pass_through) |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 3246 | iommu_identity_mapping |= IDENTMAP_ALL; |
| 3247 | |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 3248 | #ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 3249 | iommu_identity_mapping |= IDENTMAP_GFX; |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 3250 | #endif |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 3251 | |
Joerg Roedel | 86080cc | 2015-06-12 12:27:16 +0200 | [diff] [blame] | 3252 | if (iommu_identity_mapping) { |
| 3253 | ret = si_domain_init(hw_pass_through); |
| 3254 | if (ret) |
| 3255 | goto free_iommu; |
| 3256 | } |
| 3257 | |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 3258 | check_tylersburg_isoch(); |
| 3259 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 3260 | /* |
Joerg Roedel | a87f491 | 2015-06-12 12:32:54 +0200 | [diff] [blame] | 3261 | * If we copied translations from a previous kernel in the kdump |
| 3262 | * case, we can not assign the devices to domains now, as that |
| 3263 | * would eliminate the old mappings. So skip this part and defer |
| 3264 | * the assignment to device driver initialization time. |
| 3265 | */ |
| 3266 | if (copied_tables) |
| 3267 | goto domains_done; |
| 3268 | |
| 3269 | /* |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 3270 | * If pass through is not set or not enabled, setup context entries for |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3271 | * identity mappings for rmrr, gfx, and isa and may fall back to static |
| 3272 | * identity mapping if iommu_identity_mapping is set. |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 3273 | */ |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 3274 | if (iommu_identity_mapping) { |
| 3275 | ret = iommu_prepare_static_identity_mapping(hw_pass_through); |
| 3276 | if (ret) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 3277 | pr_crit("Failed to setup IOMMU pass-through\n"); |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 3278 | goto free_iommu; |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 3279 | } |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 3280 | } |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 3281 | /* |
| 3282 | * For each rmrr |
| 3283 | * for each dev attached to rmrr |
| 3284 | * do |
| 3285 | * locate drhd for dev, alloc domain for dev |
| 3286 | * allocate free domain |
| 3287 | * allocate page table entries for rmrr |
| 3288 | * if context not allocated for bus |
| 3289 | * allocate and init context |
| 3290 | * set present in root table for this bus |
| 3291 | * init context with domain, translation etc |
| 3292 | * endfor |
| 3293 | * endfor |
| 3294 | */ |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 3295 | pr_info("Setting RMRR:\n"); |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 3296 | for_each_rmrr_units(rmrr) { |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3297 | /* some BIOS lists non-exist devices in DMAR table. */ |
| 3298 | for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt, |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 3299 | i, dev) { |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 3300 | ret = iommu_prepare_rmrr_dev(rmrr, dev); |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 3301 | if (ret) |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 3302 | pr_err("Mapping reserved region failed\n"); |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 3303 | } |
| 3304 | } |
| 3305 | |
| 3306 | iommu_prepare_isa(); |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 3307 | |
Joerg Roedel | a87f491 | 2015-06-12 12:32:54 +0200 | [diff] [blame] | 3308 | domains_done: |
| 3309 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3310 | /* |
| 3311 | * for each drhd |
| 3312 | * enable fault log |
| 3313 | * global invalidate context cache |
| 3314 | * global invalidate iotlb |
| 3315 | * enable translation |
| 3316 | */ |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 3317 | for_each_iommu(iommu, drhd) { |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 3318 | if (drhd->ignored) { |
| 3319 | /* |
| 3320 | * we always have to disable PMRs or DMA may fail on |
| 3321 | * this device |
| 3322 | */ |
| 3323 | if (force_on) |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 3324 | iommu_disable_protect_mem_regions(iommu); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3325 | continue; |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 3326 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3327 | |
| 3328 | iommu_flush_write_buffer(iommu); |
| 3329 | |
David Woodhouse | a222a7f | 2015-10-07 23:35:18 +0100 | [diff] [blame] | 3330 | #ifdef CONFIG_INTEL_IOMMU_SVM |
| 3331 | if (pasid_enabled(iommu) && ecap_prs(iommu->ecap)) { |
| 3332 | ret = intel_svm_enable_prq(iommu); |
| 3333 | if (ret) |
| 3334 | goto free_iommu; |
| 3335 | } |
| 3336 | #endif |
Keshavamurthy, Anil S | 3460a6d | 2007-10-21 16:41:54 -0700 | [diff] [blame] | 3337 | ret = dmar_set_interrupt(iommu); |
| 3338 | if (ret) |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 3339 | goto free_iommu; |
Keshavamurthy, Anil S | 3460a6d | 2007-10-21 16:41:54 -0700 | [diff] [blame] | 3340 | |
Joerg Roedel | 8939ddf | 2015-06-12 14:40:01 +0200 | [diff] [blame] | 3341 | if (!translation_pre_enabled(iommu)) |
| 3342 | iommu_enable_translation(iommu); |
| 3343 | |
David Woodhouse | b94996c | 2009-09-19 15:28:12 -0700 | [diff] [blame] | 3344 | iommu_disable_protect_mem_regions(iommu); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3345 | } |
| 3346 | |
| 3347 | return 0; |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 3348 | |
| 3349 | free_iommu: |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 3350 | for_each_active_iommu(iommu, drhd) { |
| 3351 | disable_dmar_iommu(iommu); |
Jiang Liu | a868e6b | 2014-01-06 14:18:20 +0800 | [diff] [blame] | 3352 | free_dmar_iommu(iommu); |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 3353 | } |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 3354 | free_g_iommus: |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3355 | for_each_possible_cpu(cpu) |
| 3356 | kfree(per_cpu_ptr(&deferred_flush, cpu)->tables); |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 3357 | kfree(g_iommus); |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 3358 | error: |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3359 | return ret; |
| 3360 | } |
| 3361 | |
David Woodhouse | 5a5e02a | 2009-07-04 09:35:44 +0100 | [diff] [blame] | 3362 | /* This takes a number of _MM_ pages, not VTD pages */ |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3363 | static unsigned long intel_alloc_iova(struct device *dev, |
David Woodhouse | 875764d | 2009-06-28 21:20:51 +0100 | [diff] [blame] | 3364 | struct dmar_domain *domain, |
| 3365 | unsigned long nrpages, uint64_t dma_mask) |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3366 | { |
Omer Peleg | 22e2f9f | 2016-04-20 11:34:11 +0300 | [diff] [blame] | 3367 | unsigned long iova_pfn = 0; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3368 | |
David Woodhouse | 875764d | 2009-06-28 21:20:51 +0100 | [diff] [blame] | 3369 | /* Restrict dma_mask to the width that the iommu can handle */ |
| 3370 | dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask); |
Robin Murphy | 8f6429c | 2015-07-16 19:40:12 +0100 | [diff] [blame] | 3371 | /* Ensure we reserve the whole size-aligned region */ |
| 3372 | nrpages = __roundup_pow_of_two(nrpages); |
David Woodhouse | 875764d | 2009-06-28 21:20:51 +0100 | [diff] [blame] | 3373 | |
| 3374 | if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) { |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3375 | /* |
| 3376 | * First try to allocate an io virtual address in |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 3377 | * DMA_BIT_MASK(32) and if that fails then try allocating |
Joe Perches | 3609801 | 2007-12-17 11:40:11 -0800 | [diff] [blame] | 3378 | * from higher range |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3379 | */ |
Omer Peleg | 22e2f9f | 2016-04-20 11:34:11 +0300 | [diff] [blame] | 3380 | iova_pfn = alloc_iova_fast(&domain->iovad, nrpages, |
| 3381 | IOVA_PFN(DMA_BIT_MASK(32))); |
| 3382 | if (iova_pfn) |
| 3383 | return iova_pfn; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3384 | } |
Omer Peleg | 22e2f9f | 2016-04-20 11:34:11 +0300 | [diff] [blame] | 3385 | iova_pfn = alloc_iova_fast(&domain->iovad, nrpages, IOVA_PFN(dma_mask)); |
| 3386 | if (unlikely(!iova_pfn)) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 3387 | pr_err("Allocating %ld-page iova for %s failed", |
David Woodhouse | 207e359 | 2014-03-09 16:12:32 -0700 | [diff] [blame] | 3388 | nrpages, dev_name(dev)); |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3389 | return 0; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3390 | } |
| 3391 | |
Omer Peleg | 22e2f9f | 2016-04-20 11:34:11 +0300 | [diff] [blame] | 3392 | return iova_pfn; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3393 | } |
| 3394 | |
David Woodhouse | d4b709f | 2014-03-09 16:07:40 -0700 | [diff] [blame] | 3395 | static struct dmar_domain *__get_valid_domain_for_dev(struct device *dev) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3396 | { |
Joerg Roedel | b1ce5b7 | 2015-09-23 19:16:01 +0200 | [diff] [blame] | 3397 | struct dmar_rmrr_unit *rmrr; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3398 | struct dmar_domain *domain; |
Joerg Roedel | b1ce5b7 | 2015-09-23 19:16:01 +0200 | [diff] [blame] | 3399 | struct device *i_dev; |
| 3400 | int i, ret; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3401 | |
David Woodhouse | d4b709f | 2014-03-09 16:07:40 -0700 | [diff] [blame] | 3402 | domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3403 | if (!domain) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 3404 | pr_err("Allocating domain for %s failed\n", |
David Woodhouse | d4b709f | 2014-03-09 16:07:40 -0700 | [diff] [blame] | 3405 | dev_name(dev)); |
Al Viro | 4fe05bb | 2007-10-29 04:51:16 +0000 | [diff] [blame] | 3406 | return NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3407 | } |
| 3408 | |
Joerg Roedel | b1ce5b7 | 2015-09-23 19:16:01 +0200 | [diff] [blame] | 3409 | /* We have a new domain - setup possible RMRRs for the device */ |
| 3410 | rcu_read_lock(); |
| 3411 | for_each_rmrr_units(rmrr) { |
| 3412 | for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt, |
| 3413 | i, i_dev) { |
| 3414 | if (i_dev != dev) |
| 3415 | continue; |
| 3416 | |
| 3417 | ret = domain_prepare_identity_map(dev, domain, |
| 3418 | rmrr->base_address, |
| 3419 | rmrr->end_address); |
| 3420 | if (ret) |
| 3421 | dev_err(dev, "Mapping reserved region failed\n"); |
| 3422 | } |
| 3423 | } |
| 3424 | rcu_read_unlock(); |
| 3425 | |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3426 | return domain; |
| 3427 | } |
| 3428 | |
David Woodhouse | d4b709f | 2014-03-09 16:07:40 -0700 | [diff] [blame] | 3429 | static inline struct dmar_domain *get_valid_domain_for_dev(struct device *dev) |
David Woodhouse | 147202a | 2009-07-07 19:43:20 +0100 | [diff] [blame] | 3430 | { |
| 3431 | struct device_domain_info *info; |
| 3432 | |
| 3433 | /* No lock here, assumes no domain exit in normal case */ |
David Woodhouse | d4b709f | 2014-03-09 16:07:40 -0700 | [diff] [blame] | 3434 | info = dev->archdata.iommu; |
David Woodhouse | 147202a | 2009-07-07 19:43:20 +0100 | [diff] [blame] | 3435 | if (likely(info)) |
| 3436 | return info->domain; |
| 3437 | |
| 3438 | return __get_valid_domain_for_dev(dev); |
| 3439 | } |
| 3440 | |
David Woodhouse | ecb509e | 2014-03-09 16:29:55 -0700 | [diff] [blame] | 3441 | /* Check if the dev needs to go through non-identity map and unmap process.*/ |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 3442 | static int iommu_no_mapping(struct device *dev) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3443 | { |
| 3444 | int found; |
| 3445 | |
David Woodhouse | 3d89194 | 2014-03-06 15:59:26 +0000 | [diff] [blame] | 3446 | if (iommu_dummy(dev)) |
David Woodhouse | 1e4c64c | 2009-07-04 10:40:38 +0100 | [diff] [blame] | 3447 | return 1; |
| 3448 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3449 | if (!iommu_identity_mapping) |
David Woodhouse | 1e4c64c | 2009-07-04 10:40:38 +0100 | [diff] [blame] | 3450 | return 0; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3451 | |
David Woodhouse | 9b22662 | 2014-03-09 14:03:28 -0700 | [diff] [blame] | 3452 | found = identity_mapping(dev); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3453 | if (found) { |
David Woodhouse | ecb509e | 2014-03-09 16:29:55 -0700 | [diff] [blame] | 3454 | if (iommu_should_identity_map(dev, 0)) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3455 | return 1; |
| 3456 | else { |
| 3457 | /* |
| 3458 | * 32 bit DMA is removed from si_domain and fall back |
| 3459 | * to non-identity mapping. |
| 3460 | */ |
Joerg Roedel | e6de0f8 | 2015-07-22 16:30:36 +0200 | [diff] [blame] | 3461 | dmar_remove_one_dev_info(si_domain, dev); |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 3462 | pr_info("32bit %s uses non-identity mapping\n", |
| 3463 | dev_name(dev)); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3464 | return 0; |
| 3465 | } |
| 3466 | } else { |
| 3467 | /* |
| 3468 | * In case of a detached 64 bit DMA device from vm, the device |
| 3469 | * is put into si_domain for identity mapping. |
| 3470 | */ |
David Woodhouse | ecb509e | 2014-03-09 16:29:55 -0700 | [diff] [blame] | 3471 | if (iommu_should_identity_map(dev, 0)) { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3472 | int ret; |
Joerg Roedel | 28ccce0 | 2015-07-21 14:45:31 +0200 | [diff] [blame] | 3473 | ret = domain_add_dev_info(si_domain, dev); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3474 | if (!ret) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 3475 | pr_info("64bit %s uses identity mapping\n", |
| 3476 | dev_name(dev)); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3477 | return 1; |
| 3478 | } |
| 3479 | } |
| 3480 | } |
| 3481 | |
David Woodhouse | 1e4c64c | 2009-07-04 10:40:38 +0100 | [diff] [blame] | 3482 | return 0; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3483 | } |
| 3484 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3485 | static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr, |
FUJITA Tomonori | bb9e6d6 | 2008-10-15 16:08:28 +0900 | [diff] [blame] | 3486 | size_t size, int dir, u64 dma_mask) |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3487 | { |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3488 | struct dmar_domain *domain; |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 3489 | phys_addr_t start_paddr; |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3490 | unsigned long iova_pfn; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3491 | int prot = 0; |
Ingo Molnar | 6865f0d | 2008-04-22 11:09:04 +0200 | [diff] [blame] | 3492 | int ret; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3493 | struct intel_iommu *iommu; |
Fenghua Yu | 33041ec | 2009-08-04 15:10:59 -0700 | [diff] [blame] | 3494 | unsigned long paddr_pfn = paddr >> PAGE_SHIFT; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3495 | |
| 3496 | BUG_ON(dir == DMA_NONE); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3497 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3498 | if (iommu_no_mapping(dev)) |
Ingo Molnar | 6865f0d | 2008-04-22 11:09:04 +0200 | [diff] [blame] | 3499 | return paddr; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3500 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3501 | domain = get_valid_domain_for_dev(dev); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3502 | if (!domain) |
| 3503 | return 0; |
| 3504 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3505 | iommu = domain_get_iommu(domain); |
David Woodhouse | 88cb6a7 | 2009-06-28 15:03:06 +0100 | [diff] [blame] | 3506 | size = aligned_nrpages(paddr, size); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3507 | |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3508 | iova_pfn = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), dma_mask); |
| 3509 | if (!iova_pfn) |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3510 | goto error; |
| 3511 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3512 | /* |
| 3513 | * Check if DMAR supports zero-length reads on write only |
| 3514 | * mappings.. |
| 3515 | */ |
| 3516 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3517 | !cap_zlr(iommu->cap)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3518 | prot |= DMA_PTE_READ; |
| 3519 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) |
| 3520 | prot |= DMA_PTE_WRITE; |
| 3521 | /* |
Ingo Molnar | 6865f0d | 2008-04-22 11:09:04 +0200 | [diff] [blame] | 3522 | * paddr - (paddr + size) might be partial page, we should map the whole |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3523 | * page. Note: if two part of one page are separately mapped, we |
Ingo Molnar | 6865f0d | 2008-04-22 11:09:04 +0200 | [diff] [blame] | 3524 | * might have two guest_addr mapping to the same host paddr, but this |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3525 | * is not a big problem |
| 3526 | */ |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3527 | ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova_pfn), |
Fenghua Yu | 33041ec | 2009-08-04 15:10:59 -0700 | [diff] [blame] | 3528 | mm_to_dma_pfn(paddr_pfn), size, prot); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3529 | if (ret) |
| 3530 | goto error; |
| 3531 | |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3532 | /* it's a non-present to present mapping. Only flush if caching mode */ |
| 3533 | if (cap_caching_mode(iommu->cap)) |
Joerg Roedel | a1ddcbe | 2015-07-21 15:20:32 +0200 | [diff] [blame] | 3534 | iommu_flush_iotlb_psi(iommu, domain, |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3535 | mm_to_dma_pfn(iova_pfn), |
Joerg Roedel | a1ddcbe | 2015-07-21 15:20:32 +0200 | [diff] [blame] | 3536 | size, 0, 1); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3537 | else |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3538 | iommu_flush_write_buffer(iommu); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3539 | |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3540 | start_paddr = (phys_addr_t)iova_pfn << PAGE_SHIFT; |
David Woodhouse | 03d6a24 | 2009-06-28 15:33:46 +0100 | [diff] [blame] | 3541 | start_paddr += paddr & ~PAGE_MASK; |
| 3542 | return start_paddr; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3543 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3544 | error: |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3545 | if (iova_pfn) |
Omer Peleg | 22e2f9f | 2016-04-20 11:34:11 +0300 | [diff] [blame] | 3546 | free_iova_fast(&domain->iovad, iova_pfn, dma_to_mm_pfn(size)); |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 3547 | pr_err("Device %s request: %zx@%llx dir %d --- failed\n", |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3548 | dev_name(dev), size, (unsigned long long)paddr, dir); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3549 | return 0; |
| 3550 | } |
| 3551 | |
FUJITA Tomonori | ffbbef5 | 2009-01-05 23:47:26 +0900 | [diff] [blame] | 3552 | static dma_addr_t intel_map_page(struct device *dev, struct page *page, |
| 3553 | unsigned long offset, size_t size, |
| 3554 | enum dma_data_direction dir, |
| 3555 | struct dma_attrs *attrs) |
FUJITA Tomonori | bb9e6d6 | 2008-10-15 16:08:28 +0900 | [diff] [blame] | 3556 | { |
FUJITA Tomonori | ffbbef5 | 2009-01-05 23:47:26 +0900 | [diff] [blame] | 3557 | return __intel_map_single(dev, page_to_phys(page) + offset, size, |
David Woodhouse | 46333e3 | 2014-03-10 20:01:21 -0700 | [diff] [blame] | 3558 | dir, *dev->dma_mask); |
FUJITA Tomonori | bb9e6d6 | 2008-10-15 16:08:28 +0900 | [diff] [blame] | 3559 | } |
| 3560 | |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3561 | static void flush_unmaps(struct deferred_flush_data *flush_data) |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3562 | { |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3563 | int i, j; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3564 | |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3565 | flush_data->timer_on = 0; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3566 | |
| 3567 | /* just flush them all */ |
| 3568 | for (i = 0; i < g_num_of_iommus; i++) { |
Weidong Han | a2bb845 | 2008-12-08 11:24:12 +0800 | [diff] [blame] | 3569 | struct intel_iommu *iommu = g_iommus[i]; |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3570 | struct deferred_flush_table *flush_table = |
| 3571 | &flush_data->tables[i]; |
Weidong Han | a2bb845 | 2008-12-08 11:24:12 +0800 | [diff] [blame] | 3572 | if (!iommu) |
| 3573 | continue; |
Suresh Siddha | c42d9f3 | 2008-07-10 11:16:36 -0700 | [diff] [blame] | 3574 | |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3575 | if (!flush_table->next) |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 3576 | continue; |
| 3577 | |
Nadav Amit | 78d5f0f | 2010-04-08 23:00:41 +0300 | [diff] [blame] | 3578 | /* In caching mode, global flushes turn emulation expensive */ |
| 3579 | if (!cap_caching_mode(iommu->cap)) |
| 3580 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 3581 | DMA_TLB_GLOBAL_FLUSH); |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3582 | for (j = 0; j < flush_table->next; j++) { |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 3583 | unsigned long mask; |
Omer Peleg | 314f1dc | 2016-04-20 11:32:45 +0300 | [diff] [blame] | 3584 | struct deferred_flush_entry *entry = |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3585 | &flush_table->entries[j]; |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3586 | unsigned long iova_pfn = entry->iova_pfn; |
Omer Peleg | 769530e | 2016-04-20 11:33:25 +0300 | [diff] [blame] | 3587 | unsigned long nrpages = entry->nrpages; |
Omer Peleg | 314f1dc | 2016-04-20 11:32:45 +0300 | [diff] [blame] | 3588 | struct dmar_domain *domain = entry->domain; |
| 3589 | struct page *freelist = entry->freelist; |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 3590 | |
Nadav Amit | 78d5f0f | 2010-04-08 23:00:41 +0300 | [diff] [blame] | 3591 | /* On real hardware multiple invalidations are expensive */ |
| 3592 | if (cap_caching_mode(iommu->cap)) |
Joerg Roedel | a1ddcbe | 2015-07-21 15:20:32 +0200 | [diff] [blame] | 3593 | iommu_flush_iotlb_psi(iommu, domain, |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3594 | mm_to_dma_pfn(iova_pfn), |
Omer Peleg | 769530e | 2016-04-20 11:33:25 +0300 | [diff] [blame] | 3595 | nrpages, !freelist, 0); |
Nadav Amit | 78d5f0f | 2010-04-08 23:00:41 +0300 | [diff] [blame] | 3596 | else { |
Omer Peleg | 769530e | 2016-04-20 11:33:25 +0300 | [diff] [blame] | 3597 | mask = ilog2(nrpages); |
Omer Peleg | 314f1dc | 2016-04-20 11:32:45 +0300 | [diff] [blame] | 3598 | iommu_flush_dev_iotlb(domain, |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3599 | (uint64_t)iova_pfn << PAGE_SHIFT, mask); |
Nadav Amit | 78d5f0f | 2010-04-08 23:00:41 +0300 | [diff] [blame] | 3600 | } |
Omer Peleg | 22e2f9f | 2016-04-20 11:34:11 +0300 | [diff] [blame] | 3601 | free_iova_fast(&domain->iovad, iova_pfn, nrpages); |
Omer Peleg | 314f1dc | 2016-04-20 11:32:45 +0300 | [diff] [blame] | 3602 | if (freelist) |
| 3603 | dma_free_pagelist(freelist); |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3604 | } |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3605 | flush_table->next = 0; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3606 | } |
| 3607 | |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3608 | flush_data->size = 0; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3609 | } |
| 3610 | |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3611 | static void flush_unmaps_timeout(unsigned long cpuid) |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3612 | { |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3613 | struct deferred_flush_data *flush_data = per_cpu_ptr(&deferred_flush, cpuid); |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3614 | unsigned long flags; |
| 3615 | |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3616 | spin_lock_irqsave(&flush_data->lock, flags); |
| 3617 | flush_unmaps(flush_data); |
| 3618 | spin_unlock_irqrestore(&flush_data->lock, flags); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3619 | } |
| 3620 | |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3621 | static void add_unmap(struct dmar_domain *dom, unsigned long iova_pfn, |
Omer Peleg | 769530e | 2016-04-20 11:33:25 +0300 | [diff] [blame] | 3622 | unsigned long nrpages, struct page *freelist) |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3623 | { |
| 3624 | unsigned long flags; |
Omer Peleg | 314f1dc | 2016-04-20 11:32:45 +0300 | [diff] [blame] | 3625 | int entry_id, iommu_id; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3626 | struct intel_iommu *iommu; |
Omer Peleg | 314f1dc | 2016-04-20 11:32:45 +0300 | [diff] [blame] | 3627 | struct deferred_flush_entry *entry; |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3628 | struct deferred_flush_data *flush_data; |
| 3629 | unsigned int cpuid; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3630 | |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3631 | cpuid = get_cpu(); |
| 3632 | flush_data = per_cpu_ptr(&deferred_flush, cpuid); |
| 3633 | |
| 3634 | /* Flush all CPUs' entries to avoid deferring too much. If |
| 3635 | * this becomes a bottleneck, can just flush us, and rely on |
| 3636 | * flush timer for the rest. |
| 3637 | */ |
| 3638 | if (flush_data->size == HIGH_WATER_MARK) { |
| 3639 | int cpu; |
| 3640 | |
| 3641 | for_each_online_cpu(cpu) |
| 3642 | flush_unmaps_timeout(cpu); |
| 3643 | } |
| 3644 | |
| 3645 | spin_lock_irqsave(&flush_data->lock, flags); |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3646 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3647 | iommu = domain_get_iommu(dom); |
| 3648 | iommu_id = iommu->seq_id; |
Suresh Siddha | c42d9f3 | 2008-07-10 11:16:36 -0700 | [diff] [blame] | 3649 | |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3650 | entry_id = flush_data->tables[iommu_id].next; |
| 3651 | ++(flush_data->tables[iommu_id].next); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3652 | |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3653 | entry = &flush_data->tables[iommu_id].entries[entry_id]; |
Omer Peleg | 314f1dc | 2016-04-20 11:32:45 +0300 | [diff] [blame] | 3654 | entry->domain = dom; |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3655 | entry->iova_pfn = iova_pfn; |
Omer Peleg | 769530e | 2016-04-20 11:33:25 +0300 | [diff] [blame] | 3656 | entry->nrpages = nrpages; |
Omer Peleg | 314f1dc | 2016-04-20 11:32:45 +0300 | [diff] [blame] | 3657 | entry->freelist = freelist; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3658 | |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3659 | if (!flush_data->timer_on) { |
| 3660 | mod_timer(&flush_data->timer, jiffies + msecs_to_jiffies(10)); |
| 3661 | flush_data->timer_on = 1; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3662 | } |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 3663 | flush_data->size++; |
| 3664 | spin_unlock_irqrestore(&flush_data->lock, flags); |
| 3665 | |
| 3666 | put_cpu(); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3667 | } |
| 3668 | |
Omer Peleg | 769530e | 2016-04-20 11:33:25 +0300 | [diff] [blame] | 3669 | static void intel_unmap(struct device *dev, dma_addr_t dev_addr, size_t size) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3670 | { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3671 | struct dmar_domain *domain; |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 3672 | unsigned long start_pfn, last_pfn; |
Omer Peleg | 769530e | 2016-04-20 11:33:25 +0300 | [diff] [blame] | 3673 | unsigned long nrpages; |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3674 | unsigned long iova_pfn; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3675 | struct intel_iommu *iommu; |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3676 | struct page *freelist; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3677 | |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 3678 | if (iommu_no_mapping(dev)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3679 | return; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3680 | |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame] | 3681 | domain = find_domain(dev); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3682 | BUG_ON(!domain); |
| 3683 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3684 | iommu = domain_get_iommu(domain); |
| 3685 | |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3686 | iova_pfn = IOVA_PFN(dev_addr); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3687 | |
Omer Peleg | 769530e | 2016-04-20 11:33:25 +0300 | [diff] [blame] | 3688 | nrpages = aligned_nrpages(dev_addr, size); |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3689 | start_pfn = mm_to_dma_pfn(iova_pfn); |
Omer Peleg | 769530e | 2016-04-20 11:33:25 +0300 | [diff] [blame] | 3690 | last_pfn = start_pfn + nrpages - 1; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3691 | |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 3692 | pr_debug("Device %s unmapping: pfn %lx-%lx\n", |
David Woodhouse | 207e359 | 2014-03-09 16:12:32 -0700 | [diff] [blame] | 3693 | dev_name(dev), start_pfn, last_pfn); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3694 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3695 | freelist = domain_unmap(domain, start_pfn, last_pfn); |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 3696 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3697 | if (intel_iommu_strict) { |
Joerg Roedel | a1ddcbe | 2015-07-21 15:20:32 +0200 | [diff] [blame] | 3698 | iommu_flush_iotlb_psi(iommu, domain, start_pfn, |
Omer Peleg | 769530e | 2016-04-20 11:33:25 +0300 | [diff] [blame] | 3699 | nrpages, !freelist, 0); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3700 | /* free iova */ |
Omer Peleg | 22e2f9f | 2016-04-20 11:34:11 +0300 | [diff] [blame] | 3701 | free_iova_fast(&domain->iovad, iova_pfn, dma_to_mm_pfn(nrpages)); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3702 | dma_free_pagelist(freelist); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3703 | } else { |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3704 | add_unmap(domain, iova_pfn, nrpages, freelist); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3705 | /* |
| 3706 | * queue up the release of the unmap to save the 1/6th of the |
| 3707 | * cpu used up by the iotlb flush operation... |
| 3708 | */ |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3709 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3710 | } |
| 3711 | |
Jiang Liu | d41a4ad | 2014-07-11 14:19:34 +0800 | [diff] [blame] | 3712 | static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr, |
| 3713 | size_t size, enum dma_data_direction dir, |
| 3714 | struct dma_attrs *attrs) |
| 3715 | { |
Omer Peleg | 769530e | 2016-04-20 11:33:25 +0300 | [diff] [blame] | 3716 | intel_unmap(dev, dev_addr, size); |
Jiang Liu | d41a4ad | 2014-07-11 14:19:34 +0800 | [diff] [blame] | 3717 | } |
| 3718 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3719 | static void *intel_alloc_coherent(struct device *dev, size_t size, |
Andrzej Pietrasiewicz | baa676f | 2012-03-27 14:28:18 +0200 | [diff] [blame] | 3720 | dma_addr_t *dma_handle, gfp_t flags, |
| 3721 | struct dma_attrs *attrs) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3722 | { |
Akinobu Mita | 3674643 | 2014-06-04 16:06:51 -0700 | [diff] [blame] | 3723 | struct page *page = NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3724 | int order; |
| 3725 | |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 3726 | size = PAGE_ALIGN(size); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3727 | order = get_order(size); |
Alex Williamson | e8bb910 | 2009-11-04 15:59:34 -0700 | [diff] [blame] | 3728 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3729 | if (!iommu_no_mapping(dev)) |
Alex Williamson | e8bb910 | 2009-11-04 15:59:34 -0700 | [diff] [blame] | 3730 | flags &= ~(GFP_DMA | GFP_DMA32); |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3731 | else if (dev->coherent_dma_mask < dma_get_required_mask(dev)) { |
| 3732 | if (dev->coherent_dma_mask < DMA_BIT_MASK(32)) |
Alex Williamson | e8bb910 | 2009-11-04 15:59:34 -0700 | [diff] [blame] | 3733 | flags |= GFP_DMA; |
| 3734 | else |
| 3735 | flags |= GFP_DMA32; |
| 3736 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3737 | |
Mel Gorman | d0164ad | 2015-11-06 16:28:21 -0800 | [diff] [blame] | 3738 | if (gfpflags_allow_blocking(flags)) { |
Akinobu Mita | 3674643 | 2014-06-04 16:06:51 -0700 | [diff] [blame] | 3739 | unsigned int count = size >> PAGE_SHIFT; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3740 | |
Akinobu Mita | 3674643 | 2014-06-04 16:06:51 -0700 | [diff] [blame] | 3741 | page = dma_alloc_from_contiguous(dev, count, order); |
| 3742 | if (page && iommu_no_mapping(dev) && |
| 3743 | page_to_phys(page) + size > dev->coherent_dma_mask) { |
| 3744 | dma_release_from_contiguous(dev, page, count); |
| 3745 | page = NULL; |
| 3746 | } |
| 3747 | } |
| 3748 | |
| 3749 | if (!page) |
| 3750 | page = alloc_pages(flags, order); |
| 3751 | if (!page) |
| 3752 | return NULL; |
| 3753 | memset(page_address(page), 0, size); |
| 3754 | |
| 3755 | *dma_handle = __intel_map_single(dev, page_to_phys(page), size, |
FUJITA Tomonori | bb9e6d6 | 2008-10-15 16:08:28 +0900 | [diff] [blame] | 3756 | DMA_BIDIRECTIONAL, |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3757 | dev->coherent_dma_mask); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3758 | if (*dma_handle) |
Akinobu Mita | 3674643 | 2014-06-04 16:06:51 -0700 | [diff] [blame] | 3759 | return page_address(page); |
| 3760 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
| 3761 | __free_pages(page, order); |
| 3762 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3763 | return NULL; |
| 3764 | } |
| 3765 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3766 | static void intel_free_coherent(struct device *dev, size_t size, void *vaddr, |
Andrzej Pietrasiewicz | baa676f | 2012-03-27 14:28:18 +0200 | [diff] [blame] | 3767 | dma_addr_t dma_handle, struct dma_attrs *attrs) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3768 | { |
| 3769 | int order; |
Akinobu Mita | 3674643 | 2014-06-04 16:06:51 -0700 | [diff] [blame] | 3770 | struct page *page = virt_to_page(vaddr); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3771 | |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 3772 | size = PAGE_ALIGN(size); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3773 | order = get_order(size); |
| 3774 | |
Omer Peleg | 769530e | 2016-04-20 11:33:25 +0300 | [diff] [blame] | 3775 | intel_unmap(dev, dma_handle, size); |
Akinobu Mita | 3674643 | 2014-06-04 16:06:51 -0700 | [diff] [blame] | 3776 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
| 3777 | __free_pages(page, order); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3778 | } |
| 3779 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3780 | static void intel_unmap_sg(struct device *dev, struct scatterlist *sglist, |
FUJITA Tomonori | d7ab5c4 | 2009-01-28 21:53:18 +0900 | [diff] [blame] | 3781 | int nelems, enum dma_data_direction dir, |
| 3782 | struct dma_attrs *attrs) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3783 | { |
Omer Peleg | 769530e | 2016-04-20 11:33:25 +0300 | [diff] [blame] | 3784 | dma_addr_t startaddr = sg_dma_address(sglist) & PAGE_MASK; |
| 3785 | unsigned long nrpages = 0; |
| 3786 | struct scatterlist *sg; |
| 3787 | int i; |
| 3788 | |
| 3789 | for_each_sg(sglist, sg, nelems, i) { |
| 3790 | nrpages += aligned_nrpages(sg_dma_address(sg), sg_dma_len(sg)); |
| 3791 | } |
| 3792 | |
| 3793 | intel_unmap(dev, startaddr, nrpages << VTD_PAGE_SHIFT); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3794 | } |
| 3795 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3796 | static int intel_nontranslate_map_sg(struct device *hddev, |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3797 | struct scatterlist *sglist, int nelems, int dir) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3798 | { |
| 3799 | int i; |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3800 | struct scatterlist *sg; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3801 | |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3802 | for_each_sg(sglist, sg, nelems, i) { |
FUJITA Tomonori | 12d4d40 | 2007-10-23 09:32:25 +0200 | [diff] [blame] | 3803 | BUG_ON(!sg_page(sg)); |
Dan Williams | 3e6110f | 2015-12-15 12:54:06 -0800 | [diff] [blame] | 3804 | sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset; |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3805 | sg->dma_length = sg->length; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3806 | } |
| 3807 | return nelems; |
| 3808 | } |
| 3809 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3810 | static int intel_map_sg(struct device *dev, struct scatterlist *sglist, int nelems, |
FUJITA Tomonori | d7ab5c4 | 2009-01-28 21:53:18 +0900 | [diff] [blame] | 3811 | enum dma_data_direction dir, struct dma_attrs *attrs) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3812 | { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3813 | int i; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3814 | struct dmar_domain *domain; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3815 | size_t size = 0; |
| 3816 | int prot = 0; |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3817 | unsigned long iova_pfn; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3818 | int ret; |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3819 | struct scatterlist *sg; |
David Woodhouse | b536d24 | 2009-06-28 14:49:31 +0100 | [diff] [blame] | 3820 | unsigned long start_vpfn; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3821 | struct intel_iommu *iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3822 | |
| 3823 | BUG_ON(dir == DMA_NONE); |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3824 | if (iommu_no_mapping(dev)) |
| 3825 | return intel_nontranslate_map_sg(dev, sglist, nelems, dir); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3826 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3827 | domain = get_valid_domain_for_dev(dev); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3828 | if (!domain) |
| 3829 | return 0; |
| 3830 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3831 | iommu = domain_get_iommu(domain); |
| 3832 | |
David Woodhouse | b536d24 | 2009-06-28 14:49:31 +0100 | [diff] [blame] | 3833 | for_each_sg(sglist, sg, nelems, i) |
David Woodhouse | 88cb6a7 | 2009-06-28 15:03:06 +0100 | [diff] [blame] | 3834 | size += aligned_nrpages(sg->offset, sg->length); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3835 | |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3836 | iova_pfn = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3837 | *dev->dma_mask); |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3838 | if (!iova_pfn) { |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3839 | sglist->dma_length = 0; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3840 | return 0; |
| 3841 | } |
| 3842 | |
| 3843 | /* |
| 3844 | * Check if DMAR supports zero-length reads on write only |
| 3845 | * mappings.. |
| 3846 | */ |
| 3847 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3848 | !cap_zlr(iommu->cap)) |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3849 | prot |= DMA_PTE_READ; |
| 3850 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) |
| 3851 | prot |= DMA_PTE_WRITE; |
| 3852 | |
Omer Peleg | 2aac630 | 2016-04-20 11:33:57 +0300 | [diff] [blame] | 3853 | start_vpfn = mm_to_dma_pfn(iova_pfn); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 3854 | |
Fenghua Yu | f532959 | 2009-08-04 15:09:37 -0700 | [diff] [blame] | 3855 | ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 3856 | if (unlikely(ret)) { |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 3857 | dma_pte_free_pagetable(domain, start_vpfn, |
| 3858 | start_vpfn + size - 1); |
Omer Peleg | 22e2f9f | 2016-04-20 11:34:11 +0300 | [diff] [blame] | 3859 | free_iova_fast(&domain->iovad, iova_pfn, dma_to_mm_pfn(size)); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 3860 | return 0; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3861 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3862 | |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3863 | /* it's a non-present to present mapping. Only flush if caching mode */ |
| 3864 | if (cap_caching_mode(iommu->cap)) |
Joerg Roedel | a1ddcbe | 2015-07-21 15:20:32 +0200 | [diff] [blame] | 3865 | iommu_flush_iotlb_psi(iommu, domain, start_vpfn, size, 0, 1); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3866 | else |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3867 | iommu_flush_write_buffer(iommu); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3868 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3869 | return nelems; |
| 3870 | } |
| 3871 | |
FUJITA Tomonori | dfb805e | 2009-01-28 21:53:17 +0900 | [diff] [blame] | 3872 | static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr) |
| 3873 | { |
| 3874 | return !dma_addr; |
| 3875 | } |
| 3876 | |
FUJITA Tomonori | 160c1d8 | 2009-01-05 23:59:02 +0900 | [diff] [blame] | 3877 | struct dma_map_ops intel_dma_ops = { |
Andrzej Pietrasiewicz | baa676f | 2012-03-27 14:28:18 +0200 | [diff] [blame] | 3878 | .alloc = intel_alloc_coherent, |
| 3879 | .free = intel_free_coherent, |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3880 | .map_sg = intel_map_sg, |
| 3881 | .unmap_sg = intel_unmap_sg, |
FUJITA Tomonori | ffbbef5 | 2009-01-05 23:47:26 +0900 | [diff] [blame] | 3882 | .map_page = intel_map_page, |
| 3883 | .unmap_page = intel_unmap_page, |
FUJITA Tomonori | dfb805e | 2009-01-28 21:53:17 +0900 | [diff] [blame] | 3884 | .mapping_error = intel_mapping_error, |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3885 | }; |
| 3886 | |
| 3887 | static inline int iommu_domain_cache_init(void) |
| 3888 | { |
| 3889 | int ret = 0; |
| 3890 | |
| 3891 | iommu_domain_cache = kmem_cache_create("iommu_domain", |
| 3892 | sizeof(struct dmar_domain), |
| 3893 | 0, |
| 3894 | SLAB_HWCACHE_ALIGN, |
| 3895 | |
| 3896 | NULL); |
| 3897 | if (!iommu_domain_cache) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 3898 | pr_err("Couldn't create iommu_domain cache\n"); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3899 | ret = -ENOMEM; |
| 3900 | } |
| 3901 | |
| 3902 | return ret; |
| 3903 | } |
| 3904 | |
| 3905 | static inline int iommu_devinfo_cache_init(void) |
| 3906 | { |
| 3907 | int ret = 0; |
| 3908 | |
| 3909 | iommu_devinfo_cache = kmem_cache_create("iommu_devinfo", |
| 3910 | sizeof(struct device_domain_info), |
| 3911 | 0, |
| 3912 | SLAB_HWCACHE_ALIGN, |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3913 | NULL); |
| 3914 | if (!iommu_devinfo_cache) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 3915 | pr_err("Couldn't create devinfo cache\n"); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3916 | ret = -ENOMEM; |
| 3917 | } |
| 3918 | |
| 3919 | return ret; |
| 3920 | } |
| 3921 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3922 | static int __init iommu_init_mempool(void) |
| 3923 | { |
| 3924 | int ret; |
Sakari Ailus | ae1ff3d | 2015-07-13 14:31:28 +0300 | [diff] [blame] | 3925 | ret = iova_cache_get(); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3926 | if (ret) |
| 3927 | return ret; |
| 3928 | |
| 3929 | ret = iommu_domain_cache_init(); |
| 3930 | if (ret) |
| 3931 | goto domain_error; |
| 3932 | |
| 3933 | ret = iommu_devinfo_cache_init(); |
| 3934 | if (!ret) |
| 3935 | return ret; |
| 3936 | |
| 3937 | kmem_cache_destroy(iommu_domain_cache); |
| 3938 | domain_error: |
Sakari Ailus | ae1ff3d | 2015-07-13 14:31:28 +0300 | [diff] [blame] | 3939 | iova_cache_put(); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3940 | |
| 3941 | return -ENOMEM; |
| 3942 | } |
| 3943 | |
| 3944 | static void __init iommu_exit_mempool(void) |
| 3945 | { |
| 3946 | kmem_cache_destroy(iommu_devinfo_cache); |
| 3947 | kmem_cache_destroy(iommu_domain_cache); |
Sakari Ailus | ae1ff3d | 2015-07-13 14:31:28 +0300 | [diff] [blame] | 3948 | iova_cache_put(); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3949 | } |
| 3950 | |
Dan Williams | 556ab45 | 2010-07-23 15:47:56 -0700 | [diff] [blame] | 3951 | static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev) |
| 3952 | { |
| 3953 | struct dmar_drhd_unit *drhd; |
| 3954 | u32 vtbar; |
| 3955 | int rc; |
| 3956 | |
| 3957 | /* We know that this device on this chipset has its own IOMMU. |
| 3958 | * If we find it under a different IOMMU, then the BIOS is lying |
| 3959 | * to us. Hope that the IOMMU for this device is actually |
| 3960 | * disabled, and it needs no translation... |
| 3961 | */ |
| 3962 | rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar); |
| 3963 | if (rc) { |
| 3964 | /* "can't" happen */ |
| 3965 | dev_info(&pdev->dev, "failed to run vt-d quirk\n"); |
| 3966 | return; |
| 3967 | } |
| 3968 | vtbar &= 0xffff0000; |
| 3969 | |
| 3970 | /* we know that the this iommu should be at offset 0xa000 from vtbar */ |
| 3971 | drhd = dmar_find_matched_drhd_unit(pdev); |
| 3972 | if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000, |
| 3973 | TAINT_FIRMWARE_WORKAROUND, |
| 3974 | "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n")) |
| 3975 | pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; |
| 3976 | } |
| 3977 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu); |
| 3978 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3979 | static void __init init_no_remapping_devices(void) |
| 3980 | { |
| 3981 | struct dmar_drhd_unit *drhd; |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 3982 | struct device *dev; |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3983 | int i; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3984 | |
| 3985 | for_each_drhd_unit(drhd) { |
| 3986 | if (!drhd->include_all) { |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3987 | for_each_active_dev_scope(drhd->devices, |
| 3988 | drhd->devices_cnt, i, dev) |
| 3989 | break; |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 3990 | /* ignore DMAR unit if no devices exist */ |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3991 | if (i == drhd->devices_cnt) |
| 3992 | drhd->ignored = 1; |
| 3993 | } |
| 3994 | } |
| 3995 | |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 3996 | for_each_active_drhd_unit(drhd) { |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 3997 | if (drhd->include_all) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3998 | continue; |
| 3999 | |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 4000 | for_each_active_dev_scope(drhd->devices, |
| 4001 | drhd->devices_cnt, i, dev) |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 4002 | if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev))) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4003 | break; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4004 | if (i < drhd->devices_cnt) |
| 4005 | continue; |
| 4006 | |
David Woodhouse | c0771df | 2011-10-14 20:59:46 +0100 | [diff] [blame] | 4007 | /* This IOMMU has *only* gfx devices. Either bypass it or |
| 4008 | set the gfx_mapped flag, as appropriate */ |
| 4009 | if (dmar_map_gfx) { |
| 4010 | intel_iommu_gfx_mapped = 1; |
| 4011 | } else { |
| 4012 | drhd->ignored = 1; |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 4013 | for_each_active_dev_scope(drhd->devices, |
| 4014 | drhd->devices_cnt, i, dev) |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 4015 | dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4016 | } |
| 4017 | } |
| 4018 | } |
| 4019 | |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 4020 | #ifdef CONFIG_SUSPEND |
| 4021 | static int init_iommu_hw(void) |
| 4022 | { |
| 4023 | struct dmar_drhd_unit *drhd; |
| 4024 | struct intel_iommu *iommu = NULL; |
| 4025 | |
| 4026 | for_each_active_iommu(iommu, drhd) |
| 4027 | if (iommu->qi) |
| 4028 | dmar_reenable_qi(iommu); |
| 4029 | |
Joseph Cihula | b779260 | 2011-05-03 00:08:37 -0700 | [diff] [blame] | 4030 | for_each_iommu(iommu, drhd) { |
| 4031 | if (drhd->ignored) { |
| 4032 | /* |
| 4033 | * we always have to disable PMRs or DMA may fail on |
| 4034 | * this device |
| 4035 | */ |
| 4036 | if (force_on) |
| 4037 | iommu_disable_protect_mem_regions(iommu); |
| 4038 | continue; |
| 4039 | } |
| 4040 | |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 4041 | iommu_flush_write_buffer(iommu); |
| 4042 | |
| 4043 | iommu_set_root_entry(iommu); |
| 4044 | |
| 4045 | iommu->flush.flush_context(iommu, 0, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 4046 | DMA_CCMD_GLOBAL_INVL); |
Jiang Liu | 2a41cce | 2014-07-11 14:19:33 +0800 | [diff] [blame] | 4047 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
| 4048 | iommu_enable_translation(iommu); |
David Woodhouse | b94996c | 2009-09-19 15:28:12 -0700 | [diff] [blame] | 4049 | iommu_disable_protect_mem_regions(iommu); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 4050 | } |
| 4051 | |
| 4052 | return 0; |
| 4053 | } |
| 4054 | |
| 4055 | static void iommu_flush_all(void) |
| 4056 | { |
| 4057 | struct dmar_drhd_unit *drhd; |
| 4058 | struct intel_iommu *iommu; |
| 4059 | |
| 4060 | for_each_active_iommu(iommu, drhd) { |
| 4061 | iommu->flush.flush_context(iommu, 0, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 4062 | DMA_CCMD_GLOBAL_INVL); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 4063 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 4064 | DMA_TLB_GLOBAL_FLUSH); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 4065 | } |
| 4066 | } |
| 4067 | |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 4068 | static int iommu_suspend(void) |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 4069 | { |
| 4070 | struct dmar_drhd_unit *drhd; |
| 4071 | struct intel_iommu *iommu = NULL; |
| 4072 | unsigned long flag; |
| 4073 | |
| 4074 | for_each_active_iommu(iommu, drhd) { |
| 4075 | iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS, |
| 4076 | GFP_ATOMIC); |
| 4077 | if (!iommu->iommu_state) |
| 4078 | goto nomem; |
| 4079 | } |
| 4080 | |
| 4081 | iommu_flush_all(); |
| 4082 | |
| 4083 | for_each_active_iommu(iommu, drhd) { |
| 4084 | iommu_disable_translation(iommu); |
| 4085 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 4086 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 4087 | |
| 4088 | iommu->iommu_state[SR_DMAR_FECTL_REG] = |
| 4089 | readl(iommu->reg + DMAR_FECTL_REG); |
| 4090 | iommu->iommu_state[SR_DMAR_FEDATA_REG] = |
| 4091 | readl(iommu->reg + DMAR_FEDATA_REG); |
| 4092 | iommu->iommu_state[SR_DMAR_FEADDR_REG] = |
| 4093 | readl(iommu->reg + DMAR_FEADDR_REG); |
| 4094 | iommu->iommu_state[SR_DMAR_FEUADDR_REG] = |
| 4095 | readl(iommu->reg + DMAR_FEUADDR_REG); |
| 4096 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 4097 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 4098 | } |
| 4099 | return 0; |
| 4100 | |
| 4101 | nomem: |
| 4102 | for_each_active_iommu(iommu, drhd) |
| 4103 | kfree(iommu->iommu_state); |
| 4104 | |
| 4105 | return -ENOMEM; |
| 4106 | } |
| 4107 | |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 4108 | static void iommu_resume(void) |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 4109 | { |
| 4110 | struct dmar_drhd_unit *drhd; |
| 4111 | struct intel_iommu *iommu = NULL; |
| 4112 | unsigned long flag; |
| 4113 | |
| 4114 | if (init_iommu_hw()) { |
Joseph Cihula | b779260 | 2011-05-03 00:08:37 -0700 | [diff] [blame] | 4115 | if (force_on) |
| 4116 | panic("tboot: IOMMU setup failed, DMAR can not resume!\n"); |
| 4117 | else |
| 4118 | WARN(1, "IOMMU setup failed, DMAR can not resume!\n"); |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 4119 | return; |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 4120 | } |
| 4121 | |
| 4122 | for_each_active_iommu(iommu, drhd) { |
| 4123 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 4124 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 4125 | |
| 4126 | writel(iommu->iommu_state[SR_DMAR_FECTL_REG], |
| 4127 | iommu->reg + DMAR_FECTL_REG); |
| 4128 | writel(iommu->iommu_state[SR_DMAR_FEDATA_REG], |
| 4129 | iommu->reg + DMAR_FEDATA_REG); |
| 4130 | writel(iommu->iommu_state[SR_DMAR_FEADDR_REG], |
| 4131 | iommu->reg + DMAR_FEADDR_REG); |
| 4132 | writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG], |
| 4133 | iommu->reg + DMAR_FEUADDR_REG); |
| 4134 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 4135 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 4136 | } |
| 4137 | |
| 4138 | for_each_active_iommu(iommu, drhd) |
| 4139 | kfree(iommu->iommu_state); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 4140 | } |
| 4141 | |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 4142 | static struct syscore_ops iommu_syscore_ops = { |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 4143 | .resume = iommu_resume, |
| 4144 | .suspend = iommu_suspend, |
| 4145 | }; |
| 4146 | |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 4147 | static void __init init_iommu_pm_ops(void) |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 4148 | { |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 4149 | register_syscore_ops(&iommu_syscore_ops); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 4150 | } |
| 4151 | |
| 4152 | #else |
Rafael J. Wysocki | 99592ba | 2011-06-07 21:32:31 +0200 | [diff] [blame] | 4153 | static inline void init_iommu_pm_ops(void) {} |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 4154 | #endif /* CONFIG_PM */ |
| 4155 | |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4156 | |
Jiang Liu | c2a0b53 | 2014-11-09 22:47:56 +0800 | [diff] [blame] | 4157 | int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg) |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4158 | { |
| 4159 | struct acpi_dmar_reserved_memory *rmrr; |
| 4160 | struct dmar_rmrr_unit *rmrru; |
| 4161 | |
| 4162 | rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL); |
| 4163 | if (!rmrru) |
| 4164 | return -ENOMEM; |
| 4165 | |
| 4166 | rmrru->hdr = header; |
| 4167 | rmrr = (struct acpi_dmar_reserved_memory *)header; |
| 4168 | rmrru->base_address = rmrr->base_address; |
| 4169 | rmrru->end_address = rmrr->end_address; |
Jiang Liu | 2e45528 | 2014-02-19 14:07:36 +0800 | [diff] [blame] | 4170 | rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1), |
| 4171 | ((void *)rmrr) + rmrr->header.length, |
| 4172 | &rmrru->devices_cnt); |
| 4173 | if (rmrru->devices_cnt && rmrru->devices == NULL) { |
| 4174 | kfree(rmrru); |
| 4175 | return -ENOMEM; |
| 4176 | } |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4177 | |
Jiang Liu | 2e45528 | 2014-02-19 14:07:36 +0800 | [diff] [blame] | 4178 | list_add(&rmrru->list, &dmar_rmrr_units); |
| 4179 | |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4180 | return 0; |
| 4181 | } |
| 4182 | |
Jiang Liu | 6b19724 | 2014-11-09 22:47:58 +0800 | [diff] [blame] | 4183 | static struct dmar_atsr_unit *dmar_find_atsr(struct acpi_dmar_atsr *atsr) |
| 4184 | { |
| 4185 | struct dmar_atsr_unit *atsru; |
| 4186 | struct acpi_dmar_atsr *tmp; |
| 4187 | |
| 4188 | list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) { |
| 4189 | tmp = (struct acpi_dmar_atsr *)atsru->hdr; |
| 4190 | if (atsr->segment != tmp->segment) |
| 4191 | continue; |
| 4192 | if (atsr->header.length != tmp->header.length) |
| 4193 | continue; |
| 4194 | if (memcmp(atsr, tmp, atsr->header.length) == 0) |
| 4195 | return atsru; |
| 4196 | } |
| 4197 | |
| 4198 | return NULL; |
| 4199 | } |
| 4200 | |
| 4201 | int dmar_parse_one_atsr(struct acpi_dmar_header *hdr, void *arg) |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4202 | { |
| 4203 | struct acpi_dmar_atsr *atsr; |
| 4204 | struct dmar_atsr_unit *atsru; |
| 4205 | |
Jiang Liu | 6b19724 | 2014-11-09 22:47:58 +0800 | [diff] [blame] | 4206 | if (system_state != SYSTEM_BOOTING && !intel_iommu_enabled) |
| 4207 | return 0; |
| 4208 | |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4209 | atsr = container_of(hdr, struct acpi_dmar_atsr, header); |
Jiang Liu | 6b19724 | 2014-11-09 22:47:58 +0800 | [diff] [blame] | 4210 | atsru = dmar_find_atsr(atsr); |
| 4211 | if (atsru) |
| 4212 | return 0; |
| 4213 | |
| 4214 | atsru = kzalloc(sizeof(*atsru) + hdr->length, GFP_KERNEL); |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4215 | if (!atsru) |
| 4216 | return -ENOMEM; |
| 4217 | |
Jiang Liu | 6b19724 | 2014-11-09 22:47:58 +0800 | [diff] [blame] | 4218 | /* |
| 4219 | * If memory is allocated from slab by ACPI _DSM method, we need to |
| 4220 | * copy the memory content because the memory buffer will be freed |
| 4221 | * on return. |
| 4222 | */ |
| 4223 | atsru->hdr = (void *)(atsru + 1); |
| 4224 | memcpy(atsru->hdr, hdr, hdr->length); |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4225 | atsru->include_all = atsr->flags & 0x1; |
Jiang Liu | 2e45528 | 2014-02-19 14:07:36 +0800 | [diff] [blame] | 4226 | if (!atsru->include_all) { |
| 4227 | atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1), |
| 4228 | (void *)atsr + atsr->header.length, |
| 4229 | &atsru->devices_cnt); |
| 4230 | if (atsru->devices_cnt && atsru->devices == NULL) { |
| 4231 | kfree(atsru); |
| 4232 | return -ENOMEM; |
| 4233 | } |
| 4234 | } |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4235 | |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 4236 | list_add_rcu(&atsru->list, &dmar_atsr_units); |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4237 | |
| 4238 | return 0; |
| 4239 | } |
| 4240 | |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4241 | static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru) |
| 4242 | { |
| 4243 | dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt); |
| 4244 | kfree(atsru); |
| 4245 | } |
| 4246 | |
Jiang Liu | 6b19724 | 2014-11-09 22:47:58 +0800 | [diff] [blame] | 4247 | int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg) |
| 4248 | { |
| 4249 | struct acpi_dmar_atsr *atsr; |
| 4250 | struct dmar_atsr_unit *atsru; |
| 4251 | |
| 4252 | atsr = container_of(hdr, struct acpi_dmar_atsr, header); |
| 4253 | atsru = dmar_find_atsr(atsr); |
| 4254 | if (atsru) { |
| 4255 | list_del_rcu(&atsru->list); |
| 4256 | synchronize_rcu(); |
| 4257 | intel_iommu_free_atsr(atsru); |
| 4258 | } |
| 4259 | |
| 4260 | return 0; |
| 4261 | } |
| 4262 | |
| 4263 | int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg) |
| 4264 | { |
| 4265 | int i; |
| 4266 | struct device *dev; |
| 4267 | struct acpi_dmar_atsr *atsr; |
| 4268 | struct dmar_atsr_unit *atsru; |
| 4269 | |
| 4270 | atsr = container_of(hdr, struct acpi_dmar_atsr, header); |
| 4271 | atsru = dmar_find_atsr(atsr); |
| 4272 | if (!atsru) |
| 4273 | return 0; |
| 4274 | |
Linus Torvalds | 194dc87 | 2016-07-27 20:03:31 -0700 | [diff] [blame] | 4275 | if (!atsru->include_all && atsru->devices && atsru->devices_cnt) { |
Jiang Liu | 6b19724 | 2014-11-09 22:47:58 +0800 | [diff] [blame] | 4276 | for_each_active_dev_scope(atsru->devices, atsru->devices_cnt, |
| 4277 | i, dev) |
| 4278 | return -EBUSY; |
Linus Torvalds | 194dc87 | 2016-07-27 20:03:31 -0700 | [diff] [blame] | 4279 | } |
Jiang Liu | 6b19724 | 2014-11-09 22:47:58 +0800 | [diff] [blame] | 4280 | |
| 4281 | return 0; |
| 4282 | } |
| 4283 | |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 4284 | static int intel_iommu_add(struct dmar_drhd_unit *dmaru) |
| 4285 | { |
| 4286 | int sp, ret = 0; |
| 4287 | struct intel_iommu *iommu = dmaru->iommu; |
| 4288 | |
| 4289 | if (g_iommus[iommu->seq_id]) |
| 4290 | return 0; |
| 4291 | |
| 4292 | if (hw_pass_through && !ecap_pass_through(iommu->ecap)) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 4293 | pr_warn("%s: Doesn't support hardware pass through.\n", |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 4294 | iommu->name); |
| 4295 | return -ENXIO; |
| 4296 | } |
| 4297 | if (!ecap_sc_support(iommu->ecap) && |
| 4298 | domain_update_iommu_snooping(iommu)) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 4299 | pr_warn("%s: Doesn't support snooping.\n", |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 4300 | iommu->name); |
| 4301 | return -ENXIO; |
| 4302 | } |
| 4303 | sp = domain_update_iommu_superpage(iommu) - 1; |
| 4304 | if (sp >= 0 && !(cap_super_page_val(iommu->cap) & (1 << sp))) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 4305 | pr_warn("%s: Doesn't support large page.\n", |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 4306 | iommu->name); |
| 4307 | return -ENXIO; |
| 4308 | } |
| 4309 | |
| 4310 | /* |
| 4311 | * Disable translation if already enabled prior to OS handover. |
| 4312 | */ |
| 4313 | if (iommu->gcmd & DMA_GCMD_TE) |
| 4314 | iommu_disable_translation(iommu); |
| 4315 | |
| 4316 | g_iommus[iommu->seq_id] = iommu; |
| 4317 | ret = iommu_init_domains(iommu); |
| 4318 | if (ret == 0) |
| 4319 | ret = iommu_alloc_root_entry(iommu); |
| 4320 | if (ret) |
| 4321 | goto out; |
| 4322 | |
David Woodhouse | 8a94ade | 2015-03-24 14:54:56 +0000 | [diff] [blame] | 4323 | #ifdef CONFIG_INTEL_IOMMU_SVM |
| 4324 | if (pasid_enabled(iommu)) |
| 4325 | intel_svm_alloc_pasid_tables(iommu); |
| 4326 | #endif |
| 4327 | |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 4328 | if (dmaru->ignored) { |
| 4329 | /* |
| 4330 | * we always have to disable PMRs or DMA may fail on this device |
| 4331 | */ |
| 4332 | if (force_on) |
| 4333 | iommu_disable_protect_mem_regions(iommu); |
| 4334 | return 0; |
| 4335 | } |
| 4336 | |
| 4337 | intel_iommu_init_qi(iommu); |
| 4338 | iommu_flush_write_buffer(iommu); |
David Woodhouse | a222a7f | 2015-10-07 23:35:18 +0100 | [diff] [blame] | 4339 | |
| 4340 | #ifdef CONFIG_INTEL_IOMMU_SVM |
| 4341 | if (pasid_enabled(iommu) && ecap_prs(iommu->ecap)) { |
| 4342 | ret = intel_svm_enable_prq(iommu); |
| 4343 | if (ret) |
| 4344 | goto disable_iommu; |
| 4345 | } |
| 4346 | #endif |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 4347 | ret = dmar_set_interrupt(iommu); |
| 4348 | if (ret) |
| 4349 | goto disable_iommu; |
| 4350 | |
| 4351 | iommu_set_root_entry(iommu); |
| 4352 | iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); |
| 4353 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
| 4354 | iommu_enable_translation(iommu); |
| 4355 | |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 4356 | iommu_disable_protect_mem_regions(iommu); |
| 4357 | return 0; |
| 4358 | |
| 4359 | disable_iommu: |
| 4360 | disable_dmar_iommu(iommu); |
| 4361 | out: |
| 4362 | free_dmar_iommu(iommu); |
| 4363 | return ret; |
| 4364 | } |
| 4365 | |
Jiang Liu | 6b19724 | 2014-11-09 22:47:58 +0800 | [diff] [blame] | 4366 | int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert) |
| 4367 | { |
Jiang Liu | ffebeb4 | 2014-11-09 22:48:02 +0800 | [diff] [blame] | 4368 | int ret = 0; |
| 4369 | struct intel_iommu *iommu = dmaru->iommu; |
| 4370 | |
| 4371 | if (!intel_iommu_enabled) |
| 4372 | return 0; |
| 4373 | if (iommu == NULL) |
| 4374 | return -EINVAL; |
| 4375 | |
| 4376 | if (insert) { |
| 4377 | ret = intel_iommu_add(dmaru); |
| 4378 | } else { |
| 4379 | disable_dmar_iommu(iommu); |
| 4380 | free_dmar_iommu(iommu); |
| 4381 | } |
| 4382 | |
| 4383 | return ret; |
Jiang Liu | 6b19724 | 2014-11-09 22:47:58 +0800 | [diff] [blame] | 4384 | } |
| 4385 | |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4386 | static void intel_iommu_free_dmars(void) |
| 4387 | { |
| 4388 | struct dmar_rmrr_unit *rmrru, *rmrr_n; |
| 4389 | struct dmar_atsr_unit *atsru, *atsr_n; |
| 4390 | |
| 4391 | list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) { |
| 4392 | list_del(&rmrru->list); |
| 4393 | dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt); |
| 4394 | kfree(rmrru); |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4395 | } |
| 4396 | |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4397 | list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) { |
| 4398 | list_del(&atsru->list); |
| 4399 | intel_iommu_free_atsr(atsru); |
| 4400 | } |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4401 | } |
| 4402 | |
| 4403 | int dmar_find_matched_atsr_unit(struct pci_dev *dev) |
| 4404 | { |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 4405 | int i, ret = 1; |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4406 | struct pci_bus *bus; |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 4407 | struct pci_dev *bridge = NULL; |
| 4408 | struct device *tmp; |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4409 | struct acpi_dmar_atsr *atsr; |
| 4410 | struct dmar_atsr_unit *atsru; |
| 4411 | |
| 4412 | dev = pci_physfn(dev); |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4413 | for (bus = dev->bus; bus; bus = bus->parent) { |
Jiang Liu | b5f82dd | 2014-02-19 14:07:31 +0800 | [diff] [blame] | 4414 | bridge = bus->self; |
David Woodhouse | d14053b | 2015-10-15 09:28:06 +0100 | [diff] [blame] | 4415 | /* If it's an integrated device, allow ATS */ |
| 4416 | if (!bridge) |
| 4417 | return 1; |
| 4418 | /* Connected via non-PCIe: no ATS */ |
| 4419 | if (!pci_is_pcie(bridge) || |
Yijing Wang | 62f87c0 | 2012-07-24 17:20:03 +0800 | [diff] [blame] | 4420 | pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4421 | return 0; |
David Woodhouse | d14053b | 2015-10-15 09:28:06 +0100 | [diff] [blame] | 4422 | /* If we found the root port, look it up in the ATSR */ |
Jiang Liu | b5f82dd | 2014-02-19 14:07:31 +0800 | [diff] [blame] | 4423 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4424 | break; |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4425 | } |
| 4426 | |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 4427 | rcu_read_lock(); |
Jiang Liu | b5f82dd | 2014-02-19 14:07:31 +0800 | [diff] [blame] | 4428 | list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) { |
| 4429 | atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header); |
| 4430 | if (atsr->segment != pci_domain_nr(dev->bus)) |
| 4431 | continue; |
| 4432 | |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 4433 | for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp) |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 4434 | if (tmp == &bridge->dev) |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 4435 | goto out; |
Jiang Liu | b5f82dd | 2014-02-19 14:07:31 +0800 | [diff] [blame] | 4436 | |
| 4437 | if (atsru->include_all) |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 4438 | goto out; |
Jiang Liu | b5f82dd | 2014-02-19 14:07:31 +0800 | [diff] [blame] | 4439 | } |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 4440 | ret = 0; |
| 4441 | out: |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 4442 | rcu_read_unlock(); |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4443 | |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 4444 | return ret; |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4445 | } |
| 4446 | |
Jiang Liu | 59ce051 | 2014-02-19 14:07:35 +0800 | [diff] [blame] | 4447 | int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info) |
| 4448 | { |
| 4449 | int ret = 0; |
| 4450 | struct dmar_rmrr_unit *rmrru; |
| 4451 | struct dmar_atsr_unit *atsru; |
| 4452 | struct acpi_dmar_atsr *atsr; |
| 4453 | struct acpi_dmar_reserved_memory *rmrr; |
| 4454 | |
| 4455 | if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING) |
| 4456 | return 0; |
| 4457 | |
| 4458 | list_for_each_entry(rmrru, &dmar_rmrr_units, list) { |
| 4459 | rmrr = container_of(rmrru->hdr, |
| 4460 | struct acpi_dmar_reserved_memory, header); |
| 4461 | if (info->event == BUS_NOTIFY_ADD_DEVICE) { |
| 4462 | ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1), |
| 4463 | ((void *)rmrr) + rmrr->header.length, |
| 4464 | rmrr->segment, rmrru->devices, |
| 4465 | rmrru->devices_cnt); |
Jiang Liu | 27e2495 | 2014-06-20 15:08:06 +0800 | [diff] [blame] | 4466 | if(ret < 0) |
Jiang Liu | 59ce051 | 2014-02-19 14:07:35 +0800 | [diff] [blame] | 4467 | return ret; |
Joerg Roedel | e6a8c9b | 2016-02-29 23:49:47 +0100 | [diff] [blame] | 4468 | } else if (info->event == BUS_NOTIFY_REMOVED_DEVICE) { |
Jiang Liu | 27e2495 | 2014-06-20 15:08:06 +0800 | [diff] [blame] | 4469 | dmar_remove_dev_scope(info, rmrr->segment, |
| 4470 | rmrru->devices, rmrru->devices_cnt); |
Jiang Liu | 59ce051 | 2014-02-19 14:07:35 +0800 | [diff] [blame] | 4471 | } |
| 4472 | } |
| 4473 | |
| 4474 | list_for_each_entry(atsru, &dmar_atsr_units, list) { |
| 4475 | if (atsru->include_all) |
| 4476 | continue; |
| 4477 | |
| 4478 | atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header); |
| 4479 | if (info->event == BUS_NOTIFY_ADD_DEVICE) { |
| 4480 | ret = dmar_insert_dev_scope(info, (void *)(atsr + 1), |
| 4481 | (void *)atsr + atsr->header.length, |
| 4482 | atsr->segment, atsru->devices, |
| 4483 | atsru->devices_cnt); |
| 4484 | if (ret > 0) |
| 4485 | break; |
| 4486 | else if(ret < 0) |
| 4487 | return ret; |
Joerg Roedel | e6a8c9b | 2016-02-29 23:49:47 +0100 | [diff] [blame] | 4488 | } else if (info->event == BUS_NOTIFY_REMOVED_DEVICE) { |
Jiang Liu | 59ce051 | 2014-02-19 14:07:35 +0800 | [diff] [blame] | 4489 | if (dmar_remove_dev_scope(info, atsr->segment, |
| 4490 | atsru->devices, atsru->devices_cnt)) |
| 4491 | break; |
| 4492 | } |
| 4493 | } |
| 4494 | |
| 4495 | return 0; |
| 4496 | } |
| 4497 | |
Fenghua Yu | 99dcade | 2009-11-11 07:23:06 -0800 | [diff] [blame] | 4498 | /* |
| 4499 | * Here we only respond to action of unbound device from driver. |
| 4500 | * |
| 4501 | * Added device is not attached to its DMAR domain here yet. That will happen |
| 4502 | * when mapping the device to iova. |
| 4503 | */ |
| 4504 | static int device_notifier(struct notifier_block *nb, |
| 4505 | unsigned long action, void *data) |
| 4506 | { |
| 4507 | struct device *dev = data; |
Fenghua Yu | 99dcade | 2009-11-11 07:23:06 -0800 | [diff] [blame] | 4508 | struct dmar_domain *domain; |
| 4509 | |
David Woodhouse | 3d89194 | 2014-03-06 15:59:26 +0000 | [diff] [blame] | 4510 | if (iommu_dummy(dev)) |
David Woodhouse | 44cd613 | 2009-12-02 10:18:30 +0000 | [diff] [blame] | 4511 | return 0; |
| 4512 | |
Joerg Roedel | 1196c2f | 2014-09-30 13:02:03 +0200 | [diff] [blame] | 4513 | if (action != BUS_NOTIFY_REMOVED_DEVICE) |
Jiang Liu | 7e7dfab | 2014-02-19 14:07:23 +0800 | [diff] [blame] | 4514 | return 0; |
| 4515 | |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame] | 4516 | domain = find_domain(dev); |
Fenghua Yu | 99dcade | 2009-11-11 07:23:06 -0800 | [diff] [blame] | 4517 | if (!domain) |
| 4518 | return 0; |
| 4519 | |
Joerg Roedel | e6de0f8 | 2015-07-22 16:30:36 +0200 | [diff] [blame] | 4520 | dmar_remove_one_dev_info(domain, dev); |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 4521 | if (!domain_type_is_vm_or_si(domain) && list_empty(&domain->devices)) |
Jiang Liu | 7e7dfab | 2014-02-19 14:07:23 +0800 | [diff] [blame] | 4522 | domain_exit(domain); |
Alex Williamson | a97590e | 2011-03-04 14:52:16 -0700 | [diff] [blame] | 4523 | |
Fenghua Yu | 99dcade | 2009-11-11 07:23:06 -0800 | [diff] [blame] | 4524 | return 0; |
| 4525 | } |
| 4526 | |
| 4527 | static struct notifier_block device_nb = { |
| 4528 | .notifier_call = device_notifier, |
| 4529 | }; |
| 4530 | |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 4531 | static int intel_iommu_memory_notifier(struct notifier_block *nb, |
| 4532 | unsigned long val, void *v) |
| 4533 | { |
| 4534 | struct memory_notify *mhp = v; |
| 4535 | unsigned long long start, end; |
| 4536 | unsigned long start_vpfn, last_vpfn; |
| 4537 | |
| 4538 | switch (val) { |
| 4539 | case MEM_GOING_ONLINE: |
| 4540 | start = mhp->start_pfn << PAGE_SHIFT; |
| 4541 | end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1; |
| 4542 | if (iommu_domain_identity_map(si_domain, start, end)) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 4543 | pr_warn("Failed to build identity map for [%llx-%llx]\n", |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 4544 | start, end); |
| 4545 | return NOTIFY_BAD; |
| 4546 | } |
| 4547 | break; |
| 4548 | |
| 4549 | case MEM_OFFLINE: |
| 4550 | case MEM_CANCEL_ONLINE: |
| 4551 | start_vpfn = mm_to_dma_pfn(mhp->start_pfn); |
| 4552 | last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1); |
| 4553 | while (start_vpfn <= last_vpfn) { |
| 4554 | struct iova *iova; |
| 4555 | struct dmar_drhd_unit *drhd; |
| 4556 | struct intel_iommu *iommu; |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 4557 | struct page *freelist; |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 4558 | |
| 4559 | iova = find_iova(&si_domain->iovad, start_vpfn); |
| 4560 | if (iova == NULL) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 4561 | pr_debug("Failed get IOVA for PFN %lx\n", |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 4562 | start_vpfn); |
| 4563 | break; |
| 4564 | } |
| 4565 | |
| 4566 | iova = split_and_remove_iova(&si_domain->iovad, iova, |
| 4567 | start_vpfn, last_vpfn); |
| 4568 | if (iova == NULL) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 4569 | pr_warn("Failed to split IOVA PFN [%lx-%lx]\n", |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 4570 | start_vpfn, last_vpfn); |
| 4571 | return NOTIFY_BAD; |
| 4572 | } |
| 4573 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 4574 | freelist = domain_unmap(si_domain, iova->pfn_lo, |
| 4575 | iova->pfn_hi); |
| 4576 | |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 4577 | rcu_read_lock(); |
| 4578 | for_each_active_iommu(iommu, drhd) |
Joerg Roedel | a1ddcbe | 2015-07-21 15:20:32 +0200 | [diff] [blame] | 4579 | iommu_flush_iotlb_psi(iommu, si_domain, |
Jiang Liu | a156ef9 | 2014-07-11 14:19:36 +0800 | [diff] [blame] | 4580 | iova->pfn_lo, iova_size(iova), |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 4581 | !freelist, 0); |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 4582 | rcu_read_unlock(); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 4583 | dma_free_pagelist(freelist); |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 4584 | |
| 4585 | start_vpfn = iova->pfn_hi + 1; |
| 4586 | free_iova_mem(iova); |
| 4587 | } |
| 4588 | break; |
| 4589 | } |
| 4590 | |
| 4591 | return NOTIFY_OK; |
| 4592 | } |
| 4593 | |
| 4594 | static struct notifier_block intel_iommu_memory_nb = { |
| 4595 | .notifier_call = intel_iommu_memory_notifier, |
| 4596 | .priority = 0 |
| 4597 | }; |
| 4598 | |
Omer Peleg | 22e2f9f | 2016-04-20 11:34:11 +0300 | [diff] [blame] | 4599 | static void free_all_cpu_cached_iovas(unsigned int cpu) |
| 4600 | { |
| 4601 | int i; |
| 4602 | |
| 4603 | for (i = 0; i < g_num_of_iommus; i++) { |
| 4604 | struct intel_iommu *iommu = g_iommus[i]; |
| 4605 | struct dmar_domain *domain; |
Aaron Campbell | 0caa761 | 2016-07-02 21:23:24 -0300 | [diff] [blame] | 4606 | int did; |
Omer Peleg | 22e2f9f | 2016-04-20 11:34:11 +0300 | [diff] [blame] | 4607 | |
| 4608 | if (!iommu) |
| 4609 | continue; |
| 4610 | |
Jan Niehusmann | 3bd4f91 | 2016-06-06 14:20:11 +0200 | [diff] [blame] | 4611 | for (did = 0; did < cap_ndoms(iommu->cap); did++) { |
Aaron Campbell | 0caa761 | 2016-07-02 21:23:24 -0300 | [diff] [blame] | 4612 | domain = get_iommu_domain(iommu, (u16)did); |
Omer Peleg | 22e2f9f | 2016-04-20 11:34:11 +0300 | [diff] [blame] | 4613 | |
| 4614 | if (!domain) |
| 4615 | continue; |
| 4616 | free_cpu_cached_iovas(cpu, &domain->iovad); |
| 4617 | } |
| 4618 | } |
| 4619 | } |
| 4620 | |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 4621 | static int intel_iommu_cpu_notifier(struct notifier_block *nfb, |
| 4622 | unsigned long action, void *v) |
| 4623 | { |
| 4624 | unsigned int cpu = (unsigned long)v; |
| 4625 | |
| 4626 | switch (action) { |
| 4627 | case CPU_DEAD: |
| 4628 | case CPU_DEAD_FROZEN: |
Omer Peleg | 22e2f9f | 2016-04-20 11:34:11 +0300 | [diff] [blame] | 4629 | free_all_cpu_cached_iovas(cpu); |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 4630 | flush_unmaps_timeout(cpu); |
| 4631 | break; |
| 4632 | } |
| 4633 | return NOTIFY_OK; |
| 4634 | } |
| 4635 | |
| 4636 | static struct notifier_block intel_iommu_cpu_nb = { |
| 4637 | .notifier_call = intel_iommu_cpu_notifier, |
| 4638 | }; |
Alex Williamson | a5459cf | 2014-06-12 16:12:31 -0600 | [diff] [blame] | 4639 | |
| 4640 | static ssize_t intel_iommu_show_version(struct device *dev, |
| 4641 | struct device_attribute *attr, |
| 4642 | char *buf) |
| 4643 | { |
| 4644 | struct intel_iommu *iommu = dev_get_drvdata(dev); |
| 4645 | u32 ver = readl(iommu->reg + DMAR_VER_REG); |
| 4646 | return sprintf(buf, "%d:%d\n", |
| 4647 | DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver)); |
| 4648 | } |
| 4649 | static DEVICE_ATTR(version, S_IRUGO, intel_iommu_show_version, NULL); |
| 4650 | |
| 4651 | static ssize_t intel_iommu_show_address(struct device *dev, |
| 4652 | struct device_attribute *attr, |
| 4653 | char *buf) |
| 4654 | { |
| 4655 | struct intel_iommu *iommu = dev_get_drvdata(dev); |
| 4656 | return sprintf(buf, "%llx\n", iommu->reg_phys); |
| 4657 | } |
| 4658 | static DEVICE_ATTR(address, S_IRUGO, intel_iommu_show_address, NULL); |
| 4659 | |
| 4660 | static ssize_t intel_iommu_show_cap(struct device *dev, |
| 4661 | struct device_attribute *attr, |
| 4662 | char *buf) |
| 4663 | { |
| 4664 | struct intel_iommu *iommu = dev_get_drvdata(dev); |
| 4665 | return sprintf(buf, "%llx\n", iommu->cap); |
| 4666 | } |
| 4667 | static DEVICE_ATTR(cap, S_IRUGO, intel_iommu_show_cap, NULL); |
| 4668 | |
| 4669 | static ssize_t intel_iommu_show_ecap(struct device *dev, |
| 4670 | struct device_attribute *attr, |
| 4671 | char *buf) |
| 4672 | { |
| 4673 | struct intel_iommu *iommu = dev_get_drvdata(dev); |
| 4674 | return sprintf(buf, "%llx\n", iommu->ecap); |
| 4675 | } |
| 4676 | static DEVICE_ATTR(ecap, S_IRUGO, intel_iommu_show_ecap, NULL); |
| 4677 | |
Alex Williamson | 2238c08 | 2015-07-14 15:24:53 -0600 | [diff] [blame] | 4678 | static ssize_t intel_iommu_show_ndoms(struct device *dev, |
| 4679 | struct device_attribute *attr, |
| 4680 | char *buf) |
| 4681 | { |
| 4682 | struct intel_iommu *iommu = dev_get_drvdata(dev); |
| 4683 | return sprintf(buf, "%ld\n", cap_ndoms(iommu->cap)); |
| 4684 | } |
| 4685 | static DEVICE_ATTR(domains_supported, S_IRUGO, intel_iommu_show_ndoms, NULL); |
| 4686 | |
| 4687 | static ssize_t intel_iommu_show_ndoms_used(struct device *dev, |
| 4688 | struct device_attribute *attr, |
| 4689 | char *buf) |
| 4690 | { |
| 4691 | struct intel_iommu *iommu = dev_get_drvdata(dev); |
| 4692 | return sprintf(buf, "%d\n", bitmap_weight(iommu->domain_ids, |
| 4693 | cap_ndoms(iommu->cap))); |
| 4694 | } |
| 4695 | static DEVICE_ATTR(domains_used, S_IRUGO, intel_iommu_show_ndoms_used, NULL); |
| 4696 | |
Alex Williamson | a5459cf | 2014-06-12 16:12:31 -0600 | [diff] [blame] | 4697 | static struct attribute *intel_iommu_attrs[] = { |
| 4698 | &dev_attr_version.attr, |
| 4699 | &dev_attr_address.attr, |
| 4700 | &dev_attr_cap.attr, |
| 4701 | &dev_attr_ecap.attr, |
Alex Williamson | 2238c08 | 2015-07-14 15:24:53 -0600 | [diff] [blame] | 4702 | &dev_attr_domains_supported.attr, |
| 4703 | &dev_attr_domains_used.attr, |
Alex Williamson | a5459cf | 2014-06-12 16:12:31 -0600 | [diff] [blame] | 4704 | NULL, |
| 4705 | }; |
| 4706 | |
| 4707 | static struct attribute_group intel_iommu_group = { |
| 4708 | .name = "intel-iommu", |
| 4709 | .attrs = intel_iommu_attrs, |
| 4710 | }; |
| 4711 | |
| 4712 | const struct attribute_group *intel_iommu_groups[] = { |
| 4713 | &intel_iommu_group, |
| 4714 | NULL, |
| 4715 | }; |
| 4716 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4717 | int __init intel_iommu_init(void) |
| 4718 | { |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4719 | int ret = -ENODEV; |
Takao Indoh | 3a93c84 | 2013-04-23 17:35:03 +0900 | [diff] [blame] | 4720 | struct dmar_drhd_unit *drhd; |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 4721 | struct intel_iommu *iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4722 | |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 4723 | /* VT-d is required for a TXT/tboot launch, so enforce that */ |
| 4724 | force_on = tboot_force_iommu(); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4725 | |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 4726 | if (iommu_init_mempool()) { |
| 4727 | if (force_on) |
| 4728 | panic("tboot: Failed to initialize iommu memory\n"); |
| 4729 | return -ENOMEM; |
| 4730 | } |
| 4731 | |
| 4732 | down_write(&dmar_global_lock); |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 4733 | if (dmar_table_init()) { |
| 4734 | if (force_on) |
| 4735 | panic("tboot: Failed to initialize DMAR table\n"); |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4736 | goto out_free_dmar; |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 4737 | } |
| 4738 | |
Suresh Siddha | c2c7286 | 2011-08-23 17:05:19 -0700 | [diff] [blame] | 4739 | if (dmar_dev_scope_init() < 0) { |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 4740 | if (force_on) |
| 4741 | panic("tboot: Failed to initialize DMAR device scope\n"); |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4742 | goto out_free_dmar; |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 4743 | } |
Suresh Siddha | 1886e8a | 2008-07-10 11:16:37 -0700 | [diff] [blame] | 4744 | |
FUJITA Tomonori | 75f1cdf | 2009-11-10 19:46:20 +0900 | [diff] [blame] | 4745 | if (no_iommu || dmar_disabled) |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4746 | goto out_free_dmar; |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 4747 | |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4748 | if (list_empty(&dmar_rmrr_units)) |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 4749 | pr_info("No RMRR found\n"); |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4750 | |
| 4751 | if (list_empty(&dmar_atsr_units)) |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 4752 | pr_info("No ATSR found\n"); |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4753 | |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 4754 | if (dmar_init_reserved_ranges()) { |
| 4755 | if (force_on) |
| 4756 | panic("tboot: Failed to reserve iommu ranges\n"); |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 4757 | goto out_free_reserved_range; |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 4758 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4759 | |
| 4760 | init_no_remapping_devices(); |
| 4761 | |
Joseph Cihula | b779260 | 2011-05-03 00:08:37 -0700 | [diff] [blame] | 4762 | ret = init_dmars(); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4763 | if (ret) { |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 4764 | if (force_on) |
| 4765 | panic("tboot: Failed to initialize DMARs\n"); |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 4766 | pr_err("Initialization failed\n"); |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4767 | goto out_free_reserved_range; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4768 | } |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 4769 | up_write(&dmar_global_lock); |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 4770 | pr_info("Intel(R) Virtualization Technology for Directed I/O\n"); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4771 | |
FUJITA Tomonori | 75f1cdf | 2009-11-10 19:46:20 +0900 | [diff] [blame] | 4772 | #ifdef CONFIG_SWIOTLB |
| 4773 | swiotlb = 0; |
| 4774 | #endif |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 4775 | dma_ops = &intel_dma_ops; |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 4776 | |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 4777 | init_iommu_pm_ops(); |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 4778 | |
Alex Williamson | a5459cf | 2014-06-12 16:12:31 -0600 | [diff] [blame] | 4779 | for_each_active_iommu(iommu, drhd) |
| 4780 | iommu->iommu_dev = iommu_device_create(NULL, iommu, |
| 4781 | intel_iommu_groups, |
Kees Cook | 2439d4a | 2015-07-24 16:27:57 -0700 | [diff] [blame] | 4782 | "%s", iommu->name); |
Alex Williamson | a5459cf | 2014-06-12 16:12:31 -0600 | [diff] [blame] | 4783 | |
Joerg Roedel | 4236d97d | 2011-09-06 17:56:07 +0200 | [diff] [blame] | 4784 | bus_set_iommu(&pci_bus_type, &intel_iommu_ops); |
Fenghua Yu | 99dcade | 2009-11-11 07:23:06 -0800 | [diff] [blame] | 4785 | bus_register_notifier(&pci_bus_type, &device_nb); |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 4786 | if (si_domain && !hw_pass_through) |
| 4787 | register_memory_notifier(&intel_iommu_memory_nb); |
Omer Peleg | aa47324 | 2016-04-20 11:33:02 +0300 | [diff] [blame] | 4788 | register_hotcpu_notifier(&intel_iommu_cpu_nb); |
Fenghua Yu | 99dcade | 2009-11-11 07:23:06 -0800 | [diff] [blame] | 4789 | |
Eugeni Dodonov | 8bc1f85 | 2011-11-23 16:42:14 -0200 | [diff] [blame] | 4790 | intel_iommu_enabled = 1; |
| 4791 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4792 | return 0; |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4793 | |
| 4794 | out_free_reserved_range: |
| 4795 | put_iova_domain(&reserved_iova_list); |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4796 | out_free_dmar: |
| 4797 | intel_iommu_free_dmars(); |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 4798 | up_write(&dmar_global_lock); |
| 4799 | iommu_exit_mempool(); |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4800 | return ret; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4801 | } |
Keshavamurthy, Anil S | e820482 | 2007-10-21 16:41:55 -0700 | [diff] [blame] | 4802 | |
Joerg Roedel | 2452d9d | 2015-07-23 16:20:14 +0200 | [diff] [blame] | 4803 | static int domain_context_clear_one_cb(struct pci_dev *pdev, u16 alias, void *opaque) |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 4804 | { |
| 4805 | struct intel_iommu *iommu = opaque; |
| 4806 | |
Joerg Roedel | 2452d9d | 2015-07-23 16:20:14 +0200 | [diff] [blame] | 4807 | domain_context_clear_one(iommu, PCI_BUS_NUM(alias), alias & 0xff); |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 4808 | return 0; |
| 4809 | } |
| 4810 | |
| 4811 | /* |
| 4812 | * NB - intel-iommu lacks any sort of reference counting for the users of |
| 4813 | * dependent devices. If multiple endpoints have intersecting dependent |
| 4814 | * devices, unbinding the driver from any one of them will possibly leave |
| 4815 | * the others unable to operate. |
| 4816 | */ |
Joerg Roedel | 2452d9d | 2015-07-23 16:20:14 +0200 | [diff] [blame] | 4817 | static void domain_context_clear(struct intel_iommu *iommu, struct device *dev) |
Han, Weidong | 3199aa6 | 2009-02-26 17:31:12 +0800 | [diff] [blame] | 4818 | { |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 4819 | if (!iommu || !dev || !dev_is_pci(dev)) |
Han, Weidong | 3199aa6 | 2009-02-26 17:31:12 +0800 | [diff] [blame] | 4820 | return; |
| 4821 | |
Joerg Roedel | 2452d9d | 2015-07-23 16:20:14 +0200 | [diff] [blame] | 4822 | pci_for_each_dma_alias(to_pci_dev(dev), &domain_context_clear_one_cb, iommu); |
Han, Weidong | 3199aa6 | 2009-02-26 17:31:12 +0800 | [diff] [blame] | 4823 | } |
| 4824 | |
Joerg Roedel | 127c761 | 2015-07-23 17:44:46 +0200 | [diff] [blame] | 4825 | static void __dmar_remove_one_dev_info(struct device_domain_info *info) |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4826 | { |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4827 | struct intel_iommu *iommu; |
| 4828 | unsigned long flags; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4829 | |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 4830 | assert_spin_locked(&device_domain_lock); |
| 4831 | |
Joerg Roedel | b608ac3 | 2015-07-21 18:19:08 +0200 | [diff] [blame] | 4832 | if (WARN_ON(!info)) |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4833 | return; |
| 4834 | |
Joerg Roedel | 127c761 | 2015-07-23 17:44:46 +0200 | [diff] [blame] | 4835 | iommu = info->iommu; |
| 4836 | |
| 4837 | if (info->dev) { |
| 4838 | iommu_disable_dev_iotlb(info); |
| 4839 | domain_context_clear(iommu, info->dev); |
| 4840 | } |
| 4841 | |
Joerg Roedel | b608ac3 | 2015-07-21 18:19:08 +0200 | [diff] [blame] | 4842 | unlink_domain_info(info); |
Roland Dreier | 3e7abe2 | 2011-07-20 06:22:21 -0700 | [diff] [blame] | 4843 | |
Joerg Roedel | d160aca | 2015-07-22 11:52:53 +0200 | [diff] [blame] | 4844 | spin_lock_irqsave(&iommu->lock, flags); |
Joerg Roedel | 127c761 | 2015-07-23 17:44:46 +0200 | [diff] [blame] | 4845 | domain_detach_iommu(info->domain, iommu); |
Joerg Roedel | d160aca | 2015-07-22 11:52:53 +0200 | [diff] [blame] | 4846 | spin_unlock_irqrestore(&iommu->lock, flags); |
Joerg Roedel | 127c761 | 2015-07-23 17:44:46 +0200 | [diff] [blame] | 4847 | |
| 4848 | free_devinfo_mem(info); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4849 | } |
| 4850 | |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 4851 | static void dmar_remove_one_dev_info(struct dmar_domain *domain, |
| 4852 | struct device *dev) |
| 4853 | { |
Joerg Roedel | 127c761 | 2015-07-23 17:44:46 +0200 | [diff] [blame] | 4854 | struct device_domain_info *info; |
Joerg Roedel | 55d9404 | 2015-07-22 16:50:40 +0200 | [diff] [blame] | 4855 | unsigned long flags; |
| 4856 | |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4857 | spin_lock_irqsave(&device_domain_lock, flags); |
Joerg Roedel | 127c761 | 2015-07-23 17:44:46 +0200 | [diff] [blame] | 4858 | info = dev->archdata.iommu; |
| 4859 | __dmar_remove_one_dev_info(info); |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 4860 | spin_unlock_irqrestore(&device_domain_lock, flags); |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 4861 | } |
| 4862 | |
| 4863 | static int md_domain_init(struct dmar_domain *domain, int guest_width) |
| 4864 | { |
| 4865 | int adjust_width; |
| 4866 | |
Robin Murphy | 0fb5fe8 | 2015-01-12 17:51:16 +0000 | [diff] [blame] | 4867 | init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN, |
| 4868 | DMA_32BIT_PFN); |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 4869 | domain_reserve_special_ranges(domain); |
| 4870 | |
| 4871 | /* calculate AGAW */ |
| 4872 | domain->gaw = guest_width; |
| 4873 | adjust_width = guestwidth_to_adjustwidth(guest_width); |
| 4874 | domain->agaw = width_to_agaw(adjust_width); |
| 4875 | |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 4876 | domain->iommu_coherency = 0; |
Sheng Yang | c5b1525 | 2009-08-06 13:31:56 +0800 | [diff] [blame] | 4877 | domain->iommu_snooping = 0; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 4878 | domain->iommu_superpage = 0; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4879 | domain->max_addr = 0; |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 4880 | |
| 4881 | /* always allocate the top pgd */ |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 4882 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid); |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 4883 | if (!domain->pgd) |
| 4884 | return -ENOMEM; |
| 4885 | domain_flush_cache(domain, domain->pgd, PAGE_SIZE); |
| 4886 | return 0; |
| 4887 | } |
| 4888 | |
Joerg Roedel | 00a77de | 2015-03-26 13:43:08 +0100 | [diff] [blame] | 4889 | static struct iommu_domain *intel_iommu_domain_alloc(unsigned type) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4890 | { |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4891 | struct dmar_domain *dmar_domain; |
Joerg Roedel | 00a77de | 2015-03-26 13:43:08 +0100 | [diff] [blame] | 4892 | struct iommu_domain *domain; |
| 4893 | |
| 4894 | if (type != IOMMU_DOMAIN_UNMANAGED) |
| 4895 | return NULL; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4896 | |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 4897 | dmar_domain = alloc_domain(DOMAIN_FLAG_VIRTUAL_MACHINE); |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4898 | if (!dmar_domain) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 4899 | pr_err("Can't allocate dmar_domain\n"); |
Joerg Roedel | 00a77de | 2015-03-26 13:43:08 +0100 | [diff] [blame] | 4900 | return NULL; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4901 | } |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 4902 | if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 4903 | pr_err("Domain initialization failed\n"); |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 4904 | domain_exit(dmar_domain); |
Joerg Roedel | 00a77de | 2015-03-26 13:43:08 +0100 | [diff] [blame] | 4905 | return NULL; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4906 | } |
Allen Kay | 8140a95 | 2011-10-14 12:32:17 -0700 | [diff] [blame] | 4907 | domain_update_iommu_cap(dmar_domain); |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4908 | |
Joerg Roedel | 00a77de | 2015-03-26 13:43:08 +0100 | [diff] [blame] | 4909 | domain = &dmar_domain->domain; |
Joerg Roedel | 8a0e715 | 2012-01-26 19:40:54 +0100 | [diff] [blame] | 4910 | domain->geometry.aperture_start = 0; |
| 4911 | domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw); |
| 4912 | domain->geometry.force_aperture = true; |
| 4913 | |
Joerg Roedel | 00a77de | 2015-03-26 13:43:08 +0100 | [diff] [blame] | 4914 | return domain; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4915 | } |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4916 | |
Joerg Roedel | 00a77de | 2015-03-26 13:43:08 +0100 | [diff] [blame] | 4917 | static void intel_iommu_domain_free(struct iommu_domain *domain) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4918 | { |
Joerg Roedel | 00a77de | 2015-03-26 13:43:08 +0100 | [diff] [blame] | 4919 | domain_exit(to_dmar_domain(domain)); |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4920 | } |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4921 | |
Joerg Roedel | 4c5478c | 2008-12-03 14:58:24 +0100 | [diff] [blame] | 4922 | static int intel_iommu_attach_device(struct iommu_domain *domain, |
| 4923 | struct device *dev) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4924 | { |
Joerg Roedel | 00a77de | 2015-03-26 13:43:08 +0100 | [diff] [blame] | 4925 | struct dmar_domain *dmar_domain = to_dmar_domain(domain); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4926 | struct intel_iommu *iommu; |
| 4927 | int addr_width; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 4928 | u8 bus, devfn; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4929 | |
Alex Williamson | c875d2c | 2014-07-03 09:57:02 -0600 | [diff] [blame] | 4930 | if (device_is_rmrr_locked(dev)) { |
| 4931 | dev_warn(dev, "Device is ineligible for IOMMU domain attach due to platform RMRR requirement. Contact your platform vendor.\n"); |
| 4932 | return -EPERM; |
| 4933 | } |
| 4934 | |
David Woodhouse | 7207d8f | 2014-03-09 16:31:06 -0700 | [diff] [blame] | 4935 | /* normally dev is not mapped */ |
| 4936 | if (unlikely(domain_context_mapped(dev))) { |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4937 | struct dmar_domain *old_domain; |
| 4938 | |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame] | 4939 | old_domain = find_domain(dev); |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4940 | if (old_domain) { |
Joerg Roedel | d160aca | 2015-07-22 11:52:53 +0200 | [diff] [blame] | 4941 | rcu_read_lock(); |
Joerg Roedel | de7e888 | 2015-07-22 11:58:07 +0200 | [diff] [blame] | 4942 | dmar_remove_one_dev_info(old_domain, dev); |
Joerg Roedel | d160aca | 2015-07-22 11:52:53 +0200 | [diff] [blame] | 4943 | rcu_read_unlock(); |
Joerg Roedel | 62c2216 | 2014-12-09 12:56:45 +0100 | [diff] [blame] | 4944 | |
| 4945 | if (!domain_type_is_vm_or_si(old_domain) && |
| 4946 | list_empty(&old_domain->devices)) |
| 4947 | domain_exit(old_domain); |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4948 | } |
| 4949 | } |
| 4950 | |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 4951 | iommu = device_to_iommu(dev, &bus, &devfn); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4952 | if (!iommu) |
| 4953 | return -ENODEV; |
| 4954 | |
| 4955 | /* check if this iommu agaw is sufficient for max mapped address */ |
| 4956 | addr_width = agaw_to_width(iommu->agaw); |
Tom Lyon | a99c47a | 2010-05-17 08:20:45 +0100 | [diff] [blame] | 4957 | if (addr_width > cap_mgaw(iommu->cap)) |
| 4958 | addr_width = cap_mgaw(iommu->cap); |
| 4959 | |
| 4960 | if (dmar_domain->max_addr > (1LL << addr_width)) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 4961 | pr_err("%s: iommu width (%d) is not " |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4962 | "sufficient for the mapped address (%llx)\n", |
Tom Lyon | a99c47a | 2010-05-17 08:20:45 +0100 | [diff] [blame] | 4963 | __func__, addr_width, dmar_domain->max_addr); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4964 | return -EFAULT; |
| 4965 | } |
Tom Lyon | a99c47a | 2010-05-17 08:20:45 +0100 | [diff] [blame] | 4966 | dmar_domain->gaw = addr_width; |
| 4967 | |
| 4968 | /* |
| 4969 | * Knock out extra levels of page tables if necessary |
| 4970 | */ |
| 4971 | while (iommu->agaw < dmar_domain->agaw) { |
| 4972 | struct dma_pte *pte; |
| 4973 | |
| 4974 | pte = dmar_domain->pgd; |
| 4975 | if (dma_pte_present(pte)) { |
Sheng Yang | 25cbff1 | 2010-06-12 19:21:42 +0800 | [diff] [blame] | 4976 | dmar_domain->pgd = (struct dma_pte *) |
| 4977 | phys_to_virt(dma_pte_addr(pte)); |
Jan Kiszka | 7a66101 | 2010-11-02 08:05:51 +0100 | [diff] [blame] | 4978 | free_pgtable_page(pte); |
Tom Lyon | a99c47a | 2010-05-17 08:20:45 +0100 | [diff] [blame] | 4979 | } |
| 4980 | dmar_domain->agaw--; |
| 4981 | } |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4982 | |
Joerg Roedel | 28ccce0 | 2015-07-21 14:45:31 +0200 | [diff] [blame] | 4983 | return domain_add_dev_info(dmar_domain, dev); |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4984 | } |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4985 | |
Joerg Roedel | 4c5478c | 2008-12-03 14:58:24 +0100 | [diff] [blame] | 4986 | static void intel_iommu_detach_device(struct iommu_domain *domain, |
| 4987 | struct device *dev) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4988 | { |
Joerg Roedel | e6de0f8 | 2015-07-22 16:30:36 +0200 | [diff] [blame] | 4989 | dmar_remove_one_dev_info(to_dmar_domain(domain), dev); |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4990 | } |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4991 | |
Joerg Roedel | b146a1c9f | 2010-01-20 17:17:37 +0100 | [diff] [blame] | 4992 | static int intel_iommu_map(struct iommu_domain *domain, |
| 4993 | unsigned long iova, phys_addr_t hpa, |
Ohad Ben-Cohen | 5009065 | 2011-11-10 11:32:25 +0200 | [diff] [blame] | 4994 | size_t size, int iommu_prot) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4995 | { |
Joerg Roedel | 00a77de | 2015-03-26 13:43:08 +0100 | [diff] [blame] | 4996 | struct dmar_domain *dmar_domain = to_dmar_domain(domain); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4997 | u64 max_addr; |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 4998 | int prot = 0; |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4999 | int ret; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 5000 | |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 5001 | if (iommu_prot & IOMMU_READ) |
| 5002 | prot |= DMA_PTE_READ; |
| 5003 | if (iommu_prot & IOMMU_WRITE) |
| 5004 | prot |= DMA_PTE_WRITE; |
Sheng Yang | 9cf06697 | 2009-03-18 15:33:07 +0800 | [diff] [blame] | 5005 | if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping) |
| 5006 | prot |= DMA_PTE_SNP; |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 5007 | |
David Woodhouse | 163cc52 | 2009-06-28 00:51:17 +0100 | [diff] [blame] | 5008 | max_addr = iova + size; |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 5009 | if (dmar_domain->max_addr < max_addr) { |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 5010 | u64 end; |
| 5011 | |
| 5012 | /* check if minimum agaw is sufficient for mapped address */ |
Tom Lyon | 8954da1 | 2010-05-17 08:19:52 +0100 | [diff] [blame] | 5013 | end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 5014 | if (end < max_addr) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 5015 | pr_err("%s: iommu width (%d) is not " |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 5016 | "sufficient for the mapped address (%llx)\n", |
Tom Lyon | 8954da1 | 2010-05-17 08:19:52 +0100 | [diff] [blame] | 5017 | __func__, dmar_domain->gaw, max_addr); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 5018 | return -EFAULT; |
| 5019 | } |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 5020 | dmar_domain->max_addr = max_addr; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 5021 | } |
David Woodhouse | ad05122 | 2009-06-28 14:22:28 +0100 | [diff] [blame] | 5022 | /* Round up size to next multiple of PAGE_SIZE, if it and |
| 5023 | the low bits of hpa would take us onto the next page */ |
David Woodhouse | 88cb6a7 | 2009-06-28 15:03:06 +0100 | [diff] [blame] | 5024 | size = aligned_nrpages(hpa, size); |
David Woodhouse | ad05122 | 2009-06-28 14:22:28 +0100 | [diff] [blame] | 5025 | ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT, |
| 5026 | hpa >> VTD_PAGE_SHIFT, size, prot); |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 5027 | return ret; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 5028 | } |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 5029 | |
Ohad Ben-Cohen | 5009065 | 2011-11-10 11:32:25 +0200 | [diff] [blame] | 5030 | static size_t intel_iommu_unmap(struct iommu_domain *domain, |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 5031 | unsigned long iova, size_t size) |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 5032 | { |
Joerg Roedel | 00a77de | 2015-03-26 13:43:08 +0100 | [diff] [blame] | 5033 | struct dmar_domain *dmar_domain = to_dmar_domain(domain); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 5034 | struct page *freelist = NULL; |
| 5035 | struct intel_iommu *iommu; |
| 5036 | unsigned long start_pfn, last_pfn; |
| 5037 | unsigned int npages; |
Joerg Roedel | 42e8c18 | 2015-07-21 15:50:02 +0200 | [diff] [blame] | 5038 | int iommu_id, level = 0; |
Sheng Yang | 4b99d35 | 2009-07-08 11:52:52 +0100 | [diff] [blame] | 5039 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 5040 | /* Cope with horrid API which requires us to unmap more than the |
| 5041 | size argument if it happens to be a large-page mapping. */ |
Joerg Roedel | dc02e46 | 2015-08-13 11:15:13 +0200 | [diff] [blame] | 5042 | BUG_ON(!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level)); |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 5043 | |
| 5044 | if (size < VTD_PAGE_SIZE << level_to_offset_bits(level)) |
| 5045 | size = VTD_PAGE_SIZE << level_to_offset_bits(level); |
| 5046 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 5047 | start_pfn = iova >> VTD_PAGE_SHIFT; |
| 5048 | last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT; |
| 5049 | |
| 5050 | freelist = domain_unmap(dmar_domain, start_pfn, last_pfn); |
| 5051 | |
| 5052 | npages = last_pfn - start_pfn + 1; |
| 5053 | |
Joerg Roedel | 29a2771 | 2015-07-21 17:17:12 +0200 | [diff] [blame] | 5054 | for_each_domain_iommu(iommu_id, dmar_domain) { |
Joerg Roedel | a1ddcbe | 2015-07-21 15:20:32 +0200 | [diff] [blame] | 5055 | iommu = g_iommus[iommu_id]; |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 5056 | |
Joerg Roedel | 42e8c18 | 2015-07-21 15:50:02 +0200 | [diff] [blame] | 5057 | iommu_flush_iotlb_psi(g_iommus[iommu_id], dmar_domain, |
| 5058 | start_pfn, npages, !freelist, 0); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 5059 | } |
| 5060 | |
| 5061 | dma_free_pagelist(freelist); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 5062 | |
David Woodhouse | 163cc52 | 2009-06-28 00:51:17 +0100 | [diff] [blame] | 5063 | if (dmar_domain->max_addr == iova + size) |
| 5064 | dmar_domain->max_addr = iova; |
Joerg Roedel | b146a1c9f | 2010-01-20 17:17:37 +0100 | [diff] [blame] | 5065 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 5066 | return size; |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 5067 | } |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 5068 | |
Joerg Roedel | d14d657 | 2008-12-03 15:06:57 +0100 | [diff] [blame] | 5069 | static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain, |
Varun Sethi | bb5547ac | 2013-03-29 01:23:58 +0530 | [diff] [blame] | 5070 | dma_addr_t iova) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 5071 | { |
Joerg Roedel | 00a77de | 2015-03-26 13:43:08 +0100 | [diff] [blame] | 5072 | struct dmar_domain *dmar_domain = to_dmar_domain(domain); |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 5073 | struct dma_pte *pte; |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 5074 | int level = 0; |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 5075 | u64 phys = 0; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 5076 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 5077 | pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level); |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 5078 | if (pte) |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 5079 | phys = dma_pte_addr(pte); |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 5080 | |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 5081 | return phys; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 5082 | } |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 5083 | |
Joerg Roedel | 5d587b8 | 2014-09-05 10:50:45 +0200 | [diff] [blame] | 5084 | static bool intel_iommu_capable(enum iommu_cap cap) |
Sheng Yang | dbb9fd8 | 2009-03-18 15:33:06 +0800 | [diff] [blame] | 5085 | { |
Sheng Yang | dbb9fd8 | 2009-03-18 15:33:06 +0800 | [diff] [blame] | 5086 | if (cap == IOMMU_CAP_CACHE_COHERENCY) |
Joerg Roedel | 5d587b8 | 2014-09-05 10:50:45 +0200 | [diff] [blame] | 5087 | return domain_update_iommu_snooping(NULL) == 1; |
Tom Lyon | 323f99c | 2010-07-02 16:56:14 -0400 | [diff] [blame] | 5088 | if (cap == IOMMU_CAP_INTR_REMAP) |
Joerg Roedel | 5d587b8 | 2014-09-05 10:50:45 +0200 | [diff] [blame] | 5089 | return irq_remapping_enabled == 1; |
Sheng Yang | dbb9fd8 | 2009-03-18 15:33:06 +0800 | [diff] [blame] | 5090 | |
Joerg Roedel | 5d587b8 | 2014-09-05 10:50:45 +0200 | [diff] [blame] | 5091 | return false; |
Sheng Yang | dbb9fd8 | 2009-03-18 15:33:06 +0800 | [diff] [blame] | 5092 | } |
| 5093 | |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 5094 | static int intel_iommu_add_device(struct device *dev) |
Alex Williamson | 70ae6f0 | 2011-10-21 15:56:11 -0400 | [diff] [blame] | 5095 | { |
Alex Williamson | a5459cf | 2014-06-12 16:12:31 -0600 | [diff] [blame] | 5096 | struct intel_iommu *iommu; |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 5097 | struct iommu_group *group; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 5098 | u8 bus, devfn; |
Alex Williamson | 70ae6f0 | 2011-10-21 15:56:11 -0400 | [diff] [blame] | 5099 | |
Alex Williamson | a5459cf | 2014-06-12 16:12:31 -0600 | [diff] [blame] | 5100 | iommu = device_to_iommu(dev, &bus, &devfn); |
| 5101 | if (!iommu) |
Alex Williamson | 70ae6f0 | 2011-10-21 15:56:11 -0400 | [diff] [blame] | 5102 | return -ENODEV; |
| 5103 | |
Alex Williamson | a5459cf | 2014-06-12 16:12:31 -0600 | [diff] [blame] | 5104 | iommu_device_link(iommu->iommu_dev, dev); |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 5105 | |
Alex Williamson | e17f9ff | 2014-07-03 09:51:37 -0600 | [diff] [blame] | 5106 | group = iommu_group_get_for_dev(dev); |
Alex Williamson | 783f157 | 2012-05-30 14:19:43 -0600 | [diff] [blame] | 5107 | |
Alex Williamson | e17f9ff | 2014-07-03 09:51:37 -0600 | [diff] [blame] | 5108 | if (IS_ERR(group)) |
| 5109 | return PTR_ERR(group); |
Alex Williamson | 70ae6f0 | 2011-10-21 15:56:11 -0400 | [diff] [blame] | 5110 | |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 5111 | iommu_group_put(group); |
Alex Williamson | e17f9ff | 2014-07-03 09:51:37 -0600 | [diff] [blame] | 5112 | return 0; |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 5113 | } |
| 5114 | |
| 5115 | static void intel_iommu_remove_device(struct device *dev) |
| 5116 | { |
Alex Williamson | a5459cf | 2014-06-12 16:12:31 -0600 | [diff] [blame] | 5117 | struct intel_iommu *iommu; |
| 5118 | u8 bus, devfn; |
| 5119 | |
| 5120 | iommu = device_to_iommu(dev, &bus, &devfn); |
| 5121 | if (!iommu) |
| 5122 | return; |
| 5123 | |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 5124 | iommu_group_remove_device(dev); |
Alex Williamson | a5459cf | 2014-06-12 16:12:31 -0600 | [diff] [blame] | 5125 | |
| 5126 | iommu_device_unlink(iommu->iommu_dev, dev); |
Alex Williamson | 70ae6f0 | 2011-10-21 15:56:11 -0400 | [diff] [blame] | 5127 | } |
| 5128 | |
David Woodhouse | 2f26e0a | 2015-09-09 11:40:47 +0100 | [diff] [blame] | 5129 | #ifdef CONFIG_INTEL_IOMMU_SVM |
| 5130 | int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdev) |
| 5131 | { |
| 5132 | struct device_domain_info *info; |
| 5133 | struct context_entry *context; |
| 5134 | struct dmar_domain *domain; |
| 5135 | unsigned long flags; |
| 5136 | u64 ctx_lo; |
| 5137 | int ret; |
| 5138 | |
| 5139 | domain = get_valid_domain_for_dev(sdev->dev); |
| 5140 | if (!domain) |
| 5141 | return -EINVAL; |
| 5142 | |
| 5143 | spin_lock_irqsave(&device_domain_lock, flags); |
| 5144 | spin_lock(&iommu->lock); |
| 5145 | |
| 5146 | ret = -EINVAL; |
| 5147 | info = sdev->dev->archdata.iommu; |
| 5148 | if (!info || !info->pasid_supported) |
| 5149 | goto out; |
| 5150 | |
| 5151 | context = iommu_context_addr(iommu, info->bus, info->devfn, 0); |
| 5152 | if (WARN_ON(!context)) |
| 5153 | goto out; |
| 5154 | |
| 5155 | ctx_lo = context[0].lo; |
| 5156 | |
| 5157 | sdev->did = domain->iommu_did[iommu->seq_id]; |
| 5158 | sdev->sid = PCI_DEVID(info->bus, info->devfn); |
| 5159 | |
| 5160 | if (!(ctx_lo & CONTEXT_PASIDE)) { |
| 5161 | context[1].hi = (u64)virt_to_phys(iommu->pasid_state_table); |
| 5162 | context[1].lo = (u64)virt_to_phys(iommu->pasid_table) | ecap_pss(iommu->ecap); |
| 5163 | wmb(); |
| 5164 | /* CONTEXT_TT_MULTI_LEVEL and CONTEXT_TT_DEV_IOTLB are both |
| 5165 | * extended to permit requests-with-PASID if the PASIDE bit |
| 5166 | * is set. which makes sense. For CONTEXT_TT_PASS_THROUGH, |
| 5167 | * however, the PASIDE bit is ignored and requests-with-PASID |
| 5168 | * are unconditionally blocked. Which makes less sense. |
| 5169 | * So convert from CONTEXT_TT_PASS_THROUGH to one of the new |
| 5170 | * "guest mode" translation types depending on whether ATS |
| 5171 | * is available or not. Annoyingly, we can't use the new |
| 5172 | * modes *unless* PASIDE is set. */ |
| 5173 | if ((ctx_lo & CONTEXT_TT_MASK) == (CONTEXT_TT_PASS_THROUGH << 2)) { |
| 5174 | ctx_lo &= ~CONTEXT_TT_MASK; |
| 5175 | if (info->ats_supported) |
| 5176 | ctx_lo |= CONTEXT_TT_PT_PASID_DEV_IOTLB << 2; |
| 5177 | else |
| 5178 | ctx_lo |= CONTEXT_TT_PT_PASID << 2; |
| 5179 | } |
| 5180 | ctx_lo |= CONTEXT_PASIDE; |
David Woodhouse | 907fea3 | 2015-10-13 14:11:13 +0100 | [diff] [blame] | 5181 | if (iommu->pasid_state_table) |
| 5182 | ctx_lo |= CONTEXT_DINVE; |
David Woodhouse | a222a7f | 2015-10-07 23:35:18 +0100 | [diff] [blame] | 5183 | if (info->pri_supported) |
| 5184 | ctx_lo |= CONTEXT_PRS; |
David Woodhouse | 2f26e0a | 2015-09-09 11:40:47 +0100 | [diff] [blame] | 5185 | context[0].lo = ctx_lo; |
| 5186 | wmb(); |
| 5187 | iommu->flush.flush_context(iommu, sdev->did, sdev->sid, |
| 5188 | DMA_CCMD_MASK_NOBIT, |
| 5189 | DMA_CCMD_DEVICE_INVL); |
| 5190 | } |
| 5191 | |
| 5192 | /* Enable PASID support in the device, if it wasn't already */ |
| 5193 | if (!info->pasid_enabled) |
| 5194 | iommu_enable_dev_iotlb(info); |
| 5195 | |
| 5196 | if (info->ats_enabled) { |
| 5197 | sdev->dev_iotlb = 1; |
| 5198 | sdev->qdep = info->ats_qdep; |
| 5199 | if (sdev->qdep >= QI_DEV_EIOTLB_MAX_INVS) |
| 5200 | sdev->qdep = 0; |
| 5201 | } |
| 5202 | ret = 0; |
| 5203 | |
| 5204 | out: |
| 5205 | spin_unlock(&iommu->lock); |
| 5206 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 5207 | |
| 5208 | return ret; |
| 5209 | } |
| 5210 | |
| 5211 | struct intel_iommu *intel_svm_device_to_iommu(struct device *dev) |
| 5212 | { |
| 5213 | struct intel_iommu *iommu; |
| 5214 | u8 bus, devfn; |
| 5215 | |
| 5216 | if (iommu_dummy(dev)) { |
| 5217 | dev_warn(dev, |
| 5218 | "No IOMMU translation for device; cannot enable SVM\n"); |
| 5219 | return NULL; |
| 5220 | } |
| 5221 | |
| 5222 | iommu = device_to_iommu(dev, &bus, &devfn); |
| 5223 | if ((!iommu)) { |
Sudeep Dutt | b9997e3 | 2015-10-18 20:54:37 -0700 | [diff] [blame] | 5224 | dev_err(dev, "No IOMMU for device; cannot enable SVM\n"); |
David Woodhouse | 2f26e0a | 2015-09-09 11:40:47 +0100 | [diff] [blame] | 5225 | return NULL; |
| 5226 | } |
| 5227 | |
| 5228 | if (!iommu->pasid_table) { |
Sudeep Dutt | b9997e3 | 2015-10-18 20:54:37 -0700 | [diff] [blame] | 5229 | dev_err(dev, "PASID not enabled on IOMMU; cannot enable SVM\n"); |
David Woodhouse | 2f26e0a | 2015-09-09 11:40:47 +0100 | [diff] [blame] | 5230 | return NULL; |
| 5231 | } |
| 5232 | |
| 5233 | return iommu; |
| 5234 | } |
| 5235 | #endif /* CONFIG_INTEL_IOMMU_SVM */ |
| 5236 | |
Thierry Reding | b22f643 | 2014-06-27 09:03:12 +0200 | [diff] [blame] | 5237 | static const struct iommu_ops intel_iommu_ops = { |
Joerg Roedel | 5d587b8 | 2014-09-05 10:50:45 +0200 | [diff] [blame] | 5238 | .capable = intel_iommu_capable, |
Joerg Roedel | 00a77de | 2015-03-26 13:43:08 +0100 | [diff] [blame] | 5239 | .domain_alloc = intel_iommu_domain_alloc, |
| 5240 | .domain_free = intel_iommu_domain_free, |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 5241 | .attach_dev = intel_iommu_attach_device, |
| 5242 | .detach_dev = intel_iommu_detach_device, |
Joerg Roedel | b146a1c9f | 2010-01-20 17:17:37 +0100 | [diff] [blame] | 5243 | .map = intel_iommu_map, |
| 5244 | .unmap = intel_iommu_unmap, |
Olav Haugan | 315786e | 2014-10-25 09:55:16 -0700 | [diff] [blame] | 5245 | .map_sg = default_iommu_map_sg, |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 5246 | .iova_to_phys = intel_iommu_iova_to_phys, |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 5247 | .add_device = intel_iommu_add_device, |
| 5248 | .remove_device = intel_iommu_remove_device, |
Joerg Roedel | a960fad | 2015-10-21 23:51:39 +0200 | [diff] [blame] | 5249 | .device_group = pci_device_group, |
Ohad Ben-Cohen | 6d1c56a | 2011-11-10 11:32:30 +0200 | [diff] [blame] | 5250 | .pgsize_bitmap = INTEL_IOMMU_PGSIZES, |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 5251 | }; |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 5252 | |
Daniel Vetter | 9452618 | 2013-01-20 23:50:13 +0100 | [diff] [blame] | 5253 | static void quirk_iommu_g4x_gfx(struct pci_dev *dev) |
| 5254 | { |
| 5255 | /* G4x/GM45 integrated gfx dmar support is totally busted. */ |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 5256 | pr_info("Disabling IOMMU for graphics on this chipset\n"); |
Daniel Vetter | 9452618 | 2013-01-20 23:50:13 +0100 | [diff] [blame] | 5257 | dmar_map_gfx = 0; |
| 5258 | } |
| 5259 | |
| 5260 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx); |
| 5261 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx); |
| 5262 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx); |
| 5263 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx); |
| 5264 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx); |
| 5265 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx); |
| 5266 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx); |
| 5267 | |
Greg Kroah-Hartman | d34d651 | 2012-12-21 15:05:21 -0800 | [diff] [blame] | 5268 | static void quirk_iommu_rwbf(struct pci_dev *dev) |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 5269 | { |
| 5270 | /* |
| 5271 | * Mobile 4 Series Chipset neglects to set RWBF capability, |
Daniel Vetter | 210561f | 2013-01-21 19:48:59 +0100 | [diff] [blame] | 5272 | * but needs it. Same seems to hold for the desktop versions. |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 5273 | */ |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 5274 | pr_info("Forcing write-buffer flush capability\n"); |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 5275 | rwbf_quirk = 1; |
| 5276 | } |
| 5277 | |
| 5278 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); |
Daniel Vetter | 210561f | 2013-01-21 19:48:59 +0100 | [diff] [blame] | 5279 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf); |
| 5280 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf); |
| 5281 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf); |
| 5282 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf); |
| 5283 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf); |
| 5284 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf); |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 5285 | |
Adam Jackson | eecfd57 | 2010-08-25 21:17:34 +0100 | [diff] [blame] | 5286 | #define GGC 0x52 |
| 5287 | #define GGC_MEMORY_SIZE_MASK (0xf << 8) |
| 5288 | #define GGC_MEMORY_SIZE_NONE (0x0 << 8) |
| 5289 | #define GGC_MEMORY_SIZE_1M (0x1 << 8) |
| 5290 | #define GGC_MEMORY_SIZE_2M (0x3 << 8) |
| 5291 | #define GGC_MEMORY_VT_ENABLED (0x8 << 8) |
| 5292 | #define GGC_MEMORY_SIZE_2M_VT (0x9 << 8) |
| 5293 | #define GGC_MEMORY_SIZE_3M_VT (0xa << 8) |
| 5294 | #define GGC_MEMORY_SIZE_4M_VT (0xb << 8) |
| 5295 | |
Greg Kroah-Hartman | d34d651 | 2012-12-21 15:05:21 -0800 | [diff] [blame] | 5296 | static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev) |
David Woodhouse | 9eecabc | 2010-09-21 22:28:23 +0100 | [diff] [blame] | 5297 | { |
| 5298 | unsigned short ggc; |
| 5299 | |
Adam Jackson | eecfd57 | 2010-08-25 21:17:34 +0100 | [diff] [blame] | 5300 | if (pci_read_config_word(dev, GGC, &ggc)) |
David Woodhouse | 9eecabc | 2010-09-21 22:28:23 +0100 | [diff] [blame] | 5301 | return; |
| 5302 | |
Adam Jackson | eecfd57 | 2010-08-25 21:17:34 +0100 | [diff] [blame] | 5303 | if (!(ggc & GGC_MEMORY_VT_ENABLED)) { |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 5304 | pr_info("BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n"); |
David Woodhouse | 9eecabc | 2010-09-21 22:28:23 +0100 | [diff] [blame] | 5305 | dmar_map_gfx = 0; |
David Woodhouse | 6fbcfb3 | 2011-09-25 19:11:14 -0700 | [diff] [blame] | 5306 | } else if (dmar_map_gfx) { |
| 5307 | /* we have to ensure the gfx device is idle before we flush */ |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 5308 | pr_info("Disabling batched IOTLB flush on Ironlake\n"); |
David Woodhouse | 6fbcfb3 | 2011-09-25 19:11:14 -0700 | [diff] [blame] | 5309 | intel_iommu_strict = 1; |
| 5310 | } |
David Woodhouse | 9eecabc | 2010-09-21 22:28:23 +0100 | [diff] [blame] | 5311 | } |
| 5312 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt); |
| 5313 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt); |
| 5314 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt); |
| 5315 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt); |
| 5316 | |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 5317 | /* On Tylersburg chipsets, some BIOSes have been known to enable the |
| 5318 | ISOCH DMAR unit for the Azalia sound device, but not give it any |
| 5319 | TLB entries, which causes it to deadlock. Check for that. We do |
| 5320 | this in a function called from init_dmars(), instead of in a PCI |
| 5321 | quirk, because we don't want to print the obnoxious "BIOS broken" |
| 5322 | message if VT-d is actually disabled. |
| 5323 | */ |
| 5324 | static void __init check_tylersburg_isoch(void) |
| 5325 | { |
| 5326 | struct pci_dev *pdev; |
| 5327 | uint32_t vtisochctrl; |
| 5328 | |
| 5329 | /* If there's no Azalia in the system anyway, forget it. */ |
| 5330 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL); |
| 5331 | if (!pdev) |
| 5332 | return; |
| 5333 | pci_dev_put(pdev); |
| 5334 | |
| 5335 | /* System Management Registers. Might be hidden, in which case |
| 5336 | we can't do the sanity check. But that's OK, because the |
| 5337 | known-broken BIOSes _don't_ actually hide it, so far. */ |
| 5338 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL); |
| 5339 | if (!pdev) |
| 5340 | return; |
| 5341 | |
| 5342 | if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) { |
| 5343 | pci_dev_put(pdev); |
| 5344 | return; |
| 5345 | } |
| 5346 | |
| 5347 | pci_dev_put(pdev); |
| 5348 | |
| 5349 | /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */ |
| 5350 | if (vtisochctrl & 1) |
| 5351 | return; |
| 5352 | |
| 5353 | /* Drop all bits other than the number of TLB entries */ |
| 5354 | vtisochctrl &= 0x1c; |
| 5355 | |
| 5356 | /* If we have the recommended number of TLB entries (16), fine. */ |
| 5357 | if (vtisochctrl == 0x10) |
| 5358 | return; |
| 5359 | |
| 5360 | /* Zero TLB entries? You get to ride the short bus to school. */ |
| 5361 | if (!vtisochctrl) { |
| 5362 | WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n" |
| 5363 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", |
| 5364 | dmi_get_system_info(DMI_BIOS_VENDOR), |
| 5365 | dmi_get_system_info(DMI_BIOS_VERSION), |
| 5366 | dmi_get_system_info(DMI_PRODUCT_VERSION)); |
| 5367 | iommu_identity_mapping |= IDENTMAP_AZALIA; |
| 5368 | return; |
| 5369 | } |
Joerg Roedel | 9f10e5b | 2015-06-12 09:57:06 +0200 | [diff] [blame] | 5370 | |
| 5371 | pr_warn("Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n", |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 5372 | vtisochctrl); |
| 5373 | } |