Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
| 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 4 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 6 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the |
| 10 | * "Software"), to deal in the Software without restriction, including |
| 11 | * without limitation the rights to use, copy, modify, merge, publish, |
| 12 | * distribute, sub license, and/or sell copies of the Software, and to |
| 13 | * permit persons to whom the Software is furnished to do so, subject to |
| 14 | * the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice (including the |
| 17 | * next paragraph) shall be included in all copies or substantial portions |
| 18 | * of the Software. |
| 19 | * |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 27 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 28 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | |
| 30 | #ifndef _I915_DRV_H_ |
| 31 | #define _I915_DRV_H_ |
| 32 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 33 | #include "i915_reg.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 34 | #include "intel_bios.h" |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 35 | #include "intel_ringbuffer.h" |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 36 | #include <linux/io-mapping.h> |
Daniel Vetter | 0ade638 | 2010-08-24 22:18:41 +0200 | [diff] [blame] | 37 | #include <drm/intel-gtt.h> |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 38 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | /* General customization: |
| 40 | */ |
| 41 | |
| 42 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." |
| 43 | |
| 44 | #define DRIVER_NAME "i915" |
| 45 | #define DRIVER_DESC "Intel Graphics" |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 46 | #define DRIVER_DATE "20080730" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 48 | enum pipe { |
| 49 | PIPE_A = 0, |
| 50 | PIPE_B, |
| 51 | }; |
| 52 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 53 | enum plane { |
| 54 | PLANE_A = 0, |
| 55 | PLANE_B, |
| 56 | }; |
| 57 | |
Keith Packard | 5244021 | 2008-11-18 09:30:25 -0800 | [diff] [blame] | 58 | #define I915_NUM_PIPE 2 |
| 59 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 60 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
| 61 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 62 | /* Interface history: |
| 63 | * |
| 64 | * 1.1: Original. |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 65 | * 1.2: Add Power Management |
| 66 | * 1.3: Add vblank support |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 67 | * 1.4: Fix cmdbuffer path, add heap destroy |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 68 | * 1.5: Add vblank pipe configuration |
=?utf-8?q?Michel_D=C3=A4nzer?= | 2228ed6 | 2006-10-25 01:05:09 +1000 | [diff] [blame] | 69 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
| 70 | * - Support vertical blank on secondary display pipe |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 71 | */ |
| 72 | #define DRIVER_MAJOR 1 |
=?utf-8?q?Michel_D=C3=A4nzer?= | 2228ed6 | 2006-10-25 01:05:09 +1000 | [diff] [blame] | 73 | #define DRIVER_MINOR 6 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | #define DRIVER_PATCHLEVEL 0 |
| 75 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 76 | #define WATCH_COHERENCY 0 |
| 77 | #define WATCH_BUF 0 |
| 78 | #define WATCH_EXEC 0 |
| 79 | #define WATCH_LRU 0 |
| 80 | #define WATCH_RELOC 0 |
| 81 | #define WATCH_INACTIVE 0 |
| 82 | #define WATCH_PWRITE 0 |
| 83 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 84 | #define I915_GEM_PHYS_CURSOR_0 1 |
| 85 | #define I915_GEM_PHYS_CURSOR_1 2 |
| 86 | #define I915_GEM_PHYS_OVERLAY_REGS 3 |
| 87 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) |
| 88 | |
| 89 | struct drm_i915_gem_phys_object { |
| 90 | int id; |
| 91 | struct page **page_list; |
| 92 | drm_dma_handle_t *handle; |
| 93 | struct drm_gem_object *cur_obj; |
| 94 | }; |
| 95 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 96 | struct mem_block { |
| 97 | struct mem_block *next; |
| 98 | struct mem_block *prev; |
| 99 | int start; |
| 100 | int size; |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 101 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 102 | }; |
| 103 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 104 | struct opregion_header; |
| 105 | struct opregion_acpi; |
| 106 | struct opregion_swsci; |
| 107 | struct opregion_asle; |
| 108 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 109 | struct intel_opregion { |
| 110 | struct opregion_header *header; |
| 111 | struct opregion_acpi *acpi; |
| 112 | struct opregion_swsci *swsci; |
| 113 | struct opregion_asle *asle; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 114 | void *vbt; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 115 | }; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 116 | #define OPREGION_SIZE (8*1024) |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 117 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 118 | struct intel_overlay; |
| 119 | struct intel_overlay_error_state; |
| 120 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 121 | struct drm_i915_master_private { |
| 122 | drm_local_map_t *sarea; |
| 123 | struct _drm_i915_sarea *sarea_priv; |
| 124 | }; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 125 | #define I915_FENCE_REG_NONE -1 |
| 126 | |
| 127 | struct drm_i915_fence_reg { |
| 128 | struct drm_gem_object *obj; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 129 | struct list_head lru_list; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 130 | }; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 131 | |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 132 | struct sdvo_device_mapping { |
| 133 | u8 dvo_port; |
| 134 | u8 slave_addr; |
| 135 | u8 dvo_wiring; |
| 136 | u8 initialized; |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 137 | u8 ddc_pin; |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 138 | }; |
| 139 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 140 | struct drm_i915_error_state { |
| 141 | u32 eir; |
| 142 | u32 pgtbl_er; |
| 143 | u32 pipeastat; |
| 144 | u32 pipebstat; |
| 145 | u32 ipeir; |
| 146 | u32 ipehr; |
| 147 | u32 instdone; |
| 148 | u32 acthd; |
| 149 | u32 instpm; |
| 150 | u32 instps; |
| 151 | u32 instdone1; |
| 152 | u32 seqno; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 153 | u64 bbaddr; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 154 | struct timeval time; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 155 | struct drm_i915_error_object { |
| 156 | int page_count; |
| 157 | u32 gtt_offset; |
| 158 | u32 *pages[0]; |
| 159 | } *ringbuffer, *batchbuffer[2]; |
| 160 | struct drm_i915_error_buffer { |
| 161 | size_t size; |
| 162 | u32 name; |
| 163 | u32 seqno; |
| 164 | u32 gtt_offset; |
| 165 | u32 read_domains; |
| 166 | u32 write_domain; |
| 167 | u32 fence_reg; |
| 168 | s32 pinned:2; |
| 169 | u32 tiling:2; |
| 170 | u32 dirty:1; |
| 171 | u32 purgeable:1; |
| 172 | } *active_bo; |
| 173 | u32 active_bo_count; |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 174 | struct intel_overlay_error_state *overlay; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 175 | }; |
| 176 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 177 | struct drm_i915_display_funcs { |
| 178 | void (*dpms)(struct drm_crtc *crtc, int mode); |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 179 | bool (*fbc_enabled)(struct drm_device *dev); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 180 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
| 181 | void (*disable_fbc)(struct drm_device *dev); |
| 182 | int (*get_display_clock_speed)(struct drm_device *dev); |
| 183 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
| 184 | void (*update_wm)(struct drm_device *dev, int planea_clock, |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 185 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
| 186 | int pixel_size); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 187 | /* clock updates for mode set */ |
| 188 | /* cursor updates */ |
| 189 | /* render clock increase/decrease */ |
| 190 | /* display clock increase/decrease */ |
| 191 | /* pll clock increase/decrease */ |
| 192 | /* clock gating init */ |
| 193 | }; |
| 194 | |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 195 | struct intel_device_info { |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 196 | u8 gen; |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 197 | u8 is_mobile : 1; |
| 198 | u8 is_i8xx : 1; |
Adam Jackson | 5ce8ba7 | 2010-04-15 14:03:30 -0400 | [diff] [blame] | 199 | u8 is_i85x : 1; |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 200 | u8 is_i915g : 1; |
| 201 | u8 is_i9xx : 1; |
| 202 | u8 is_i945gm : 1; |
| 203 | u8 is_i965g : 1; |
| 204 | u8 is_i965gm : 1; |
| 205 | u8 is_g33 : 1; |
| 206 | u8 need_gfx_hws : 1; |
| 207 | u8 is_g4x : 1; |
| 208 | u8 is_pineview : 1; |
Chris Wilson | 534843d | 2010-07-05 18:01:46 +0100 | [diff] [blame] | 209 | u8 is_broadwater : 1; |
| 210 | u8 is_crestline : 1; |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 211 | u8 is_ironlake : 1; |
| 212 | u8 has_fbc : 1; |
| 213 | u8 has_rc6 : 1; |
| 214 | u8 has_pipe_cxsr : 1; |
| 215 | u8 has_hotplug : 1; |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 216 | u8 cursor_needs_physical : 1; |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 217 | u8 has_overlay : 1; |
| 218 | u8 overlay_needs_physical : 1; |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 219 | }; |
| 220 | |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 221 | enum no_fbc_reason { |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame^] | 222 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 223 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
| 224 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ |
| 225 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ |
| 226 | FBC_BAD_PLANE, /* fbc not supported on plane */ |
| 227 | FBC_NOT_TILED, /* buffer not tiled */ |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 228 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 229 | }; |
| 230 | |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 231 | enum intel_pch { |
| 232 | PCH_IBX, /* Ibexpeak PCH */ |
| 233 | PCH_CPT, /* Cougarpoint PCH */ |
| 234 | }; |
| 235 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 236 | #define QUIRK_PIPEA_FORCE (1<<0) |
| 237 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 238 | struct intel_fbdev; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 239 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 240 | typedef struct drm_i915_private { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 241 | struct drm_device *dev; |
| 242 | |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 243 | const struct intel_device_info *info; |
| 244 | |
Dave Airlie | ac5c4e7 | 2008-12-19 15:38:34 +1000 | [diff] [blame] | 245 | int has_gem; |
| 246 | |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 247 | void __iomem *regs; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 248 | |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 249 | struct pci_dev *bridge_dev; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 250 | struct intel_ring_buffer render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 251 | struct intel_ring_buffer bsd_ring; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 252 | uint32_t next_seqno; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 253 | |
Dave Airlie | 9c8da5e | 2005-07-10 15:38:56 +1000 | [diff] [blame] | 254 | drm_dma_handle_t *status_page_dmah; |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 255 | void *seqno_page; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 256 | dma_addr_t dma_status_page; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 257 | uint32_t counter; |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 258 | unsigned int seqno_gfx_addr; |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 259 | drm_local_map_t hws_map; |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 260 | struct drm_gem_object *seqno_obj; |
Jesse Barnes | 97f5ab6 | 2009-10-08 10:16:48 -0700 | [diff] [blame] | 261 | struct drm_gem_object *pwrctx; |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 262 | struct drm_gem_object *renderctx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 263 | |
Jesse Barnes | d765898 | 2009-06-05 14:41:29 +0000 | [diff] [blame] | 264 | struct resource mch_res; |
| 265 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 266 | unsigned int cpp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 267 | int back_offset; |
| 268 | int front_offset; |
| 269 | int current_page; |
| 270 | int page_flipping; |
Jesse Barnes | be282fd | 2010-08-13 15:50:28 -0700 | [diff] [blame] | 271 | #define I915_DEBUG_READ (1<<0) |
| 272 | #define I915_DEBUG_WRITE (1<<1) |
| 273 | unsigned long debug_flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 274 | |
| 275 | wait_queue_head_t irq_queue; |
| 276 | atomic_t irq_received; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 277 | /** Protects user_irq_refcount and irq_mask_reg */ |
| 278 | spinlock_t user_irq_lock; |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 279 | u32 trace_irq_seqno; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 280 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
| 281 | u32 irq_mask_reg; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 282 | u32 pipestat[2]; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 283 | /** splitted irq regs for graphics and display engine on Ironlake, |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 284 | irq_mask_reg is still used for display irq. */ |
| 285 | u32 gt_irq_mask_reg; |
| 286 | u32 gt_irq_enable_reg; |
| 287 | u32 de_irq_enable_reg; |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 288 | u32 pch_irq_mask_reg; |
| 289 | u32 pch_irq_enable_reg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 290 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 291 | u32 hotplug_supported_mask; |
| 292 | struct work_struct hotplug_work; |
| 293 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 294 | int tex_lru_log_granularity; |
| 295 | int allow_batchbuffer; |
| 296 | struct mem_block *agp_heap; |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 297 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 298 | int vblank_pipe; |
Dave Airlie | a3524f1 | 2010-06-06 18:59:41 +1000 | [diff] [blame] | 299 | int num_pipe; |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 300 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 301 | /* For hangcheck timer */ |
| 302 | #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */ |
| 303 | struct timer_list hangcheck_timer; |
| 304 | int hangcheck_count; |
| 305 | uint32_t last_acthd; |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 306 | uint32_t last_instdone; |
| 307 | uint32_t last_instdone1; |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 308 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 309 | unsigned long cfb_size; |
| 310 | unsigned long cfb_pitch; |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame^] | 311 | unsigned long cfb_offset; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 312 | int cfb_fence; |
| 313 | int cfb_plane; |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame^] | 314 | int cfb_y; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 315 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 316 | int irq_enabled; |
| 317 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 318 | struct intel_opregion opregion; |
| 319 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 320 | /* overlay */ |
| 321 | struct intel_overlay *overlay; |
| 322 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 323 | /* LVDS info */ |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 324 | int backlight_level; /* restore backlight to this value */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 325 | bool panel_wants_dither; |
| 326 | struct drm_display_mode *panel_fixed_mode; |
Ma Ling | 8863170 | 2009-05-13 11:19:55 +0800 | [diff] [blame] | 327 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
| 328 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 329 | |
| 330 | /* Feature bits from the VBIOS */ |
Hannes Eder | 95281e3 | 2008-12-18 15:09:00 +0100 | [diff] [blame] | 331 | unsigned int int_tv_support:1; |
| 332 | unsigned int lvds_dither:1; |
| 333 | unsigned int lvds_vbt:1; |
| 334 | unsigned int int_crt_support:1; |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 335 | unsigned int lvds_use_ssc:1; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 336 | unsigned int edp_support:1; |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 337 | int lvds_ssc_freq; |
Zhenyu Wang | 500a8cc | 2010-01-13 11:19:52 +0800 | [diff] [blame] | 338 | int edp_bpp; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 339 | |
Jesse Barnes | c1c7af6 | 2009-09-10 15:28:03 -0700 | [diff] [blame] | 340 | struct notifier_block lid_notifier; |
| 341 | |
Shaohua Li | 29874f4 | 2009-11-18 15:15:02 +0800 | [diff] [blame] | 342 | int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */ |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 343 | struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
| 344 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
| 345 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
| 346 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 347 | unsigned int fsb_freq, mem_freq, is_ddr3; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 348 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 349 | spinlock_t error_lock; |
| 350 | struct drm_i915_error_state *first_error; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 351 | struct work_struct error_work; |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 352 | struct workqueue_struct *wq; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 353 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 354 | /* Display functions */ |
| 355 | struct drm_i915_display_funcs display; |
| 356 | |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 357 | /* PCH chipset type */ |
| 358 | enum intel_pch pch_type; |
| 359 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 360 | unsigned long quirks; |
| 361 | |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 362 | /* Register state */ |
Linus Torvalds | c9354c8 | 2009-11-02 09:29:55 -0800 | [diff] [blame] | 363 | bool modeset_on_lid; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 364 | u8 saveLBB; |
| 365 | u32 saveDSPACNTR; |
| 366 | u32 saveDSPBCNTR; |
Keith Packard | e948e99 | 2008-05-07 12:27:53 +1000 | [diff] [blame] | 367 | u32 saveDSPARB; |
Peng Li | 461cba2 | 2008-11-18 12:39:02 +0800 | [diff] [blame] | 368 | u32 saveHWS; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 369 | u32 savePIPEACONF; |
| 370 | u32 savePIPEBCONF; |
| 371 | u32 savePIPEASRC; |
| 372 | u32 savePIPEBSRC; |
| 373 | u32 saveFPA0; |
| 374 | u32 saveFPA1; |
| 375 | u32 saveDPLL_A; |
| 376 | u32 saveDPLL_A_MD; |
| 377 | u32 saveHTOTAL_A; |
| 378 | u32 saveHBLANK_A; |
| 379 | u32 saveHSYNC_A; |
| 380 | u32 saveVTOTAL_A; |
| 381 | u32 saveVBLANK_A; |
| 382 | u32 saveVSYNC_A; |
| 383 | u32 saveBCLRPAT_A; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 384 | u32 saveTRANSACONF; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 385 | u32 saveTRANS_HTOTAL_A; |
| 386 | u32 saveTRANS_HBLANK_A; |
| 387 | u32 saveTRANS_HSYNC_A; |
| 388 | u32 saveTRANS_VTOTAL_A; |
| 389 | u32 saveTRANS_VBLANK_A; |
| 390 | u32 saveTRANS_VSYNC_A; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 391 | u32 savePIPEASTAT; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 392 | u32 saveDSPASTRIDE; |
| 393 | u32 saveDSPASIZE; |
| 394 | u32 saveDSPAPOS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 395 | u32 saveDSPAADDR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 396 | u32 saveDSPASURF; |
| 397 | u32 saveDSPATILEOFF; |
| 398 | u32 savePFIT_PGM_RATIOS; |
Jesse Barnes | 0eb96d6 | 2009-10-14 12:33:41 -0700 | [diff] [blame] | 399 | u32 saveBLC_HIST_CTL; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 400 | u32 saveBLC_PWM_CTL; |
| 401 | u32 saveBLC_PWM_CTL2; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 402 | u32 saveBLC_CPU_PWM_CTL; |
| 403 | u32 saveBLC_CPU_PWM_CTL2; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 404 | u32 saveFPB0; |
| 405 | u32 saveFPB1; |
| 406 | u32 saveDPLL_B; |
| 407 | u32 saveDPLL_B_MD; |
| 408 | u32 saveHTOTAL_B; |
| 409 | u32 saveHBLANK_B; |
| 410 | u32 saveHSYNC_B; |
| 411 | u32 saveVTOTAL_B; |
| 412 | u32 saveVBLANK_B; |
| 413 | u32 saveVSYNC_B; |
| 414 | u32 saveBCLRPAT_B; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 415 | u32 saveTRANSBCONF; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 416 | u32 saveTRANS_HTOTAL_B; |
| 417 | u32 saveTRANS_HBLANK_B; |
| 418 | u32 saveTRANS_HSYNC_B; |
| 419 | u32 saveTRANS_VTOTAL_B; |
| 420 | u32 saveTRANS_VBLANK_B; |
| 421 | u32 saveTRANS_VSYNC_B; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 422 | u32 savePIPEBSTAT; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 423 | u32 saveDSPBSTRIDE; |
| 424 | u32 saveDSPBSIZE; |
| 425 | u32 saveDSPBPOS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 426 | u32 saveDSPBADDR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 427 | u32 saveDSPBSURF; |
| 428 | u32 saveDSPBTILEOFF; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 429 | u32 saveVGA0; |
| 430 | u32 saveVGA1; |
| 431 | u32 saveVGA_PD; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 432 | u32 saveVGACNTRL; |
| 433 | u32 saveADPA; |
| 434 | u32 saveLVDS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 435 | u32 savePP_ON_DELAYS; |
| 436 | u32 savePP_OFF_DELAYS; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 437 | u32 saveDVOA; |
| 438 | u32 saveDVOB; |
| 439 | u32 saveDVOC; |
| 440 | u32 savePP_ON; |
| 441 | u32 savePP_OFF; |
| 442 | u32 savePP_CONTROL; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 443 | u32 savePP_DIVISOR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 444 | u32 savePFIT_CONTROL; |
| 445 | u32 save_palette_a[256]; |
| 446 | u32 save_palette_b[256]; |
Jesse Barnes | 06027f9 | 2009-10-05 13:47:26 -0700 | [diff] [blame] | 447 | u32 saveDPFC_CB_BASE; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 448 | u32 saveFBC_CFB_BASE; |
| 449 | u32 saveFBC_LL_BASE; |
| 450 | u32 saveFBC_CONTROL; |
| 451 | u32 saveFBC_CONTROL2; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 452 | u32 saveIER; |
| 453 | u32 saveIIR; |
| 454 | u32 saveIMR; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 455 | u32 saveDEIER; |
| 456 | u32 saveDEIMR; |
| 457 | u32 saveGTIER; |
| 458 | u32 saveGTIMR; |
| 459 | u32 saveFDI_RXA_IMR; |
| 460 | u32 saveFDI_RXB_IMR; |
Keith Packard | 1f84e55 | 2008-02-16 19:19:29 -0800 | [diff] [blame] | 461 | u32 saveCACHE_MODE_0; |
Keith Packard | 1f84e55 | 2008-02-16 19:19:29 -0800 | [diff] [blame] | 462 | u32 saveMI_ARB_STATE; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 463 | u32 saveSWF0[16]; |
| 464 | u32 saveSWF1[16]; |
| 465 | u32 saveSWF2[3]; |
| 466 | u8 saveMSR; |
| 467 | u8 saveSR[8]; |
Jesse Barnes | 123f794 | 2008-02-07 11:15:20 -0800 | [diff] [blame] | 468 | u8 saveGR[25]; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 469 | u8 saveAR_INDEX; |
Jesse Barnes | a59e122 | 2008-05-07 12:25:46 +1000 | [diff] [blame] | 470 | u8 saveAR[21]; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 471 | u8 saveDACMASK; |
Jesse Barnes | a59e122 | 2008-05-07 12:25:46 +1000 | [diff] [blame] | 472 | u8 saveCR[37]; |
Keith Packard | 79f11c1 | 2009-04-30 14:43:44 -0700 | [diff] [blame] | 473 | uint64_t saveFENCE[16]; |
Eric Anholt | 1fd1c62 | 2009-06-03 07:26:58 +0000 | [diff] [blame] | 474 | u32 saveCURACNTR; |
| 475 | u32 saveCURAPOS; |
| 476 | u32 saveCURABASE; |
| 477 | u32 saveCURBCNTR; |
| 478 | u32 saveCURBPOS; |
| 479 | u32 saveCURBBASE; |
| 480 | u32 saveCURSIZE; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 481 | u32 saveDP_B; |
| 482 | u32 saveDP_C; |
| 483 | u32 saveDP_D; |
| 484 | u32 savePIPEA_GMCH_DATA_M; |
| 485 | u32 savePIPEB_GMCH_DATA_M; |
| 486 | u32 savePIPEA_GMCH_DATA_N; |
| 487 | u32 savePIPEB_GMCH_DATA_N; |
| 488 | u32 savePIPEA_DP_LINK_M; |
| 489 | u32 savePIPEB_DP_LINK_M; |
| 490 | u32 savePIPEA_DP_LINK_N; |
| 491 | u32 savePIPEB_DP_LINK_N; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 492 | u32 saveFDI_RXA_CTL; |
| 493 | u32 saveFDI_TXA_CTL; |
| 494 | u32 saveFDI_RXB_CTL; |
| 495 | u32 saveFDI_TXB_CTL; |
| 496 | u32 savePFA_CTL_1; |
| 497 | u32 savePFB_CTL_1; |
| 498 | u32 savePFA_WIN_SZ; |
| 499 | u32 savePFB_WIN_SZ; |
| 500 | u32 savePFA_WIN_POS; |
| 501 | u32 savePFB_WIN_POS; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 502 | u32 savePCH_DREF_CONTROL; |
| 503 | u32 saveDISP_ARB_CTL; |
| 504 | u32 savePIPEA_DATA_M1; |
| 505 | u32 savePIPEA_DATA_N1; |
| 506 | u32 savePIPEA_LINK_M1; |
| 507 | u32 savePIPEA_LINK_N1; |
| 508 | u32 savePIPEB_DATA_M1; |
| 509 | u32 savePIPEB_DATA_N1; |
| 510 | u32 savePIPEB_LINK_M1; |
| 511 | u32 savePIPEB_LINK_N1; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 512 | u32 saveMCHBAR_RENDER_STANDBY; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 513 | |
| 514 | struct { |
Daniel Vetter | 1996675 | 2010-09-06 20:08:44 +0200 | [diff] [blame] | 515 | /** Bridge to intel-gtt-ko */ |
| 516 | struct intel_gtt *gtt; |
| 517 | /** Memory allocator for GTT stolen memory */ |
| 518 | struct drm_mm vram; |
| 519 | /** Memory allocator for GTT */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 520 | struct drm_mm gtt_space; |
| 521 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 522 | struct io_mapping *gtt_mapping; |
Eric Anholt | ab657db1 | 2009-01-23 12:57:47 -0800 | [diff] [blame] | 523 | int gtt_mtrr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 524 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 525 | /** |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 526 | * Membership on list of all loaded devices, used to evict |
| 527 | * inactive buffers under memory pressure. |
| 528 | * |
| 529 | * Modifications should only be done whilst holding the |
| 530 | * shrink_list_lock spinlock. |
| 531 | */ |
| 532 | struct list_head shrink_list; |
| 533 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 534 | /** |
| 535 | * List of objects which are not in the ringbuffer but which |
| 536 | * still have a write_domain which needs to be flushed before |
| 537 | * unbinding. |
| 538 | * |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 539 | * last_rendering_seqno is 0 while an object is in this list. |
| 540 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 541 | * A reference is held on the buffer while on this list. |
| 542 | */ |
| 543 | struct list_head flushing_list; |
| 544 | |
| 545 | /** |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 546 | * List of objects currently pending a GPU write flush. |
| 547 | * |
| 548 | * All elements on this list will belong to either the |
| 549 | * active_list or flushing_list, last_rendering_seqno can |
| 550 | * be used to differentiate between the two elements. |
| 551 | */ |
| 552 | struct list_head gpu_write_list; |
| 553 | |
| 554 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 555 | * LRU list of objects which are not in the ringbuffer and |
| 556 | * are ready to unbind, but are still in the GTT. |
| 557 | * |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 558 | * last_rendering_seqno is 0 while an object is in this list. |
| 559 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 560 | * A reference is not held on the buffer while on this list, |
| 561 | * as merely being GTT-bound shouldn't prevent its being |
| 562 | * freed, and we'll pull it off the list in the free path. |
| 563 | */ |
| 564 | struct list_head inactive_list; |
| 565 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 566 | /** LRU list of objects with fence regs on them. */ |
| 567 | struct list_head fence_list; |
| 568 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 569 | /** |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 570 | * List of objects currently pending being freed. |
| 571 | * |
| 572 | * These objects are no longer in use, but due to a signal |
| 573 | * we were prevented from freeing them at the appointed time. |
| 574 | */ |
| 575 | struct list_head deferred_free_list; |
| 576 | |
| 577 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 578 | * We leave the user IRQ off as much as possible, |
| 579 | * but this means that requests will finish and never |
| 580 | * be retired once the system goes idle. Set a timer to |
| 581 | * fire periodically while the ring is running. When it |
| 582 | * fires, go retire requests. |
| 583 | */ |
| 584 | struct delayed_work retire_work; |
| 585 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 586 | /** |
| 587 | * Waiting sequence number, if any |
| 588 | */ |
| 589 | uint32_t waiting_gem_seqno; |
| 590 | |
| 591 | /** |
| 592 | * Last seq seen at irq time |
| 593 | */ |
| 594 | uint32_t irq_gem_seqno; |
| 595 | |
| 596 | /** |
| 597 | * Flag if the X Server, and thus DRM, is not currently in |
| 598 | * control of the device. |
| 599 | * |
| 600 | * This is set between LeaveVT and EnterVT. It needs to be |
| 601 | * replaced with a semaphore. It also needs to be |
| 602 | * transitioned away from for kernel modesetting. |
| 603 | */ |
| 604 | int suspended; |
| 605 | |
| 606 | /** |
| 607 | * Flag if the hardware appears to be wedged. |
| 608 | * |
| 609 | * This is set when attempts to idle the device timeout. |
| 610 | * It prevents command submission from occuring and makes |
| 611 | * every pending request fail |
| 612 | */ |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 613 | atomic_t wedged; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 614 | |
| 615 | /** Bit 6 swizzling required for X tiling */ |
| 616 | uint32_t bit_6_swizzle_x; |
| 617 | /** Bit 6 swizzling required for Y tiling */ |
| 618 | uint32_t bit_6_swizzle_y; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 619 | |
| 620 | /* storage for physical objects */ |
| 621 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 622 | } mm; |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 623 | struct sdvo_device_mapping sdvo_mappings[2]; |
Zhao Yakui | a3e17eb | 2009-10-10 10:42:37 +0800 | [diff] [blame] | 624 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
| 625 | unsigned int lvds_border_bits; |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 626 | /* Panel fitter placement and size for Ironlake+ */ |
| 627 | u32 pch_pf_pos, pch_pf_size; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 628 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 629 | struct drm_crtc *plane_to_crtc_mapping[2]; |
| 630 | struct drm_crtc *pipe_to_crtc_mapping[2]; |
| 631 | wait_queue_head_t pending_flip_queue; |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 632 | bool flip_pending_is_done; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 633 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 634 | /* Reclocking support */ |
| 635 | bool render_reclock_avail; |
| 636 | bool lvds_downclock_avail; |
Zhao Yakui | bfac4d6 | 2010-04-07 17:11:22 +0800 | [diff] [blame] | 637 | /* indicate whether the LVDS EDID is OK */ |
| 638 | bool lvds_edid_good; |
Zhao Yakui | 18f9ed1 | 2009-11-20 03:24:16 +0000 | [diff] [blame] | 639 | /* indicates the reduced downclock for LVDS*/ |
| 640 | int lvds_downclock; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 641 | struct work_struct idle_work; |
| 642 | struct timer_list idle_timer; |
| 643 | bool busy; |
| 644 | u16 orig_clock; |
Zhao Yakui | 6363ee6 | 2009-11-24 09:48:44 +0800 | [diff] [blame] | 645 | int child_dev_num; |
| 646 | struct child_device_config *child_dev; |
Zhao Yakui | a256537 | 2009-12-11 09:26:11 +0800 | [diff] [blame] | 647 | struct drm_connector *int_lvds_connector; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 648 | |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 649 | bool mchbar_need_disable; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 650 | |
| 651 | u8 cur_delay; |
| 652 | u8 min_delay; |
| 653 | u8 max_delay; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 654 | u8 fmax; |
| 655 | u8 fstart; |
| 656 | |
| 657 | u64 last_count1; |
| 658 | unsigned long last_time1; |
| 659 | u64 last_count2; |
| 660 | struct timespec last_time2; |
| 661 | unsigned long gfx_power; |
| 662 | int c_m; |
| 663 | int r_t; |
| 664 | u8 corr; |
| 665 | spinlock_t *mchdev_lock; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 666 | |
| 667 | enum no_fbc_reason no_fbc_reason; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 668 | |
Jesse Barnes | 20bf377 | 2010-04-21 11:39:22 -0700 | [diff] [blame] | 669 | struct drm_mm_node *compressed_fb; |
| 670 | struct drm_mm_node *compressed_llb; |
Eric Anholt | 34dc4d4 | 2010-05-07 14:30:03 -0700 | [diff] [blame] | 671 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 672 | /* list of fbdev register on this device */ |
| 673 | struct intel_fbdev *fbdev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 674 | } drm_i915_private_t; |
| 675 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 676 | /** driver private structure attached to each drm_gem_object */ |
| 677 | struct drm_i915_gem_object { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 678 | struct drm_gem_object base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 679 | |
| 680 | /** Current space allocated to this object in the GTT, if any. */ |
| 681 | struct drm_mm_node *gtt_space; |
| 682 | |
| 683 | /** This object's place on the active/flushing/inactive lists */ |
| 684 | struct list_head list; |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 685 | /** This object's place on GPU write list */ |
| 686 | struct list_head gpu_write_list; |
Chris Wilson | cd377ea | 2010-08-07 11:01:24 +0100 | [diff] [blame] | 687 | /** This object's place on eviction list */ |
| 688 | struct list_head evict_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 689 | |
| 690 | /** |
| 691 | * This is set if the object is on the active or flushing lists |
| 692 | * (has pending rendering), and is not set if it's on inactive (ready |
| 693 | * to be unbound). |
| 694 | */ |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 695 | unsigned int active : 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 696 | |
| 697 | /** |
| 698 | * This is set if the object has been written to since last bound |
| 699 | * to the GTT |
| 700 | */ |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 701 | unsigned int dirty : 1; |
| 702 | |
| 703 | /** |
| 704 | * Fence register bits (if any) for this object. Will be set |
| 705 | * as needed when mapped into the GTT. |
| 706 | * Protected by dev->struct_mutex. |
| 707 | * |
| 708 | * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE) |
| 709 | */ |
Chris Wilson | 11824e8 | 2010-06-06 15:40:18 +0100 | [diff] [blame] | 710 | signed int fence_reg : 5; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 711 | |
| 712 | /** |
| 713 | * Used for checking the object doesn't appear more than once |
| 714 | * in an execbuffer object list. |
| 715 | */ |
| 716 | unsigned int in_execbuffer : 1; |
| 717 | |
| 718 | /** |
| 719 | * Advice: are the backing pages purgeable? |
| 720 | */ |
| 721 | unsigned int madv : 2; |
| 722 | |
| 723 | /** |
| 724 | * Refcount for the pages array. With the current locking scheme, there |
| 725 | * are at most two concurrent users: Binding a bo to the gtt and |
| 726 | * pwrite/pread using physical addresses. So two bits for a maximum |
| 727 | * of two users are enough. |
| 728 | */ |
| 729 | unsigned int pages_refcount : 2; |
| 730 | #define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3 |
| 731 | |
| 732 | /** |
| 733 | * Current tiling mode for the object. |
| 734 | */ |
| 735 | unsigned int tiling_mode : 2; |
| 736 | |
| 737 | /** How many users have pinned this object in GTT space. The following |
| 738 | * users can each hold at most one reference: pwrite/pread, pin_ioctl |
| 739 | * (via user_pin_count), execbuffer (objects are not allowed multiple |
| 740 | * times for the same batchbuffer), and the framebuffer code. When |
| 741 | * switching/pageflipping, the framebuffer code has at most two buffers |
| 742 | * pinned per crtc. |
| 743 | * |
| 744 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 |
| 745 | * bits with absolutely no headroom. So use 4 bits. */ |
Chris Wilson | 11824e8 | 2010-06-06 15:40:18 +0100 | [diff] [blame] | 746 | unsigned int pin_count : 4; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 747 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 748 | |
| 749 | /** AGP memory structure for our GTT binding. */ |
| 750 | DRM_AGP_MEM *agp_mem; |
| 751 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 752 | struct page **pages; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 753 | |
| 754 | /** |
| 755 | * Current offset of the object in GTT space. |
| 756 | * |
| 757 | * This is the same as gtt_space->start |
| 758 | */ |
| 759 | uint32_t gtt_offset; |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 760 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 761 | /* Which ring is refering to is this object */ |
| 762 | struct intel_ring_buffer *ring; |
| 763 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 764 | /** |
| 765 | * Fake offset for use by mmap(2) |
| 766 | */ |
| 767 | uint64_t mmap_offset; |
| 768 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 769 | /** Breadcrumb of last rendering to the buffer. */ |
| 770 | uint32_t last_rendering_seqno; |
| 771 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 772 | /** Current tiling stride for the object, if it's tiled. */ |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 773 | uint32_t stride; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 774 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 775 | /** Record of address bit 17 of each page at last unbind. */ |
Chris Wilson | d312ec2 | 2010-06-06 15:40:22 +0100 | [diff] [blame] | 776 | unsigned long *bit_17; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 777 | |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 778 | /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ |
| 779 | uint32_t agp_type; |
| 780 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 781 | /** |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 782 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
| 783 | * flags which individual pages are valid. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 784 | */ |
| 785 | uint8_t *page_cpu_valid; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 786 | |
| 787 | /** User space pin count and filp owning the pin */ |
| 788 | uint32_t user_pin_count; |
| 789 | struct drm_file *pin_filp; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 790 | |
| 791 | /** for phy allocated objects */ |
| 792 | struct drm_i915_gem_phys_object *phys_obj; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 793 | |
| 794 | /** |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 795 | * Number of crtcs where this object is currently the fb, but |
| 796 | * will be page flipped away on the next vblank. When it |
| 797 | * reaches 0, dev_priv->pending_flip_queue will be woken up. |
| 798 | */ |
| 799 | atomic_t pending_flip; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 800 | }; |
| 801 | |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 802 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 803 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 804 | /** |
| 805 | * Request queue structure. |
| 806 | * |
| 807 | * The request queue allows us to note sequence numbers that have been emitted |
| 808 | * and may be associated with active buffers to be retired. |
| 809 | * |
| 810 | * By keeping this list, we can avoid having to do questionable |
| 811 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate |
| 812 | * an emission time with seqnos for tracking how far ahead of the GPU we are. |
| 813 | */ |
| 814 | struct drm_i915_gem_request { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 815 | /** On Which ring this request was generated */ |
| 816 | struct intel_ring_buffer *ring; |
| 817 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 818 | /** GEM sequence number associated with this request. */ |
| 819 | uint32_t seqno; |
| 820 | |
| 821 | /** Time at which this request was emitted, in jiffies. */ |
| 822 | unsigned long emitted_jiffies; |
| 823 | |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 824 | /** global list entry for this request */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 825 | struct list_head list; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 826 | |
| 827 | /** file_priv list entry for this request */ |
| 828 | struct list_head client_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 829 | }; |
| 830 | |
| 831 | struct drm_i915_file_private { |
| 832 | struct { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 833 | struct list_head request_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 834 | } mm; |
| 835 | }; |
| 836 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 837 | enum intel_chip_family { |
| 838 | CHIP_I8XX = 0x01, |
| 839 | CHIP_I9XX = 0x02, |
| 840 | CHIP_I915 = 0x04, |
| 841 | CHIP_I965 = 0x08, |
| 842 | }; |
| 843 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 844 | extern struct drm_ioctl_desc i915_ioctls[]; |
Dave Airlie | b3a8363 | 2005-09-30 18:37:36 +1000 | [diff] [blame] | 845 | extern int i915_max_ioctl; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 846 | extern unsigned int i915_fbpercrtc; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 847 | extern unsigned int i915_powersave; |
Jesse Barnes | 3381434 | 2010-01-14 20:48:02 +0000 | [diff] [blame] | 848 | extern unsigned int i915_lvds_downclock; |
Dave Airlie | b3a8363 | 2005-09-30 18:37:36 +1000 | [diff] [blame] | 849 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 850 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
| 851 | extern int i915_resume(struct drm_device *dev); |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 852 | extern void i915_save_display(struct drm_device *dev); |
| 853 | extern void i915_restore_display(struct drm_device *dev); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 854 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
| 855 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); |
| 856 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 857 | /* i915_dma.c */ |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 858 | extern void i915_kernel_lost_context(struct drm_device * dev); |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 859 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 860 | extern int i915_driver_unload(struct drm_device *); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 861 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 862 | extern void i915_driver_lastclose(struct drm_device * dev); |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 863 | extern void i915_driver_preclose(struct drm_device *dev, |
| 864 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 865 | extern void i915_driver_postclose(struct drm_device *dev, |
| 866 | struct drm_file *file_priv); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 867 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 868 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
| 869 | unsigned long arg); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 870 | extern int i915_emit_box(struct drm_device *dev, |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 871 | struct drm_clip_rect *boxes, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 872 | int i, int DR1, int DR4); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 873 | extern int i965_reset(struct drm_device *dev, u8 flags); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 874 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
| 875 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
| 876 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
| 877 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
| 878 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 879 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 880 | /* i915_irq.c */ |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 881 | void i915_hangcheck_elapsed(unsigned long data); |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 882 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
| 883 | struct drm_file *file_priv); |
| 884 | extern int i915_irq_wait(struct drm_device *dev, void *data, |
| 885 | struct drm_file *file_priv); |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 886 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 887 | extern void i915_enable_interrupt (struct drm_device *dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 888 | |
| 889 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 890 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 891 | extern int i915_driver_irq_postinstall(struct drm_device *dev); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 892 | extern void i915_driver_irq_uninstall(struct drm_device * dev); |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 893 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
| 894 | struct drm_file *file_priv); |
| 895 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
| 896 | struct drm_file *file_priv); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 897 | extern int i915_enable_vblank(struct drm_device *dev, int crtc); |
| 898 | extern void i915_disable_vblank(struct drm_device *dev, int crtc); |
| 899 | extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 900 | extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 901 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
| 902 | struct drm_file *file_priv); |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 903 | extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 904 | extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 905 | extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, |
| 906 | u32 mask); |
| 907 | extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, |
| 908 | u32 mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 909 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 910 | void |
| 911 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
| 912 | |
| 913 | void |
| 914 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
| 915 | |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 916 | void intel_enable_asle (struct drm_device *dev); |
| 917 | |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 918 | #ifdef CONFIG_DEBUG_FS |
| 919 | extern void i915_destroy_error_state(struct drm_device *dev); |
| 920 | #else |
| 921 | #define i915_destroy_error_state(x) |
| 922 | #endif |
| 923 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 924 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 925 | /* i915_mem.c */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 926 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
| 927 | struct drm_file *file_priv); |
| 928 | extern int i915_mem_free(struct drm_device *dev, void *data, |
| 929 | struct drm_file *file_priv); |
| 930 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, |
| 931 | struct drm_file *file_priv); |
| 932 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, |
| 933 | struct drm_file *file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 934 | extern void i915_mem_takedown(struct mem_block **heap); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 935 | extern void i915_mem_release(struct drm_device * dev, |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 936 | struct drm_file *file_priv, struct mem_block *heap); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 937 | /* i915_gem.c */ |
| 938 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 939 | struct drm_file *file_priv); |
| 940 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 941 | struct drm_file *file_priv); |
| 942 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 943 | struct drm_file *file_priv); |
| 944 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 945 | struct drm_file *file_priv); |
| 946 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 947 | struct drm_file *file_priv); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 948 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 949 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 950 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 951 | struct drm_file *file_priv); |
| 952 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 953 | struct drm_file *file_priv); |
| 954 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 955 | struct drm_file *file_priv); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 956 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 957 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 958 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 959 | struct drm_file *file_priv); |
| 960 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 961 | struct drm_file *file_priv); |
| 962 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 963 | struct drm_file *file_priv); |
| 964 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 965 | struct drm_file *file_priv); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 966 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 967 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 968 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 969 | struct drm_file *file_priv); |
| 970 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 971 | struct drm_file *file_priv); |
| 972 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
| 973 | struct drm_file *file_priv); |
| 974 | int i915_gem_get_tiling(struct drm_device *dev, void *data, |
| 975 | struct drm_file *file_priv); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 976 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 977 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 978 | void i915_gem_load(struct drm_device *dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 979 | int i915_gem_init_object(struct drm_gem_object *obj); |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 980 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
| 981 | size_t size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 982 | void i915_gem_free_object(struct drm_gem_object *obj); |
| 983 | int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); |
| 984 | void i915_gem_object_unpin(struct drm_gem_object *obj); |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 985 | int i915_gem_object_unbind(struct drm_gem_object *obj); |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 986 | void i915_gem_release_mmap(struct drm_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 987 | void i915_gem_lastclose(struct drm_device *dev); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 988 | uint32_t i915_get_gem_seqno(struct drm_device *dev, |
| 989 | struct intel_ring_buffer *ring); |
Ben Gamari | 22be172 | 2009-09-14 17:48:43 -0400 | [diff] [blame] | 990 | bool i915_seqno_passed(uint32_t seq1, uint32_t seq2); |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 991 | int i915_gem_object_get_fence_reg(struct drm_gem_object *obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 992 | int i915_gem_object_put_fence_reg(struct drm_gem_object *obj); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 993 | void i915_gem_retire_requests(struct drm_device *dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 994 | void i915_gem_clflush_object(struct drm_gem_object *obj); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 995 | int i915_gem_object_set_domain(struct drm_gem_object *obj, |
| 996 | uint32_t read_domains, |
| 997 | uint32_t write_domain); |
| 998 | int i915_gem_init_ringbuffer(struct drm_device *dev); |
| 999 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
| 1000 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, |
| 1001 | unsigned long end); |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 1002 | int i915_gpu_idle(struct drm_device *dev); |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 1003 | int i915_gem_idle(struct drm_device *dev); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1004 | uint32_t i915_add_request(struct drm_device *dev, |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 1005 | struct drm_file *file_priv, |
| 1006 | struct drm_i915_gem_request *request, |
| 1007 | struct intel_ring_buffer *ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1008 | int i915_do_wait_request(struct drm_device *dev, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1009 | uint32_t seqno, |
| 1010 | bool interruptible, |
| 1011 | struct intel_ring_buffer *ring); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1012 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1013 | void i915_gem_process_flushing_list(struct drm_device *dev, |
| 1014 | uint32_t flush_domains, |
| 1015 | struct intel_ring_buffer *ring); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1016 | int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, |
| 1017 | int write); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 1018 | int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1019 | int i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 1020 | struct drm_gem_object *obj, |
| 1021 | int id, |
| 1022 | int align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1023 | void i915_gem_detach_phys_object(struct drm_device *dev, |
| 1024 | struct drm_gem_object *obj); |
| 1025 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 1026 | int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask); |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 1027 | void i915_gem_object_put_pages(struct drm_gem_object *obj); |
Eric Anholt | 1fd1c62 | 2009-06-03 07:26:58 +0000 | [diff] [blame] | 1028 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 1029 | int i915_gem_object_flush_write_domain(struct drm_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1030 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 1031 | void i915_gem_shrinker_init(void); |
| 1032 | void i915_gem_shrinker_exit(void); |
| 1033 | |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 1034 | /* i915_gem_evict.c */ |
| 1035 | int i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignment); |
| 1036 | int i915_gem_evict_everything(struct drm_device *dev); |
| 1037 | int i915_gem_evict_inactive(struct drm_device *dev); |
| 1038 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1039 | /* i915_gem_tiling.c */ |
| 1040 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1041 | void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); |
| 1042 | void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 1043 | bool i915_tiling_ok(struct drm_device *dev, int stride, int size, |
| 1044 | int tiling_mode); |
Owain Ainsworth | f590d27 | 2010-02-18 15:33:00 +0000 | [diff] [blame] | 1045 | bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, |
| 1046 | int tiling_mode); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1047 | |
| 1048 | /* i915_gem_debug.c */ |
| 1049 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, |
| 1050 | const char *where, uint32_t mark); |
| 1051 | #if WATCH_INACTIVE |
| 1052 | void i915_verify_inactive(struct drm_device *dev, char *file, int line); |
| 1053 | #else |
| 1054 | #define i915_verify_inactive(dev, file, line) |
| 1055 | #endif |
| 1056 | void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); |
| 1057 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, |
| 1058 | const char *where, uint32_t mark); |
| 1059 | void i915_dump_lru(struct drm_device *dev, const char *where); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1060 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1061 | /* i915_debugfs.c */ |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 1062 | int i915_debugfs_init(struct drm_minor *minor); |
| 1063 | void i915_debugfs_cleanup(struct drm_minor *minor); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1064 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 1065 | /* i915_suspend.c */ |
| 1066 | extern int i915_save_state(struct drm_device *dev); |
| 1067 | extern int i915_restore_state(struct drm_device *dev); |
| 1068 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1069 | /* i915_suspend.c */ |
| 1070 | extern int i915_save_state(struct drm_device *dev); |
| 1071 | extern int i915_restore_state(struct drm_device *dev); |
| 1072 | |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 1073 | /* intel_opregion.c */ |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1074 | extern int intel_opregion_setup(struct drm_device *dev); |
| 1075 | #ifdef CONFIG_ACPI |
| 1076 | extern void intel_opregion_init(struct drm_device *dev); |
| 1077 | extern void intel_opregion_fini(struct drm_device *dev); |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 1078 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
| 1079 | extern void intel_opregion_gse_intr(struct drm_device *dev); |
| 1080 | extern void intel_opregion_enable_asle(struct drm_device *dev); |
Len Brown | 65e082c | 2008-10-24 17:18:10 -0400 | [diff] [blame] | 1081 | #else |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1082 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
| 1083 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 1084 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
| 1085 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } |
| 1086 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } |
Len Brown | 65e082c | 2008-10-24 17:18:10 -0400 | [diff] [blame] | 1087 | #endif |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1088 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1089 | /* modesetting */ |
| 1090 | extern void intel_modeset_init(struct drm_device *dev); |
| 1091 | extern void intel_modeset_cleanup(struct drm_device *dev); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1092 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1093 | extern void i8xx_disable_fbc(struct drm_device *dev); |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1094 | extern void g4x_disable_fbc(struct drm_device *dev); |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1095 | extern void ironlake_disable_fbc(struct drm_device *dev); |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1096 | extern void intel_disable_fbc(struct drm_device *dev); |
| 1097 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); |
| 1098 | extern bool intel_fbc_enabled(struct drm_device *dev); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1099 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 1100 | extern void intel_detect_pch (struct drm_device *dev); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1101 | extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 1102 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1103 | /* overlay */ |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 1104 | #ifdef CONFIG_DEBUG_FS |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1105 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
| 1106 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 1107 | #endif |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1108 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 1109 | /** |
| 1110 | * Lock test for when it's just for synchronization of ring access. |
| 1111 | * |
| 1112 | * In that case, we don't need to do it when GEM is initialized as nobody else |
| 1113 | * has access to the ring. |
| 1114 | */ |
| 1115 | #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1116 | if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \ |
| 1117 | == NULL) \ |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 1118 | LOCK_TEST_WITH_RETURN(dev, file_priv); \ |
| 1119 | } while (0) |
| 1120 | |
Jesse Barnes | be282fd | 2010-08-13 15:50:28 -0700 | [diff] [blame] | 1121 | static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg) |
| 1122 | { |
| 1123 | u32 val; |
| 1124 | |
| 1125 | val = readl(dev_priv->regs + reg); |
| 1126 | if (dev_priv->debug_flags & I915_DEBUG_READ) |
| 1127 | printk(KERN_ERR "read 0x%08x from 0x%08x\n", val, reg); |
| 1128 | return val; |
| 1129 | } |
| 1130 | |
| 1131 | static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg, |
| 1132 | u32 val) |
| 1133 | { |
| 1134 | writel(val, dev_priv->regs + reg); |
| 1135 | if (dev_priv->debug_flags & I915_DEBUG_WRITE) |
| 1136 | printk(KERN_ERR "wrote 0x%08x to 0x%08x\n", val, reg); |
| 1137 | } |
| 1138 | |
| 1139 | #define I915_READ(reg) i915_read(dev_priv, (reg)) |
| 1140 | #define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val)) |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 1141 | #define I915_READ16(reg) readw(dev_priv->regs + (reg)) |
| 1142 | #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg)) |
| 1143 | #define I915_READ8(reg) readb(dev_priv->regs + (reg)) |
| 1144 | #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1145 | #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg)) |
Keith Packard | 049ef7e | 2009-04-30 14:43:43 -0700 | [diff] [blame] | 1146 | #define I915_READ64(reg) readq(dev_priv->regs + (reg)) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 1147 | #define POSTING_READ(reg) (void)I915_READ(reg) |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1148 | #define POSTING_READ16(reg) (void)I915_READ16(reg) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1149 | |
Jesse Barnes | be282fd | 2010-08-13 15:50:28 -0700 | [diff] [blame] | 1150 | #define I915_DEBUG_ENABLE_IO() (dev_priv->debug_flags |= I915_DEBUG_READ | \ |
| 1151 | I915_DEBUG_WRITE) |
| 1152 | #define I915_DEBUG_DISABLE_IO() (dev_priv->debug_flags &= ~(I915_DEBUG_READ | \ |
| 1153 | I915_DEBUG_WRITE)) |
| 1154 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1155 | #define I915_VERBOSE 0 |
| 1156 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1157 | #define BEGIN_LP_RING(n) do { \ |
Chris Wilson | dbd7ac9 | 2010-08-04 15:18:15 +0100 | [diff] [blame] | 1158 | drm_i915_private_t *dev_priv__ = dev->dev_private; \ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1159 | if (I915_VERBOSE) \ |
| 1160 | DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \ |
Chris Wilson | dbd7ac9 | 2010-08-04 15:18:15 +0100 | [diff] [blame] | 1161 | intel_ring_begin(dev, &dev_priv__->render_ring, (n)); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1162 | } while (0) |
| 1163 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1164 | |
| 1165 | #define OUT_RING(x) do { \ |
Chris Wilson | dbd7ac9 | 2010-08-04 15:18:15 +0100 | [diff] [blame] | 1166 | drm_i915_private_t *dev_priv__ = dev->dev_private; \ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1167 | if (I915_VERBOSE) \ |
| 1168 | DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \ |
Chris Wilson | dbd7ac9 | 2010-08-04 15:18:15 +0100 | [diff] [blame] | 1169 | intel_ring_emit(dev, &dev_priv__->render_ring, x); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1170 | } while (0) |
| 1171 | |
| 1172 | #define ADVANCE_LP_RING() do { \ |
Chris Wilson | dbd7ac9 | 2010-08-04 15:18:15 +0100 | [diff] [blame] | 1173 | drm_i915_private_t *dev_priv__ = dev->dev_private; \ |
Chris Wilson | 0ef82af | 2009-09-05 18:07:06 +0100 | [diff] [blame] | 1174 | if (I915_VERBOSE) \ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1175 | DRM_DEBUG("ADVANCE_LP_RING %x\n", \ |
Chris Wilson | dbd7ac9 | 2010-08-04 15:18:15 +0100 | [diff] [blame] | 1176 | dev_priv__->render_ring.tail); \ |
| 1177 | intel_ring_advance(dev, &dev_priv__->render_ring); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1178 | } while(0) |
| 1179 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1180 | /** |
| 1181 | * Reads a dword out of the status page, which is written to from the command |
| 1182 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or |
| 1183 | * MI_STORE_DATA_IMM. |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1184 | * |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1185 | * The following dwords have a reserved meaning: |
Keith Packard | 0cdad7e | 2008-10-14 17:19:38 -0700 | [diff] [blame] | 1186 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
| 1187 | * 0x04: ring 0 head pointer |
| 1188 | * 0x05: ring 1 head pointer (915-class) |
| 1189 | * 0x06: ring 2 head pointer (915-class) |
| 1190 | * 0x10-0x1b: Context status DWords (GM45) |
| 1191 | * 0x1f: Last written status offset. (GM45) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1192 | * |
Keith Packard | 0cdad7e | 2008-10-14 17:19:38 -0700 | [diff] [blame] | 1193 | * The area from dword 0x20 to 0x3ff is available for driver usage. |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1194 | */ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1195 | #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\ |
| 1196 | (dev_priv->render_ring.status_page.page_addr))[reg]) |
Keith Packard | 0baf823 | 2008-11-08 11:44:14 +1000 | [diff] [blame] | 1197 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
Keith Packard | 0cdad7e | 2008-10-14 17:19:38 -0700 | [diff] [blame] | 1198 | #define I915_GEM_HWS_INDEX 0x20 |
Keith Packard | 0baf823 | 2008-11-08 11:44:14 +1000 | [diff] [blame] | 1199 | #define I915_BREADCRUMB_INDEX 0x21 |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1200 | |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 1201 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1202 | |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 1203 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) |
| 1204 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) |
Adam Jackson | 5ce8ba7 | 2010-04-15 14:03:30 -0400 | [diff] [blame] | 1205 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 1206 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 1207 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
| 1208 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) |
| 1209 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) |
| 1210 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
| 1211 | #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g) |
| 1212 | #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm) |
Chris Wilson | 534843d | 2010-07-05 18:01:46 +0100 | [diff] [blame] | 1213 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
| 1214 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 1215 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
| 1216 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
| 1217 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) |
| 1218 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) |
| 1219 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
| 1220 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1221 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) |
| 1222 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 1223 | #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake) |
| 1224 | #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx) |
| 1225 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
Zhenyu Wang | 280da22 | 2009-06-05 15:38:37 +0800 | [diff] [blame] | 1226 | |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 1227 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
| 1228 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) |
| 1229 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) |
| 1230 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) |
| 1231 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1232 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1233 | #define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev)) |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 1234 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1235 | |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 1236 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
| 1237 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
| 1238 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1239 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
| 1240 | * rows, which changed the alignment requirements and fence programming. |
| 1241 | */ |
| 1242 | #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ |
| 1243 | IS_I915GM(dev))) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1244 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev)) |
| 1245 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
| 1246 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
| 1247 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) |
Zhenyu Wang | 103a196 | 2009-11-27 11:44:36 +0800 | [diff] [blame] | 1248 | #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \ |
Zhenyu Wang | 7da9f6c | 2010-04-07 16:15:52 +0800 | [diff] [blame] | 1249 | !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \ |
| 1250 | !IS_GEN6(dev)) |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 1251 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 1252 | /* dsparb controlled by hw only */ |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1253 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
Zhenyu Wang | b39d50e | 2008-02-19 20:59:09 +1000 | [diff] [blame] | 1254 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1255 | #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev)) |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 1256 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
| 1257 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
| 1258 | #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1259 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1260 | #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \ |
| 1261 | IS_GEN6(dev)) |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 1262 | #define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev)) |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1263 | |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 1264 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
| 1265 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
| 1266 | |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1267 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1268 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1269 | #endif |