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Graeme Gregory518fb722011-05-02 16:20:08 -05001/*
2 * tps65910.c -- TI tps65910
3 *
4 * Copyright 2010 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/err.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
Graeme Gregory518fb722011-05-02 16:20:08 -050023#include <linux/slab.h>
24#include <linux/gpio.h>
25#include <linux/mfd/tps65910.h>
Rhyland Klein67901782012-05-08 11:42:41 -070026#include <linux/regulator/of_regulator.h>
Graeme Gregory518fb722011-05-02 16:20:08 -050027
Graeme Gregory518fb722011-05-02 16:20:08 -050028#define TPS65910_SUPPLY_STATE_ENABLED 0x1
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +053029#define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \
30 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \
Laxman Dewanganf30b0712012-03-07 18:21:49 +053031 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \
32 TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
Graeme Gregory518fb722011-05-02 16:20:08 -050033
Axel Lind9fe28f2012-06-21 18:48:00 +080034/* supported VIO voltages in microvolts */
35static const unsigned int VIO_VSEL_table[] = {
36 1500000, 1800000, 2500000, 3300000,
Graeme Gregory518fb722011-05-02 16:20:08 -050037};
38
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -050039/* VSEL tables for TPS65910 specific LDOs and dcdc's */
40
AnilKumar Cha9a56592012-10-15 17:45:58 +053041/* supported VRTC voltages in microvolts */
42static const unsigned int VRTC_VSEL_table[] = {
43 1800000,
44};
45
Axel Lind9fe28f2012-06-21 18:48:00 +080046/* supported VDD3 voltages in microvolts */
47static const unsigned int VDD3_VSEL_table[] = {
48 5000000,
Graeme Gregory518fb722011-05-02 16:20:08 -050049};
50
Axel Lind9fe28f2012-06-21 18:48:00 +080051/* supported VDIG1 voltages in microvolts */
52static const unsigned int VDIG1_VSEL_table[] = {
53 1200000, 1500000, 1800000, 2700000,
Graeme Gregory518fb722011-05-02 16:20:08 -050054};
55
Axel Lind9fe28f2012-06-21 18:48:00 +080056/* supported VDIG2 voltages in microvolts */
57static const unsigned int VDIG2_VSEL_table[] = {
58 1000000, 1100000, 1200000, 1800000,
Graeme Gregory518fb722011-05-02 16:20:08 -050059};
60
Axel Lind9fe28f2012-06-21 18:48:00 +080061/* supported VPLL voltages in microvolts */
62static const unsigned int VPLL_VSEL_table[] = {
63 1000000, 1100000, 1800000, 2500000,
Graeme Gregory518fb722011-05-02 16:20:08 -050064};
65
Axel Lind9fe28f2012-06-21 18:48:00 +080066/* supported VDAC voltages in microvolts */
67static const unsigned int VDAC_VSEL_table[] = {
68 1800000, 2600000, 2800000, 2850000,
Graeme Gregory518fb722011-05-02 16:20:08 -050069};
70
Axel Lind9fe28f2012-06-21 18:48:00 +080071/* supported VAUX1 voltages in microvolts */
72static const unsigned int VAUX1_VSEL_table[] = {
73 1800000, 2500000, 2800000, 2850000,
Graeme Gregory518fb722011-05-02 16:20:08 -050074};
75
Axel Lind9fe28f2012-06-21 18:48:00 +080076/* supported VAUX2 voltages in microvolts */
77static const unsigned int VAUX2_VSEL_table[] = {
78 1800000, 2800000, 2900000, 3300000,
Graeme Gregory518fb722011-05-02 16:20:08 -050079};
80
Axel Lind9fe28f2012-06-21 18:48:00 +080081/* supported VAUX33 voltages in microvolts */
82static const unsigned int VAUX33_VSEL_table[] = {
83 1800000, 2000000, 2800000, 3300000,
Graeme Gregory518fb722011-05-02 16:20:08 -050084};
85
Axel Lind9fe28f2012-06-21 18:48:00 +080086/* supported VMMC voltages in microvolts */
87static const unsigned int VMMC_VSEL_table[] = {
88 1800000, 2800000, 3000000, 3300000,
Graeme Gregory518fb722011-05-02 16:20:08 -050089};
90
91struct tps_info {
92 const char *name;
Laxman Dewangan19228a62012-07-06 14:13:12 +053093 const char *vin_name;
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +053094 u8 n_voltages;
Axel Lind9fe28f2012-06-21 18:48:00 +080095 const unsigned int *voltage_table;
Laxman Dewangan0651eed2012-03-13 11:35:20 +053096 int enable_time_us;
Graeme Gregory518fb722011-05-02 16:20:08 -050097};
98
99static struct tps_info tps65910_regs[] = {
100 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530101 .name = "vrtc",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530102 .vin_name = "vcc7",
AnilKumar Cha9a56592012-10-15 17:45:58 +0530103 .n_voltages = ARRAY_SIZE(VRTC_VSEL_table),
104 .voltage_table = VRTC_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530105 .enable_time_us = 2200,
Graeme Gregory518fb722011-05-02 16:20:08 -0500106 },
107 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530108 .name = "vio",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530109 .vin_name = "vccio",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530110 .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
111 .voltage_table = VIO_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530112 .enable_time_us = 350,
Graeme Gregory518fb722011-05-02 16:20:08 -0500113 },
114 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530115 .name = "vdd1",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530116 .vin_name = "vcc1",
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530117 .enable_time_us = 350,
Graeme Gregory518fb722011-05-02 16:20:08 -0500118 },
119 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530120 .name = "vdd2",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530121 .vin_name = "vcc2",
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530122 .enable_time_us = 350,
Graeme Gregory518fb722011-05-02 16:20:08 -0500123 },
124 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530125 .name = "vdd3",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530126 .n_voltages = ARRAY_SIZE(VDD3_VSEL_table),
127 .voltage_table = VDD3_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530128 .enable_time_us = 200,
Graeme Gregory518fb722011-05-02 16:20:08 -0500129 },
130 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530131 .name = "vdig1",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530132 .vin_name = "vcc6",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530133 .n_voltages = ARRAY_SIZE(VDIG1_VSEL_table),
134 .voltage_table = VDIG1_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530135 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500136 },
137 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530138 .name = "vdig2",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530139 .vin_name = "vcc6",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530140 .n_voltages = ARRAY_SIZE(VDIG2_VSEL_table),
141 .voltage_table = VDIG2_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530142 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500143 },
144 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530145 .name = "vpll",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530146 .vin_name = "vcc5",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530147 .n_voltages = ARRAY_SIZE(VPLL_VSEL_table),
148 .voltage_table = VPLL_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530149 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500150 },
151 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530152 .name = "vdac",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530153 .vin_name = "vcc5",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530154 .n_voltages = ARRAY_SIZE(VDAC_VSEL_table),
155 .voltage_table = VDAC_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530156 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500157 },
158 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530159 .name = "vaux1",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530160 .vin_name = "vcc4",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530161 .n_voltages = ARRAY_SIZE(VAUX1_VSEL_table),
162 .voltage_table = VAUX1_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530163 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500164 },
165 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530166 .name = "vaux2",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530167 .vin_name = "vcc4",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530168 .n_voltages = ARRAY_SIZE(VAUX2_VSEL_table),
169 .voltage_table = VAUX2_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530170 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500171 },
172 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530173 .name = "vaux33",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530174 .vin_name = "vcc3",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530175 .n_voltages = ARRAY_SIZE(VAUX33_VSEL_table),
176 .voltage_table = VAUX33_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530177 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500178 },
179 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530180 .name = "vmmc",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530181 .vin_name = "vcc3",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530182 .n_voltages = ARRAY_SIZE(VMMC_VSEL_table),
183 .voltage_table = VMMC_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530184 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500185 },
186};
187
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500188static struct tps_info tps65911_regs[] = {
189 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530190 .name = "vrtc",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530191 .vin_name = "vcc7",
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530192 .enable_time_us = 2200,
Laxman Dewanganc2f8efd2012-01-18 20:46:56 +0530193 },
194 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530195 .name = "vio",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530196 .vin_name = "vccio",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530197 .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
198 .voltage_table = VIO_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530199 .enable_time_us = 350,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500200 },
201 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530202 .name = "vdd1",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530203 .vin_name = "vcc1",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530204 .n_voltages = 0x4C,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530205 .enable_time_us = 350,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500206 },
207 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530208 .name = "vdd2",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530209 .vin_name = "vcc2",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530210 .n_voltages = 0x4C,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530211 .enable_time_us = 350,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500212 },
213 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530214 .name = "vddctrl",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530215 .n_voltages = 0x44,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530216 .enable_time_us = 900,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500217 },
218 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530219 .name = "ldo1",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530220 .vin_name = "vcc6",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530221 .n_voltages = 0x33,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530222 .enable_time_us = 420,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500223 },
224 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530225 .name = "ldo2",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530226 .vin_name = "vcc6",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530227 .n_voltages = 0x33,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530228 .enable_time_us = 420,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500229 },
230 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530231 .name = "ldo3",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530232 .vin_name = "vcc5",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530233 .n_voltages = 0x1A,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530234 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500235 },
236 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530237 .name = "ldo4",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530238 .vin_name = "vcc5",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530239 .n_voltages = 0x33,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530240 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500241 },
242 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530243 .name = "ldo5",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530244 .vin_name = "vcc4",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530245 .n_voltages = 0x1A,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530246 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500247 },
248 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530249 .name = "ldo6",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530250 .vin_name = "vcc3",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530251 .n_voltages = 0x1A,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530252 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500253 },
254 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530255 .name = "ldo7",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530256 .vin_name = "vcc3",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530257 .n_voltages = 0x1A,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530258 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500259 },
260 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530261 .name = "ldo8",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530262 .vin_name = "vcc3",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530263 .n_voltages = 0x1A,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530264 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500265 },
266};
267
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530268#define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits))
269static unsigned int tps65910_ext_sleep_control[] = {
270 0,
271 EXT_CONTROL_REG_BITS(VIO, 1, 0),
272 EXT_CONTROL_REG_BITS(VDD1, 1, 1),
273 EXT_CONTROL_REG_BITS(VDD2, 1, 2),
274 EXT_CONTROL_REG_BITS(VDD3, 1, 3),
275 EXT_CONTROL_REG_BITS(VDIG1, 0, 1),
276 EXT_CONTROL_REG_BITS(VDIG2, 0, 2),
277 EXT_CONTROL_REG_BITS(VPLL, 0, 6),
278 EXT_CONTROL_REG_BITS(VDAC, 0, 7),
279 EXT_CONTROL_REG_BITS(VAUX1, 0, 3),
280 EXT_CONTROL_REG_BITS(VAUX2, 0, 4),
281 EXT_CONTROL_REG_BITS(VAUX33, 0, 5),
282 EXT_CONTROL_REG_BITS(VMMC, 0, 0),
283};
284
285static unsigned int tps65911_ext_sleep_control[] = {
286 0,
287 EXT_CONTROL_REG_BITS(VIO, 1, 0),
288 EXT_CONTROL_REG_BITS(VDD1, 1, 1),
289 EXT_CONTROL_REG_BITS(VDD2, 1, 2),
290 EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3),
291 EXT_CONTROL_REG_BITS(LDO1, 0, 1),
292 EXT_CONTROL_REG_BITS(LDO2, 0, 2),
293 EXT_CONTROL_REG_BITS(LDO3, 0, 7),
294 EXT_CONTROL_REG_BITS(LDO4, 0, 6),
295 EXT_CONTROL_REG_BITS(LDO5, 0, 3),
296 EXT_CONTROL_REG_BITS(LDO6, 0, 0),
297 EXT_CONTROL_REG_BITS(LDO7, 0, 5),
298 EXT_CONTROL_REG_BITS(LDO8, 0, 4),
299};
300
Graeme Gregory518fb722011-05-02 16:20:08 -0500301struct tps65910_reg {
Axel Lin39aa9b62011-07-11 09:57:43 +0800302 struct regulator_desc *desc;
Graeme Gregory518fb722011-05-02 16:20:08 -0500303 struct tps65910 *mfd;
Axel Lin39aa9b62011-07-11 09:57:43 +0800304 struct regulator_dev **rdev;
305 struct tps_info **info;
Axel Lin39aa9b62011-07-11 09:57:43 +0800306 int num_regulators;
Graeme Gregory518fb722011-05-02 16:20:08 -0500307 int mode;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500308 int (*get_ctrl_reg)(int);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530309 unsigned int *ext_sleep_control;
310 unsigned int board_ext_control[TPS65910_NUM_REGS];
Graeme Gregory518fb722011-05-02 16:20:08 -0500311};
312
Graeme Gregory518fb722011-05-02 16:20:08 -0500313static int tps65910_get_ctrl_register(int id)
314{
315 switch (id) {
316 case TPS65910_REG_VRTC:
317 return TPS65910_VRTC;
318 case TPS65910_REG_VIO:
319 return TPS65910_VIO;
320 case TPS65910_REG_VDD1:
321 return TPS65910_VDD1;
322 case TPS65910_REG_VDD2:
323 return TPS65910_VDD2;
324 case TPS65910_REG_VDD3:
325 return TPS65910_VDD3;
326 case TPS65910_REG_VDIG1:
327 return TPS65910_VDIG1;
328 case TPS65910_REG_VDIG2:
329 return TPS65910_VDIG2;
330 case TPS65910_REG_VPLL:
331 return TPS65910_VPLL;
332 case TPS65910_REG_VDAC:
333 return TPS65910_VDAC;
334 case TPS65910_REG_VAUX1:
335 return TPS65910_VAUX1;
336 case TPS65910_REG_VAUX2:
337 return TPS65910_VAUX2;
338 case TPS65910_REG_VAUX33:
339 return TPS65910_VAUX33;
340 case TPS65910_REG_VMMC:
341 return TPS65910_VMMC;
342 default:
343 return -EINVAL;
344 }
345}
346
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500347static int tps65911_get_ctrl_register(int id)
348{
349 switch (id) {
350 case TPS65910_REG_VRTC:
351 return TPS65910_VRTC;
352 case TPS65910_REG_VIO:
353 return TPS65910_VIO;
354 case TPS65910_REG_VDD1:
355 return TPS65910_VDD1;
356 case TPS65910_REG_VDD2:
357 return TPS65910_VDD2;
358 case TPS65911_REG_VDDCTRL:
359 return TPS65911_VDDCTRL;
360 case TPS65911_REG_LDO1:
361 return TPS65911_LDO1;
362 case TPS65911_REG_LDO2:
363 return TPS65911_LDO2;
364 case TPS65911_REG_LDO3:
365 return TPS65911_LDO3;
366 case TPS65911_REG_LDO4:
367 return TPS65911_LDO4;
368 case TPS65911_REG_LDO5:
369 return TPS65911_LDO5;
370 case TPS65911_REG_LDO6:
371 return TPS65911_LDO6;
372 case TPS65911_REG_LDO7:
373 return TPS65911_LDO7;
374 case TPS65911_REG_LDO8:
375 return TPS65911_LDO8;
376 default:
377 return -EINVAL;
378 }
379}
380
Graeme Gregory518fb722011-05-02 16:20:08 -0500381static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode)
382{
383 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
384 struct tps65910 *mfd = pmic->mfd;
385 int reg, value, id = rdev_get_id(dev);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500386
387 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500388 if (reg < 0)
389 return reg;
390
391 switch (mode) {
392 case REGULATOR_MODE_NORMAL:
Axel Linfaa95fd2012-07-11 19:44:13 +0800393 return tps65910_reg_update_bits(pmic->mfd, reg,
394 LDO_ST_MODE_BIT | LDO_ST_ON_BIT,
395 LDO_ST_ON_BIT);
Graeme Gregory518fb722011-05-02 16:20:08 -0500396 case REGULATOR_MODE_IDLE:
397 value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT;
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700398 return tps65910_reg_set_bits(mfd, reg, value);
Graeme Gregory518fb722011-05-02 16:20:08 -0500399 case REGULATOR_MODE_STANDBY:
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700400 return tps65910_reg_clear_bits(mfd, reg, LDO_ST_ON_BIT);
Graeme Gregory518fb722011-05-02 16:20:08 -0500401 }
402
403 return -EINVAL;
404}
405
406static unsigned int tps65910_get_mode(struct regulator_dev *dev)
407{
408 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
Axel Linfaa95fd2012-07-11 19:44:13 +0800409 int ret, reg, value, id = rdev_get_id(dev);
Graeme Gregory518fb722011-05-02 16:20:08 -0500410
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500411 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500412 if (reg < 0)
413 return reg;
414
Axel Linfaa95fd2012-07-11 19:44:13 +0800415 ret = tps65910_reg_read(pmic->mfd, reg, &value);
416 if (ret < 0)
417 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500418
Axel Lin58599392012-03-13 07:15:27 +0800419 if (!(value & LDO_ST_ON_BIT))
Graeme Gregory518fb722011-05-02 16:20:08 -0500420 return REGULATOR_MODE_STANDBY;
421 else if (value & LDO_ST_MODE_BIT)
422 return REGULATOR_MODE_IDLE;
423 else
424 return REGULATOR_MODE_NORMAL;
425}
426
Laxman Dewangan18039e02012-03-14 13:00:58 +0530427static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev)
Graeme Gregory518fb722011-05-02 16:20:08 -0500428{
429 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
Axel Linfaa95fd2012-07-11 19:44:13 +0800430 int ret, id = rdev_get_id(dev);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500431 int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0;
Graeme Gregory518fb722011-05-02 16:20:08 -0500432
433 switch (id) {
434 case TPS65910_REG_VDD1:
Axel Linfaa95fd2012-07-11 19:44:13 +0800435 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1_OP, &opvsel);
436 if (ret < 0)
437 return ret;
438 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1, &mult);
439 if (ret < 0)
440 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500441 mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT;
Axel Linfaa95fd2012-07-11 19:44:13 +0800442 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1_SR, &srvsel);
443 if (ret < 0)
444 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500445 sr = opvsel & VDD1_OP_CMD_MASK;
446 opvsel &= VDD1_OP_SEL_MASK;
447 srvsel &= VDD1_SR_SEL_MASK;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500448 vselmax = 75;
Graeme Gregory518fb722011-05-02 16:20:08 -0500449 break;
450 case TPS65910_REG_VDD2:
Axel Linfaa95fd2012-07-11 19:44:13 +0800451 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2_OP, &opvsel);
452 if (ret < 0)
453 return ret;
454 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2, &mult);
455 if (ret < 0)
456 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500457 mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT;
Axel Linfaa95fd2012-07-11 19:44:13 +0800458 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2_SR, &srvsel);
459 if (ret < 0)
460 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500461 sr = opvsel & VDD2_OP_CMD_MASK;
462 opvsel &= VDD2_OP_SEL_MASK;
463 srvsel &= VDD2_SR_SEL_MASK;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500464 vselmax = 75;
465 break;
466 case TPS65911_REG_VDDCTRL:
Axel Linfaa95fd2012-07-11 19:44:13 +0800467 ret = tps65910_reg_read(pmic->mfd, TPS65911_VDDCTRL_OP,
468 &opvsel);
469 if (ret < 0)
470 return ret;
471 ret = tps65910_reg_read(pmic->mfd, TPS65911_VDDCTRL_SR,
472 &srvsel);
473 if (ret < 0)
474 return ret;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500475 sr = opvsel & VDDCTRL_OP_CMD_MASK;
476 opvsel &= VDDCTRL_OP_SEL_MASK;
477 srvsel &= VDDCTRL_SR_SEL_MASK;
478 vselmax = 64;
Graeme Gregory518fb722011-05-02 16:20:08 -0500479 break;
480 }
481
482 /* multiplier 0 == 1 but 2,3 normal */
483 if (!mult)
484 mult=1;
485
486 if (sr) {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500487 /* normalise to valid range */
488 if (srvsel < 3)
489 srvsel = 3;
490 if (srvsel > vselmax)
491 srvsel = vselmax;
Laxman Dewangan18039e02012-03-14 13:00:58 +0530492 return srvsel - 3;
Graeme Gregory518fb722011-05-02 16:20:08 -0500493 } else {
494
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500495 /* normalise to valid range*/
496 if (opvsel < 3)
497 opvsel = 3;
498 if (opvsel > vselmax)
499 opvsel = vselmax;
Laxman Dewangan18039e02012-03-14 13:00:58 +0530500 return opvsel - 3;
Graeme Gregory518fb722011-05-02 16:20:08 -0500501 }
Laxman Dewangan18039e02012-03-14 13:00:58 +0530502 return -EINVAL;
Graeme Gregory518fb722011-05-02 16:20:08 -0500503}
504
Axel Lin1f904fd2012-05-09 09:22:47 +0800505static int tps65910_get_voltage_sel(struct regulator_dev *dev)
Graeme Gregory518fb722011-05-02 16:20:08 -0500506{
507 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
Axel Linfaa95fd2012-07-11 19:44:13 +0800508 int ret, reg, value, id = rdev_get_id(dev);
Graeme Gregory518fb722011-05-02 16:20:08 -0500509
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500510 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500511 if (reg < 0)
512 return reg;
513
Axel Linfaa95fd2012-07-11 19:44:13 +0800514 ret = tps65910_reg_read(pmic->mfd, reg, &value);
515 if (ret < 0)
516 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500517
518 switch (id) {
519 case TPS65910_REG_VIO:
520 case TPS65910_REG_VDIG1:
521 case TPS65910_REG_VDIG2:
522 case TPS65910_REG_VPLL:
523 case TPS65910_REG_VDAC:
524 case TPS65910_REG_VAUX1:
525 case TPS65910_REG_VAUX2:
526 case TPS65910_REG_VAUX33:
527 case TPS65910_REG_VMMC:
528 value &= LDO_SEL_MASK;
529 value >>= LDO_SEL_SHIFT;
530 break;
531 default:
532 return -EINVAL;
533 }
534
Axel Lin1f904fd2012-05-09 09:22:47 +0800535 return value;
Graeme Gregory518fb722011-05-02 16:20:08 -0500536}
537
538static int tps65910_get_voltage_vdd3(struct regulator_dev *dev)
539{
Axel Lind9fe28f2012-06-21 18:48:00 +0800540 return dev->desc->volt_table[0];
Graeme Gregory518fb722011-05-02 16:20:08 -0500541}
542
Axel Lin1f904fd2012-05-09 09:22:47 +0800543static int tps65911_get_voltage_sel(struct regulator_dev *dev)
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500544{
545 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
Axel Linfaa95fd2012-07-11 19:44:13 +0800546 int ret, id = rdev_get_id(dev);
547 unsigned int value, reg;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500548
549 reg = pmic->get_ctrl_reg(id);
550
Axel Linfaa95fd2012-07-11 19:44:13 +0800551 ret = tps65910_reg_read(pmic->mfd, reg, &value);
552 if (ret < 0)
553 return ret;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500554
555 switch (id) {
556 case TPS65911_REG_LDO1:
557 case TPS65911_REG_LDO2:
558 case TPS65911_REG_LDO4:
559 value &= LDO1_SEL_MASK;
560 value >>= LDO_SEL_SHIFT;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500561 break;
562 case TPS65911_REG_LDO3:
563 case TPS65911_REG_LDO5:
564 case TPS65911_REG_LDO6:
565 case TPS65911_REG_LDO7:
566 case TPS65911_REG_LDO8:
567 value &= LDO3_SEL_MASK;
568 value >>= LDO_SEL_SHIFT;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500569 break;
570 case TPS65910_REG_VIO:
Laxman Dewangane882eae2012-02-17 18:56:11 +0530571 value &= LDO_SEL_MASK;
572 value >>= LDO_SEL_SHIFT;
Axel Lin1f904fd2012-05-09 09:22:47 +0800573 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500574 default:
575 return -EINVAL;
576 }
577
Axel Lin1f904fd2012-05-09 09:22:47 +0800578 return value;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500579}
580
Axel Lin94732b92012-03-09 10:22:20 +0800581static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev,
582 unsigned selector)
Graeme Gregory518fb722011-05-02 16:20:08 -0500583{
584 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
585 int id = rdev_get_id(dev), vsel;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500586 int dcdc_mult = 0;
Graeme Gregory518fb722011-05-02 16:20:08 -0500587
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500588 switch (id) {
589 case TPS65910_REG_VDD1:
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530590 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500591 if (dcdc_mult == 1)
592 dcdc_mult--;
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530593 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
Graeme Gregory518fb722011-05-02 16:20:08 -0500594
Axel Linfaa95fd2012-07-11 19:44:13 +0800595 tps65910_reg_update_bits(pmic->mfd, TPS65910_VDD1,
596 VDD1_VGAIN_SEL_MASK,
597 dcdc_mult << VDD1_VGAIN_SEL_SHIFT);
598 tps65910_reg_write(pmic->mfd, TPS65910_VDD1_OP, vsel);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500599 break;
600 case TPS65910_REG_VDD2:
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530601 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500602 if (dcdc_mult == 1)
603 dcdc_mult--;
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530604 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500605
Axel Linfaa95fd2012-07-11 19:44:13 +0800606 tps65910_reg_update_bits(pmic->mfd, TPS65910_VDD2,
607 VDD1_VGAIN_SEL_MASK,
608 dcdc_mult << VDD2_VGAIN_SEL_SHIFT);
609 tps65910_reg_write(pmic->mfd, TPS65910_VDD2_OP, vsel);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500610 break;
611 case TPS65911_REG_VDDCTRL:
Laxman Dewanganc4632ae2012-03-07 16:39:05 +0530612 vsel = selector + 3;
Axel Linfaa95fd2012-07-11 19:44:13 +0800613 tps65910_reg_write(pmic->mfd, TPS65911_VDDCTRL_OP, vsel);
Graeme Gregory518fb722011-05-02 16:20:08 -0500614 }
615
616 return 0;
617}
618
Axel Lin94732b92012-03-09 10:22:20 +0800619static int tps65910_set_voltage_sel(struct regulator_dev *dev,
620 unsigned selector)
Graeme Gregory518fb722011-05-02 16:20:08 -0500621{
622 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
623 int reg, id = rdev_get_id(dev);
624
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500625 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500626 if (reg < 0)
627 return reg;
628
629 switch (id) {
630 case TPS65910_REG_VIO:
631 case TPS65910_REG_VDIG1:
632 case TPS65910_REG_VDIG2:
633 case TPS65910_REG_VPLL:
634 case TPS65910_REG_VDAC:
635 case TPS65910_REG_VAUX1:
636 case TPS65910_REG_VAUX2:
637 case TPS65910_REG_VAUX33:
638 case TPS65910_REG_VMMC:
Axel Linfaa95fd2012-07-11 19:44:13 +0800639 return tps65910_reg_update_bits(pmic->mfd, reg, LDO_SEL_MASK,
640 selector << LDO_SEL_SHIFT);
Graeme Gregory518fb722011-05-02 16:20:08 -0500641 }
642
643 return -EINVAL;
644}
645
Axel Lin94732b92012-03-09 10:22:20 +0800646static int tps65911_set_voltage_sel(struct regulator_dev *dev,
647 unsigned selector)
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500648{
649 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
650 int reg, id = rdev_get_id(dev);
651
652 reg = pmic->get_ctrl_reg(id);
653 if (reg < 0)
654 return reg;
655
656 switch (id) {
657 case TPS65911_REG_LDO1:
658 case TPS65911_REG_LDO2:
659 case TPS65911_REG_LDO4:
Axel Linfaa95fd2012-07-11 19:44:13 +0800660 return tps65910_reg_update_bits(pmic->mfd, reg, LDO1_SEL_MASK,
661 selector << LDO_SEL_SHIFT);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500662 case TPS65911_REG_LDO3:
663 case TPS65911_REG_LDO5:
664 case TPS65911_REG_LDO6:
665 case TPS65911_REG_LDO7:
666 case TPS65911_REG_LDO8:
Axel Linfaa95fd2012-07-11 19:44:13 +0800667 return tps65910_reg_update_bits(pmic->mfd, reg, LDO3_SEL_MASK,
668 selector << LDO_SEL_SHIFT);
Laxman Dewangane882eae2012-02-17 18:56:11 +0530669 case TPS65910_REG_VIO:
Axel Linfaa95fd2012-07-11 19:44:13 +0800670 return tps65910_reg_update_bits(pmic->mfd, reg, LDO_SEL_MASK,
671 selector << LDO_SEL_SHIFT);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500672 }
673
674 return -EINVAL;
675}
676
677
Graeme Gregory518fb722011-05-02 16:20:08 -0500678static int tps65910_list_voltage_dcdc(struct regulator_dev *dev,
679 unsigned selector)
680{
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500681 int volt, mult = 1, id = rdev_get_id(dev);
Graeme Gregory518fb722011-05-02 16:20:08 -0500682
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500683 switch (id) {
684 case TPS65910_REG_VDD1:
685 case TPS65910_REG_VDD2:
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530686 mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500687 volt = VDD1_2_MIN_VOLT +
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530688 (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET;
Axel Lind04156b2011-07-10 21:44:09 +0800689 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500690 case TPS65911_REG_VDDCTRL:
691 volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET);
Axel Lind04156b2011-07-10 21:44:09 +0800692 break;
693 default:
694 BUG();
695 return -EINVAL;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500696 }
Graeme Gregory518fb722011-05-02 16:20:08 -0500697
698 return volt * 100 * mult;
699}
700
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500701static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector)
702{
703 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
704 int step_mv = 0, id = rdev_get_id(dev);
705
706 switch(id) {
707 case TPS65911_REG_LDO1:
708 case TPS65911_REG_LDO2:
709 case TPS65911_REG_LDO4:
710 /* The first 5 values of the selector correspond to 1V */
711 if (selector < 5)
712 selector = 0;
713 else
714 selector -= 4;
715
716 step_mv = 50;
717 break;
718 case TPS65911_REG_LDO3:
719 case TPS65911_REG_LDO5:
720 case TPS65911_REG_LDO6:
721 case TPS65911_REG_LDO7:
722 case TPS65911_REG_LDO8:
723 /* The first 3 values of the selector correspond to 1V */
724 if (selector < 3)
725 selector = 0;
726 else
727 selector -= 2;
728
729 step_mv = 100;
730 break;
731 case TPS65910_REG_VIO:
Axel Lind9fe28f2012-06-21 18:48:00 +0800732 return pmic->info[id]->voltage_table[selector];
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500733 default:
734 return -EINVAL;
735 }
736
737 return (LDO_MIN_VOLT + selector * step_mv) * 1000;
738}
739
Graeme Gregory518fb722011-05-02 16:20:08 -0500740/* Regulator ops (except VRTC) */
741static struct regulator_ops tps65910_ops_dcdc = {
Axel Lina40a9c42012-04-17 14:34:46 +0800742 .is_enabled = regulator_is_enabled_regmap,
743 .enable = regulator_enable_regmap,
744 .disable = regulator_disable_regmap,
Graeme Gregory518fb722011-05-02 16:20:08 -0500745 .set_mode = tps65910_set_mode,
746 .get_mode = tps65910_get_mode,
Laxman Dewangan18039e02012-03-14 13:00:58 +0530747 .get_voltage_sel = tps65910_get_voltage_dcdc_sel,
Axel Lin94732b92012-03-09 10:22:20 +0800748 .set_voltage_sel = tps65910_set_voltage_dcdc_sel,
Axel Lin01bc3a12012-06-20 22:40:10 +0800749 .set_voltage_time_sel = regulator_set_voltage_time_sel,
Graeme Gregory518fb722011-05-02 16:20:08 -0500750 .list_voltage = tps65910_list_voltage_dcdc,
751};
752
753static struct regulator_ops tps65910_ops_vdd3 = {
Axel Lina40a9c42012-04-17 14:34:46 +0800754 .is_enabled = regulator_is_enabled_regmap,
755 .enable = regulator_enable_regmap,
756 .disable = regulator_disable_regmap,
Graeme Gregory518fb722011-05-02 16:20:08 -0500757 .set_mode = tps65910_set_mode,
758 .get_mode = tps65910_get_mode,
759 .get_voltage = tps65910_get_voltage_vdd3,
Axel Lind9fe28f2012-06-21 18:48:00 +0800760 .list_voltage = regulator_list_voltage_table,
Graeme Gregory518fb722011-05-02 16:20:08 -0500761};
762
763static struct regulator_ops tps65910_ops = {
Axel Lina40a9c42012-04-17 14:34:46 +0800764 .is_enabled = regulator_is_enabled_regmap,
765 .enable = regulator_enable_regmap,
766 .disable = regulator_disable_regmap,
Graeme Gregory518fb722011-05-02 16:20:08 -0500767 .set_mode = tps65910_set_mode,
768 .get_mode = tps65910_get_mode,
Axel Lin1f904fd2012-05-09 09:22:47 +0800769 .get_voltage_sel = tps65910_get_voltage_sel,
Axel Lin94732b92012-03-09 10:22:20 +0800770 .set_voltage_sel = tps65910_set_voltage_sel,
Axel Lind9fe28f2012-06-21 18:48:00 +0800771 .list_voltage = regulator_list_voltage_table,
Graeme Gregory518fb722011-05-02 16:20:08 -0500772};
773
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500774static struct regulator_ops tps65911_ops = {
Axel Lina40a9c42012-04-17 14:34:46 +0800775 .is_enabled = regulator_is_enabled_regmap,
776 .enable = regulator_enable_regmap,
777 .disable = regulator_disable_regmap,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500778 .set_mode = tps65910_set_mode,
779 .get_mode = tps65910_get_mode,
Axel Lin1f904fd2012-05-09 09:22:47 +0800780 .get_voltage_sel = tps65911_get_voltage_sel,
Axel Lin94732b92012-03-09 10:22:20 +0800781 .set_voltage_sel = tps65911_set_voltage_sel,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500782 .list_voltage = tps65911_list_voltage,
783};
784
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530785static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic,
786 int id, int ext_sleep_config)
787{
788 struct tps65910 *mfd = pmic->mfd;
789 u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF;
790 u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF);
791 int ret;
792
793 /*
794 * Regulator can not be control from multiple external input EN1, EN2
795 * and EN3 together.
796 */
797 if (ext_sleep_config & EXT_SLEEP_CONTROL) {
798 int en_count;
799 en_count = ((ext_sleep_config &
800 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0);
801 en_count += ((ext_sleep_config &
802 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0);
803 en_count += ((ext_sleep_config &
804 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0);
Laxman Dewanganf30b0712012-03-07 18:21:49 +0530805 en_count += ((ext_sleep_config &
806 TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530807 if (en_count > 1) {
808 dev_err(mfd->dev,
809 "External sleep control flag is not proper\n");
810 return -EINVAL;
811 }
812 }
813
814 pmic->board_ext_control[id] = ext_sleep_config;
815
816 /* External EN1 control */
817 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1)
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700818 ret = tps65910_reg_set_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530819 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
820 else
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700821 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530822 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
823 if (ret < 0) {
824 dev_err(mfd->dev,
825 "Error in configuring external control EN1\n");
826 return ret;
827 }
828
829 /* External EN2 control */
830 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2)
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700831 ret = tps65910_reg_set_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530832 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
833 else
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700834 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530835 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
836 if (ret < 0) {
837 dev_err(mfd->dev,
838 "Error in configuring external control EN2\n");
839 return ret;
840 }
841
842 /* External EN3 control for TPS65910 LDO only */
843 if ((tps65910_chip_id(mfd) == TPS65910) &&
844 (id >= TPS65910_REG_VDIG1)) {
845 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3)
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700846 ret = tps65910_reg_set_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530847 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
848 else
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700849 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530850 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
851 if (ret < 0) {
852 dev_err(mfd->dev,
853 "Error in configuring external control EN3\n");
854 return ret;
855 }
856 }
857
858 /* Return if no external control is selected */
859 if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) {
860 /* Clear all sleep controls */
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700861 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530862 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
863 if (!ret)
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700864 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530865 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
866 if (ret < 0)
867 dev_err(mfd->dev,
868 "Error in configuring SLEEP register\n");
869 return ret;
870 }
871
872 /*
873 * For regulator that has separate operational and sleep register make
874 * sure that operational is used and clear sleep register to turn
875 * regulator off when external control is inactive
876 */
877 if ((id == TPS65910_REG_VDD1) ||
878 (id == TPS65910_REG_VDD2) ||
879 ((id == TPS65911_REG_VDDCTRL) &&
880 (tps65910_chip_id(mfd) == TPS65911))) {
881 int op_reg_add = pmic->get_ctrl_reg(id) + 1;
882 int sr_reg_add = pmic->get_ctrl_reg(id) + 2;
Axel Linfaa95fd2012-07-11 19:44:13 +0800883 int opvsel, srvsel;
884
885 ret = tps65910_reg_read(pmic->mfd, op_reg_add, &opvsel);
886 if (ret < 0)
887 return ret;
888 ret = tps65910_reg_read(pmic->mfd, sr_reg_add, &srvsel);
889 if (ret < 0)
890 return ret;
891
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530892 if (opvsel & VDD1_OP_CMD_MASK) {
893 u8 reg_val = srvsel & VDD1_OP_SEL_MASK;
Axel Linfaa95fd2012-07-11 19:44:13 +0800894
895 ret = tps65910_reg_write(pmic->mfd, op_reg_add,
896 reg_val);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530897 if (ret < 0) {
898 dev_err(mfd->dev,
899 "Error in configuring op register\n");
900 return ret;
901 }
902 }
Axel Linfaa95fd2012-07-11 19:44:13 +0800903 ret = tps65910_reg_write(pmic->mfd, sr_reg_add, 0);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530904 if (ret < 0) {
905 dev_err(mfd->dev, "Error in settting sr register\n");
906 return ret;
907 }
908 }
909
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700910 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530911 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
Laxman Dewanganf30b0712012-03-07 18:21:49 +0530912 if (!ret) {
913 if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700914 ret = tps65910_reg_set_bits(mfd,
Laxman Dewanganf30b0712012-03-07 18:21:49 +0530915 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
916 else
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700917 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewanganf30b0712012-03-07 18:21:49 +0530918 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
919 }
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530920 if (ret < 0)
921 dev_err(mfd->dev,
922 "Error in configuring SLEEP register\n");
Laxman Dewanganf30b0712012-03-07 18:21:49 +0530923
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530924 return ret;
925}
926
Rhyland Klein67901782012-05-08 11:42:41 -0700927#ifdef CONFIG_OF
928
929static struct of_regulator_match tps65910_matches[] = {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530930 { .name = "vrtc", .driver_data = (void *) &tps65910_regs[0] },
931 { .name = "vio", .driver_data = (void *) &tps65910_regs[1] },
932 { .name = "vdd1", .driver_data = (void *) &tps65910_regs[2] },
933 { .name = "vdd2", .driver_data = (void *) &tps65910_regs[3] },
934 { .name = "vdd3", .driver_data = (void *) &tps65910_regs[4] },
935 { .name = "vdig1", .driver_data = (void *) &tps65910_regs[5] },
936 { .name = "vdig2", .driver_data = (void *) &tps65910_regs[6] },
937 { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] },
938 { .name = "vdac", .driver_data = (void *) &tps65910_regs[8] },
939 { .name = "vaux1", .driver_data = (void *) &tps65910_regs[9] },
940 { .name = "vaux2", .driver_data = (void *) &tps65910_regs[10] },
941 { .name = "vaux33", .driver_data = (void *) &tps65910_regs[11] },
942 { .name = "vmmc", .driver_data = (void *) &tps65910_regs[12] },
Rhyland Klein67901782012-05-08 11:42:41 -0700943};
944
945static struct of_regulator_match tps65911_matches[] = {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530946 { .name = "vrtc", .driver_data = (void *) &tps65911_regs[0] },
947 { .name = "vio", .driver_data = (void *) &tps65911_regs[1] },
948 { .name = "vdd1", .driver_data = (void *) &tps65911_regs[2] },
949 { .name = "vdd2", .driver_data = (void *) &tps65911_regs[3] },
950 { .name = "vddctrl", .driver_data = (void *) &tps65911_regs[4] },
951 { .name = "ldo1", .driver_data = (void *) &tps65911_regs[5] },
952 { .name = "ldo2", .driver_data = (void *) &tps65911_regs[6] },
953 { .name = "ldo3", .driver_data = (void *) &tps65911_regs[7] },
954 { .name = "ldo4", .driver_data = (void *) &tps65911_regs[8] },
955 { .name = "ldo5", .driver_data = (void *) &tps65911_regs[9] },
956 { .name = "ldo6", .driver_data = (void *) &tps65911_regs[10] },
957 { .name = "ldo7", .driver_data = (void *) &tps65911_regs[11] },
958 { .name = "ldo8", .driver_data = (void *) &tps65911_regs[12] },
Rhyland Klein67901782012-05-08 11:42:41 -0700959};
960
961static struct tps65910_board *tps65910_parse_dt_reg_data(
Laxman Dewangan84df8c12012-05-20 21:48:50 +0530962 struct platform_device *pdev,
963 struct of_regulator_match **tps65910_reg_matches)
Rhyland Klein67901782012-05-08 11:42:41 -0700964{
965 struct tps65910_board *pmic_plat_data;
966 struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
Axel Linc92f5dd2013-01-27 21:16:56 +0800967 struct device_node *np, *regulators;
Rhyland Klein67901782012-05-08 11:42:41 -0700968 struct of_regulator_match *matches;
969 unsigned int prop;
970 int idx = 0, ret, count;
971
972 pmic_plat_data = devm_kzalloc(&pdev->dev, sizeof(*pmic_plat_data),
973 GFP_KERNEL);
974
975 if (!pmic_plat_data) {
976 dev_err(&pdev->dev, "Failure to alloc pdata for regulators.\n");
977 return NULL;
978 }
979
Axel Linc92f5dd2013-01-27 21:16:56 +0800980 np = of_node_get(pdev->dev.parent->of_node);
Rhyland Klein67901782012-05-08 11:42:41 -0700981 regulators = of_find_node_by_name(np, "regulators");
Laxman Dewangan92ab9532012-05-20 21:48:49 +0530982 if (!regulators) {
983 dev_err(&pdev->dev, "regulator node not found\n");
984 return NULL;
985 }
Rhyland Klein67901782012-05-08 11:42:41 -0700986
987 switch (tps65910_chip_id(tps65910)) {
988 case TPS65910:
989 count = ARRAY_SIZE(tps65910_matches);
990 matches = tps65910_matches;
991 break;
992 case TPS65911:
993 count = ARRAY_SIZE(tps65911_matches);
994 matches = tps65911_matches;
995 break;
996 default:
Axel Linc92f5dd2013-01-27 21:16:56 +0800997 of_node_put(regulators);
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +0530998 dev_err(&pdev->dev, "Invalid tps chip version\n");
Rhyland Klein67901782012-05-08 11:42:41 -0700999 return NULL;
1000 }
1001
Axel Lin08337fd2013-01-24 10:31:45 +08001002 ret = of_regulator_match(&pdev->dev, regulators, matches, count);
Axel Linc92f5dd2013-01-27 21:16:56 +08001003 of_node_put(regulators);
Rhyland Klein67901782012-05-08 11:42:41 -07001004 if (ret < 0) {
1005 dev_err(&pdev->dev, "Error parsing regulator init data: %d\n",
1006 ret);
1007 return NULL;
1008 }
1009
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301010 *tps65910_reg_matches = matches;
1011
Rhyland Klein67901782012-05-08 11:42:41 -07001012 for (idx = 0; idx < count; idx++) {
1013 if (!matches[idx].init_data || !matches[idx].of_node)
1014 continue;
1015
1016 pmic_plat_data->tps65910_pmic_init_data[idx] =
1017 matches[idx].init_data;
1018
1019 ret = of_property_read_u32(matches[idx].of_node,
1020 "ti,regulator-ext-sleep-control", &prop);
1021 if (!ret)
1022 pmic_plat_data->regulator_ext_sleep_control[idx] = prop;
Laxman Dewangan19228a62012-07-06 14:13:12 +05301023
Rhyland Klein67901782012-05-08 11:42:41 -07001024 }
1025
1026 return pmic_plat_data;
1027}
1028#else
1029static inline struct tps65910_board *tps65910_parse_dt_reg_data(
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301030 struct platform_device *pdev,
1031 struct of_regulator_match **tps65910_reg_matches)
Rhyland Klein67901782012-05-08 11:42:41 -07001032{
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301033 *tps65910_reg_matches = NULL;
Mark Brown74ea0e52012-06-15 19:04:33 +01001034 return NULL;
Rhyland Klein67901782012-05-08 11:42:41 -07001035}
1036#endif
1037
Bill Pembertona5023572012-11-19 13:22:22 -05001038static int tps65910_probe(struct platform_device *pdev)
Graeme Gregory518fb722011-05-02 16:20:08 -05001039{
1040 struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
Mark Brownc1727082012-04-04 00:50:22 +01001041 struct regulator_config config = { };
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001042 struct tps_info *info;
Graeme Gregory518fb722011-05-02 16:20:08 -05001043 struct regulator_init_data *reg_data;
1044 struct regulator_dev *rdev;
1045 struct tps65910_reg *pmic;
1046 struct tps65910_board *pmic_plat_data;
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301047 struct of_regulator_match *tps65910_reg_matches = NULL;
Graeme Gregory518fb722011-05-02 16:20:08 -05001048 int i, err;
1049
1050 pmic_plat_data = dev_get_platdata(tps65910->dev);
Rhyland Klein67901782012-05-08 11:42:41 -07001051 if (!pmic_plat_data && tps65910->dev->of_node)
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301052 pmic_plat_data = tps65910_parse_dt_reg_data(pdev,
1053 &tps65910_reg_matches);
Rhyland Klein67901782012-05-08 11:42:41 -07001054
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301055 if (!pmic_plat_data) {
1056 dev_err(&pdev->dev, "Platform data not found\n");
Graeme Gregory518fb722011-05-02 16:20:08 -05001057 return -EINVAL;
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301058 }
Graeme Gregory518fb722011-05-02 16:20:08 -05001059
Axel Lin9eb0c422012-04-11 14:40:18 +08001060 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301061 if (!pmic) {
1062 dev_err(&pdev->dev, "Memory allocation failed for pmic\n");
Graeme Gregory518fb722011-05-02 16:20:08 -05001063 return -ENOMEM;
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301064 }
Graeme Gregory518fb722011-05-02 16:20:08 -05001065
Graeme Gregory518fb722011-05-02 16:20:08 -05001066 pmic->mfd = tps65910;
1067 platform_set_drvdata(pdev, pmic);
1068
1069 /* Give control of all register to control port */
Rhyland Klein3f7e8272012-05-08 11:42:38 -07001070 tps65910_reg_set_bits(pmic->mfd, TPS65910_DEVCTRL,
Graeme Gregory518fb722011-05-02 16:20:08 -05001071 DEVCTRL_SR_CTL_I2C_SEL_MASK);
1072
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001073 switch(tps65910_chip_id(tps65910)) {
1074 case TPS65910:
1075 pmic->get_ctrl_reg = &tps65910_get_ctrl_register;
Axel Lin39aa9b62011-07-11 09:57:43 +08001076 pmic->num_regulators = ARRAY_SIZE(tps65910_regs);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301077 pmic->ext_sleep_control = tps65910_ext_sleep_control;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001078 info = tps65910_regs;
Axel Lind04156b2011-07-10 21:44:09 +08001079 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001080 case TPS65911:
1081 pmic->get_ctrl_reg = &tps65911_get_ctrl_register;
Axel Lin39aa9b62011-07-11 09:57:43 +08001082 pmic->num_regulators = ARRAY_SIZE(tps65911_regs);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301083 pmic->ext_sleep_control = tps65911_ext_sleep_control;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001084 info = tps65911_regs;
Axel Lind04156b2011-07-10 21:44:09 +08001085 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001086 default:
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301087 dev_err(&pdev->dev, "Invalid tps chip version\n");
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001088 return -ENODEV;
1089 }
1090
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301091 pmic->desc = devm_kzalloc(&pdev->dev, pmic->num_regulators *
Axel Lin39aa9b62011-07-11 09:57:43 +08001092 sizeof(struct regulator_desc), GFP_KERNEL);
1093 if (!pmic->desc) {
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301094 dev_err(&pdev->dev, "Memory alloc fails for desc\n");
1095 return -ENOMEM;
Axel Lin39aa9b62011-07-11 09:57:43 +08001096 }
1097
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301098 pmic->info = devm_kzalloc(&pdev->dev, pmic->num_regulators *
Axel Lin39aa9b62011-07-11 09:57:43 +08001099 sizeof(struct tps_info *), GFP_KERNEL);
1100 if (!pmic->info) {
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301101 dev_err(&pdev->dev, "Memory alloc fails for info\n");
1102 return -ENOMEM;
Axel Lin39aa9b62011-07-11 09:57:43 +08001103 }
1104
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301105 pmic->rdev = devm_kzalloc(&pdev->dev, pmic->num_regulators *
Axel Lin39aa9b62011-07-11 09:57:43 +08001106 sizeof(struct regulator_dev *), GFP_KERNEL);
1107 if (!pmic->rdev) {
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301108 dev_err(&pdev->dev, "Memory alloc fails for rdev\n");
1109 return -ENOMEM;
Axel Lin39aa9b62011-07-11 09:57:43 +08001110 }
1111
Kyle Mannac1fc1482011-11-03 12:08:06 -05001112 for (i = 0; i < pmic->num_regulators && i < TPS65910_NUM_REGS;
1113 i++, info++) {
1114
1115 reg_data = pmic_plat_data->tps65910_pmic_init_data[i];
1116
1117 /* Regulator API handles empty constraints but not NULL
1118 * constraints */
1119 if (!reg_data)
1120 continue;
1121
Graeme Gregory518fb722011-05-02 16:20:08 -05001122 /* Register the regulators */
1123 pmic->info[i] = info;
1124
1125 pmic->desc[i].name = info->name;
Laxman Dewangand2cfdb02012-07-17 11:34:06 +05301126 pmic->desc[i].supply_name = info->vin_name;
Axel Lin77fa44d2011-05-12 13:47:50 +08001127 pmic->desc[i].id = i;
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +05301128 pmic->desc[i].n_voltages = info->n_voltages;
Axel Lin94f48ab2012-07-04 09:59:17 +08001129 pmic->desc[i].enable_time = info->enable_time_us;
Graeme Gregory518fb722011-05-02 16:20:08 -05001130
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001131 if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) {
Graeme Gregory518fb722011-05-02 16:20:08 -05001132 pmic->desc[i].ops = &tps65910_ops_dcdc;
Afzal Mohammed780dc9b2011-11-08 18:54:10 +05301133 pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE *
1134 VDD1_2_NUM_VOLT_COARSE;
Axel Lin01bc3a12012-06-20 22:40:10 +08001135 pmic->desc[i].ramp_delay = 12500;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001136 } else if (i == TPS65910_REG_VDD3) {
Axel Lin01bc3a12012-06-20 22:40:10 +08001137 if (tps65910_chip_id(tps65910) == TPS65910) {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001138 pmic->desc[i].ops = &tps65910_ops_vdd3;
Axel Lind9fe28f2012-06-21 18:48:00 +08001139 pmic->desc[i].volt_table = info->voltage_table;
Axel Lin01bc3a12012-06-20 22:40:10 +08001140 } else {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001141 pmic->desc[i].ops = &tps65910_ops_dcdc;
Axel Lin01bc3a12012-06-20 22:40:10 +08001142 pmic->desc[i].ramp_delay = 5000;
1143 }
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001144 } else {
Axel Lind9fe28f2012-06-21 18:48:00 +08001145 if (tps65910_chip_id(tps65910) == TPS65910) {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001146 pmic->desc[i].ops = &tps65910_ops;
Axel Lind9fe28f2012-06-21 18:48:00 +08001147 pmic->desc[i].volt_table = info->voltage_table;
1148 } else {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001149 pmic->desc[i].ops = &tps65911_ops;
Axel Lind9fe28f2012-06-21 18:48:00 +08001150 }
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001151 }
Graeme Gregory518fb722011-05-02 16:20:08 -05001152
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301153 err = tps65910_set_ext_sleep_config(pmic, i,
1154 pmic_plat_data->regulator_ext_sleep_control[i]);
1155 /*
1156 * Failing on regulator for configuring externally control
1157 * is not a serious issue, just throw warning.
1158 */
1159 if (err < 0)
1160 dev_warn(tps65910->dev,
1161 "Failed to initialise ext control config\n");
1162
Graeme Gregory518fb722011-05-02 16:20:08 -05001163 pmic->desc[i].type = REGULATOR_VOLTAGE;
1164 pmic->desc[i].owner = THIS_MODULE;
Axel Lina40a9c42012-04-17 14:34:46 +08001165 pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i);
1166 pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED;
Graeme Gregory518fb722011-05-02 16:20:08 -05001167
Mark Brownc1727082012-04-04 00:50:22 +01001168 config.dev = tps65910->dev;
1169 config.init_data = reg_data;
1170 config.driver_data = pmic;
Axel Lina40a9c42012-04-17 14:34:46 +08001171 config.regmap = tps65910->regmap;
Mark Brownc1727082012-04-04 00:50:22 +01001172
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301173 if (tps65910_reg_matches)
1174 config.of_node = tps65910_reg_matches[i].of_node;
Rhyland Klein67901782012-05-08 11:42:41 -07001175
Mark Brownc1727082012-04-04 00:50:22 +01001176 rdev = regulator_register(&pmic->desc[i], &config);
Graeme Gregory518fb722011-05-02 16:20:08 -05001177 if (IS_ERR(rdev)) {
1178 dev_err(tps65910->dev,
1179 "failed to register %s regulator\n",
1180 pdev->name);
1181 err = PTR_ERR(rdev);
Axel Lin39aa9b62011-07-11 09:57:43 +08001182 goto err_unregister_regulator;
Graeme Gregory518fb722011-05-02 16:20:08 -05001183 }
1184
1185 /* Save regulator for cleanup */
1186 pmic->rdev[i] = rdev;
1187 }
1188 return 0;
1189
Axel Lin39aa9b62011-07-11 09:57:43 +08001190err_unregister_regulator:
Graeme Gregory518fb722011-05-02 16:20:08 -05001191 while (--i >= 0)
1192 regulator_unregister(pmic->rdev[i]);
Graeme Gregory518fb722011-05-02 16:20:08 -05001193 return err;
1194}
1195
Bill Pemberton8dc995f2012-11-19 13:26:10 -05001196static int tps65910_remove(struct platform_device *pdev)
Graeme Gregory518fb722011-05-02 16:20:08 -05001197{
Axel Lin39aa9b62011-07-11 09:57:43 +08001198 struct tps65910_reg *pmic = platform_get_drvdata(pdev);
Graeme Gregory518fb722011-05-02 16:20:08 -05001199 int i;
1200
Axel Lin39aa9b62011-07-11 09:57:43 +08001201 for (i = 0; i < pmic->num_regulators; i++)
1202 regulator_unregister(pmic->rdev[i]);
Graeme Gregory518fb722011-05-02 16:20:08 -05001203
Graeme Gregory518fb722011-05-02 16:20:08 -05001204 return 0;
1205}
1206
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301207static void tps65910_shutdown(struct platform_device *pdev)
1208{
1209 struct tps65910_reg *pmic = platform_get_drvdata(pdev);
1210 int i;
1211
1212 /*
1213 * Before bootloader jumps to kernel, it makes sure that required
1214 * external control signals are in desired state so that given rails
1215 * can be configure accordingly.
1216 * If rails are configured to be controlled from external control
1217 * then before shutting down/rebooting the system, the external
1218 * control configuration need to be remove from the rails so that
1219 * its output will be available as per register programming even
1220 * if external controls are removed. This is require when the POR
1221 * value of the control signals are not in active state and before
1222 * bootloader initializes it, the system requires the rail output
1223 * to be active for booting.
1224 */
1225 for (i = 0; i < pmic->num_regulators; i++) {
1226 int err;
1227 if (!pmic->rdev[i])
1228 continue;
1229
1230 err = tps65910_set_ext_sleep_config(pmic, i, 0);
1231 if (err < 0)
1232 dev_err(&pdev->dev,
1233 "Error in clearing external control\n");
1234 }
1235}
1236
Graeme Gregory518fb722011-05-02 16:20:08 -05001237static struct platform_driver tps65910_driver = {
1238 .driver = {
1239 .name = "tps65910-pmic",
1240 .owner = THIS_MODULE,
1241 },
1242 .probe = tps65910_probe,
Bill Pemberton5eb9f2b2012-11-19 13:20:42 -05001243 .remove = tps65910_remove,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301244 .shutdown = tps65910_shutdown,
Graeme Gregory518fb722011-05-02 16:20:08 -05001245};
1246
1247static int __init tps65910_init(void)
1248{
1249 return platform_driver_register(&tps65910_driver);
1250}
1251subsys_initcall(tps65910_init);
1252
1253static void __exit tps65910_cleanup(void)
1254{
1255 platform_driver_unregister(&tps65910_driver);
1256}
1257module_exit(tps65910_cleanup);
1258
1259MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
Axel Linae0e6542012-02-21 10:14:55 +08001260MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver");
Graeme Gregory518fb722011-05-02 16:20:08 -05001261MODULE_LICENSE("GPL v2");
1262MODULE_ALIAS("platform:tps65910-pmic");