Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / c9cbbd4fc066d654392eeefcfdce5b567ae8a420 / . / arch / arm / boot / dts / tegra30-cardhu.dtsi
blob: 1e156d9d0506085c4ea615ac8c7e06193573edcb [file] [log] [blame]
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]1#include "tegra30.dtsi"
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]2
Laxman Dewangan640a7af2012-08-09 16:30:38 +0530[diff] [blame]3/**
4 * This file contains common DT entry for all fab version of Cardhu.
5 * There is multiple fab version of Cardhu starting from A01 to A07.
6 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
7 * A02 will have different sets of GPIOs for fixed regulator compare to
8 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
9 * compatible with fab version A04. Based on Cardhu fab version, the
10 * related dts file need to be chosen like for Cardhu fab version A02,
11 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
12 * tegra30-cardhu-a04.dts.
13 * The identification of board is done in two ways, by looking the sticker
14 * on PCB and by reading board id eeprom.
15 * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
16 * number is the fab version like here it is 002 and hence fab version A02.
17 * The (downstream internal) U-Boot of Cardhu display the board-id as
18 * follows:
19 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
20 * In this Fab version is 02 i.e. A02.
21 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
22 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
23 * wide.
24 */
25
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]26/ {
27 model = "NVIDIA Tegra30 Cardhu evaluation board";
28 compatible = "nvidia,cardhu", "nvidia,tegra30";
29
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]30 aliases {
Stephen Warren763fbff2014-02-13 17:18:26 -0700[diff] [blame]31 rtc0 = "/i2c@7000d000/tps65911@2d";
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]32 rtc1 = "/rtc@7000e000";
33 };
34
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]35 memory {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]36 reg = <0x80000000 0x40000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]37 };
38
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]39 pcie-controller@00003000 {
Jay Agarwal89e7ada2013-08-09 16:49:27 +0200[diff] [blame]40 status = "okay";
41 pex-clk-supply = <&pex_hvdd_3v3_reg>;
42 vdd-supply = <&ldo1_reg>;
43 avdd-supply = <&ldo2_reg>;
44
45 pci@1,0 {
46 nvidia,num-lanes = <4>;
47 };
48
49 pci@2,0 {
50 nvidia,num-lanes = <1>;
51 };
52
53 pci@3,0 {
54 status = "okay";
55 nvidia,num-lanes = <1>;
56 };
57 };
58
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]59 host1x@50000000 {
60 dc@54200000 {
61 rgb {
62 status = "okay";
63
64 nvidia,panel = <&panel>;
65 };
66 };
67 };
68
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]69 pinmux@70000868 {
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]70 pinctrl-names = "default";
71 pinctrl-0 = <&state_default>;
72
73 state_default: pinmux {
74 sdmmc1_clk_pz0 {
75 nvidia,pins = "sdmmc1_clk_pz0";
76 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]77 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]79 };
80 sdmmc1_cmd_pz1 {
81 nvidia,pins = "sdmmc1_cmd_pz1",
82 "sdmmc1_dat0_py7",
83 "sdmmc1_dat1_py6",
84 "sdmmc1_dat2_py5",
85 "sdmmc1_dat3_py4";
86 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]87 nvidia,pull = <TEGRA_PIN_PULL_UP>;
88 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]89 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]90 sdmmc3_clk_pa6 {
91 nvidia,pins = "sdmmc3_clk_pa6";
92 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]93 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
94 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]95 };
96 sdmmc3_cmd_pa7 {
97 nvidia,pins = "sdmmc3_cmd_pa7",
98 "sdmmc3_dat0_pb7",
99 "sdmmc3_dat1_pb6",
100 "sdmmc3_dat2_pb5",
101 "sdmmc3_dat3_pb4";
102 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]103 nvidia,pull = <TEGRA_PIN_PULL_UP>;
104 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]105 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]106 sdmmc4_clk_pcc4 {
107 nvidia,pins = "sdmmc4_clk_pcc4",
108 "sdmmc4_rst_n_pcc3";
109 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]110 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
111 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]112 };
113 sdmmc4_dat0_paa0 {
114 nvidia,pins = "sdmmc4_dat0_paa0",
115 "sdmmc4_dat1_paa1",
116 "sdmmc4_dat2_paa2",
117 "sdmmc4_dat3_paa3",
118 "sdmmc4_dat4_paa4",
119 "sdmmc4_dat5_paa5",
120 "sdmmc4_dat6_paa6",
121 "sdmmc4_dat7_paa7";
122 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]123 nvidia,pull = <TEGRA_PIN_PULL_UP>;
124 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]125 };
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]126 dap2_fs_pa2 {
127 nvidia,pins = "dap2_fs_pa2",
128 "dap2_sclk_pa3",
129 "dap2_din_pa4",
130 "dap2_dout_pa5";
131 nvidia,function = "i2s1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]132 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
133 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]134 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]135 sdio3 {
136 nvidia,pins = "drive_sdio3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]137 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
138 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]139 nvidia,pull-down-strength = <46>;
140 nvidia,pull-up-strength = <42>;
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]141 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
142 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]143 };
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]144 uart3_txd_pw6 {
145 nvidia,pins = "uart3_txd_pw6",
146 "uart3_cts_n_pa1",
147 "uart3_rts_n_pc0",
148 "uart3_rxd_pw7";
149 nvidia,function = "uartc";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]150 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
151 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]152 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]153 };
154 };
155
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]156 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]157 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]158 };
159
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]160 serial@70006200 {
161 compatible = "nvidia,tegra30-hsuart";
162 status = "okay";
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]163 };
164
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]165 pwm@7000a000 {
166 status = "okay";
167 };
168
169 panelddc: i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]170 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]171 clock-frequency = <100000>;
172 };
173
174 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]175 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]176 clock-frequency = <100000>;
177 };
178
179 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]180 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]181 clock-frequency = <100000>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]182
183 /* ALS and Proximity sensor */
184 isl29028@44 {
185 compatible = "isil,isl29028";
186 reg = <0x44>;
187 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]188 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]189 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]190 };
191
192 i2c@7000c700 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]193 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]194 clock-frequency = <100000>;
195 };
196
197 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]198 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]199 clock-frequency = <100000>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]200
201 wm8903: wm8903@1a {
202 compatible = "wlf,wm8903";
203 reg = <0x1a>;
204 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]205 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]206
207 gpio-controller;
208 #gpio-cells = <2>;
209
210 micdet-cfg = <0>;
211 micdet-delay = <100>;
212 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
213 };
Laxman Dewangan331da582012-05-10 20:38:45 +0000[diff] [blame]214
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]215 pmic: tps65911@2d {
216 compatible = "ti,tps65911";
217 reg = <0x2d>;
218
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]219 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]220 #interrupt-cells = <2>;
221 interrupt-controller;
222
Stephen Warren44b12ef2012-09-11 11:42:26 -0600[diff] [blame]223 ti,system-power-controller;
224
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]225 #gpio-cells = <2>;
226 gpio-controller;
227
228 vcc1-supply = <&vdd_ac_bat_reg>;
229 vcc2-supply = <&vdd_ac_bat_reg>;
230 vcc3-supply = <&vio_reg>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]231 vcc4-supply = <&vdd_5v0_reg>;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]232 vcc5-supply = <&vdd_ac_bat_reg>;
233 vcc6-supply = <&vdd2_reg>;
234 vcc7-supply = <&vdd_ac_bat_reg>;
235 vccio-supply = <&vdd_ac_bat_reg>;
236
237 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]238 vdd1_reg: vdd1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]239 regulator-name = "vddio_ddr_1v2";
240 regulator-min-microvolt = <1200000>;
241 regulator-max-microvolt = <1200000>;
242 regulator-always-on;
243 };
244
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]245 vdd2_reg: vdd2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]246 regulator-name = "vdd_1v5_gen";
247 regulator-min-microvolt = <1500000>;
248 regulator-max-microvolt = <1500000>;
249 regulator-always-on;
250 };
251
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]252 vddctrl_reg: vddctrl {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]253 regulator-name = "vdd_cpu,vdd_sys";
254 regulator-min-microvolt = <1000000>;
255 regulator-max-microvolt = <1000000>;
256 regulator-always-on;
257 };
258
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]259 vio_reg: vio {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]260 regulator-name = "vdd_1v8_gen";
261 regulator-min-microvolt = <1800000>;
262 regulator-max-microvolt = <1800000>;
263 regulator-always-on;
264 };
265
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]266 ldo1_reg: ldo1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]267 regulator-name = "vdd_pexa,vdd_pexb";
268 regulator-min-microvolt = <1050000>;
269 regulator-max-microvolt = <1050000>;
270 };
271
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]272 ldo2_reg: ldo2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]273 regulator-name = "vdd_sata,avdd_plle";
274 regulator-min-microvolt = <1050000>;
275 regulator-max-microvolt = <1050000>;
276 };
277
278 /* LDO3 is not connected to anything */
279
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]280 ldo4_reg: ldo4 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]281 regulator-name = "vdd_rtc";
282 regulator-min-microvolt = <1200000>;
283 regulator-max-microvolt = <1200000>;
284 regulator-always-on;
285 };
286
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]287 ldo5_reg: ldo5 {
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]288 regulator-name = "vddio_sdmmc,avdd_vdac";
289 regulator-min-microvolt = <3300000>;
290 regulator-max-microvolt = <3300000>;
291 regulator-always-on;
292 };
293
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]294 ldo6_reg: ldo6 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]295 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
296 regulator-min-microvolt = <1200000>;
297 regulator-max-microvolt = <1200000>;
298 };
299
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]300 ldo7_reg: ldo7 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]301 regulator-name = "vdd_pllm,x,u,a_p_c_s";
302 regulator-min-microvolt = <1200000>;
303 regulator-max-microvolt = <1200000>;
304 regulator-always-on;
305 };
306
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]307 ldo8_reg: ldo8 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]308 regulator-name = "vdd_ddr_hs";
309 regulator-min-microvolt = <1000000>;
310 regulator-max-microvolt = <1000000>;
311 regulator-always-on;
312 };
313 };
314 };
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]315
Wei Ni7c7de6b2013-10-07 17:28:29 +0800[diff] [blame]316 temperature-sensor@4c {
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]317 compatible = "onnn,nct1008";
318 reg = <0x4c>;
Wei Ni7c7de6b2013-10-07 17:28:29 +0800[diff] [blame]319 vcc-supply = <&sys_3v3_reg>;
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]320 interrupt-parent = <&gpio>;
321 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
322 };
Stephen Warren2b8584d2013-07-15 10:33:53 -0600[diff] [blame]323
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]324 tps62361@60 {
Stephen Warren2b8584d2013-07-15 10:33:53 -0600[diff] [blame]325 compatible = "ti,tps62361";
326 reg = <0x60>;
327
328 regulator-name = "tps62361-vout";
329 regulator-min-microvolt = <500000>;
330 regulator-max-microvolt = <1500000>;
331 regulator-boot-on;
332 regulator-always-on;
333 ti,vsel0-state-high;
334 ti,vsel1-state-high;
335 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]336 };
Stephen Warren850c4c82012-02-01 16:29:57 -0700[diff] [blame]337
Laxman Dewanganc42cb1c2012-10-31 14:32:54 +0530[diff] [blame]338 spi@7000da00 {
339 status = "okay";
340 spi-max-frequency = <25000000>;
341 spi-flash@1 {
342 compatible = "winbond,w25q32";
343 reg = <1>;
344 spi-max-frequency = <20000000>;
345 };
346 };
347
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]348 pmc@7000e400 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]349 status = "okay";
350 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800[diff] [blame]351 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800[diff] [blame]352 nvidia,cpu-pwr-good-time = <2000>;
353 nvidia,cpu-pwr-off-time = <200>;
354 nvidia,core-pwr-good-time = <3845 3845>;
355 nvidia,core-pwr-off-time = <0>;
356 nvidia,core-power-req-active-high;
357 nvidia,sys-clock-req-active-high;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]358 };
359
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]360 ahub@70080000 {
361 i2s@70080400 {
362 status = "okay";
363 };
364 };
365
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]366 sdhci@78000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]367 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]368 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
369 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
370 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]371 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]372 };
373
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]374 sdhci@78000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]375 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]376 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600[diff] [blame]377 non-removable;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]378 };
379
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300[diff] [blame]380 usb@7d008000 {
381 status = "okay";
382 };
383
384 usb-phy@7d008000 {
385 vbus-supply = <&usb3_vbus_reg>;
386 status = "okay";
387 };
388
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]389 backlight: backlight {
390 compatible = "pwm-backlight";
391
392 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
393 power-supply = <&vdd_bl_reg>;
394 pwms = <&pwm 0 5000000>;
395
396 brightness-levels = <0 4 8 16 32 64 128 255>;
397 default-brightness-level = <6>;
398 };
399
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]400 clocks {
401 compatible = "simple-bus";
402 #address-cells = <1>;
403 #size-cells = <0>;
404
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]405 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]406 compatible = "fixed-clock";
407 reg=<0>;
408 #clock-cells = <0>;
409 clock-frequency = <32768>;
410 };
411 };
412
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]413 panel: panel {
414 compatible = "chunghwa,claa101wb01", "simple-panel";
415 ddc-i2c-bus = <&panelddc>;
416
417 power-supply = <&vdd_pnl1_reg>;
418 enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
419
420 backlight = <&backlight>;
421 };
422
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]423 regulators {
424 compatible = "simple-bus";
425 #address-cells = <1>;
426 #size-cells = <0>;
427
428 vdd_ac_bat_reg: regulator@0 {
429 compatible = "regulator-fixed";
430 reg = <0>;
431 regulator-name = "vdd_ac_bat";
432 regulator-min-microvolt = <5000000>;
433 regulator-max-microvolt = <5000000>;
434 regulator-always-on;
435 };
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]436
437 cam_1v8_reg: regulator@1 {
438 compatible = "regulator-fixed";
439 reg = <1>;
440 regulator-name = "cam_1v8";
441 regulator-min-microvolt = <1800000>;
442 regulator-max-microvolt = <1800000>;
443 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]444 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]445 vin-supply = <&vio_reg>;
446 };
447
448 cp_5v_reg: regulator@2 {
449 compatible = "regulator-fixed";
450 reg = <2>;
451 regulator-name = "cp_5v";
452 regulator-min-microvolt = <5000000>;
453 regulator-max-microvolt = <5000000>;
454 regulator-boot-on;
455 regulator-always-on;
456 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]457 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]458 };
459
460 emmc_3v3_reg: regulator@3 {
461 compatible = "regulator-fixed";
462 reg = <3>;
463 regulator-name = "emmc_3v3";
464 regulator-min-microvolt = <3300000>;
465 regulator-max-microvolt = <3300000>;
466 regulator-always-on;
467 regulator-boot-on;
468 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]469 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]470 vin-supply = <&sys_3v3_reg>;
471 };
472
473 modem_3v3_reg: regulator@4 {
474 compatible = "regulator-fixed";
475 reg = <4>;
476 regulator-name = "modem_3v3";
477 regulator-min-microvolt = <3300000>;
478 regulator-max-microvolt = <3300000>;
479 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]480 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]481 };
482
483 pex_hvdd_3v3_reg: regulator@5 {
484 compatible = "regulator-fixed";
485 reg = <5>;
486 regulator-name = "pex_hvdd_3v3";
487 regulator-min-microvolt = <3300000>;
488 regulator-max-microvolt = <3300000>;
489 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]490 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]491 vin-supply = <&sys_3v3_reg>;
492 };
493
494 vdd_cam1_ldo_reg: regulator@6 {
495 compatible = "regulator-fixed";
496 reg = <6>;
497 regulator-name = "vdd_cam1_ldo";
498 regulator-min-microvolt = <2800000>;
499 regulator-max-microvolt = <2800000>;
500 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]501 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]502 vin-supply = <&sys_3v3_reg>;
503 };
504
505 vdd_cam2_ldo_reg: regulator@7 {
506 compatible = "regulator-fixed";
507 reg = <7>;
508 regulator-name = "vdd_cam2_ldo";
509 regulator-min-microvolt = <2800000>;
510 regulator-max-microvolt = <2800000>;
511 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]512 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]513 vin-supply = <&sys_3v3_reg>;
514 };
515
516 vdd_cam3_ldo_reg: regulator@8 {
517 compatible = "regulator-fixed";
518 reg = <8>;
519 regulator-name = "vdd_cam3_ldo";
520 regulator-min-microvolt = <3300000>;
521 regulator-max-microvolt = <3300000>;
522 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]523 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]524 vin-supply = <&sys_3v3_reg>;
525 };
526
527 vdd_com_reg: regulator@9 {
528 compatible = "regulator-fixed";
529 reg = <9>;
530 regulator-name = "vdd_com";
531 regulator-min-microvolt = <3300000>;
532 regulator-max-microvolt = <3300000>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]533 regulator-always-on;
534 regulator-boot-on;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]535 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]536 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]537 vin-supply = <&sys_3v3_reg>;
538 };
539
540 vdd_fuse_3v3_reg: regulator@10 {
541 compatible = "regulator-fixed";
542 reg = <10>;
543 regulator-name = "vdd_fuse_3v3";
544 regulator-min-microvolt = <3300000>;
545 regulator-max-microvolt = <3300000>;
546 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]547 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]548 vin-supply = <&sys_3v3_reg>;
549 };
550
551 vdd_pnl1_reg: regulator@11 {
552 compatible = "regulator-fixed";
553 reg = <11>;
554 regulator-name = "vdd_pnl1";
555 regulator-min-microvolt = <3300000>;
556 regulator-max-microvolt = <3300000>;
557 regulator-always-on;
558 regulator-boot-on;
559 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]560 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]561 vin-supply = <&sys_3v3_reg>;
562 };
563
564 vdd_vid_reg: regulator@12 {
565 compatible = "regulator-fixed";
566 reg = <12>;
567 regulator-name = "vddio_vid";
568 regulator-min-microvolt = <5000000>;
569 regulator-max-microvolt = <5000000>;
570 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]571 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]572 gpio-open-drain;
573 vin-supply = <&vdd_5v0_reg>;
574 };
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]575 };
576
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]577 sound {
578 compatible = "nvidia,tegra-audio-wm8903-cardhu",
579 "nvidia,tegra-audio-wm8903";
580 nvidia,model = "NVIDIA Tegra Cardhu";
581
582 nvidia,audio-routing =
583 "Headphone Jack", "HPOUTR",
584 "Headphone Jack", "HPOUTL",
585 "Int Spk", "ROP",
586 "Int Spk", "RON",
587 "Int Spk", "LOP",
588 "Int Spk", "LON",
589 "Mic Jack", "MICBIAS",
590 "IN1L", "Mic Jack";
591
592 nvidia,i2s-controller = <&tegra_i2s1>;
593 nvidia,audio-codec = <&wm8903>;
594
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]595 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
596 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
597 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]598
Hiroshi Doyu05849c92013-05-22 19:45:34 +0300[diff] [blame]599 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
600 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
601 <&tegra_car TEGRA30_CLK_EXTERN1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]602 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]603 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]604};