blob: 874b60b2e20f225d39616f027dbc805eafb987dc [file] [log] [blame]
Brett Russ20f733e2005-09-01 18:26:17 -04001/*
2 * sata_mv.c - Marvell SATA support
3 *
Mark Lorde12bef52008-03-31 19:33:56 -04004 * Copyright 2008: Marvell Corporation, all rights reserved.
Jeff Garzik8b260242005-11-12 12:32:50 -05005 * Copyright 2005: EMC Corporation, all rights reserved.
Jeff Garzike2b1be52005-11-18 14:04:23 -05006 * Copyright 2005 Red Hat, Inc. All rights reserved.
Brett Russ20f733e2005-09-01 18:26:17 -04007 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
Jeff Garzik4a05e202007-05-24 23:40:15 -040025/*
Mark Lord85afb932008-04-19 14:54:41 -040026 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 *
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
37 *
Mark Lord85afb932008-04-19 14:54:41 -040038 * --> Develop a low-power-consumption strategy, and implement it.
39 *
40 * --> [Experiment, low priority] Investigate interrupt coalescing.
41 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
42 * the overhead reduced by interrupt mitigation is quite often not
43 * worth the latency cost.
44 *
45 * --> [Experiment, Marvell value added] Is it possible to use target
46 * mode to cross-connect two Linux boxes with Marvell cards? If so,
47 * creating LibATA target mode support would be very interesting.
48 *
49 * Target mode, for those without docs, is the ability to directly
50 * connect two SATA ports.
51 */
Jeff Garzik4a05e202007-05-24 23:40:15 -040052
Brett Russ20f733e2005-09-01 18:26:17 -040053#include <linux/kernel.h>
54#include <linux/module.h>
55#include <linux/pci.h>
56#include <linux/init.h>
57#include <linux/blkdev.h>
58#include <linux/delay.h>
59#include <linux/interrupt.h>
Andrew Morton8d8b6002008-02-04 23:43:44 -080060#include <linux/dmapool.h>
Brett Russ20f733e2005-09-01 18:26:17 -040061#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050062#include <linux/device.h>
Saeed Bisharaf351b2d2008-02-01 18:08:03 -050063#include <linux/platform_device.h>
64#include <linux/ata_platform.h>
Lennert Buytenhek15a32632008-03-27 14:51:39 -040065#include <linux/mbus.h>
Mark Lordc46938c2008-05-02 14:02:28 -040066#include <linux/bitops.h>
Brett Russ20f733e2005-09-01 18:26:17 -040067#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050068#include <scsi/scsi_cmnd.h>
Jeff Garzik6c087722007-10-12 00:16:23 -040069#include <scsi/scsi_device.h>
Brett Russ20f733e2005-09-01 18:26:17 -040070#include <linux/libata.h>
Brett Russ20f733e2005-09-01 18:26:17 -040071
72#define DRV_NAME "sata_mv"
Mark Lord0388a8c2008-05-28 13:41:52 -040073#define DRV_VERSION "1.24"
Brett Russ20f733e2005-09-01 18:26:17 -040074
75enum {
76 /* BAR's are enumerated in terms of pci_resource_start() terms */
77 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
78 MV_IO_BAR = 2, /* offset 0x18: IO space */
79 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
80
81 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
82 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
83
84 MV_PCI_REG_BASE = 0,
85 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
Mark Lord615ab952006-05-19 16:24:56 -040086 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
87 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
88 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
89 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
90 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
91
Brett Russ20f733e2005-09-01 18:26:17 -040092 MV_SATAHC0_REG_BASE = 0x20000,
Mark Lord8e7decd2008-05-02 02:07:51 -040093 MV_FLASH_CTL_OFS = 0x1046c,
94 MV_GPIO_PORT_CTL_OFS = 0x104f0,
95 MV_RESET_CFG_OFS = 0x180d8,
Brett Russ20f733e2005-09-01 18:26:17 -040096
97 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
98 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
99 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
100 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
101
Brett Russ31961942005-09-30 01:36:00 -0400102 MV_MAX_Q_DEPTH = 32,
103 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
104
105 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
106 * CRPB needs alignment on a 256B boundary. Size == 256B
Brett Russ31961942005-09-30 01:36:00 -0400107 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
108 */
109 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
110 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
Mark Lordda2fa9b2008-01-26 18:32:45 -0500111 MV_MAX_SG_CT = 256,
Brett Russ31961942005-09-30 01:36:00 -0400112 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
Brett Russ31961942005-09-30 01:36:00 -0400113
Mark Lord352fab72008-04-19 14:43:42 -0400114 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
Brett Russ20f733e2005-09-01 18:26:17 -0400115 MV_PORT_HC_SHIFT = 2,
Mark Lord352fab72008-04-19 14:43:42 -0400116 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
117 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
118 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
Brett Russ20f733e2005-09-01 18:26:17 -0400119
120 /* Host Flags */
121 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
122 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
Saeed Bishara7bb3c522008-01-30 11:50:45 -1100123
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400124 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400125 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
126 ATA_FLAG_PIO_POLLING,
Mark Lordad3aef52008-05-14 09:21:43 -0400127
Jeff Garzik47c2b672005-11-12 21:13:17 -0500128 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
Brett Russ20f733e2005-09-01 18:26:17 -0400129
Mark Lordad3aef52008-05-14 09:21:43 -0400130 MV_GENIIE_FLAGS = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
131 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
Mark Lordc443c502008-05-14 09:24:39 -0400132 ATA_FLAG_NCQ | ATA_FLAG_AN,
Mark Lordad3aef52008-05-14 09:21:43 -0400133
Brett Russ31961942005-09-30 01:36:00 -0400134 CRQB_FLAG_READ = (1 << 0),
135 CRQB_TAG_SHIFT = 1,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400136 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
Mark Lorde12bef52008-03-31 19:33:56 -0400137 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400138 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
Brett Russ31961942005-09-30 01:36:00 -0400139 CRQB_CMD_ADDR_SHIFT = 8,
140 CRQB_CMD_CS = (0x2 << 11),
141 CRQB_CMD_LAST = (1 << 15),
142
143 CRPB_FLAG_STATUS_SHIFT = 8,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400144 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
145 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
Brett Russ31961942005-09-30 01:36:00 -0400146
147 EPRD_FLAG_END_OF_TBL = (1 << 31),
148
Brett Russ20f733e2005-09-01 18:26:17 -0400149 /* PCI interface registers */
150
Brett Russ31961942005-09-30 01:36:00 -0400151 PCI_COMMAND_OFS = 0xc00,
Mark Lord8e7decd2008-05-02 02:07:51 -0400152 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
Brett Russ31961942005-09-30 01:36:00 -0400153
Brett Russ20f733e2005-09-01 18:26:17 -0400154 PCI_MAIN_CMD_STS_OFS = 0xd30,
155 STOP_PCI_MASTER = (1 << 2),
156 PCI_MASTER_EMPTY = (1 << 3),
157 GLOB_SFT_RST = (1 << 4),
158
Mark Lord8e7decd2008-05-02 02:07:51 -0400159 MV_PCI_MODE_OFS = 0xd00,
160 MV_PCI_MODE_MASK = 0x30,
161
Jeff Garzik522479f2005-11-12 22:14:02 -0500162 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
163 MV_PCI_DISC_TIMER = 0xd04,
164 MV_PCI_MSI_TRIGGER = 0xc38,
165 MV_PCI_SERR_MASK = 0xc28,
Mark Lord8e7decd2008-05-02 02:07:51 -0400166 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
Jeff Garzik522479f2005-11-12 22:14:02 -0500167 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
168 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
169 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
170 MV_PCI_ERR_COMMAND = 0x1d50,
171
Mark Lord02a121d2007-12-01 13:07:22 -0500172 PCI_IRQ_CAUSE_OFS = 0x1d58,
173 PCI_IRQ_MASK_OFS = 0x1d5c,
Brett Russ20f733e2005-09-01 18:26:17 -0400174 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
175
Mark Lord02a121d2007-12-01 13:07:22 -0500176 PCIE_IRQ_CAUSE_OFS = 0x1900,
177 PCIE_IRQ_MASK_OFS = 0x1910,
Mark Lord646a4da2008-01-26 18:30:37 -0500178 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
Mark Lord02a121d2007-12-01 13:07:22 -0500179
Mark Lord7368f912008-04-25 11:24:24 -0400180 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
181 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
182 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
183 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
184 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
Mark Lord352fab72008-04-19 14:43:42 -0400185 ERR_IRQ = (1 << 0), /* shift by port # */
186 DONE_IRQ = (1 << 1), /* shift by port # */
Brett Russ20f733e2005-09-01 18:26:17 -0400187 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
188 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
189 PCI_ERR = (1 << 18),
190 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
191 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
Jeff Garzikfb621e22007-02-25 04:19:45 -0500192 PORTS_0_3_COAL_DONE = (1 << 8),
193 PORTS_4_7_COAL_DONE = (1 << 17),
Brett Russ20f733e2005-09-01 18:26:17 -0400194 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
195 GPIO_INT = (1 << 22),
196 SELF_INT = (1 << 23),
197 TWSI_INT = (1 << 24),
198 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
Jeff Garzikfb621e22007-02-25 04:19:45 -0500199 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
Mark Lorde12bef52008-03-31 19:33:56 -0400200 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
Brett Russ20f733e2005-09-01 18:26:17 -0400201
202 /* SATAHC registers */
203 HC_CFG_OFS = 0,
204
205 HC_IRQ_CAUSE_OFS = 0x14,
Mark Lord352fab72008-04-19 14:43:42 -0400206 DMA_IRQ = (1 << 0), /* shift by port # */
207 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
Brett Russ20f733e2005-09-01 18:26:17 -0400208 DEV_IRQ = (1 << 8), /* shift by port # */
209
210 /* Shadow block registers */
Brett Russ31961942005-09-30 01:36:00 -0400211 SHD_BLK_OFS = 0x100,
212 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
Brett Russ20f733e2005-09-01 18:26:17 -0400213
214 /* SATA registers */
215 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
216 SATA_ACTIVE_OFS = 0x350,
Mark Lord0c589122008-01-26 18:31:16 -0500217 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
Mark Lordc443c502008-05-14 09:24:39 -0400218 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
Mark Lord17c5aab2008-04-16 14:56:51 -0400219
Mark Lorde12bef52008-03-31 19:33:56 -0400220 LTMODE_OFS = 0x30c,
Mark Lord17c5aab2008-04-16 14:56:51 -0400221 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
222
Jeff Garzik47c2b672005-11-12 21:13:17 -0500223 PHY_MODE3 = 0x310,
Jeff Garzikbca1c4e2005-11-12 12:48:15 -0500224 PHY_MODE4 = 0x314,
Mark Lordba069e32008-05-31 16:46:34 -0400225 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
226 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
227 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
228 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
229
Jeff Garzikbca1c4e2005-11-12 12:48:15 -0500230 PHY_MODE2 = 0x330,
Mark Lorde12bef52008-03-31 19:33:56 -0400231 SATA_IFCTL_OFS = 0x344,
Mark Lord8e7decd2008-05-02 02:07:51 -0400232 SATA_TESTCTL_OFS = 0x348,
Mark Lorde12bef52008-03-31 19:33:56 -0400233 SATA_IFSTAT_OFS = 0x34c,
234 VENDOR_UNIQUE_FIS_OFS = 0x35c,
Mark Lord17c5aab2008-04-16 14:56:51 -0400235
Mark Lord8e7decd2008-05-02 02:07:51 -0400236 FISCFG_OFS = 0x360,
237 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
238 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
Mark Lord17c5aab2008-04-16 14:56:51 -0400239
Jeff Garzikc9d39132005-11-13 17:47:51 -0500240 MV5_PHY_MODE = 0x74,
Mark Lord8e7decd2008-05-02 02:07:51 -0400241 MV5_LTMODE_OFS = 0x30,
242 MV5_PHY_CTL_OFS = 0x0C,
243 SATA_INTERFACE_CFG_OFS = 0x050,
Jeff Garzikbca1c4e2005-11-12 12:48:15 -0500244
245 MV_M2_PREAMP_MASK = 0x7e0,
Brett Russ20f733e2005-09-01 18:26:17 -0400246
247 /* Port registers */
248 EDMA_CFG_OFS = 0,
Mark Lord0c589122008-01-26 18:31:16 -0500249 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
250 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
251 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
252 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
253 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
Mark Lorde12bef52008-03-31 19:33:56 -0400254 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
255 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
Brett Russ20f733e2005-09-01 18:26:17 -0400256
257 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
258 EDMA_ERR_IRQ_MASK_OFS = 0xc,
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400259 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
260 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
261 EDMA_ERR_DEV = (1 << 2), /* device error */
262 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
263 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
264 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400265 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
266 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400267 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400268 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400269 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
270 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
271 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
272 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
Mark Lord646a4da2008-01-26 18:30:37 -0500273
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400274 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
Mark Lord646a4da2008-01-26 18:30:37 -0500275 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
276 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
277 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
278 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
279
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400280 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
Mark Lord646a4da2008-01-26 18:30:37 -0500281
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400282 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
Mark Lord646a4da2008-01-26 18:30:37 -0500283 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
284 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
285 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
286 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
287 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
288
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400289 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
Mark Lord646a4da2008-01-26 18:30:37 -0500290
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400291 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400292 EDMA_ERR_OVERRUN_5 = (1 << 5),
293 EDMA_ERR_UNDERRUN_5 = (1 << 6),
Mark Lord646a4da2008-01-26 18:30:37 -0500294
295 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
296 EDMA_ERR_LNK_CTRL_RX_1 |
297 EDMA_ERR_LNK_CTRL_RX_3 |
Mark Lord85afb932008-04-19 14:54:41 -0400298 EDMA_ERR_LNK_CTRL_TX,
Mark Lord646a4da2008-01-26 18:30:37 -0500299
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400300 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
301 EDMA_ERR_PRD_PAR |
302 EDMA_ERR_DEV_DCON |
303 EDMA_ERR_DEV_CON |
304 EDMA_ERR_SERR |
305 EDMA_ERR_SELF_DIS |
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400306 EDMA_ERR_CRQB_PAR |
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400307 EDMA_ERR_CRPB_PAR |
308 EDMA_ERR_INTRL_PAR |
309 EDMA_ERR_IORDY |
310 EDMA_ERR_LNK_CTRL_RX_2 |
311 EDMA_ERR_LNK_DATA_RX |
312 EDMA_ERR_LNK_DATA_TX |
313 EDMA_ERR_TRANS_PROTO,
Mark Lorde12bef52008-03-31 19:33:56 -0400314
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400315 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
316 EDMA_ERR_PRD_PAR |
317 EDMA_ERR_DEV_DCON |
318 EDMA_ERR_DEV_CON |
319 EDMA_ERR_OVERRUN_5 |
320 EDMA_ERR_UNDERRUN_5 |
321 EDMA_ERR_SELF_DIS_5 |
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400322 EDMA_ERR_CRQB_PAR |
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400323 EDMA_ERR_CRPB_PAR |
324 EDMA_ERR_INTRL_PAR |
325 EDMA_ERR_IORDY,
Brett Russ20f733e2005-09-01 18:26:17 -0400326
Brett Russ31961942005-09-30 01:36:00 -0400327 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
328 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
Brett Russ31961942005-09-30 01:36:00 -0400329
330 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
331 EDMA_REQ_Q_PTR_SHIFT = 5,
332
333 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
334 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
335 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
Brett Russ31961942005-09-30 01:36:00 -0400336 EDMA_RSP_Q_PTR_SHIFT = 3,
337
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400338 EDMA_CMD_OFS = 0x28, /* EDMA command register */
339 EDMA_EN = (1 << 0), /* enable EDMA */
340 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
Mark Lord8e7decd2008-05-02 02:07:51 -0400341 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
Brett Russ20f733e2005-09-01 18:26:17 -0400342
Mark Lord8e7decd2008-05-02 02:07:51 -0400343 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
344 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
345 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
346
347 EDMA_IORDY_TMOUT_OFS = 0x34,
348 EDMA_ARB_CFG_OFS = 0x38,
349
350 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
Jeff Garzikbca1c4e2005-11-12 12:48:15 -0500351
Brett Russ31961942005-09-30 01:36:00 -0400352 /* Host private flags (hp_flags) */
353 MV_HP_FLAG_MSI = (1 << 0),
Jeff Garzik47c2b672005-11-12 21:13:17 -0500354 MV_HP_ERRATA_50XXB0 = (1 << 1),
355 MV_HP_ERRATA_50XXB2 = (1 << 2),
356 MV_HP_ERRATA_60X1B2 = (1 << 3),
357 MV_HP_ERRATA_60X1C0 = (1 << 4),
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400358 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
359 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
360 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
Mark Lord02a121d2007-12-01 13:07:22 -0500361 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
Mark Lord616d4a92008-05-02 02:08:32 -0400362 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
Mark Lord1f398472008-05-27 17:54:48 -0400363 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
Brett Russ20f733e2005-09-01 18:26:17 -0400364
Brett Russ31961942005-09-30 01:36:00 -0400365 /* Port private flags (pp_flags) */
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400366 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
Mark Lord72109162008-01-26 18:31:33 -0500367 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
Mark Lord00f42ea2008-05-02 02:11:45 -0400368 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
Mark Lord29d187b2008-05-02 02:15:37 -0400369 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
Brett Russ31961942005-09-30 01:36:00 -0400370};
371
Jeff Garzikee9ccdf2007-07-12 15:51:22 -0400372#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
373#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
Jeff Garzike4e7b892006-01-31 12:18:41 -0500374#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
Mark Lord8e7decd2008-05-02 02:07:51 -0400375#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
Mark Lord1f398472008-05-27 17:54:48 -0400376#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
Jeff Garzikbca1c4e2005-11-12 12:48:15 -0500377
Lennert Buytenhek15a32632008-03-27 14:51:39 -0400378#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
379#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
380
Jeff Garzik095fec82005-11-12 09:50:49 -0500381enum {
Jeff Garzikbaf14aa2007-10-09 13:51:57 -0400382 /* DMA boundary 0xffff is required by the s/g splitting
383 * we need on /length/ in mv_fill-sg().
384 */
385 MV_DMA_BOUNDARY = 0xffffU,
Jeff Garzik095fec82005-11-12 09:50:49 -0500386
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400387 /* mask of register bits containing lower 32 bits
388 * of EDMA request queue DMA address
389 */
Jeff Garzik095fec82005-11-12 09:50:49 -0500390 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
391
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400392 /* ditto, for response queue */
Jeff Garzik095fec82005-11-12 09:50:49 -0500393 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
394};
395
Jeff Garzik522479f2005-11-12 22:14:02 -0500396enum chip_type {
397 chip_504x,
398 chip_508x,
399 chip_5080,
400 chip_604x,
401 chip_608x,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500402 chip_6042,
403 chip_7042,
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500404 chip_soc,
Jeff Garzik522479f2005-11-12 22:14:02 -0500405};
406
Brett Russ31961942005-09-30 01:36:00 -0400407/* Command ReQuest Block: 32B */
408struct mv_crqb {
Mark Lorde1469872006-05-22 19:02:03 -0400409 __le32 sg_addr;
410 __le32 sg_addr_hi;
411 __le16 ctrl_flags;
412 __le16 ata_cmd[11];
Brett Russ31961942005-09-30 01:36:00 -0400413};
414
Jeff Garzike4e7b892006-01-31 12:18:41 -0500415struct mv_crqb_iie {
Mark Lorde1469872006-05-22 19:02:03 -0400416 __le32 addr;
417 __le32 addr_hi;
418 __le32 flags;
419 __le32 len;
420 __le32 ata_cmd[4];
Jeff Garzike4e7b892006-01-31 12:18:41 -0500421};
422
Brett Russ31961942005-09-30 01:36:00 -0400423/* Command ResPonse Block: 8B */
424struct mv_crpb {
Mark Lorde1469872006-05-22 19:02:03 -0400425 __le16 id;
426 __le16 flags;
427 __le32 tmstmp;
Brett Russ31961942005-09-30 01:36:00 -0400428};
429
430/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
431struct mv_sg {
Mark Lorde1469872006-05-22 19:02:03 -0400432 __le32 addr;
433 __le32 flags_size;
434 __le32 addr_hi;
435 __le32 reserved;
Brett Russ20f733e2005-09-01 18:26:17 -0400436};
437
438struct mv_port_priv {
Brett Russ31961942005-09-30 01:36:00 -0400439 struct mv_crqb *crqb;
440 dma_addr_t crqb_dma;
441 struct mv_crpb *crpb;
442 dma_addr_t crpb_dma;
Mark Lordeb73d552008-01-29 13:24:00 -0500443 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
444 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400445
446 unsigned int req_idx;
447 unsigned int resp_idx;
448
Brett Russ31961942005-09-30 01:36:00 -0400449 u32 pp_flags;
Mark Lord29d187b2008-05-02 02:15:37 -0400450 unsigned int delayed_eh_pmp_map;
Brett Russ20f733e2005-09-01 18:26:17 -0400451};
452
Jeff Garzikbca1c4e2005-11-12 12:48:15 -0500453struct mv_port_signal {
454 u32 amps;
455 u32 pre;
456};
457
Mark Lord02a121d2007-12-01 13:07:22 -0500458struct mv_host_priv {
459 u32 hp_flags;
Mark Lord96e2c4872008-05-17 13:38:00 -0400460 u32 main_irq_mask;
Mark Lord02a121d2007-12-01 13:07:22 -0500461 struct mv_port_signal signal[8];
462 const struct mv_hw_ops *ops;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500463 int n_ports;
464 void __iomem *base;
Mark Lord7368f912008-04-25 11:24:24 -0400465 void __iomem *main_irq_cause_addr;
466 void __iomem *main_irq_mask_addr;
Mark Lord02a121d2007-12-01 13:07:22 -0500467 u32 irq_cause_ofs;
468 u32 irq_mask_ofs;
469 u32 unmask_all_irqs;
Mark Lordda2fa9b2008-01-26 18:32:45 -0500470 /*
471 * These consistent DMA memory pools give us guaranteed
472 * alignment for hardware-accessed data structures,
473 * and less memory waste in accomplishing the alignment.
474 */
475 struct dma_pool *crqb_pool;
476 struct dma_pool *crpb_pool;
477 struct dma_pool *sg_tbl_pool;
Mark Lord02a121d2007-12-01 13:07:22 -0500478};
479
Jeff Garzik47c2b672005-11-12 21:13:17 -0500480struct mv_hw_ops {
Jeff Garzik2a47ce02005-11-12 23:05:14 -0500481 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
482 unsigned int port);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500483 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
484 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
485 void __iomem *mmio);
Jeff Garzikc9d39132005-11-13 17:47:51 -0500486 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
487 unsigned int n_hc);
Jeff Garzik522479f2005-11-12 22:14:02 -0500488 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
Saeed Bishara7bb3c522008-01-30 11:50:45 -1100489 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500490};
491
Tejun Heo82ef04f2008-07-31 17:02:40 +0900492static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
493static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
494static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
495static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
Brett Russ31961942005-09-30 01:36:00 -0400496static int mv_port_start(struct ata_port *ap);
497static void mv_port_stop(struct ata_port *ap);
Mark Lord3e4a1392008-05-02 02:10:02 -0400498static int mv_qc_defer(struct ata_queued_cmd *qc);
Brett Russ31961942005-09-30 01:36:00 -0400499static void mv_qc_prep(struct ata_queued_cmd *qc);
Jeff Garzike4e7b892006-01-31 12:18:41 -0500500static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900501static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900502static int mv_hardreset(struct ata_link *link, unsigned int *class,
503 unsigned long deadline);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400504static void mv_eh_freeze(struct ata_port *ap);
505static void mv_eh_thaw(struct ata_port *ap);
Mark Lordf2738272008-01-26 18:32:29 -0500506static void mv6_dev_config(struct ata_device *dev);
Brett Russ20f733e2005-09-01 18:26:17 -0400507
Jeff Garzik2a47ce02005-11-12 23:05:14 -0500508static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
509 unsigned int port);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500510static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
511static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
512 void __iomem *mmio);
Jeff Garzikc9d39132005-11-13 17:47:51 -0500513static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
514 unsigned int n_hc);
Jeff Garzik522479f2005-11-12 22:14:02 -0500515static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
Saeed Bishara7bb3c522008-01-30 11:50:45 -1100516static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500517
Jeff Garzik2a47ce02005-11-12 23:05:14 -0500518static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
519 unsigned int port);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500520static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
521static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
522 void __iomem *mmio);
Jeff Garzikc9d39132005-11-13 17:47:51 -0500523static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
524 unsigned int n_hc);
Jeff Garzik522479f2005-11-12 22:14:02 -0500525static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500526static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
527 void __iomem *mmio);
528static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
529 void __iomem *mmio);
530static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
531 void __iomem *mmio, unsigned int n_hc);
532static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
533 void __iomem *mmio);
534static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
Saeed Bishara7bb3c522008-01-30 11:50:45 -1100535static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
Mark Lorde12bef52008-03-31 19:33:56 -0400536static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500537 unsigned int port_no);
Mark Lorde12bef52008-03-31 19:33:56 -0400538static int mv_stop_edma(struct ata_port *ap);
Mark Lordb5624682008-03-31 19:34:40 -0400539static int mv_stop_edma_engine(void __iomem *port_mmio);
Mark Lorde12bef52008-03-31 19:33:56 -0400540static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500541
Mark Lorde49856d2008-04-16 14:59:07 -0400542static void mv_pmp_select(struct ata_port *ap, int pmp);
543static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
544 unsigned long deadline);
545static int mv_softreset(struct ata_link *link, unsigned int *class,
546 unsigned long deadline);
Mark Lord29d187b2008-05-02 02:15:37 -0400547static void mv_pmp_error_handler(struct ata_port *ap);
Mark Lord4c299ca2008-05-02 02:16:20 -0400548static void mv_process_crpb_entries(struct ata_port *ap,
549 struct mv_port_priv *pp);
Brett Russ20f733e2005-09-01 18:26:17 -0400550
Mark Lordeb73d552008-01-29 13:24:00 -0500551/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
552 * because we have to allow room for worst case splitting of
553 * PRDs for 64K boundaries in mv_fill_sg().
554 */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400555static struct scsi_host_template mv5_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900556 ATA_BASE_SHT(DRV_NAME),
Jeff Garzikbaf14aa2007-10-09 13:51:57 -0400557 .sg_tablesize = MV_MAX_SG_CT / 2,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400558 .dma_boundary = MV_DMA_BOUNDARY,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400559};
560
561static struct scsi_host_template mv6_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900562 ATA_NCQ_SHT(DRV_NAME),
Mark Lord138bfdd2008-01-26 18:33:18 -0500563 .can_queue = MV_MAX_Q_DEPTH - 1,
Jeff Garzikbaf14aa2007-10-09 13:51:57 -0400564 .sg_tablesize = MV_MAX_SG_CT / 2,
Brett Russ20f733e2005-09-01 18:26:17 -0400565 .dma_boundary = MV_DMA_BOUNDARY,
Brett Russ20f733e2005-09-01 18:26:17 -0400566};
567
Tejun Heo029cfd62008-03-25 12:22:49 +0900568static struct ata_port_operations mv5_ops = {
569 .inherits = &ata_sff_port_ops,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500570
Mark Lord3e4a1392008-05-02 02:10:02 -0400571 .qc_defer = mv_qc_defer,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500572 .qc_prep = mv_qc_prep,
573 .qc_issue = mv_qc_issue,
574
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400575 .freeze = mv_eh_freeze,
576 .thaw = mv_eh_thaw,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900577 .hardreset = mv_hardreset,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900578 .error_handler = ata_std_error_handler, /* avoid SFF EH */
Tejun Heo029cfd62008-03-25 12:22:49 +0900579 .post_internal_cmd = ATA_OP_NULL,
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400580
Jeff Garzikc9d39132005-11-13 17:47:51 -0500581 .scr_read = mv5_scr_read,
582 .scr_write = mv5_scr_write,
583
584 .port_start = mv_port_start,
585 .port_stop = mv_port_stop,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500586};
587
Tejun Heo029cfd62008-03-25 12:22:49 +0900588static struct ata_port_operations mv6_ops = {
589 .inherits = &mv5_ops,
Mark Lordf2738272008-01-26 18:32:29 -0500590 .dev_config = mv6_dev_config,
Brett Russ20f733e2005-09-01 18:26:17 -0400591 .scr_read = mv_scr_read,
592 .scr_write = mv_scr_write,
593
Mark Lorde49856d2008-04-16 14:59:07 -0400594 .pmp_hardreset = mv_pmp_hardreset,
595 .pmp_softreset = mv_softreset,
596 .softreset = mv_softreset,
Mark Lord29d187b2008-05-02 02:15:37 -0400597 .error_handler = mv_pmp_error_handler,
Brett Russ20f733e2005-09-01 18:26:17 -0400598};
599
Tejun Heo029cfd62008-03-25 12:22:49 +0900600static struct ata_port_operations mv_iie_ops = {
601 .inherits = &mv6_ops,
602 .dev_config = ATA_OP_NULL,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500603 .qc_prep = mv_qc_prep_iie,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500604};
605
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100606static const struct ata_port_info mv_port_info[] = {
Brett Russ20f733e2005-09-01 18:26:17 -0400607 { /* chip_504x */
Jeff Garzikcca39742006-08-24 03:19:22 -0400608 .flags = MV_COMMON_FLAGS,
Brett Russ31961942005-09-30 01:36:00 -0400609 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400610 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500611 .port_ops = &mv5_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400612 },
613 { /* chip_508x */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400614 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
Brett Russ31961942005-09-30 01:36:00 -0400615 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400616 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500617 .port_ops = &mv5_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400618 },
Jeff Garzik47c2b672005-11-12 21:13:17 -0500619 { /* chip_5080 */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400620 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
Jeff Garzik47c2b672005-11-12 21:13:17 -0500621 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400622 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500623 .port_ops = &mv5_ops,
Jeff Garzik47c2b672005-11-12 21:13:17 -0500624 },
Brett Russ20f733e2005-09-01 18:26:17 -0400625 { /* chip_604x */
Mark Lord138bfdd2008-01-26 18:33:18 -0500626 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
Mark Lorde49856d2008-04-16 14:59:07 -0400627 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
Mark Lord138bfdd2008-01-26 18:33:18 -0500628 ATA_FLAG_NCQ,
Brett Russ31961942005-09-30 01:36:00 -0400629 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400630 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500631 .port_ops = &mv6_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400632 },
633 { /* chip_608x */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400634 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
Mark Lorde49856d2008-04-16 14:59:07 -0400635 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
Mark Lord138bfdd2008-01-26 18:33:18 -0500636 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
Brett Russ31961942005-09-30 01:36:00 -0400637 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400638 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500639 .port_ops = &mv6_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400640 },
Jeff Garzike4e7b892006-01-31 12:18:41 -0500641 { /* chip_6042 */
Mark Lordad3aef52008-05-14 09:21:43 -0400642 .flags = MV_GENIIE_FLAGS,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500643 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400644 .udma_mask = ATA_UDMA6,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500645 .port_ops = &mv_iie_ops,
646 },
647 { /* chip_7042 */
Mark Lordad3aef52008-05-14 09:21:43 -0400648 .flags = MV_GENIIE_FLAGS,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500649 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400650 .udma_mask = ATA_UDMA6,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500651 .port_ops = &mv_iie_ops,
652 },
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500653 { /* chip_soc */
Mark Lord1f398472008-05-27 17:54:48 -0400654 .flags = MV_GENIIE_FLAGS,
Mark Lord17c5aab2008-04-16 14:56:51 -0400655 .pio_mask = 0x1f, /* pio0-4 */
656 .udma_mask = ATA_UDMA6,
657 .port_ops = &mv_iie_ops,
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500658 },
Brett Russ20f733e2005-09-01 18:26:17 -0400659};
660
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500661static const struct pci_device_id mv_pci_tbl[] = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400662 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
663 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
664 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
665 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
Mark Lord46c57842008-09-04 18:21:07 -0400666 /* RocketRAID 1720/174x have different identifiers */
667 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
Alan Coxcfbf7232007-07-09 14:38:41 +0100668 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
669 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
Brett Russ20f733e2005-09-01 18:26:17 -0400670
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400671 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
672 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
673 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
674 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
675 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
Jeff Garzik29179532005-11-11 08:08:03 -0500676
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400677 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
678
Florian Attenbergerd9f9c6b2007-07-02 17:09:29 +0200679 /* Adaptec 1430SA */
680 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
681
Mark Lord02a121d2007-12-01 13:07:22 -0500682 /* Marvell 7042 support */
Morrison, Tom6a3d5862007-03-06 02:38:10 -0800683 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
684
Mark Lord02a121d2007-12-01 13:07:22 -0500685 /* Highpoint RocketRAID PCIe series */
686 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
687 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
688
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400689 { } /* terminate list */
Brett Russ20f733e2005-09-01 18:26:17 -0400690};
691
Jeff Garzik47c2b672005-11-12 21:13:17 -0500692static const struct mv_hw_ops mv5xxx_ops = {
693 .phy_errata = mv5_phy_errata,
694 .enable_leds = mv5_enable_leds,
695 .read_preamp = mv5_read_preamp,
696 .reset_hc = mv5_reset_hc,
Jeff Garzik522479f2005-11-12 22:14:02 -0500697 .reset_flash = mv5_reset_flash,
698 .reset_bus = mv5_reset_bus,
Jeff Garzik47c2b672005-11-12 21:13:17 -0500699};
700
701static const struct mv_hw_ops mv6xxx_ops = {
702 .phy_errata = mv6_phy_errata,
703 .enable_leds = mv6_enable_leds,
704 .read_preamp = mv6_read_preamp,
705 .reset_hc = mv6_reset_hc,
Jeff Garzik522479f2005-11-12 22:14:02 -0500706 .reset_flash = mv6_reset_flash,
707 .reset_bus = mv_reset_pci_bus,
Jeff Garzik47c2b672005-11-12 21:13:17 -0500708};
709
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500710static const struct mv_hw_ops mv_soc_ops = {
711 .phy_errata = mv6_phy_errata,
712 .enable_leds = mv_soc_enable_leds,
713 .read_preamp = mv_soc_read_preamp,
714 .reset_hc = mv_soc_reset_hc,
715 .reset_flash = mv_soc_reset_flash,
716 .reset_bus = mv_soc_reset_bus,
717};
718
Brett Russ20f733e2005-09-01 18:26:17 -0400719/*
720 * Functions
721 */
722
723static inline void writelfl(unsigned long data, void __iomem *addr)
724{
725 writel(data, addr);
726 (void) readl(addr); /* flush to avoid PCI posted write */
727}
728
Jeff Garzikc9d39132005-11-13 17:47:51 -0500729static inline unsigned int mv_hc_from_port(unsigned int port)
730{
731 return port >> MV_PORT_HC_SHIFT;
732}
733
734static inline unsigned int mv_hardport_from_port(unsigned int port)
735{
736 return port & MV_PORT_MASK;
737}
738
Mark Lord1cfd19a2008-04-19 15:05:50 -0400739/*
740 * Consolidate some rather tricky bit shift calculations.
741 * This is hot-path stuff, so not a function.
742 * Simple code, with two return values, so macro rather than inline.
743 *
744 * port is the sole input, in range 0..7.
Mark Lord7368f912008-04-25 11:24:24 -0400745 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
746 * hardport is the other output, in range 0..3.
Mark Lord1cfd19a2008-04-19 15:05:50 -0400747 *
748 * Note that port and hardport may be the same variable in some cases.
749 */
750#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
751{ \
752 shift = mv_hc_from_port(port) * HC_SHIFT; \
753 hardport = mv_hardport_from_port(port); \
754 shift += hardport * 2; \
755}
756
Mark Lord352fab72008-04-19 14:43:42 -0400757static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
758{
759 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
760}
761
Jeff Garzikc9d39132005-11-13 17:47:51 -0500762static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
763 unsigned int port)
764{
765 return mv_hc_base(base, mv_hc_from_port(port));
766}
767
Brett Russ20f733e2005-09-01 18:26:17 -0400768static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
769{
Jeff Garzikc9d39132005-11-13 17:47:51 -0500770 return mv_hc_base_from_port(base, port) +
Jeff Garzik8b260242005-11-12 12:32:50 -0500771 MV_SATAHC_ARBTR_REG_SZ +
Jeff Garzikc9d39132005-11-13 17:47:51 -0500772 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
Brett Russ20f733e2005-09-01 18:26:17 -0400773}
774
Mark Lorde12bef52008-03-31 19:33:56 -0400775static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
776{
777 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
778 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
779
780 return hc_mmio + ofs;
781}
782
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500783static inline void __iomem *mv_host_base(struct ata_host *host)
784{
785 struct mv_host_priv *hpriv = host->private_data;
786 return hpriv->base;
787}
788
Brett Russ20f733e2005-09-01 18:26:17 -0400789static inline void __iomem *mv_ap_base(struct ata_port *ap)
790{
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500791 return mv_port_base(mv_host_base(ap->host), ap->port_no);
Brett Russ20f733e2005-09-01 18:26:17 -0400792}
793
Jeff Garzikcca39742006-08-24 03:19:22 -0400794static inline int mv_get_hc_count(unsigned long port_flags)
Brett Russ20f733e2005-09-01 18:26:17 -0400795{
Jeff Garzikcca39742006-08-24 03:19:22 -0400796 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
Brett Russ20f733e2005-09-01 18:26:17 -0400797}
798
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400799static void mv_set_edma_ptrs(void __iomem *port_mmio,
800 struct mv_host_priv *hpriv,
801 struct mv_port_priv *pp)
802{
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400803 u32 index;
804
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400805 /*
806 * initialize request queue
807 */
Mark Lordfcfb1f72008-04-19 15:06:40 -0400808 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
809 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400810
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400811 WARN_ON(pp->crqb_dma & 0x3ff);
812 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400813 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400814 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
Mark Lord5cf73bf2008-05-27 17:58:56 -0400815 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400816
817 /*
818 * initialize response queue
819 */
Mark Lordfcfb1f72008-04-19 15:06:40 -0400820 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
821 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400822
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400823 WARN_ON(pp->crpb_dma & 0xff);
824 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
Mark Lord5cf73bf2008-05-27 17:58:56 -0400825 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400826 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400827 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400828}
829
Mark Lordc4de5732008-05-17 13:35:21 -0400830static void mv_set_main_irq_mask(struct ata_host *host,
831 u32 disable_bits, u32 enable_bits)
832{
833 struct mv_host_priv *hpriv = host->private_data;
834 u32 old_mask, new_mask;
835
Mark Lord96e2c4872008-05-17 13:38:00 -0400836 old_mask = hpriv->main_irq_mask;
Mark Lordc4de5732008-05-17 13:35:21 -0400837 new_mask = (old_mask & ~disable_bits) | enable_bits;
Mark Lord96e2c4872008-05-17 13:38:00 -0400838 if (new_mask != old_mask) {
839 hpriv->main_irq_mask = new_mask;
Mark Lordc4de5732008-05-17 13:35:21 -0400840 writelfl(new_mask, hpriv->main_irq_mask_addr);
Mark Lord96e2c4872008-05-17 13:38:00 -0400841 }
Mark Lordc4de5732008-05-17 13:35:21 -0400842}
843
844static void mv_enable_port_irqs(struct ata_port *ap,
845 unsigned int port_bits)
846{
847 unsigned int shift, hardport, port = ap->port_no;
848 u32 disable_bits, enable_bits;
849
850 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
851
852 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
853 enable_bits = port_bits << shift;
854 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
855}
856
Brett Russ05b308e2005-10-05 17:08:53 -0400857/**
858 * mv_start_dma - Enable eDMA engine
859 * @base: port base address
860 * @pp: port private data
861 *
Tejun Heobeec7db2006-02-11 19:11:13 +0900862 * Verify the local cache of the eDMA state is accurate with a
863 * WARN_ON.
Brett Russ05b308e2005-10-05 17:08:53 -0400864 *
865 * LOCKING:
866 * Inherited from caller.
867 */
Mark Lord0c589122008-01-26 18:31:16 -0500868static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
Mark Lord72109162008-01-26 18:31:33 -0500869 struct mv_port_priv *pp, u8 protocol)
Brett Russ31961942005-09-30 01:36:00 -0400870{
Mark Lord72109162008-01-26 18:31:33 -0500871 int want_ncq = (protocol == ATA_PROT_NCQ);
872
873 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
874 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
875 if (want_ncq != using_ncq)
Mark Lordb5624682008-03-31 19:34:40 -0400876 mv_stop_edma(ap);
Mark Lord72109162008-01-26 18:31:33 -0500877 }
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400878 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
Mark Lord0c589122008-01-26 18:31:16 -0500879 struct mv_host_priv *hpriv = ap->host->private_data;
Mark Lord352fab72008-04-19 14:43:42 -0400880 int hardport = mv_hardport_from_port(ap->port_no);
Mark Lord0c589122008-01-26 18:31:16 -0500881 void __iomem *hc_mmio = mv_hc_base_from_port(
Mark Lordb0bccb12009-01-19 18:04:37 -0500882 mv_host_base(ap->host), ap->port_no);
Mark Lordcae6edc2009-01-19 18:05:42 -0500883 u32 hc_irq_cause;
Mark Lord0c589122008-01-26 18:31:16 -0500884
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400885 /* clear EDMA event indicators, if any */
Mark Lordf630d562008-01-26 18:31:00 -0500886 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400887
Mark Lordcae6edc2009-01-19 18:05:42 -0500888 /* clear pending irq events */
889 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
890 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
Mark Lord0c589122008-01-26 18:31:16 -0500891
Mark Lorde12bef52008-03-31 19:33:56 -0400892 mv_edma_cfg(ap, want_ncq);
Mark Lord0c589122008-01-26 18:31:16 -0500893
894 /* clear FIS IRQ Cause */
Mark Lorde4006072008-05-14 09:19:30 -0400895 if (IS_GEN_IIE(hpriv))
896 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
Mark Lord0c589122008-01-26 18:31:16 -0500897
Mark Lordf630d562008-01-26 18:31:00 -0500898 mv_set_edma_ptrs(port_mmio, hpriv, pp);
Mark Lord88e675e2008-05-17 13:36:30 -0400899 mv_enable_port_irqs(ap, DONE_IRQ|ERR_IRQ);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400900
Mark Lordf630d562008-01-26 18:31:00 -0500901 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
Brett Russafb0edd2005-10-05 17:08:42 -0400902 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
903 }
Brett Russ31961942005-09-30 01:36:00 -0400904}
905
Mark Lord9b2c4e02008-05-02 02:09:14 -0400906static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
907{
908 void __iomem *port_mmio = mv_ap_base(ap);
909 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
910 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
911 int i;
912
913 /*
914 * Wait for the EDMA engine to finish transactions in progress.
Mark Lordc46938c2008-05-02 14:02:28 -0400915 * No idea what a good "timeout" value might be, but measurements
916 * indicate that it often requires hundreds of microseconds
917 * with two drives in-use. So we use the 15msec value above
918 * as a rough guess at what even more drives might require.
Mark Lord9b2c4e02008-05-02 02:09:14 -0400919 */
920 for (i = 0; i < timeout; ++i) {
921 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
922 if ((edma_stat & empty_idle) == empty_idle)
923 break;
924 udelay(per_loop);
925 }
926 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
927}
928
Brett Russ05b308e2005-10-05 17:08:53 -0400929/**
Mark Lorde12bef52008-03-31 19:33:56 -0400930 * mv_stop_edma_engine - Disable eDMA engine
Mark Lordb5624682008-03-31 19:34:40 -0400931 * @port_mmio: io base address
Brett Russ05b308e2005-10-05 17:08:53 -0400932 *
933 * LOCKING:
934 * Inherited from caller.
935 */
Mark Lordb5624682008-03-31 19:34:40 -0400936static int mv_stop_edma_engine(void __iomem *port_mmio)
Brett Russ31961942005-09-30 01:36:00 -0400937{
Mark Lordb5624682008-03-31 19:34:40 -0400938 int i;
Brett Russ31961942005-09-30 01:36:00 -0400939
Mark Lordb5624682008-03-31 19:34:40 -0400940 /* Disable eDMA. The disable bit auto clears. */
941 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
Jeff Garzik8b260242005-11-12 12:32:50 -0500942
Mark Lordb5624682008-03-31 19:34:40 -0400943 /* Wait for the chip to confirm eDMA is off. */
944 for (i = 10000; i > 0; i--) {
945 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
Jeff Garzik4537deb2007-07-12 14:30:19 -0400946 if (!(reg & EDMA_EN))
Mark Lordb5624682008-03-31 19:34:40 -0400947 return 0;
948 udelay(10);
Brett Russ31961942005-09-30 01:36:00 -0400949 }
Mark Lordb5624682008-03-31 19:34:40 -0400950 return -EIO;
Brett Russ31961942005-09-30 01:36:00 -0400951}
952
Mark Lorde12bef52008-03-31 19:33:56 -0400953static int mv_stop_edma(struct ata_port *ap)
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400954{
Mark Lordb5624682008-03-31 19:34:40 -0400955 void __iomem *port_mmio = mv_ap_base(ap);
956 struct mv_port_priv *pp = ap->private_data;
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400957
Mark Lordb5624682008-03-31 19:34:40 -0400958 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
959 return 0;
960 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
Mark Lord9b2c4e02008-05-02 02:09:14 -0400961 mv_wait_for_edma_empty_idle(ap);
Mark Lordb5624682008-03-31 19:34:40 -0400962 if (mv_stop_edma_engine(port_mmio)) {
963 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
964 return -EIO;
965 }
966 return 0;
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400967}
968
Jeff Garzik8a70f8d2005-10-05 17:19:47 -0400969#ifdef ATA_DEBUG
Brett Russ31961942005-09-30 01:36:00 -0400970static void mv_dump_mem(void __iomem *start, unsigned bytes)
971{
Brett Russ31961942005-09-30 01:36:00 -0400972 int b, w;
973 for (b = 0; b < bytes; ) {
974 DPRINTK("%p: ", start + b);
975 for (w = 0; b < bytes && w < 4; w++) {
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400976 printk("%08x ", readl(start + b));
Brett Russ31961942005-09-30 01:36:00 -0400977 b += sizeof(u32);
978 }
979 printk("\n");
980 }
Brett Russ31961942005-09-30 01:36:00 -0400981}
Jeff Garzik8a70f8d2005-10-05 17:19:47 -0400982#endif
983
Brett Russ31961942005-09-30 01:36:00 -0400984static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
985{
986#ifdef ATA_DEBUG
987 int b, w;
988 u32 dw;
989 for (b = 0; b < bytes; ) {
990 DPRINTK("%02x: ", b);
991 for (w = 0; b < bytes && w < 4; w++) {
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400992 (void) pci_read_config_dword(pdev, b, &dw);
993 printk("%08x ", dw);
Brett Russ31961942005-09-30 01:36:00 -0400994 b += sizeof(u32);
995 }
996 printk("\n");
997 }
998#endif
999}
1000static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1001 struct pci_dev *pdev)
1002{
1003#ifdef ATA_DEBUG
Jeff Garzik8b260242005-11-12 12:32:50 -05001004 void __iomem *hc_base = mv_hc_base(mmio_base,
Brett Russ31961942005-09-30 01:36:00 -04001005 port >> MV_PORT_HC_SHIFT);
1006 void __iomem *port_base;
1007 int start_port, num_ports, p, start_hc, num_hcs, hc;
1008
1009 if (0 > port) {
1010 start_hc = start_port = 0;
1011 num_ports = 8; /* shld be benign for 4 port devs */
1012 num_hcs = 2;
1013 } else {
1014 start_hc = port >> MV_PORT_HC_SHIFT;
1015 start_port = port;
1016 num_ports = num_hcs = 1;
1017 }
Jeff Garzik8b260242005-11-12 12:32:50 -05001018 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
Brett Russ31961942005-09-30 01:36:00 -04001019 num_ports > 1 ? num_ports - 1 : start_port);
1020
1021 if (NULL != pdev) {
1022 DPRINTK("PCI config space regs:\n");
1023 mv_dump_pci_cfg(pdev, 0x68);
1024 }
1025 DPRINTK("PCI regs:\n");
1026 mv_dump_mem(mmio_base+0xc00, 0x3c);
1027 mv_dump_mem(mmio_base+0xd00, 0x34);
1028 mv_dump_mem(mmio_base+0xf00, 0x4);
1029 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1030 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
Dan Alonid220c372006-04-10 23:20:22 -07001031 hc_base = mv_hc_base(mmio_base, hc);
Brett Russ31961942005-09-30 01:36:00 -04001032 DPRINTK("HC regs (HC %i):\n", hc);
1033 mv_dump_mem(hc_base, 0x1c);
1034 }
1035 for (p = start_port; p < start_port + num_ports; p++) {
1036 port_base = mv_port_base(mmio_base, p);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001037 DPRINTK("EDMA regs (port %i):\n", p);
Brett Russ31961942005-09-30 01:36:00 -04001038 mv_dump_mem(port_base, 0x54);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001039 DPRINTK("SATA regs (port %i):\n", p);
Brett Russ31961942005-09-30 01:36:00 -04001040 mv_dump_mem(port_base+0x300, 0x60);
1041 }
1042#endif
1043}
1044
Brett Russ20f733e2005-09-01 18:26:17 -04001045static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1046{
1047 unsigned int ofs;
1048
1049 switch (sc_reg_in) {
1050 case SCR_STATUS:
1051 case SCR_CONTROL:
1052 case SCR_ERROR:
1053 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1054 break;
1055 case SCR_ACTIVE:
1056 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1057 break;
1058 default:
1059 ofs = 0xffffffffU;
1060 break;
1061 }
1062 return ofs;
1063}
1064
Tejun Heo82ef04f2008-07-31 17:02:40 +09001065static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
Brett Russ20f733e2005-09-01 18:26:17 -04001066{
1067 unsigned int ofs = mv_scr_offset(sc_reg_in);
1068
Tejun Heoda3dbb12007-07-16 14:29:40 +09001069 if (ofs != 0xffffffffU) {
Tejun Heo82ef04f2008-07-31 17:02:40 +09001070 *val = readl(mv_ap_base(link->ap) + ofs);
Tejun Heoda3dbb12007-07-16 14:29:40 +09001071 return 0;
1072 } else
1073 return -EINVAL;
Brett Russ20f733e2005-09-01 18:26:17 -04001074}
1075
Tejun Heo82ef04f2008-07-31 17:02:40 +09001076static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
Brett Russ20f733e2005-09-01 18:26:17 -04001077{
1078 unsigned int ofs = mv_scr_offset(sc_reg_in);
1079
Tejun Heoda3dbb12007-07-16 14:29:40 +09001080 if (ofs != 0xffffffffU) {
Tejun Heo82ef04f2008-07-31 17:02:40 +09001081 writelfl(val, mv_ap_base(link->ap) + ofs);
Tejun Heoda3dbb12007-07-16 14:29:40 +09001082 return 0;
1083 } else
1084 return -EINVAL;
Brett Russ20f733e2005-09-01 18:26:17 -04001085}
1086
Mark Lordf2738272008-01-26 18:32:29 -05001087static void mv6_dev_config(struct ata_device *adev)
1088{
1089 /*
Mark Lorde49856d2008-04-16 14:59:07 -04001090 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1091 *
1092 * Gen-II does not support NCQ over a port multiplier
1093 * (no FIS-based switching).
Mark Lordf2738272008-01-26 18:32:29 -05001094 */
Mark Lorde49856d2008-04-16 14:59:07 -04001095 if (adev->flags & ATA_DFLAG_NCQ) {
Mark Lord352fab72008-04-19 14:43:42 -04001096 if (sata_pmp_attached(adev->link->ap)) {
Mark Lorde49856d2008-04-16 14:59:07 -04001097 adev->flags &= ~ATA_DFLAG_NCQ;
Mark Lord352fab72008-04-19 14:43:42 -04001098 ata_dev_printk(adev, KERN_INFO,
1099 "NCQ disabled for command-based switching\n");
Mark Lord352fab72008-04-19 14:43:42 -04001100 }
Mark Lorde49856d2008-04-16 14:59:07 -04001101 }
Mark Lordf2738272008-01-26 18:32:29 -05001102}
1103
Mark Lord3e4a1392008-05-02 02:10:02 -04001104static int mv_qc_defer(struct ata_queued_cmd *qc)
1105{
1106 struct ata_link *link = qc->dev->link;
1107 struct ata_port *ap = link->ap;
1108 struct mv_port_priv *pp = ap->private_data;
1109
1110 /*
Mark Lord29d187b2008-05-02 02:15:37 -04001111 * Don't allow new commands if we're in a delayed EH state
1112 * for NCQ and/or FIS-based switching.
1113 */
1114 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1115 return ATA_DEFER_PORT;
1116 /*
Mark Lord3e4a1392008-05-02 02:10:02 -04001117 * If the port is completely idle, then allow the new qc.
1118 */
1119 if (ap->nr_active_links == 0)
1120 return 0;
1121
Tejun Heo4bdee6c2008-08-13 20:24:16 +09001122 /*
1123 * The port is operating in host queuing mode (EDMA) with NCQ
1124 * enabled, allow multiple NCQ commands. EDMA also allows
1125 * queueing multiple DMA commands but libata core currently
1126 * doesn't allow it.
1127 */
1128 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1129 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol))
1130 return 0;
1131
Mark Lord3e4a1392008-05-02 02:10:02 -04001132 return ATA_DEFER_PORT;
1133}
1134
Mark Lord00f42ea2008-05-02 02:11:45 -04001135static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
Mark Lorde49856d2008-04-16 14:59:07 -04001136{
Mark Lord00f42ea2008-05-02 02:11:45 -04001137 u32 new_fiscfg, old_fiscfg;
1138 u32 new_ltmode, old_ltmode;
1139 u32 new_haltcond, old_haltcond;
1140
1141 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1142 old_ltmode = readl(port_mmio + LTMODE_OFS);
1143 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1144
1145 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1146 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1147 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1148
1149 if (want_fbs) {
1150 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1151 new_ltmode = old_ltmode | LTMODE_BIT8;
Mark Lord4c299ca2008-05-02 02:16:20 -04001152 if (want_ncq)
1153 new_haltcond &= ~EDMA_ERR_DEV;
1154 else
1155 new_fiscfg |= FISCFG_WAIT_DEV_ERR;
Mark Lorde49856d2008-04-16 14:59:07 -04001156 }
Mark Lord00f42ea2008-05-02 02:11:45 -04001157
Mark Lord8e7decd2008-05-02 02:07:51 -04001158 if (new_fiscfg != old_fiscfg)
1159 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
Mark Lorde49856d2008-04-16 14:59:07 -04001160 if (new_ltmode != old_ltmode)
1161 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
Mark Lord00f42ea2008-05-02 02:11:45 -04001162 if (new_haltcond != old_haltcond)
1163 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
Mark Lord0c589122008-01-26 18:31:16 -05001164}
Jeff Garzike4e7b892006-01-31 12:18:41 -05001165
Mark Lorddd2890f2008-05-02 02:10:56 -04001166static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1167{
1168 struct mv_host_priv *hpriv = ap->host->private_data;
1169 u32 old, new;
1170
1171 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1172 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1173 if (want_ncq)
1174 new = old | (1 << 22);
1175 else
1176 new = old & ~(1 << 22);
1177 if (new != old)
1178 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1179}
1180
Mark Lorde12bef52008-03-31 19:33:56 -04001181static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
Jeff Garzike4e7b892006-01-31 12:18:41 -05001182{
1183 u32 cfg;
Mark Lorde12bef52008-03-31 19:33:56 -04001184 struct mv_port_priv *pp = ap->private_data;
1185 struct mv_host_priv *hpriv = ap->host->private_data;
1186 void __iomem *port_mmio = mv_ap_base(ap);
Jeff Garzike4e7b892006-01-31 12:18:41 -05001187
1188 /* set up non-NCQ EDMA configuration */
1189 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
Mark Lord00f42ea2008-05-02 02:11:45 -04001190 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN;
Jeff Garzike4e7b892006-01-31 12:18:41 -05001191
1192 if (IS_GEN_I(hpriv))
1193 cfg |= (1 << 8); /* enab config burst size mask */
1194
Mark Lorddd2890f2008-05-02 02:10:56 -04001195 else if (IS_GEN_II(hpriv)) {
Jeff Garzike4e7b892006-01-31 12:18:41 -05001196 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
Mark Lorddd2890f2008-05-02 02:10:56 -04001197 mv_60x1_errata_sata25(ap, want_ncq);
Jeff Garzike4e7b892006-01-31 12:18:41 -05001198
Mark Lorddd2890f2008-05-02 02:10:56 -04001199 } else if (IS_GEN_IIE(hpriv)) {
Mark Lord00f42ea2008-05-02 02:11:45 -04001200 int want_fbs = sata_pmp_attached(ap);
1201 /*
1202 * Possible future enhancement:
1203 *
1204 * The chip can use FBS with non-NCQ, if we allow it,
1205 * But first we need to have the error handling in place
1206 * for this mode (datasheet section 7.3.15.4.2.3).
1207 * So disallow non-NCQ FBS for now.
1208 */
1209 want_fbs &= want_ncq;
1210
1211 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1212
1213 if (want_fbs) {
1214 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1215 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1216 }
1217
Jeff Garzike728eab2007-02-25 02:53:41 -05001218 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1219 cfg |= (1 << 22); /* enab 4-entry host queue cache */
Mark Lord1f398472008-05-27 17:54:48 -04001220 if (!IS_SOC(hpriv))
Mark Lord616d4a92008-05-02 02:08:32 -04001221 cfg |= (1 << 18); /* enab early completion */
1222 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1223 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
Jeff Garzike4e7b892006-01-31 12:18:41 -05001224 }
1225
Mark Lord72109162008-01-26 18:31:33 -05001226 if (want_ncq) {
1227 cfg |= EDMA_CFG_NCQ;
1228 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1229 } else
1230 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1231
Jeff Garzike4e7b892006-01-31 12:18:41 -05001232 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1233}
1234
Mark Lordda2fa9b2008-01-26 18:32:45 -05001235static void mv_port_free_dma_mem(struct ata_port *ap)
1236{
1237 struct mv_host_priv *hpriv = ap->host->private_data;
1238 struct mv_port_priv *pp = ap->private_data;
Mark Lordeb73d552008-01-29 13:24:00 -05001239 int tag;
Mark Lordda2fa9b2008-01-26 18:32:45 -05001240
1241 if (pp->crqb) {
1242 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1243 pp->crqb = NULL;
1244 }
1245 if (pp->crpb) {
1246 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1247 pp->crpb = NULL;
1248 }
Mark Lordeb73d552008-01-29 13:24:00 -05001249 /*
1250 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1251 * For later hardware, we have one unique sg_tbl per NCQ tag.
1252 */
1253 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1254 if (pp->sg_tbl[tag]) {
1255 if (tag == 0 || !IS_GEN_I(hpriv))
1256 dma_pool_free(hpriv->sg_tbl_pool,
1257 pp->sg_tbl[tag],
1258 pp->sg_tbl_dma[tag]);
1259 pp->sg_tbl[tag] = NULL;
1260 }
Mark Lordda2fa9b2008-01-26 18:32:45 -05001261 }
1262}
1263
Brett Russ05b308e2005-10-05 17:08:53 -04001264/**
1265 * mv_port_start - Port specific init/start routine.
1266 * @ap: ATA channel to manipulate
1267 *
1268 * Allocate and point to DMA memory, init port private memory,
1269 * zero indices.
1270 *
1271 * LOCKING:
1272 * Inherited from caller.
1273 */
Brett Russ31961942005-09-30 01:36:00 -04001274static int mv_port_start(struct ata_port *ap)
1275{
Jeff Garzikcca39742006-08-24 03:19:22 -04001276 struct device *dev = ap->host->dev;
1277 struct mv_host_priv *hpriv = ap->host->private_data;
Brett Russ31961942005-09-30 01:36:00 -04001278 struct mv_port_priv *pp;
James Bottomleydde20202008-02-19 11:36:56 +01001279 int tag;
Brett Russ31961942005-09-30 01:36:00 -04001280
Tejun Heo24dc5f32007-01-20 16:00:28 +09001281 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Jeff Garzik6037d6b2005-11-04 22:08:00 -05001282 if (!pp)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001283 return -ENOMEM;
Mark Lordda2fa9b2008-01-26 18:32:45 -05001284 ap->private_data = pp;
Brett Russ31961942005-09-30 01:36:00 -04001285
Mark Lordda2fa9b2008-01-26 18:32:45 -05001286 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1287 if (!pp->crqb)
1288 return -ENOMEM;
1289 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
Brett Russ31961942005-09-30 01:36:00 -04001290
Mark Lordda2fa9b2008-01-26 18:32:45 -05001291 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1292 if (!pp->crpb)
1293 goto out_port_free_dma_mem;
1294 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
Brett Russ31961942005-09-30 01:36:00 -04001295
Mark Lord3bd0a702008-06-18 12:11:16 -04001296 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1297 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1298 ap->flags |= ATA_FLAG_AN;
Mark Lordeb73d552008-01-29 13:24:00 -05001299 /*
1300 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1301 * For later hardware, we need one unique sg_tbl per NCQ tag.
1302 */
1303 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1304 if (tag == 0 || !IS_GEN_I(hpriv)) {
1305 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1306 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1307 if (!pp->sg_tbl[tag])
1308 goto out_port_free_dma_mem;
1309 } else {
1310 pp->sg_tbl[tag] = pp->sg_tbl[0];
1311 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1312 }
1313 }
Brett Russ31961942005-09-30 01:36:00 -04001314 return 0;
Mark Lordda2fa9b2008-01-26 18:32:45 -05001315
1316out_port_free_dma_mem:
1317 mv_port_free_dma_mem(ap);
1318 return -ENOMEM;
Brett Russ31961942005-09-30 01:36:00 -04001319}
1320
Brett Russ05b308e2005-10-05 17:08:53 -04001321/**
1322 * mv_port_stop - Port specific cleanup/stop routine.
1323 * @ap: ATA channel to manipulate
1324 *
1325 * Stop DMA, cleanup port memory.
1326 *
1327 * LOCKING:
Jeff Garzikcca39742006-08-24 03:19:22 -04001328 * This routine uses the host lock to protect the DMA stop.
Brett Russ05b308e2005-10-05 17:08:53 -04001329 */
Brett Russ31961942005-09-30 01:36:00 -04001330static void mv_port_stop(struct ata_port *ap)
1331{
Mark Lorde12bef52008-03-31 19:33:56 -04001332 mv_stop_edma(ap);
Mark Lord88e675e2008-05-17 13:36:30 -04001333 mv_enable_port_irqs(ap, 0);
Mark Lordda2fa9b2008-01-26 18:32:45 -05001334 mv_port_free_dma_mem(ap);
Brett Russ31961942005-09-30 01:36:00 -04001335}
1336
Brett Russ05b308e2005-10-05 17:08:53 -04001337/**
1338 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1339 * @qc: queued command whose SG list to source from
1340 *
1341 * Populate the SG list and mark the last entry.
1342 *
1343 * LOCKING:
1344 * Inherited from caller.
1345 */
Jeff Garzik6c087722007-10-12 00:16:23 -04001346static void mv_fill_sg(struct ata_queued_cmd *qc)
Brett Russ31961942005-09-30 01:36:00 -04001347{
1348 struct mv_port_priv *pp = qc->ap->private_data;
Jeff Garzik972c26b2005-10-18 22:14:54 -04001349 struct scatterlist *sg;
Jeff Garzik3be6cbd2007-10-18 16:21:18 -04001350 struct mv_sg *mv_sg, *last_sg = NULL;
Tejun Heoff2aeb12007-12-05 16:43:11 +09001351 unsigned int si;
Brett Russ31961942005-09-30 01:36:00 -04001352
Mark Lordeb73d552008-01-29 13:24:00 -05001353 mv_sg = pp->sg_tbl[qc->tag];
Tejun Heoff2aeb12007-12-05 16:43:11 +09001354 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Jeff Garzikd88184f2007-02-26 01:26:06 -05001355 dma_addr_t addr = sg_dma_address(sg);
1356 u32 sg_len = sg_dma_len(sg);
Brett Russ31961942005-09-30 01:36:00 -04001357
Olof Johansson4007b492007-10-02 20:45:27 -05001358 while (sg_len) {
1359 u32 offset = addr & 0xffff;
1360 u32 len = sg_len;
Brett Russ31961942005-09-30 01:36:00 -04001361
Olof Johansson4007b492007-10-02 20:45:27 -05001362 if ((offset + sg_len > 0x10000))
1363 len = 0x10000 - offset;
Jeff Garzik972c26b2005-10-18 22:14:54 -04001364
Olof Johansson4007b492007-10-02 20:45:27 -05001365 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1366 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
Jeff Garzik6c087722007-10-12 00:16:23 -04001367 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
Olof Johansson4007b492007-10-02 20:45:27 -05001368
1369 sg_len -= len;
1370 addr += len;
1371
Jeff Garzik3be6cbd2007-10-18 16:21:18 -04001372 last_sg = mv_sg;
Olof Johansson4007b492007-10-02 20:45:27 -05001373 mv_sg++;
Olof Johansson4007b492007-10-02 20:45:27 -05001374 }
Brett Russ31961942005-09-30 01:36:00 -04001375 }
Jeff Garzik3be6cbd2007-10-18 16:21:18 -04001376
1377 if (likely(last_sg))
1378 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
Brett Russ31961942005-09-30 01:36:00 -04001379}
1380
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001381static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
Brett Russ31961942005-09-30 01:36:00 -04001382{
Mark Lord559eeda2006-05-19 16:40:15 -04001383 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
Brett Russ31961942005-09-30 01:36:00 -04001384 (last ? CRQB_CMD_LAST : 0);
Mark Lord559eeda2006-05-19 16:40:15 -04001385 *cmdw = cpu_to_le16(tmp);
Brett Russ31961942005-09-30 01:36:00 -04001386}
1387
Brett Russ05b308e2005-10-05 17:08:53 -04001388/**
1389 * mv_qc_prep - Host specific command preparation.
1390 * @qc: queued command to prepare
1391 *
1392 * This routine simply redirects to the general purpose routine
1393 * if command is not DMA. Else, it handles prep of the CRQB
1394 * (command request block), does some sanity checking, and calls
1395 * the SG load routine.
1396 *
1397 * LOCKING:
1398 * Inherited from caller.
1399 */
Brett Russ31961942005-09-30 01:36:00 -04001400static void mv_qc_prep(struct ata_queued_cmd *qc)
1401{
1402 struct ata_port *ap = qc->ap;
1403 struct mv_port_priv *pp = ap->private_data;
Mark Lorde1469872006-05-22 19:02:03 -04001404 __le16 *cw;
Brett Russ31961942005-09-30 01:36:00 -04001405 struct ata_taskfile *tf;
1406 u16 flags = 0;
Mark Lorda6432432006-05-19 16:36:36 -04001407 unsigned in_index;
Brett Russ31961942005-09-30 01:36:00 -04001408
Mark Lord138bfdd2008-01-26 18:33:18 -05001409 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1410 (qc->tf.protocol != ATA_PROT_NCQ))
Brett Russ31961942005-09-30 01:36:00 -04001411 return;
Brett Russ20f733e2005-09-01 18:26:17 -04001412
Brett Russ31961942005-09-30 01:36:00 -04001413 /* Fill in command request block
1414 */
Jeff Garzike4e7b892006-01-31 12:18:41 -05001415 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
Brett Russ31961942005-09-30 01:36:00 -04001416 flags |= CRQB_FLAG_READ;
Tejun Heobeec7db2006-02-11 19:11:13 +09001417 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
Brett Russ31961942005-09-30 01:36:00 -04001418 flags |= qc->tag << CRQB_TAG_SHIFT;
Mark Lorde49856d2008-04-16 14:59:07 -04001419 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
Brett Russ31961942005-09-30 01:36:00 -04001420
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001421 /* get current queue index from software */
Mark Lordfcfb1f72008-04-19 15:06:40 -04001422 in_index = pp->req_idx;
Brett Russ31961942005-09-30 01:36:00 -04001423
Mark Lorda6432432006-05-19 16:36:36 -04001424 pp->crqb[in_index].sg_addr =
Mark Lordeb73d552008-01-29 13:24:00 -05001425 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
Mark Lorda6432432006-05-19 16:36:36 -04001426 pp->crqb[in_index].sg_addr_hi =
Mark Lordeb73d552008-01-29 13:24:00 -05001427 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
Mark Lorda6432432006-05-19 16:36:36 -04001428 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1429
1430 cw = &pp->crqb[in_index].ata_cmd[0];
Brett Russ31961942005-09-30 01:36:00 -04001431 tf = &qc->tf;
1432
1433 /* Sadly, the CRQB cannot accomodate all registers--there are
1434 * only 11 bytes...so we must pick and choose required
1435 * registers based on the command. So, we drop feature and
1436 * hob_feature for [RW] DMA commands, but they are needed for
Mark Lordcd12e1f2009-01-19 18:06:28 -05001437 * NCQ. NCQ will drop hob_nsect, which is not needed there
1438 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
Brett Russ31961942005-09-30 01:36:00 -04001439 */
1440 switch (tf->command) {
1441 case ATA_CMD_READ:
1442 case ATA_CMD_READ_EXT:
1443 case ATA_CMD_WRITE:
1444 case ATA_CMD_WRITE_EXT:
Jens Axboec15d85c2006-02-15 15:59:25 +01001445 case ATA_CMD_WRITE_FUA_EXT:
Brett Russ31961942005-09-30 01:36:00 -04001446 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1447 break;
Brett Russ31961942005-09-30 01:36:00 -04001448 case ATA_CMD_FPDMA_READ:
1449 case ATA_CMD_FPDMA_WRITE:
Jeff Garzik8b260242005-11-12 12:32:50 -05001450 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
Brett Russ31961942005-09-30 01:36:00 -04001451 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1452 break;
Brett Russ31961942005-09-30 01:36:00 -04001453 default:
1454 /* The only other commands EDMA supports in non-queued and
1455 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1456 * of which are defined/used by Linux. If we get here, this
1457 * driver needs work.
1458 *
1459 * FIXME: modify libata to give qc_prep a return value and
1460 * return error here.
1461 */
1462 BUG_ON(tf->command);
1463 break;
1464 }
1465 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1466 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1467 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1468 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1469 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1470 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1471 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1472 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1473 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1474
Jeff Garzike4e7b892006-01-31 12:18:41 -05001475 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
Brett Russ31961942005-09-30 01:36:00 -04001476 return;
Jeff Garzike4e7b892006-01-31 12:18:41 -05001477 mv_fill_sg(qc);
1478}
1479
1480/**
1481 * mv_qc_prep_iie - Host specific command preparation.
1482 * @qc: queued command to prepare
1483 *
1484 * This routine simply redirects to the general purpose routine
1485 * if command is not DMA. Else, it handles prep of the CRQB
1486 * (command request block), does some sanity checking, and calls
1487 * the SG load routine.
1488 *
1489 * LOCKING:
1490 * Inherited from caller.
1491 */
1492static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1493{
1494 struct ata_port *ap = qc->ap;
1495 struct mv_port_priv *pp = ap->private_data;
1496 struct mv_crqb_iie *crqb;
1497 struct ata_taskfile *tf;
Mark Lorda6432432006-05-19 16:36:36 -04001498 unsigned in_index;
Jeff Garzike4e7b892006-01-31 12:18:41 -05001499 u32 flags = 0;
1500
Mark Lord138bfdd2008-01-26 18:33:18 -05001501 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1502 (qc->tf.protocol != ATA_PROT_NCQ))
Jeff Garzike4e7b892006-01-31 12:18:41 -05001503 return;
1504
Mark Lorde12bef52008-03-31 19:33:56 -04001505 /* Fill in Gen IIE command request block */
Jeff Garzike4e7b892006-01-31 12:18:41 -05001506 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1507 flags |= CRQB_FLAG_READ;
1508
Tejun Heobeec7db2006-02-11 19:11:13 +09001509 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
Jeff Garzike4e7b892006-01-31 12:18:41 -05001510 flags |= qc->tag << CRQB_TAG_SHIFT;
Mark Lord8c0aeb42008-01-26 18:31:48 -05001511 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
Mark Lorde49856d2008-04-16 14:59:07 -04001512 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
Jeff Garzike4e7b892006-01-31 12:18:41 -05001513
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001514 /* get current queue index from software */
Mark Lordfcfb1f72008-04-19 15:06:40 -04001515 in_index = pp->req_idx;
Mark Lorda6432432006-05-19 16:36:36 -04001516
1517 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
Mark Lordeb73d552008-01-29 13:24:00 -05001518 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1519 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
Jeff Garzike4e7b892006-01-31 12:18:41 -05001520 crqb->flags = cpu_to_le32(flags);
1521
1522 tf = &qc->tf;
1523 crqb->ata_cmd[0] = cpu_to_le32(
1524 (tf->command << 16) |
1525 (tf->feature << 24)
1526 );
1527 crqb->ata_cmd[1] = cpu_to_le32(
1528 (tf->lbal << 0) |
1529 (tf->lbam << 8) |
1530 (tf->lbah << 16) |
1531 (tf->device << 24)
1532 );
1533 crqb->ata_cmd[2] = cpu_to_le32(
1534 (tf->hob_lbal << 0) |
1535 (tf->hob_lbam << 8) |
1536 (tf->hob_lbah << 16) |
1537 (tf->hob_feature << 24)
1538 );
1539 crqb->ata_cmd[3] = cpu_to_le32(
1540 (tf->nsect << 0) |
1541 (tf->hob_nsect << 8)
1542 );
1543
1544 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1545 return;
Brett Russ31961942005-09-30 01:36:00 -04001546 mv_fill_sg(qc);
1547}
1548
Brett Russ05b308e2005-10-05 17:08:53 -04001549/**
1550 * mv_qc_issue - Initiate a command to the host
1551 * @qc: queued command to start
1552 *
1553 * This routine simply redirects to the general purpose routine
1554 * if command is not DMA. Else, it sanity checks our local
1555 * caches of the request producer/consumer indices then enables
1556 * DMA and bumps the request producer index.
1557 *
1558 * LOCKING:
1559 * Inherited from caller.
1560 */
Tejun Heo9a3d9eb2006-01-23 13:09:36 +09001561static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
Brett Russ31961942005-09-30 01:36:00 -04001562{
Jeff Garzikc5d3e452007-07-11 18:30:50 -04001563 struct ata_port *ap = qc->ap;
1564 void __iomem *port_mmio = mv_ap_base(ap);
1565 struct mv_port_priv *pp = ap->private_data;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001566 u32 in_index;
Brett Russ31961942005-09-30 01:36:00 -04001567
Mark Lord138bfdd2008-01-26 18:33:18 -05001568 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1569 (qc->tf.protocol != ATA_PROT_NCQ)) {
Mark Lordc6112bd2008-06-18 12:13:02 -04001570 static int limit_warnings = 10;
1571 /*
1572 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
1573 *
1574 * Someday, we might implement special polling workarounds
1575 * for these, but it all seems rather unnecessary since we
1576 * normally use only DMA for commands which transfer more
1577 * than a single block of data.
1578 *
1579 * Much of the time, this could just work regardless.
1580 * So for now, just log the incident, and allow the attempt.
1581 */
Mark Lordc7843e82008-06-18 21:57:42 -04001582 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
Mark Lordc6112bd2008-06-18 12:13:02 -04001583 --limit_warnings;
1584 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
1585 ": attempting PIO w/multiple DRQ: "
1586 "this may fail due to h/w errata\n");
1587 }
Mark Lord17c5aab2008-04-16 14:56:51 -04001588 /*
1589 * We're about to send a non-EDMA capable command to the
Brett Russ31961942005-09-30 01:36:00 -04001590 * port. Turn off EDMA so there won't be problems accessing
1591 * shadow block, etc registers.
1592 */
Mark Lordb5624682008-03-31 19:34:40 -04001593 mv_stop_edma(ap);
Mark Lord88e675e2008-05-17 13:36:30 -04001594 mv_enable_port_irqs(ap, ERR_IRQ);
Mark Lorde49856d2008-04-16 14:59:07 -04001595 mv_pmp_select(ap, qc->dev->link->pmp);
Tejun Heo9363c382008-04-07 22:47:16 +09001596 return ata_sff_qc_issue(qc);
Brett Russ31961942005-09-30 01:36:00 -04001597 }
1598
Mark Lord72109162008-01-26 18:31:33 -05001599 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001600
Mark Lordfcfb1f72008-04-19 15:06:40 -04001601 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1602 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
Brett Russ31961942005-09-30 01:36:00 -04001603
1604 /* and write the request in pointer to kick the EDMA to life */
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001605 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1606 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
Brett Russ31961942005-09-30 01:36:00 -04001607
1608 return 0;
1609}
1610
Mark Lord8f767f82008-04-19 14:53:07 -04001611static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1612{
1613 struct mv_port_priv *pp = ap->private_data;
1614 struct ata_queued_cmd *qc;
1615
1616 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1617 return NULL;
1618 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1619 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1620 qc = NULL;
1621 return qc;
1622}
1623
Mark Lord29d187b2008-05-02 02:15:37 -04001624static void mv_pmp_error_handler(struct ata_port *ap)
1625{
1626 unsigned int pmp, pmp_map;
1627 struct mv_port_priv *pp = ap->private_data;
1628
1629 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1630 /*
1631 * Perform NCQ error analysis on failed PMPs
1632 * before we freeze the port entirely.
1633 *
1634 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1635 */
1636 pmp_map = pp->delayed_eh_pmp_map;
1637 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1638 for (pmp = 0; pmp_map != 0; pmp++) {
1639 unsigned int this_pmp = (1 << pmp);
1640 if (pmp_map & this_pmp) {
1641 struct ata_link *link = &ap->pmp_link[pmp];
1642 pmp_map &= ~this_pmp;
1643 ata_eh_analyze_ncq_error(link);
1644 }
1645 }
1646 ata_port_freeze(ap);
1647 }
1648 sata_pmp_error_handler(ap);
1649}
1650
Mark Lord4c299ca2008-05-02 02:16:20 -04001651static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1652{
1653 void __iomem *port_mmio = mv_ap_base(ap);
1654
1655 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1656}
1657
Mark Lord4c299ca2008-05-02 02:16:20 -04001658static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1659{
1660 struct ata_eh_info *ehi;
1661 unsigned int pmp;
1662
1663 /*
1664 * Initialize EH info for PMPs which saw device errors
1665 */
1666 ehi = &ap->link.eh_info;
1667 for (pmp = 0; pmp_map != 0; pmp++) {
1668 unsigned int this_pmp = (1 << pmp);
1669 if (pmp_map & this_pmp) {
1670 struct ata_link *link = &ap->pmp_link[pmp];
1671
1672 pmp_map &= ~this_pmp;
1673 ehi = &link->eh_info;
1674 ata_ehi_clear_desc(ehi);
1675 ata_ehi_push_desc(ehi, "dev err");
1676 ehi->err_mask |= AC_ERR_DEV;
1677 ehi->action |= ATA_EH_RESET;
1678 ata_link_abort(link);
1679 }
1680 }
1681}
1682
Mark Lord06aaca32008-05-19 09:01:24 -04001683static int mv_req_q_empty(struct ata_port *ap)
1684{
1685 void __iomem *port_mmio = mv_ap_base(ap);
1686 u32 in_ptr, out_ptr;
1687
1688 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
1689 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1690 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1691 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1692 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
1693}
1694
Mark Lord4c299ca2008-05-02 02:16:20 -04001695static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1696{
1697 struct mv_port_priv *pp = ap->private_data;
1698 int failed_links;
1699 unsigned int old_map, new_map;
1700
1701 /*
1702 * Device error during FBS+NCQ operation:
1703 *
1704 * Set a port flag to prevent further I/O being enqueued.
1705 * Leave the EDMA running to drain outstanding commands from this port.
1706 * Perform the post-mortem/EH only when all responses are complete.
1707 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1708 */
1709 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1710 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1711 pp->delayed_eh_pmp_map = 0;
1712 }
1713 old_map = pp->delayed_eh_pmp_map;
1714 new_map = old_map | mv_get_err_pmp_map(ap);
1715
1716 if (old_map != new_map) {
1717 pp->delayed_eh_pmp_map = new_map;
1718 mv_pmp_eh_prep(ap, new_map & ~old_map);
1719 }
Mark Lordc46938c2008-05-02 14:02:28 -04001720 failed_links = hweight16(new_map);
Mark Lord4c299ca2008-05-02 02:16:20 -04001721
1722 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1723 "failed_links=%d nr_active_links=%d\n",
1724 __func__, pp->delayed_eh_pmp_map,
1725 ap->qc_active, failed_links,
1726 ap->nr_active_links);
1727
Mark Lord06aaca32008-05-19 09:01:24 -04001728 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
Mark Lord4c299ca2008-05-02 02:16:20 -04001729 mv_process_crpb_entries(ap, pp);
1730 mv_stop_edma(ap);
1731 mv_eh_freeze(ap);
1732 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1733 return 1; /* handled */
1734 }
1735 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1736 return 1; /* handled */
1737}
1738
1739static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1740{
1741 /*
1742 * Possible future enhancement:
1743 *
1744 * FBS+non-NCQ operation is not yet implemented.
1745 * See related notes in mv_edma_cfg().
1746 *
1747 * Device error during FBS+non-NCQ operation:
1748 *
1749 * We need to snapshot the shadow registers for each failed command.
1750 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1751 */
1752 return 0; /* not handled */
1753}
1754
1755static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
1756{
1757 struct mv_port_priv *pp = ap->private_data;
1758
1759 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1760 return 0; /* EDMA was not active: not handled */
1761 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
1762 return 0; /* FBS was not active: not handled */
1763
1764 if (!(edma_err_cause & EDMA_ERR_DEV))
1765 return 0; /* non DEV error: not handled */
1766 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
1767 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
1768 return 0; /* other problems: not handled */
1769
1770 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1771 /*
1772 * EDMA should NOT have self-disabled for this case.
1773 * If it did, then something is wrong elsewhere,
1774 * and we cannot handle it here.
1775 */
1776 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1777 ata_port_printk(ap, KERN_WARNING,
1778 "%s: err_cause=0x%x pp_flags=0x%x\n",
1779 __func__, edma_err_cause, pp->pp_flags);
1780 return 0; /* not handled */
1781 }
1782 return mv_handle_fbs_ncq_dev_err(ap);
1783 } else {
1784 /*
1785 * EDMA should have self-disabled for this case.
1786 * If it did not, then something is wrong elsewhere,
1787 * and we cannot handle it here.
1788 */
1789 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
1790 ata_port_printk(ap, KERN_WARNING,
1791 "%s: err_cause=0x%x pp_flags=0x%x\n",
1792 __func__, edma_err_cause, pp->pp_flags);
1793 return 0; /* not handled */
1794 }
1795 return mv_handle_fbs_non_ncq_dev_err(ap);
1796 }
1797 return 0; /* not handled */
1798}
1799
Mark Lorda9010322008-05-02 02:14:02 -04001800static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
Mark Lord8f767f82008-04-19 14:53:07 -04001801{
Mark Lord8f767f82008-04-19 14:53:07 -04001802 struct ata_eh_info *ehi = &ap->link.eh_info;
Mark Lorda9010322008-05-02 02:14:02 -04001803 char *when = "idle";
Mark Lord8f767f82008-04-19 14:53:07 -04001804
Mark Lord8f767f82008-04-19 14:53:07 -04001805 ata_ehi_clear_desc(ehi);
Mark Lorda9010322008-05-02 02:14:02 -04001806 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
1807 when = "disabled";
1808 } else if (edma_was_enabled) {
1809 when = "EDMA enabled";
Mark Lord8f767f82008-04-19 14:53:07 -04001810 } else {
1811 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1812 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
Mark Lorda9010322008-05-02 02:14:02 -04001813 when = "polling";
Mark Lord8f767f82008-04-19 14:53:07 -04001814 }
Mark Lorda9010322008-05-02 02:14:02 -04001815 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
Mark Lord8f767f82008-04-19 14:53:07 -04001816 ehi->err_mask |= AC_ERR_OTHER;
1817 ehi->action |= ATA_EH_RESET;
1818 ata_port_freeze(ap);
1819}
1820
Brett Russ05b308e2005-10-05 17:08:53 -04001821/**
Brett Russ05b308e2005-10-05 17:08:53 -04001822 * mv_err_intr - Handle error interrupts on the port
1823 * @ap: ATA channel to manipulate
1824 *
Mark Lord8d073792008-04-19 15:07:49 -04001825 * Most cases require a full reset of the chip's state machine,
1826 * which also performs a COMRESET.
1827 * Also, if the port disabled DMA, update our cached copy to match.
Brett Russ05b308e2005-10-05 17:08:53 -04001828 *
1829 * LOCKING:
1830 * Inherited from caller.
1831 */
Mark Lord37b90462008-05-02 02:12:34 -04001832static void mv_err_intr(struct ata_port *ap)
Brett Russ20f733e2005-09-01 18:26:17 -04001833{
Brett Russ31961942005-09-30 01:36:00 -04001834 void __iomem *port_mmio = mv_ap_base(ap);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001835 u32 edma_err_cause, eh_freeze_mask, serr = 0;
Mark Lorde4006072008-05-14 09:19:30 -04001836 u32 fis_cause = 0;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001837 struct mv_port_priv *pp = ap->private_data;
1838 struct mv_host_priv *hpriv = ap->host->private_data;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001839 unsigned int action = 0, err_mask = 0;
Tejun Heo9af5c9c2007-08-06 18:36:22 +09001840 struct ata_eh_info *ehi = &ap->link.eh_info;
Mark Lord37b90462008-05-02 02:12:34 -04001841 struct ata_queued_cmd *qc;
1842 int abort = 0;
Brett Russ20f733e2005-09-01 18:26:17 -04001843
Mark Lord8d073792008-04-19 15:07:49 -04001844 /*
Mark Lord37b90462008-05-02 02:12:34 -04001845 * Read and clear the SError and err_cause bits.
Mark Lorde4006072008-05-14 09:19:30 -04001846 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
1847 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
Mark Lord8d073792008-04-19 15:07:49 -04001848 */
Mark Lord37b90462008-05-02 02:12:34 -04001849 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1850 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1851
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001852 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
Mark Lorde4006072008-05-14 09:19:30 -04001853 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1854 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1855 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1856 }
Mark Lord8d073792008-04-19 15:07:49 -04001857 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001858
Mark Lord4c299ca2008-05-02 02:16:20 -04001859 if (edma_err_cause & EDMA_ERR_DEV) {
1860 /*
1861 * Device errors during FIS-based switching operation
1862 * require special handling.
1863 */
1864 if (mv_handle_dev_err(ap, edma_err_cause))
1865 return;
1866 }
1867
Mark Lord37b90462008-05-02 02:12:34 -04001868 qc = mv_get_active_qc(ap);
1869 ata_ehi_clear_desc(ehi);
1870 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1871 edma_err_cause, pp->pp_flags);
Mark Lorde4006072008-05-14 09:19:30 -04001872
Mark Lordc443c502008-05-14 09:24:39 -04001873 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
Mark Lorde4006072008-05-14 09:19:30 -04001874 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
Mark Lordc443c502008-05-14 09:24:39 -04001875 if (fis_cause & SATA_FIS_IRQ_AN) {
1876 u32 ec = edma_err_cause &
1877 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
1878 sata_async_notification(ap);
1879 if (!ec)
1880 return; /* Just an AN; no need for the nukes */
1881 ata_ehi_push_desc(ehi, "SDB notify");
1882 }
1883 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001884 /*
Mark Lord352fab72008-04-19 14:43:42 -04001885 * All generations share these EDMA error cause bits:
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001886 */
Mark Lord37b90462008-05-02 02:12:34 -04001887 if (edma_err_cause & EDMA_ERR_DEV) {
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001888 err_mask |= AC_ERR_DEV;
Mark Lord37b90462008-05-02 02:12:34 -04001889 action |= ATA_EH_RESET;
1890 ata_ehi_push_desc(ehi, "dev error");
1891 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001892 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
Jeff Garzik6c1153e2007-07-13 15:20:15 -04001893 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001894 EDMA_ERR_INTRL_PAR)) {
1895 err_mask |= AC_ERR_ATA_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09001896 action |= ATA_EH_RESET;
Tejun Heob64bbc32007-07-16 14:29:39 +09001897 ata_ehi_push_desc(ehi, "parity error");
Brett Russafb0edd2005-10-05 17:08:42 -04001898 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001899 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1900 ata_ehi_hotplugged(ehi);
1901 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
Tejun Heob64bbc32007-07-16 14:29:39 +09001902 "dev disconnect" : "dev connect");
Tejun Heocf480622008-01-24 00:05:14 +09001903 action |= ATA_EH_RESET;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001904 }
1905
Mark Lord352fab72008-04-19 14:43:42 -04001906 /*
1907 * Gen-I has a different SELF_DIS bit,
1908 * different FREEZE bits, and no SERR bit:
1909 */
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04001910 if (IS_GEN_I(hpriv)) {
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001911 eh_freeze_mask = EDMA_EH_FREEZE_5;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001912 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001913 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
Tejun Heob64bbc32007-07-16 14:29:39 +09001914 ata_ehi_push_desc(ehi, "EDMA self-disable");
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001915 }
1916 } else {
1917 eh_freeze_mask = EDMA_EH_FREEZE;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001918 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001919 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
Tejun Heob64bbc32007-07-16 14:29:39 +09001920 ata_ehi_push_desc(ehi, "EDMA self-disable");
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001921 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001922 if (edma_err_cause & EDMA_ERR_SERR) {
Mark Lord8d073792008-04-19 15:07:49 -04001923 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1924 err_mask |= AC_ERR_ATA_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09001925 action |= ATA_EH_RESET;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001926 }
1927 }
Brett Russ20f733e2005-09-01 18:26:17 -04001928
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001929 if (!err_mask) {
1930 err_mask = AC_ERR_OTHER;
Tejun Heocf480622008-01-24 00:05:14 +09001931 action |= ATA_EH_RESET;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001932 }
1933
1934 ehi->serror |= serr;
1935 ehi->action |= action;
1936
1937 if (qc)
1938 qc->err_mask |= err_mask;
1939 else
1940 ehi->err_mask |= err_mask;
1941
Mark Lord37b90462008-05-02 02:12:34 -04001942 if (err_mask == AC_ERR_DEV) {
1943 /*
1944 * Cannot do ata_port_freeze() here,
1945 * because it would kill PIO access,
1946 * which is needed for further diagnosis.
1947 */
1948 mv_eh_freeze(ap);
1949 abort = 1;
1950 } else if (edma_err_cause & eh_freeze_mask) {
1951 /*
1952 * Note to self: ata_port_freeze() calls ata_port_abort()
1953 */
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001954 ata_port_freeze(ap);
Mark Lord37b90462008-05-02 02:12:34 -04001955 } else {
1956 abort = 1;
1957 }
1958
1959 if (abort) {
1960 if (qc)
1961 ata_link_abort(qc->dev->link);
1962 else
1963 ata_port_abort(ap);
1964 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001965}
1966
Mark Lordfcfb1f72008-04-19 15:06:40 -04001967static void mv_process_crpb_response(struct ata_port *ap,
1968 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1969{
1970 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1971
1972 if (qc) {
1973 u8 ata_status;
1974 u16 edma_status = le16_to_cpu(response->flags);
1975 /*
1976 * edma_status from a response queue entry:
1977 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1978 * MSB is saved ATA status from command completion.
1979 */
1980 if (!ncq_enabled) {
1981 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1982 if (err_cause) {
1983 /*
1984 * Error will be seen/handled by mv_err_intr().
1985 * So do nothing at all here.
1986 */
1987 return;
1988 }
1989 }
1990 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
Mark Lord37b90462008-05-02 02:12:34 -04001991 if (!ac_err_mask(ata_status))
1992 ata_qc_complete(qc);
1993 /* else: leave it for mv_err_intr() */
Mark Lordfcfb1f72008-04-19 15:06:40 -04001994 } else {
1995 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1996 __func__, tag);
1997 }
1998}
1999
2000static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002001{
2002 void __iomem *port_mmio = mv_ap_base(ap);
2003 struct mv_host_priv *hpriv = ap->host->private_data;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002004 u32 in_index;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002005 bool work_done = false;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002006 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002007
Mark Lordfcfb1f72008-04-19 15:06:40 -04002008 /* Get the hardware queue position index */
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002009 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2010 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2011
Mark Lordfcfb1f72008-04-19 15:06:40 -04002012 /* Process new responses from since the last time we looked */
2013 while (in_index != pp->resp_idx) {
Jeff Garzik6c1153e2007-07-13 15:20:15 -04002014 unsigned int tag;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002015 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002016
Mark Lordfcfb1f72008-04-19 15:06:40 -04002017 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002018
Mark Lordfcfb1f72008-04-19 15:06:40 -04002019 if (IS_GEN_I(hpriv)) {
2020 /* 50xx: no NCQ, only one command active at a time */
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002021 tag = ap->link.active_tag;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002022 } else {
2023 /* Gen II/IIE: get command tag from CRPB entry */
2024 tag = le16_to_cpu(response->id) & 0x1f;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002025 }
Mark Lordfcfb1f72008-04-19 15:06:40 -04002026 mv_process_crpb_response(ap, response, tag, ncq_enabled);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002027 work_done = true;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002028 }
2029
Mark Lord352fab72008-04-19 14:43:42 -04002030 /* Update the software queue position index in hardware */
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002031 if (work_done)
2032 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
Mark Lordfcfb1f72008-04-19 15:06:40 -04002033 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002034 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
Brett Russ20f733e2005-09-01 18:26:17 -04002035}
2036
Mark Lorda9010322008-05-02 02:14:02 -04002037static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2038{
2039 struct mv_port_priv *pp;
2040 int edma_was_enabled;
2041
2042 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2043 mv_unexpected_intr(ap, 0);
2044 return;
2045 }
2046 /*
2047 * Grab a snapshot of the EDMA_EN flag setting,
2048 * so that we have a consistent view for this port,
2049 * even if something we call of our routines changes it.
2050 */
2051 pp = ap->private_data;
2052 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2053 /*
2054 * Process completed CRPB response(s) before other events.
2055 */
2056 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2057 mv_process_crpb_entries(ap, pp);
Mark Lord4c299ca2008-05-02 02:16:20 -04002058 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2059 mv_handle_fbs_ncq_dev_err(ap);
Mark Lorda9010322008-05-02 02:14:02 -04002060 }
2061 /*
2062 * Handle chip-reported errors, or continue on to handle PIO.
2063 */
2064 if (unlikely(port_cause & ERR_IRQ)) {
2065 mv_err_intr(ap);
2066 } else if (!edma_was_enabled) {
2067 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2068 if (qc)
2069 ata_sff_host_intr(ap, qc);
2070 else
2071 mv_unexpected_intr(ap, edma_was_enabled);
2072 }
2073}
2074
Brett Russ05b308e2005-10-05 17:08:53 -04002075/**
2076 * mv_host_intr - Handle all interrupts on the given host controller
Jeff Garzikcca39742006-08-24 03:19:22 -04002077 * @host: host specific structure
Mark Lord7368f912008-04-25 11:24:24 -04002078 * @main_irq_cause: Main interrupt cause register for the chip.
Brett Russ05b308e2005-10-05 17:08:53 -04002079 *
2080 * LOCKING:
2081 * Inherited from caller.
2082 */
Mark Lord7368f912008-04-25 11:24:24 -04002083static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
Brett Russ20f733e2005-09-01 18:26:17 -04002084{
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05002085 struct mv_host_priv *hpriv = host->private_data;
Mark Lordeabd5eb2008-05-02 02:13:27 -04002086 void __iomem *mmio = hpriv->base, *hc_mmio;
Mark Lorda3718c12008-04-19 15:07:18 -04002087 unsigned int handled = 0, port;
Brett Russ20f733e2005-09-01 18:26:17 -04002088
Mark Lorda3718c12008-04-19 15:07:18 -04002089 for (port = 0; port < hpriv->n_ports; port++) {
Jeff Garzikcca39742006-08-24 03:19:22 -04002090 struct ata_port *ap = host->ports[port];
Mark Lordeabd5eb2008-05-02 02:13:27 -04002091 unsigned int p, shift, hardport, port_cause;
2092
Mark Lorda3718c12008-04-19 15:07:18 -04002093 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
Mark Lorda3718c12008-04-19 15:07:18 -04002094 /*
Mark Lordeabd5eb2008-05-02 02:13:27 -04002095 * Each hc within the host has its own hc_irq_cause register,
2096 * where the interrupting ports bits get ack'd.
Mark Lorda3718c12008-04-19 15:07:18 -04002097 */
Mark Lordeabd5eb2008-05-02 02:13:27 -04002098 if (hardport == 0) { /* first port on this hc ? */
2099 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2100 u32 port_mask, ack_irqs;
2101 /*
2102 * Skip this entire hc if nothing pending for any ports
2103 */
2104 if (!hc_cause) {
2105 port += MV_PORTS_PER_HC - 1;
2106 continue;
2107 }
2108 /*
2109 * We don't need/want to read the hc_irq_cause register,
2110 * because doing so hurts performance, and
2111 * main_irq_cause already gives us everything we need.
2112 *
2113 * But we do have to *write* to the hc_irq_cause to ack
2114 * the ports that we are handling this time through.
2115 *
2116 * This requires that we create a bitmap for those
2117 * ports which interrupted us, and use that bitmap
2118 * to ack (only) those ports via hc_irq_cause.
2119 */
2120 ack_irqs = 0;
2121 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2122 if ((port + p) >= hpriv->n_ports)
2123 break;
2124 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2125 if (hc_cause & port_mask)
2126 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2127 }
Mark Lorda3718c12008-04-19 15:07:18 -04002128 hc_mmio = mv_hc_base_from_port(mmio, port);
Mark Lordeabd5eb2008-05-02 02:13:27 -04002129 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
Mark Lorda3718c12008-04-19 15:07:18 -04002130 handled = 1;
2131 }
Mark Lorda9010322008-05-02 02:14:02 -04002132 /*
2133 * Handle interrupts signalled for this port:
2134 */
Mark Lordeabd5eb2008-05-02 02:13:27 -04002135 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
Mark Lorda9010322008-05-02 02:14:02 -04002136 if (port_cause)
2137 mv_port_intr(ap, port_cause);
Brett Russ20f733e2005-09-01 18:26:17 -04002138 }
Mark Lorda3718c12008-04-19 15:07:18 -04002139 return handled;
Brett Russ20f733e2005-09-01 18:26:17 -04002140}
2141
Mark Lorda3718c12008-04-19 15:07:18 -04002142static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002143{
Mark Lord02a121d2007-12-01 13:07:22 -05002144 struct mv_host_priv *hpriv = host->private_data;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002145 struct ata_port *ap;
2146 struct ata_queued_cmd *qc;
2147 struct ata_eh_info *ehi;
2148 unsigned int i, err_mask, printed = 0;
2149 u32 err_cause;
2150
Mark Lord02a121d2007-12-01 13:07:22 -05002151 err_cause = readl(mmio + hpriv->irq_cause_ofs);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002152
2153 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2154 err_cause);
2155
2156 DPRINTK("All regs @ PCI error\n");
2157 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2158
Mark Lord02a121d2007-12-01 13:07:22 -05002159 writelfl(0, mmio + hpriv->irq_cause_ofs);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002160
2161 for (i = 0; i < host->n_ports; i++) {
2162 ap = host->ports[i];
Tejun Heo936fd732007-08-06 18:36:23 +09002163 if (!ata_link_offline(&ap->link)) {
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002164 ehi = &ap->link.eh_info;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002165 ata_ehi_clear_desc(ehi);
2166 if (!printed++)
2167 ata_ehi_push_desc(ehi,
2168 "PCI err cause 0x%08x", err_cause);
2169 err_mask = AC_ERR_HOST_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002170 ehi->action = ATA_EH_RESET;
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002171 qc = ata_qc_from_tag(ap, ap->link.active_tag);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002172 if (qc)
2173 qc->err_mask |= err_mask;
2174 else
2175 ehi->err_mask |= err_mask;
2176
2177 ata_port_freeze(ap);
2178 }
2179 }
Mark Lorda3718c12008-04-19 15:07:18 -04002180 return 1; /* handled */
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002181}
2182
Brett Russ05b308e2005-10-05 17:08:53 -04002183/**
Jeff Garzikc5d3e452007-07-11 18:30:50 -04002184 * mv_interrupt - Main interrupt event handler
Brett Russ05b308e2005-10-05 17:08:53 -04002185 * @irq: unused
2186 * @dev_instance: private data; in this case the host structure
Brett Russ05b308e2005-10-05 17:08:53 -04002187 *
2188 * Read the read only register to determine if any host
2189 * controllers have pending interrupts. If so, call lower level
2190 * routine to handle. Also check for PCI errors which are only
2191 * reported here.
2192 *
Jeff Garzik8b260242005-11-12 12:32:50 -05002193 * LOCKING:
Jeff Garzikcca39742006-08-24 03:19:22 -04002194 * This routine holds the host lock while processing pending
Brett Russ05b308e2005-10-05 17:08:53 -04002195 * interrupts.
2196 */
David Howells7d12e782006-10-05 14:55:46 +01002197static irqreturn_t mv_interrupt(int irq, void *dev_instance)
Brett Russ20f733e2005-09-01 18:26:17 -04002198{
Jeff Garzikcca39742006-08-24 03:19:22 -04002199 struct ata_host *host = dev_instance;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05002200 struct mv_host_priv *hpriv = host->private_data;
Mark Lorda3718c12008-04-19 15:07:18 -04002201 unsigned int handled = 0;
Mark Lord96e2c4872008-05-17 13:38:00 -04002202 u32 main_irq_cause, pending_irqs;
Brett Russ20f733e2005-09-01 18:26:17 -04002203
Mark Lord646a4da2008-01-26 18:30:37 -05002204 spin_lock(&host->lock);
Mark Lord7368f912008-04-25 11:24:24 -04002205 main_irq_cause = readl(hpriv->main_irq_cause_addr);
Mark Lord96e2c4872008-05-17 13:38:00 -04002206 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
Mark Lord352fab72008-04-19 14:43:42 -04002207 /*
2208 * Deal with cases where we either have nothing pending, or have read
2209 * a bogus register value which can indicate HW removal or PCI fault.
Brett Russ20f733e2005-09-01 18:26:17 -04002210 */
Mark Lorda44253d2008-05-17 13:37:07 -04002211 if (pending_irqs && main_irq_cause != 0xffffffffU) {
Mark Lord1f398472008-05-27 17:54:48 -04002212 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
Mark Lorda3718c12008-04-19 15:07:18 -04002213 handled = mv_pci_error(host, hpriv->base);
2214 else
Mark Lorda44253d2008-05-17 13:37:07 -04002215 handled = mv_host_intr(host, pending_irqs);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002216 }
Jeff Garzikcca39742006-08-24 03:19:22 -04002217 spin_unlock(&host->lock);
Brett Russ20f733e2005-09-01 18:26:17 -04002218 return IRQ_RETVAL(handled);
2219}
2220
Jeff Garzikc9d39132005-11-13 17:47:51 -05002221static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2222{
2223 unsigned int ofs;
2224
2225 switch (sc_reg_in) {
2226 case SCR_STATUS:
2227 case SCR_ERROR:
2228 case SCR_CONTROL:
2229 ofs = sc_reg_in * sizeof(u32);
2230 break;
2231 default:
2232 ofs = 0xffffffffU;
2233 break;
2234 }
2235 return ofs;
2236}
2237
Tejun Heo82ef04f2008-07-31 17:02:40 +09002238static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
Jeff Garzikc9d39132005-11-13 17:47:51 -05002239{
Tejun Heo82ef04f2008-07-31 17:02:40 +09002240 struct mv_host_priv *hpriv = link->ap->host->private_data;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05002241 void __iomem *mmio = hpriv->base;
Tejun Heo82ef04f2008-07-31 17:02:40 +09002242 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
Jeff Garzikc9d39132005-11-13 17:47:51 -05002243 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2244
Tejun Heoda3dbb12007-07-16 14:29:40 +09002245 if (ofs != 0xffffffffU) {
2246 *val = readl(addr + ofs);
2247 return 0;
2248 } else
2249 return -EINVAL;
Jeff Garzikc9d39132005-11-13 17:47:51 -05002250}
2251
Tejun Heo82ef04f2008-07-31 17:02:40 +09002252static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
Jeff Garzikc9d39132005-11-13 17:47:51 -05002253{
Tejun Heo82ef04f2008-07-31 17:02:40 +09002254 struct mv_host_priv *hpriv = link->ap->host->private_data;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05002255 void __iomem *mmio = hpriv->base;
Tejun Heo82ef04f2008-07-31 17:02:40 +09002256 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
Jeff Garzikc9d39132005-11-13 17:47:51 -05002257 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2258
Tejun Heoda3dbb12007-07-16 14:29:40 +09002259 if (ofs != 0xffffffffU) {
Tejun Heo0d5ff562007-02-01 15:06:36 +09002260 writelfl(val, addr + ofs);
Tejun Heoda3dbb12007-07-16 14:29:40 +09002261 return 0;
2262 } else
2263 return -EINVAL;
Jeff Garzikc9d39132005-11-13 17:47:51 -05002264}
2265
Saeed Bishara7bb3c522008-01-30 11:50:45 -11002266static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
Jeff Garzik522479f2005-11-12 22:14:02 -05002267{
Saeed Bishara7bb3c522008-01-30 11:50:45 -11002268 struct pci_dev *pdev = to_pci_dev(host->dev);
Jeff Garzik522479f2005-11-12 22:14:02 -05002269 int early_5080;
2270
Auke Kok44c10132007-06-08 15:46:36 -07002271 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
Jeff Garzik522479f2005-11-12 22:14:02 -05002272
2273 if (!early_5080) {
2274 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2275 tmp |= (1 << 0);
2276 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2277 }
2278
Saeed Bishara7bb3c522008-01-30 11:50:45 -11002279 mv_reset_pci_bus(host, mmio);
Jeff Garzik522479f2005-11-12 22:14:02 -05002280}
2281
2282static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2283{
Mark Lord8e7decd2008-05-02 02:07:51 -04002284 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
Jeff Garzik522479f2005-11-12 22:14:02 -05002285}
2286
Jeff Garzik47c2b672005-11-12 21:13:17 -05002287static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05002288 void __iomem *mmio)
2289{
Jeff Garzikc9d39132005-11-13 17:47:51 -05002290 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2291 u32 tmp;
2292
2293 tmp = readl(phy_mmio + MV5_PHY_MODE);
2294
2295 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2296 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05002297}
2298
Jeff Garzik47c2b672005-11-12 21:13:17 -05002299static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05002300{
Jeff Garzik522479f2005-11-12 22:14:02 -05002301 u32 tmp;
2302
Mark Lord8e7decd2008-05-02 02:07:51 -04002303 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
Jeff Garzik522479f2005-11-12 22:14:02 -05002304
2305 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2306
2307 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2308 tmp |= ~(1 << 0);
2309 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05002310}
2311
Jeff Garzik2a47ce02005-11-12 23:05:14 -05002312static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2313 unsigned int port)
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002314{
Jeff Garzikc9d39132005-11-13 17:47:51 -05002315 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2316 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2317 u32 tmp;
2318 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2319
2320 if (fix_apm_sq) {
Mark Lord8e7decd2008-05-02 02:07:51 -04002321 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
Jeff Garzikc9d39132005-11-13 17:47:51 -05002322 tmp |= (1 << 19);
Mark Lord8e7decd2008-05-02 02:07:51 -04002323 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
Jeff Garzikc9d39132005-11-13 17:47:51 -05002324
Mark Lord8e7decd2008-05-02 02:07:51 -04002325 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
Jeff Garzikc9d39132005-11-13 17:47:51 -05002326 tmp &= ~0x3;
2327 tmp |= 0x1;
Mark Lord8e7decd2008-05-02 02:07:51 -04002328 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
Jeff Garzikc9d39132005-11-13 17:47:51 -05002329 }
2330
2331 tmp = readl(phy_mmio + MV5_PHY_MODE);
2332 tmp &= ~mask;
2333 tmp |= hpriv->signal[port].pre;
2334 tmp |= hpriv->signal[port].amps;
2335 writel(tmp, phy_mmio + MV5_PHY_MODE);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002336}
2337
Jeff Garzikc9d39132005-11-13 17:47:51 -05002338
2339#undef ZERO
2340#define ZERO(reg) writel(0, port_mmio + (reg))
2341static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2342 unsigned int port)
Jeff Garzik47c2b672005-11-12 21:13:17 -05002343{
Jeff Garzikc9d39132005-11-13 17:47:51 -05002344 void __iomem *port_mmio = mv_port_base(mmio, port);
2345
Mark Lorde12bef52008-03-31 19:33:56 -04002346 mv_reset_channel(hpriv, mmio, port);
Jeff Garzikc9d39132005-11-13 17:47:51 -05002347
2348 ZERO(0x028); /* command */
2349 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2350 ZERO(0x004); /* timer */
2351 ZERO(0x008); /* irq err cause */
2352 ZERO(0x00c); /* irq err mask */
2353 ZERO(0x010); /* rq bah */
2354 ZERO(0x014); /* rq inp */
2355 ZERO(0x018); /* rq outp */
2356 ZERO(0x01c); /* respq bah */
2357 ZERO(0x024); /* respq outp */
2358 ZERO(0x020); /* respq inp */
2359 ZERO(0x02c); /* test control */
Mark Lord8e7decd2008-05-02 02:07:51 -04002360 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
Jeff Garzikc9d39132005-11-13 17:47:51 -05002361}
2362#undef ZERO
2363
2364#define ZERO(reg) writel(0, hc_mmio + (reg))
2365static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2366 unsigned int hc)
2367{
2368 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2369 u32 tmp;
2370
2371 ZERO(0x00c);
2372 ZERO(0x010);
2373 ZERO(0x014);
2374 ZERO(0x018);
2375
2376 tmp = readl(hc_mmio + 0x20);
2377 tmp &= 0x1c1c1c1c;
2378 tmp |= 0x03030303;
2379 writel(tmp, hc_mmio + 0x20);
2380}
2381#undef ZERO
2382
2383static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2384 unsigned int n_hc)
2385{
2386 unsigned int hc, port;
2387
2388 for (hc = 0; hc < n_hc; hc++) {
2389 for (port = 0; port < MV_PORTS_PER_HC; port++)
2390 mv5_reset_hc_port(hpriv, mmio,
2391 (hc * MV_PORTS_PER_HC) + port);
2392
2393 mv5_reset_one_hc(hpriv, mmio, hc);
2394 }
2395
2396 return 0;
Jeff Garzik47c2b672005-11-12 21:13:17 -05002397}
2398
Jeff Garzik101ffae2005-11-12 22:17:49 -05002399#undef ZERO
2400#define ZERO(reg) writel(0, mmio + (reg))
Saeed Bishara7bb3c522008-01-30 11:50:45 -11002401static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
Jeff Garzik101ffae2005-11-12 22:17:49 -05002402{
Mark Lord02a121d2007-12-01 13:07:22 -05002403 struct mv_host_priv *hpriv = host->private_data;
Jeff Garzik101ffae2005-11-12 22:17:49 -05002404 u32 tmp;
2405
Mark Lord8e7decd2008-05-02 02:07:51 -04002406 tmp = readl(mmio + MV_PCI_MODE_OFS);
Jeff Garzik101ffae2005-11-12 22:17:49 -05002407 tmp &= 0xff00ffff;
Mark Lord8e7decd2008-05-02 02:07:51 -04002408 writel(tmp, mmio + MV_PCI_MODE_OFS);
Jeff Garzik101ffae2005-11-12 22:17:49 -05002409
2410 ZERO(MV_PCI_DISC_TIMER);
2411 ZERO(MV_PCI_MSI_TRIGGER);
Mark Lord8e7decd2008-05-02 02:07:51 -04002412 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
Jeff Garzik101ffae2005-11-12 22:17:49 -05002413 ZERO(MV_PCI_SERR_MASK);
Mark Lord02a121d2007-12-01 13:07:22 -05002414 ZERO(hpriv->irq_cause_ofs);
2415 ZERO(hpriv->irq_mask_ofs);
Jeff Garzik101ffae2005-11-12 22:17:49 -05002416 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2417 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2418 ZERO(MV_PCI_ERR_ATTRIBUTE);
2419 ZERO(MV_PCI_ERR_COMMAND);
2420}
2421#undef ZERO
2422
2423static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2424{
2425 u32 tmp;
2426
2427 mv5_reset_flash(hpriv, mmio);
2428
Mark Lord8e7decd2008-05-02 02:07:51 -04002429 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
Jeff Garzik101ffae2005-11-12 22:17:49 -05002430 tmp &= 0x3;
2431 tmp |= (1 << 5) | (1 << 6);
Mark Lord8e7decd2008-05-02 02:07:51 -04002432 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
Jeff Garzik101ffae2005-11-12 22:17:49 -05002433}
2434
2435/**
2436 * mv6_reset_hc - Perform the 6xxx global soft reset
2437 * @mmio: base address of the HBA
2438 *
2439 * This routine only applies to 6xxx parts.
2440 *
2441 * LOCKING:
2442 * Inherited from caller.
2443 */
Jeff Garzikc9d39132005-11-13 17:47:51 -05002444static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2445 unsigned int n_hc)
Jeff Garzik101ffae2005-11-12 22:17:49 -05002446{
2447 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2448 int i, rc = 0;
2449 u32 t;
2450
2451 /* Following procedure defined in PCI "main command and status
2452 * register" table.
2453 */
2454 t = readl(reg);
2455 writel(t | STOP_PCI_MASTER, reg);
2456
2457 for (i = 0; i < 1000; i++) {
2458 udelay(1);
2459 t = readl(reg);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002460 if (PCI_MASTER_EMPTY & t)
Jeff Garzik101ffae2005-11-12 22:17:49 -05002461 break;
Jeff Garzik101ffae2005-11-12 22:17:49 -05002462 }
2463 if (!(PCI_MASTER_EMPTY & t)) {
2464 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2465 rc = 1;
2466 goto done;
2467 }
2468
2469 /* set reset */
2470 i = 5;
2471 do {
2472 writel(t | GLOB_SFT_RST, reg);
2473 t = readl(reg);
2474 udelay(1);
2475 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2476
2477 if (!(GLOB_SFT_RST & t)) {
2478 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2479 rc = 1;
2480 goto done;
2481 }
2482
2483 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2484 i = 5;
2485 do {
2486 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2487 t = readl(reg);
2488 udelay(1);
2489 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2490
2491 if (GLOB_SFT_RST & t) {
2492 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2493 rc = 1;
2494 }
2495done:
2496 return rc;
2497}
2498
Jeff Garzik47c2b672005-11-12 21:13:17 -05002499static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05002500 void __iomem *mmio)
2501{
2502 void __iomem *port_mmio;
2503 u32 tmp;
2504
Mark Lord8e7decd2008-05-02 02:07:51 -04002505 tmp = readl(mmio + MV_RESET_CFG_OFS);
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05002506 if ((tmp & (1 << 0)) == 0) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05002507 hpriv->signal[idx].amps = 0x7 << 8;
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05002508 hpriv->signal[idx].pre = 0x1 << 5;
2509 return;
2510 }
2511
2512 port_mmio = mv_port_base(mmio, idx);
2513 tmp = readl(port_mmio + PHY_MODE2);
2514
2515 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2516 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2517}
2518
Jeff Garzik47c2b672005-11-12 21:13:17 -05002519static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05002520{
Mark Lord8e7decd2008-05-02 02:07:51 -04002521 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05002522}
2523
Jeff Garzikc9d39132005-11-13 17:47:51 -05002524static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
Jeff Garzik2a47ce02005-11-12 23:05:14 -05002525 unsigned int port)
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002526{
Jeff Garzikc9d39132005-11-13 17:47:51 -05002527 void __iomem *port_mmio = mv_port_base(mmio, port);
2528
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002529 u32 hp_flags = hpriv->hp_flags;
Jeff Garzik47c2b672005-11-12 21:13:17 -05002530 int fix_phy_mode2 =
2531 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002532 int fix_phy_mode4 =
Jeff Garzik47c2b672005-11-12 21:13:17 -05002533 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
Mark Lord8c30a8b2008-05-27 17:56:31 -04002534 u32 m2, m3;
Jeff Garzik47c2b672005-11-12 21:13:17 -05002535
2536 if (fix_phy_mode2) {
2537 m2 = readl(port_mmio + PHY_MODE2);
2538 m2 &= ~(1 << 16);
2539 m2 |= (1 << 31);
2540 writel(m2, port_mmio + PHY_MODE2);
2541
2542 udelay(200);
2543
2544 m2 = readl(port_mmio + PHY_MODE2);
2545 m2 &= ~((1 << 16) | (1 << 31));
2546 writel(m2, port_mmio + PHY_MODE2);
2547
2548 udelay(200);
2549 }
2550
Mark Lord8c30a8b2008-05-27 17:56:31 -04002551 /*
2552 * Gen-II/IIe PHY_MODE3 errata RM#2:
2553 * Achieves better receiver noise performance than the h/w default:
2554 */
2555 m3 = readl(port_mmio + PHY_MODE3);
2556 m3 = (m3 & 0x1f) | (0x5555601 << 5);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002557
Mark Lord0388a8c2008-05-28 13:41:52 -04002558 /* Guideline 88F5182 (GL# SATA-S11) */
2559 if (IS_SOC(hpriv))
2560 m3 &= ~0x1c;
2561
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002562 if (fix_phy_mode4) {
Mark Lordba069e32008-05-31 16:46:34 -04002563 u32 m4 = readl(port_mmio + PHY_MODE4);
2564 /*
2565 * Enforce reserved-bit restrictions on GenIIe devices only.
2566 * For earlier chipsets, force only the internal config field
2567 * (workaround for errata FEr SATA#10 part 1).
2568 */
Mark Lord8c30a8b2008-05-27 17:56:31 -04002569 if (IS_GEN_IIE(hpriv))
Mark Lordba069e32008-05-31 16:46:34 -04002570 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
2571 else
2572 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
Mark Lord8c30a8b2008-05-27 17:56:31 -04002573 writel(m4, port_mmio + PHY_MODE4);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002574 }
Mark Lordb406c7a2008-05-28 12:01:12 -04002575 /*
2576 * Workaround for 60x1-B2 errata SATA#13:
2577 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
2578 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
2579 */
2580 writel(m3, port_mmio + PHY_MODE3);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002581
2582 /* Revert values of pre-emphasis and signal amps to the saved ones */
2583 m2 = readl(port_mmio + PHY_MODE2);
2584
2585 m2 &= ~MV_M2_PREAMP_MASK;
Jeff Garzik2a47ce02005-11-12 23:05:14 -05002586 m2 |= hpriv->signal[port].amps;
2587 m2 |= hpriv->signal[port].pre;
Jeff Garzik47c2b672005-11-12 21:13:17 -05002588 m2 &= ~(1 << 16);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002589
Jeff Garzike4e7b892006-01-31 12:18:41 -05002590 /* according to mvSata 3.6.1, some IIE values are fixed */
2591 if (IS_GEN_IIE(hpriv)) {
2592 m2 &= ~0xC30FF01F;
2593 m2 |= 0x0000900F;
2594 }
2595
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002596 writel(m2, port_mmio + PHY_MODE2);
2597}
2598
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05002599/* TODO: use the generic LED interface to configure the SATA Presence */
2600/* & Acitivy LEDs on the board */
2601static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2602 void __iomem *mmio)
2603{
2604 return;
2605}
2606
2607static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2608 void __iomem *mmio)
2609{
2610 void __iomem *port_mmio;
2611 u32 tmp;
2612
2613 port_mmio = mv_port_base(mmio, idx);
2614 tmp = readl(port_mmio + PHY_MODE2);
2615
2616 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2617 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2618}
2619
2620#undef ZERO
2621#define ZERO(reg) writel(0, port_mmio + (reg))
2622static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2623 void __iomem *mmio, unsigned int port)
2624{
2625 void __iomem *port_mmio = mv_port_base(mmio, port);
2626
Mark Lorde12bef52008-03-31 19:33:56 -04002627 mv_reset_channel(hpriv, mmio, port);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05002628
2629 ZERO(0x028); /* command */
2630 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2631 ZERO(0x004); /* timer */
2632 ZERO(0x008); /* irq err cause */
2633 ZERO(0x00c); /* irq err mask */
2634 ZERO(0x010); /* rq bah */
2635 ZERO(0x014); /* rq inp */
2636 ZERO(0x018); /* rq outp */
2637 ZERO(0x01c); /* respq bah */
2638 ZERO(0x024); /* respq outp */
2639 ZERO(0x020); /* respq inp */
2640 ZERO(0x02c); /* test control */
Mark Lord8e7decd2008-05-02 02:07:51 -04002641 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05002642}
2643
2644#undef ZERO
2645
2646#define ZERO(reg) writel(0, hc_mmio + (reg))
2647static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2648 void __iomem *mmio)
2649{
2650 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2651
2652 ZERO(0x00c);
2653 ZERO(0x010);
2654 ZERO(0x014);
2655
2656}
2657
2658#undef ZERO
2659
2660static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2661 void __iomem *mmio, unsigned int n_hc)
2662{
2663 unsigned int port;
2664
2665 for (port = 0; port < hpriv->n_ports; port++)
2666 mv_soc_reset_hc_port(hpriv, mmio, port);
2667
2668 mv_soc_reset_one_hc(hpriv, mmio);
2669
2670 return 0;
2671}
2672
2673static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2674 void __iomem *mmio)
2675{
2676 return;
2677}
2678
2679static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2680{
2681 return;
2682}
2683
Mark Lord8e7decd2008-05-02 02:07:51 -04002684static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
Mark Lordb67a1062008-03-31 19:35:13 -04002685{
Mark Lord8e7decd2008-05-02 02:07:51 -04002686 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
Mark Lordb67a1062008-03-31 19:35:13 -04002687
Mark Lord8e7decd2008-05-02 02:07:51 -04002688 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
Mark Lordb67a1062008-03-31 19:35:13 -04002689 if (want_gen2i)
Mark Lord8e7decd2008-05-02 02:07:51 -04002690 ifcfg |= (1 << 7); /* enable gen2i speed */
2691 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
Mark Lordb67a1062008-03-31 19:35:13 -04002692}
2693
Mark Lorde12bef52008-03-31 19:33:56 -04002694static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
Jeff Garzikc9d39132005-11-13 17:47:51 -05002695 unsigned int port_no)
Brett Russ20f733e2005-09-01 18:26:17 -04002696{
Jeff Garzikc9d39132005-11-13 17:47:51 -05002697 void __iomem *port_mmio = mv_port_base(mmio, port_no);
Brett Russ20f733e2005-09-01 18:26:17 -04002698
Mark Lord8e7decd2008-05-02 02:07:51 -04002699 /*
2700 * The datasheet warns against setting EDMA_RESET when EDMA is active
2701 * (but doesn't say what the problem might be). So we first try
2702 * to disable the EDMA engine before doing the EDMA_RESET operation.
2703 */
Mark Lord0d8be5c2008-04-16 14:56:12 -04002704 mv_stop_edma_engine(port_mmio);
Mark Lord8e7decd2008-05-02 02:07:51 -04002705 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002706
Mark Lordb67a1062008-03-31 19:35:13 -04002707 if (!IS_GEN_I(hpriv)) {
Mark Lord8e7decd2008-05-02 02:07:51 -04002708 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2709 mv_setup_ifcfg(port_mmio, 1);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002710 }
Mark Lordb67a1062008-03-31 19:35:13 -04002711 /*
Mark Lord8e7decd2008-05-02 02:07:51 -04002712 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
Mark Lordb67a1062008-03-31 19:35:13 -04002713 * link, and physical layers. It resets all SATA interface registers
2714 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
Brett Russ20f733e2005-09-01 18:26:17 -04002715 */
Mark Lord8e7decd2008-05-02 02:07:51 -04002716 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
Mark Lordb67a1062008-03-31 19:35:13 -04002717 udelay(25); /* allow reset propagation */
Brett Russ31961942005-09-30 01:36:00 -04002718 writelfl(0, port_mmio + EDMA_CMD_OFS);
Brett Russ20f733e2005-09-01 18:26:17 -04002719
Jeff Garzikc9d39132005-11-13 17:47:51 -05002720 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2721
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04002722 if (IS_GEN_I(hpriv))
Jeff Garzikc9d39132005-11-13 17:47:51 -05002723 mdelay(1);
2724}
2725
Mark Lorde49856d2008-04-16 14:59:07 -04002726static void mv_pmp_select(struct ata_port *ap, int pmp)
Jeff Garzikc9d39132005-11-13 17:47:51 -05002727{
Mark Lorde49856d2008-04-16 14:59:07 -04002728 if (sata_pmp_supported(ap)) {
2729 void __iomem *port_mmio = mv_ap_base(ap);
2730 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2731 int old = reg & 0xf;
Jeff Garzikc9d39132005-11-13 17:47:51 -05002732
Mark Lorde49856d2008-04-16 14:59:07 -04002733 if (old != pmp) {
2734 reg = (reg & ~0xf) | pmp;
2735 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2736 }
Tejun Heoda3dbb12007-07-16 14:29:40 +09002737 }
Brett Russ20f733e2005-09-01 18:26:17 -04002738}
2739
Mark Lorde49856d2008-04-16 14:59:07 -04002740static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2741 unsigned long deadline)
Jeff Garzik22374672005-11-17 10:59:48 -05002742{
Mark Lorde49856d2008-04-16 14:59:07 -04002743 mv_pmp_select(link->ap, sata_srst_pmp(link));
2744 return sata_std_hardreset(link, class, deadline);
2745}
Jeff Garzik0ea9e172007-07-13 17:06:45 -04002746
Mark Lorde49856d2008-04-16 14:59:07 -04002747static int mv_softreset(struct ata_link *link, unsigned int *class,
2748 unsigned long deadline)
2749{
2750 mv_pmp_select(link->ap, sata_srst_pmp(link));
2751 return ata_sff_softreset(link, class, deadline);
Jeff Garzik22374672005-11-17 10:59:48 -05002752}
2753
Tejun Heocc0680a2007-08-06 18:36:23 +09002754static int mv_hardreset(struct ata_link *link, unsigned int *class,
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002755 unsigned long deadline)
2756{
Tejun Heocc0680a2007-08-06 18:36:23 +09002757 struct ata_port *ap = link->ap;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002758 struct mv_host_priv *hpriv = ap->host->private_data;
Mark Lordb5624682008-03-31 19:34:40 -04002759 struct mv_port_priv *pp = ap->private_data;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05002760 void __iomem *mmio = hpriv->base;
Mark Lord0d8be5c2008-04-16 14:56:12 -04002761 int rc, attempts = 0, extra = 0;
2762 u32 sstatus;
2763 bool online;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002764
Mark Lorde12bef52008-03-31 19:33:56 -04002765 mv_reset_channel(hpriv, mmio, ap->port_no);
Mark Lordb5624682008-03-31 19:34:40 -04002766 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002767
Mark Lord0d8be5c2008-04-16 14:56:12 -04002768 /* Workaround for errata FEr SATA#10 (part 2) */
2769 do {
Mark Lord17c5aab2008-04-16 14:56:51 -04002770 const unsigned long *timing =
2771 sata_ehc_deb_timing(&link->eh_context);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002772
Mark Lord17c5aab2008-04-16 14:56:51 -04002773 rc = sata_link_hardreset(link, timing, deadline + extra,
2774 &online, NULL);
Mark Lord9dcffd92008-05-14 09:18:12 -04002775 rc = online ? -EAGAIN : rc;
Mark Lord17c5aab2008-04-16 14:56:51 -04002776 if (rc)
Mark Lord0d8be5c2008-04-16 14:56:12 -04002777 return rc;
Mark Lord0d8be5c2008-04-16 14:56:12 -04002778 sata_scr_read(link, SCR_STATUS, &sstatus);
2779 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2780 /* Force 1.5gb/s link speed and try again */
Mark Lord8e7decd2008-05-02 02:07:51 -04002781 mv_setup_ifcfg(mv_ap_base(ap), 0);
Mark Lord0d8be5c2008-04-16 14:56:12 -04002782 if (time_after(jiffies + HZ, deadline))
2783 extra = HZ; /* only extend it once, max */
2784 }
2785 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002786
Mark Lord17c5aab2008-04-16 14:56:51 -04002787 return rc;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002788}
2789
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002790static void mv_eh_freeze(struct ata_port *ap)
Brett Russ20f733e2005-09-01 18:26:17 -04002791{
Mark Lord1cfd19a2008-04-19 15:05:50 -04002792 mv_stop_edma(ap);
Mark Lordc4de5732008-05-17 13:35:21 -04002793 mv_enable_port_irqs(ap, 0);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002794}
2795
2796static void mv_eh_thaw(struct ata_port *ap)
2797{
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05002798 struct mv_host_priv *hpriv = ap->host->private_data;
Mark Lordc4de5732008-05-17 13:35:21 -04002799 unsigned int port = ap->port_no;
2800 unsigned int hardport = mv_hardport_from_port(port);
Mark Lord1cfd19a2008-04-19 15:05:50 -04002801 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002802 void __iomem *port_mmio = mv_ap_base(ap);
Mark Lordc4de5732008-05-17 13:35:21 -04002803 u32 hc_irq_cause;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002804
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002805 /* clear EDMA errors on this port */
2806 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2807
2808 /* clear pending irq events */
Mark Lordcae6edc2009-01-19 18:05:42 -05002809 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
Mark Lord1cfd19a2008-04-19 15:05:50 -04002810 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002811
Mark Lord88e675e2008-05-17 13:36:30 -04002812 mv_enable_port_irqs(ap, ERR_IRQ);
Brett Russ31961942005-09-30 01:36:00 -04002813}
2814
Brett Russ05b308e2005-10-05 17:08:53 -04002815/**
2816 * mv_port_init - Perform some early initialization on a single port.
2817 * @port: libata data structure storing shadow register addresses
2818 * @port_mmio: base address of the port
2819 *
2820 * Initialize shadow register mmio addresses, clear outstanding
2821 * interrupts on the port, and unmask interrupts for the future
2822 * start of the port.
2823 *
2824 * LOCKING:
2825 * Inherited from caller.
2826 */
Brett Russ31961942005-09-30 01:36:00 -04002827static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2828{
Tejun Heo0d5ff562007-02-01 15:06:36 +09002829 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
Brett Russ31961942005-09-30 01:36:00 -04002830 unsigned serr_ofs;
2831
Jeff Garzik8b260242005-11-12 12:32:50 -05002832 /* PIO related setup
Brett Russ31961942005-09-30 01:36:00 -04002833 */
2834 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
Jeff Garzik8b260242005-11-12 12:32:50 -05002835 port->error_addr =
Brett Russ31961942005-09-30 01:36:00 -04002836 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2837 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2838 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2839 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2840 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2841 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
Jeff Garzik8b260242005-11-12 12:32:50 -05002842 port->status_addr =
Brett Russ31961942005-09-30 01:36:00 -04002843 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2844 /* special case: control/altstatus doesn't have ATA_REG_ address */
2845 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2846
2847 /* unused: */
Randy Dunlap8d9db2d2007-02-16 01:40:06 -08002848 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
Brett Russ20f733e2005-09-01 18:26:17 -04002849
Brett Russ31961942005-09-30 01:36:00 -04002850 /* Clear any currently outstanding port interrupt conditions */
2851 serr_ofs = mv_scr_offset(SCR_ERROR);
2852 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2853 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2854
Mark Lord646a4da2008-01-26 18:30:37 -05002855 /* unmask all non-transient EDMA error interrupts */
2856 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
Brett Russ20f733e2005-09-01 18:26:17 -04002857
Jeff Garzik8b260242005-11-12 12:32:50 -05002858 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
Brett Russ31961942005-09-30 01:36:00 -04002859 readl(port_mmio + EDMA_CFG_OFS),
2860 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2861 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
Brett Russ20f733e2005-09-01 18:26:17 -04002862}
2863
Mark Lord616d4a92008-05-02 02:08:32 -04002864static unsigned int mv_in_pcix_mode(struct ata_host *host)
2865{
2866 struct mv_host_priv *hpriv = host->private_data;
2867 void __iomem *mmio = hpriv->base;
2868 u32 reg;
2869
Mark Lord1f398472008-05-27 17:54:48 -04002870 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
Mark Lord616d4a92008-05-02 02:08:32 -04002871 return 0; /* not PCI-X capable */
2872 reg = readl(mmio + MV_PCI_MODE_OFS);
2873 if ((reg & MV_PCI_MODE_MASK) == 0)
2874 return 0; /* conventional PCI mode */
2875 return 1; /* chip is in PCI-X mode */
2876}
2877
2878static int mv_pci_cut_through_okay(struct ata_host *host)
2879{
2880 struct mv_host_priv *hpriv = host->private_data;
2881 void __iomem *mmio = hpriv->base;
2882 u32 reg;
2883
2884 if (!mv_in_pcix_mode(host)) {
2885 reg = readl(mmio + PCI_COMMAND_OFS);
2886 if (reg & PCI_COMMAND_MRDTRIG)
2887 return 0; /* not okay */
2888 }
2889 return 1; /* okay */
2890}
2891
Tejun Heo4447d352007-04-17 23:44:08 +09002892static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002893{
Tejun Heo4447d352007-04-17 23:44:08 +09002894 struct pci_dev *pdev = to_pci_dev(host->dev);
2895 struct mv_host_priv *hpriv = host->private_data;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002896 u32 hp_flags = hpriv->hp_flags;
2897
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002898 switch (board_idx) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05002899 case chip_5080:
2900 hpriv->ops = &mv5xxx_ops;
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04002901 hp_flags |= MV_HP_GEN_I;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002902
Auke Kok44c10132007-06-08 15:46:36 -07002903 switch (pdev->revision) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05002904 case 0x1:
2905 hp_flags |= MV_HP_ERRATA_50XXB0;
2906 break;
2907 case 0x3:
2908 hp_flags |= MV_HP_ERRATA_50XXB2;
2909 break;
2910 default:
2911 dev_printk(KERN_WARNING, &pdev->dev,
2912 "Applying 50XXB2 workarounds to unknown rev\n");
2913 hp_flags |= MV_HP_ERRATA_50XXB2;
2914 break;
2915 }
2916 break;
2917
2918 case chip_504x:
2919 case chip_508x:
2920 hpriv->ops = &mv5xxx_ops;
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04002921 hp_flags |= MV_HP_GEN_I;
Jeff Garzik47c2b672005-11-12 21:13:17 -05002922
Auke Kok44c10132007-06-08 15:46:36 -07002923 switch (pdev->revision) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05002924 case 0x0:
2925 hp_flags |= MV_HP_ERRATA_50XXB0;
2926 break;
2927 case 0x3:
2928 hp_flags |= MV_HP_ERRATA_50XXB2;
2929 break;
2930 default:
2931 dev_printk(KERN_WARNING, &pdev->dev,
2932 "Applying B2 workarounds to unknown rev\n");
2933 hp_flags |= MV_HP_ERRATA_50XXB2;
2934 break;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002935 }
2936 break;
2937
2938 case chip_604x:
2939 case chip_608x:
Jeff Garzik47c2b672005-11-12 21:13:17 -05002940 hpriv->ops = &mv6xxx_ops;
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04002941 hp_flags |= MV_HP_GEN_II;
Jeff Garzik47c2b672005-11-12 21:13:17 -05002942
Auke Kok44c10132007-06-08 15:46:36 -07002943 switch (pdev->revision) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05002944 case 0x7:
2945 hp_flags |= MV_HP_ERRATA_60X1B2;
2946 break;
2947 case 0x9:
2948 hp_flags |= MV_HP_ERRATA_60X1C0;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002949 break;
2950 default:
2951 dev_printk(KERN_WARNING, &pdev->dev,
Jeff Garzik47c2b672005-11-12 21:13:17 -05002952 "Applying B2 workarounds to unknown rev\n");
2953 hp_flags |= MV_HP_ERRATA_60X1B2;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05002954 break;
2955 }
2956 break;
2957
Jeff Garzike4e7b892006-01-31 12:18:41 -05002958 case chip_7042:
Mark Lord616d4a92008-05-02 02:08:32 -04002959 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
Mark Lord306b30f2007-12-04 14:07:52 -05002960 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2961 (pdev->device == 0x2300 || pdev->device == 0x2310))
2962 {
Mark Lord4e520032007-12-11 12:58:05 -05002963 /*
2964 * Highpoint RocketRAID PCIe 23xx series cards:
2965 *
2966 * Unconfigured drives are treated as "Legacy"
2967 * by the BIOS, and it overwrites sector 8 with
2968 * a "Lgcy" metadata block prior to Linux boot.
2969 *
2970 * Configured drives (RAID or JBOD) leave sector 8
2971 * alone, but instead overwrite a high numbered
2972 * sector for the RAID metadata. This sector can
2973 * be determined exactly, by truncating the physical
2974 * drive capacity to a nice even GB value.
2975 *
2976 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2977 *
2978 * Warn the user, lest they think we're just buggy.
2979 */
2980 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2981 " BIOS CORRUPTS DATA on all attached drives,"
2982 " regardless of if/how they are configured."
2983 " BEWARE!\n");
2984 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2985 " use sectors 8-9 on \"Legacy\" drives,"
2986 " and avoid the final two gigabytes on"
2987 " all RocketRAID BIOS initialized drives.\n");
Mark Lord306b30f2007-12-04 14:07:52 -05002988 }
Mark Lord8e7decd2008-05-02 02:07:51 -04002989 /* drop through */
Jeff Garzike4e7b892006-01-31 12:18:41 -05002990 case chip_6042:
2991 hpriv->ops = &mv6xxx_ops;
Jeff Garzike4e7b892006-01-31 12:18:41 -05002992 hp_flags |= MV_HP_GEN_IIE;
Mark Lord616d4a92008-05-02 02:08:32 -04002993 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2994 hp_flags |= MV_HP_CUT_THROUGH;
Jeff Garzike4e7b892006-01-31 12:18:41 -05002995
Auke Kok44c10132007-06-08 15:46:36 -07002996 switch (pdev->revision) {
Mark Lord5cf73bf2008-05-27 17:58:56 -04002997 case 0x2: /* Rev.B0: the first/only public release */
Jeff Garzike4e7b892006-01-31 12:18:41 -05002998 hp_flags |= MV_HP_ERRATA_60X1C0;
2999 break;
3000 default:
3001 dev_printk(KERN_WARNING, &pdev->dev,
3002 "Applying 60X1C0 workarounds to unknown rev\n");
3003 hp_flags |= MV_HP_ERRATA_60X1C0;
3004 break;
3005 }
3006 break;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003007 case chip_soc:
3008 hpriv->ops = &mv_soc_ops;
Saeed Bisharaeb3a55a2008-08-04 00:52:55 -11003009 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3010 MV_HP_ERRATA_60X1C0;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003011 break;
Jeff Garzike4e7b892006-01-31 12:18:41 -05003012
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003013 default:
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003014 dev_printk(KERN_ERR, host->dev,
Jeff Garzik5796d1c2007-10-26 00:03:37 -04003015 "BUG: invalid board index %u\n", board_idx);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003016 return 1;
3017 }
3018
3019 hpriv->hp_flags = hp_flags;
Mark Lord02a121d2007-12-01 13:07:22 -05003020 if (hp_flags & MV_HP_PCIE) {
3021 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3022 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3023 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3024 } else {
3025 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3026 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3027 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3028 }
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003029
3030 return 0;
3031}
3032
Brett Russ05b308e2005-10-05 17:08:53 -04003033/**
Jeff Garzik47c2b672005-11-12 21:13:17 -05003034 * mv_init_host - Perform some early initialization of the host.
Tejun Heo4447d352007-04-17 23:44:08 +09003035 * @host: ATA host to initialize
3036 * @board_idx: controller index
Brett Russ05b308e2005-10-05 17:08:53 -04003037 *
3038 * If possible, do an early global reset of the host. Then do
3039 * our port init and clear/unmask all/relevant host interrupts.
3040 *
3041 * LOCKING:
3042 * Inherited from caller.
3043 */
Tejun Heo4447d352007-04-17 23:44:08 +09003044static int mv_init_host(struct ata_host *host, unsigned int board_idx)
Brett Russ20f733e2005-09-01 18:26:17 -04003045{
3046 int rc = 0, n_hc, port, hc;
Tejun Heo4447d352007-04-17 23:44:08 +09003047 struct mv_host_priv *hpriv = host->private_data;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003048 void __iomem *mmio = hpriv->base;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003049
Tejun Heo4447d352007-04-17 23:44:08 +09003050 rc = mv_chip_id(host, board_idx);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003051 if (rc)
Mark Lord352fab72008-04-19 14:43:42 -04003052 goto done;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003053
Mark Lord1f398472008-05-27 17:54:48 -04003054 if (IS_SOC(hpriv)) {
Mark Lord7368f912008-04-25 11:24:24 -04003055 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3056 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
Mark Lord1f398472008-05-27 17:54:48 -04003057 } else {
3058 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3059 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003060 }
Mark Lord352fab72008-04-19 14:43:42 -04003061
3062 /* global interrupt mask: 0 == mask everything */
Mark Lordc4de5732008-05-17 13:35:21 -04003063 mv_set_main_irq_mask(host, ~0, 0);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003064
Tejun Heo4447d352007-04-17 23:44:08 +09003065 n_hc = mv_get_hc_count(host->ports[0]->flags);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003066
Tejun Heo4447d352007-04-17 23:44:08 +09003067 for (port = 0; port < host->n_ports; port++)
Jeff Garzik47c2b672005-11-12 21:13:17 -05003068 hpriv->ops->read_preamp(hpriv, port, mmio);
Brett Russ20f733e2005-09-01 18:26:17 -04003069
Jeff Garzikc9d39132005-11-13 17:47:51 -05003070 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
Jeff Garzik47c2b672005-11-12 21:13:17 -05003071 if (rc)
Brett Russ20f733e2005-09-01 18:26:17 -04003072 goto done;
Brett Russ20f733e2005-09-01 18:26:17 -04003073
Jeff Garzik522479f2005-11-12 22:14:02 -05003074 hpriv->ops->reset_flash(hpriv, mmio);
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003075 hpriv->ops->reset_bus(host, mmio);
Jeff Garzik47c2b672005-11-12 21:13:17 -05003076 hpriv->ops->enable_leds(hpriv, mmio);
Brett Russ20f733e2005-09-01 18:26:17 -04003077
Tejun Heo4447d352007-04-17 23:44:08 +09003078 for (port = 0; port < host->n_ports; port++) {
Tejun Heocbcdd872007-08-18 13:14:55 +09003079 struct ata_port *ap = host->ports[port];
Jeff Garzik2a47ce02005-11-12 23:05:14 -05003080 void __iomem *port_mmio = mv_port_base(mmio, port);
Tejun Heocbcdd872007-08-18 13:14:55 +09003081
3082 mv_port_init(&ap->ioaddr, port_mmio);
3083
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003084#ifdef CONFIG_PCI
Mark Lord1f398472008-05-27 17:54:48 -04003085 if (!IS_SOC(hpriv)) {
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003086 unsigned int offset = port_mmio - mmio;
3087 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3088 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3089 }
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003090#endif
Brett Russ20f733e2005-09-01 18:26:17 -04003091 }
3092
3093 for (hc = 0; hc < n_hc; hc++) {
Brett Russ31961942005-09-30 01:36:00 -04003094 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3095
3096 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3097 "(before clear)=0x%08x\n", hc,
3098 readl(hc_mmio + HC_CFG_OFS),
3099 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3100
3101 /* Clear any currently outstanding hc interrupt conditions */
3102 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
Brett Russ20f733e2005-09-01 18:26:17 -04003103 }
3104
Mark Lord1f398472008-05-27 17:54:48 -04003105 if (!IS_SOC(hpriv)) {
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003106 /* Clear any currently outstanding host interrupt conditions */
3107 writelfl(0, mmio + hpriv->irq_cause_ofs);
Brett Russ31961942005-09-30 01:36:00 -04003108
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003109 /* and unmask interrupt generation for host regs */
3110 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
Jeff Garzikfb621e22007-02-25 04:19:45 -05003111
Mark Lord51de32d2008-05-17 13:34:42 -04003112 /*
3113 * enable only global host interrupts for now.
3114 * The per-port interrupts get done later as ports are set up.
3115 */
Mark Lordc4de5732008-05-17 13:35:21 -04003116 mv_set_main_irq_mask(host, 0, PCI_ERR);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003117 }
Brett Russ31961942005-09-30 01:36:00 -04003118done:
Brett Russ20f733e2005-09-01 18:26:17 -04003119 return rc;
3120}
3121
Byron Bradleyfbf14e22008-02-10 21:17:30 +00003122static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3123{
3124 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3125 MV_CRQB_Q_SZ, 0);
3126 if (!hpriv->crqb_pool)
3127 return -ENOMEM;
3128
3129 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3130 MV_CRPB_Q_SZ, 0);
3131 if (!hpriv->crpb_pool)
3132 return -ENOMEM;
3133
3134 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3135 MV_SG_TBL_SZ, 0);
3136 if (!hpriv->sg_tbl_pool)
3137 return -ENOMEM;
3138
3139 return 0;
3140}
3141
Lennert Buytenhek15a32632008-03-27 14:51:39 -04003142static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3143 struct mbus_dram_target_info *dram)
3144{
3145 int i;
3146
3147 for (i = 0; i < 4; i++) {
3148 writel(0, hpriv->base + WINDOW_CTRL(i));
3149 writel(0, hpriv->base + WINDOW_BASE(i));
3150 }
3151
3152 for (i = 0; i < dram->num_cs; i++) {
3153 struct mbus_dram_window *cs = dram->cs + i;
3154
3155 writel(((cs->size - 1) & 0xffff0000) |
3156 (cs->mbus_attr << 8) |
3157 (dram->mbus_dram_target_id << 4) | 1,
3158 hpriv->base + WINDOW_CTRL(i));
3159 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3160 }
3161}
3162
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003163/**
3164 * mv_platform_probe - handle a positive probe of an soc Marvell
3165 * host
3166 * @pdev: platform device found
3167 *
3168 * LOCKING:
3169 * Inherited from caller.
3170 */
3171static int mv_platform_probe(struct platform_device *pdev)
3172{
3173 static int printed_version;
3174 const struct mv_sata_platform_data *mv_platform_data;
3175 const struct ata_port_info *ppi[] =
3176 { &mv_port_info[chip_soc], NULL };
3177 struct ata_host *host;
3178 struct mv_host_priv *hpriv;
3179 struct resource *res;
3180 int n_ports, rc;
3181
3182 if (!printed_version++)
3183 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3184
3185 /*
3186 * Simple resource validation ..
3187 */
3188 if (unlikely(pdev->num_resources != 2)) {
3189 dev_err(&pdev->dev, "invalid number of resources\n");
3190 return -EINVAL;
3191 }
3192
3193 /*
3194 * Get the register base first
3195 */
3196 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3197 if (res == NULL)
3198 return -EINVAL;
3199
3200 /* allocate host */
3201 mv_platform_data = pdev->dev.platform_data;
3202 n_ports = mv_platform_data->n_ports;
3203
3204 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3205 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3206
3207 if (!host || !hpriv)
3208 return -ENOMEM;
3209 host->private_data = hpriv;
3210 hpriv->n_ports = n_ports;
3211
3212 host->iomap = NULL;
Saeed Bisharaf1cb0ea2008-02-18 07:42:28 -11003213 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3214 res->end - res->start + 1);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003215 hpriv->base -= MV_SATAHC0_REG_BASE;
3216
Lennert Buytenhek15a32632008-03-27 14:51:39 -04003217 /*
3218 * (Re-)program MBUS remapping windows if we are asked to.
3219 */
3220 if (mv_platform_data->dram != NULL)
3221 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3222
Byron Bradleyfbf14e22008-02-10 21:17:30 +00003223 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3224 if (rc)
3225 return rc;
3226
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003227 /* initialize adapter */
3228 rc = mv_init_host(host, chip_soc);
3229 if (rc)
3230 return rc;
3231
3232 dev_printk(KERN_INFO, &pdev->dev,
3233 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3234 host->n_ports);
3235
3236 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3237 IRQF_SHARED, &mv6_sht);
3238}
3239
3240/*
3241 *
3242 * mv_platform_remove - unplug a platform interface
3243 * @pdev: platform device
3244 *
3245 * A platform bus SATA device has been unplugged. Perform the needed
3246 * cleanup. Also called on module unload for any active devices.
3247 */
3248static int __devexit mv_platform_remove(struct platform_device *pdev)
3249{
3250 struct device *dev = &pdev->dev;
3251 struct ata_host *host = dev_get_drvdata(dev);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003252
3253 ata_host_detach(host);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003254 return 0;
3255}
3256
3257static struct platform_driver mv_platform_driver = {
3258 .probe = mv_platform_probe,
3259 .remove = __devexit_p(mv_platform_remove),
3260 .driver = {
3261 .name = DRV_NAME,
3262 .owner = THIS_MODULE,
3263 },
3264};
3265
3266
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003267#ifdef CONFIG_PCI
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003268static int mv_pci_init_one(struct pci_dev *pdev,
3269 const struct pci_device_id *ent);
3270
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003271
3272static struct pci_driver mv_pci_driver = {
3273 .name = DRV_NAME,
3274 .id_table = mv_pci_tbl,
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003275 .probe = mv_pci_init_one,
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003276 .remove = ata_pci_remove_one,
3277};
3278
3279/*
3280 * module options
3281 */
3282static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3283
3284
3285/* move to PCI layer or libata core? */
3286static int pci_go_64(struct pci_dev *pdev)
3287{
3288 int rc;
3289
3290 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3291 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3292 if (rc) {
3293 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3294 if (rc) {
3295 dev_printk(KERN_ERR, &pdev->dev,
3296 "64-bit DMA enable failed\n");
3297 return rc;
3298 }
3299 }
3300 } else {
3301 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3302 if (rc) {
3303 dev_printk(KERN_ERR, &pdev->dev,
3304 "32-bit DMA enable failed\n");
3305 return rc;
3306 }
3307 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3308 if (rc) {
3309 dev_printk(KERN_ERR, &pdev->dev,
3310 "32-bit consistent DMA enable failed\n");
3311 return rc;
3312 }
3313 }
3314
3315 return rc;
3316}
3317
Brett Russ05b308e2005-10-05 17:08:53 -04003318/**
3319 * mv_print_info - Dump key info to kernel log for perusal.
Tejun Heo4447d352007-04-17 23:44:08 +09003320 * @host: ATA host to print info about
Brett Russ05b308e2005-10-05 17:08:53 -04003321 *
3322 * FIXME: complete this.
3323 *
3324 * LOCKING:
3325 * Inherited from caller.
3326 */
Tejun Heo4447d352007-04-17 23:44:08 +09003327static void mv_print_info(struct ata_host *host)
Brett Russ31961942005-09-30 01:36:00 -04003328{
Tejun Heo4447d352007-04-17 23:44:08 +09003329 struct pci_dev *pdev = to_pci_dev(host->dev);
3330 struct mv_host_priv *hpriv = host->private_data;
Auke Kok44c10132007-06-08 15:46:36 -07003331 u8 scc;
Jeff Garzikc1e4fe72007-07-09 12:29:31 -04003332 const char *scc_s, *gen;
Brett Russ31961942005-09-30 01:36:00 -04003333
3334 /* Use this to determine the HW stepping of the chip so we know
3335 * what errata to workaround
3336 */
Brett Russ31961942005-09-30 01:36:00 -04003337 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3338 if (scc == 0)
3339 scc_s = "SCSI";
3340 else if (scc == 0x01)
3341 scc_s = "RAID";
3342 else
Jeff Garzikc1e4fe72007-07-09 12:29:31 -04003343 scc_s = "?";
3344
3345 if (IS_GEN_I(hpriv))
3346 gen = "I";
3347 else if (IS_GEN_II(hpriv))
3348 gen = "II";
3349 else if (IS_GEN_IIE(hpriv))
3350 gen = "IIE";
3351 else
3352 gen = "?";
Brett Russ31961942005-09-30 01:36:00 -04003353
Jeff Garzika9524a72005-10-30 14:39:11 -05003354 dev_printk(KERN_INFO, &pdev->dev,
Jeff Garzikc1e4fe72007-07-09 12:29:31 -04003355 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3356 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
Brett Russ31961942005-09-30 01:36:00 -04003357 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3358}
3359
Brett Russ05b308e2005-10-05 17:08:53 -04003360/**
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003361 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
Brett Russ05b308e2005-10-05 17:08:53 -04003362 * @pdev: PCI device found
3363 * @ent: PCI device ID entry for the matched host
3364 *
3365 * LOCKING:
3366 * Inherited from caller.
3367 */
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003368static int mv_pci_init_one(struct pci_dev *pdev,
3369 const struct pci_device_id *ent)
Brett Russ20f733e2005-09-01 18:26:17 -04003370{
Jeff Garzik2dcb4072007-10-19 06:42:56 -04003371 static int printed_version;
Brett Russ20f733e2005-09-01 18:26:17 -04003372 unsigned int board_idx = (unsigned int)ent->driver_data;
Tejun Heo4447d352007-04-17 23:44:08 +09003373 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3374 struct ata_host *host;
3375 struct mv_host_priv *hpriv;
3376 int n_ports, rc;
Brett Russ20f733e2005-09-01 18:26:17 -04003377
Jeff Garzika9524a72005-10-30 14:39:11 -05003378 if (!printed_version++)
3379 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
Brett Russ20f733e2005-09-01 18:26:17 -04003380
Tejun Heo4447d352007-04-17 23:44:08 +09003381 /* allocate host */
3382 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3383
3384 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3385 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3386 if (!host || !hpriv)
3387 return -ENOMEM;
3388 host->private_data = hpriv;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003389 hpriv->n_ports = n_ports;
Tejun Heo4447d352007-04-17 23:44:08 +09003390
3391 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09003392 rc = pcim_enable_device(pdev);
3393 if (rc)
Brett Russ20f733e2005-09-01 18:26:17 -04003394 return rc;
Brett Russ20f733e2005-09-01 18:26:17 -04003395
Tejun Heo0d5ff562007-02-01 15:06:36 +09003396 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3397 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09003398 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09003399 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09003400 return rc;
Tejun Heo4447d352007-04-17 23:44:08 +09003401 host->iomap = pcim_iomap_table(pdev);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003402 hpriv->base = host->iomap[MV_PRIMARY_BAR];
Brett Russ20f733e2005-09-01 18:26:17 -04003403
Jeff Garzikd88184f2007-02-26 01:26:06 -05003404 rc = pci_go_64(pdev);
3405 if (rc)
3406 return rc;
3407
Mark Lordda2fa9b2008-01-26 18:32:45 -05003408 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3409 if (rc)
3410 return rc;
3411
Brett Russ20f733e2005-09-01 18:26:17 -04003412 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09003413 rc = mv_init_host(host, board_idx);
Tejun Heo24dc5f32007-01-20 16:00:28 +09003414 if (rc)
3415 return rc;
Brett Russ20f733e2005-09-01 18:26:17 -04003416
Brett Russ31961942005-09-30 01:36:00 -04003417 /* Enable interrupts */
Tejun Heo6a59dcf2007-02-24 15:12:31 +09003418 if (msi && pci_enable_msi(pdev))
Brett Russ31961942005-09-30 01:36:00 -04003419 pci_intx(pdev, 1);
Brett Russ20f733e2005-09-01 18:26:17 -04003420
Brett Russ31961942005-09-30 01:36:00 -04003421 mv_dump_pci_cfg(pdev, 0x68);
Tejun Heo4447d352007-04-17 23:44:08 +09003422 mv_print_info(host);
Brett Russ20f733e2005-09-01 18:26:17 -04003423
Tejun Heo4447d352007-04-17 23:44:08 +09003424 pci_set_master(pdev);
Jeff Garzikea8b4db2007-07-17 02:21:50 -04003425 pci_try_set_mwi(pdev);
Tejun Heo4447d352007-04-17 23:44:08 +09003426 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
Jeff Garzikc5d3e452007-07-11 18:30:50 -04003427 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
Brett Russ20f733e2005-09-01 18:26:17 -04003428}
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003429#endif
Brett Russ20f733e2005-09-01 18:26:17 -04003430
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003431static int mv_platform_probe(struct platform_device *pdev);
3432static int __devexit mv_platform_remove(struct platform_device *pdev);
3433
Brett Russ20f733e2005-09-01 18:26:17 -04003434static int __init mv_init(void)
3435{
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003436 int rc = -ENODEV;
3437#ifdef CONFIG_PCI
3438 rc = pci_register_driver(&mv_pci_driver);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003439 if (rc < 0)
3440 return rc;
3441#endif
3442 rc = platform_driver_register(&mv_platform_driver);
3443
3444#ifdef CONFIG_PCI
3445 if (rc < 0)
3446 pci_unregister_driver(&mv_pci_driver);
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003447#endif
3448 return rc;
Brett Russ20f733e2005-09-01 18:26:17 -04003449}
3450
3451static void __exit mv_exit(void)
3452{
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003453#ifdef CONFIG_PCI
Brett Russ20f733e2005-09-01 18:26:17 -04003454 pci_unregister_driver(&mv_pci_driver);
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003455#endif
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003456 platform_driver_unregister(&mv_platform_driver);
Brett Russ20f733e2005-09-01 18:26:17 -04003457}
3458
3459MODULE_AUTHOR("Brett Russ");
3460MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3461MODULE_LICENSE("GPL");
3462MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3463MODULE_VERSION(DRV_VERSION);
Mark Lord17c5aab2008-04-16 14:56:51 -04003464MODULE_ALIAS("platform:" DRV_NAME);
Brett Russ20f733e2005-09-01 18:26:17 -04003465
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003466#ifdef CONFIG_PCI
Jeff Garzikddef9bb2006-02-02 16:17:06 -05003467module_param(msi, int, 0444);
3468MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003469#endif
Jeff Garzikddef9bb2006-02-02 16:17:06 -05003470
Brett Russ20f733e2005-09-01 18:26:17 -04003471module_init(mv_init);
3472module_exit(mv_exit);