blob: 7e327309cf69f612b05cdb1544ff5c4deba9f68e [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
David Brownell75862692005-09-23 17:14:37 -070010 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 */
13
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/types.h>
15#include <linux/kernel.h>
Paul Gortmaker363c75d2011-05-27 09:37:25 -040016#include <linux/export.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/pci.h>
18#include <linux/init.h>
19#include <linux/delay.h>
Len Brown25be5e62005-05-27 04:21:50 -040020#include <linux/acpi.h>
bjorn.helgaas@hp.com9f23ed32007-12-17 14:09:38 -070021#include <linux/kallsyms.h>
Andreas Petlund75e07fc2008-11-20 20:42:25 -080022#include <linux/dmi.h>
Alexander Duyck649426e2009-03-05 13:57:28 -050023#include <linux/pci-aspm.h>
Yuji Shimada32a9a6822009-03-16 17:13:39 +090024#include <linux/ioport.h>
Arjan van de Ven32098742012-01-30 20:52:07 -080025#include <linux/sched.h>
26#include <linux/ktime.h>
Douglas Lehr9fe373f2014-08-21 09:26:52 +100027#include <linux/mm.h>
Rafael J. Wysocki93177a72010-01-02 22:57:24 +010028#include <asm/dma.h> /* isa_dma_bridge_buggy */
Greg KHbc56b9e2005-04-08 14:53:31 +090029#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
Yuji Shimada32a9a6822009-03-16 17:13:39 +090031/*
Jacob Pan253d2e52010-07-16 10:19:22 -070032 * Decoding should be disabled for a PCI device during BAR sizing to avoid
33 * conflict. But doing so may cause problems on host bridge and perhaps other
34 * key system devices. For devices that need to have mmio decoding always-on,
35 * we need to set the dev->mmio_always_on bit.
36 */
Bill Pemberton15856ad2012-11-21 15:35:00 -050037static void quirk_mmio_always_on(struct pci_dev *dev)
Jacob Pan253d2e52010-07-16 10:19:22 -070038{
Yinghai Lu52d21b52012-02-23 23:46:53 -080039 dev->mmio_always_on = 1;
Jacob Pan253d2e52010-07-16 10:19:22 -070040}
Yinghai Lu52d21b52012-02-23 23:46:53 -080041DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
42 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
Jacob Pan253d2e52010-07-16 10:19:22 -070043
Doug Thompsonbd8481e2006-05-08 17:06:09 -070044/* The Mellanox Tavor device gives false positive parity errors
45 * Mark this device with a broken_parity_status, to allow
46 * PCI scanning code to "skip" this now blacklisted device.
47 */
Bill Pemberton15856ad2012-11-21 15:35:00 -050048static void quirk_mellanox_tavor(struct pci_dev *dev)
Doug Thompsonbd8481e2006-05-08 17:06:09 -070049{
50 dev->broken_parity_status = 1; /* This device gives false positives */
51}
Ryan Desfosses3c78bc62014-04-18 20:13:49 -040052DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
53DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
Doug Thompsonbd8481e2006-05-08 17:06:09 -070054
Bjorn Helgaasf7625982013-11-14 11:28:18 -070055/* Deal with broken BIOSes that neglect to enable passive release,
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 which can cause problems in combination with the 82441FX/PPro MTRRs */
Alan Cox1597cac2006-12-04 15:14:45 -080057static void quirk_passive_release(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070058{
59 struct pci_dev *d = NULL;
60 unsigned char dlc;
61
62 /* We have to make sure a particular bit is set in the PIIX3
63 ISA bridge, so we have to go out and find it. */
64 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
65 pci_read_config_byte(d, 0x82, &dlc);
66 if (!(dlc & 1<<1)) {
Adam Jackson999da9f2008-12-01 14:30:29 -080067 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070068 dlc |= 1<<1;
69 pci_write_config_byte(d, 0x82, dlc);
70 }
71 }
72}
Andrew Morton652c5382007-11-21 15:07:13 -080073DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
74DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
Linus Torvalds1da177e2005-04-16 15:20:36 -070075
76/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
77 but VIA don't answer queries. If you happen to have good contacts at VIA
Bjorn Helgaasf7625982013-11-14 11:28:18 -070078 ask them for me please -- Alan
79
80 This appears to be BIOS not version dependent. So presumably there is a
Linus Torvalds1da177e2005-04-16 15:20:36 -070081 chipset level fix */
Bjorn Helgaasf7625982013-11-14 11:28:18 -070082
Bill Pemberton15856ad2012-11-21 15:35:00 -050083static void quirk_isa_dma_hangs(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070084{
85 if (!isa_dma_bridge_buggy) {
Ryan Desfosses3c78bc62014-04-18 20:13:49 -040086 isa_dma_bridge_buggy = 1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -070087 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070088 }
89}
90 /*
91 * Its not totally clear which chipsets are the problematic ones
92 * We know 82C586 and 82C596 variants are affected.
93 */
Andrew Morton652c5382007-11-21 15:07:13 -080094DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
95DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
96DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
Bjorn Helgaasf7625982013-11-14 11:28:18 -070097DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
Andrew Morton652c5382007-11-21 15:07:13 -080098DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102/*
Len Brown4731fdc2010-09-24 21:02:27 -0400103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
104 * for some HT machines to use C4 w/o hanging.
105 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500106static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
Len Brown4731fdc2010-09-24 21:02:27 -0400107{
108 u32 pmbase;
109 u16 pm1a;
110
111 pci_read_config_dword(dev, 0x40, &pmbase);
112 pmbase = pmbase & 0xff80;
113 pm1a = inw(pmbase);
114
115 if (pm1a & 0x10) {
116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
117 outw(0x10, pmbase);
118 }
119}
120DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
121
122/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123 * Chipsets where PCI->PCI transfers vanish or hang
124 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500125static void quirk_nopcipci(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400127 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700128 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129 pci_pci_problems |= PCIPCI_FAIL;
130 }
131}
Andrew Morton652c5382007-11-21 15:07:13 -0800132DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
133DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
Alan Cox236561e2006-09-30 23:27:03 -0700134
Bill Pemberton15856ad2012-11-21 15:35:00 -0500135static void quirk_nopciamd(struct pci_dev *dev)
Alan Cox236561e2006-09-30 23:27:03 -0700136{
137 u8 rev;
138 pci_read_config_byte(dev, 0x08, &rev);
139 if (rev == 0x13) {
140 /* Erratum 24 */
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700141 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
Alan Cox236561e2006-09-30 23:27:03 -0700142 pci_pci_problems |= PCIAGP_FAIL;
143 }
144}
Andrew Morton652c5382007-11-21 15:07:13 -0800145DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146
147/*
148 * Triton requires workarounds to be used by the drivers
149 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500150static void quirk_triton(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400152 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700153 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154 pci_pci_problems |= PCIPCI_TRITON;
155 }
156}
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161
162/*
163 * VIA Apollo KT133 needs PCI latency patch
164 * Made according to a windows driver based patch by George E. Breese
165 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400166 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
167 * the info on which Mr Breese based his work.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168 *
169 * Updated based on further information from the site and also on
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700170 * information provided by VIA
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171 */
Alan Cox1597cac2006-12-04 15:14:45 -0800172static void quirk_vialatency(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173{
174 struct pci_dev *p;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175 u8 busarb;
176 /* Ok we have a potential problem chipset here. Now see if we have
177 a buggy southbridge */
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700178
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400180 if (p != NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
182 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700183 if (p->revision < 0x40 || p->revision > 0x42)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184 goto exit;
185 } else {
186 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400187 if (p == NULL) /* No problem parts */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188 goto exit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700190 if (p->revision < 0x10 || p->revision > 0x12)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191 goto exit;
192 }
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700193
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194 /*
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700195 * Ok we have the problem. Now set the PCI master grant to
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196 * occur every master grant. The apparent bug is that under high
197 * PCI load (quite common in Linux of course) you can get data
198 * loss when the CPU is held off the bus for 3 bus master requests
199 * This happens to include the IDE controllers....
200 *
201 * VIA only apply this fix when an SB Live! is present but under
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300202 * both Linux and Windows this isn't enough, and we have seen
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203 * corruption without SB Live! but with things like 3 UDMA IDE
204 * controllers. So we ignore that bit of the VIA recommendation..
205 */
206
207 pci_read_config_byte(dev, 0x76, &busarb);
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700208 /* Set bit 4 and bi 5 of byte 76 to 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209 "Master priority rotation on every PCI master grant */
210 busarb &= ~(1<<5);
211 busarb |= (1<<4);
212 pci_write_config_byte(dev, 0x76, busarb);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700213 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214exit:
215 pci_dev_put(p);
216}
Andrew Morton652c5382007-11-21 15:07:13 -0800217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Alan Cox1597cac2006-12-04 15:14:45 -0800220/* Must restore this on a resume from RAM */
Andrew Morton652c5382007-11-21 15:07:13 -0800221DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
222DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
223DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224
225/*
226 * VIA Apollo VP3 needs ETBF on BT848/878
227 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500228static void quirk_viaetbf(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400230 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700231 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232 pci_pci_problems |= PCIPCI_VIAETBF;
233 }
234}
Andrew Morton652c5382007-11-21 15:07:13 -0800235DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236
Bill Pemberton15856ad2012-11-21 15:35:00 -0500237static void quirk_vsfx(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400239 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700240 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241 pci_pci_problems |= PCIPCI_VSFX;
242 }
243}
Andrew Morton652c5382007-11-21 15:07:13 -0800244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245
246/*
247 * Ali Magik requires workarounds to be used by the drivers
248 * that DMA to AGP space. Latency must be set to 0xA and triton
249 * workaround applied too
250 * [Info kindly provided by ALi]
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700251 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500252static void quirk_alimagik(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400254 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700255 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
257 }
258}
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700259DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261
262/*
263 * Natoma has some interesting boundary conditions with Zoran stuff
264 * at least
265 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500266static void quirk_natoma(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400268 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700269 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270 pci_pci_problems |= PCIPCI_NATOMA;
271 }
272}
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700273DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
274DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
275DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
276DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279
280/*
281 * This chip can cause PCI parity errors if config register 0xA0 is read
282 * while DMAs are occurring.
283 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500284static void quirk_citrine(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285{
286 dev->cfg_size = 0xA0;
287}
Andrew Morton652c5382007-11-21 15:07:13 -0800288DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289
Douglas Lehr9fe373f2014-08-21 09:26:52 +1000290/* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
291static void quirk_extend_bar_to_page(struct pci_dev *dev)
292{
293 int i;
294
295 for (i = 0; i < PCI_STD_RESOURCE_END; i++) {
296 struct resource *r = &dev->resource[i];
297
298 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
299 r->end = PAGE_SIZE - 1;
300 r->start = 0;
301 r->flags |= IORESOURCE_UNSET;
302 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
303 i, r);
304 }
305 }
306}
307DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
308
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309/*
310 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
311 * If it's needed, re-allocate the region.
312 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500313static void quirk_s3_64M(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314{
315 struct resource *r = &dev->resource[0];
316
317 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
Bjorn Helgaasbd064f02014-02-26 11:25:58 -0700318 r->flags |= IORESOURCE_UNSET;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319 r->start = 0;
320 r->end = 0x3ffffff;
321 }
322}
Andrew Morton652c5382007-11-21 15:07:13 -0800323DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325
Myron Stowe06cf35f2015-02-03 16:01:24 -0700326static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
327 const char *name)
328{
329 u32 region;
330 struct pci_bus_region bus_region;
331 struct resource *res = dev->resource + pos;
332
333 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
334
335 if (!region)
336 return;
337
338 res->name = pci_name(dev);
339 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
340 res->flags |=
341 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
342 region &= ~(size - 1);
343
344 /* Convert from PCI bus to resource space */
345 bus_region.start = region;
346 bus_region.end = region + size - 1;
347 pcibios_bus_to_resource(dev->bus, res, &bus_region);
348
349 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
350 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
351}
352
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500353/*
354 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
355 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
356 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
357 * (which conflicts w/ BAR1's memory range).
Myron Stowe06cf35f2015-02-03 16:01:24 -0700358 *
359 * CS553x's ISA PCI BARs may also be read-only (ref:
360 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500361 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500362static void quirk_cs5536_vsa(struct pci_dev *dev)
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500363{
Myron Stowe06cf35f2015-02-03 16:01:24 -0700364 static char *name = "CS5536 ISA bridge";
365
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500366 if (pci_resource_len(dev, 0) != 8) {
Myron Stowe06cf35f2015-02-03 16:01:24 -0700367 quirk_io(dev, 0, 8, name); /* SMB */
368 quirk_io(dev, 1, 256, name); /* GPIO */
369 quirk_io(dev, 2, 64, name); /* MFGPT */
370 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
371 name);
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500372 }
373}
374DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
375
Yinghai Lu65195c72013-04-12 12:44:15 +0000376static void quirk_io_region(struct pci_dev *dev, int port,
377 unsigned size, int nr, const char *name)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378{
Yinghai Lu65195c72013-04-12 12:44:15 +0000379 u16 region;
380 struct pci_bus_region bus_region;
381 struct resource *res = dev->resource + nr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382
Yinghai Lu65195c72013-04-12 12:44:15 +0000383 pci_read_config_word(dev, port, &region);
384 region &= ~(size - 1);
David S. Miller085ae412005-08-08 13:19:08 -0700385
Yinghai Lu65195c72013-04-12 12:44:15 +0000386 if (!region)
387 return;
David S. Miller085ae412005-08-08 13:19:08 -0700388
Yinghai Lu65195c72013-04-12 12:44:15 +0000389 res->name = pci_name(dev);
390 res->flags = IORESOURCE_IO;
391
392 /* Convert from PCI bus to resource space */
393 bus_region.start = region;
394 bus_region.end = region + size - 1;
Yinghai Lufc279852013-12-09 22:54:40 -0800395 pcibios_bus_to_resource(dev->bus, res, &bus_region);
Yinghai Lu65195c72013-04-12 12:44:15 +0000396
397 if (!pci_claim_resource(dev, nr))
398 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
399}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400
401/*
402 * ATI Northbridge setups MCE the processor if you even
403 * read somewhere between 0x3b0->0x3bb or read 0x3d3
404 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500405static void quirk_ati_exploding_mce(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406{
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700407 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
409 request_region(0x3b0, 0x0C, "RadeonIGP");
410 request_region(0x3d3, 0x01, "RadeonIGP");
411}
Andrew Morton652c5382007-11-21 15:07:13 -0800412DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413
414/*
Huang Ruibe6646b2014-10-31 11:11:16 +0800415 * In the AMD NL platform, this device ([1022:7912]) has a class code of
416 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
417 * claim it.
418 * But the dwc3 driver is a more specific driver for this device, and we'd
419 * prefer to use it instead of xhci. To prevent xhci from claiming the
420 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
421 * defines as "USB device (not host controller)". The dwc3 driver can then
422 * claim it based on its Vendor and Device ID.
423 */
424static void quirk_amd_nl_class(struct pci_dev *pdev)
425{
Bjorn Helgaascd76d102015-06-19 15:28:31 -0500426 u32 class = pdev->class;
427
428 /* Use "USB Device (not host controller)" class */
429 pdev->class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe;
430 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
431 class, pdev->class);
Huang Ruibe6646b2014-10-31 11:11:16 +0800432}
433DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
434 quirk_amd_nl_class);
435
436/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700437 * Let's make the southbridge information explicit instead
438 * of having to worry about people probing the ACPI areas,
439 * for example.. (Yes, it happens, and if you read the wrong
440 * ACPI register it will put the machine to sleep with no
441 * way of waking it up again. Bummer).
442 *
443 * ALI M7101: Two IO regions pointed to by words at
444 * 0xE0 (64 bytes of ACPI registers)
445 * 0xE2 (32 bytes of SMB registers)
446 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500447static void quirk_ali7101_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448{
Yinghai Lu65195c72013-04-12 12:44:15 +0000449 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
450 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451}
Andrew Morton652c5382007-11-21 15:07:13 -0800452DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453
Linus Torvalds6693e742005-10-25 20:40:09 -0700454static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
455{
456 u32 devres;
457 u32 mask, size, base;
458
459 pci_read_config_dword(dev, port, &devres);
460 if ((devres & enable) != enable)
461 return;
462 mask = (devres >> 16) & 15;
463 base = devres & 0xffff;
464 size = 16;
465 for (;;) {
466 unsigned bit = size >> 1;
467 if ((bit & mask) == bit)
468 break;
469 size = bit;
470 }
471 /*
472 * For now we only print it out. Eventually we'll want to
473 * reserve it (at least if it's in the 0x1000+ range), but
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700474 * let's get enough confirmation reports first.
Linus Torvalds6693e742005-10-25 20:40:09 -0700475 */
476 base &= -size;
Ryan Desfosses227f0642014-04-18 20:13:50 -0400477 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
478 base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700479}
480
481static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
482{
483 u32 devres;
484 u32 mask, size, base;
485
486 pci_read_config_dword(dev, port, &devres);
487 if ((devres & enable) != enable)
488 return;
489 base = devres & 0xffff0000;
490 mask = (devres & 0x3f) << 16;
491 size = 128 << 16;
492 for (;;) {
493 unsigned bit = size >> 1;
494 if ((bit & mask) == bit)
495 break;
496 size = bit;
497 }
498 /*
499 * For now we only print it out. Eventually we'll want to
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700500 * reserve it, but let's get enough confirmation reports first.
Linus Torvalds6693e742005-10-25 20:40:09 -0700501 */
502 base &= -size;
Ryan Desfosses227f0642014-04-18 20:13:50 -0400503 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
504 base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700505}
506
Linus Torvalds1da177e2005-04-16 15:20:36 -0700507/*
508 * PIIX4 ACPI: Two IO regions pointed to by longwords at
509 * 0x40 (64 bytes of ACPI registers)
Linus Torvalds08db2a72005-10-30 14:40:07 -0800510 * 0x90 (16 bytes of SMB registers)
Linus Torvalds6693e742005-10-25 20:40:09 -0700511 * and a few strange programmable PIIX4 device resources.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700512 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500513static void quirk_piix4_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514{
Yinghai Lu65195c72013-04-12 12:44:15 +0000515 u32 res_a;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516
Yinghai Lu65195c72013-04-12 12:44:15 +0000517 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
518 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
Linus Torvalds6693e742005-10-25 20:40:09 -0700519
520 /* Device resource A has enables for some of the other ones */
521 pci_read_config_dword(dev, 0x5c, &res_a);
522
523 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
524 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
525
526 /* Device resource D is just bitfields for static resources */
527
528 /* Device 12 enabled? */
529 if (res_a & (1 << 29)) {
530 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
531 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
532 }
533 /* Device 13 enabled? */
534 if (res_a & (1 << 30)) {
535 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
536 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
537 }
538 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
539 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700540}
Andrew Morton652c5382007-11-21 15:07:13 -0800541DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
542DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700543
Jiri Slabycdb97552011-02-28 10:45:09 +0100544#define ICH_PMBASE 0x40
545#define ICH_ACPI_CNTL 0x44
546#define ICH4_ACPI_EN 0x10
547#define ICH6_ACPI_EN 0x80
548#define ICH4_GPIOBASE 0x58
549#define ICH4_GPIO_CNTL 0x5c
550#define ICH4_GPIO_EN 0x10
551#define ICH6_GPIOBASE 0x48
552#define ICH6_GPIO_CNTL 0x4c
553#define ICH6_GPIO_EN 0x10
554
Linus Torvalds1da177e2005-04-16 15:20:36 -0700555/*
556 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
557 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
558 * 0x58 (64 bytes of GPIO I/O space)
559 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500560static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561{
Jiri Slabycdb97552011-02-28 10:45:09 +0100562 u8 enable;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700563
Jiri Slaby87e3dc32011-02-28 10:45:10 +0100564 /*
565 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
566 * with low legacy (and fixed) ports. We don't know the decoding
567 * priority and can't tell whether the legacy device or the one created
568 * here is really at that address. This happens on boards with broken
569 * BIOSes.
570 */
571
Jiri Slabycdb97552011-02-28 10:45:09 +0100572 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
Yinghai Lu65195c72013-04-12 12:44:15 +0000573 if (enable & ICH4_ACPI_EN)
574 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
575 "ICH4 ACPI/GPIO/TCO");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700576
Jiri Slabycdb97552011-02-28 10:45:09 +0100577 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
Yinghai Lu65195c72013-04-12 12:44:15 +0000578 if (enable & ICH4_GPIO_EN)
579 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
580 "ICH4 GPIO");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700581}
Andrew Morton652c5382007-11-21 15:07:13 -0800582DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
583DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
584DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
585DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
586DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
587DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
588DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
589DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
590DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
591DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700592
Bill Pemberton15856ad2012-11-21 15:35:00 -0500593static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000594{
Jiri Slabycdb97552011-02-28 10:45:09 +0100595 u8 enable;
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000596
Jiri Slabycdb97552011-02-28 10:45:09 +0100597 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
Yinghai Lu65195c72013-04-12 12:44:15 +0000598 if (enable & ICH6_ACPI_EN)
599 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
600 "ICH6 ACPI/GPIO/TCO");
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000601
Jiri Slabycdb97552011-02-28 10:45:09 +0100602 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
Yinghai Lu65195c72013-04-12 12:44:15 +0000603 if (enable & ICH6_GPIO_EN)
604 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
605 "ICH6 GPIO");
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000606}
Linus Torvalds894886e2008-12-06 10:10:10 -0800607
Bill Pemberton15856ad2012-11-21 15:35:00 -0500608static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
Linus Torvalds894886e2008-12-06 10:10:10 -0800609{
610 u32 val;
611 u32 size, base;
612
613 pci_read_config_dword(dev, reg, &val);
614
615 /* Enabled? */
616 if (!(val & 1))
617 return;
618 base = val & 0xfffc;
619 if (dynsize) {
620 /*
621 * This is not correct. It is 16, 32 or 64 bytes depending on
622 * register D31:F0:ADh bits 5:4.
623 *
624 * But this gets us at least _part_ of it.
625 */
626 size = 16;
627 } else {
628 size = 128;
629 }
630 base &= ~(size-1);
631
632 /* Just print it out for now. We should reserve it after more debugging */
633 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
634}
635
Bill Pemberton15856ad2012-11-21 15:35:00 -0500636static void quirk_ich6_lpc(struct pci_dev *dev)
Linus Torvalds894886e2008-12-06 10:10:10 -0800637{
638 /* Shared ACPI/GPIO decode with all ICH6+ */
639 ich6_lpc_acpi_gpio(dev);
640
641 /* ICH6-specific generic IO decode */
642 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
643 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
644}
645DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
646DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
647
Bill Pemberton15856ad2012-11-21 15:35:00 -0500648static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
Linus Torvalds894886e2008-12-06 10:10:10 -0800649{
650 u32 val;
651 u32 mask, base;
652
653 pci_read_config_dword(dev, reg, &val);
654
655 /* Enabled? */
656 if (!(val & 1))
657 return;
658
659 /*
660 * IO base in bits 15:2, mask in bits 23:18, both
661 * are dword-based
662 */
663 base = val & 0xfffc;
664 mask = (val >> 16) & 0xfc;
665 mask |= 3;
666
667 /* Just print it out for now. We should reserve it after more debugging */
668 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
669}
670
671/* ICH7-10 has the same common LPC generic IO decode registers */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500672static void quirk_ich7_lpc(struct pci_dev *dev)
Linus Torvalds894886e2008-12-06 10:10:10 -0800673{
Jean Delvare5d9c0a72011-04-15 10:03:53 +0200674 /* We share the common ACPI/GPIO decode with ICH6 */
Linus Torvalds894886e2008-12-06 10:10:10 -0800675 ich6_lpc_acpi_gpio(dev);
676
677 /* And have 4 ICH7+ generic decodes */
678 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
679 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
680 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
681 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
682}
683DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
685DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
686DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
687DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
688DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
689DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
690DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
691DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
692DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
693DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
694DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
695DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000696
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697/*
698 * VIA ACPI: One IO region pointed to by longword at
699 * 0x48 or 0x20 (256 bytes of ACPI registers)
700 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500701static void quirk_vt82c586_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702{
Yinghai Lu65195c72013-04-12 12:44:15 +0000703 if (dev->revision & 0x10)
704 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
705 "vt82c586 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700706}
Andrew Morton652c5382007-11-21 15:07:13 -0800707DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700708
709/*
710 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
711 * 0x48 (256 bytes of ACPI registers)
712 * 0x70 (128 bytes of hardware monitoring register)
713 * 0x90 (16 bytes of SMB registers)
714 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500715static void quirk_vt82c686_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700717 quirk_vt82c586_acpi(dev);
718
Yinghai Lu65195c72013-04-12 12:44:15 +0000719 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
720 "vt82c686 HW-mon");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721
Yinghai Lu65195c72013-04-12 12:44:15 +0000722 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723}
Andrew Morton652c5382007-11-21 15:07:13 -0800724DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700725
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400726/*
727 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
728 * 0x88 (128 bytes of power management registers)
729 * 0xd0 (16 bytes of SMB registers)
730 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500731static void quirk_vt8235_acpi(struct pci_dev *dev)
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400732{
Yinghai Lu65195c72013-04-12 12:44:15 +0000733 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
734 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400735}
736DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
737
Gabe Black1f56f4a2009-10-06 09:19:45 -0500738/*
739 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
740 * Disable fast back-to-back on the secondary bus segment
741 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500742static void quirk_xio2000a(struct pci_dev *dev)
Gabe Black1f56f4a2009-10-06 09:19:45 -0500743{
744 struct pci_dev *pdev;
745 u16 command;
746
Ryan Desfosses227f0642014-04-18 20:13:50 -0400747 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
Gabe Black1f56f4a2009-10-06 09:19:45 -0500748 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
749 pci_read_config_word(pdev, PCI_COMMAND, &command);
750 if (command & PCI_COMMAND_FAST_BACK)
751 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
752 }
753}
754DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
755 quirk_xio2000a);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700756
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700757#ifdef CONFIG_X86_IO_APIC
Linus Torvalds1da177e2005-04-16 15:20:36 -0700758
759#include <asm/io_apic.h>
760
761/*
762 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
763 * devices to the external APIC.
764 *
765 * TODO: When we have device-specific interrupt routers,
766 * this code will go away from quirks.
767 */
Alan Cox1597cac2006-12-04 15:14:45 -0800768static void quirk_via_ioapic(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700769{
770 u8 tmp;
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700771
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772 if (nr_ioapics < 1)
773 tmp = 0; /* nothing routed to external APIC */
774 else
775 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700776
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700777 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778 tmp == 0 ? "Disa" : "Ena");
779
780 /* Offset 0x58: External APIC IRQ output control */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400781 pci_write_config_byte(dev, 0x58, tmp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700782}
Andrew Morton652c5382007-11-21 15:07:13 -0800783DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200784DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785
786/*
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700787 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
Karsten Wiesea1740912005-09-03 15:56:33 -0700788 * This leads to doubled level interrupt rates.
789 * Set this bit to get rid of cycle wastage.
790 * Otherwise uncritical.
791 */
Alan Cox1597cac2006-12-04 15:14:45 -0800792static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
Karsten Wiesea1740912005-09-03 15:56:33 -0700793{
794 u8 misc_control2;
795#define BYPASS_APIC_DEASSERT 8
796
797 pci_read_config_byte(dev, 0x5B, &misc_control2);
798 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700799 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
Karsten Wiesea1740912005-09-03 15:56:33 -0700800 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
801 }
802}
803DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200804DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Karsten Wiesea1740912005-09-03 15:56:33 -0700805
806/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807 * The AMD io apic can hang the box when an apic irq is masked.
808 * We check all revs >= B0 (yet not in the pre production!) as the bug
809 * is currently marked NoFix
810 *
811 * We have multiple reports of hangs with this chipset that went away with
Alan Cox236561e2006-09-30 23:27:03 -0700812 * noapic specified. For the moment we assume it's the erratum. We may be wrong
Linus Torvalds1da177e2005-04-16 15:20:36 -0700813 * of course. However the advice is demonstrably good even if so..
814 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500815static void quirk_amd_ioapic(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816{
Auke Kok44c10132007-06-08 15:46:36 -0700817 if (dev->revision >= 0x02) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700818 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
819 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700820 }
821}
Andrew Morton652c5382007-11-21 15:07:13 -0800822DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700823#endif /* CONFIG_X86_IO_APIC */
824
Peter Orubad556ad42007-05-15 13:59:13 +0200825/*
826 * Some settings of MMRBC can lead to data corruption so block changes.
827 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
828 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500829static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
Peter Orubad556ad42007-05-15 13:59:13 +0200830{
Auke Kokaa288d42007-08-27 16:17:47 -0700831 if (dev->subordinate && dev->revision <= 0x12) {
Ryan Desfosses227f0642014-04-18 20:13:50 -0400832 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
833 dev->revision);
Peter Orubad556ad42007-05-15 13:59:13 +0200834 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
835 }
836}
837DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700838
839/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840 * FIXME: it is questionable that quirk_via_acpi
841 * is needed. It shows up as an ISA bridge, and does not
842 * support the PCI_INTERRUPT_LINE register at all. Therefore
843 * it seems like setting the pci_dev's 'irq' to the
844 * value of the ACPI SCI interrupt is only done for convenience.
845 * -jgarzik
846 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500847static void quirk_via_acpi(struct pci_dev *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700848{
849 /*
850 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
851 */
852 u8 irq;
853 pci_read_config_byte(d, 0x42, &irq);
854 irq &= 0xf;
855 if (irq && (irq != 2))
856 d->irq = irq;
857}
Andrew Morton652c5382007-11-21 15:07:13 -0800858DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
859DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860
Daniel Drake09d60292006-09-25 16:52:19 -0700861
862/*
Alan Cox1597cac2006-12-04 15:14:45 -0800863 * VIA bridges which have VLink
Daniel Drake09d60292006-09-25 16:52:19 -0700864 */
Alan Cox1597cac2006-12-04 15:14:45 -0800865
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800866static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
867
868static void quirk_via_bridge(struct pci_dev *dev)
869{
870 /* See what bridge we have and find the device ranges */
871 switch (dev->device) {
872 case PCI_DEVICE_ID_VIA_82C686:
Jean Delvarecb7468e2007-01-31 23:48:12 -0800873 /* The VT82C686 is special, it attaches to PCI and can have
874 any device number. All its subdevices are functions of
875 that single device. */
876 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
877 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800878 break;
879 case PCI_DEVICE_ID_VIA_8237:
880 case PCI_DEVICE_ID_VIA_8237A:
881 via_vlink_dev_lo = 15;
882 break;
883 case PCI_DEVICE_ID_VIA_8235:
884 via_vlink_dev_lo = 16;
885 break;
886 case PCI_DEVICE_ID_VIA_8231:
887 case PCI_DEVICE_ID_VIA_8233_0:
888 case PCI_DEVICE_ID_VIA_8233A:
889 case PCI_DEVICE_ID_VIA_8233C_0:
890 via_vlink_dev_lo = 17;
891 break;
892 }
893}
894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
895DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
896DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
897DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
898DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
899DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
900DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
901DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
Daniel Drake09d60292006-09-25 16:52:19 -0700902
Alan Cox1597cac2006-12-04 15:14:45 -0800903/**
904 * quirk_via_vlink - VIA VLink IRQ number update
905 * @dev: PCI device
906 *
907 * If the device we are dealing with is on a PIC IRQ we need to
908 * ensure that the IRQ line register which usually is not relevant
909 * for PCI cards, is actually written so that interrupts get sent
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800910 * to the right place.
911 * We only do this on systems where a VIA south bridge was detected,
912 * and only for VIA devices on the motherboard (see quirk_via_bridge
913 * above).
Alan Cox1597cac2006-12-04 15:14:45 -0800914 */
915
916static void quirk_via_vlink(struct pci_dev *dev)
Len Brown25be5e62005-05-27 04:21:50 -0400917{
918 u8 irq, new_irq;
919
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800920 /* Check if we have VLink at all */
921 if (via_vlink_dev_lo == -1)
Daniel Drake09d60292006-09-25 16:52:19 -0700922 return;
923
924 new_irq = dev->irq;
925
926 /* Don't quirk interrupts outside the legacy IRQ range */
927 if (!new_irq || new_irq > 15)
928 return;
929
Alan Cox1597cac2006-12-04 15:14:45 -0800930 /* Internal device ? */
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800931 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
932 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
Alan Cox1597cac2006-12-04 15:14:45 -0800933 return;
934
935 /* This is an internal VLink device on a PIC interrupt. The BIOS
936 ought to have set this but may not have, so we redo it */
937
Len Brown25be5e62005-05-27 04:21:50 -0400938 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
939 if (new_irq != irq) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700940 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
941 irq, new_irq);
Len Brown25be5e62005-05-27 04:21:50 -0400942 udelay(15); /* unknown if delay really needed */
943 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
944 }
945}
Alan Cox1597cac2006-12-04 15:14:45 -0800946DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
Len Brown25be5e62005-05-27 04:21:50 -0400947
Linus Torvalds1da177e2005-04-16 15:20:36 -0700948/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700949 * VIA VT82C598 has its device ID settable and many BIOSes
950 * set it to the ID of VT82C597 for backward compatibility.
951 * We need to switch it off to be able to recognize the real
952 * type of the chip.
953 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500954static void quirk_vt82c598_id(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700955{
956 pci_write_config_byte(dev, 0xfc, 0);
957 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
958}
Andrew Morton652c5382007-11-21 15:07:13 -0800959DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700960
961/*
962 * CardBus controllers have a legacy base address that enables them
963 * to respond as i82365 pcmcia controllers. We don't want them to
964 * do this even if the Linux CardBus driver is not loaded, because
965 * the Linux i82365 driver does not (and should not) handle CardBus.
966 */
Alan Cox1597cac2006-12-04 15:14:45 -0800967static void quirk_cardbus_legacy(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700968{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700969 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
970}
Yinghai Luae9de562012-02-23 23:46:54 -0800971DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
972 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
973DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
974 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700975
976/*
977 * Following the PCI ordering rules is optional on the AMD762. I'm not
978 * sure what the designers were smoking but let's not inhale...
979 *
980 * To be fair to AMD, it follows the spec by default, its BIOS people
981 * who turn it off!
982 */
Alan Cox1597cac2006-12-04 15:14:45 -0800983static void quirk_amd_ordering(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700984{
985 u32 pcic;
986 pci_read_config_dword(dev, 0x4C, &pcic);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400987 if ((pcic & 6) != 6) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700988 pcic |= 6;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700989 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700990 pci_write_config_dword(dev, 0x4C, pcic);
991 pci_read_config_dword(dev, 0x84, &pcic);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400992 pcic |= (1 << 23); /* Required in this mode */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700993 pci_write_config_dword(dev, 0x84, pcic);
994 }
995}
Andrew Morton652c5382007-11-21 15:07:13 -0800996DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200997DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700998
999/*
1000 * DreamWorks provided workaround for Dunord I-3000 problem
1001 *
1002 * This card decodes and responds to addresses not apparently
1003 * assigned to it. We force a larger allocation to ensure that
1004 * nothing gets put too close to it.
1005 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001006static void quirk_dunord(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001008 struct resource *r = &dev->resource[1];
Bjorn Helgaasbd064f02014-02-26 11:25:58 -07001009
1010 r->flags |= IORESOURCE_UNSET;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001011 r->start = 0;
1012 r->end = 0xffffff;
1013}
Andrew Morton652c5382007-11-21 15:07:13 -08001014DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015
1016/*
1017 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1018 * is subtractive decoding (transparent), and does indicate this
1019 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1020 * instead of 0x01.
1021 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001022static void quirk_transparent_bridge(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001023{
1024 dev->transparent = 1;
1025}
Andrew Morton652c5382007-11-21 15:07:13 -08001026DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1027DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001028
1029/*
1030 * Common misconfiguration of the MediaGX/Geode PCI master that will
1031 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
Justin P. Mattock631dd1a2010-10-18 11:03:14 +02001032 * datasheets found at http://www.national.com/analog for info on what
Linus Torvalds1da177e2005-04-16 15:20:36 -07001033 * these bits do. <christer@weinigel.se>
1034 */
Alan Cox1597cac2006-12-04 15:14:45 -08001035static void quirk_mediagx_master(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001036{
1037 u8 reg;
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001038
Linus Torvalds1da177e2005-04-16 15:20:36 -07001039 pci_read_config_byte(dev, 0x41, &reg);
1040 if (reg & 2) {
1041 reg &= ~2;
Ryan Desfosses227f0642014-04-18 20:13:50 -04001042 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1043 reg);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001044 pci_write_config_byte(dev, 0x41, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001045 }
1046}
Andrew Morton652c5382007-11-21 15:07:13 -08001047DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1048DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001049
1050/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051 * Ensure C0 rev restreaming is off. This is normally done by
1052 * the BIOS but in the odd case it is not the results are corruption
1053 * hence the presence of a Linux check
1054 */
Alan Cox1597cac2006-12-04 15:14:45 -08001055static void quirk_disable_pxb(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001056{
1057 u16 config;
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001058
Auke Kok44c10132007-06-08 15:46:36 -07001059 if (pdev->revision != 0x04) /* Only C0 requires this */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001060 return;
1061 pci_read_config_word(pdev, 0x40, &config);
1062 if (config & (1<<6)) {
1063 config &= ~(1<<6);
1064 pci_write_config_word(pdev, 0x40, config);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001065 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001066 }
1067}
Andrew Morton652c5382007-11-21 15:07:13 -08001068DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001069DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001070
Myron Stowe25e742b2012-07-09 15:36:14 -06001071static void quirk_amd_ide_mode(struct pci_dev *pdev)
Conke Huab174432006-12-19 13:11:37 -08001072{
Shane Huang5deab532009-10-13 11:14:00 +08001073 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
Crane Cai05a7d222008-02-02 13:56:56 +08001074 u8 tmp;
Conke Huab174432006-12-19 13:11:37 -08001075
Crane Cai05a7d222008-02-02 13:56:56 +08001076 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1077 if (tmp == 0x01) {
Conke Huab174432006-12-19 13:11:37 -08001078 pci_read_config_byte(pdev, 0x40, &tmp);
1079 pci_write_config_byte(pdev, 0x40, tmp|1);
1080 pci_write_config_byte(pdev, 0x9, 1);
1081 pci_write_config_byte(pdev, 0xa, 6);
1082 pci_write_config_byte(pdev, 0x40, tmp);
1083
Conke Huc9f89472007-01-09 05:32:51 -05001084 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
Crane Cai05a7d222008-02-02 13:56:56 +08001085 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
Conke Huab174432006-12-19 13:11:37 -08001086 }
1087}
Crane Cai05a7d222008-02-02 13:56:56 +08001088DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001089DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Crane Cai05a7d222008-02-02 13:56:56 +08001090DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001091DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Shane Huang5deab532009-10-13 11:14:00 +08001092DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1093DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
Shane Huangfafe5c3d82013-06-03 18:24:10 +08001094DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1095DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
Conke Huab174432006-12-19 13:11:37 -08001096
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097/*
1098 * Serverworks CSB5 IDE does not fully support native mode
1099 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001100static void quirk_svwks_csb5ide(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001101{
1102 u8 prog;
1103 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1104 if (prog & 5) {
1105 prog &= ~5;
1106 pdev->class &= ~5;
1107 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Alan Cox368c73d2006-10-04 00:41:26 +01001108 /* PCI layer will sort out resources */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001109 }
1110}
Andrew Morton652c5382007-11-21 15:07:13 -08001111DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001112
1113/*
1114 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1115 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001116static void quirk_ide_samemode(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001117{
1118 u8 prog;
1119
1120 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1121
1122 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001123 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001124 prog &= ~5;
1125 pdev->class &= ~5;
1126 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001127 }
1128}
Alan Cox368c73d2006-10-04 00:41:26 +01001129DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001130
Alan Cox979b1792008-07-24 17:18:38 +01001131/*
1132 * Some ATA devices break if put into D3
1133 */
1134
Bill Pemberton15856ad2012-11-21 15:35:00 -05001135static void quirk_no_ata_d3(struct pci_dev *pdev)
Alan Cox979b1792008-07-24 17:18:38 +01001136{
Yinghai Lufaa738b2012-02-23 23:46:55 -08001137 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
Alan Cox979b1792008-07-24 17:18:38 +01001138}
Yinghai Lufaa738b2012-02-23 23:46:55 -08001139/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1140DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1141 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1142DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1143 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
Alan Cox7a661c62009-06-24 16:02:27 +01001144/* ALi loses some register settings that we cannot then restore */
Yinghai Lufaa738b2012-02-23 23:46:55 -08001145DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1146 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
Alan Cox7a661c62009-06-24 16:02:27 +01001147/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1148 occur when mode detecting */
Yinghai Lufaa738b2012-02-23 23:46:55 -08001149DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1150 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
Alan Cox979b1792008-07-24 17:18:38 +01001151
Linus Torvalds1da177e2005-04-16 15:20:36 -07001152/* This was originally an Alpha specific thing, but it really fits here.
1153 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1154 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001155static void quirk_eisa_bridge(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001156{
1157 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1158}
Andrew Morton652c5382007-11-21 15:07:13 -08001159DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001160
Johannes Goecke7daa0c42006-04-20 02:43:17 -07001161
1162/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001163 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1164 * is not activated. The myth is that Asus said that they do not want the
1165 * users to be irritated by just another PCI Device in the Win98 device
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001166 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
Linus Torvalds1da177e2005-04-16 15:20:36 -07001167 * package 2.7.0 for details)
1168 *
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001169 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1170 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001171 * becomes necessary to do this tweak in two steps -- the chosen trigger
1172 * is either the Host bridge (preferred) or on-board VGA controller.
Jean Delvare9208ee82007-03-24 16:56:44 +01001173 *
1174 * Note that we used to unhide the SMBus that way on Toshiba laptops
1175 * (Satellite A40 and Tecra M2) but then found that the thermal management
1176 * was done by SMM code, which could cause unsynchronized concurrent
1177 * accesses to the SMBus registers, with potentially bad effects. Thus you
1178 * should be very careful when adding new entries: if SMM is accessing the
1179 * Intel SMBus, this is a very good reason to leave it hidden.
Jean Delvarea99acc82008-03-28 14:16:04 -07001180 *
1181 * Likewise, many recent laptops use ACPI for thermal management. If the
1182 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1183 * natively, and keeping the SMBus hidden is the right thing to do. If you
1184 * are about to add an entry in the table below, please first disassemble
1185 * the DSDT and double-check that there is no code accessing the SMBus.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001186 */
Vivek Goyal9d24a812007-01-11 01:52:44 +01001187static int asus_hides_smbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001188
Bill Pemberton15856ad2012-11-21 15:35:00 -05001189static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001190{
1191 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1192 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001193 switch (dev->subsystem_device) {
Jean Delvarea00db372005-06-29 17:04:06 +02001194 case 0x8025: /* P4B-LX */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001195 case 0x8070: /* P4B */
1196 case 0x8088: /* P4B533 */
1197 case 0x1626: /* L3C notebook */
1198 asus_hides_smbus = 1;
1199 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001200 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001201 switch (dev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001202 case 0x80b1: /* P4GE-V */
1203 case 0x80b2: /* P4PE */
1204 case 0x8093: /* P4B533-V */
1205 asus_hides_smbus = 1;
1206 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001207 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001208 switch (dev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001209 case 0x8030: /* P4T533 */
1210 asus_hides_smbus = 1;
1211 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001212 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001213 switch (dev->subsystem_device) {
1214 case 0x8070: /* P4G8X Deluxe */
1215 asus_hides_smbus = 1;
1216 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001217 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
Jean Delvare321311a2006-07-31 08:53:15 +02001218 switch (dev->subsystem_device) {
1219 case 0x80c9: /* PU-DLS */
1220 asus_hides_smbus = 1;
1221 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001222 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001223 switch (dev->subsystem_device) {
1224 case 0x1751: /* M2N notebook */
1225 case 0x1821: /* M5N notebook */
Mats Erik Andersson4096ed02009-05-12 12:05:23 +02001226 case 0x1897: /* A6L notebook */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001227 asus_hides_smbus = 1;
1228 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001229 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001230 switch (dev->subsystem_device) {
1231 case 0x184b: /* W1N notebook */
1232 case 0x186a: /* M6Ne notebook */
1233 asus_hides_smbus = 1;
1234 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001235 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Jean Delvare2e457852007-01-05 09:17:56 +01001236 switch (dev->subsystem_device) {
1237 case 0x80f2: /* P4P800-X */
1238 asus_hides_smbus = 1;
1239 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001240 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001241 switch (dev->subsystem_device) {
1242 case 0x1882: /* M6V notebook */
Jean Delvare2d1e1c72006-04-01 16:46:35 +02001243 case 0x1977: /* A6VA notebook */
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001244 asus_hides_smbus = 1;
1245 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001246 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1247 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001248 switch (dev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001249 case 0x088C: /* HP Compaq nc8000 */
1250 case 0x0890: /* HP Compaq nc6000 */
1251 asus_hides_smbus = 1;
1252 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001253 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001254 switch (dev->subsystem_device) {
1255 case 0x12bc: /* HP D330L */
Jean Delvaree3b1bd52005-09-21 22:26:31 +02001256 case 0x12bd: /* HP D530 */
Michal Miroslaw74c57422009-05-12 13:49:25 -07001257 case 0x006a: /* HP Compaq nx9500 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001258 asus_hides_smbus = 1;
1259 }
Jean Delvare677cc642007-11-21 18:29:06 +01001260 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1261 switch (dev->subsystem_device) {
1262 case 0x12bf: /* HP xw4100 */
1263 asus_hides_smbus = 1;
1264 }
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001265 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1266 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1267 switch (dev->subsystem_device) {
1268 case 0xC00C: /* Samsung P35 notebook */
1269 asus_hides_smbus = 1;
1270 }
Rumen Ivanov Zarevc87f8832005-09-06 13:39:32 -07001271 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1272 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001273 switch (dev->subsystem_device) {
Rumen Ivanov Zarevc87f8832005-09-06 13:39:32 -07001274 case 0x0058: /* Compaq Evo N620c */
1275 asus_hides_smbus = 1;
1276 }
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001277 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001278 switch (dev->subsystem_device) {
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001279 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1280 /* Motherboard doesn't have Host bridge
1281 * subvendor/subdevice IDs, therefore checking
1282 * its on-board VGA controller */
1283 asus_hides_smbus = 1;
1284 }
David O'Shea8293b0f2009-03-02 09:51:13 +01001285 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001286 switch (dev->subsystem_device) {
Jean Delvare10260d92008-06-04 13:53:31 +02001287 case 0x00b8: /* Compaq Evo D510 CMT */
1288 case 0x00b9: /* Compaq Evo D510 SFF */
Jean Delvare6b5096e2009-07-28 11:49:19 +02001289 case 0x00ba: /* Compaq Evo D510 USDT */
David O'Shea8293b0f2009-03-02 09:51:13 +01001290 /* Motherboard doesn't have Host bridge
1291 * subvendor/subdevice IDs and on-board VGA
1292 * controller is disabled if an AGP card is
1293 * inserted, therefore checking USB UHCI
1294 * Controller #1 */
Jean Delvare10260d92008-06-04 13:53:31 +02001295 asus_hides_smbus = 1;
1296 }
Krzysztof Helt27e46852008-06-08 13:47:02 +02001297 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1298 switch (dev->subsystem_device) {
1299 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1300 /* Motherboard doesn't have host bridge
1301 * subvendor/subdevice IDs, therefore checking
1302 * its on-board VGA controller */
1303 asus_hides_smbus = 1;
1304 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001305 }
1306}
Andrew Morton652c5382007-11-21 15:07:13 -08001307DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1309DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1310DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
Jean Delvare677cc642007-11-21 18:29:06 +01001311DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
Andrew Morton652c5382007-11-21 15:07:13 -08001312DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1313DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1314DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1315DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1316DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001317
Andrew Morton652c5382007-11-21 15:07:13 -08001318DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
David O'Shea8293b0f2009-03-02 09:51:13 +01001319DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
Krzysztof Helt27e46852008-06-08 13:47:02 +02001320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001321
Alan Cox1597cac2006-12-04 15:14:45 -08001322static void asus_hides_smbus_lpc(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001323{
1324 u16 val;
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001325
Linus Torvalds1da177e2005-04-16 15:20:36 -07001326 if (likely(!asus_hides_smbus))
1327 return;
1328
1329 pci_read_config_word(dev, 0xF2, &val);
1330 if (val & 0x8) {
1331 pci_write_config_word(dev, 0xF2, val & (~0x8));
1332 pci_read_config_word(dev, 0xF2, &val);
1333 if (val & 0x8)
Ryan Desfosses227f0642014-04-18 20:13:50 -04001334 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1335 val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001336 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001337 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001338 }
1339}
Andrew Morton652c5382007-11-21 15:07:13 -08001340DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1341DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1342DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1343DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1344DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1345DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001347DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1348DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1349DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1350DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1351DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1352DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1353DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001354
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001355/* It appears we just have one such device. If not, we have a warning */
1356static void __iomem *asus_rcba_base;
1357static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001358{
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001359 u32 rcba;
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001360
1361 if (likely(!asus_hides_smbus))
1362 return;
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001363 WARN_ON(asus_rcba_base);
1364
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001365 pci_read_config_dword(dev, 0xF0, &rcba);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001366 /* use bits 31:14, 16 kB aligned */
1367 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1368 if (asus_rcba_base == NULL)
1369 return;
1370}
1371
1372static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1373{
1374 u32 val;
1375
1376 if (likely(!asus_hides_smbus || !asus_rcba_base))
1377 return;
1378 /* read the Function Disable register, dword mode only */
1379 val = readl(asus_rcba_base + 0x3418);
1380 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1381}
1382
1383static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1384{
1385 if (likely(!asus_hides_smbus || !asus_rcba_base))
1386 return;
1387 iounmap(asus_rcba_base);
1388 asus_rcba_base = NULL;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001389 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001390}
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001391
1392static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1393{
1394 asus_hides_smbus_lpc_ich6_suspend(dev);
1395 asus_hides_smbus_lpc_ich6_resume_early(dev);
1396 asus_hides_smbus_lpc_ich6_resume(dev);
1397}
Andrew Morton652c5382007-11-21 15:07:13 -08001398DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001399DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1400DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1401DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
Carl-Daniel Hailfingerce007ea2006-05-15 09:44:33 -07001402
Linus Torvalds1da177e2005-04-16 15:20:36 -07001403/*
1404 * SiS 96x south bridge: BIOS typically hides SMBus device...
1405 */
Alan Cox1597cac2006-12-04 15:14:45 -08001406static void quirk_sis_96x_smbus(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407{
1408 u8 val = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001409 pci_read_config_byte(dev, 0x77, &val);
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001410 if (val & 0x10) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001411 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001412 pci_write_config_byte(dev, 0x77, val & ~0x10);
1413 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001414}
Andrew Morton652c5382007-11-21 15:07:13 -08001415DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1416DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1417DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1418DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001419DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1420DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1421DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1422DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001423
Linus Torvalds1da177e2005-04-16 15:20:36 -07001424/*
1425 * ... This is further complicated by the fact that some SiS96x south
1426 * bridges pretend to be 85C503/5513 instead. In that case see if we
1427 * spotted a compatible north bridge to make sure.
1428 * (pci_find_device doesn't work yet)
1429 *
1430 * We can also enable the sis96x bit in the discovery register..
1431 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001432#define SIS_DETECT_REGISTER 0x40
1433
Alan Cox1597cac2006-12-04 15:14:45 -08001434static void quirk_sis_503(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001435{
1436 u8 reg;
1437 u16 devid;
1438
1439 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1440 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1441 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1442 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1443 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1444 return;
1445 }
1446
Linus Torvalds1da177e2005-04-16 15:20:36 -07001447 /*
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001448 * Ok, it now shows up as a 96x.. run the 96x quirk by
1449 * hand in case it has already been processed.
1450 * (depends on link order, which is apparently not guaranteed)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001451 */
1452 dev->device = devid;
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001453 quirk_sis_96x_smbus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001454}
Andrew Morton652c5382007-11-21 15:07:13 -08001455DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001456DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001457
Linus Torvalds1da177e2005-04-16 15:20:36 -07001458
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001459/*
1460 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1461 * and MC97 modem controller are disabled when a second PCI soundcard is
1462 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1463 * -- bjd
1464 */
Alan Cox1597cac2006-12-04 15:14:45 -08001465static void asus_hides_ac97_lpc(struct pci_dev *dev)
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001466{
1467 u8 val;
1468 int asus_hides_ac97 = 0;
1469
1470 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1471 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1472 asus_hides_ac97 = 1;
1473 }
1474
1475 if (!asus_hides_ac97)
1476 return;
1477
1478 pci_read_config_byte(dev, 0x50, &val);
1479 if (val & 0xc0) {
1480 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1481 pci_read_config_byte(dev, 0x50, &val);
1482 if (val & 0xc0)
Ryan Desfosses227f0642014-04-18 20:13:50 -04001483 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1484 val);
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001485 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001486 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001487 }
1488}
Andrew Morton652c5382007-11-21 15:07:13 -08001489DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001490DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Alan Cox1597cac2006-12-04 15:14:45 -08001491
Tejun Heo77967052006-08-19 03:54:39 +09001492#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
Alan Cox15e0c692006-07-12 15:05:41 +01001493
1494/*
1495 * If we are using libata we can drive this chip properly but must
1496 * do this early on to make the additional device appear during
1497 * the PCI scanning.
1498 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001499static void quirk_jmicron_ata(struct pci_dev *pdev)
Alan Cox15e0c692006-07-12 15:05:41 +01001500{
Tejun Heoe34bb372007-02-26 20:24:03 +09001501 u32 conf1, conf5, class;
Alan Cox15e0c692006-07-12 15:05:41 +01001502 u8 hdr;
1503
1504 /* Only poke fn 0 */
1505 if (PCI_FUNC(pdev->devfn))
1506 return;
1507
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001508 pci_read_config_dword(pdev, 0x40, &conf1);
1509 pci_read_config_dword(pdev, 0x80, &conf5);
Alan Cox15e0c692006-07-12 15:05:41 +01001510
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001511 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1512 conf5 &= ~(1 << 24); /* Clear bit 24 */
Alan Cox15e0c692006-07-12 15:05:41 +01001513
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001514 switch (pdev->device) {
Tejun Heo4daedcf2010-06-03 11:57:04 +02001515 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1516 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001517 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001518 /* The controller should be in single function ahci mode */
1519 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1520 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001521
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001522 case PCI_DEVICE_ID_JMICRON_JMB365:
1523 case PCI_DEVICE_ID_JMICRON_JMB366:
1524 /* Redirect IDE second PATA port to the right spot */
1525 conf5 |= (1 << 24);
1526 /* Fall through */
1527 case PCI_DEVICE_ID_JMICRON_JMB361:
1528 case PCI_DEVICE_ID_JMICRON_JMB363:
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001529 case PCI_DEVICE_ID_JMICRON_JMB369:
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001530 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1531 /* Set the class codes correctly and then direct IDE 0 */
Tejun Heo3a9e3a52007-10-23 15:27:31 +09001532 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001533 break;
1534
1535 case PCI_DEVICE_ID_JMICRON_JMB368:
1536 /* The controller should be in single function IDE mode */
1537 conf1 |= 0x00C00000; /* Set 22, 23 */
1538 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001539 }
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001540
1541 pci_write_config_dword(pdev, 0x40, conf1);
1542 pci_write_config_dword(pdev, 0x80, conf5);
1543
1544 /* Update pdev accordingly */
1545 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1546 pdev->hdr_type = hdr & 0x7f;
1547 pdev->multifunction = !!(hdr & 0x80);
Tejun Heoe34bb372007-02-26 20:24:03 +09001548
1549 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1550 pdev->class = class >> 8;
Alan Cox15e0c692006-07-12 15:05:41 +01001551}
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001552DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1553DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
Tejun Heo4daedcf2010-06-03 11:57:04 +02001554DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001555DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001556DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001557DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1558DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1559DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001560DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001561DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1562DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
Tejun Heo4daedcf2010-06-03 11:57:04 +02001563DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001564DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001565DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001566DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1567DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1568DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001569DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
Alan Cox15e0c692006-07-12 15:05:41 +01001570
1571#endif
1572
Zhang Rui91f15fb2015-08-24 15:27:11 -05001573static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1574{
1575 if (dev->multifunction) {
1576 device_disable_async_suspend(&dev->dev);
1577 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1578 }
1579}
1580DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1581DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1582DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1583DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1584
Linus Torvalds1da177e2005-04-16 15:20:36 -07001585#ifdef CONFIG_X86_IO_APIC
Bill Pemberton15856ad2012-11-21 15:35:00 -05001586static void quirk_alder_ioapic(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001587{
1588 int i;
1589
1590 if ((pdev->class >> 8) != 0xff00)
1591 return;
1592
1593 /* the first BAR is the location of the IO APIC...we must
1594 * not touch this (and it's already covered by the fixmap), so
1595 * forcibly insert it into the resource tree */
1596 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1597 insert_resource(&iomem_resource, &pdev->resource[0]);
1598
1599 /* The next five BARs all seem to be rubbish, so just clean
1600 * them out */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001601 for (i = 1; i < 6; i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001602 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001603}
Andrew Morton652c5382007-11-21 15:07:13 -08001604DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001605#endif
1606
Bill Pemberton15856ad2012-11-21 15:35:00 -05001607static void quirk_pcie_mch(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001608{
Eric W. Biederman0ba379e2009-09-06 21:48:35 -07001609 pdev->no_msi = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001610}
Andrew Morton652c5382007-11-21 15:07:13 -08001611DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1612DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001614
Kristen Accardi4602b882005-08-16 15:15:58 -07001615
1616/*
1617 * It's possible for the MSI to get corrupted if shpc and acpi
1618 * are used together on certain PXH-based systems.
1619 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001620static void quirk_pcie_pxh(struct pci_dev *dev)
Kristen Accardi4602b882005-08-16 15:15:58 -07001621{
Kristen Accardi4602b882005-08-16 15:15:58 -07001622 dev->no_msi = 1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001623 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
Kristen Accardi4602b882005-08-16 15:15:58 -07001624}
1625DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1626DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1627DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1628DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1629DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1630
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -07001631/*
1632 * Some Intel PCI Express chipsets have trouble with downstream
1633 * device power management.
1634 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001635static void quirk_intel_pcie_pm(struct pci_dev *dev)
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -07001636{
1637 pci_pm_d3_delay = 120;
1638 dev->no_d1d2 = 1;
1639}
1640
1641DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1642DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1643DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1644DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1645DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1646DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1647DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1648DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1649DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1650DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1651DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1652DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1653DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1654DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1655DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1656DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1657DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1658DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1659DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1660DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1661DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
Kristen Accardi4602b882005-08-16 15:15:58 -07001662
Stefan Assmann426b3b82008-06-11 16:35:16 +02001663#ifdef CONFIG_X86_IO_APIC
1664/*
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001665 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1666 * remap the original interrupt in the linux kernel to the boot interrupt, so
1667 * that a PCI device's interrupt handler is installed on the boot interrupt
1668 * line instead.
1669 */
1670static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1671{
Stefan Assmann41b9eb22008-07-15 13:48:55 +02001672 if (noioapicquirk || noioapicreroute)
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001673 return;
1674
1675 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001676 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1677 dev->vendor, dev->device);
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001678}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001679DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1680DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1681DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1682DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1683DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1684DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1685DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1686DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1687DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1688DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1689DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1690DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1691DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1692DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1693DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1694DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001695
1696/*
Stefan Assmann426b3b82008-06-11 16:35:16 +02001697 * On some chipsets we can disable the generation of legacy INTx boot
1698 * interrupts.
1699 */
1700
1701/*
1702 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1703 * 300641-004US, section 5.7.3.
1704 */
1705#define INTEL_6300_IOAPIC_ABAR 0x40
1706#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1707
1708static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1709{
1710 u16 pci_config_word;
1711
1712 if (noioapicquirk)
1713 return;
1714
1715 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1716 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1717 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1718
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001719 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1720 dev->vendor, dev->device);
Stefan Assmann426b3b82008-06-11 16:35:16 +02001721}
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001722DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1723DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
Olaf Dabrunz77251182008-07-08 15:59:47 +02001724
1725/*
1726 * disable boot interrupts on HT-1000
1727 */
1728#define BC_HT1000_FEATURE_REG 0x64
1729#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1730#define BC_HT1000_MAP_IDX 0xC00
1731#define BC_HT1000_MAP_DATA 0xC01
1732
1733static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1734{
1735 u32 pci_config_dword;
1736 u8 irq;
1737
1738 if (noioapicquirk)
1739 return;
1740
1741 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1742 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1743 BC_HT1000_PIC_REGS_ENABLE);
1744
1745 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1746 outb(irq, BC_HT1000_MAP_IDX);
1747 outb(0x00, BC_HT1000_MAP_DATA);
1748 }
1749
1750 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1751
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001752 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1753 dev->vendor, dev->device);
Olaf Dabrunz77251182008-07-08 15:59:47 +02001754}
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001755DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1756DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001757
1758/*
1759 * disable boot interrupts on AMD and ATI chipsets
1760 */
1761/*
1762 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1763 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1764 * (due to an erratum).
1765 */
1766#define AMD_813X_MISC 0x40
1767#define AMD_813X_NOIOAMODE (1<<0)
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001768#define AMD_813X_REV_B1 0x12
Stefan Assmannbbe19442009-02-26 10:46:48 -08001769#define AMD_813X_REV_B2 0x13
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001770
1771static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1772{
1773 u32 pci_config_dword;
1774
1775 if (noioapicquirk)
1776 return;
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001777 if ((dev->revision == AMD_813X_REV_B1) ||
1778 (dev->revision == AMD_813X_REV_B2))
Stefan Assmannbbe19442009-02-26 10:46:48 -08001779 return;
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001780
1781 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1782 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1783 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1784
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001785 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1786 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001787}
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001788DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1789DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1790DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1791DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001792
1793#define AMD_8111_PCI_IRQ_ROUTING 0x56
1794
1795static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1796{
1797 u16 pci_config_word;
1798
1799 if (noioapicquirk)
1800 return;
1801
1802 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1803 if (!pci_config_word) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04001804 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1805 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001806 return;
1807 }
1808 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001809 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1810 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001811}
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001812DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1813DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
Stefan Assmann426b3b82008-06-11 16:35:16 +02001814#endif /* CONFIG_X86_IO_APIC */
1815
Sergei Shtylyov33dced22007-02-07 18:18:45 +01001816/*
1817 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1818 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1819 * Re-allocate the region if needed...
1820 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001821static void quirk_tc86c001_ide(struct pci_dev *dev)
Sergei Shtylyov33dced22007-02-07 18:18:45 +01001822{
1823 struct resource *r = &dev->resource[0];
1824
1825 if (r->start & 0x8) {
Bjorn Helgaasbd064f02014-02-26 11:25:58 -07001826 r->flags |= IORESOURCE_UNSET;
Sergei Shtylyov33dced22007-02-07 18:18:45 +01001827 r->start = 0;
1828 r->end = 0xf;
1829 }
1830}
1831DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1832 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1833 quirk_tc86c001_ide);
1834
Ian Abbott21c5fd92012-10-30 17:25:53 +00001835/*
1836 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1837 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1838 * being read correctly if bit 7 of the base address is set.
1839 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1840 * Re-allocate the regions to a 256-byte boundary if necessary.
1841 */
Linus Torvalds193c0d62012-12-13 12:14:47 -08001842static void quirk_plx_pci9050(struct pci_dev *dev)
Ian Abbott21c5fd92012-10-30 17:25:53 +00001843{
1844 unsigned int bar;
1845
1846 /* Fixed in revision 2 (PCI 9052). */
1847 if (dev->revision >= 2)
1848 return;
1849 for (bar = 0; bar <= 1; bar++)
1850 if (pci_resource_len(dev, bar) == 0x80 &&
1851 (pci_resource_start(dev, bar) & 0x80)) {
1852 struct resource *r = &dev->resource[bar];
Ryan Desfosses227f0642014-04-18 20:13:50 -04001853 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
Ian Abbott21c5fd92012-10-30 17:25:53 +00001854 bar);
Bjorn Helgaasbd064f02014-02-26 11:25:58 -07001855 r->flags |= IORESOURCE_UNSET;
Ian Abbott21c5fd92012-10-30 17:25:53 +00001856 r->start = 0;
1857 r->end = 0xff;
1858 }
1859}
1860DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1861 quirk_plx_pci9050);
Ian Abbott2794bb22012-10-29 14:40:18 +00001862/*
1863 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1864 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1865 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1866 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1867 *
1868 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1869 * driver.
1870 */
1871DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1872DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
Ian Abbott21c5fd92012-10-30 17:25:53 +00001873
Bill Pemberton15856ad2012-11-21 15:35:00 -05001874static void quirk_netmos(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001875{
1876 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1877 unsigned int num_serial = dev->subsystem_device & 0xf;
1878
1879 /*
1880 * These Netmos parts are multiport serial devices with optional
1881 * parallel ports. Even when parallel ports are present, they
1882 * are identified as class SERIAL, which means the serial driver
1883 * will claim them. To prevent this, mark them as class OTHER.
1884 * These combo devices should be claimed by parport_serial.
1885 *
1886 * The subdevice ID is of the form 0x00PS, where <P> is the number
1887 * of parallel ports and <S> is the number of serial ports.
1888 */
1889 switch (dev->device) {
Jiri Slaby4c9c1682008-12-08 16:19:14 +01001890 case PCI_DEVICE_ID_NETMOS_9835:
1891 /* Well, this rule doesn't hold for the following 9835 device */
1892 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1893 dev->subsystem_device == 0x0299)
1894 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001895 case PCI_DEVICE_ID_NETMOS_9735:
1896 case PCI_DEVICE_ID_NETMOS_9745:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001897 case PCI_DEVICE_ID_NETMOS_9845:
1898 case PCI_DEVICE_ID_NETMOS_9855:
Yinghai Lu08803ef2012-02-23 23:46:56 -08001899 if (num_parallel) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04001900 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001901 dev->device, num_parallel, num_serial);
1902 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1903 (dev->class & 0xff);
1904 }
1905 }
1906}
Yinghai Lu08803ef2012-02-23 23:46:56 -08001907DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1908 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001909
Alex Williamsonda2d03e2015-09-15 22:24:46 -06001910/*
1911 * Quirk non-zero PCI functions to route VPD access through function 0 for
1912 * devices that share VPD resources between functions. The functions are
1913 * expected to be identical devices.
1914 */
Mark Rustad7aa6ca42015-07-13 11:40:07 -07001915static void quirk_f0_vpd_link(struct pci_dev *dev)
1916{
Alex Williamsonda2d03e2015-09-15 22:24:46 -06001917 struct pci_dev *f0;
1918
1919 if (!PCI_FUNC(dev->devfn))
Mark Rustad7aa6ca42015-07-13 11:40:07 -07001920 return;
Alex Williamsonda2d03e2015-09-15 22:24:46 -06001921
1922 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
1923 if (!f0)
1924 return;
1925
1926 if (f0->vpd && dev->class == f0->class &&
1927 dev->vendor == f0->vendor && dev->device == f0->device)
1928 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
1929
1930 pci_dev_put(f0);
Mark Rustad7aa6ca42015-07-13 11:40:07 -07001931}
1932DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1933 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
1934
Bill Pemberton15856ad2012-11-21 15:35:00 -05001935static void quirk_e100_interrupt(struct pci_dev *dev)
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001936{
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001937 u16 command, pmcsr;
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001938 u8 __iomem *csr;
1939 u8 cmd_hi;
1940
1941 switch (dev->device) {
1942 /* PCI IDs taken from drivers/net/e100.c */
1943 case 0x1029:
1944 case 0x1030 ... 0x1034:
1945 case 0x1038 ... 0x103E:
1946 case 0x1050 ... 0x1057:
1947 case 0x1059:
1948 case 0x1064 ... 0x106B:
1949 case 0x1091 ... 0x1095:
1950 case 0x1209:
1951 case 0x1229:
1952 case 0x2449:
1953 case 0x2459:
1954 case 0x245D:
1955 case 0x27DC:
1956 break;
1957 default:
1958 return;
1959 }
1960
1961 /*
1962 * Some firmware hands off the e100 with interrupts enabled,
1963 * which can cause a flood of interrupts if packets are
1964 * received before the driver attaches to the device. So
1965 * disable all e100 interrupts here. The driver will
1966 * re-enable them when it's ready.
1967 */
1968 pci_read_config_word(dev, PCI_COMMAND, &command);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001969
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10001970 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001971 return;
1972
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001973 /*
1974 * Check that the device is in the D0 power state. If it's not,
1975 * there is no point to look any further.
1976 */
Yijing Wang728cdb72013-06-18 16:22:14 +08001977 if (dev->pm_cap) {
1978 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001979 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1980 return;
1981 }
1982
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10001983 /* Convert from PCI bus to resource space. */
1984 csr = ioremap(pci_resource_start(dev, 0), 8);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001985 if (!csr) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001986 dev_warn(&dev->dev, "Can't map e100 registers\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001987 return;
1988 }
1989
1990 cmd_hi = readb(csr + 3);
1991 if (cmd_hi == 0) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04001992 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001993 writeb(1, csr + 3);
1994 }
1995
1996 iounmap(csr);
1997}
Yinghai Lu4c5b28e2012-02-23 23:46:57 -08001998DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1999 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03002000
Alexander Duyck649426e2009-03-05 13:57:28 -05002001/*
2002 * The 82575 and 82598 may experience data corruption issues when transitioning
2003 * out of L0S. To prevent this we need to disable L0S on the pci-e link
2004 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002005static void quirk_disable_aspm_l0s(struct pci_dev *dev)
Alexander Duyck649426e2009-03-05 13:57:28 -05002006{
2007 dev_info(&dev->dev, "Disabling L0s\n");
2008 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2009}
2010DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2011DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2012DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2013DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2014DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2015DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2016DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2017DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2018DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2019DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2020DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2021DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2022DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2023DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2024
Bill Pemberton15856ad2012-11-21 15:35:00 -05002025static void fixup_rev1_53c810(struct pci_dev *dev)
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03002026{
Bjorn Helgaase6323e32015-06-19 15:36:45 -05002027 u32 class = dev->class;
2028
2029 /*
2030 * rev 1 ncr53c810 chips don't set the class at all which means
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03002031 * they don't get their resources remapped. Fix that here.
2032 */
Bjorn Helgaase6323e32015-06-19 15:36:45 -05002033 if (class)
2034 return;
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03002035
Bjorn Helgaase6323e32015-06-19 15:36:45 -05002036 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2037 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2038 class, dev->class);
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03002039}
2040DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2041
Daniel Yeisley9d265122005-12-05 07:06:43 -05002042/* Enable 1k I/O space granularity on the Intel P64H2 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002043static void quirk_p64h2_1k_io(struct pci_dev *dev)
Daniel Yeisley9d265122005-12-05 07:06:43 -05002044{
2045 u16 en1k;
Daniel Yeisley9d265122005-12-05 07:06:43 -05002046
2047 pci_read_config_word(dev, 0x40, &en1k);
2048
2049 if (en1k & 0x200) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002050 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -06002051 dev->io_window_1k = 1;
Daniel Yeisley9d265122005-12-05 07:06:43 -05002052 }
2053}
2054DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2055
Brice Goglincf34a8e2006-06-13 14:35:42 -04002056/* Under some circumstances, AER is not linked with extended capabilities.
2057 * Force it to be linked by setting the corresponding control bit in the
2058 * config space.
2059 */
Alan Cox1597cac2006-12-04 15:14:45 -08002060static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
Brice Goglincf34a8e2006-06-13 14:35:42 -04002061{
2062 uint8_t b;
2063 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2064 if (!(b & 0x20)) {
2065 pci_write_config_byte(dev, 0xf41, b | 0x20);
Ryan Desfosses227f0642014-04-18 20:13:50 -04002066 dev_info(&dev->dev, "Linking AER extended capability\n");
Brice Goglincf34a8e2006-06-13 14:35:42 -04002067 }
2068 }
2069}
2070DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2071 quirk_nvidia_ck804_pcie_aer_ext_cap);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02002072DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
Alan Cox1597cac2006-12-04 15:14:45 -08002073 quirk_nvidia_ck804_pcie_aer_ext_cap);
Brice Goglincf34a8e2006-06-13 14:35:42 -04002074
Bill Pemberton15856ad2012-11-21 15:35:00 -05002075static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
Tim Yamin53a9bf42007-11-01 23:14:54 +00002076{
2077 /*
2078 * Disable PCI Bus Parking and PCI Master read caching on CX700
2079 * which causes unspecified timing errors with a VT6212L on the PCI
Tim Yaminca846392010-03-19 14:22:58 -07002080 * bus leading to USB2.0 packet loss.
2081 *
2082 * This quirk is only enabled if a second (on the external PCI bus)
2083 * VT6212L is found -- the CX700 core itself also contains a USB
2084 * host controller with the same PCI ID as the VT6212L.
Tim Yamin53a9bf42007-11-01 23:14:54 +00002085 */
2086
Tim Yaminca846392010-03-19 14:22:58 -07002087 /* Count VT6212L instances */
2088 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2089 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
Tim Yamin53a9bf42007-11-01 23:14:54 +00002090 uint8_t b;
Tim Yaminca846392010-03-19 14:22:58 -07002091
2092 /* p should contain the first (internal) VT6212L -- see if we have
2093 an external one by searching again */
2094 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2095 if (!p)
2096 return;
2097 pci_dev_put(p);
2098
Tim Yamin53a9bf42007-11-01 23:14:54 +00002099 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2100 if (b & 0x40) {
2101 /* Turn off PCI Bus Parking */
2102 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2103
Ryan Desfosses227f0642014-04-18 20:13:50 -04002104 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
Tim Yaminbc043272008-03-30 20:58:59 +01002105 }
2106 }
2107
2108 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2109 if (b != 0) {
Tim Yamin53a9bf42007-11-01 23:14:54 +00002110 /* Turn off PCI Master read caching */
2111 pci_write_config_byte(dev, 0x72, 0x0);
Tim Yaminbc043272008-03-30 20:58:59 +01002112
2113 /* Set PCI Master Bus time-out to "1x16 PCLK" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00002114 pci_write_config_byte(dev, 0x75, 0x1);
Tim Yaminbc043272008-03-30 20:58:59 +01002115
2116 /* Disable "Read FIFO Timer" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00002117 pci_write_config_byte(dev, 0x77, 0x0);
2118
Ryan Desfosses227f0642014-04-18 20:13:50 -04002119 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
Tim Yamin53a9bf42007-11-01 23:14:54 +00002120 }
2121 }
2122}
Tim Yaminca846392010-03-19 14:22:58 -07002123DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
Tim Yamin53a9bf42007-11-01 23:14:54 +00002124
Benjamin Li99cb233d2008-07-02 10:59:04 -07002125/*
2126 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2127 * VPD end tag will hang the device. This problem was initially
2128 * observed when a vpd entry was created in sysfs
2129 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2130 * will dump 32k of data. Reading a full 32k will cause an access
2131 * beyond the VPD end tag causing the device to hang. Once the device
2132 * is hung, the bnx2 driver will not be able to reset the device.
2133 * We believe that it is legal to read beyond the end tag and
2134 * therefore the solution is to limit the read/write length.
2135 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002136static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
Benjamin Li99cb233d2008-07-02 10:59:04 -07002137{
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002138 /*
Dean Hildebrand35405f22008-08-07 17:31:45 -07002139 * Only disable the VPD capability for 5706, 5706S, 5708,
2140 * 5708S and 5709 rev. A
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002141 */
Benjamin Li99cb233d2008-07-02 10:59:04 -07002142 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
Dean Hildebrand35405f22008-08-07 17:31:45 -07002143 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
Benjamin Li99cb233d2008-07-02 10:59:04 -07002144 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002145 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
Benjamin Li99cb233d2008-07-02 10:59:04 -07002146 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2147 (dev->revision & 0xf0) == 0x0)) {
2148 if (dev->vpd)
2149 dev->vpd->len = 0x80;
2150 }
2151}
2152
Yu Zhaobffadff2008-10-28 14:44:11 +08002153DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2154 PCI_DEVICE_ID_NX2_5706,
2155 quirk_brcm_570x_limit_vpd);
2156DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2157 PCI_DEVICE_ID_NX2_5706S,
2158 quirk_brcm_570x_limit_vpd);
2159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2160 PCI_DEVICE_ID_NX2_5708,
2161 quirk_brcm_570x_limit_vpd);
2162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2163 PCI_DEVICE_ID_NX2_5708S,
2164 quirk_brcm_570x_limit_vpd);
2165DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2166 PCI_DEVICE_ID_NX2_5709,
2167 quirk_brcm_570x_limit_vpd);
2168DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2169 PCI_DEVICE_ID_NX2_5709S,
2170 quirk_brcm_570x_limit_vpd);
Benjamin Li99cb233d2008-07-02 10:59:04 -07002171
Myron Stowe25e742b2012-07-09 15:36:14 -06002172static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
Matt Carlson0b471502012-02-27 09:44:48 +00002173{
2174 u32 rev;
2175
2176 pci_read_config_dword(dev, 0xf4, &rev);
2177
2178 /* Only CAP the MRRS if the device is a 5719 A0 */
2179 if (rev == 0x05719000) {
2180 int readrq = pcie_get_readrq(dev);
2181 if (readrq > 2048)
2182 pcie_set_readrq(dev, 2048);
2183 }
2184}
2185
2186DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2187 PCI_DEVICE_ID_TIGON3_5719,
2188 quirk_brcm_5719_limit_mrrs);
2189
Michal Miroslaw26c56dc2009-05-12 13:49:26 -07002190/* Originally in EDAC sources for i82875P:
2191 * Intel tells BIOS developers to hide device 6 which
2192 * configures the overflow device access containing
2193 * the DRBs - this is where we expose device 6.
2194 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2195 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002196static void quirk_unhide_mch_dev6(struct pci_dev *dev)
Michal Miroslaw26c56dc2009-05-12 13:49:26 -07002197{
2198 u8 reg;
2199
2200 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2201 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2202 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2203 }
2204}
2205
2206DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2207 quirk_unhide_mch_dev6);
2208DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2209 quirk_unhide_mch_dev6);
2210
Chris Metcalf12962262012-04-07 17:10:17 -04002211#ifdef CONFIG_TILEPRO
Chris Metcalff02cbbe2010-11-02 12:05:10 -04002212/*
Chris Metcalf12962262012-04-07 17:10:17 -04002213 * The Tilera TILEmpower tilepro platform needs to set the link speed
Chris Metcalff02cbbe2010-11-02 12:05:10 -04002214 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2215 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2216 * capability register of the PEX8624 PCIe switch. The switch
2217 * supports link speed auto negotiation, but falsely sets
2218 * the link speed to 5GT/s.
2219 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002220static void quirk_tile_plx_gen1(struct pci_dev *dev)
Chris Metcalff02cbbe2010-11-02 12:05:10 -04002221{
2222 if (tile_plx_gen1) {
2223 pci_write_config_dword(dev, 0x98, 0x1);
2224 mdelay(50);
2225 }
2226}
2227DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
Chris Metcalf12962262012-04-07 17:10:17 -04002228#endif /* CONFIG_TILEPRO */
Michal Miroslaw26c56dc2009-05-12 13:49:26 -07002229
Brice Goglin3f79e102006-08-31 01:54:56 -04002230#ifdef CONFIG_PCI_MSI
Tejun Heoebdf7d32007-05-31 00:40:48 -07002231/* Some chipsets do not support MSI. We cannot easily rely on setting
2232 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002233 * some other buses controlled by the chipset even if Linux is not
2234 * aware of it. Instead of setting the flag on all buses in the
Tejun Heoebdf7d32007-05-31 00:40:48 -07002235 * machine, simply disable MSI globally.
Brice Goglin3f79e102006-08-31 01:54:56 -04002236 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002237static void quirk_disable_all_msi(struct pci_dev *dev)
Brice Goglin3f79e102006-08-31 01:54:56 -04002238{
Michael Ellerman88187df2007-01-25 19:34:07 +11002239 pci_no_msi();
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002240 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04002241}
Tejun Heoebdf7d32007-05-31 00:40:48 -07002242DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2243DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
Tejun Heo66d715c2008-07-04 09:59:32 -07002245DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
Jay Cliburn184b8122007-05-26 17:01:04 -05002246DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
Thomas Renninger162dedd2009-04-03 06:34:00 -07002247DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
Tejun Heo549e1562010-05-23 10:22:55 +02002248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
Ondrej Zary10b4ad12015-09-24 17:02:07 -05002249DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
Brice Goglin3f79e102006-08-31 01:54:56 -04002250
2251/* Disable MSI on chipsets that are known to not support it */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002252static void quirk_disable_msi(struct pci_dev *dev)
Brice Goglin3f79e102006-08-31 01:54:56 -04002253{
2254 if (dev->subordinate) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002255 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04002256 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2257 }
2258}
2259DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
Matthew Wilcox134b3452010-03-24 07:11:01 -06002260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
Alex Deucher9313ff42010-05-18 10:42:53 -04002261DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
Brice Goglin6397c752006-08-31 01:55:32 -04002262
Clemens Ladischaff61362010-05-26 12:21:10 +02002263/*
2264 * The APC bridge device in AMD 780 family northbridges has some random
2265 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2266 * we use the possible vendor/device IDs of the host bridge for the
2267 * declared quirk, and search for the APC bridge by slot number.
2268 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002269static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
Clemens Ladischaff61362010-05-26 12:21:10 +02002270{
2271 struct pci_dev *apc_bridge;
2272
2273 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2274 if (apc_bridge) {
2275 if (apc_bridge->device == 0x9602)
2276 quirk_disable_msi(apc_bridge);
2277 pci_dev_put(apc_bridge);
2278 }
2279}
2280DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2281DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2282
Brice Goglin6397c752006-08-31 01:55:32 -04002283/* Go through the list of Hypertransport capabilities and
2284 * return 1 if a HT MSI capability is found and enabled */
Myron Stowe25e742b2012-07-09 15:36:14 -06002285static int msi_ht_cap_enabled(struct pci_dev *dev)
Brice Goglin6397c752006-08-31 01:55:32 -04002286{
Wei Yangfff905f2015-06-30 09:16:41 +08002287 int pos, ttl = PCI_FIND_CAP_TTL;
Michael Ellerman7a380502006-11-22 18:26:21 +11002288
2289 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2290 while (pos && ttl--) {
2291 u8 flags;
2292
2293 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04002294 &flags) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002295 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
Michael Ellerman7a380502006-11-22 18:26:21 +11002296 flags & HT_MSI_FLAGS_ENABLE ?
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002297 "enabled" : "disabled");
Michael Ellerman7a380502006-11-22 18:26:21 +11002298 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
Brice Goglin6397c752006-08-31 01:55:32 -04002299 }
Michael Ellerman7a380502006-11-22 18:26:21 +11002300
2301 pos = pci_find_next_ht_capability(dev, pos,
2302 HT_CAPTYPE_MSI_MAPPING);
Brice Goglin6397c752006-08-31 01:55:32 -04002303 }
2304 return 0;
2305}
2306
2307/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
Myron Stowe25e742b2012-07-09 15:36:14 -06002308static void quirk_msi_ht_cap(struct pci_dev *dev)
Brice Goglin6397c752006-08-31 01:55:32 -04002309{
2310 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002311 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04002312 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2313 }
2314}
2315DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2316 quirk_msi_ht_cap);
Sebastien Dugue6bae1d92007-12-13 16:09:25 -08002317
Brice Goglin6397c752006-08-31 01:55:32 -04002318/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2319 * MSI are supported if the MSI capability set in any of these mappings.
2320 */
Myron Stowe25e742b2012-07-09 15:36:14 -06002321static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
Brice Goglin6397c752006-08-31 01:55:32 -04002322{
2323 struct pci_dev *pdev;
2324
2325 if (!dev->subordinate)
2326 return;
2327
2328 /* check HT MSI cap on this chipset and the root one.
2329 * a single one having MSI is enough to be sure that MSI are supported.
2330 */
Alan Cox11f242f2006-10-10 14:39:00 -07002331 pdev = pci_get_slot(dev->bus, 0);
Jesper Juhl9ac0ce82006-12-04 15:14:48 -08002332 if (!pdev)
2333 return;
David Rientjes0c875c22006-12-03 11:55:34 -08002334 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002335 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04002336 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2337 }
Alan Cox11f242f2006-10-10 14:39:00 -07002338 pci_dev_put(pdev);
Brice Goglin6397c752006-08-31 01:55:32 -04002339}
2340DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2341 quirk_nvidia_ck804_msi_ht_cap);
David Millerba698ad2007-10-25 01:16:30 -07002342
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07002343/* Force enable MSI mapping capability on HT bridges */
Myron Stowe25e742b2012-07-09 15:36:14 -06002344static void ht_enable_msi_mapping(struct pci_dev *dev)
Peer Chen9dc625e2008-02-04 23:50:13 -08002345{
Wei Yangfff905f2015-06-30 09:16:41 +08002346 int pos, ttl = PCI_FIND_CAP_TTL;
Peer Chen9dc625e2008-02-04 23:50:13 -08002347
2348 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2349 while (pos && ttl--) {
2350 u8 flags;
2351
2352 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2353 &flags) == 0) {
2354 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2355
2356 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2357 flags | HT_MSI_FLAGS_ENABLE);
2358 }
2359 pos = pci_find_next_ht_capability(dev, pos,
2360 HT_CAPTYPE_MSI_MAPPING);
2361 }
2362}
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07002363DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2364 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2365 ht_enable_msi_mapping);
Peer Chen9dc625e2008-02-04 23:50:13 -08002366
Yinghai Lue0ae4f52009-02-17 20:40:09 -08002367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2368 ht_enable_msi_mapping);
2369
Ben Hutchingse4146bb2010-05-16 02:28:49 +01002370/* The P5N32-SLI motherboards from Asus have a problem with msi
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002371 * for the MCP55 NIC. It is not yet determined whether the msi problem
2372 * also affects other devices. As for now, turn off msi for this device.
2373 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002374static void nvenet_msi_disable(struct pci_dev *dev)
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002375{
Jean Delvare9251bac2011-05-15 18:13:46 +02002376 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2377
2378 if (board_name &&
2379 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2380 strstr(board_name, "P5N32-E SLI"))) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002381 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002382 dev->no_msi = 1;
2383 }
2384}
2385DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2386 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2387 nvenet_msi_disable);
2388
Neil Horman66db60e2010-09-21 13:54:39 -04002389/*
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002390 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2391 * config register. This register controls the routing of legacy
2392 * interrupts from devices that route through the MCP55. If this register
2393 * is misprogrammed, interrupts are only sent to the BSP, unlike
2394 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2395 * having this register set properly prevents kdump from booting up
2396 * properly, so let's make sure that we have it set correctly.
2397 * Note that this is an undocumented register.
Neil Horman66db60e2010-09-21 13:54:39 -04002398 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002399static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
Neil Horman66db60e2010-09-21 13:54:39 -04002400{
2401 u32 cfg;
2402
Neil Horman49c2fa082010-12-08 09:47:48 -05002403 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2404 return;
2405
Neil Horman66db60e2010-09-21 13:54:39 -04002406 pci_read_config_dword(dev, 0x74, &cfg);
2407
2408 if (cfg & ((1 << 2) | (1 << 15))) {
2409 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2410 cfg &= ~((1 << 2) | (1 << 15));
2411 pci_write_config_dword(dev, 0x74, cfg);
2412 }
2413}
2414
2415DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2416 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2417 nvbridge_check_legacy_irq_routing);
2418
2419DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2420 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2421 nvbridge_check_legacy_irq_routing);
2422
Myron Stowe25e742b2012-07-09 15:36:14 -06002423static int ht_check_msi_mapping(struct pci_dev *dev)
Yinghai Lude745302009-03-20 19:29:41 -07002424{
Wei Yangfff905f2015-06-30 09:16:41 +08002425 int pos, ttl = PCI_FIND_CAP_TTL;
Yinghai Lude745302009-03-20 19:29:41 -07002426 int found = 0;
2427
2428 /* check if there is HT MSI cap or enabled on this device */
2429 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2430 while (pos && ttl--) {
2431 u8 flags;
2432
2433 if (found < 1)
2434 found = 1;
2435 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2436 &flags) == 0) {
2437 if (flags & HT_MSI_FLAGS_ENABLE) {
2438 if (found < 2) {
2439 found = 2;
2440 break;
2441 }
2442 }
2443 }
2444 pos = pci_find_next_ht_capability(dev, pos,
2445 HT_CAPTYPE_MSI_MAPPING);
2446 }
2447
2448 return found;
2449}
2450
Myron Stowe25e742b2012-07-09 15:36:14 -06002451static int host_bridge_with_leaf(struct pci_dev *host_bridge)
Yinghai Lude745302009-03-20 19:29:41 -07002452{
2453 struct pci_dev *dev;
2454 int pos;
2455 int i, dev_no;
2456 int found = 0;
2457
2458 dev_no = host_bridge->devfn >> 3;
2459 for (i = dev_no + 1; i < 0x20; i++) {
2460 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2461 if (!dev)
2462 continue;
2463
2464 /* found next host bridge ?*/
2465 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2466 if (pos != 0) {
2467 pci_dev_put(dev);
2468 break;
2469 }
2470
2471 if (ht_check_msi_mapping(dev)) {
2472 found = 1;
2473 pci_dev_put(dev);
2474 break;
2475 }
2476 pci_dev_put(dev);
2477 }
2478
2479 return found;
2480}
2481
Yinghai Lueeafda72009-03-29 12:30:05 -07002482#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2483#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2484
Myron Stowe25e742b2012-07-09 15:36:14 -06002485static int is_end_of_ht_chain(struct pci_dev *dev)
Yinghai Lueeafda72009-03-29 12:30:05 -07002486{
2487 int pos, ctrl_off;
2488 int end = 0;
2489 u16 flags, ctrl;
2490
2491 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2492
2493 if (!pos)
2494 goto out;
2495
2496 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2497
2498 ctrl_off = ((flags >> 10) & 1) ?
2499 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2500 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2501
2502 if (ctrl & (1 << 6))
2503 end = 1;
2504
2505out:
2506 return end;
2507}
2508
Myron Stowe25e742b2012-07-09 15:36:14 -06002509static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002510{
2511 struct pci_dev *host_bridge;
2512 int pos;
2513 int i, dev_no;
2514 int found = 0;
2515
2516 dev_no = dev->devfn >> 3;
2517 for (i = dev_no; i >= 0; i--) {
2518 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2519 if (!host_bridge)
2520 continue;
2521
2522 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2523 if (pos != 0) {
2524 found = 1;
2525 break;
2526 }
2527 pci_dev_put(host_bridge);
2528 }
2529
2530 if (!found)
2531 return;
2532
Yinghai Lueeafda72009-03-29 12:30:05 -07002533 /* don't enable end_device/host_bridge with leaf directly here */
2534 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2535 host_bridge_with_leaf(host_bridge))
Yinghai Lude745302009-03-20 19:29:41 -07002536 goto out;
2537
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002538 /* root did that ! */
2539 if (msi_ht_cap_enabled(host_bridge))
2540 goto out;
2541
2542 ht_enable_msi_mapping(dev);
2543
2544out:
2545 pci_dev_put(host_bridge);
2546}
2547
Myron Stowe25e742b2012-07-09 15:36:14 -06002548static void ht_disable_msi_mapping(struct pci_dev *dev)
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002549{
Wei Yangfff905f2015-06-30 09:16:41 +08002550 int pos, ttl = PCI_FIND_CAP_TTL;
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002551
2552 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2553 while (pos && ttl--) {
2554 u8 flags;
2555
2556 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2557 &flags) == 0) {
Prakash Punnoor6a958d52009-03-06 10:10:35 +01002558 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002559
2560 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2561 flags & ~HT_MSI_FLAGS_ENABLE);
2562 }
2563 pos = pci_find_next_ht_capability(dev, pos,
2564 HT_CAPTYPE_MSI_MAPPING);
2565 }
2566}
2567
Myron Stowe25e742b2012-07-09 15:36:14 -06002568static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
Peer Chen9dc625e2008-02-04 23:50:13 -08002569{
2570 struct pci_dev *host_bridge;
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002571 int pos;
2572 int found;
2573
Rafael J. Wysocki3d2a5312010-07-23 22:19:55 +02002574 if (!pci_msi_enabled())
2575 return;
2576
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002577 /* check if there is HT MSI cap or enabled on this device */
2578 found = ht_check_msi_mapping(dev);
2579
2580 /* no HT MSI CAP */
2581 if (found == 0)
2582 return;
Peer Chen9dc625e2008-02-04 23:50:13 -08002583
2584 /*
2585 * HT MSI mapping should be disabled on devices that are below
2586 * a non-Hypertransport host bridge. Locate the host bridge...
2587 */
2588 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2589 if (host_bridge == NULL) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002590 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
Peer Chen9dc625e2008-02-04 23:50:13 -08002591 return;
2592 }
2593
2594 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2595 if (pos != 0) {
2596 /* Host bridge is to HT */
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002597 if (found == 1) {
2598 /* it is not enabled, try to enable it */
Yinghai Lude745302009-03-20 19:29:41 -07002599 if (all)
2600 ht_enable_msi_mapping(dev);
2601 else
2602 nv_ht_enable_msi_mapping(dev);
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002603 }
Myron Stowedff3aef2012-07-09 15:36:08 -06002604 goto out;
Peer Chen9dc625e2008-02-04 23:50:13 -08002605 }
2606
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002607 /* HT MSI is not enabled */
2608 if (found == 1)
Myron Stowedff3aef2012-07-09 15:36:08 -06002609 goto out;
Peer Chen9dc625e2008-02-04 23:50:13 -08002610
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002611 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2612 ht_disable_msi_mapping(dev);
Myron Stowedff3aef2012-07-09 15:36:08 -06002613
2614out:
2615 pci_dev_put(host_bridge);
Peer Chen9dc625e2008-02-04 23:50:13 -08002616}
Yinghai Lude745302009-03-20 19:29:41 -07002617
Myron Stowe25e742b2012-07-09 15:36:14 -06002618static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
Yinghai Lude745302009-03-20 19:29:41 -07002619{
2620 return __nv_msi_ht_cap_quirk(dev, 1);
2621}
2622
Myron Stowe25e742b2012-07-09 15:36:14 -06002623static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
Yinghai Lude745302009-03-20 19:29:41 -07002624{
2625 return __nv_msi_ht_cap_quirk(dev, 0);
2626}
2627
2628DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
Tejun Heo6dab62e2009-07-21 16:08:43 -07002629DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
Yinghai Lude745302009-03-20 19:29:41 -07002630
2631DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
Tejun Heo6dab62e2009-07-21 16:08:43 -07002632DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
Peer Chen9dc625e2008-02-04 23:50:13 -08002633
Bill Pemberton15856ad2012-11-21 15:35:00 -05002634static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
David Millerba698ad2007-10-25 01:16:30 -07002635{
2636 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2637}
Bill Pemberton15856ad2012-11-21 15:35:00 -05002638static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
Shane Huang4600c9d2008-01-25 15:46:24 +09002639{
2640 struct pci_dev *p;
2641
2642 /* SB700 MSI issue will be fixed at HW level from revision A21,
2643 * we need check PCI REVISION ID of SMBus controller to get SB700
2644 * revision.
2645 */
2646 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2647 NULL);
2648 if (!p)
2649 return;
2650
2651 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2652 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2653 pci_dev_put(p);
2654}
Xiong Huang70588812013-03-07 08:55:16 +00002655static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2656{
2657 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2658 if (dev->revision < 0x18) {
2659 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2660 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2661 }
2662}
David Millerba698ad2007-10-25 01:16:30 -07002663DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2664 PCI_DEVICE_ID_TIGON3_5780,
2665 quirk_msi_intx_disable_bug);
2666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2667 PCI_DEVICE_ID_TIGON3_5780S,
2668 quirk_msi_intx_disable_bug);
2669DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2670 PCI_DEVICE_ID_TIGON3_5714,
2671 quirk_msi_intx_disable_bug);
2672DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2673 PCI_DEVICE_ID_TIGON3_5714S,
2674 quirk_msi_intx_disable_bug);
2675DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2676 PCI_DEVICE_ID_TIGON3_5715,
2677 quirk_msi_intx_disable_bug);
2678DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2679 PCI_DEVICE_ID_TIGON3_5715S,
2680 quirk_msi_intx_disable_bug);
2681
David Millerbc38b412007-10-25 01:16:52 -07002682DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
Shane Huang4600c9d2008-01-25 15:46:24 +09002683 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002684DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
Shane Huang4600c9d2008-01-25 15:46:24 +09002685 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002686DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
Shane Huang4600c9d2008-01-25 15:46:24 +09002687 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002688DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
Shane Huang4600c9d2008-01-25 15:46:24 +09002689 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002690DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
Shane Huang4600c9d2008-01-25 15:46:24 +09002691 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002692
2693DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2694 quirk_msi_intx_disable_bug);
2695DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2696 quirk_msi_intx_disable_bug);
2697DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2698 quirk_msi_intx_disable_bug);
2699
Huang, Xiong7cb6a292012-04-30 15:38:49 +00002700DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2701 quirk_msi_intx_disable_bug);
2702DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2703 quirk_msi_intx_disable_bug);
2704DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2705 quirk_msi_intx_disable_bug);
2706DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2707 quirk_msi_intx_disable_bug);
2708DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2709 quirk_msi_intx_disable_bug);
2710DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2711 quirk_msi_intx_disable_bug);
Xiong Huang70588812013-03-07 08:55:16 +00002712DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2713 quirk_msi_intx_disable_qca_bug);
2714DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2715 quirk_msi_intx_disable_qca_bug);
2716DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2717 quirk_msi_intx_disable_qca_bug);
2718DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2719 quirk_msi_intx_disable_qca_bug);
2720DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2721 quirk_msi_intx_disable_qca_bug);
Brice Goglin3f79e102006-08-31 01:54:56 -04002722#endif /* CONFIG_PCI_MSI */
Thomas Petazzoni3d137312008-08-19 10:28:24 +02002723
Felix Radensky33223402010-03-28 16:02:02 +03002724/* Allow manual resource allocation for PCI hotplug bridges
2725 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2726 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002727 * kernel fails to allocate resources when hotplug device is
Felix Radensky33223402010-03-28 16:02:02 +03002728 * inserted and PCI bus is rescanned.
2729 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002730static void quirk_hotplug_bridge(struct pci_dev *dev)
Felix Radensky33223402010-03-28 16:02:02 +03002731{
2732 dev->is_hotplug_bridge = 1;
2733}
2734
2735DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2736
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002737/*
2738 * This is a quirk for the Ricoh MMC controller found as a part of
2739 * some mulifunction chips.
2740
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002741 * This is very similar and based on the ricoh_mmc driver written by
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002742 * Philip Langdale. Thank you for these magic sequences.
2743 *
2744 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2745 * and one or both of cardbus or firewire.
2746 *
2747 * It happens that they implement SD and MMC
2748 * support as separate controllers (and PCI functions). The linux SDHCI
2749 * driver supports MMC cards but the chip detects MMC cards in hardware
2750 * and directs them to the MMC controller - so the SDHCI driver never sees
2751 * them.
2752 *
2753 * To get around this, we must disable the useless MMC controller.
2754 * At that point, the SDHCI controller will start seeing them
2755 * It seems to be the case that the relevant PCI registers to deactivate the
2756 * MMC controller live on PCI function 0, which might be the cardbus controller
2757 * or the firewire controller, depending on the particular chip in question
2758 *
2759 * This has to be done early, because as soon as we disable the MMC controller
2760 * other pci functions shift up one level, e.g. function #2 becomes function
2761 * #1, and this will confuse the pci core.
2762 */
2763
2764#ifdef CONFIG_MMC_RICOH_MMC
2765static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2766{
2767 /* disable via cardbus interface */
2768 u8 write_enable;
2769 u8 write_target;
2770 u8 disable;
2771
2772 /* disable must be done via function #0 */
2773 if (PCI_FUNC(dev->devfn))
2774 return;
2775
2776 pci_read_config_byte(dev, 0xB7, &disable);
2777 if (disable & 0x02)
2778 return;
2779
2780 pci_read_config_byte(dev, 0x8E, &write_enable);
2781 pci_write_config_byte(dev, 0x8E, 0xAA);
2782 pci_read_config_byte(dev, 0x8D, &write_target);
2783 pci_write_config_byte(dev, 0x8D, 0xB7);
2784 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2785 pci_write_config_byte(dev, 0x8E, write_enable);
2786 pci_write_config_byte(dev, 0x8D, write_target);
2787
2788 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2789 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2790}
2791DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2792DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2793
2794static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2795{
2796 /* disable via firewire interface */
2797 u8 write_enable;
2798 u8 disable;
2799
2800 /* disable must be done via function #0 */
2801 if (PCI_FUNC(dev->devfn))
2802 return;
Manoj Iyer15bed0f2011-07-11 16:28:35 -05002803 /*
Andy Lutomirski812089e2012-12-01 12:37:20 -08002804 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
Manoj Iyer15bed0f2011-07-11 16:28:35 -05002805 * certain types of SD/MMC cards. Lowering the SD base
2806 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2807 *
2808 * 0x150 - SD2.0 mode enable for changing base clock
2809 * frequency to 50Mhz
2810 * 0xe1 - Base clock frequency
2811 * 0x32 - 50Mhz new clock frequency
2812 * 0xf9 - Key register for 0x150
2813 * 0xfc - key register for 0xe1
2814 */
Andy Lutomirski812089e2012-12-01 12:37:20 -08002815 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2816 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
Manoj Iyer15bed0f2011-07-11 16:28:35 -05002817 pci_write_config_byte(dev, 0xf9, 0xfc);
2818 pci_write_config_byte(dev, 0x150, 0x10);
2819 pci_write_config_byte(dev, 0xf9, 0x00);
2820 pci_write_config_byte(dev, 0xfc, 0x01);
2821 pci_write_config_byte(dev, 0xe1, 0x32);
2822 pci_write_config_byte(dev, 0xfc, 0x00);
2823
2824 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2825 }
Josh Boyer3e309cd2011-10-05 11:44:50 -04002826
2827 pci_read_config_byte(dev, 0xCB, &disable);
2828
2829 if (disable & 0x02)
2830 return;
2831
2832 pci_read_config_byte(dev, 0xCA, &write_enable);
2833 pci_write_config_byte(dev, 0xCA, 0x57);
2834 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2835 pci_write_config_byte(dev, 0xCA, write_enable);
2836
2837 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2838 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2839
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002840}
2841DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2842DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
Andy Lutomirski812089e2012-12-01 12:37:20 -08002843DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2844DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
Manoj Iyerbe98ca62011-05-26 11:19:05 -05002845DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2846DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002847#endif /*CONFIG_MMC_RICOH_MMC*/
2848
Suresh Siddhad3f13812011-08-23 17:05:25 -07002849#ifdef CONFIG_DMAR_TABLE
Suresh Siddha254e42002010-12-06 12:26:30 -08002850#define VTUNCERRMSK_REG 0x1ac
2851#define VTD_MSK_SPEC_ERRORS (1 << 31)
2852/*
2853 * This is a quirk for masking vt-d spec defined errors to platform error
2854 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2855 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2856 * on the RAS config settings of the platform) when a vt-d fault happens.
2857 * The resulting SMI caused the system to hang.
2858 *
2859 * VT-d spec related errors are already handled by the VT-d OS code, so no
2860 * need to report the same error through other channels.
2861 */
2862static void vtd_mask_spec_errors(struct pci_dev *dev)
2863{
2864 u32 word;
2865
2866 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2867 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2868}
2869DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2870DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2871#endif
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002872
Bill Pemberton15856ad2012-11-21 15:35:00 -05002873static void fixup_ti816x_class(struct pci_dev *dev)
Hemant Pedanekar63c44082011-04-05 12:32:50 +05302874{
Bjorn Helgaasd1541dc2015-06-19 15:58:24 -05002875 u32 class = dev->class;
2876
Hemant Pedanekar63c44082011-04-05 12:32:50 +05302877 /* TI 816x devices do not have class code set when in PCIe boot mode */
Bjorn Helgaasd1541dc2015-06-19 15:58:24 -05002878 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
2879 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
2880 class, dev->class);
Hemant Pedanekar63c44082011-04-05 12:32:50 +05302881}
Yinghai Lu40c96232012-02-23 23:46:58 -08002882DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05002883 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
Hemant Pedanekar63c44082011-04-05 12:32:50 +05302884
Ben Hutchingsa94d0722011-10-05 22:35:03 +01002885/* Some PCIe devices do not work reliably with the claimed maximum
2886 * payload size supported.
2887 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002888static void fixup_mpss_256(struct pci_dev *dev)
Ben Hutchingsa94d0722011-10-05 22:35:03 +01002889{
2890 dev->pcie_mpss = 1; /* 256 bytes */
2891}
2892DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2893 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2895 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2896DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2897 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2898
Jon Masond387a8d2011-10-14 14:56:13 -05002899/* Intel 5000 and 5100 Memory controllers have an errata with read completion
2900 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2901 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2902 * until all of the devices are discovered and buses walked, read completion
2903 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2904 * it is possible to hotplug a device with MPS of 256B.
2905 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002906static void quirk_intel_mc_errata(struct pci_dev *dev)
Jon Masond387a8d2011-10-14 14:56:13 -05002907{
2908 int err;
2909 u16 rcc;
2910
Keith Busch27d868b2015-08-24 08:48:16 -05002911 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2912 pcie_bus_config == PCIE_BUS_DEFAULT)
Jon Masond387a8d2011-10-14 14:56:13 -05002913 return;
2914
2915 /* Intel errata specifies bits to change but does not say what they are.
2916 * Keeping them magical until such time as the registers and values can
2917 * be explained.
2918 */
2919 err = pci_read_config_word(dev, 0x48, &rcc);
2920 if (err) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002921 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
Jon Masond387a8d2011-10-14 14:56:13 -05002922 return;
2923 }
2924
2925 if (!(rcc & (1 << 10)))
2926 return;
2927
2928 rcc &= ~(1 << 10);
2929
2930 err = pci_write_config_word(dev, 0x48, rcc);
2931 if (err) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002932 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
Jon Masond387a8d2011-10-14 14:56:13 -05002933 return;
2934 }
2935
Ryan Desfosses227f0642014-04-18 20:13:50 -04002936 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
Jon Masond387a8d2011-10-14 14:56:13 -05002937}
2938/* Intel 5000 series memory controllers and ports 2-7 */
2939DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2940DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2941DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2942DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2943DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2944DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2945DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2946DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2947DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2948DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2949DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2950DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2951DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2952DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2953/* Intel 5100 series memory controllers and ports 2-7 */
2954DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2955DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2956DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2957DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2958DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2959DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2960DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2961DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2962DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2963DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2964DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2965
Arjan van de Ven32098742012-01-30 20:52:07 -08002966
Jon Mason12b03182013-05-06 08:03:33 +00002967/*
2968 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
2969 * work around this, query the size it should be configured to by the device and
2970 * modify the resource end to correspond to this new size.
2971 */
2972static void quirk_intel_ntb(struct pci_dev *dev)
2973{
2974 int rc;
2975 u8 val;
2976
2977 rc = pci_read_config_byte(dev, 0x00D0, &val);
2978 if (rc)
2979 return;
2980
2981 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
2982
2983 rc = pci_read_config_byte(dev, 0x00D1, &val);
2984 if (rc)
2985 return;
2986
2987 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
2988}
2989DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
2990DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
2991
Myron Stowe2729d5b2012-07-09 15:36:02 -06002992static ktime_t fixup_debug_start(struct pci_dev *dev,
2993 void (*fn)(struct pci_dev *dev))
Arjan van de Ven32098742012-01-30 20:52:07 -08002994{
Myron Stowe2729d5b2012-07-09 15:36:02 -06002995 ktime_t calltime = ktime_set(0, 0);
2996
2997 dev_dbg(&dev->dev, "calling %pF\n", fn);
2998 if (initcall_debug) {
2999 pr_debug("calling %pF @ %i for %s\n",
3000 fn, task_pid_nr(current), dev_name(&dev->dev));
3001 calltime = ktime_get();
3002 }
3003
3004 return calltime;
3005}
3006
3007static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
3008 void (*fn)(struct pci_dev *dev))
3009{
3010 ktime_t delta, rettime;
Arjan van de Ven32098742012-01-30 20:52:07 -08003011 unsigned long long duration;
3012
Myron Stowe2729d5b2012-07-09 15:36:02 -06003013 if (initcall_debug) {
3014 rettime = ktime_get();
3015 delta = ktime_sub(rettime, calltime);
3016 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3017 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
3018 fn, duration, dev_name(&dev->dev));
3019 }
Arjan van de Ven32098742012-01-30 20:52:07 -08003020}
3021
Thomas Jaroschf67fd552011-12-07 22:08:11 +01003022/*
3023 * Some BIOS implementations leave the Intel GPU interrupts enabled,
3024 * even though no one is handling them (f.e. i915 driver is never loaded).
3025 * Additionally the interrupt destination is not set up properly
3026 * and the interrupt ends up -somewhere-.
3027 *
3028 * These spurious interrupts are "sticky" and the kernel disables
3029 * the (shared) interrupt line after 100.000+ generated interrupts.
3030 *
3031 * Fix it by disabling the still enabled interrupts.
3032 * This resolves crashes often seen on monitor unplug.
3033 */
3034#define I915_DEIER_REG 0x4400c
Bill Pemberton15856ad2012-11-21 15:35:00 -05003035static void disable_igfx_irq(struct pci_dev *dev)
Thomas Jaroschf67fd552011-12-07 22:08:11 +01003036{
3037 void __iomem *regs = pci_iomap(dev, 0, 0);
3038 if (regs == NULL) {
3039 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
3040 return;
3041 }
3042
3043 /* Check if any interrupt line is still enabled */
3044 if (readl(regs + I915_DEIER_REG) != 0) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04003045 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
Thomas Jaroschf67fd552011-12-07 22:08:11 +01003046
3047 writel(0, regs + I915_DEIER_REG);
3048 }
3049
3050 pci_iounmap(dev, regs);
3051}
3052DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3053DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
Thomas Jarosch7c821262014-04-07 15:10:32 +02003054DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
Thomas Jaroschf67fd552011-12-07 22:08:11 +01003055
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003056/*
Todd E Brandtb8cac702013-09-10 16:10:43 -07003057 * PCI devices which are on Intel chips can skip the 10ms delay
3058 * before entering D3 mode.
3059 */
3060static void quirk_remove_d3_delay(struct pci_dev *dev)
3061{
3062 dev->d3_delay = 0;
3063}
3064DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3065DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3066DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3067DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3068DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3069DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3070DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3071DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3072DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3073DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3074DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3075DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3076DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3077DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
Srinidhi Kasagar4a118752015-06-19 11:52:46 +05303078/* Intel Cherrytrail devices do not need 10ms d3_delay */
3079DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3080DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3081DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3082DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3083DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3084DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3085DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3086DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3087DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
Todd E Brandtb8cac702013-09-10 16:10:43 -07003088/*
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003089 * Some devices may pass our check in pci_intx_mask_supported if
3090 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3091 * support this feature.
3092 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05003093static void quirk_broken_intx_masking(struct pci_dev *dev)
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003094{
3095 dev->broken_intx_masking = 1;
3096}
Jan Kiszkade509f92012-06-07 10:30:59 +02003097DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
3098 quirk_broken_intx_masking);
Alex Williamson0bdb3b22012-06-07 11:01:59 -06003099DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3100 quirk_broken_intx_masking);
Alex Williamson3cb30b72014-05-01 14:36:31 -06003101/*
3102 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3103 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3104 *
3105 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3106 */
3107DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK, 0x8169,
3108 quirk_broken_intx_masking);
Gavin Shan11e42532014-09-05 15:35:30 -06003109DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3110 quirk_broken_intx_masking);
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003111
Alex Williamsonc3e59ee2015-01-15 18:17:12 -06003112static void quirk_no_bus_reset(struct pci_dev *dev)
3113{
3114 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3115}
3116
3117/*
3118 * Atheros AR93xx chips do not behave after a bus reset. The device will
3119 * throw a Link Down error on AER-capable systems and regardless of AER,
3120 * config space of the device is never accessible again and typically
3121 * causes the system to hang or reset when access is attempted.
3122 * http://www.spinics.net/lists/linux-pci/msg34797.html
3123 */
3124DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3125
Alex Williamsond84f3172014-11-21 11:24:14 -07003126static void quirk_no_pm_reset(struct pci_dev *dev)
3127{
3128 /*
3129 * We can't do a bus reset on root bus devices, but an ineffective
3130 * PM reset may be better than nothing.
3131 */
3132 if (!pci_is_root_bus(dev->bus))
3133 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3134}
3135
3136/*
3137 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3138 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3139 * to have no effect on the device: it retains the framebuffer contents and
3140 * monitor sync. Advertising this support makes other layers, like VFIO,
3141 * assume pci_reset_function() is viable for this device. Mark it as
3142 * unavailable to skip it when testing reset methods.
3143 */
3144DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3145 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3146
Andreas Noever1df51722014-06-03 22:04:10 +02003147#ifdef CONFIG_ACPI
3148/*
3149 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3150 *
3151 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3152 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3153 * be present after resume if a device was plugged in before suspend.
3154 *
3155 * The thunderbolt controller consists of a pcie switch with downstream
3156 * bridges leading to the NHI and to the tunnel pci bridges.
3157 *
3158 * This quirk cuts power to the whole chip. Therefore we have to apply it
3159 * during suspend_noirq of the upstream bridge.
3160 *
3161 * Power is automagically restored before resume. No action is needed.
3162 */
3163static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3164{
3165 acpi_handle bridge, SXIO, SXFP, SXLV;
3166
3167 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3168 return;
3169 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3170 return;
3171 bridge = ACPI_HANDLE(&dev->dev);
3172 if (!bridge)
3173 return;
3174 /*
3175 * SXIO and SXLV are present only on machines requiring this quirk.
3176 * TB bridges in external devices might have the same device id as those
3177 * on the host, but they will not have the associated ACPI methods. This
3178 * implicitly checks that we are at the right bridge.
3179 */
3180 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3181 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3182 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3183 return;
3184 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
3185
3186 /* magic sequence */
3187 acpi_execute_simple_method(SXIO, NULL, 1);
3188 acpi_execute_simple_method(SXFP, NULL, 0);
3189 msleep(300);
3190 acpi_execute_simple_method(SXLV, NULL, 0);
3191 acpi_execute_simple_method(SXIO, NULL, 0);
3192 acpi_execute_simple_method(SXLV, NULL, 0);
3193}
3194DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 0x1547,
3195 quirk_apple_poweroff_thunderbolt);
3196
3197/*
3198 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3199 *
3200 * During suspend the thunderbolt controller is reset and all pci
3201 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3202 * during resume. We have to manually wait for the NHI since there is
3203 * no parent child relationship between the NHI and the tunneled
3204 * bridges.
3205 */
3206static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3207{
3208 struct pci_dev *sibling = NULL;
3209 struct pci_dev *nhi = NULL;
3210
3211 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3212 return;
3213 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3214 return;
3215 /*
3216 * Find the NHI and confirm that we are a bridge on the tb host
3217 * controller and not on a tb endpoint.
3218 */
3219 sibling = pci_get_slot(dev->bus, 0x0);
3220 if (sibling == dev)
3221 goto out; /* we are the downstream bridge to the NHI */
3222 if (!sibling || !sibling->subordinate)
3223 goto out;
3224 nhi = pci_get_slot(sibling->subordinate, 0x0);
3225 if (!nhi)
3226 goto out;
3227 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3228 || (nhi->device != 0x1547 && nhi->device != 0x156c)
3229 || nhi->subsystem_vendor != 0x2222
3230 || nhi->subsystem_device != 0x1111)
3231 goto out;
Darrick J. Wongc89ac442015-03-31 19:38:38 -07003232 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
Andreas Noever1df51722014-06-03 22:04:10 +02003233 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3234out:
3235 pci_dev_put(nhi);
3236 pci_dev_put(sibling);
3237}
3238DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x1547,
3239 quirk_apple_wait_for_thunderbolt);
3240DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x156d,
3241 quirk_apple_wait_for_thunderbolt);
3242#endif
3243
Jesse Barnesbfb0f332008-10-27 17:50:21 -07003244static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3245 struct pci_fixup *end)
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003246{
Myron Stowe2729d5b2012-07-09 15:36:02 -06003247 ktime_t calltime;
3248
Yinghai Luf4ca5c62012-02-23 23:46:49 -08003249 for (; f < end; f++)
3250 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3251 f->class == (u32) PCI_ANY_ID) &&
3252 (f->vendor == dev->vendor ||
3253 f->vendor == (u16) PCI_ANY_ID) &&
3254 (f->device == dev->device ||
3255 f->device == (u16) PCI_ANY_ID)) {
Myron Stowe2729d5b2012-07-09 15:36:02 -06003256 calltime = fixup_debug_start(dev, f->hook);
3257 f->hook(dev);
3258 fixup_debug_report(dev, calltime, f->hook);
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003259 }
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003260}
3261
3262extern struct pci_fixup __start_pci_fixups_early[];
3263extern struct pci_fixup __end_pci_fixups_early[];
3264extern struct pci_fixup __start_pci_fixups_header[];
3265extern struct pci_fixup __end_pci_fixups_header[];
3266extern struct pci_fixup __start_pci_fixups_final[];
3267extern struct pci_fixup __end_pci_fixups_final[];
3268extern struct pci_fixup __start_pci_fixups_enable[];
3269extern struct pci_fixup __end_pci_fixups_enable[];
3270extern struct pci_fixup __start_pci_fixups_resume[];
3271extern struct pci_fixup __end_pci_fixups_resume[];
3272extern struct pci_fixup __start_pci_fixups_resume_early[];
3273extern struct pci_fixup __end_pci_fixups_resume_early[];
3274extern struct pci_fixup __start_pci_fixups_suspend[];
3275extern struct pci_fixup __end_pci_fixups_suspend[];
Andreas Noever7d2a01b2014-06-03 22:04:09 +02003276extern struct pci_fixup __start_pci_fixups_suspend_late[];
3277extern struct pci_fixup __end_pci_fixups_suspend_late[];
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003278
Myron Stowe95df8b82012-07-13 14:29:00 -06003279static bool pci_apply_fixup_final_quirks;
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003280
3281void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3282{
3283 struct pci_fixup *start, *end;
3284
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04003285 switch (pass) {
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003286 case pci_fixup_early:
3287 start = __start_pci_fixups_early;
3288 end = __end_pci_fixups_early;
3289 break;
3290
3291 case pci_fixup_header:
3292 start = __start_pci_fixups_header;
3293 end = __end_pci_fixups_header;
3294 break;
3295
3296 case pci_fixup_final:
Myron Stowe95df8b82012-07-13 14:29:00 -06003297 if (!pci_apply_fixup_final_quirks)
3298 return;
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003299 start = __start_pci_fixups_final;
3300 end = __end_pci_fixups_final;
3301 break;
3302
3303 case pci_fixup_enable:
3304 start = __start_pci_fixups_enable;
3305 end = __end_pci_fixups_enable;
3306 break;
3307
3308 case pci_fixup_resume:
3309 start = __start_pci_fixups_resume;
3310 end = __end_pci_fixups_resume;
3311 break;
3312
3313 case pci_fixup_resume_early:
3314 start = __start_pci_fixups_resume_early;
3315 end = __end_pci_fixups_resume_early;
3316 break;
3317
3318 case pci_fixup_suspend:
3319 start = __start_pci_fixups_suspend;
3320 end = __end_pci_fixups_suspend;
3321 break;
3322
Andreas Noever7d2a01b2014-06-03 22:04:09 +02003323 case pci_fixup_suspend_late:
3324 start = __start_pci_fixups_suspend_late;
3325 end = __end_pci_fixups_suspend_late;
3326 break;
3327
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003328 default:
3329 /* stupid compiler warning, you would think with an enum... */
3330 return;
3331 }
3332 pci_do_fixups(dev, start, end);
3333}
Rafael J. Wysocki93177a72010-01-02 22:57:24 +01003334EXPORT_SYMBOL(pci_fixup_device);
David Woodhouse8d86fb22009-10-12 12:48:43 +01003335
Myron Stowe735bff12012-07-09 15:36:46 -06003336
David Woodhouse00010262009-10-12 12:50:34 +01003337static int __init pci_apply_final_quirks(void)
David Woodhouse8d86fb22009-10-12 12:48:43 +01003338{
3339 struct pci_dev *dev = NULL;
Jesse Barnesac1aa472009-10-26 13:20:44 -07003340 u8 cls = 0;
3341 u8 tmp;
3342
3343 if (pci_cache_line_size)
3344 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3345 pci_cache_line_size << 2);
David Woodhouse8d86fb22009-10-12 12:48:43 +01003346
Myron Stowe95df8b82012-07-13 14:29:00 -06003347 pci_apply_fixup_final_quirks = true;
Kulikov Vasiliy4e344b12010-07-03 20:04:39 +04003348 for_each_pci_dev(dev) {
David Woodhouse8d86fb22009-10-12 12:48:43 +01003349 pci_fixup_device(pci_fixup_final, dev);
Jesse Barnesac1aa472009-10-26 13:20:44 -07003350 /*
3351 * If arch hasn't set it explicitly yet, use the CLS
3352 * value shared by all PCI devices. If there's a
3353 * mismatch, fall back to the default value.
3354 */
3355 if (!pci_cache_line_size) {
3356 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3357 if (!cls)
3358 cls = tmp;
3359 if (!tmp || cls == tmp)
3360 continue;
3361
Ryan Desfosses227f0642014-04-18 20:13:50 -04003362 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3363 cls << 2, tmp << 2,
Jesse Barnesac1aa472009-10-26 13:20:44 -07003364 pci_dfl_cache_line_size << 2);
3365 pci_cache_line_size = pci_dfl_cache_line_size;
3366 }
3367 }
Myron Stowe735bff12012-07-09 15:36:46 -06003368
Jesse Barnesac1aa472009-10-26 13:20:44 -07003369 if (!pci_cache_line_size) {
3370 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3371 cls << 2, pci_dfl_cache_line_size << 2);
Csaba Henk2820f332009-12-15 17:55:25 +05303372 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
David Woodhouse8d86fb22009-10-12 12:48:43 +01003373 }
3374
3375 return 0;
3376}
3377
David Woodhousecf6f3bf2009-10-12 12:51:22 +01003378fs_initcall_sync(pci_apply_final_quirks);
Dexuan Cuib9c3b262009-12-07 13:03:21 +08003379
3380/*
3381 * Followings are device-specific reset methods which can be used to
3382 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3383 * not available.
3384 */
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003385static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3386{
Bjorn Helgaas76b57c62012-08-22 09:41:27 -06003387 /*
3388 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3389 *
3390 * The 82599 supports FLR on VFs, but FLR support is reported only
3391 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3392 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3393 */
3394
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003395 if (probe)
3396 return 0;
3397
Casey Leedom4d708ab2013-08-06 15:48:39 +05303398 if (!pci_wait_for_pending_transaction(dev))
3399 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
Bjorn Helgaas76b57c62012-08-22 09:41:27 -06003400
Bjorn Helgaas76b57c62012-08-22 09:41:27 -06003401 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3402
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003403 msleep(100);
3404
3405 return 0;
3406}
3407
Xudong Haodf558de2012-04-27 09:16:46 -06003408#include "../gpu/drm/i915/i915_reg.h"
3409#define MSG_CTL 0x45010
3410#define NSDE_PWR_STATE 0xd0100
3411#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3412
3413static int reset_ivb_igd(struct pci_dev *dev, int probe)
3414{
3415 void __iomem *mmio_base;
3416 unsigned long timeout;
3417 u32 val;
3418
3419 if (probe)
3420 return 0;
3421
3422 mmio_base = pci_iomap(dev, 0, 0);
3423 if (!mmio_base)
3424 return -ENOMEM;
3425
3426 iowrite32(0x00000002, mmio_base + MSG_CTL);
3427
3428 /*
3429 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3430 * driver loaded sets the right bits. However, this's a reset and
3431 * the bits have been set by i915 previously, so we clobber
3432 * SOUTH_CHICKEN2 register directly here.
3433 */
3434 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3435
3436 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3437 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3438
3439 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3440 do {
3441 val = ioread32(mmio_base + PCH_PP_STATUS);
3442 if ((val & 0xb0000000) == 0)
3443 goto reset_complete;
3444 msleep(10);
3445 } while (time_before(jiffies, timeout));
3446 dev_warn(&dev->dev, "timeout during reset\n");
3447
3448reset_complete:
3449 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3450
3451 pci_iounmap(dev, mmio_base);
3452 return 0;
3453}
3454
Casey Leedom2c6217e2013-08-06 15:48:37 +05303455/*
3456 * Device-specific reset method for Chelsio T4-based adapters.
3457 */
3458static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3459{
3460 u16 old_command;
3461 u16 msix_flags;
3462
3463 /*
3464 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3465 * that we have no device-specific reset method.
3466 */
3467 if ((dev->device & 0xf000) != 0x4000)
3468 return -ENOTTY;
3469
3470 /*
3471 * If this is the "probe" phase, return 0 indicating that we can
3472 * reset this device.
3473 */
3474 if (probe)
3475 return 0;
3476
3477 /*
3478 * T4 can wedge if there are DMAs in flight within the chip and Bus
3479 * Master has been disabled. We need to have it on till the Function
3480 * Level Reset completes. (BUS_MASTER is disabled in
3481 * pci_reset_function()).
3482 */
3483 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3484 pci_write_config_word(dev, PCI_COMMAND,
3485 old_command | PCI_COMMAND_MASTER);
3486
3487 /*
3488 * Perform the actual device function reset, saving and restoring
3489 * configuration information around the reset.
3490 */
3491 pci_save_state(dev);
3492
3493 /*
3494 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3495 * are disabled when an MSI-X interrupt message needs to be delivered.
3496 * So we briefly re-enable MSI-X interrupts for the duration of the
3497 * FLR. The pci_restore_state() below will restore the original
3498 * MSI-X state.
3499 */
3500 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3501 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3502 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3503 msix_flags |
3504 PCI_MSIX_FLAGS_ENABLE |
3505 PCI_MSIX_FLAGS_MASKALL);
3506
3507 /*
3508 * Start of pcie_flr() code sequence. This reset code is a copy of
3509 * the guts of pcie_flr() because that's not an exported function.
3510 */
3511
3512 if (!pci_wait_for_pending_transaction(dev))
3513 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3514
3515 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3516 msleep(100);
3517
3518 /*
3519 * End of pcie_flr() code sequence.
3520 */
3521
3522 /*
3523 * Restore the configuration information (BAR values, etc.) including
3524 * the original PCI Configuration Space Command word, and return
3525 * success.
3526 */
3527 pci_restore_state(dev);
3528 pci_write_config_word(dev, PCI_COMMAND, old_command);
3529 return 0;
3530}
3531
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003532#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
Xudong Haodf558de2012-04-27 09:16:46 -06003533#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3534#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003535
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003536static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003537 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3538 reset_intel_82599_sfp_virtfn },
Xudong Haodf558de2012-04-27 09:16:46 -06003539 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3540 reset_ivb_igd },
3541 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3542 reset_ivb_igd },
Casey Leedom2c6217e2013-08-06 15:48:37 +05303543 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3544 reset_chelsio_generic_dev },
Dexuan Cuib9c3b262009-12-07 13:03:21 +08003545 { 0 }
3546};
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003547
Xudong Haodf558de2012-04-27 09:16:46 -06003548/*
3549 * These device-specific reset methods are here rather than in a driver
3550 * because when a host assigns a device to a guest VM, the host may need
3551 * to reset the device but probably doesn't have a driver for it.
3552 */
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003553int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3554{
Linus Torvaldsdf9d1e82009-12-31 16:44:43 -08003555 const struct pci_dev_reset_methods *i;
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003556
3557 for (i = pci_dev_reset_methods; i->reset; i++) {
3558 if ((i->vendor == dev->vendor ||
3559 i->vendor == (u16)PCI_ANY_ID) &&
3560 (i->device == dev->device ||
3561 i->device == (u16)PCI_ANY_ID))
3562 return i->reset(dev, probe);
3563 }
3564
3565 return -ENOTTY;
3566}
Alex Williamson12ea6ca2012-06-11 05:26:55 +00003567
Alex Williamsonec637fb2014-05-22 17:07:49 -06003568static void quirk_dma_func0_alias(struct pci_dev *dev)
3569{
3570 if (PCI_FUNC(dev->devfn) != 0) {
3571 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
3572 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3573 }
3574}
3575
3576/*
3577 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3578 *
3579 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3580 */
3581DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3582DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3583
Alex Williamsoncc346a42014-05-28 14:54:00 -06003584static void quirk_dma_func1_alias(struct pci_dev *dev)
3585{
3586 if (PCI_FUNC(dev->devfn) != 1) {
3587 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 1);
3588 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3589 }
3590}
3591
3592/*
3593 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3594 * SKUs function 1 is present and is a legacy IDE controller, in other
3595 * SKUs this function is not present, making this a ghost requester.
3596 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3597 */
Sakari Ailus247de692015-05-22 00:03:38 +03003598DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3599 quirk_dma_func1_alias);
Alex Williamsoncc346a42014-05-28 14:54:00 -06003600DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3601 quirk_dma_func1_alias);
3602/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3603DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3604 quirk_dma_func1_alias);
3605/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3606DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3607 quirk_dma_func1_alias);
3608/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3609DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3610 quirk_dma_func1_alias);
3611/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3612DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3613 quirk_dma_func1_alias);
3614/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3615DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3616 quirk_dma_func1_alias);
Jérôme Carreteroc2e0fb92014-06-03 15:41:56 -04003617DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3618 quirk_dma_func1_alias);
Alex Williamsoncc346a42014-05-28 14:54:00 -06003619/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3620DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3621 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3622 quirk_dma_func1_alias);
3623
Alex Williamsonebdb51e2014-05-22 17:08:07 -06003624/*
Alex Williamsond3d2ab42015-01-13 11:26:50 -07003625 * Some devices DMA with the wrong devfn, not just the wrong function.
3626 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3627 * the alias is "fixed" and independent of the device devfn.
3628 *
3629 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3630 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3631 * single device on the secondary bus. In reality, the single exposed
3632 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3633 * that provides a bridge to the internal bus of the I/O processor. The
3634 * controller supports private devices, which can be hidden from PCI config
3635 * space. In the case of the Adaptec 3405, a private device at 01.0
3636 * appears to be the DMA engine, which therefore needs to become a DMA
3637 * alias for the device.
3638 */
3639static const struct pci_device_id fixed_dma_alias_tbl[] = {
3640 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3641 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3642 .driver_data = PCI_DEVFN(1, 0) },
3643 { 0 }
3644};
3645
3646static void quirk_fixed_dma_alias(struct pci_dev *dev)
3647{
3648 const struct pci_device_id *id;
3649
3650 id = pci_match_id(fixed_dma_alias_tbl, dev);
3651 if (id) {
3652 dev->dma_alias_devfn = id->driver_data;
3653 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3654 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
3655 PCI_SLOT(dev->dma_alias_devfn),
3656 PCI_FUNC(dev->dma_alias_devfn));
3657 }
3658}
3659
3660DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3661
3662/*
Alex Williamsonebdb51e2014-05-22 17:08:07 -06003663 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3664 * using the wrong DMA alias for the device. Some of these devices can be
3665 * used as either forward or reverse bridges, so we need to test whether the
3666 * device is operating in the correct mode. We could probably apply this
3667 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3668 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3669 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3670 */
3671static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3672{
3673 if (!pci_is_root_bus(pdev->bus) &&
3674 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3675 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3676 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3677 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3678}
3679/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3680DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3681 quirk_use_pcie_bridge_dma_alias);
3682/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3683DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
Alex Williamson98ca50d2014-06-09 12:43:25 -06003684/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3685DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
Alex Williamson8ab4abb2014-07-05 15:26:52 -06003686/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3687DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
Alex Williamsonebdb51e2014-05-22 17:08:07 -06003688
Alex Williamson15b100d2013-06-27 16:40:00 -06003689/*
Krzysztof =?utf-8?Q?Ha=C5=82asa?=3657ceb2015-06-19 10:00:15 +02003690 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
3691 * class code. Fix it.
3692 */
3693static void quirk_tw686x_class(struct pci_dev *pdev)
3694{
3695 u32 class = pdev->class;
3696
3697 /* Use "Multimedia controller" class */
3698 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
3699 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
3700 class, pdev->class);
3701}
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05003702DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
Krzysztof =?utf-8?Q?Ha=C5=82asa?=3657ceb2015-06-19 10:00:15 +02003703 quirk_tw686x_class);
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05003704DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
Krzysztof =?utf-8?Q?Ha=C5=82asa?=3657ceb2015-06-19 10:00:15 +02003705 quirk_tw686x_class);
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05003706DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
Krzysztof =?utf-8?Q?Ha=C5=82asa?=3657ceb2015-06-19 10:00:15 +02003707 quirk_tw686x_class);
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05003708DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
Krzysztof =?utf-8?Q?Ha=C5=82asa?=3657ceb2015-06-19 10:00:15 +02003709 quirk_tw686x_class);
3710
3711/*
Hariprasad Shenaic56d4452015-10-18 19:55:04 +05303712 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
3713 * values for the Attribute as were supplied in the header of the
3714 * corresponding Request, except as explicitly allowed when IDO is used."
3715 *
3716 * If a non-compliant device generates a completion with a different
3717 * attribute than the request, the receiver may accept it (which itself
3718 * seems non-compliant based on sec 2.3.2), or it may handle it as a
3719 * Malformed TLP or an Unexpected Completion, which will probably lead to a
3720 * device access timeout.
3721 *
3722 * If the non-compliant device generates completions with zero attributes
3723 * (instead of copying the attributes from the request), we can work around
3724 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
3725 * upstream devices so they always generate requests with zero attributes.
3726 *
3727 * This affects other devices under the same Root Port, but since these
3728 * attributes are performance hints, there should be no functional problem.
3729 *
3730 * Note that Configuration Space accesses are never supposed to have TLP
3731 * Attributes, so we're safe waiting till after any Configuration Space
3732 * accesses to do the Root Port fixup.
3733 */
3734static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
3735{
3736 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
3737
3738 if (!root_port) {
3739 dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n");
3740 return;
3741 }
3742
3743 dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
3744 dev_name(&pdev->dev));
3745 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
3746 PCI_EXP_DEVCTL_RELAX_EN |
3747 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
3748}
3749
3750/*
3751 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
3752 * Completion it generates.
3753 */
3754static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
3755{
3756 /*
3757 * This mask/compare operation selects for Physical Function 4 on a
3758 * T5. We only need to fix up the Root Port once for any of the
3759 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
3760 * 0x54xx so we use that one,
3761 */
3762 if ((pdev->device & 0xff00) == 0x5400)
3763 quirk_disable_root_port_attributes(pdev);
3764}
3765DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3766 quirk_chelsio_T5_disable_root_port_attributes);
3767
3768/*
Alex Williamson15b100d2013-06-27 16:40:00 -06003769 * AMD has indicated that the devices below do not support peer-to-peer
3770 * in any system where they are found in the southbridge with an AMD
3771 * IOMMU in the system. Multifunction devices that do not support
3772 * peer-to-peer between functions can claim to support a subset of ACS.
3773 * Such devices effectively enable request redirect (RR) and completion
3774 * redirect (CR) since all transactions are redirected to the upstream
3775 * root complex.
3776 *
3777 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
3778 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
3779 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
3780 *
3781 * 1002:4385 SBx00 SMBus Controller
3782 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
3783 * 1002:4383 SBx00 Azalia (Intel HDA)
3784 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
3785 * 1002:4384 SBx00 PCI to PCI Bridge
3786 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
Marti Raudsepp3587e622014-10-02 08:50:31 -06003787 *
3788 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
3789 *
3790 * 1022:780f [AMD] FCH PCI Bridge
3791 * 1022:7809 [AMD] FCH USB OHCI Controller
Alex Williamson15b100d2013-06-27 16:40:00 -06003792 */
3793static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
3794{
3795#ifdef CONFIG_ACPI
3796 struct acpi_table_header *header = NULL;
3797 acpi_status status;
3798
3799 /* Targeting multifunction devices on the SB (appears on root bus) */
3800 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
3801 return -ENODEV;
3802
3803 /* The IVRS table describes the AMD IOMMU */
3804 status = acpi_get_table("IVRS", 0, &header);
3805 if (ACPI_FAILURE(status))
3806 return -ENODEV;
3807
3808 /* Filter out flags not applicable to multifunction */
3809 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
3810
3811 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
3812#else
3813 return -ENODEV;
3814#endif
3815}
3816
Alex Williamsond99321b2014-02-03 14:27:46 -07003817/*
3818 * Many Intel PCH root ports do provide ACS-like features to disable peer
3819 * transactions and validate bus numbers in requests, but do not provide an
3820 * actual PCIe ACS capability. This is the list of device IDs known to fall
3821 * into that category as provided by Intel in Red Hat bugzilla 1037684.
3822 */
3823static const u16 pci_quirk_intel_pch_acs_ids[] = {
3824 /* Ibexpeak PCH */
3825 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
3826 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
3827 /* Cougarpoint PCH */
3828 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
3829 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
3830 /* Pantherpoint PCH */
3831 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
3832 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
3833 /* Lynxpoint-H PCH */
3834 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
3835 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
3836 /* Lynxpoint-LP PCH */
3837 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
3838 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
3839 /* Wildcat PCH */
3840 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
3841 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
Alex Williamson1a30fd02014-03-31 12:21:38 -06003842 /* Patsburg (X79) PCH */
3843 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
Alex Williamson78e88352015-01-22 11:15:43 -07003844 /* Wellsburg (X99) PCH */
3845 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
3846 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
Alex Williamsondca230d2015-05-01 13:20:13 -06003847 /* Lynx Point (9 series) PCH */
3848 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
Alex Williamsond99321b2014-02-03 14:27:46 -07003849};
3850
3851static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
3852{
3853 int i;
3854
3855 /* Filter out a few obvious non-matches first */
3856 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
3857 return false;
3858
3859 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
3860 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
3861 return true;
3862
3863 return false;
3864}
3865
3866#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
3867
3868static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
3869{
3870 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
3871 INTEL_PCH_ACS_FLAGS : 0;
3872
3873 if (!pci_quirk_intel_pch_acs_match(dev))
3874 return -ENOTTY;
3875
3876 return acs_flags & ~flags ? 0 : 1;
3877}
3878
Alex Williamson100ebb22014-09-26 17:07:59 -06003879static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
Alex Williamson89b51cb2014-09-17 08:59:36 -06003880{
3881 /*
3882 * SV, TB, and UF are not relevant to multifunction endpoints.
3883 *
Alex Williamson100ebb22014-09-26 17:07:59 -06003884 * Multifunction devices are only required to implement RR, CR, and DT
3885 * in their ACS capability if they support peer-to-peer transactions.
3886 * Devices matching this quirk have been verified by the vendor to not
3887 * perform peer-to-peer with other functions, allowing us to mask out
3888 * these bits as if they were unimplemented in the ACS capability.
Alex Williamson89b51cb2014-09-17 08:59:36 -06003889 */
3890 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
3891 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
3892
3893 return acs_flags ? 0 : 1;
3894}
3895
Alex Williamsonad805752012-06-11 05:27:07 +00003896static const struct pci_dev_acs_enabled {
3897 u16 vendor;
3898 u16 device;
3899 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3900} pci_dev_acs_enabled[] = {
Alex Williamson15b100d2013-06-27 16:40:00 -06003901 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
3902 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
3903 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
3904 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
3905 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
3906 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
Marti Raudsepp3587e622014-10-02 08:50:31 -06003907 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
3908 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
Alex Williamson100ebb22014-09-26 17:07:59 -06003909 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
3910 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
3911 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
3912 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
3913 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
3914 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
3915 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
3916 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
3917 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
3918 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
3919 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
3920 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
3921 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
3922 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
3923 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
3924 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
3925 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
3926 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
3927 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
3928 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
3929 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
3930 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
Alex Williamsond7488042015-03-20 12:27:57 -06003931 /* 82580 */
3932 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
3933 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
3934 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
3935 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
3936 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
3937 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
3938 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
3939 /* 82576 */
3940 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
3941 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
3942 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
3943 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
3944 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
3945 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
3946 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
3947 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
3948 /* 82575 */
3949 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
3950 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
3951 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
3952 /* I350 */
3953 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
3954 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
3955 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
3956 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
3957 /* 82571 (Quads omitted due to non-ACS switch) */
3958 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
3959 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
3960 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
3961 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
Alex Williamson95e16582015-08-10 12:32:04 -06003962 /* I219 */
3963 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
3964 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
Alex Williamsond7488042015-03-20 12:27:57 -06003965 /* Intel PCH root ports */
Alex Williamsond99321b2014-02-03 14:27:46 -07003966 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
Vasundhara Volam6a3763d2015-01-13 01:22:23 -05003967 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
3968 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
Alex Williamsonad805752012-06-11 05:27:07 +00003969 { 0 }
3970};
3971
3972int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
3973{
3974 const struct pci_dev_acs_enabled *i;
3975 int ret;
3976
3977 /*
3978 * Allow devices that do not expose standard PCIe ACS capabilities
3979 * or control to indicate their support here. Multi-function express
3980 * devices which do not allow internal peer-to-peer between functions,
3981 * but do not implement PCIe ACS may wish to return true here.
3982 */
3983 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
3984 if ((i->vendor == dev->vendor ||
3985 i->vendor == (u16)PCI_ANY_ID) &&
3986 (i->device == dev->device ||
3987 i->device == (u16)PCI_ANY_ID)) {
3988 ret = i->acs_enabled(dev, acs_flags);
3989 if (ret >= 0)
3990 return ret;
3991 }
3992 }
3993
3994 return -ENOTTY;
3995}
Alex Williamson2c744242014-02-03 14:27:33 -07003996
Alex Williamsond99321b2014-02-03 14:27:46 -07003997/* Config space offset of Root Complex Base Address register */
3998#define INTEL_LPC_RCBA_REG 0xf0
3999/* 31:14 RCBA address */
4000#define INTEL_LPC_RCBA_MASK 0xffffc000
4001/* RCBA Enable */
4002#define INTEL_LPC_RCBA_ENABLE (1 << 0)
4003
4004/* Backbone Scratch Pad Register */
4005#define INTEL_BSPR_REG 0x1104
4006/* Backbone Peer Non-Posted Disable */
4007#define INTEL_BSPR_REG_BPNPD (1 << 8)
4008/* Backbone Peer Posted Disable */
4009#define INTEL_BSPR_REG_BPPD (1 << 9)
4010
4011/* Upstream Peer Decode Configuration Register */
4012#define INTEL_UPDCR_REG 0x1114
4013/* 5:0 Peer Decode Enable bits */
4014#define INTEL_UPDCR_REG_MASK 0x3f
4015
4016static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4017{
4018 u32 rcba, bspr, updcr;
4019 void __iomem *rcba_mem;
4020
4021 /*
4022 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4023 * are D28:F* and therefore get probed before LPC, thus we can't
4024 * use pci_get_slot/pci_read_config_dword here.
4025 */
4026 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4027 INTEL_LPC_RCBA_REG, &rcba);
4028 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4029 return -EINVAL;
4030
4031 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4032 PAGE_ALIGN(INTEL_UPDCR_REG));
4033 if (!rcba_mem)
4034 return -ENOMEM;
4035
4036 /*
4037 * The BSPR can disallow peer cycles, but it's set by soft strap and
4038 * therefore read-only. If both posted and non-posted peer cycles are
4039 * disallowed, we're ok. If either are allowed, then we need to use
4040 * the UPDCR to disable peer decodes for each port. This provides the
4041 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4042 */
4043 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4044 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4045 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4046 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4047 if (updcr & INTEL_UPDCR_REG_MASK) {
4048 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
4049 updcr &= ~INTEL_UPDCR_REG_MASK;
4050 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4051 }
4052 }
4053
4054 iounmap(rcba_mem);
4055 return 0;
4056}
4057
4058/* Miscellaneous Port Configuration register */
4059#define INTEL_MPC_REG 0xd8
4060/* MPC: Invalid Receive Bus Number Check Enable */
4061#define INTEL_MPC_REG_IRBNCE (1 << 26)
4062
4063static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4064{
4065 u32 mpc;
4066
4067 /*
4068 * When enabled, the IRBNCE bit of the MPC register enables the
4069 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4070 * ensures that requester IDs fall within the bus number range
4071 * of the bridge. Enable if not already.
4072 */
4073 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4074 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4075 dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
4076 mpc |= INTEL_MPC_REG_IRBNCE;
4077 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4078 }
4079}
4080
4081static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4082{
4083 if (!pci_quirk_intel_pch_acs_match(dev))
4084 return -ENOTTY;
4085
4086 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4087 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
4088 return 0;
4089 }
4090
4091 pci_quirk_enable_intel_rp_mpc_acs(dev);
4092
4093 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4094
4095 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
4096
4097 return 0;
4098}
4099
Alex Williamson2c744242014-02-03 14:27:33 -07004100static const struct pci_dev_enable_acs {
4101 u16 vendor;
4102 u16 device;
4103 int (*enable_acs)(struct pci_dev *dev);
4104} pci_dev_enable_acs[] = {
Alex Williamsond99321b2014-02-03 14:27:46 -07004105 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
Alex Williamson2c744242014-02-03 14:27:33 -07004106 { 0 }
4107};
4108
4109void pci_dev_specific_enable_acs(struct pci_dev *dev)
4110{
4111 const struct pci_dev_enable_acs *i;
4112 int ret;
4113
4114 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4115 if ((i->vendor == dev->vendor ||
4116 i->vendor == (u16)PCI_ANY_ID) &&
4117 (i->device == dev->device ||
4118 i->device == (u16)PCI_ANY_ID)) {
4119 ret = i->enable_acs(dev);
4120 if (ret >= 0)
4121 return;
4122 }
4123 }
4124}
Tadeusz Struk3388a612015-08-07 11:34:42 -07004125
4126/*
4127 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with
4128 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4129 * Next Capability pointer in the MSI Capability Structure should point to
4130 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4131 * the list.
4132 */
4133static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4134{
4135 int pos, i = 0;
4136 u8 next_cap;
4137 u16 reg16, *cap;
4138 struct pci_cap_saved_state *state;
4139
4140 /* Bail if the hardware bug is fixed */
4141 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4142 return;
4143
4144 /* Bail if MSI Capability Structure is not found for some reason */
4145 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4146 if (!pos)
4147 return;
4148
4149 /*
4150 * Bail if Next Capability pointer in the MSI Capability Structure
4151 * is not the expected incorrect 0x00.
4152 */
4153 pci_read_config_byte(pdev, pos + 1, &next_cap);
4154 if (next_cap)
4155 return;
4156
4157 /*
4158 * PCIe Capability Structure is expected to be at 0x50 and should
4159 * terminate the list (Next Capability pointer is 0x00). Verify
4160 * Capability Id and Next Capability pointer is as expected.
4161 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4162 * to correctly set kernel data structures which have already been
4163 * set incorrectly due to the hardware bug.
4164 */
4165 pos = 0x50;
4166 pci_read_config_word(pdev, pos, &reg16);
4167 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4168 u32 status;
4169#ifndef PCI_EXP_SAVE_REGS
4170#define PCI_EXP_SAVE_REGS 7
4171#endif
4172 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4173
4174 pdev->pcie_cap = pos;
4175 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
4176 pdev->pcie_flags_reg = reg16;
4177 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
4178 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4179
4180 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4181 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4182 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4183 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4184
4185 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4186 return;
4187
4188 /*
4189 * Save PCIE cap
4190 */
4191 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4192 if (!state)
4193 return;
4194
4195 state->cap.cap_nr = PCI_CAP_ID_EXP;
4196 state->cap.cap_extended = 0;
4197 state->cap.size = size;
4198 cap = (u16 *)&state->cap.data[0];
4199 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4200 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4201 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4202 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4203 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4204 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4205 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4206 hlist_add_head(&state->next, &pdev->saved_cap_space);
4207 }
4208}
4209DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);