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gerrit-public.fairphone.software / kernel / msm-4.9 / efb45b305fff1fe08bbd1e16591de71e7963cc58 / . / arch / arm / boot / dts / tegra30-cardhu.dtsi
blob: 20637954624425795453cc78699e674276de5430 [file] [log] [blame]
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]1#include "tegra30.dtsi"
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]2
Laxman Dewangan640a7af2012-08-09 16:30:38 +0530[diff] [blame]3/**
4 * This file contains common DT entry for all fab version of Cardhu.
5 * There is multiple fab version of Cardhu starting from A01 to A07.
6 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
7 * A02 will have different sets of GPIOs for fixed regulator compare to
8 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
9 * compatible with fab version A04. Based on Cardhu fab version, the
10 * related dts file need to be chosen like for Cardhu fab version A02,
11 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
12 * tegra30-cardhu-a04.dts.
13 * The identification of board is done in two ways, by looking the sticker
14 * on PCB and by reading board id eeprom.
15 * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
16 * number is the fab version like here it is 002 and hence fab version A02.
17 * The (downstream internal) U-Boot of Cardhu display the board-id as
18 * follows:
19 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
20 * In this Fab version is 02 i.e. A02.
21 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
22 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
23 * wide.
24 */
25
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]26/ {
27 model = "NVIDIA Tegra30 Cardhu evaluation board";
28 compatible = "nvidia,cardhu", "nvidia,tegra30";
29
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]30 aliases {
Stephen Warren763fbff2014-02-13 17:18:26 -0700[diff] [blame]31 rtc0 = "/i2c@7000d000/tps65911@2d";
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]32 rtc1 = "/rtc@7000e000";
33 };
34
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]35 memory {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]36 reg = <0x80000000 0x40000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]37 };
38
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]39 pcie-controller@00003000 {
Jay Agarwal89e7ada2013-08-09 16:49:27 +0200[diff] [blame]40 status = "okay";
Thierry Redingcca86142014-05-28 16:49:12 +0200[diff] [blame]41
42 /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
43 avdd-pexb-supply = <&ldo1_reg>;
44 vdd-pexb-supply = <&ldo1_reg>;
45 avdd-pex-pll-supply = <&ldo1_reg>;
46 hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
47 vddio-pex-ctl-supply = <&sys_3v3_reg>;
48 avdd-plle-supply = <&ldo2_reg>;
49
Jay Agarwal89e7ada2013-08-09 16:49:27 +0200[diff] [blame]50 pci@1,0 {
51 nvidia,num-lanes = <4>;
52 };
53
54 pci@2,0 {
55 nvidia,num-lanes = <1>;
56 };
57
58 pci@3,0 {
59 status = "okay";
60 nvidia,num-lanes = <1>;
61 };
62 };
63
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]64 host1x@50000000 {
65 dc@54200000 {
66 rgb {
67 status = "okay";
68
69 nvidia,panel = <&panel>;
70 };
71 };
72 };
73
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]74 pinmux@70000868 {
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]75 pinctrl-names = "default";
76 pinctrl-0 = <&state_default>;
77
78 state_default: pinmux {
79 sdmmc1_clk_pz0 {
80 nvidia,pins = "sdmmc1_clk_pz0";
81 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]82 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
83 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]84 };
85 sdmmc1_cmd_pz1 {
86 nvidia,pins = "sdmmc1_cmd_pz1",
87 "sdmmc1_dat0_py7",
88 "sdmmc1_dat1_py6",
89 "sdmmc1_dat2_py5",
90 "sdmmc1_dat3_py4";
91 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]92 nvidia,pull = <TEGRA_PIN_PULL_UP>;
93 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]94 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]95 sdmmc3_clk_pa6 {
96 nvidia,pins = "sdmmc3_clk_pa6";
97 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]98 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
99 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]100 };
101 sdmmc3_cmd_pa7 {
102 nvidia,pins = "sdmmc3_cmd_pa7",
103 "sdmmc3_dat0_pb7",
104 "sdmmc3_dat1_pb6",
105 "sdmmc3_dat2_pb5",
106 "sdmmc3_dat3_pb4";
107 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]108 nvidia,pull = <TEGRA_PIN_PULL_UP>;
109 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]110 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]111 sdmmc4_clk_pcc4 {
112 nvidia,pins = "sdmmc4_clk_pcc4",
113 "sdmmc4_rst_n_pcc3";
114 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]115 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
116 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]117 };
118 sdmmc4_dat0_paa0 {
119 nvidia,pins = "sdmmc4_dat0_paa0",
120 "sdmmc4_dat1_paa1",
121 "sdmmc4_dat2_paa2",
122 "sdmmc4_dat3_paa3",
123 "sdmmc4_dat4_paa4",
124 "sdmmc4_dat5_paa5",
125 "sdmmc4_dat6_paa6",
126 "sdmmc4_dat7_paa7";
127 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]128 nvidia,pull = <TEGRA_PIN_PULL_UP>;
129 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]130 };
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]131 dap2_fs_pa2 {
132 nvidia,pins = "dap2_fs_pa2",
133 "dap2_sclk_pa3",
134 "dap2_din_pa4",
135 "dap2_dout_pa5";
136 nvidia,function = "i2s1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]137 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
138 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]139 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]140 sdio3 {
141 nvidia,pins = "drive_sdio3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]142 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
143 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]144 nvidia,pull-down-strength = <46>;
145 nvidia,pull-up-strength = <42>;
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]146 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
147 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]148 };
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]149 uart3_txd_pw6 {
150 nvidia,pins = "uart3_txd_pw6",
151 "uart3_cts_n_pa1",
152 "uart3_rts_n_pc0",
153 "uart3_rxd_pw7";
154 nvidia,function = "uartc";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]155 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
156 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]157 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]158 };
159 };
160
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]161 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]162 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]163 };
164
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]165 serial@70006200 {
166 compatible = "nvidia,tegra30-hsuart";
167 status = "okay";
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]168 };
169
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]170 pwm@7000a000 {
171 status = "okay";
172 };
173
174 panelddc: i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]175 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]176 clock-frequency = <100000>;
177 };
178
179 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]180 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]181 clock-frequency = <100000>;
182 };
183
184 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]185 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]186 clock-frequency = <100000>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]187
188 /* ALS and Proximity sensor */
189 isl29028@44 {
190 compatible = "isil,isl29028";
191 reg = <0x44>;
192 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]193 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]194 };
Bryan Wu40431d12014-02-07 15:54:58 -0800[diff] [blame]195
196 i2cmux@70 {
197 compatible = "nxp,pca9546";
198 #address-cells = <1>;
199 #size-cells = <0>;
200 reg = <0x70>;
201 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]202 };
203
204 i2c@7000c700 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]205 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]206 clock-frequency = <100000>;
207 };
208
209 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]210 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]211 clock-frequency = <100000>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]212
213 wm8903: wm8903@1a {
214 compatible = "wlf,wm8903";
215 reg = <0x1a>;
216 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]217 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]218
219 gpio-controller;
220 #gpio-cells = <2>;
221
222 micdet-cfg = <0>;
223 micdet-delay = <100>;
224 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
225 };
Laxman Dewangan331da582012-05-10 20:38:45 +0000[diff] [blame]226
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]227 pmic: tps65911@2d {
228 compatible = "ti,tps65911";
229 reg = <0x2d>;
230
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]231 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]232 #interrupt-cells = <2>;
233 interrupt-controller;
234
Stephen Warren44b12ef2012-09-11 11:42:26 -0600[diff] [blame]235 ti,system-power-controller;
236
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]237 #gpio-cells = <2>;
238 gpio-controller;
239
240 vcc1-supply = <&vdd_ac_bat_reg>;
241 vcc2-supply = <&vdd_ac_bat_reg>;
242 vcc3-supply = <&vio_reg>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]243 vcc4-supply = <&vdd_5v0_reg>;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]244 vcc5-supply = <&vdd_ac_bat_reg>;
245 vcc6-supply = <&vdd2_reg>;
246 vcc7-supply = <&vdd_ac_bat_reg>;
247 vccio-supply = <&vdd_ac_bat_reg>;
248
249 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]250 vdd1_reg: vdd1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]251 regulator-name = "vddio_ddr_1v2";
252 regulator-min-microvolt = <1200000>;
253 regulator-max-microvolt = <1200000>;
254 regulator-always-on;
255 };
256
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]257 vdd2_reg: vdd2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]258 regulator-name = "vdd_1v5_gen";
259 regulator-min-microvolt = <1500000>;
260 regulator-max-microvolt = <1500000>;
261 regulator-always-on;
262 };
263
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]264 vddctrl_reg: vddctrl {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]265 regulator-name = "vdd_cpu,vdd_sys";
266 regulator-min-microvolt = <1000000>;
267 regulator-max-microvolt = <1000000>;
268 regulator-always-on;
269 };
270
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]271 vio_reg: vio {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]272 regulator-name = "vdd_1v8_gen";
273 regulator-min-microvolt = <1800000>;
274 regulator-max-microvolt = <1800000>;
275 regulator-always-on;
276 };
277
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]278 ldo1_reg: ldo1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]279 regulator-name = "vdd_pexa,vdd_pexb";
280 regulator-min-microvolt = <1050000>;
281 regulator-max-microvolt = <1050000>;
282 };
283
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]284 ldo2_reg: ldo2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]285 regulator-name = "vdd_sata,avdd_plle";
286 regulator-min-microvolt = <1050000>;
287 regulator-max-microvolt = <1050000>;
288 };
289
290 /* LDO3 is not connected to anything */
291
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]292 ldo4_reg: ldo4 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]293 regulator-name = "vdd_rtc";
294 regulator-min-microvolt = <1200000>;
295 regulator-max-microvolt = <1200000>;
296 regulator-always-on;
297 };
298
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]299 ldo5_reg: ldo5 {
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]300 regulator-name = "vddio_sdmmc,avdd_vdac";
301 regulator-min-microvolt = <3300000>;
302 regulator-max-microvolt = <3300000>;
303 regulator-always-on;
304 };
305
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]306 ldo6_reg: ldo6 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]307 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
308 regulator-min-microvolt = <1200000>;
309 regulator-max-microvolt = <1200000>;
310 };
311
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]312 ldo7_reg: ldo7 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]313 regulator-name = "vdd_pllm,x,u,a_p_c_s";
314 regulator-min-microvolt = <1200000>;
315 regulator-max-microvolt = <1200000>;
316 regulator-always-on;
317 };
318
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]319 ldo8_reg: ldo8 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]320 regulator-name = "vdd_ddr_hs";
321 regulator-min-microvolt = <1000000>;
322 regulator-max-microvolt = <1000000>;
323 regulator-always-on;
324 };
325 };
326 };
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]327
Wei Ni7c7de6b2013-10-07 17:28:29 +0800[diff] [blame]328 temperature-sensor@4c {
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]329 compatible = "onnn,nct1008";
330 reg = <0x4c>;
Wei Ni7c7de6b2013-10-07 17:28:29 +0800[diff] [blame]331 vcc-supply = <&sys_3v3_reg>;
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]332 interrupt-parent = <&gpio>;
333 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
334 };
Stephen Warren2b8584d2013-07-15 10:33:53 -0600[diff] [blame]335
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]336 tps62361@60 {
Stephen Warren2b8584d2013-07-15 10:33:53 -0600[diff] [blame]337 compatible = "ti,tps62361";
338 reg = <0x60>;
339
340 regulator-name = "tps62361-vout";
341 regulator-min-microvolt = <500000>;
342 regulator-max-microvolt = <1500000>;
343 regulator-boot-on;
344 regulator-always-on;
345 ti,vsel0-state-high;
346 ti,vsel1-state-high;
347 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]348 };
Stephen Warren850c4c82012-02-01 16:29:57 -0700[diff] [blame]349
Laxman Dewanganc42cb1c2012-10-31 14:32:54 +0530[diff] [blame]350 spi@7000da00 {
351 status = "okay";
352 spi-max-frequency = <25000000>;
353 spi-flash@1 {
354 compatible = "winbond,w25q32";
355 reg = <1>;
356 spi-max-frequency = <20000000>;
357 };
358 };
359
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]360 pmc@7000e400 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]361 status = "okay";
362 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800[diff] [blame]363 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800[diff] [blame]364 nvidia,cpu-pwr-good-time = <2000>;
365 nvidia,cpu-pwr-off-time = <200>;
366 nvidia,core-pwr-good-time = <3845 3845>;
367 nvidia,core-pwr-off-time = <0>;
368 nvidia,core-power-req-active-high;
369 nvidia,sys-clock-req-active-high;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]370 };
371
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]372 ahub@70080000 {
373 i2s@70080400 {
374 status = "okay";
375 };
376 };
377
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]378 sdhci@78000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]379 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]380 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
381 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
382 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]383 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]384 };
385
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]386 sdhci@78000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]387 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]388 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600[diff] [blame]389 non-removable;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]390 };
391
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300[diff] [blame]392 usb@7d008000 {
393 status = "okay";
394 };
395
396 usb-phy@7d008000 {
397 vbus-supply = <&usb3_vbus_reg>;
398 status = "okay";
399 };
400
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]401 backlight: backlight {
402 compatible = "pwm-backlight";
403
404 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
405 power-supply = <&vdd_bl_reg>;
406 pwms = <&pwm 0 5000000>;
407
408 brightness-levels = <0 4 8 16 32 64 128 255>;
409 default-brightness-level = <6>;
410 };
411
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]412 clocks {
413 compatible = "simple-bus";
414 #address-cells = <1>;
415 #size-cells = <0>;
416
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]417 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]418 compatible = "fixed-clock";
419 reg=<0>;
420 #clock-cells = <0>;
421 clock-frequency = <32768>;
422 };
423 };
424
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]425 panel: panel {
426 compatible = "chunghwa,claa101wb01", "simple-panel";
427 ddc-i2c-bus = <&panelddc>;
428
429 power-supply = <&vdd_pnl1_reg>;
430 enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
431
432 backlight = <&backlight>;
433 };
434
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]435 regulators {
436 compatible = "simple-bus";
437 #address-cells = <1>;
438 #size-cells = <0>;
439
440 vdd_ac_bat_reg: regulator@0 {
441 compatible = "regulator-fixed";
442 reg = <0>;
443 regulator-name = "vdd_ac_bat";
444 regulator-min-microvolt = <5000000>;
445 regulator-max-microvolt = <5000000>;
446 regulator-always-on;
447 };
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]448
449 cam_1v8_reg: regulator@1 {
450 compatible = "regulator-fixed";
451 reg = <1>;
452 regulator-name = "cam_1v8";
453 regulator-min-microvolt = <1800000>;
454 regulator-max-microvolt = <1800000>;
455 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]456 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]457 vin-supply = <&vio_reg>;
458 };
459
460 cp_5v_reg: regulator@2 {
461 compatible = "regulator-fixed";
462 reg = <2>;
463 regulator-name = "cp_5v";
464 regulator-min-microvolt = <5000000>;
465 regulator-max-microvolt = <5000000>;
466 regulator-boot-on;
467 regulator-always-on;
468 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]469 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]470 };
471
472 emmc_3v3_reg: regulator@3 {
473 compatible = "regulator-fixed";
474 reg = <3>;
475 regulator-name = "emmc_3v3";
476 regulator-min-microvolt = <3300000>;
477 regulator-max-microvolt = <3300000>;
478 regulator-always-on;
479 regulator-boot-on;
480 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]481 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]482 vin-supply = <&sys_3v3_reg>;
483 };
484
485 modem_3v3_reg: regulator@4 {
486 compatible = "regulator-fixed";
487 reg = <4>;
488 regulator-name = "modem_3v3";
489 regulator-min-microvolt = <3300000>;
490 regulator-max-microvolt = <3300000>;
491 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]492 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]493 };
494
495 pex_hvdd_3v3_reg: regulator@5 {
496 compatible = "regulator-fixed";
497 reg = <5>;
498 regulator-name = "pex_hvdd_3v3";
499 regulator-min-microvolt = <3300000>;
500 regulator-max-microvolt = <3300000>;
501 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]502 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]503 vin-supply = <&sys_3v3_reg>;
504 };
505
506 vdd_cam1_ldo_reg: regulator@6 {
507 compatible = "regulator-fixed";
508 reg = <6>;
509 regulator-name = "vdd_cam1_ldo";
510 regulator-min-microvolt = <2800000>;
511 regulator-max-microvolt = <2800000>;
512 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]513 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]514 vin-supply = <&sys_3v3_reg>;
515 };
516
517 vdd_cam2_ldo_reg: regulator@7 {
518 compatible = "regulator-fixed";
519 reg = <7>;
520 regulator-name = "vdd_cam2_ldo";
521 regulator-min-microvolt = <2800000>;
522 regulator-max-microvolt = <2800000>;
523 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]524 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]525 vin-supply = <&sys_3v3_reg>;
526 };
527
528 vdd_cam3_ldo_reg: regulator@8 {
529 compatible = "regulator-fixed";
530 reg = <8>;
531 regulator-name = "vdd_cam3_ldo";
532 regulator-min-microvolt = <3300000>;
533 regulator-max-microvolt = <3300000>;
534 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]535 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]536 vin-supply = <&sys_3v3_reg>;
537 };
538
539 vdd_com_reg: regulator@9 {
540 compatible = "regulator-fixed";
541 reg = <9>;
542 regulator-name = "vdd_com";
543 regulator-min-microvolt = <3300000>;
544 regulator-max-microvolt = <3300000>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]545 regulator-always-on;
546 regulator-boot-on;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]547 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]548 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]549 vin-supply = <&sys_3v3_reg>;
550 };
551
552 vdd_fuse_3v3_reg: regulator@10 {
553 compatible = "regulator-fixed";
554 reg = <10>;
555 regulator-name = "vdd_fuse_3v3";
556 regulator-min-microvolt = <3300000>;
557 regulator-max-microvolt = <3300000>;
558 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]559 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]560 vin-supply = <&sys_3v3_reg>;
561 };
562
563 vdd_pnl1_reg: regulator@11 {
564 compatible = "regulator-fixed";
565 reg = <11>;
566 regulator-name = "vdd_pnl1";
567 regulator-min-microvolt = <3300000>;
568 regulator-max-microvolt = <3300000>;
569 regulator-always-on;
570 regulator-boot-on;
571 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]572 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]573 vin-supply = <&sys_3v3_reg>;
574 };
575
576 vdd_vid_reg: regulator@12 {
577 compatible = "regulator-fixed";
578 reg = <12>;
579 regulator-name = "vddio_vid";
580 regulator-min-microvolt = <5000000>;
581 regulator-max-microvolt = <5000000>;
582 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]583 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]584 gpio-open-drain;
585 vin-supply = <&vdd_5v0_reg>;
586 };
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]587 };
588
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]589 sound {
590 compatible = "nvidia,tegra-audio-wm8903-cardhu",
591 "nvidia,tegra-audio-wm8903";
592 nvidia,model = "NVIDIA Tegra Cardhu";
593
594 nvidia,audio-routing =
595 "Headphone Jack", "HPOUTR",
596 "Headphone Jack", "HPOUTL",
597 "Int Spk", "ROP",
598 "Int Spk", "RON",
599 "Int Spk", "LOP",
600 "Int Spk", "LON",
601 "Mic Jack", "MICBIAS",
602 "IN1L", "Mic Jack";
603
604 nvidia,i2s-controller = <&tegra_i2s1>;
605 nvidia,audio-codec = <&wm8903>;
606
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]607 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
608 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
609 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]610
Hiroshi Doyu05849c92013-05-22 19:45:34 +0300[diff] [blame]611 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
612 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
613 <&tegra_car TEGRA30_CLK_EXTERN1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]614 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]615 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]616};